E28F004B5-B80_技术文档

ADVANCE INFORMATION

E

SMART 5 BOOT BLOCK

FLASH MEMORY FAMILY

2, 4, 8 MBIT

28F200B5, 28F400B5, 28F800B5, 28F004B5

SmartVoltage Technology

Extended Block Erase Cycling

100,000 Cycles at Commercial Temp

10,000 Cycles at Extended Temp

Smart 5 Flash: 5 V Reads,

5 V or 12 V Writes

Increased Programming Throughput

at 12 V V_PP

Hardware Data Protection Feature

Absolute Hardware-Protection for

Boot Block

Very High-Performance Read

2-, 4-Mbit: 60 ns Access Time

8-Mbit: 70 ns Access Time

Write Lockout during Power

Transitions

x8 or x8/x16-Configurable Data Bus

Automated Word/Byte Program and

Block Erase

Low Power Consumption

Max 60 mA Read Current at 5 V

Auto Power Savings: <1 mA Typical

Standby Current

Command User Interface

Status Registers

Erase Suspend Capability

SRAM-Compatible Write Interface

Optimized Array Blocking Architecture

16-KB Protected Boot Block

Reset/Deep Power-Down Input

Provides Low-Power Mode and

Reset for Boot Operations

Two 8-KB Parameter Blocks

96-KB and 128-KB Main Blocks

Top or Bottom Boot Locations

Pinout Compatible 2, 4, and 8 Mbit

Extended Temperature Operation

ETOX™ Flash Technology

–40 °C to +85 °C

0.6 µ ETOX IV Initial Production

0.4 µ ETOX V Later Production

Industry-Standard Packaging

40, 48-Lead TSOP, 44-Lead PSOP

Intel’s Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring high-density,

low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetrically-

blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for

embedded code execution applications, such as networking infrastructure and office automation.

Based on Intel’s boot block architecture, the Smart 5 boot block memory family enables quick and easy

upgrades for designs that demand state-of-the-art technology. This family of products comes in industry-

standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for

board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP.

December 1997

Order Number: 290599-004

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F200B5, 28F400/004B5, 28F800B5 may contain design defects or errors known are errata. Current characterized errata

are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call 1-800-548-4725

or visit Intel’s website at http://www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners.

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SMART 5 BOOT BLOCK MEMORY FAMILY

CONTENTS

PAGE

1.0 INTRODUCTION .............................................5

4.0 DESIGN CONSIDERATIONS........................24

4.1 Power Consumption...................................24

4.1.1 Active Power .......................................24

4.1.2 Automatic Power Savings (APS) .........24

4.1.3 Standby Power ....................................25

4.1.4 Deep Power-Down Mode.....................25

4.2 Power-Up/Down Operation.........................25

4.2.1 RP# Connected to System Reset ........25

4.3 Board Design .............................................25

4.3.1 Power Supply Decoupling....................25

1.1 New Features in the Smart 5 Memory

Products......................................................5

1.2 Product Overview.........................................5

2.0 PRODUCT DESCRIPTION..............................6

2.1 Pin Descriptions ...........................................6

2.2 Pinouts.........................................................8

2.3 Memory Blocking Organization...................10

2.3.1 One 16-KB Boot Block.........................10

2.3.2 Two 8-KB Parameter Blocks................10

4.3.2 V

Trace on Printed Circuit Boards...25

PP

2.3.3 Main Blocks - One 96-KB + Additional

128-KB Blocks....................................10

5.0 ELECTRICAL SPECIFICATIONS..................26

5.1 Absolute Maximum Ratings........................26

5.2 Operating Conditions..................................26

5.3 Capacitance ...............................................27

3.0 PRINCIPLES OF OPERATION .....................13

3.1 Bus Operations ..........................................13

3.1.1 Read....................................................13

3.1.2 Output Disable.....................................14

3.1.3 Standby...............................................14

3.1.4 Word/Byte Configuration......................14

3.1.5 Deep Power-Down/Reset ....................14

3.1.6 Write....................................................14

3.2 Modes of Operation....................................16

3.2.1 Read Array..........................................16

3.2.2 Read Identifier.....................................16

3.2.3 Read Status Register ..........................16

3.2.4 Word/Byte Program.............................17

3.2.5 Block Erase.........................................17

3.3 Boot Block Locking ....................................23

3.3.1 V_PP= V_ILfor Complete Protection .......24

3.3.2 WP# = V_ILfor Boot Block Locking .......24

5.4 DC Characteristics—Commercial and

Extended Temperature..............................27

5.5 AC Characteristics—Read Operations—

Commercial and Extended Temperature ...31

5.6 Erase and Program Timings—Commercial

and Extended Temperature.......................32

5.7 AC Characteristics—Write Operations—

Commercial and Extended Temperature ...33

6.0 ORDERING INFORMATION..........................35

7.0 ADDITIONAL INFORMATION.......................36

APPENDIX A: Write State Machine: Current-

Next State Chart ..........................................37

APPENDIX B: Product Block Diagram..............38

3.3.3 RP# = V_HHor WP# = V_IHfor Boot Block

Unlocking ...........................................24

3.3.4 Note for 8-Mbit 44-PSOP Package......24

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REVISION HISTORY

Number

-001

Description

Original Version

-002

Minor changes throughout document.

Section 3.1.5 and Figure 14 redone to clarify program/erase operation abort.

Information added to Table 2, Figure 1, and Section 3.3 to clarify WP# on 8-Mbit,

44-PSOP.

Read and Write Waveforms changed to numbered format.

Typical numbers removed from DC Characteristics and Erase/Program Timings.

-003

-004

Minor text changes throughout document.

Figure 1, 44-PSOP pinout: mistake on pin 3 on 2-Mbit pinout corrected from A₁₇to NC.

Specs t_EHQZand t_GHQZimproved.

Explanations of program/erase abort commands reworked in Table 6, Command

Codes.

Specifications for 28F004B5 40-TSOP version added; Erase suspend text and

flowchart updated for clarity (Section 3.2.5.1, Table 6, Figure 10)

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SMART 5 BOOT BLOCK MEMORY FAMILY

1.0 INTRODUCTION

•

A delay is required if the part is reset during an

in-progress program or erase operation.

This datasheet contains specifications for 2-, 4-,

and 8-Mbit Smart 5 boot block flash memories.

Section 1.0 provides a feature overview. Sections

2.0, 3.0, and 4.0 describe the product and

functionality. Section 5.0 details the electrical and

timing specifications for both commercial and

extended temperature operation. Finally, Sections

6.0 and 7.0 provide ordering and reference

information.

On the fly word-byte mode switching is no

longer supported. Word-byte mode must be

configured at power-up and remain stable

during operation.

•

Write operations are no longer specified as

WE#- or CE#-controlled in favor of a simpler

“unified” write method, which is compatible

with either of the old methods.

1.1

New Features in the

Smart 5 Memory Products

1.2

Product Overview

The Smart 5 boot block memory family provides

pinout-compatible flash memories at the

2-, 4-, and 8-Mbit densities. The 28F200B5,

28F400B5, and 28F800B5 can be configured to

operate either in 16-bit or 8-bit bus mode, with the

data divided into individually erasable blocks. The

28F004B5 provides 8-bit operation in a compact

package.

The Smart 5 boot block flash memory family offers

identical features with the BV/CV/BE/CE

SmartVoltage products, except the Smart 5 boot

block -B5 parts only support 5 V V_CCread voltage.

The following differences distinguish the Smart 5

boot block products from their predecessors:

Table 1. Smart 5 Boot Block Family: Feature Summary

Feature

V_CCRead Voltage

V_PPProg/Erase Voltage

Bus-width

28F200B5

28F400B5

5 V ± 5%, 5 V ± 10%

5 V ± 10% or 12 V ± 5%, auto-detected

28F800B5

28F004B5

Reference

Section 5.2

Table 2

8- or 16-bit

80

8- or 16-bit

70, 90

8-bit

Speed (ns) Commercial

Extended

60, 80

Section 5.6

80

90

not available Section 5.6

x8: 512K x 8

Memory Arrangement

x8: 256K x 8

x8: 512K x 8

x8: 1M x 8

x16: 128K x 16 x16: 256K x 16 x16: 512K x 16

Blocking

Boot

1 x 16 KB

2 x 8 KB

1 x 16 KB

2 x 8 KB

1 x 16 KB

2 x 8 KB

1 x 16 KB

2 x 8 KB

Section 2.3,

Figs. 4-7

Parameter

Main

1 x 96 KB

1 x 128 KB

3 x 128 KB

7 x 128 KB

3 x 128 KB

Boot Location

Locking

Top or Bottom boot locations available

Boot Block lockable using WP# and/or RP#

All other blocks protectable using V_PPswitch

Section 3.3

Section 5.2

Operating Temperature

Erase Cycling

Commercial: 0 °C – +70 °C, Extended: -40 °C – +85 °C

100,000 cycles at Commercial, 10,000 cycles at Extended

Packages

44-PSOP, 48-TSOP

40-TSOP

Figs. 1-2

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SmartVoltage technology enables fast factory

programming and low-power designs. Specifically

designed for 5 V systems, Smart 5 components

support read operations at 5 V V_CCand internally

configure to program/erase at 5 V or 12 V. The 12 V

V_PPoption renders the fastest program and erase

performance which will increase your factory

throughput. With the 5 V V_PPoption, V_CCand V_PP

can be tied together for a simple 5 V design. In

addition, the dedicated V_PPpin gives complete data

When CE# and RP# pins are at V_CC, the

component enters a CMOS standby mode. Driving

RP# to GND enables a deep power-down mode

which significantly reduces power consumption,

provides write protection, resets the device, and

clears the status register. A reset time (t_PHQV) is

required from RP# switching high until outputs are

valid. Likewise, the device has a wake time (t_PHEL

)

from RP#-high until writes to the CUI are

recognized. See Section 4.2.

protection when V_PP≤ V_PPLK

.

The deep power-down mode can also be used as a

device reset, allowing the flash to be reset along

with the rest of the system. For example, when the

flash memory powers-up, it automatically defaults

to the read array mode, but during a warm system

reset, where power continues uninterrupted to the

system components, the flash memory could

The memory array is asymmetrically divided into

blocks in an asymmetrical architecture to

accommodate microprocessors that boot from the

top (denoted by -T suffix) or the bottom (-B suffix)

of the memory map. The blocks include

a

hardware-lockable boot block (16,384 bytes), two

parameter blocks (8,192 bytes each) and main

blocks (one block of 98,304 bytes and additional

block(s) of 131,072 bytes). See Figures 4–7 for

memory maps. Each block can be independently

erased and programmed 100,000 times at

commercial temperature or 10,000 times at

extended temperature. Unlike erase operations,

remain in

a non-read mode, such as erase.

Consequently, the system Reset signal should be

tied to RP# to reset the memory to normal read

mode upon activation of the Reset signal. This also

provides protection against unwanted command

writes due to invalid system bus conditions during

system reset or power-up/down sequences.

which erase all locations within

a

block

simultaneously, each byte or word in the flash

memory can be programmed independently of other

memory locations.

These devices are configurable at power-up for

either byte-wide or word-wide input/output using the

BYTE# pin. Please see Table 2 for a detailed

description of BYTE# operations, especially the

usage of the DQ₁₅/A_–1pin.

The hardware-lockable boot block provides

complete code security for the kernel code required

for system initialization. Locking and unlocking of

the boot block is controlled by WP# and/or RP#

(see Section 3.3 for details).

These Smart 5 memory products are available in

the 44-lead PSOP (Plastic Small Outline Package),

which is ROM/EPROM-compatible, and the 48-lead

TSOP (Thin Small Outline Package, 1.2 mm thick)

as shown in Figure 1, and 2, respectively.

The system processor interfaces to the flash device

through a Command User Interface (CUI), using

valid command sequences to initiate device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for program and erase operations. The

Status Register (SR) indicates the status of the

WSM and whether it successfully completed the

desired program or erase operation.

2.0 PRODUCT DESCRIPTION

This section describes the pinout and block

architecture of the device family.

2.1

Pin Descriptions

The Automatic Power Savings (APS) feature

substantially reduces active current when the

device is in static mode (addresses not switching).

In APS mode, the typical I_CCRcurrent is 1 mA.

The pin descriptions table details the usage of each

of the device pins.

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Table 2. Pin Descriptions

Symbol

Type

Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally latched

during a write cycle.

A₀–A₁₈

INPUT

28F200: A[0–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]

A₉

INPUT

ADDRESS INPUT: When A₉is at V_HHthe signature mode is accessed. During

this mode, A₀decodes between the manufacturer and device IDs. When BYTE#

is at a logic low, only the lower byte of the signatures are read. DQ₁₅/A_–1is a

don’t care in the signature mode when BYTE# is low.

DQ₀–DQ₇

INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle

OUTPUT during a Program command. Inputs commands to the Command User Interface

when CE# and WE# are active. Data is internally latched during the write cycle.

Outputs array, intelligent identifier and status register data. The data pins float to

tri-state when the chip is de-selected or the outputs are disabled.

DQ₈–DQ₁₅

INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle

OUTPUT during a Program command. Data is internally latched during the write cycle.

Outputs array data. The data pins float to tri-state when the chip is de-selected or

the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide

mode DQ₁₅/A_–1becomes the lowest order address for data output on DQ₀–DQ₇.

Not applicable to 28F004B5.

CE#

INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE# is active low. CE# high de-selects the memory device and

reduces power consumption to standby levels. If CE# and RP# are high, but not

at a CMOS high level, the standby current will increase due to current flow

through the CE# and RP# input stages.

OE#

WE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data buffers during

a read cycle. OE# is active low.

WRITE ENABLE: Controls writes to the command register and array blocks. WE#

is active low. Addresses and data are latched on the rising edge of the WE#

pulse.

RP#

INPUT

RESET/DEEP POWER-DOWN: Uses three voltage levels (V_IL, V_IH, and V_HH) to

control two different functions: reset/deep power-down mode and boot block

unlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,

which puts the outputs at High-Z, resets the Write State Machine, and draws

minimum current.

When RP# is at logic high, the device is in standard operation. When RP#

transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V_HH, the boot block is unlocked and can be programmed or

erased. This overrides any control from the WP# input.

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Table 2. Pin Descriptions (Continued)

Name and Function

Symbol

WP#

Type

INPUT

WRITE PROTECT: Provides a method for unlocking the boot block with a logic

level signal in a system without a 12 V supply.

When WP# is at logic low, the boot block is locked, preventing program and

erase operations to the boot block. If a program or erase operation is attempted

on the boot block when WP# is low, the corresponding status bit (bit 4 for

program, bit 5 for erase) will be set in the status register to indicate the operation

failed.

When WP# is at logic high, the boot block is unlocked and can be

programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at

V

_HH. This pin can not be left floating. Because the 8-Mbit 44-PSOP package does

not have enough pins, it does not include this pin and thus 12 V on RP# is

required to unlock the boot block. See Section 3.3 for details on write protection.

BYTE#

INPUT

BYTE# ENABLE: Configures whether the device operates in byte-wide mode (x8)

or word-wide mode (x16). This pin must be set at power-up or return from deep

power-down and not changed during device operation. BYTE# pin must be

controlled at CMOS levels to meet the CMOS current specification in standby

mode.

When BYTE# is at logic low, the byte-wide mode is enabled, where data is

read and programmed on DQ₀–DQ₇and DQ₁₅/A_–1becomes the lowest order

address that decodes between the upper and lower byte. DQ₈–DQ₁₄are tri-stated

during the byte-wide mode.

When BYTE# is at logic high, the word-wide mode is enabled, where data is

read and programmed on DQ₀–DQ₁₅

.

Not applicable to 28F004B5.

V_CC

V_PP

DEVICE POWER SUPPLY: 5.0 V ± 10%

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or

programming data in each block, a voltage either of 5 V ± 10% or 12 V ± 5% must

be applied to this pin. When V_PP< V_PPLKall blocks are locked and protected

against Program and Erase commands.

GND

NC

GROUND: For all internal circuitry.

NO CONNECT: Pin may be driven or left floating.

Pinouts for the corresponding 2-, 4-, and 8-Mbit

components are provided on the same diagram for

2.2

Pinouts

convenient reference. 2-Mbit pinouts are given on

the chip illustration in the center, with 4-Mbit and

8-Mbit pinouts going outward from the center.

Intel’s Smart 5 boot block architecture provides

upgrade paths in each package pinout up to the

8-Mbit density. The 44-lead PSOP pinout follows

the industry-standard ROM/EPROM pinout, as

shown in Figure 1. Designs with space concerns

should consider the 48-lead pinout shown in

Figure 2. Applications using an 8-bit bus can use

the 40-lead TSOP, which is available for the 4-Mbit

device only.

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SMART 5 BOOT BLOCK MEMORY FAMILY

28F400

RP#

WE#

A₈

28F800

RP#

WE#

A₈

V_PP

A ₁₈

A₁₇

A ₇

A ₆

A ₅

A ₄

A ₃

A ₂

A ₁

V_PP

WP#

A₁₇

A ₇

A ₆

A ₅

A ₄

A ₃

A ₂

V_PP

WP#

NC

A ₇

A ₆

A ₅

1

2

3

4

44

43

42

41

RP#

WE#

A₈

A₉

5

6

7

8

9

40

39

38

37

36

35

A ₁₀

A₁₁

A ₁₂

A₁₃

A ₁₄

A ₁₅

A₁₆

BYTE#

GND

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₆

DQ ₁₃

DQ ₅

A ₁₀

A₁₁

A₁₂

A₁₃

A ₁₄

A ₁₅

A ₁₆

BYTE#

GND

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₆

DQ ₁₃

DQ ₅

A₁₀

A₁₁

A₁₂

A₁₃

A₁₄

A₁₅

A₁₆

BYTE#

GND

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₆

DQ ₁₃

DQ ₅

PA28F200

Boot Block

44-Lead PSOP

0.525" x 1.110"

A ₄

A ₃

A ₂

A ₁

10

A ₁

TOP VIEW

A ₀

CE#

GND

OE#

11

12

13

14

15

16

17

18

19

20

21

22

34

33

32

31

30

29

28

27

26

25

24

23

CE#

GND

OE#

CE#

GND

OE#

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

DQ ₁₂

DQ ₄

V_CC

DQ ₁₂

DQ ₄

V_CC

DQ ₁₂

DQ ₄

V_CC

0599-01

NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A₁₈on the 8-Mbit because no other pins were available for the high order

address. Thus, the 8-Mbit in 44-PSOP cannot unlock the boot block without RP# = V_HH. See Section 3.3 for details. To allow

upgrades to 8-Mbit from 2/4-Mbit in this package design pin 2 to control WP# at the 2/4-Mbit level and A₁₈at the 8-Mbit density.

Figure 1. 44-Lead PSOP Pinout Diagram

28F800 28F400

28F400

28F800

A

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

A₉

A₈

NC

WE#

RP#

V_PP

A₁₅

A₁₄

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

A₉

A₈

NC

WE#

RP#

V_PP

WP#

NC

A₇

A₆

A₅

A₄

A₃

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

16

BYTE#

GND

DQ

BYTE#

GND

DQ

BYTE#

GND

/A

DQ

-1

15

A

13

12

11

A

/A

-1

15

7

14

6

13

5

12

4

15

7

14

6

13

5

12

4

DQ

V

DQ

V

DQ

V

7

14

6

13

5

A₁₀

A₉

A₈

NC

WE#

RP#

V_PP

WP#

NC

28F200

Boot Block

48-Lead TSOP

12 mm x 20 mm

12

4

CC

DQ

11

3

10

2

9

1

11

3

10

2

9

1

11

3

10

2

9

1

WP#

NC

A₁₈

DQ

TOP VIEW

DQ

OE#

GND

CE#

A₁₇

A₇

A₆

A₅

A₄

A₃

A₇

A₆

A₅

A₄

A₃

8

0

8

0

8

0

OE#

GND

CE#

OE#

GND

CE#

A

A₁

A

A₁

A

A₁

2

A

0

0599-02

Figure 2. 48-Lead TSOP Pinout Diagram

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A

17

GND

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

16

15

14

13

12

11

NC

A

10

7

DQ

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A

DQ

6

9

8

28F004B5

Boot Block

40-Lead TSOP

10mmx20mm

DQ

5

WE#

RP#

DQ

V

4

CC

V

PP

CC

NC

DQ

WP#

A

18

3

2

1

0

TOP VIEW

A

7

A

6

A

5

A

OE#

GND

CE#

4

A

3

A

2

A

1

0

Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only)

2.3.2 TWO 8-KB PARAMETER BLOCKS

2.3

Memory Blocking Organization

Each boot block component contains two parameter

blocks of 8 Kbytes (8,192 bytes) each to facilitate

storage of frequently updated small parameters that

would normally require an EEPROM. By using

software techniques, the byte-rewrite functionality

of EEPROMs can be emulated. These techniques

are detailed in Intel’s application note, AP-604

Using Intel’s Boot Block Flash Memory Parameter

Blocks to Replace EEPROM. The parameter blocks

are not write-protectable.

The boot block product family features an

asymmetrically-blocked architecture providing

system memory integration. Each erase block can

be erased independently of the others up to

100,000 times for commercial temperature or up to

10,000 times for extended temperature. The block

sizes have been chosen to optimize their

functionality for common applications of nonvolatile

storage. The combination of block sizes in the boot

block architecture allow the integration of several

memories into a single chip. For the address

locations of the blocks, see the memory maps in

Figures 4, 5, 6 and 7.

2.3.3

MAIN BLOCKS - ONE 96-KB +

ADDITIONAL 128-KB BLOCKS

After the allocation of address space to the boot

and parameter blocks, the remainder is divided into

main blocks for data or code storage. Each device

contains one 96-Kbyte (98,304 byte) block and

additional 128-Kbyte (131,072 byte) blocks. The

2-Mbit has one 128-KB block; the 4-Mbit, three; and

the 8-Mbit, seven.

2.3.1

ONE 16-KB BOOT BLOCK

The boot block is intended to replace a dedicated

boot PROM in a microprocessor or microcontroller-

based system. The 16-Kbyte (16,384 bytes) boot

block is located at either the top (denoted by -T

suffix) or the bottom (-B suffix) of the address map

to accommodate different microprocessor protocols

for boot code location. This boot block features

hardware controllable write-protection to protect the

crucial microprocessor boot code from accidental

modification. The protection of the boot block is

controlled using a combination of the V_PP, RP#, and

WP# pins, as is detailed in Section 3.3.

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28F200-T

28F400-T

28F800-T

7FFFFH

3FFFFH

1FFFFH

16-Kbyte BOOT BLOCK

7E000H

7DFFFH

7D000H

7CFFFH

7C000H

7BFFFH

3E000H

3DFFFH

1E000H

1DFFFH

1D000H

1CFFFH

1C000H

1BFFFH

8-Kbyte PARAMETER BLOCK

3D000H

3CFFFH

3C000H

3BFFFH

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

70000H

6FFFFH

30000H

2FFFFH

10000H

0FFFFH

128-Kbyte MAIN BLOCK

60000H

5FFFFH

20000H

1FFFFH

00000H

128-Kbyte MAIN BLOCK

50000H

4FFFFH

10000H

0FFFFH

40000H

3FFFFH

00000H

30000H

2FFFFH

20000H

1FFFFH

10000H

0FFFFH

00000H

0599-03

NOTE: Word addresses shown.

Figure 4. Word-Wide x16-Mode Memory Maps (Top Boot)

7FFFFH

128-Kbyte MAIN BLOCK

70000H

6FFFFH

60000H

5FFFFH

50000H

4FFFFH

40000H

3FFFFH

128-Kbyte MAIN BLOCK

30000H

2FFFFH

30000H

2FFFFH

20000H

1FFFFH

20000H

1FFFFH

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

10000H

0FFFFH

10000H

0FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

00000H

28F200-B

28F400-B

28F800-B

0599-04

NOTE: Word addresses shown.

Figure 5. Word-Wide x16-Mode Memory Maps (Bottom Boot)

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28F200-T

E

28F400-T

28F800-T

FFFFFH

7FFFFH

3FFFFH

16-Kbyte BOOT BLOCK

FC000H

FBFFFH

FA000H

F9FFFH

F8000H

F7FFFH

7C000H

7BFFFH

7A000H

79FFFH

78000H

77FFFH

3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

E0000H

DFFFFH

60000H

5FFFFH

20000H

1FFFFH

128-Kbyte MAIN BLOCK

C0000H

BFFFFH

40000H

3FFFFH

00000H

128-Kbyte MAIN BLOCK

A0000H

9FFFFH

20000H

1FFFFH

80000H

7FFFFH

00000H

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

Byte-Mode Addresses

00000H

0599-05

NOTE: In x8 operation, the least significant system address should be connected to A .

-1

Figure 6. Byte-Wide x8-Mode Memory Maps (Top Boot)

FFFFFH

Byte-Mode Addresses

128-Kbyte MAIN BLOCK

E0000H

DFFFFH

C0000H

BFFFFH

A0000H

9FFFFH

80000H

7FFFFH

128-Kbyte MAIN BLOCK

60000H

5FFFFH

60000H

5FFFFH

40000H

3FFFFH

40000H

3FFFFH

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

20000H

1FFFFH

20000H

1FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

00000H

28F200-B

28F400-B

28F800-B

0599-06

NOTE: In x8 operation, the least significant system address should be connected to A .

-1

Figure 7. Byte-Wide x8-Mode Memory Maps (Bottom Boot)

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operation has completed, the device remains in

read status register mode. From this mode any of

the other read or write modes can be reached with

the appropriate command. For example, to read

data, issue the Read Array command. Additional

Program or Erase commands can also be issued

from this state.

3.0 PRINCIPLES OF OPERATION

The system processor accesses the Smart 5 boot

block memories through the Command User

Interface (CUI), which accepts commands written

with standard microprocessor write timings and

TTL-level control inputs. The flash can be switched

into each of its three read and two write modes

During program or erase operations, the array data

is not available for reading or code execution,

except during an erase suspend. Consequently, the

software that initiates and polls progress of program

and erase operations must be copied to and

executed from system RAM during flash memory

update. After successful completion, reads are

again possible via the Read Array command.

through commands issued to the CUI.

comprehensive chart showing the state transitions

is in Appendix A.

A

After initial device power-up or return from deep

power-down mode, the device defaults to read

array mode. In this mode, manipulation of the

memory control pins allows array read, standby,

and output disable operations. The other read

modes, read identifier and read status register, can

be reached by issuing the appropriate command to

the CUI. Array data, identifier codes and status

register results can be accessed using these

commands independently from the V_PPvoltage.

Read identifier mode can also be accessed by

PROM programming equipment by raising A₉to

high voltage (V_ID).

Each of the device modes will be discussed in

detail in the following sections.

3.1

Bus Operations

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

Four control pins dictate the data flow in and out of

the component: CE#, OE#, WE#, and RP#. These

bus operations are summarized in Tables 3 and 4.

CUI commands sequences also control the write

functions of the flash memory, Program and Erase.

Issuing program or erase command sequences

internally latches addresses and data and initiates

Write State Machine (WSM) operations to execute

the requested write function. The WSM internally

regulates the program and erase algorithms,

including pulse repetition, internal verification, and

margining of data, freeing the host processor from

these tasks and allowing precise control for high

reliability. To execute Program or Erase

commands, V_PPmust be at valid write voltage (5 V

or 12 V).

3.1.1

READ

The flash memory has three read modes available,

read array, read identifier, and read status. These

read modes are accessible independent of the V_PP

voltage. RP# can be at either V_IHor V_HH. The

appropriate read-mode command must be issued to

the CUI to enter the corresponding mode. Upon

initial device power-up or after exit from deep

power-down mode, the device automatically

defaults to read array mode.

While the WSM is executing a program operation,

the device defaults to the read status register mode

and all commands are ignored. Thus during the

programming process, only status register data can

be accessed from the device. While the WSM is

CE# and OE# must be driven active to obtain data

at the outputs. CE# is the device selection control,

and, when active, enables the selected memory

device. OE# is the data output (DQ₀–DQ₁₅) control

and when active drives the selected memory data

onto the I/O bus. In read modes, WE# must be at

V_IHand RP# must be at V_IHor V_HH. Figure 15

illustrates a read cycle.

executing

a erase operation, the device also

defaults to the read status register mode but one

additional command is available, erase suspend to

read, which will suspend the erase operation and

allow reading of array data. The suspended erase

operation can be completed by issuing the Erase

Resume command. After the program or erase

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3.1.2 OUTPUT DISABLE

E

operation is restored. The CUI resets to read array

mode, and the status register is set to 80H. This

case is shown in Figure 14A.

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins (if available on

the device) DQ₀–DQ₁₅are placed in

a high-

If RP# is taken low for time t_PLPHduring a program

or erase operation, the operation will be aborted

and the memory contents at the aborted location

(for a program) or block (for an erase) are no longer

valid, since the data may be partially erased or

written. The abort process goes through the

following sequence: When RP# goes low, the

device shuts down the operation in progress, a

process which takes time t_PLRHto complete. After

this time t_PLRH, the part will either reset to read

impedance state.

3.1.3

STANDBY

Deselecting the device by bringing CE# to a logic-

high level (V_IH) places the device in standby mode

which substantially reduces device power

consumption. In standby, outputs DQ₀–DQ₁₅are

placed in a high-impedance state independent of

OE#. If deselected during program or erase

operation, the device continues functioning and

consuming active power until the operation

completes.

array mode (if RP# has gone high during t_PLRH

,

Figure 14B) or enter deep power-down mode (if

RP# is still logic low after t_PLRH, Figure 14C). In

both cases, after returning from an aborted

operation, the relevant time t_PHQVor t_PHWL/t_PHEL

must be waited before a read or write operation is

initiated, as discussed in the previous paragraph.

However, in this case, these delays are referenced

to the end of t_PLRHrather than when RP# goes high.

3.1.4

WORD/BYTE CONFIGURATION

The 16-bit devices can be configured for either an

8-bit or 16-bit bus width by setting the BYTE# pin

before power-up. This is not applicable to the 8-bit

only E28F004B5.

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, processor expects to read from

the flash memory. Automated flash memories

provide status information when read during

program or block erase operations. If a CPU reset

occurs with no flash memory reset, proper CPU

initialization may not occur because the flash

memory may be providing status information

instead of array data. Intel’s Flash memories allow

proper CPU initialization following a system reset

through the use of the RP# input. In this application,

RP# is controlled by the same RESET# signal that

resets the system CPU.

When BYTE# is set to logic low, the byte-wide

mode is enabled, where data is read and

programmed on DQ₀–DQ₇and DQ₁₅/A_–1becomes

the lowest order address that decodes between the

upper and lower byte. DQ₈–DQ₁₄are tri-stated

during the byte-wide mode.

When BYTE# is at logic high, the word-wide mode

is enabled, and data is read and programmed on

DQ₀–DQ₁₅

.

3.1.5

DEEP POWER-DOWN/RESET

3.1.6

WRITE

RP# at V_ILinitiates the deep power-down mode,

also referred to as reset mode.

The CUI does not occupy an addressable memory

location. Instead, commands are written into the

CUI using standard microprocessor write timings

when WE# and CE# are low, OE# = V_IH, and the

proper address and data (command) are presented.

The address and data for a command are latched

on the rising edge of WE# or CE#, whichever goes

high first. Figure 16 illustrates a write operation.

From read mode, RP# going low for time t_PLPH

deselects the memory, places output drivers in a

high-impedance state, and turns off all internal

circuits. After return from power-down, a time t_PHQV

is required until the initial memory access outputs

are valid. A delay (t_PHWLor t_PHEL) is required after

return from power-down before a write can be

initiated. After this wake-up interval, normal

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Table 3. Bus Operations for Word-Wide Mode (BYTE# = V_IH)

Mode

Read

Notes

RP#

V_IH

V_IL

CE#

V_IL

V_IH

X

OE#

V_IL

V_IH

X

WE#

V_IH

X

A₉

X

A₀

X

V_PP

X

DQ_0–15

D_OUT

1,2,3

Output Disable

X

High Z

0089 H

Standby

X

Deep Power-Down

9

4

X

Intelligent Identifier

(Mfr.)

V_IH

V_IL

V_IH

V_ID

V_IL

X

Intelligent Identifier

(Device)

4,5

V_IH

V_IL

V_IH

V_IL

V_ID

X

V_IH

X

See

Table 4

Write

6,7,8

D_IN

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = V_IL)

(10)

Mode

Read

Note RP#

CE#

V_IL

OE# WE#

A₉

X

A₀

X

A_–1

X

V_PP

X

DQ_0–7

D_OUT

DQ_8–14

High Z

1,2,3

V_IH

V_IL

V_IH

Output

V_IL

X

High Z

Disable

Standby

V_IH

V_IL

V_IH

X

High Z

Deep

Power-

Down

9

4

Intelligent

Identifier

(Mfr.)

V_IH

V_IL

V_IH

V_IL

V_ID

X

V_IL

V_IH

X

89H

High Z

Intelligent

Identifier

(Device)

4,5

See

Table 4

Write

6,7,8

D_IN

NOTES:

1. Refer to DC Characteristics.

2. X can be V_IL, V_IHfor control pins and addresses, V_PPLKor V_PPHfor V_PP

.

3. See DC Characteristics for V_PPLK, V_PPH1, V_PPH2, V_HH, V_IDvoltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A selects, all other addresses = X.

0

5. See Table 4 for device IDs.

6. Refer to Table 6 for valid D_INduring a write operation.

7. Command writes for block erase or program are only executed when V_PP= V_PPH1or V_PPH2

8. To program or erase the boot block, hold RP# at V_HHor WP# at V_IH. See Section 3.3.

9. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

10. This column does not apply to the E28F004B5 since it is a x8-only device.

.

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3.2.2

READ IDENTIFIER

3.2

Modes of Operation

To read the manufacturer and device codes, the

device must be in intelligent identifier read mode,

which can be reached using two methods: by

writing the intelligent identifier command (90H) or

by taking the A₉pin to V_ID. Once in intelligent

The flash memory has three read modes and two

write modes. The read modes are read array, read

identifier, and read status. The write modes are

program and block erase. An additional mode,

erase suspend to read, is available only during

block erasures. These modes are reached using

identifier read mode, A₀

=

0

outputs the

manufacturer’s identification code and A₀

=

1

the commands summarized in Table 5.

A

outputs the device code. In byte-wide mode, only

the lower byte of the above signatures is read

(DQ₁₅/A_–1is a “don’t care” in this mode). See

Table 4 for product signatures. To return to read

array mode, write a Read Array command (FFH).

comprehensive chart showing the state transitions

is in Appendix A.

3.2.1

READ ARRAY

After initial device power-up or return from deep

power-down mode, the device defaults to read

array mode. This mode can also be entered by

writing the Read Array command (FFH). The device

remains in this mode until another command is

written.

3.2.3

READ STATUS REGISTER

The status register indicates when a program or

erase operation is complete, and the success or

failure of that operation. The status register is

output when the device is read in read status

register mode, which can be entered by issuing the

Read Status (70H) command to the CUI. This mode

is automatically entered when a program or erase

operation is initiated, and the device remains in this

mode after the operation has completed. Status

register bit codes are defined in Table 7.

Data is read by presenting the address of the read

location in conjunction with a read bus operation.

Once the WSM has started a program or block

erase operation, the device will not recognize the

Read Array command until the WSM completes its

operation unless the WSM is suspended via an

Erase Suspend command. The Read Array

command functions independently of the V_PP

The status register bits are output on DQ₀–DQ₇, in

both byte-wide (x8) or word-wide (x16) mode. In the

word-wide mode, the upper byte, DQ₈–DQ₁₅

outputs 00H during a Read Status command. In the

byte-wide mode, DQ₈–DQ₁₄are tri-stated and

DQ₁₅/A_–1retains the low order address function.

,

voltage and RP# can be V_IHor V_HH

.

During system design, consideration should be

taken to ensure address and control inputs meet

required input slew rates of <10 ns as defined in

Figures 11 and 12.

Note that the contents of the status register are

latched on the falling edge of OE# or CE#,

whichever occurs last in the read cycle. This

prevents possible bus errors which might occur if

status register contents change while being read.

CE# or OE# must be toggled with each subsequent

status read, or the status register will not indicate

completion of a program or erase operation.

Table 4. Intelligent Identifier Codes

Product Mfr. ID

Device ID

-T

-B

Top Boot Bottom Boot

28F004

28F200

28F400

28F800

89H

78H

79H

Issue a Read Array (FFH) command to return to

read array.

0089 H

2274 H

4470 H

889C H

2275 H

4471 H

889D H

3.2.3.1

Clearing the Status Register

NOTE:

In byte-mode, the upper byte will be tri-stated.

Status register bits SR.5, SR.4, and SR.3 are set to

“1”s when appropriate by the WSM but can only be

reset by the Clear Status Register command.

These bits indicate various failure conditions (see

Table 7). By requiring system software to reset

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these bits, several operations (such as cumulatively

erasing multiple blocks or programming several

bytes in sequence) may be performed before

polling the status register to determine if an error

occurred during the series.

“0,” erase all bits to “1,” and verify that all bits in the

block are sufficiently erased. After block erase

command sequence is issued, the device

automatically enters read status register mode and

outputs status register data when read (see

Figure 9). The completion of the erase event is

indicated on status register bit SR.7.

Issue the Clear Status Register command (50H) to

clear the status register. It functions independently

of the applied V_PPvoltage and RP# can be V_IHor

When an erase is complete, check status register

bit SR.5 for an error flag (“1”). The cause of a failure

may be found on SR.3, which indicates “1” if V_PP

was out of program/erase voltage range (V_PPH1or

V

_HH. This command is not functional during block

erase suspend modes. Resetting the part with RP#

also clears the status register.

V

_PPH2). If an Erase Set-Up (20H) command is

issued but not followed by an Erase Confirm (D0H)

command, then both the program status (SR.4) and

the erase status (SR.5) will be set to “1.”

3.2.4

WORD/BYTE PROGRAM

Word or byte program operations are executed by a

two-cycle command sequence. Program Set-Up

(40H) is issued, followed by a second write that

specifies the address and data (latched on the

rising edge of WE# or CE#, whichever comes first).

The WSM then takes over, controlling the program

and program verify algorithms internally. While the

WSM is working, the device automatically enters

read status register mode and remains there after

the word/byte program is complete. (see Figure 8).

The completion of the program event is indicated on

status register bit SR.7.

The status register should be cleared before the

next operation. Since the device remains in status

register read mode after erasing is completed, a

command must be issued to switch to another

mode before beginning a different operation.

3.2.5.1

Erase Suspend/Resume

The Erase Suspend command (B0H) interrupts an

erase operation in order to read data in another

block of memory. While the erase is in progress,

issuing the Erase Suspend command requests that

the WSM suspend the erase algorithm after a

certain latency period. After issuing the Erase

Suspend command, write the Read Status Register

command, then check bit SR.7 and SR.6 to ensure

the device is in the erase suspend mode (both will

be set to “1”). This check is necessary because the

WSM may have completed the erase operation

before the Erase Suspend command was issued. If

this occurs, the Erase Suspend command would

switch the device into read array mode. See

Appendix A for a comprehensive chart showing the

state transitions.

When a word/byte program is complete, check

status register bit SR.4 for an error flag (“1”). The

cause of a failure may be found on SR.3, which

indicates “1” if V_PPwas out of program/erase

voltage range (V_PPH1or V_PPH2). The status register

should be cleared before the next operation. The

internal WSM verify only detects errors for “1”s that

do not successfully write to “0”s.

Since the device remains in status register read

mode after programming is completed, a command

must be issued to switch to another mode before

beginning a different operation.

When erase has been suspended, a Read Array

command (FFH) can be written to read from blocks

other than that which is suspended. The only other

valid commands at this time are Erase Resume

(D0H) or Read Status Register.

3.2.5

BLOCK ERASE

A

block erase changes all block data to 1’s

(FFFFH) and is initiated by a two-cycle command.

An Erase Set-Up command (20H) is issued first,

followed by an Erase Confirm command (D0H)

along with an address within the target block. The

address will be latched at the rising edge of WE# or

CE#, whichever comes first.

During erase suspend mode, the chip can go into a

pseudo-standby mode by taking CE# to V_IH, which

reduces active current draw. V_PPmust remain at

V_PPH1or V_PPH2(the same V_PPlevel used for block

erase) while erase is suspended. RP# must also

remain at V_IHor V_HH(the same RP# level used for

block erase).

Internally, the WSM will program all bits in the block

to “0,” verify all bits are adequately programmed to

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E

To resume the erase operation, enable the chip by

taking CE# to V_IL, then issue the Erase Resume

command, which continues the erase sequence to

completion. As with the end of a standard erase

operation, the status register must be read, cleared,

and the next instruction issued in order to continue.

Table 5. Command Codes and Descriptions

Code Device Mode

Description

00

FF

40

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine

these codes for future functions.

Read Array Places the device in read array mode, so that array data will be output on the data

pins.

Program

Set-Up

Sets the CUI into a state such that the next write will load the Address and Data

registers. The next write after the Program Set-Up command will latch addresses

and data on the rising edge and begin the program algorithm. The device then

defaults to the read status mode, where the device outputs status register data

when OE# is enabled. To read the array, issue a Read Array command.

To cancel a program operation after issuing a Program Set-Up command, write all

1’s (FFH for x8, FFFFH for x16) to the CUI. This will return to read status register

mode after a standard program time without modifying array contents. If a program

operation has already been initiated to the WSM this command cannot cancel that

operation in progress.

10

20

Alternate

Prog Set-Up

(See 40H/Program Set-Up)

Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an

Erase Confirm command, then the CUI will set both the program status (SR.4) and

erase status (SR.5) bits of the status register to a “1,” place the device into the

read status register state, and wait for another command without modifying array

contents. This can be used to cancel an erase operation after the Erase Set-Up

command has been issued. If an operation has already been initiated to the WSM

this can not cancel that operation in progress.

D0

B0

Erase

Resume/

Erase

If the previous command was an Erase Set-Up command, then the CUI will latch

address and data, and begin erasing the block indicated on the address pins.

During erase, the device will respond only to the Read Status Register and Erase

Suspend commands and will output status register data when OE# is toggled low.

Status register data is updated by toggling either OE# or CE# low.

Confirm

Erase

Suspend

Issuing this command will begin to suspend erase operation. The status register

will indicate when the device reaches erase suspend mode. In this mode, the CUI

will respond only to the Read Array, Read Status Register, and Erase Resume

commands and the WSM will also set the WSM status bit to a “1” (ready). The

WSM will continue to idle in the SUSPEND state, regardless of the state of all input

control pins except RP#, which will immediately shut down the WSM and the

remainder of the chip, if it is made active. During a suspend operation, the data

and address latches will remain closed, but the address pads are able to drive the

address into the read path. See Section 3.2.5.1. This command is useful only while

an erase operation is in progress and may reset to read array mode in other

circumstances. (See Appendix A for state transition table.)

70

Read Status Puts the device into the read status register mode, so that reading the device

Register

outputs status register data, regardless of the address presented to the device.

The device automatically enters this mode after program or erase has completed.

This is one of the two commands that is executable while the WSM is operating.

See Section 3.2.3.

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SMART 5 BOOT BLOCK MEMORY FAMILY

Table 5. Command Codes and Descriptions (Continued)

Description

Code Device Mode

50

Clear Status The WSM can only set the program status and erase status bits in the status

Register

register to “1”; it cannot clear them to “0.”

The status register operates in this fashion for two reasons. The first is to give the

host CPU the flexibility to read the status bits at any time. Second, when

programming a string of bytes, a single status register query after programming the

string may be more efficient, since it will return the accumulated error status of the

entire string. See Section 3.2.3.1.

90

Intelligent

Identifier

Puts the device into the intelligent identifier read mode, so that reading the device

will output the manufacturer and device codes. (A₀= 0 for manufacturer,

A₀= 1 for device, all other address inputs are ignored). See Section 3.2.2.

Table 6. Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Note

Oper

Write

Addr

X

Data

Oper

Addr

Data

Read Array

FFH

90H

Intelligent Identifier

Read Status Register

Clear Status Register

Word/Byte Program

Block Erase/Confirm

Erase Suspend

2,4

3

X

Read

IA

X

IID

X

70H

SRD

3

X

50H

6,7

5

PA

BA

X

40H/10H

20H

Write

PA

BA

PD

D0H

B0H

Erase Resume

X

D0H

ADDRESS

DATA

BA = Block Address

IA = Identifier Address

PA = Program Address

X = Don’t Care

SRD = Status Register Data

IID = Identifier Data

PD = Program Data

NOTES:

1. Bus operations are defined in Tables 3 and 4.

2. IA = Identifier Address: A₀= 0 for manufacturer code, A₀= 1 for device code.

3. SRD - Data read from Status Register.

4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and

device codes.

5. BA = Address within the block being erased.

6. PA = Address to be programmed. PD = Data to be programmed at location PA.

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus [DQ –DQ₁₅] = X which is either V_ILor V_IH, to minimize current

8

draw.

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E

Table 7. Status Register Bit Definition

WSMS

7

ESS

6

ES

5

DWS

4

VPPS

3

R

2

R

1

R

0

NOTES:

SR.7 WRITE STATE MACHINE STATUS

Check WSM bit first to determine word/byte

program or block erase completion, before

checking program or erase status bits.

1 = Ready

0 = Busy

(WSMS)

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

When Erase Suspend is issued, WSM halts

execution and sets both WSMS and ESS bits to

“1.” ESS bit remains set to “1” until an Erase

Resume command is issued.

0 = Erase In Progress/Completed

When this bit is set to “1,” one of the following has

occurred:

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure

0 = Successful Block Erase

1. V_PPout of range.

2. WSM has applied the max number of erase

pulses to the block and is still unable to verify

successful block erasure.

3. Erase Set-Up command was followed by a

command other than Erase Confirm.

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program

0 = Successful Byte/Word Program

When this bit is set to “1,” one of the following has

occurred:

1. V_PPout of range.

2. WSM has applied the max number of program

pulses and is still unable to verify a successful

program.

3. Erase Set-Up command was followed by a

command other than Erase Confirm.

SR.3 = V_PPSTATUS (VPPS)

1 = V_PPLow Detect, Operation Abort

0 = V_PPOK

The V_PPstatus bit does not provide continuous

indication of V_PPlevel. The WSM interrogates V_PP

level only after the Program or Erase command

sequences have been entered, and informs the

system if V_PPis out of range. The V_PPstatus bit is

not guaranteed to report accurate feedback

between V_PPLKand V_PPH

.

SR.2–SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and should

be masked out when polling the status register.

20

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Start

Bus

Operation

Command

Comments

Write

Setup

Program

Data = 40H

Addr = Word/Byte to Program

Write 40H,

Word/Byte Address

Program

Data = Data to Program

Addr = Location to Program

Write Word/Byte

Data/Address

Read

Status Register Data

Toggle CE# or OE#

to Update SRD.

Read

Status Register

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

NO

SR.7 = 1

?

Repeat for subsequent word/byte program operations.

SR Full Status Check can be done after each word/byte

program operation, or after a sequence of word/byte programs.

Write FFH after the last program operation to reset device to

read array mode.

YES

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Standby

Check SR.3

1 = V_PPLow Detect

1

SR.3 =

0

V_PPRange Error

Standby

Check SR.4

1 = Word Byte Program Error

1

Word/Byte Program

Error

SR.4 =

0

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command, in cases

where multiple bytes are programmed before full status is checked.

Word/Byte Program

Successful

If error is detected, clear the Status Register before attempting

retry or other error recovery.

0599-07

Figure 8. Automated Word/Byte Program Flowchart

21

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

Start

Bus

Operation

Command

Comments

Write

Erase Setup

Data = 20H

Addr = Within Block to be Erased

Write 20H,

Block Address

Erase

Data = D0H

Confirm

Addr = Within Block to be Erased

Write D0H and

Block Address

Read

Status Register Data

Toggle CE# or OE#

to Update Status Register

Read Status

Register

Suspend Erase

Loop

NO

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

0

YES

Suspend

SR.7 =

Erase

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase, or after a

sequence of block erasures.

1

Write FFH after the last operation to reset device to read array mode.

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Standby

Check SR.3

1 = VPP Low Detect

1

SR.3 =

0

V

PP

Range Error

Standby

Check SR.4,5

Both 1 = Command

Sequence Error

1

Command Sequence

Error

Check SR.5

1 = Block Erase Error

SR.4,5 =

0

SR.3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

Block Erase

Error

SR.5 =

0

SR.5 is only cleared by the Clear Status Register Command, in

cases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Block Erase

Successful

0599-08

Figure 9. Automated Block Erase Flowchart

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SMART 5 BOOT BLOCK MEMORY FAMILY

Bus

Operation

Command

Erase Suspend

Read Status

Comments

Data = B0H

Start

Write

Addr = X

Write B0H

Write 70H

Data = 70H

Addr = X

Write

Read

Status Register Data

Toggle OE# or CE# to Update

Status Register

Addr = X

Read Status

Register

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Check SR.6

1 = Erase Suspended

0 = Erase Completed

0

Standby

Write

SR.7 =

1

Data = FFH

Addr = X

Read Array

Read array data from block

other than the one being

programmed

0

SR.6 =

Erase Resumed

Read

1

Data = D0H

Addr = X

Write

Erase Resume

Write FFH

Read Array Data

No

Done Reading

Yes

Write D0H

Write FFH

Read Array Data

Erase Resumed

0599-09

Figure 10. Erase Suspend/Resume Flowchart

23

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

3.3 Boot Block Locking

E

functionality is required, and 12 V is not available

in-system, please consider using the 48-TSOP

package, which has

a

WP# pin and can be

The boot block family architecture features

a

unlocked with a logic-level signal. All other density-

package combinations have WP# pins.

hardware-lockable boot block so that the kernel

code for the system can be kept secure while the

parameter and main blocks are programmed and

erased independently as necessary. Only the boot

block can be locked independently from the other

blocks.

Table 8. Write Protection Truth Table

V_PP

RP# WP#

Write Protection

Provided

V_IL

X

All Blocks Locked

3.3.1

V

_PP= V_ILFOR COMPLETE

PROTECTION

≥ V_PPLK

V_IL

All Blocks Locked

(Reset)

For complete write protection of all blocks in the

device, the V_PPvoltage can be held low. When V_PP

is below V_PPLK, any program or erase operation will

result in a error in the status register.

≥ V_PPLKV_HH

X

All Blocks Unlocked

≥ V_PPLK

V_IH

V_ILBoot Block Locked

V_IHAll Blocks Unlocked

3.3.2

WP# = V_ILFOR BOOT BLOCK

LOCKING

4.0 DESIGN CONSIDERATIONS

When WP# = V_IL, the boot block is locked and any

program or erase operation to the boot block will

result in an error in the status register. All other

blocks remain unlocked in this condition and can be

programmed or erased normally. Note that this

feature is overridden and the boot block unlocked

The following section discusses recommended

design considerations which can improve the

robustness of system designs using flash memory.

when RP# = V_HH

.

4.1

Power Consumption

3.3.3

RP# = V_HHOR WP# = V_IHFOR BOOT

BLOCK UNLOCKING

Intel flash components contain features designed to

reduce power requirements. The following sections

will detail how to take advantage of these features.

Two methods can be used to unlock the boot block:

1. WP# = V_IH

4.1.1

ACTIVE POWER

2. RP# = V_HH

Asserting CE# to a logic-low level and RP# to a

logic-high level places the device in the active

mode. Refer to the DC Characteristics table for I_CCR

current values.

If both or either of these two conditions are met, the

boot block will be unlocked and can be

programmed or erased.

The Write Proctection Truth Table, Table 8, clearly

defines the write protection methods.

4.1.2

AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings (APS) provides low-

power operation in active mode. Power Reduction

Control (PRC) circuitry allows the device to put

itself into a low current state when not being

accessed. After data is read from the memory

array, PRC logic controls the device’s power

consumption by entering the APS mode where

typical I_CCcurrent is less than 1 mA. The device

stays in this static state with outputs valid until a

new location is read.

3.3.4

NOTE FOR 8-MBIT 44-PSOP

PACKAGE

The 8-Mbit in the 44-PSOP package does not have

a WP# because no other pins were available for the

8-Mbit upgrade address. Thus, in this density-

package combination only, V_HH(12 V) on RP# is

required to unlock the boot block and unlocking with

a logic-level signal is not possible. If this unlocking

24

ADVANCE INFORMATION

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SMART 5 BOOT BLOCK MEMORY FAMILY

4.1.3

STANDBY POWER

of the state of its control inputs. By holding the

device in reset (RP# connected to system

PowerGood) during power-up/down, invalid bus

conditions during power-up can be masked,

providing yet another level of memory protection.

When CE# is at a logic-high level (V_IH), and the

device is not programming or erasing, the memory

enters in standby mode, which disables much of the

device’s circuitry and substantially reduces power

consumption. Outputs (DQ₀–DQ₁₅or DQ₀–DQ₇) are

placed in a high-impedance state independent of

the status of the OE# signal. When CE# is at logic-

high level during program or erase operations, the

device will continue to perform the operation and

consume corresponding active power until the

operation is completed.

4.2.1

RP# CONNECTED TO SYSTEM

RESET

Using RP# properly during system reset is

important with automated program/erase devices

because the system expects to read from the flash

memory when it comes out of reset. If a CPU reset

occurs without a flash memory reset, proper CPU

initialization would not occur because the flash

memory may in a mode other than Read Array.

Intel’s Flash memories allow proper CPU

initialization following a system reset by connecting

the RP# pin to the same RESET# signal that resets

the system CPU.

4.1.4

DEEP POWER-DOWN MODE

The Smart 5 boot block family supports a low

typical I_CCDin deep power-down mode, which turns

off all circuits to save power. This mode is activated

by the RP# pin when it is at a logic-low (GND ±

0.2 V). Note: BYTE# pin must be at CMOS levels to

meet the I_CCDspecification.

4.3

Board Design

During read modes, the RP# pin going low de-

selects the memory and places the output drivers in

a high impedance state. Recovery from the deep

power-down state, requires a minimum access time

of t_PHQV. RP# transitions to V_IL, or turning power off

to the device will clear the status register.

4.3.1

POWER SUPPLY DECOUPLING

Flash memory’s switching characteristics require

careful decoupling methods. System designers

should consider three supply current issues:

standby current levels (I_CCS), active current levels

(I_CCR), and transient peaks produced by falling and

rising edges of CE#.

During an program or erase operation, RP# going

low for time t_PLPHwill abort the operation, but the

location’s memory contents will no longer valid and

additional timing must be met. See Section 3.1.5

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress these transient voltage peaks. Each

and

Figure 15 and Table 9 for additional

information.

flash device should have

a 0.1 µF ceramic

4.2

Power-Up/Down Operation

capacitor connected between V_CCand GND, and

between V_PPand GND. These high-frequency,

inherently low-inductance capacitors should be

placed as close as possible to the package leads.

The device protects against accidental block

erasure or programming during power transitions.

Power supply sequencing is not required, so either

V_PPor V_CCcan power-up first. The CUI defaults to

the read mode after power-up, but the system must

drop CE# low or present an address to receive valid

data at the outputs.

4.3.2

V

_PPTRACE ON PRINTED CIRCUIT

BOARDS

In-system updates to the flash memory requires

special consideration of the V_PPpower supply trace

by the printed circuit board designer. Since the V_PP

pin supplies the current for programming and

erasing, it should have similar trace widths and

layout considerations as given to the V_CCpower

supply trace. Adequate V_PPsupply traces, and

decoupling capacitors placed adjacent to the

component, will decrease spikes and overshoots.

A system designer must guard against spurious

writes when V_CCvoltages are above V_LKOand V_PP

is active. Since both WE# and CE# must be low for

a command write, driving either signal to V_IHwill

inhibit writes to the device. Additionally, alteration of

memory can only occur after successful completion

of a two-step command sequences. The device is

also disabled until RP# is brought to V_IH, regardless

25

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SMART 5 BOOT BLOCK MEMORY FAMILY

5.0 ELECTRICAL SPECIFICATIONS

E

* WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent damage. These

are stress ratings only. Operation beyond the "Operating

Conditions" is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

NOTICE: This document contains information on products in

the sampling and initial production phases of development.

The specifications are subject to change without notice.

Verify with your local Intel Sales office that you have the

latest datasheet before finalizing a design.

5.1

Absolute Maximum Ratings*

Commercial Operating Temperature

During Read/Erase/Program...... 0 °C to +70 °C

Temperature Under Bias ....... –10 °C to +80 °C

Extended Operating Temperature

During Read/Erase/Program.. –40 °C to +85 °C

Temperature Under Bias ....... –40 °C to +85 °C

Storage Temperature................. –65 °C to +125 °C

Voltage on Any Pin

1. Operating temperature is for commercial product

defined by this specification.

2. Minimum DC voltage is –0.5 V on input/output pins.

During transitions, this level may undershoot to–2.0 V

for periods

<20 ns. Maximum DC voltage on input/output pins is

(except V_CC, V_PP, A₉and RP#)

with Respect to GND........... –2.0 V to +7.0 V⁽²⁾

V

_CC+ 0.5 V which, during transitions, may overshoot to

_CC+ 2.0 V for periods <20 ns.

Voltage on Pin RP# or Pin A₉

3. Maximum DC voltage on V_PPmay overshoot to +14.0 V

for periods <20 ns. Maximum DC voltage on RP# or A₉

may overshoot to 13.5 V for periods <20 ns.

with Respect to GND....... –2.0 V to +13.5 V^(2,3)

V_PPProgram Voltage with Respect

to GND during Block Erase

4. Output shorted for no more than one second.No more

than one output shorted at a time.

and Word/Byte Program .. –2.0 V to +14.0 V^(2,3)

V_CCSupply Voltage

with Respect to GND........... –2.0 V to +7.0 V⁽²⁾

Output Short Circuit Current....................100 mA ⁽⁴⁾

5.2

Operating Conditions

Symbol

T_A

Parameter

Notes

Min

0

Max

+70

Units

°C

Commercial Operating Temperature

Extended Operating Temperature

5 V V_CCSupply Voltage (10%)

5 V V_CCSupply Voltage (5%)

5 V V_PPSupply Voltage (10%)

12 V V_CCSupply Voltage (5%)

-40

+85

°C

V_CC

1

2

1

4.50

4.75

4.50

11.4

5.50

5.25

5.50

12.6

Volts

V_PP

NOTES:

1. 10% V_CCspecifications apply to the standard test configuration (Figures12 and 13).

2. 5% V_CCspecifications apply to the high-speed test configuration (Figures11 and 13).

26

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SMART 5 BOOT BLOCK MEMORY FAMILY

5.3

Capacitance

T_A= 25 °C, f = 1 MHz

Symbol

C_IN

C_OUT

Parameter

Note

4

Typ

6

Max

8

Unit

pF

Conditions

V_IN= 0 V

V_OUT= 0 V

Input Capacitance

Output Capacitance

4, 7

10

12

pF

1. Sampled, not 100% tested.

5.4

DC Characteristics—Commercial and Extended Temperature

Temp

Comm

Extended

Sym

Parameter

Note Typ Max Typ Max Unit

Test Condition

I_IL

Input Load Current

Output Leakage Current

V_CCStandby Current

1

±1.0

± 10

2.0

±1.0 µA V_CC= V_CCMax, V_IN= V_CCor GND

± 10 µA V_CC= V_CCMax, V_IN= V_CCor GND

I_LO

I_CCS

V_CC= V_CCMax, CE# = RP# =

2.5 mA

1,3

BYTE# = WP# = V_IH

V_CC= V_CCMax

150 µA

130

8

CE# = RP# = V_CC± 0.2 V

I_CCD

V_CCDeep Power-Down

Current

1

8

µA V_CC= V_CCMax, V_IN= V_CCor GND

RP# = GND ± 0.2 V

V_CCRead Current

CMOS INPUTS

I_CCR

1,5,

6

60

65

65 mA

70 mA

50 mA

(Word or Byte Mode)

V

_CC= V_CCMax, CE# = GND,

OE# = V_CC,f = 10 MHz (5 V),

I_OUT= 0 mA, Inputs=GND or V_CC

TTL INPUTS

V_CC= V_CCMax, CE# = V_IL,

OE# = V_IH, f = 10 MHz (5 V),

I_OUT= 0 mA, Inputs = V_ILor V_IH

I_CCWV_CCProgram Current

(Word or Byte Mode)

1,4

50

45

V_PP= V_PPH1 (at 5 V)

45 mA _VPP= V_PPH2 (at 12 V)

45 mA _PP= V_PPH1 (at 5 V)

I_CCE

V_CCErase Current

35

V

30

40 mA V_PP= V_PPH2 (at 12 V)

I_CCESV_CCErase Susp Current 1,2

10

12.0 mA CE# = V_IH, Block Erase Suspend

I_PPS

I_PPD

V_PPStandby Current

1

± 10

5.0

± 15 µA V_PP< V_PPH

2

V_PPDeep Power-Down

Current

10 µA RP# = GND ± 0.2 V

I_PPR

V_PPRead Current

1

200

200 µA

V_PP≥ V_PPH2

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E

5.4 DC Characteristics—Commercial and Extended Temperature (Continued)

Temp

Comm

Extended

Sym

I_PPW

Parameter

Note Typ Max Typ Max Unit

Test Condition

30 mA V_PP= V_PPH1 (at 5 V)

25 V_PP= V_PPH2 (at 12 V)

25 mA V_PP= V_PPH1 (at 5 V)

20 V_PP= V_PPH2 (at 12 V)

V_PPProgram Current

(Word or Byte Mode)

V_PPErase Current

1,4

25

20

I_PPE

20

15

I_PPESV_PPErase Susp Current

1

200

500

200 µA V_PP= V_PPH, Block Erase Suspend

500 µA RP# = V_HH(to unlock Boot Block)

500 µA A₉= V_ID

I_RP#

I_ID

RP# Unlock Current

A₉Identifier Current

1,4

5.4

DC Characteristics—Commercial and Extended Temperature (Continued)

Temp Comm/Ext

Sym

Parameter

Note

Min

Max

Unit

Test Condition

V_ID

A₉Intelligent Identifier

Voltage

11.4

12.6

V

V_IL

Input Low Voltage

–0.5

2.0

0.8

V

V_CC

0.5 V

+

V_IH

Input High Voltage

V_OL

Output Low Voltage

0.45

V

V_CC= V_CCMin, I_OL= 5.8 mA

V_CC= V_CCMin, I_OH= –2.5 mA

V_OH

1

2

Output High Voltage (TTL)

Output High Voltage (CMOS)

2.4

0.85 x

V_CC

V_OH

V_{CC –}

0.4V

V

V_CC= V_CCMin, I_OH= –100 µA

V_PPLKV_PPLock-Out Voltage

3

0.0

4.5

1.5

5.5

V

Complete Data Protection

V_PPat 5 V

V_PPH

1

2

V_PP(Prog/Erase Operations)

V_PPH

11.4

2.0

12.6

V_PPat 12 V

V_LKOV_CCErase/Prog Lock Voltage

V_HHRP# Unlock Voltage

11.4

12.6

Boot Block Program/Erase

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NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V_CC= 5.0 V, T = +25 °C. These currents are valid for all

product versions (packages and speeds).

2.

I

_CCESis specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

I_CCESand I_CCR

.

3. Block erases and word/byte program operations are inhibited when V_PP= V_PPLK, and not guaranteed in the range between

V

_PPH1 and V_PPLK.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto less than 1 mA typical, in static operation.

6. CMOS Inputs are either V_CC± 0.2 V or GND ± 0.2 V. TTL Inputs are either V_ILor V_IH

.

3.0

OUTPUT

INPUT

1.5

TEST POINTS

1.5

0.0

0599-10

NOTE:

AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.

Input rise and fall times (10% to 90%) <10 ns.

Figure 11. High Speed Test Waveform

2.4

2.0

0.8

2.0

0.8

INPUT

OUTPUT

TEST POINTS

0.45

0599-11

NOTE:

AC test inputs driven at V_OH(2.4 V_TTL) for logic “1” and V_OL(0.45 V_TTL) for logic “0.” Input timing begins at V_IH(2.0 V_TTL) and V_IL

(0.8 V_TTL) . Output timing ends at V_IHand V_IL. Input rise and fall times (10% to 90%) <10 ns.

Figure 12. Standard Test Waveform

29

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

V

IH

RP# (P)

V_CC

t_PHQV

t_PHWL

t_PHEL

V_IL

t_PLPH

(A) Reset during Read Mode

R₁

Abort

Complete

t_PHQV

t_PHWL

t_PHEL

DEVICE

UNDER

OUT

t _PLRH

TEST

V_IH

V_IL

C_L

RP# (P)

R₂

t _PLPH

t _PLRH

<

(B) Reset during Program or Block Erase,

Abort Deep

Complete Power-

0599-12

t_PHQV

t_PHWL

t_PHEL

NOTE:

Down

t _PLRH

C_Lincludes jig capacitance.

V_IH

V_IL

RP# (P)

Figure 13. Test Configuration

t _PLPH

Test Configuration Component Values

(C) Reset Program or Block Erase,

>

t _PLPHt_PLRH

0599-13

Test Configuration

5 V Standard Test

C_L(pF) R₁(Ω) R₂(Ω)

Figure 14. AC Waveform for Reset Operation

Table 9. Reset Specifications⁽¹⁾

100

30

580

390

5 V High-Speed Test

Sym

Parameter

Min Max Unit

t_PLPHRP# Pulse Low

Time

60

ns

t_PLRHRP# Low to Reset

during Prog/Erase

12

µs

1. If RP# is tied to V , these specs are not applicable.

CC

2. These specifications are valid for all product versions

(packages and speeds).

3. If RP# is asserted while a program or block erase, is

not executing, the reset will complete within t_PLPH

.

4. A reset time, t_PHQV, is required after t_PLRHuntil outputs

are valid. See Section 3.1.5 for detailed information.

30

ADVANCE INFORMATION

E

SMART 5 BOOT BLOCK MEMORY FAMILY

5.5

AC Characteristics—Read Operations—Commercial and Extended

Temperature

Temp

Speed

V_CC

Commercial

-60/-70

Extended

-80/-90

#

Sym

Parameter

5V ± 5%⁽⁴⁾5V±10% ⁽⁵⁾5V± 10%⁽⁵⁾5V± 10%⁽⁵⁾Unit

30 pF 100 pF 100 pF 100 pF

Load

Notes Min Max Min Max Min Max Min Max

R1 t_AVAVRead Cycle

Time

2, 4 Mbit

8 Mbit

60

70

80

90

80

90

ns

R2 t_AVQVAddress to

Output Delay

2, 4 Mbit

8 Mbit

60

70

80

90

80 ns

90 ns

80 ns

90 ns

40 ns

450 ns

ns

R3 t_ELQVCE# to

Output Delay

2, 4 Mbit

8 Mbit

2

60

70

80

70

80

90

R4 t_GLQVOE# to Output Delay

R5 t_PHQVRP# to Output Delay

R6 t_ELQXCE# to Output in Low Z

R7 t_GLQXOE# to Output in Low Z

R8 t_EHQZCE# to Output in High Z

R9 t_GHQZOE# to Output in High Z

30

35

40

450

3

0

ns

20

25 ns

ns

R10 t_OH

Output Hold from Address,

CE#, or OE# Change,

Whichever Occurs First

0

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t_CE–t_OEafter the falling edge of CE# without impact on t_CE

.

3. Sampled, but not 100% tested.

4. See Test Configuration (Figure 13), 5 V High-Speed Test component values.

5. See Test Configuration (Figure 13), 5 V Standard Test component values.

6. Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device

is in deep power-down or powered down.

31

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

Device and

Data

Valid

Address Selection

Standby

V

IH

ADDRESSES (A)

V_IL

Address Stable

R1

V

IH

CE# (E)

V_IL

R8

R9

V

IH

OE# (G)

V_IL

V

WE# (W) ^IH

R4

R3

Valid Output

R7

R10

V_IL

V_OH

DATA (D/Q)

V_OL

R6

R5

High Z

R2

V

IH

RP#(P)

V_IL

0599-14

Figure 15. AC Waveforms for Read Operations

5.6

Erase and Program Timings—Commercial and Extended Temperature

V_CC= 5 V ± 10%

Temp

V_PP

Commercial

5 V ± 10% 12 V ± 5%

Extended

5 V ± 10% 12 V ± 5%

Typ Max Units

Parameter

Typ

Max

7

Typ

Max

7

Typ

Max

7

s

Boot/Parameter Block Erase Time

Main Block Erase Time

7

14

s

Main Block Write Time (Byte Mode)

Main Block Write Time (Word Mode)

Byte Program Time

s

µs

100

Word Program Time

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value

independent of V_CCand V_PP. See Note 3 for typical conditions.

3. Typical conditions are 25 °C with V_CCand V_PPat the center of the specified voltage range.Production programming using

_CC= 5.0 V, V_PP= 12.0 V typically results in a 60% reduction in programming time.

V

4. Contact your Intel representative for information regarding maximum byte/word write specifications.

5. Max program times are guaranteed for the two parameter blocks and 96-KB main block only.

32

ADVANCE INFORMATION

E

SMART 5 BOOT BLOCK MEMORY FAMILY

5.7

AC Characteristics—Write Operations—Commercial and Extended

Temperature

Comm

Extended

#

Sym

Parameter

Note Min Max Min Max Unit

W1 t_PHWL(t_PHEL

)

RP# High Recovery to WE# (CE#) Going

Low

450

ns

W2 t_ELWL(t_WLEL

)

CE# (WE#) Setup to WE# (CE#) Going

Low

0

ns

W3 t_WP

W4 t_DVWH(t_DVEH

W5 t_AVWH(t_AVEH

W6 t_WHEH(t_EHWH

W7 t_WHDX(t_EHDX

W8 t_WHAX(t_EHAX

W9 t_WPH

Write Pulse Width

9

4

3

50

0

60

0

ns

)

Data Setup to WE# (CE#) Going High

Address Setup to WE# (CE#) Going High

CE# (WE#) Hold from WE# (CE#) High

Data Hold from WE# (CE#) High

Address Hold from WE# (CE#) High

Write Pulse Width High V_CC= 5 V ± 5%

)

4

3

0

)

0

10

20

10

20

V_CC= 5 V ±

10%

W10 t_PHHWH(t_PHHEH

)

RP# V_HHSetup to WE# (CE#) Going High

V_PPSetup to WE# (CE#) Going High

RP# V_HHHold from Valid SRD

V_PPHold from Valid SRD

6,8 100

5,8 100

100

0

ns

W11 t_VPWH(t_VPEH

)

ns

W12 t_QVPH

W13 t_QVVL

6,8

5,8

7,8

0

ns

W14 t_PHBR

Boot Block Lock Delay

100

100 ns

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer toAC

Characteristics—Read-Only Operations.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally

which includes verify operations.

3. Refer to command definition table for valid A . (Table 6)

IN

4. Refer to command definition table for valid D . (Table 6)

IN

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at V_HHor WP# should be held at V_IHuntil operation completes

successfully.

7. Time t_PHBRis required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. Write pulse width (t_WP) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going high

(whichever goes high first). Hence, t_WP= t_WLWH= t_ELEH= t_WLEH= t_ELWH

.

10. Write pulse width high (t_WPH) is defined from CE# or WE# going high (whichever goes high first)to CE# or WE# going low

(whichever goes low first). Hence, t_WPH= t_WHWL= t_EHEL= t_WHEL= t_EHWL

.

33

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

A

B

C

A

D

E

F

V

IH

ADDRESSES [A]

CE#(WE#) [E(W)]

A_IN

IN

V_IL

W8

V

W5

IH

V_IL

W6

W2

V

IH

OE# [G]

V_IL

W9

V

IH

WE#(CE#) [W(E)]

V_IL

W3

W4

W7

V

IH

High Z

W1

Valid

SRD

DATA [D/Q]

D

IN

D

IN

V_IL

W10

W12

V_HH

6.5V

V

IH

RP# [P]

V_IL

V

IH

WP#

V_IL

W11

W13

V_PPH

2

V_PPH

V_PPLK

V_IL

1

V_PP[V]

0599-15

NOTE:

A.

B. Write Program Set-Up or Erase Set-Up Command.

V

power-up and standby.

CC

C. Write valid address & data (if program operation) or Erase Confirm (if erase operation) command.

D. Automated program or erase delay.

E. Read status register data.

F. Write Read Array command if write operations are completed.

Figure 16. AC Waveforms for Write Operations

34

ADVANCE INFORMATION

E

SMART 5 BOOT BLOCK MEMORY FAMILY

6.0 ORDERING INFORMATION

E2 8 F 4 0 0B5 - T 6 0

Operating Temperature

Access Speed

T = Top Boot

, ns

T = Extended Temp

Blank = Commercial Temp

B = Bottom Boot

Package

E = TSOP

PA = 44-Lead PSOP

TB = Ext. Temp 44-Lead PSOP

Voltage Options (V_PP/ V_CC

5 = (5 or 12 / 5)

)

Product line designator

for all Intel Flash products

Density / Organization

Architecture

X00 = x8/x16 Selectable (X = 2, 4, 8)

00X = x8-only (X = 4)

B = Boot Block

0599_16

VALID COMBINATIONS

40-Lead TSOP

44-Lead PSOP

48-Lead TSOP

E28F200B5T60

E28F200B5B60

E28F200B5T80

E28F200B5B80

E28F400B5T60

E28F400B5B60

E28F400B5T80

E28F400B5B80

E28F800B5T70

E28F800B5B70

E28F800B5T90

E28F800B5B90

Commercial

2M

4M

8M

PA28F200B5T60

PA28F200B5B60

PA28F200B5T80

PA28F200B5B80

PA28F400B5T60

PA28F400B5B60

PA28F400B5T80

PA28F400B5B80

PA28F800B5T70

PA28F800B5B70

PA28F800B5T90

PA28F800B5B90

E28F004B5T60

E28F004B5B60

E28F004B5T80

E28F004B5B80

Extended

2M

4M

8M

TB28F200B5T80

TB28F200B5B80

TB28F400B5T80

TB28F400B5B80

TB28F800B5T90

TB28F800B5B90

TE28F200B5T80

TE28F200B5B80

TE28F400B5T80

TE28F400B5B80

TE28F800B5T90

TE28F800B5B90

35

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

7.0 ADDITIONAL INFORMATION

Order Number

Document

292194

290531

290530

290539

290448

290449

290450

290451

297862

AB-65 Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet

28F002/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet

28F002/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

Smart 5 Boot Block Flash Memory Family 28F200B5, 28F400/004B5, 28F800B5

Specification Update

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

36

ADVANCE INFORMATION

E

SMART 5 BOOT BLOCK MEMORY FAMILY

APPENDIX A

WRITE STATE MACHINE: CURRENT-NEXT STATE

CHART

Write State Machine Current/Next States

Command Input (and Next State)

Current

State

SR.7

Data

When

Read

Array

(FFH)

Program Erase

Setup

Erase

Read

Clear

Read

ID

(90H)

Setup Confirm Susp. Resume Status Status

(10/40H)

(20H)

(D0H)

(B0H)

(D0H)

(70H)

(50H)

Read

Array

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

“1”

“0”

Array

Status

Read Array

Program

Setup

Program (Command Input = Data to be programmed)

Program

Program:

Not

Complete

Program:

Complete

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

“1”

Status

Read Array

Erase

Setup

Erase Command Error

Erase

Cmd.

Error

Erase

Erase Command Error

Erase

Cmd.

Error

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

“1”

“0”

Status

Read Array

Erase:

Not

Complete

Erase

Susp. to

Status

Erase

Erase:

Complete

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

“1”

Read Array

Erase

Suspend

to Status

Erase

Status Susp. to

Array

Erase

Res’d.

Susp. to Erase Susp. to

Array

Erase

Susp. to Susp. to Res’d.

Status

Array

Erase

Suspend

to Array

Erase

Susp. to

Array

Erase

“1”

Array

Susp. to Erase Susp. to

Array

Susp. to Susp. to Res’d.

Status

Array

Read

Status

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

“1”

Status

ID

Read Array

Read

Identifier

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array Read ID

37

ADVANCE INFORMATION

SMART 5 BOOT BLOCK MEMORY FAMILY

E

APPENDIX B

PRODUCT BLOCK DIAGRAM

7769_01

38

ADVANCE INFORMATION


型号：	E28F004B5-B80
厂家：	INTEL
描述：	512KX8 FLASH 5V PROM, 80ns, PDSO40, 10 X 20 MM, TSOP-40 可编程只读存储器光电二极管内存集成电路
文件：	总38页 (文件大小：495K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

E28F004B5-B80 [INTEL]

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