EM2130X0XQI [INTEL]

IntelÂ® EnpirionÂ® Power Solutions EM2130x0xQI 30A PowerSoC;


型号：	EM2130X0XQI
厂家：	INTEL
描述：	IntelÂ® EnpirionÂ® Power Solutions EM2130x0xQI 30A PowerSoC
文件：	总46页 (文件大小：3920K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data SheeT

Intel® Enpirion® Power Solutions

EM2130x0xQI 30A PowerSoC

Step-Down DC-DC Switching Converter with Integrated Inductor, Featuring

Digital Control with PMBus^TMv1.2 Compliant Interface

Description

Features

The EM2130 is a fully integrated 30A PowerSoC • Integrated inductor, FETs, and digital controller

synchronous buck converter. It features an

• Wide 4.5V to 16V V_INrange

advanced

digital

controller,

gate

drivers,

• 0.7V to 3.6V V_OUTrange

synchronous MOSFET switches, and

high-

• 30A continuous current with no thermal de-

rating

• High efficiency in 11mm x 17mm x 6.76mm QFN

package

o95% efficiency at V_IN= 5V, V_OUT= 3.3V

o90% efficiency at V_IN= 12V_,V_OUT= 1.2V

• Optimized total solution size of only 365 mm²

• Meets all high-performance FPGA requirements

oDigital loop for best in class transient response

o0.5% set-point over line, load, and

temperature

performance inductor. Only input and output filter

capacitors and a few small signal components are

required for a complete solution. A PMBus version

1.2 compliant interface provides setup, control, and

telemetry.

Differential remote sensing and ±0.5% set-point

accuracy provides precise regulation over line, load

and temperature variation. Very low ripple further

reduces accuracy uncertainty to provide best in

class static regulation for today’s FPGAs, ASICs,

processors, and DDR memory devices.

oOutput ripple as low as 10 mV peak-peak

oDifferential remote sensing

The EM2130 may be used in standalone mode or

utilizing the PMBus interface for a high degree of

flexibility and programmability. Advanced digital

control techniques ensure stability and excellent

dynamic performance and eliminate the need for

external compensation components. The PC-based

Intel Enpirion Digital Power Configurator provides a

user-friendly and easy-to-use interface to the

device for communication and configuration.

oMonotonic startup into pre-bias output

oOptimized FPGA configs stored in NVM

• Programmable through PMBus™

oV_OUTmargining, startup and shutdown delays

oProgrammable warnings, faults and response

• Ability to operate without PMBus™

oRVSET resistor for programmable V_OUT

oRTUNE resistor for single resistor

compensation

• Tracking pin for complex sequencing

• RoHS compliant, MSL level 3, 260°C reflow

The EM2130 features high conversion efficiency

and superior thermal performance to minimize

thermal de-rating limitations, which is key to

product reliability and longevity.

Applications

• High performance FPGA supply rails

• ASIC and processor supply rails

• High density double data rate (DDR) memory

VDDQ rails

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Ordering Information

Table 1

Package Description

Supported

V_OUTRange

Package

Markings

Part Number

0.7V to

1.325V

17 mm x 11 mm x 6.76 mm QFN104 provided in 112

units per tray

EM2130L02QI

EM2130H01QI

EVB-EM2130L02

M2130L2

17 mm x 11 mm x 6.76 mm QFN104 provided in 112

units per tray

1.35V to 3.6V M2130H

0.7V to

1.325V

Evaluation board; 30A single phase

EVB-EM2130H01

EVI-EM2COMIF

1.35V to 3.6V Evaluation board; 30A single phase

GUI interface dongle

Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-

marking.html

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Pin Assignments

100

VOUT

RVSET

VOUT

101

VOUT

VCCSEN

VTRACK

RTUNE

VINSEN

ADDR1

ADDR0

PWM

SYNC

POK

VSENN

VSENP

AGND

DGND

102

AGND

CTRL

SALRT

SDA

SCL

VDD33

PVIN

VCC 66

PVCC

PVIN

103

PVIN

PGND

PGND 51

104

PGND

Figure 1: Pin Out Diagram

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Pin Description

Table 2

NAME

VOUT

I/O

FUNCTION

1,2,3,

79-101

Regulated

Output

Regulated output voltage. Decouple to PGND with appropriate filter capacitors

A resistor from RVSET to AGND; and can be used to program the V_OUTset-point.

Using 1% tolerance or better resistor. See Table 8 and Table 9 for more

information.

Analog

I/O

RVSET

RTUNE

A resistor from RTUNE to AGND; and can be used to tune the transient

compensator for the amount of output capacitance. Using 1% tolerance or better

resistor. See Table 10 and Table 11 for more information.

Analog

I/O

Analog

Input

VINSEN

ADDR1

ADDR0

Single-ended input voltage sense (relative to AGND).

Analog

I/O

A resistor from ADDR1 to AGND; and can be used to set the PMBus™ address. Use

a 1% tolerance or better resistor.

Analog

I/O

A resistor from ADDR0 to AGND; and can be used to set the PMBus™ address. Use

a 1% tolerance or better resistor.

PWM

SYNC

PWM

PWM signal test pin.

Digital I/O PWM synchronization signal

Power OK is selectable as a push-pull output or an open drain transistor for

power system state indication. See the Power OK description for details.

POK

Digital I/O

PMBus-compatible control pin with programmable functionality. CTRL should

never be left floating if enabled in Configuration. The default configuration is for

Digital

Input

CTRL

V_OUTto be on with CTRL high (positive edge)

Digital

Output

SALRT

PMBus™ alert line.

SDA

SCL

Digital I/O PMBus™ serial data I/O.

Digital I/O PMBus™ serial clock input.

3.3V output of the internal LDO. May be used as pull-up supply for PMBus™ pins

and CTRL pin.

VDD33

Output

17-21,

61-64,

103

Input

Supply

Input supply for MOSFET switches. Decouple to PGND with appropriate filter

capacitors. Refer to Recommended Application Circuit section for more details.

PVIN

22-60,

104

PGND

PVCC

VCC

Ground

Power ground. Ground for MOSFET switches.

Input

Supply

5.0V supply voltage for driver circuitry. Decouple to GND using a 2.2µF MLCC high

quality ceramic capacitor.

Input

Supply

5.0V supply voltage for analog circuitry.

67,68,

73-76

No connect. Do not connect to any signal, supply, or ground.

Digital ground. Connect to AGND pin directly.

DGND

Ground

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NAME

I/O

FUNCTION

Analog ground. Connect to system ground plane. Refer to layout section for more

details on grounding.

70, 102 AGND

Ground

Analog

Input

VSENP

VSENN

Differential output voltage sense input (positive).

Differential output voltage sense input (negative).

Analog

Input

Voltage tracking reference input if EM2130 is configured for voltage tracking

mode. May remain floating if not used. If enabled but not used, connect to

VDD33 using a 10kΩ resistor. VTRACK is not enabled in the default

configuration.

Analog

Input

VTRACK

VCCSEN

Analog

Input

Single-ended VCC voltage sense (relative to AGND)

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Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended

operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Voltage

measurements are referenced to AGND.

Absolute Maximum Pin Ratings

Table 3

PARAMETER

SYMBOL

PVIN

MIN

-0.3

MAX

UNITS

Supply voltage PVIN

Supply voltage VCC

VCC ramp time

VDD33

VCC

5.5

VCC

VDD33

-0.3

3.6

0.1

0.3

5.5

3.6

Digital ground

Power ground

Digital I/O pins

DGND

PGND

SALRT, POK, SYNC,

SCL, SDA, CTRL

VINSEN, VCCSEN, ADDR0, ADDR1,

RVSET, RTUNE, VTRACK

Analog I/O pins

-0.3

2.0

Voltage feedback

PWM pin

VSENP, VSENN

PWM

-0.3

2.0

5.5

3.8

Output voltage pins

DC current on VOUT

VOUT

Absolute Maximum Thermal Ratings

PARAMETER

CONDITION

MIN

-65

MAX

UNITS

°C

Operating junction

temperature

+125

Storage temperature range

+150

+260

°C

Reflow peak body temperature

(10 Sec) MSL3

CONDITION

Absolute Maximum ESD Ratings

PARAMETER

MIN

2000

500

MAX

UNITS

All pins; Except VINSEN 1000 V

Max

HBD

CDM; all pins

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Recommended Operating Conditions

Table 4

PARAMETER

PINS

PVIN

MIN

4.5

MAX

UNITS

PVIN supply voltage range

Supply voltage V_CC& PV_CC

Continuous load current

Junction Temperature (Note 1)

VCC, PVCC

V_OUT

4.75

5.25

-40

125

°C

(Note 1): OTP default is set to 120°C for safety margin

Thermal Characteristics

Table 5

PARAMETER

PINS

T_SD

TYPICAL

UNITS

°C

Thermal shutdown [programmable]

Thermal shutdown Hysteresis

120

T_SDH

°C

Thermal resistance: junction to ambient (0 LFM)

°C/W

θ_JA

θ_JC

(Note 2)

Thermal resistance: junction to case bottom (0 LFM)

1.5

°C/W

Note 1: Based on 2 oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51 standards for high thermal

conductivity boards. No top side cooling required.

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Electrical Characteristics

PV_IN= 12V and V_CC= 5.0V. The minimum and maximum values are over the ambient temperature range (-40°C

to 85°C) unless otherwise noted. Typical values are at T_A= 25°C.

Table 6

PARAMETER

SYMBOL TEST CONDITIONS

SUPPLY CHARACTERISTICS

MIN

4.5

TYP

MAX

UNITS

PVIN supply voltage

range

PVIN

Device switching; no load; f_sw

800 kHz; V_OUT= 1.0V

PVIN supply

quiescent current

Device not switching

VCC supply voltage

range

VCC

4.75

5.0

5.25

VCC UVLO rising

VCC UVLO falling

4.4

4.2

Normal operation; no load;

f_sw= 800 kHz

100

150

Normal operation; no load;

f_sw= 1.33 MHz

120

PVcc & VCC

supply current

Idle; communication and

µA

telemetry only; no switching

Disabled (V_CC≤ 2.8V)

900

INTERNALLY GENERATED SUPPLY VOLTAGE

VDD33 voltage range

VDD33

3.0

3.3

3.6

VDD33 output

current

DIGITAL I/O PINS (POK, SYNC)

Input high voltage

Input low voltage

2.0

5.5

0.8

Output high voltage

Output low voltage

Input leakage current

2.4

VDD33

0.4

±1

µA

Output current -

source

2.0

Output current - sink

DIGITAL I/O PIN (CTRL)

Input high voltage

Input low voltage

2.0

3.6

0.8

-0.3

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PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

150

MAX

UNITS

µs

Configurable polarity; extra

turn-off delay configurable

(assumes 0 s turn-off delay)

CTRL response delay

(stop)

Configurable polarity; extra

turn-on delay configurable

(assumes 0 s turn-on delay)

CTRL response delay

(start)

250

µs

HKADC INPUT PINS (VINSEN, VCCSEN, ADDR0 AND ADDR1)

Input voltage

1.44

PWM AND SYNCHRONIZATION

PWM output voltage

- high

2.4

PWM output voltage

- low

0.4

±1

PWM tristate leakage

PWM pulse width

Resolution

µA

163

Switching frequency

– EM2130L

f_SW

With internal oscillator

800

kHz

Switching frequency

– EM2130H

1333

SYNC frequency

range

Percent of nominal switching

frequency

±12.5

SYNC pulse width

OUTPUT VOLTAGE SENSE, REPORTING, AND MANAGEMENT

EM2130L

0.7

1.35

-0.5

-1

1.325

3.6

Output voltage

adjustment range

EM2130H

EM2130L 0˚C < T_A< 85˚C

EM2130L -40˚C < T_A< 85˚C

EM2130H -40˚C < T_A< 85˚C

+0.5

Output voltage set-

point accuracy

-1

Output set-point

resolution

EM2130L

1.5

Line regulation

Load regulation

0.007

0.07

mV/V

mV/A

From V_CCvalid, to start of

output voltage ramp, if

configured to regulate from

power on reset, and

Output voltage

startup delay

TON_DELAY is set to 0.

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PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

500

UNITS

Output voltage ramp

delay (TON_DELAY &

TOFF_DELAY)

Configurable, no V_OUTpre-bias

condition.

VTRACK ramp rate

VTRACK range

2.0

1.4

V/ms

Without resistor divider

VTRACK offset

voltage

±100

OUTPUT CURRENT SENSE, REPORTING, AND MANAGEMENT

I_OUT> 5A, 25°C < T_A< 85°C

I_OUT> 5A, T_A= 25°C

±1.5

Current sense

reporting accuracy

±1

TEMPERATURE SENSE, REPORTING, AND MANAGEMENT

Temperature

reporting accuracy

±5

°C

Resolution

0.22

FAULT MANAGEMENT PROTECTION FEATURES

PV_INUV threshold

PVIN OV threshold

V_OUTOV threshold

V_OUTUV threshold

I_OUTOCP

3.96

16.5

115

Percentage of output voltage

DC Current Value

OTP threshold

OTP hysteresis

POK threshold

120

°C

Fixed.

On level

Off level

Watchdog Timer

Interval

SERIAL COMMUNICATION PMBUS DC CHARACTERISTICS

Input voltage – high

(VIH)

SCL and SDA

1.11

Input voltage – low

(VIL)

0.8

Rise & Fall Time

SCL and SDA >0.8V<1.1V

SCL, SDA and CTRL.

SALRT

µA

Input leakage current

leakage current

-10

Output voltage – low

(VOL)

SDA and SCL at rated pull-up

current of 20mA.

0.4

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PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

3.3

MAX

3.6

UNITS

SCL, SDA, and SALRT

termination voltage.

Nominal bus voltage

1.62

SCL and SDA termination

voltage.

Nominal bus voltage

3.6

Nominal SLART

voltage

SALRT termination voltage.

(1) These values are provided for information only

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Typical Performance Characteristics

All the performance curves are measured with EM2130 evaluation board at 25°C ambient temperature unless otherwise

noted. The output capacitors configuration for the evaluation board is 2 x 470 µF (3 mΩ ESR) + 4 x 100 µF (Ceramic) + 4

x 47 µF (Ceramic) for EM2130L and 2 x 220 µF (5 mΩ ESR) + 6 x 47 µF (Ceramic) for EM2130H.

Efficiency, V_IN= 12V

Efficiency, V_IN= 5V

EM2130L Thermal Derating, No Airflow

EM2130H Thermal Derating, No Airflow

EM2130L Line Regulation, V_OUT= 0.9V

EM2130L Load Regulation, V_OUT= 0.9V

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Typical Performance Characteristics (Continued)

Start-up/Shutdown, PVIN At No Load,

20 ms/div

Start-up/Shutdown, PVIN At 30A Load,

20 ms/div

PV_IN

V_OUT

PV_IN

V_OUT

PWM

I_OUT

PWM

I_OUT

PV_INand PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

PV_INand PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

Start-up/Shutdown, CTRL At No Load,

5 ms/div

Start-up/Shutdown, CTRL At 30A Load,

5 ms/div

CTRL

V_OUT

CTRL

V_OUT

PWM

I_OUT

PWM

I_OUT

CTRL: 1 V/div, PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

CTRL: 1 V/div, PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

Start-up Into 0.6V Pre-Bias With PVIN,

5 ms/div

Start-up Into 0.6V Pre-Bias With CTRL,

5 ms/div

PV_IN

V_OUT

CTRL

V_OUT

PWM

I_OUT

PWM

I_OUT

PV_IN: 3 V/div, PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

CTRL: 1 V/div, PWM: 3 V/div,

V_OUT: 300 mV/div, I_OUT: 10 A/div

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Typical Performance Characteristics (Continued)

Output Voltage Ripple,

No Load

Output Voltage Ripple,

30A Load

V_OUT

I_OUT

V_IN= 12V, V_OUT= 0.9V

1 µs/div, V_OUT: 10 mV/div, 20 MHz bandwidth

V_IN= 12V, V_OUT= 0.9V

1 µs/div, V_OUT: 10 mV/div, 20 MHz bandwidth

Output Voltage Transient Response,

Load Step From 0A To 15A

Output Voltage Transient Response,

Load Step From 15A To 30A

V_OUT

I_OUT

V_IN= 12V, V_OUT= 0.9V, 100µs/div

_OUT: 30 mV/div, I_OUT: 5 A/div, 15 A/µs

V_IN= 12V, V_OUT= 0.9V, 100µs/div

V_OUT: 30 mV/div, I_OUT: 5 A/div, 15 A/µs

Output Voltage Transient Response,

Load Step From 0A To 15A

Output Voltage Transient Response,

Load Step From 0A To 15A

V_OUT

I_OUT

V_IN= 12V, V_OUT= 0.9V, 2µs/div

V_IN= 12V, V_OUT= 0.9V, 10µs/div

V_OUT: 10 mV/div, I_OUT: 5 A/div, 100 A/µs

V_OUT: 10 mV/div, I_OUT: 5 A/div, 1 A/µs

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Functional Block Diagram

Average

Digital Control Loop

Current Sensing

VSENP

VFB

Adaptive

Digital

Controller

FLASH

ADC

VSENN

VTRACK

Power Train

DAC

Sequencer

OC Detection

OV/UV

Detection

PWM

VOUT

Configurable

Error Handler

DAC

DRIVER LOGIC

PWM

OT Detection

Bias

Current

Source

Int.

Temp

Sense

Vin OV/UV

Detection

VREF

1.8V

Reg

Analog

CPU

Core

NVM

(OTP)

VCCSEN

1.8V

Reg

Digital

ADDR0

ADDR1

HKADC

RTUNE

RVSET

VINSEN

Clock

Gen

GPIO

SMBus

3.3V

Reg

Figure 2: Functional Block Diagram

Functional Description

FUNCTIONAL DESCRIPTION: DEFAULT CONFIGURATION

The EM2130 is a single output digital PowerSoC synchronous step-down converter with advanced digital

control techniques, capable of supplying up to 30A of continuous output current. The PowerSoC includes

integrated power MOSFETs, a high-performance inductor and a digital controller which offers a PMBus

version 1.2 compliant interface to support an extensive suite of telemetry, configuration and control

commands.

In the default configuration, the EM2130 requires only two resistors total to set the output voltage and set

the digital compensator for the most optimized performance. This easy-to-use default configuration allows

the user to tune the EM2130 to meet the most demanding accuracy and load transient requirements

without requiring any programming or digital interface. The following sections describe the default

configuration. Refer to the Advanced Configuration section for details on the many ways the EM2130 may

be customized and configured through the PMBus interface.

In order to optimize size versus efficiency over a wide range of operating conditions, there are two module

variants – a low output voltage variant EM2130L (0.7V ≤ V_OUT≤ 1.325V) which operates at 800KHz and a

high output voltage variant EM2130H (1.35V ≤ V_OUT≤ 3.6V) which operates at 1.33MHz.

The advanced digital control loop works as a voltage-mode controller using a PID-type compensation. The

basic structure of the controller is shown in Figure 3. The EM2130 controller features two PID

compensators for steady-state operation and fast transient operation. Fast, reliable switching between the

different compensation modes ensures good transient performance and quiet steady state performance.

The EM2130 has been pre-programmed with a range of default compensation coefficients which lets the

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user select the best compensation for the best transient response and stability for the output capacitance

of the system.

The EM2130 uses two additional technologies to improve transient performance. First, the EM2130 uses

over-sampling techniques to acquire fast, accurate, and continuous information about the output voltage

so that the device can react quickly to any changes in output voltage. Second, a non-linear gain adjustment

is applied during large load transients to boost the loop gain and reduce the settling time.

Coefficients

Steady-State

Operation

Mode

Transient

Detection

Duty Cycle

Digital PID

Compensator

Non-linear

Gain

Digital Error Signal

Figure 3: Simplified Block Diagram Of The Digital Compensation

In the default configuration, the EM2130 offers a complete suite of fault warnings and protections. Input

and output Under Voltage Lock-Out (UVLO) and Over Voltage Lock-Out (OVLO) conditions are

continuously monitored. A dedicated ADC is used to provide fast and accurate current information over

the switching period allowing for fast Over-Current Protection (OCP) response. Over Temperature

Protection (OTP) is accomplished by direct monitoring of the device’s internal temperature.

POWER ON RESET

The EM2130 employs an internal power-on-reset (POR) circuit to ensure proper start-up and shut down

with a changing supply voltage. Once the VCC supply voltage increases above the POR threshold voltage,

the EM2130 begins the internal start-up process. Upon its completion, the device is ready for operation.

Two separate input voltage supplies are necessary to operate, PVIN (4.5V to 16V) and V_CC(4.75V to 5.25V).

Both of these voltage rails must be monitored for proper power-up and to protect the power MOSFETs

under various input power fault conditions. A voltage divider on each input voltage supply connected to

VINSEN for the power rail (PVIN) and VCCSEN for the supply rail (VC) is used for digital monitoring of the

supplies.

As illustrated in Figure 4, the values of resistors R1, R2, R3 and R4 are chosen so the internal monitor ADC

does not saturate within the appropriate ranges. This allows the EM2130 telemetry to report when the

recommended operation voltage has been exceeded.

It is mandatory that the listed resistors values are used in order to ensure proper operation with the

EM2130 default configuration. The resistors used must be R1=11 kΩ, R2=1 kΩ, R3=10 kΩ and R4=3.3 kΩ,

using 1% tolerance or better resistors. If these values are not used then the EM2130 will read incorrect

values for both PVIN and VCC.

Digital filtering is provided inside the EM2130 but if additional filtering is needed due to high noise on

either rail, a capacitor can be connected between each pin (VINSEN & VCCSEN) and ground to maintain

high accuracy.

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EM2130

VCC

R₃

10 kΩ

PVIN

VCCSEN

R₄

3.3 kΩ

R₁

11 kΩ

VINSEN

AGND

R₂

1 kΩ

Figure 4: VINSEN And VCCSEN Input Resistor Dividers

The EM2130 also uses the PVIN monitor for input voltage feed-forward, which eliminates variations in the

output voltage due to sudden changes in the input voltage supply. It does this by immediately changing

the duty cycle to compensate for the input supply variation by normalizing the DC gain of the loop.

SETTING THE OUTPUT VOLTAGE

Differential remote sensing provides for precise regulation at the point of load. One of thirty output

voltages may be selected in the default configuration, based on a resistor connected to the RVSET pin. At

power-up, an internal current source biases the resistor and the voltage is measured by an ADC to decode

the Vout selection. Use the RVSET tables (Table 8 and Table 9) for the details of V_OUTselection and RVSET

values.

EM2130

RDIV1

VSENP

VOUT

PGND

RDIV2

VSENN

Figure 5: Output Voltage Sense Circuitry

The digital control loop ADC of the low voltage EM2130L supports direct output voltage feedback

connection over the entire V_OUTrange. For the high output voltage EM2130H, a feedback divider is required

as shown in Figure 5. The resistor values in Table 7 are required as a function of the output voltage

selection. It is mandatory that the listed resistor values are used, use of other values may result in poor

regulation performance as these values are expected in the EM2130 default configuration. Resistors with

tight tolerances are recommended to maintain output voltage accuracy.

The resistors in the feedback path also form a low-pass filter with the internal capacitor, C_A, for removing

high-frequency disturbances from the sense signals. Place these components as close as possible to the

EM2130 for best filtering performance.

Table 7: Output Voltage Feedback Component

Module

V_OUT

R_DIV1

2 kΩ

R_DIV2

Open

2 kΩ

1 kΩ

EM2130Lxx

EM2130Hxx

0.7V ≤ V_OUT≤ 1.325V

1.35V ≤ V_OUT≤ 2.6V

2.7V ≤ V_OUT≤ 3.6V

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Table 8: Supported Configuration Voltage Values For EM2130L Output Voltage

RVSET Resistor

0kΩ

V_OUT

Reserved

1.325V

1.3V

External Resistor Divider

R_1DIV= 2kΩ, R_2DIV= open

0.392kΩ

0.576kΩ

0.787kΩ

1.000kΩ

1.240kΩ

1.500kΩ

1.780kΩ

2.100kΩ

2.430kΩ

2.800kΩ

3.240kΩ

3.740kΩ

4.220kΩ

4.750kΩ

5.360kΩ

6.040kΩ

6.810kΩ

7.680kΩ

8.660kΩ

9.530kΩ

10.500kΩ

11.800kΩ

13.000kΩ

1.275V

1.25V

1.225V

1.2V

1.175V

1.15V

1.12V

1.1V

1.075V

1.05V

1.03V

1.0V

0.975V

0.95V

0.925V

0.9V

0.875V

0.85V

14.300kΩ

15.800kΩ

17.400kΩ

0.825V

0.8V

R_1DIV= 2kΩ, R_2DIV= open

0.775V

19.100kΩ

21.000kΩ

23.200kΩ

0.75V

0.725V

0.7V

R_1DIV= 2kΩ, R_2DIV= open

Table 9: Supported Configuration Voltage Values For EM2130H Output Voltage

RVSET Resistor

V_OUT

External Resistor Divider

0kΩ

Reserved

R_1DIV= 2kΩ, R_2DIV= 1kΩ

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RVSET Resistor

0.392kΩ

0.576kΩ

0.787kΩ

1.000kΩ

1.240kΩ

1.500kΩ

1.780kΩ

2.100kΩ

2.430kΩ

2.800kΩ

3.240kΩ

3.740kΩ

4.220kΩ

4.750kΩ

5.360kΩ

6.040kΩ

6.810kΩ

7.680kΩ

8.660kΩ

9.530kΩ

10.500kΩ

11.800kΩ

13.000kΩ

V_OUT

External Resistor Divider

R_1DIV= 2kΩ, R_2DIV= 1kΩ

R_1DIV= 2kΩ, R_2DIV=1kΩ

R_1DIV= 2kΩ, R_2DIV= 1kΩ

R_1DIV= 2kΩ, R_2DIV= 2kΩ

Reserved

3.3V

3.2V

3.1V

3.0V

2.9V

2.8V

2.7V

2.6V

2.5V

2.4V

2.3V

2.2V

2.1V

2.0V

1.9V

1.8V

1.75V

1.7V

1.65V

1.6V

1.55V

1.5V

14.300kΩ

15.800kΩ

17.400kΩ

1.475V

1.45V

R_1DIV= 2kΩ, R_2DIV= 2kΩ

1.425V

19.100kΩ

21.000kΩ

23.200kΩ

1.4V

1.375V

1.35V

R_1DIV= 2kΩ, R_2DIV= 2kΩ

ENABLE And OUTPUT START-UP BEHAVIOR

The control pin (CTRL) provides a means to enable normal operation or to shut down the device. When the

CTRL pin asserted (high) the device will undergo a normal soft-start. A logic low on this pin will power the

device down in a controlled manner. Dedicated pre-biased start-up logic ensures proper start-up of the

power converter when the output capacitors are pre-charged to a non-zero output voltage. Closed-loop

stability is ensured during this period.

The typical power sequencing, including ramp up/down and delays is shown in Figure 6.

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Figure 6: Power Sequencing

POWER OK

The EM2130 has a power good indicator at its output pin, POK. When de-asserted, POK indicates that the

output voltage is below the threshold value, 90% of the programmed output voltage in the default

configuration. When asserted, POK indicates that the output is in regulation, and no major faults are

present. As a result, POK de-asserts during any serious fault condition where power conversion stops and

re-asserts when the output voltage recovers.

The POK indication can be either push-pull or open-drain, selected based upon the PMBus™ address. For

addresses in the range 0x01 to 0x40, the POK signal is a push-pull output and no pull-up resistor is

required. For addresses in the range 0x41 to 0x7F, the POK signal is open-drain and may be wire-OR’d with

other open drain signals with an appropriate pull-up resistor. The Pull-Up resistor may be connected to

the VDD33 pin but it is not recommended to use the 5VCC supply. Table 15 describes the resistor values

which are used to set the PMBus address.

In a noisy application, it is strongly recommended that a 100nf decoupling capacitor be placed between

the POK pin and GND to act as a filter to unwanted external noise. When configured as a Push-Pull

output, a 10kΩ pull-down resistor to Gnd may be used instead to prevent any spurious noise spikes

appearing on POK upon power being applied to the module.

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SMBAlert Pin

The SMBAlert pin is intended to operate using an external pull-up voltage of 3.3V and contains a weak

internal pull-up.

If operating in applications with a lower voltage pull-up voltage, it is recommended that an external low Vf

Schottky diode be placed at the input to localise this voltage.

VPull-Up

SMBAlert

EM2120

Figure 7: SMBAlert Pin Low Voltage Pull-up Option

Table 10: Schottky Diode Options

Description

Manufacturer

P/N

40V, 300mA, Schottky, SOD523

40V, 250mA, Schottky, SOD523

BAT54KFILM

BAT64T5Q

Diode Inc

COMPENSATING THE DIGITAL CONTROL LOOP

To improve the transient performance for a typical point-of-load design, it is common to add output

capacitance to the converter. This moves the output LC resonant frequency lower as capacitance increases

which results in lower bandwidth, lower phase margin, and longer settling times unless the control loop is

compensated for added capacitance.

However, with EM2130 the user does not need to be concerned with, or even understand, the details of

control loop compensation techniques. The default configuration allows users to select from

preconfigured PID control loop settings (known as compensators) through the use of pin-strapping. A

single resistor from the RTUNE pin to AGND informs the EM2130 of the compensator selection.

The selection of the compensator is driven first by the type of output capacitors used, as the ESL and ESR

of different capacitor types demands different PID coefficients to optimize transient deviation and recovery

characteristics. An all ceramic output capacitor design requires a different compensator than a design with

a combination of ceramic and polymer capacitors, i.e. POSCAP. Table 12 shows several output capacitor

part number recommendations.

The five different compensators can then be subdivided into groups of six each whereby the initial

capacitance value in the appropriate compensator can be scaled upwards by multiplication factor M to

match the additional capacitance.

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Table 11: RTUNE configuration table for EM2130L

Multiplication

factor (M)

Typical Deviation

With 15A Load Step

Compensator Description

C_OUT

RTUNE Resistor

Base

0kΩ

± 5%

± 3%

Polymer Aluminum (SP-

CAP) and Ceramic MLCC

Output Capacitors

2 x Base

3 x Base

4 x Base

5 x Base

6 x Base

Base

0.392kΩ

0.576kΩ

0.787kΩ

1.000kΩ

1.240kΩ

1.500kΩ

1.780kΩ

2.100kΩ

2.430kΩ

2.800kΩ

3.240kΩ

3.740kΩ

4.220kΩ

4.750kΩ

5.360kΩ

6.040kΩ

6.810kΩ

7.680kΩ

8.660kΩ

9.530kΩ

10.500kΩ

11.800kΩ

13.000kΩ

14.300kΩ

15.800kΩ

17.400kΩ

19.100kΩ

21.000 kΩ

23.200 kΩ

Base capacitance = 1 x 470µF

(Polymer) + 2 x 100µF

(Ceramic) + 2 x 47µF

(Ceramic)

± 1.5%

± 5%

± 3%

1.5 x Base

2 x Base

3 x Base

4 x Base

4.5 x Base

Base

1.5

All MLCC Ceramic Output

Capacitors

Base capacitance = 8 x 100µF

4.5

± 1.5%

± 5%

POSCAP and Ceramic MLCC

Output Capacitors

Base capacitance = 4 x 330 µF

(POSCAP) + 2 x 100 µF

(Ceramic)

1.5 x Base

2 x Base

2.5 x Base

3 x Base

3.5 x Base

1.5

± 3%

2.5

± 1.5%

3.5

Reserved for User

Programmed Compensation

Values

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Table 12: RTUNE configuration table for EM2130H

Multiplication

factor (M)

Typical Deviation

With 15A Load Step

Compensator Description

C_OUT

RTUNE Resistor

Base

2 x Base

2.5 x Base

3 x Base

3.5 x Base

4 x Base

Base

0kΩ

± 3%

Polymer Aluminum (SP-

CAP) and Ceramic MLCC

Output Capacitors

0.392kΩ

0.576kΩ

0.787kΩ

1.000kΩ

1.240kΩ

1.500kΩ

1.780kΩ

2.100kΩ

2.430kΩ

2.800kΩ

3.240kΩ

3.740kΩ

4.220kΩ

4.750kΩ

5.360kΩ

6.040kΩ

6.810kΩ

7.680kΩ

8.660kΩ

9.530kΩ

10.500kΩ

11.800kΩ

13.000kΩ

14.300kΩ

15.800kΩ

17.400kΩ

19.100kΩ

21.000 kΩ

23.200 kΩ

2.5

Base capacitance = 2 x 220µF

(Polymer) + 6 x 47µF

(Ceramic)

3.5

± 3%

1.5 x Base

2 x Base

2.5 x Base

2.75 x Base

3 x Base

1.5

All MLCC Ceramic Output

Capacitors

Base capacitance = 10 x

100µF

2.5

2.75

Reserved for User

Programmed Compensation

Values

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Table 13: Recommended Output Capacitors

Description

Manufacturer

Panasonic

Kemet

P/N

470µF, 2.5V, ESR 3mΩ SP-CAP

330µF, 6.3V, ESR 9 mΩ POSCAP

220µF, 6.3V, ESR 5 mΩ POSCAP

330µF, 2.5V, ESR 9 mΩ POSCAP

100µF, 6.3V, X5R, 1206 Ceramic

47µF, 6.3V, X5R 12b06 Ceramic

EEFGX0E471R

6TPF330M9L

6TPF220M5L

T520B337M2R5ATE009

C1206C107M9PACTU

GRM31CR60J476ME19L

Kemet

Murata

OUTPUT CAPACITOR RECOMMENDATION

EM2130 is designed for fast transient response and low output ripple noise. The output capacitors should

be low ESR polymer, tantalum or ceramic capacitor. Table 10 and Table 11 show different output capacitor

combinations to optimize the load transient deviation performance. With the Rtune feature, the user can

simply scale up the total output capacitance to meet further stringent transient requirement.

Please consult the documentation for your particular FPGA, ASIC, processor, or memory block for the

transient and the bulk decoupling capacitor requirements.

INPUT CAPACITOR RECOMMENDATION

The EM2130 input should be decoupled with at least three 22µF 1206 case size and one 10µF 0805 case

size MLCC ceramic capacitors or four 22µF MLCC 1206 case size ceramic capacitors. More bulk capacitor

may be needed only if there are long inductive traces at the input source or there is not enough source

capacitance.

These input decoupling ceramic capacitors can be mounted on the PCB back-side to reduce the solution

size. These input filter capacitors should have the appropriate voltage rating for the input voltage on PVIN,

and use a X5R, X7R, or equivalent dielectric rating. Y5V or equivalent dielectric formulations must not be

used as these lose too much capacitance with frequency, temperature and bias voltage.

The PVCC pin provides power to the gate drive of the internal high/low side power MOSFETs. The VCC pin

provides power to the internal digital controller. These two power inputs share the same supply voltage

(5V nominal), and should be bypassed with a single 2.2µF MLCC capacitor. To avoid switching noise

injection from PVCC to VCC, it is recommended a ferrite bead is inserted between PVCC and VCC pins as

shown Figure 15.

PROTECTION FEATURES

The EM2130 offers a complete suite of programmable fault warnings and protections. Input and output

Under Voltage Lock-Out (UVLO) and Over Voltage Lock-Out (OVLO) conditions are continuously

monitored. A dedicated ADC is used to provide fast and accurate current information during the entire

switching period to provide fast Over-Current Protection (OCP) response.

To prevent damage to the load, the EM2130 utilizes an output over-voltage protection circuit. The voltage

at VSENP is continuously compared with a configurable threshold using a high-speed analog comparator.

If the voltage exceeds the configured threshold, a fault response is generated and the PWM output is turned

off.

The output voltage is also sampled, filtered, and compared with an output over-voltage warning threshold.

If the output voltage exceeds this threshold, a warning is generated and the preconfigured actions are

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triggered. The EM2130 also monitors the output voltage with two lower thresholds. If the output voltage is

below the under-voltage warning level and above the under-voltage fault level, an output voltage under-

voltage warning is triggered. If the output voltage falls below the fault level, a fault event is generated.

Similar to output over and under voltage protection, the EM2130 monitors the input voltage at VINSEN

continuously with a configurable threshold. If the input voltage exceeds the over voltage threshold or is

below the under voltage threshold, the default response is generated.

Over Temperature Protection (OTP) is based on direct monitoring of the device’s internal temperature. If

the temperature exceeds the OTP threshold, the device will enter a soft-stop mode slowly ramping the

output voltage down until the temperature falls below the default recovery temperature.

The default fault response is zero delay and latch off for most fault conditions. The CTRL pin may be cycled

to clear the latch. Table 13 summarizes the default configurations that have been pre-programmed to the

device.

Table 14: Fault Configuration Overview

Signal

Fault Level

Warning

Fault

Default Response Type

High-impedance

Soft Off

Delay (ms)

Retries

None

Output Over-Voltage

Warning

Fault

Output Under-Voltage

Input Over-Voltage

Input Under-Voltage

Over-Current

None

Warning

Fault

Warning

Fault

Infinity

None

Warning

Fault

Warning

Fault

Internal Over-

Temperature

Infinity

FUNCTIONAL DESCRIPTION: ADVANCED CONFIGURATION

All EM2130 modules are delivered with a pre-programmed default configuration, allowing the module to

be powered up without a need to configure the device or even the need for the GUI to be connected.

However, a PMBus version 1.2 compliant interface allows access to an extensive suite of digital

communication and control commands. This includes configuring the EM2130 for optimum performance,

setting various parameters such as output voltage, and monitoring and reporting device behavior including

output voltage, output current, and fault responses.

The device may be reconfigured multiple times without storing the configuration into the non-volatile

memory (NVM). Any configuration changes will be lost upon power-on reset unless specifically stored into

NVM using either STORE_DEFAULT_ALL or STORE_DEFAULT_CODE PMBus commands. Please see Table

16 for more details.

For RVSET and RTUNE configurations, there is no reprogramming permitted.

After writing a new configuration to NVM, the user may still make changes to the device configuration

through the PMBus interface; however, now upon power cycling the device, the stored NVM configuration

will be recalled upon power-up rather than the factory default configuration of the EM2130.

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The NVM configuration can be stored three times in its entirety. However, the consumption of the available

NVM is dynamic, based on the configuration parameters that have actually changed. The unused NVM

information is given in the GUI or through the manufacture specific command

MFR_STORE_PARAMS_REMAINING.

INTEL DIGITAL POWER CONFIGURATOR

The Intel Enpirion Digital Power Configurator is a Graphical User Interface (GUI) software which allows the

EM2130 to be controlled via a USB interface to a host computer.

The user can view the power supply’s status, I/O voltages, output current and fault conditions detected by

the device, program settings to the converter, and issue PMBus commands using the GUI. Most of the

parameters (for example, VOUT turn on/off time, protection and fault limits) can be configured and

adjusted within the GUI environment. These parameters can also be configured outside of the GUI

environment using the relevant PMBus™ commands.

The GUI also allows the user to easily create, modify, test and save a configuration file which may then be

used to permanently burn the configuration into NVM within a production test environment.

ALTERNATIVE OUTPUT VOLTAGE CONTROL METHODS

In the default configuration, output voltage selection is determined at power-up by the pin-strapped

resistor RVSET. This functionality can be disabled using the PMBus command MFR_PIN_CONFIG. When

RVSET is disabled, the output voltage will be determined by the nominal output voltage setting in the user

configuration. The EM2130 supports a subset of the output voltage commands outlined in the PMBus

specification. For example, the output voltage can be dynamically changed using the PMBus command

VOUT_COMMAND. When the output is being changed by the PMBus command, power good (POK) remains

at a logic high.

POWER SEQUENCING AND THE CONTROL (CTRL) PIN

Three different configuration options are supported to enable the output voltage. The device can be

configured to turn on after an OPERATION_ON command, via the assertion of the CTRL pin or a

combination of both per the PMBus convention. The EM2130 supports power sequencing features

including programmable ramp up/down and delays. The typical sequence of events is shown in Figure 6

and follows the PMBus standard. The individual timing values shown in Figure 6 and Figure 7 can be

configured using the appropriate configuration setting in Intel Digital Power Configurator GUI.

PRE-BIASED START-UP AND SOFT-STOP

In systems with complex power architectures, there may be leakage paths from one supply domain, which

charge capacitors in another supply domain leading to a pre-biased condition on one or more power

supplies. This condition is not ideal and can be avoided through careful design, but is generally not harmful.

Attempting to discharge the pre-bias is not advised as it may force high current though the leakage path.

The EM2130 includes features to enable and disable into pre-biased output capacitors.

If the output capacitors are pre-biased when the EM2130 is enabled, start-up logic in the EM2130 ensures

that the output does not pull down the pre-biased voltage and the t_{ON_RISE}timing is preserved. Closed-loop

stability is ensured during the entire start-up sequence under all pre-bias conditions.

The EM2130 also supports pre-biased off, in which the output voltage ramp down to a user-defined level

(V_{OFF_nom}) rather than to zero. After receiving the disable command, via PMBus command or the CTRL pin,

the EM2130 ramps down the output voltage to the predefined value. Once the value is reached, the output

driver goes into a tristate mode to avoid excessive currents through the leakage path.

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Figure 8: Power Sequencing With Non-Zero Off Voltage

VOLTAGE TRACKING

The EM2130 can control the output voltage based on the external voltage applied to the VTRACK pin, thus

allowing sequencing of the output voltage from an external source. Pre-bias situations are also supported.

The VTRACK pin voltage is a single-ended input referenced to analog ground. Tracking mode is disabled

by default, but it can be enabled using the GUI software or via the manufacturer-specific PMBus command,

MFR_FEATURES_CTRL (see Table 16).

If VTRACK is not intended to be used, tie the VTRACK pin low or leave it floating.

VTRACK

VOUT

Pre-bias

Figure 9: Power Sequencing Using VTRACK With Bias Voltage On VOUT

The set point voltage for the EM2130 is defined by the lower value of the V_OUTsetting or an external voltage

applied to the VTRACK pin. If the VTRACK voltage rises above the V_OUTset point voltage, then the final

output voltage will be limited by the V_OUTsetting. If the tracking feature is enabled, but the VTRACK pin is

tied low or floating, then the output will never start as the VTRACK pin input is always the lower value and

will always be in control. Conversely, if tracking is enabled, but VTRACK is tied high, the output will start

but will follow the V_OUTset point, not the VTRACK pin.

If tracking is used for sequencing, it is recommended that the VTRACK signal be kept greater than the V_OUT

voltage. This ensures that the internal V_OUTset point is used as the final steady-state output voltage and

accuracy is not a function of the externally applied VTRACK voltage. The tracking function will override a

programmed pre-bias off level (V_{OFF_nom}).

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VFB

VTRACK

DAC

Set-Point

(Defined by lower input value)

Figure 10: VTRACK Circuitry

The following figures demonstrate ratio-metric and simultaneous sequencing of the output voltage, which

can be accomplished by applying an appropriate external voltage on the VTRACK pin. When using the

VTRACK feature, the sequencing will be ratio-metric as shown in Figure 12 if an external resistor network

is used at the VTRACK pin as shown Figure 10. If no external resistors are used, the output sequence is

simultaneous as shown in Figure 13.

In the event that a feedback divider is not required, (such as when VOUT ≤ 1.4V) but the tracking voltage

applied to VTRACK is greater than 1.4V, then a 2kΩ resistor is required in series with the VTRACK pin to

minimize leakage current as shown in Figure 11.

In applications where a voltage divider is required on the output voltage, a voltage divider consisting of the

same values is also required for the VTRACK pin.

Figure 11: VTRACK Sense Circuitry with Resistor Divider

Figure 12: VTRACK Sense Circuitry (Input > 1.4V)

VTRACK

VOUT

Figure 13: Ratiometric Sequencing Using VTRACK

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VTRACK

VOUT

Figure 14: Simultaneous Sequencing Using VTRACK

CLOCK SYNCHRONIZATION

The EM2130’s PWM synchronization feature allows the user to synchronize the switching frequency of

multiple devices. The SYNC pin can be configured as an input or an output.

When the SYNC pin is configured as input clock, the external clock need to be available before the EM2130

is enabled. The EM2130 will only lock to the external clock within 1ms after the device is enabled. After 1

ms the device can be re-synchronized to the external clock signal by toggling VOUT or via PMBus

MFR_RESYNC command.

When the SYNC pin is configured as an output clock (sync out), there is no requirement to provide an

external clock to allow synchronization.

The EM2130 SYNC functionality maybe configured as an input or an output using Intel’s GUI software or

via the manufacturer-specific PMBus command, MFR_PIN_CONFIG. The default configuration for

synchronization control is OFF.

TEMPERATURE AND OUTPUT CURRENT MEASUREMENT

The EM2130 temperature sense block provides the device and the system with precision temperature

information over a wide range of temperatures (-40°C to +150°C). The temperature sense block measures

the digital controller temperature, which will be slightly lower than the powertrain junction temperature.

The EM2130 monitors output current by real-time, temperature compensated DCR current sensing across

the inductor. This real-time current waveform is then digitally filtered and averaged for accurate telemetry,

fault warning, and management.

Factory calibration has been performed for every EM2130 device to improve measurement accuracy over

the full output current range. This allows the EM2130 to correct for DCR manufacturing variations.

For over-current protection, an unfiltered ADC is used in order to minimize delays in protecting the device.

Because this measurement is unfiltered, the accuracy of the protection threshold is less than that of the

average current reading.

PROTECTION AND FAULT RESPONSE

The EM2130 monitors various signals during operation in order to detect fault conditions. Measured and

filtered signals are compared to a configurable set of warnings and fault thresholds. In typical usage, a

warning sets a status flag, but does not trigger a response; whereas a fault sets a status flag and generates

a response. The assertion of the SMBALERT signal can be configured to individual application

requirements.

The EM2130 supports a number of different response types depending on the fault detected.

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In the default configuration, the EM2130 responds to an over temperature event by ramping down V_OUTin

a controlled manner at a slew rate defined by the T_{OFF_FALL}value. This response type is termed “Soft-Off”.

The final state of the output signals depends on the value selected for V_OFFnom

For all other faults the EM2130 will respond by immediately turning off both the top-side MOSFET and

low-side MOSFET. This response type is termed “High-Impedance”.

For each fault response, a delay and a retry setting can be configured. If the delay-to-fault value is set to

non-zero, the EM2130 will not respond to a fault immediately. Instead it will delay the response by the

configured value and then reassesses the signal. If the fault remains present during the delay time, the

appropriate response will be triggered. If the fault is no longer present, the previous detection will be

disregarded.

If the delay-to-retry value is set to non-zero, the EM2130 will not attempt to restart immediately after fault

detection. Instead it will delay the restart by the configured value. If the fault is still present when

attempting to restart, the appropriate response will be triggered. If the fault is no longer present, the

previous detection will be disregarded. If the delay-to-fault is a non-zero value, then the delay-to-retry

value will be a factor of 100 times greater than the delay-to-fault value.

The retry setting, i.e. the number of EM2130 restarts after a fault event, can be configured. This number

can be between zero and six. A setting of seven represents infinite retry operation. This setting is commonly

known as “Hiccup Mode.”

Watchdog Timer

General house-keeping operations are managed by an internal microcontroller (MCU). To ensure reliable

MCU operation in all environments a watchdog timer has been incorporated. The purpose of the

watchdog timer is to reset the MCU as a last resort in the unlikely event of it entering an unknown state.

In the exceptional event of a reset the MCU will shut down the controller into a safe state and will then

reload its memory, restarting the controller and output into its known good default operating condition.

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PMBus Functionality

INTRODUCTION

The EM2130 supports the PMBus protocol (version 1.2) to enable the use of configuration, monitoring, and

fault management features during run-time.

The PMBus host controller is connected to the EM2130 via the PMBus pins (SDA, SCL). A dedicated

SMBALERT pin is provided to notify the host that new status information is present.

The EM2130 supports packet correction (PEC) according to the PMBus™ specification.

The EM2130 supports clock stretching according to the SMBus specification.

The EM2130 communications utilizes clock stretching as required and this requires the PMBus master to

support clock stretching.The EM2130 supports more than 60 PMBus commands in addition to several

manufacturer specific commands related to output voltage, faults, telemetry, and more.

The EM2130 provides a PMBus set of synchronous communication lines, with serial clock input (SCL), serial

data I/O (SDA), and serial alarm output (SALRT) pins.

The communication lines provide 3.6V-tolerance, 1.8V I/O compatibility and open-drain outputs (SDA, SCL

and SALRT). The communication lines require external pull-up resistors; typical applications require pull-

up resistors on each end of the communication lines (typically values of 10 kΩ each), connected to VDD33

or an alternative termination voltage. Please refer to the PMBus specification (www.pmbus.org) for full

details.

The EM2130 provides configurable behavior for the SALRT pin to allow users to determine which fault or

warning conditions to communicate over the SALRT line. The default behavior of the controller ensures

that any fault or warning results in the EM2130 SALRT pin going low; the alert behavior is enabled for all

faults and warnings. You can deselect any of the faults or warnings so when one of these conditions occur,

the SALRT pin is not pulled low.

The EM2130 provides a PMBus compliant power conversion control signal through input CTRL. You can

configure input CTRL through the standard PMBus command ON_OFF_CONFIG.

By default configuration, the CTRL pin must be pulled high to enable operation and the PMBus command

OPERATION is ignored. You can override this function with the ON_OFF_CONFIG PMBus command.

Remote measurement and reporting of telemetry information at the power supply level provides feedback

on key parameters such as voltages, current levels, temperature, and energy, and allows reporting of

information such as faults and warning flags. With this information, data is collected and analyzed while

the power supply is in development, such as in the qualification or verification phases, or in the field, and

system level interaction such as power capping is implemented. Several telemetry parameters are

supported by standard PMBus commands.

The EM2130P supports PMBus output current telemetry through the READ_IOUT command and reports

the low-pass filtered, or DC, output current.

The standard PMBus command READ_VOUT supports output voltage telemetry.

The standard PMBus command READ_VIN supports input voltage telemetry.

The EM2130 supports temperature telemetry and reporting through standardized PMBus commands.

READ_TEMPERATURE_2 is mapped to the controller die temperature.

The standard PMBus command READ_FREQUENCY supports switching frequency monitoring. This

command returns the scaled frequency of the PWM output in kHz.

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The EM2130 supports the LINEAR data format according to the PMBus specification. Note that in

accordance with the PMBus specification, all commands related to the output voltage are subject to the

VOUT_MODE settings.

A detailed description of the supported PMBus commands supported by the EM2130 can be found in

EM21xx Application Note – PMBus Commands Guide.

TIMING AND BUS SPECIFICATION

t_HIGH

t_LOW

t_R

t_F

SCL

t_BUF

t_HD:DAT

t_SU:STA

t_SU:STO

t_HD:STA

SDA

t_SU:DAT

Figure 15: PMBus Timing Diagram

Table 15: EM2130 PMBus Parameters

Parameter

Symbol

f_SMB

Conditions

Min

Typ

100

Max

400

Units

PMBus operation frequency

kHz

Bus free time between start and

stop

t_BUF

1.3

μs

Hold time after start condition

Repeat start condition setup time

Stop condition setup time

Data hold time

t_HD:STA

t_SU:STA

t_SU:STO

t_HD:DAT

t_SU:DAT

t_TIMEOUT

t_LOW

0.6

μs

0.6

300

150*

Data setup time

Clock low time-out

Clock low period

1.3

0.6

Clock high period

t_HIGH

Cumulative clock low extend time

Clock or data fall time

Clock or data rise time

t_LOW:SEXT

t_F

300

t_R

Note: The EM2130 fully complies with PMBus 1.2 specifications for operation up to 100kHz on SCL. The

EM2130 may be operated at frequencies up to at least 400kHz on SCL if t_SU:DATis maintained greater than

150ns.

ADDRESS SELECTION VIA EXTERNAL RESISTORS

The PMBus protocol uses a 7-bit device address to identify different devices connected to the bus. This

address can be selected via external resistors connected to the ADDRx pins.

The resistor values are sensed using the internal ADC during the initialization phase and the appropriate

PMBus address is selected. Note that the respective circuitry is only active during the initialization phase;

hence no DC voltage can be measured at the pins. The supported PMBus addresses and the values of the

respective required resistors are listed in Table 15.

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Table 16: Supported Resistor Values For PMBus Address Selection

Address ADDR1

ADDR0

Address

(hex)

ADDR1

ADDR0

Address

(hex)

ADDR1

ADDR0

(hex)

0x40

0x01*

0x02*

0x03*

0x04*

0x05*

0x06*

0x07*

0x08*

0x09

0x0A

0x0B

0x0C*

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37*

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

1.2 k

1.8 k

2.7 k

12 k

15 k

18 k

22 k

27 k

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61*

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78*

0x79*

3.9 k

4.7 k

5.6 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

12 k

15 k

18 k

22 k

680

1.2 k

1.8 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

680

1.2 k

1.8 k

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Address ADDR1

ADDR0

Address

(hex)

ADDR1

ADDR0

Address

(hex)

ADDR1

ADDR0

(hex)

0x24

0x25

0x26

0x27

0x28*

0x29

0x2A

1.2 k

2.7 k

3.9 k

4.7 k

5.6 k

6.8 k

8.2 k

10 k

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

2.7 k

3.9 k

27 k

0x7A*

0x7B*

0x7C*

0x7D*

0x7E*

0x7F*

5.6 k

10 k

12 k

15 k

18 k

22 k

27 k

680

1.2 k

1.8 k

2.7 k

3.9 k

Note 2: The gray-highlighted addresses with an asterick are reserved by the SMBus specification.

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PMBUS COMMANDS

A detailed description of the PMBus commands supported by the EM2130 can be found in a separate

document - EM2130 PMBus Commands Guide. Below, Table 16 lists of all supported PMBus commands.

Table 17: List Of Supported PMBus Commands

Command

PMBus Parameter

Description

Code

01_HEX

02_HEX

OPERATION

ON_OFF_CONFIG

On/off command

On/off configuration

03_HEX

10_HEX

11_HEX

12_HEX

13_HEX

14_HEX

20_HEX

21_HEX

22_HEX

23_HEX

25_HEX

26_HEX

29_HEX

CLEAR_FAULTS

Clear status information

WRITE_PROTECT

Protect against changes

STORE_DEFAULT_ALL

RESTORE_DEFAULT_ALL

STORE_DEFAULT_CODE

RESTORE_DEFAULT_CODE

VOUT_MODE (Note 3)

VOUT_COMMAND

Copy entire memory into OTP

Copy entire memory from OTP

Copy single parameter into OTP

Copy single parameter from OTP

Exponent of the VOUT_COMMAND value

Set output voltage

VOUT_TRIM

Apply a fixed offset voltage

Sets maximum value

VOUT_CAL_OFFSET

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

VOUT_SCALE_LOOP

Sets minimum value

Scalar for output voltage divider

Scalar for read-back with output voltage

divider

2A_HEX

VOUT_SCALE_MONITOR

35_HEX

36_HEX

40_HEX

41_HEX

42_HEX

43_HEX

44_HEX

45_HEX

55_HEX

56_HEX

57_HEX

58_HEX

59_HEX

5A_HEX

VIN_ON

Input voltage turn on threshold

Input voltage turn off threshold

Over-voltage fault limit

VIN_OFF

VOUT_OV_FAULT_LIMIT

VOUT_OV_FAULT_RESPONSE

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

VOUT_UV_FAULT_RESPONSE

VIN_OV_FAULT_LIMIT

VIN_OV_FAULT_RESPONSE

VIN_OV_WARN_LIMIT

VIN_UV_WARN_LIMIT

VIN_UV_FAULT_LIMIT

VIN_UV_FAULT_RESPONSE

Over-voltage fault response

Over-voltage warning level

Under-voltage warning level

Under-voltage fault level

Under-voltage fault response

Over-voltage fault limit

Over-voltage fault response

Over-voltage warning level

Under-voltage warning level

Under-voltage fault level

Under-voltage fault response

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Command

PMBus Parameter

Code

Description

5E_HEX

5F_HEX

60_HEX

61_HEX

62_HEX

64_HEX

65_HEX

66_HEX

78_HEX

79_HEX

7A_HEX

7B_HEX

7C_HEX

7E_HEX

80_HEX

88_HEX

8B_HEX

8C_HEX

8E_HEX

95_HEX

96_HEX

98_HEX

99_HEX

9A_HEX

9B_HEX

9E_HEX

A0_HEX

A4_HEX

D0_HEX

D1_HEX

D2_HEX

D3_HEX

DA_HEX

DB_HEX

POWER_GOOD_ON

POWER_GOOD_OFF

TON_DELAY

Power good on threshold

Power good off threshold

Turn-on delay

TON_RISE

Turn-on rise time

TON_MAX_FAULT_LIMIT

TOFF_DELAY

Turn-on maximum fault time

Turn-off delay

TOFF_FALL

Turn-off fall time

TOFF_MAX_WARN_LIMIT

STATUS_BYTE

Turn-off maximum warning time

Unit status byte

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

Unit status word

Output voltage status

Output current status

Input status

STATUS_INPUT

STATUS_CML

Communication and memory status

Manufacturer specific status

Reads input voltage

STATUS_MFR_SPECIFIC

READ_VIN

READ_VOUT

Reads output voltage

Reads output current

Reads temperature

READ_IOUT

READ_TEMPERATURE

READ_FREQUENCY

READ_POUT

Reads switching frequency

Reads output power

PMBUS™_REVISION

MFR_ID

PMBus™ revision

Manufacturer ID

MFR_MODEL

Manufacturer model identifier

Manufacturer product revision

Serial number

MFR_REVISION

MFR_SERIAL

MFR_VIN_MIN

Minimum input voltage

Minimum output voltage

Write word (once) / Read word – 2 bytes

Write word / read word – 12 bytes

Reads VCC voltage

MFR_VOUT_MIN

MFR_SPECIFIC_00

MFR_SPECIFIC_01

MFR_READ_VCC

MFR_RESYNC

Active RESYNC

MFR_RTUNE_CONFIG

MFR_VOUT_MARGIN_HIGH

Gets/sets RTUNE settings

Gets/sets Margin High

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Command

PMBus Parameter

Code

Description

DC_HEX

MFR_VOUT_MARGIN_LOW

Gets/sets Margin Low

Returns index derived from resistor detected

on RTUNE pin

DD_HEX

MFR_RTUNE_INDEX

Returns index derived from resistor detected

on RVSET pin

DE_HEX

MFR_RVSET_INDEX

E0_HEX

E2_HEX

E3_HEX

E5_HEX

E6_HEX

MFR_VOUT_OFF

MFR_OT_FAULT_LIMIT

MFR_OT_WARN_LIMIT

MFR_OT_FAULT_RESPONSE

MFR_TEMP_ON

Sets the target turn-off voltage

Over-temperature fault level

Over-temperature warning level

Over-temperature fault response

Over-temperature on level

Enable/disable – RTUNE, RVSET, VTRACK and

SYNC

E7_HEX

E9_HEX

EA_HEX

MFR_PIN_CONFIG

MFR_STORE_CONFIG_ADDR_READ

Reads a configuration value

MFR_STORE_PARAMS_REMAININ

Number of STORE_DEFAULT_ALL commands

remaining

MFR_STORE_CONFIGS_REMAININ

EB_HEX

EC_HEX

ED_HEX

EE_HEX

Number of full configurations remaining

Commence programming of OTP

Program a configuration value

MFR_STORE_CONFIG_BEGIN

MFR_STORE_CONFIG_ADDR_DAT

MFR_STORE_CONFIG_END

Completed programming of OTP

Note 3: VOUT_ MODE is read only for the EM2130

Lo ad

Decoupling

EM2130

LOCAL CIN

LOCAL COUT

PVIN

VIN

VO UT

R1VIN

R2VIN

4X22µF

1206

Outpu t V oltage

Sense Point

VINSEN

PV CC

R1DIV

R2DIV

VSENP

VSENN

CTRL

VCC

VCCSEN

SY NC

VTRACK

VDD33

ADDR0

ADDR1

RTUN E

RV S ET

POK

SALERT

SDA

SCL

DGND AG ND PG ND

Figure 16: Recommended Application Circuit

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Layout Recommendations

Recommendation 1: It is highly recommended to use separate nets for AGND and PGND and connecting

them through a 0Ω resistor or a short. This method helps with ground management and prevents the noise

from the Power Ground disturbing the more sensitive Analog (“Signal”) Ground.

Recommendation 2: It is good practice to minimize the PGND loop. Whenever possible the input and

output loops should close to the same point, which is the ground of the EM2130 module. Module

decoupling ceramic capacitors are to be placed as close as possible to the module in order to contain the

switching noise in the smallest possible loops and to improve PVIN decoupling by minimizing the series

parasitic inductance of the PVIN traces. For achieving this goal, it helps to place decoupling capacitors on

the same side as the module since VIAs are generally more inductive, thus reducing the effectiveness of

the decoupling. Of course, bulk and load high frequency decoupling should be placed closer to the load.

Figure 17: Top Layer Layout With Critical Components Only

Recommendation 3: It is good practice to place the other small components needed by the EM2130 on

the opposite side of the board, in order to avoid cutting the power planes on the module side. Since the

EM2130 heat is evacuated mostly through the PCB, this will also help with heat dissipation; wide copper

planes under the module can also help with cooling. The PVIN copper plane should not be neglected as it

helps spread the heat from the high side FET.

Recommendation 4: It is recommended that at least below the EM2130 module, the next layers to the

surface (2 and n-1) be solid ground planes, which provides shielding and lower the ground impedance at

the module level. AGND should be also routed as a copper plane, in order to reduce the ground impedance

and reduce noise injection.

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Figure 18: VIAs in The Power Pads

Recommendation 5: In order to better spread the current and the heat through the inner layers, arrays of

VIAs should be placed in the power pads. 10mils diameter is a good size for the plated in-pad VIAs. It is

critical that through VIAs should not be placed by any means elsewhere under the module; the non-pad

area around AGND is VIA keep out area.

Recommendation 6: All other signal and LDO decoupling capacitors should be placed as close as possible

to the terminal they are decoupling, while the AGND connection should be done through VIAs to the AGND

plane.

Figure 19: Backside Decoupling

All Signal Decoupling Go To The Bottom AGND Plane And Get Connected To The EM2130 Module

AGND Through The AGND In-PAD VIAs (Again, No Other VIAs Are Allowed In That Area)

Recommendation 7: Figure 20 also shows the 0Ω resistor that connects AGND to PGND. The

recommended connecting point, as shown, is to a quiet PGND  the output capacitors PGND.

Recommendation 8: Differential remote sense should be routed as much as possible as a differential pair,

on an inner layer, preferably shielded by a ground plane.

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Figure 20: Remote Sense Routing On An Inner Layer (Highlighted, Yellow)

Recommendation 9: If the design allows it, stitching VIAs can be used on the power planes, close to the

module in order to help with cooling. This is a thermal consideration and does not matter much for the

electrical design.

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Recommended PCB Footprint

Figure 21: Recommended PCB Footprint

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Data Sheet | Intel Enpirion Power Solutions: EM2130

30% Solder Stencil Aperture (see note below)

Figure 22: 30% Solder Stencil Aperture Dimensions

Notes:

•

The solder stencil for each pad under the device is recommended to be up to 30% of the total

pad size.

•

The aperture dimensions are based on a 4mil stencil thickness.

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Package Dimensions

Figure 23: Package Dimensions (EM2130L02 Shown)

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Tray Information

Figure 24: Tray Information 1/2

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Tray Information (Continued)

Figure 2523: Tray Information 2/2

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Data Sheet | Intel Enpirion Power Solutions: EM2130

Revision History

Rev

Date

23-Dec-16 Initial Release

Add RTune table for EM2130H

Change(s)

Delete PMBus Address Selection Without Resistors table (old table 15)

21-Feb-17

Delete old Table 12 and Figure 7, update the Output Capacitor

Recommendation section.

In pin description table, update the PVCC decoupling to “GND” instead of PGND.

10-May-17 Updated for new POK functionality.

31-May-17 Updated Package Dimension and POK description

27-Aug-17 Minor Drawing Updates

Updated POK description

10-Nov-17

Corrected some text errors

30-May-18 Updated POK description, PMBus Introduction and note on Watchdog Timer

03-Jul-18

Added the solder stencil options for 30% & 45% opening

Added information relating to SMBALERT, removed stencil option for 45%

opening

20-Mar-20

Where to Get More Information

For more information about Intel and Intel Enpirion PowerSoCs, visit https://www.altera.com/enpirion

Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and

services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to

in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

* Other marks and brands may be claimed as the property of others.

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EM2130X0XQI [INTEL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E