EP2AGX65DF25C6 [INTEL]
Field Programmable Gate Array, 60214-Cell, CMOS, PBGA572,;
| 型号： | EP2AGX65DF25C6 |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 60214-Cell, CMOS, PBGA572, 栅 可编程逻辑 |
| 文件： | 总78页 (文件大小：808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1. Device Datasheet for Arria II Devices
December 2013
AIIGX53001-4.4
AIIGX53001-4.4
This chapter describes the electrical and switching characteristics of the Arria® II
device family. The Arria II device family includes the Arria II GX and GZ devices.
Electrical characteristics include operating conditions and power consumption.
Switching characteristics include transceiver specifications, core, and periphery
performance. This chapter also describes I/O timing, including programmable I/O
element (IOE) delay and programmable output buffer delay.
f
For information regarding the densities and packages of devices in the Arria II device
family, refer to Overview for the Arria II Device Family chapter.
This chapter contains the following sections:
■
■
■
“Electrical Characteristics” on page 1–1
“Transceiver Performance Specifications” on page 1–21
“Glossary” on page 1–74
Electrical Characteristics
The following sections describe the electrical characteristics.
Operating Conditions
Arria II devices are rated according to a set of defined parameters. To maintain the
highest possible performance and reliability of Arria II devices, you must consider the
operating requirements described in this chapter.
Arria II devices are offered in both commercial and industrial grades. Arria II GX
devices are offered in –4 (fastest), –5, and –6 (slowest) commercial speed grades and
–3 and –5 industrial speed grades. Arria II GZ devices are offered in –3 and –4 speed
grades for both commercial and industrial grades.
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with the "C" prefix and industrial with the “I” prefix.
Commercial devices are indicated as C4, C5, and C6 speed grade, and the industrial
devices are indicated as I3 and I5.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Arria II
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied under these conditions. Table 1–1 lists the
absolute maximum ratings for Arria II GX devices. Table 1–2 lists the absolute
maximum ratings for Arria II GZ devices.
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013
Subscribe
1–2
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
c
Conditions beyond those listed in Table 1–1 and Table 1–2 may cause permanent
damage to the device. Additionally, device operation at the absolute maximum
ratings for extended periods of time may have adverse effects on the device.
Table 1–1 lists the absolute maximum ratings for Arria II GX devices.
Table 1–1. Absolute Maximum Ratings for Arria II GX Devices
Symbol
VCC
Description
Minimum
Maximum
Unit
Supplies power to the core, periphery, I/O registers, PCI Express®
(PIPE) (PCIe) HIP block, and transceiver PCS
–0.5
1.35
V
VCCCB
Supplies power for the configuration RAM bits
–0.5
–0.5
1.8
V
V
VCCBAT
Battery back-up power supply for design security volatile key register
3.75
Supplies power to the I/O pre-drivers, differential input buffers, and
MSEL circuitry
VCCPD
–0.5
3.75
V
VCCIO
Supplies power to the I/O banks
–0.5
–0.5
3.9
V
V
VCCD_PLL
Supplies power to the digital portions of the PLL
1.35
Supplies power to the analog portions of the PLL and device-wide
power management circuitry
VCCA_PLL
–0.5
3.75
V
VI
DC input voltage
–0.5
–25
—
4.0
40
V
mA
V
IOUT
VCCA
DC output current, per pin
Supplies power to the transceiver PMA regulator
3.75
1.21
1.8
VCCL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking
VCCH_GXB Supplies power to the transceiver PMA output (TX) buffer
—
V
—
V
TJ
Operating junction temperature
Storage temperature (no bias)
–55
–65
125
150
°C
°C
TSTG
Table 1–2 lists the absolute maximum ratings for Arria II GZ devices.
Table 1–2. Absolute Maximum Ratings for Arria II GZ Devices (Part 1 of 2)
Symbol
VCC
Description
Minimum
Maximum
Unit
Supplies power to the core, periphery, I/O registers, PCIe HIP block, and
transceiver PCS
-0.5
1.35
V
VCCCB
Power supply to the configuration RAM bits
Supplies power to the configuration pins
Auxiliary supply
-0.5
-0.5
-0.5
-0.5
1.8
V
V
V
V
VCCPGM
VCCAUX
VCCBAT
3.75
3.75
3.75
Supplies battery back-up power for design security volatile key register
Supplies power to the I/O pre-drivers, differential input buffers, and
MSEL circuitry
VCCPD
-0.5
3.75
V
VCCIO
Supplies power to the I/O banks
-0.5
-0.5
-0.5
3.9
V
V
V
VCC_CLKIN
VCCD_PLL
Supplies power to the differential clock input
Supplies power to the digital portions of the PLL
3.75
1.35
Supplies power to the analog portions of the PLL and device-wide
power management circuitry
VCCA_PLL
-0.5
3.75
V
VI
DC input voltage
-0.5
-25
4.0
40
V
IOUT
DC output current, per pin
mA
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–3
Electrical Characteristics
Table 1–2. Absolute Maximum Ratings for Arria II GZ Devices (Part 2 of 2)
Symbol
VCCA_L
Description
Supplies transceiver high voltage power (left side)
Supplies transceiver high voltage power (right side)
Supplies transceiver HIP digital power (left side)
Supplies receiver power (left side)
Minimum
-0.5
Maximum
3.75
Unit
V
V
V
V
V
V
V
VCCA_R
VCCHIP_L
VCCR_L
VCCR_R
VCCT_L
VCCT_R
-0.5
3.75
-0.5
1.35
-0.5
1.35
Supplies receiver power (right side)
-0.5
1.35
Supplies transmitter power (left side)
-0.5
1.35
Supplies transmitter power (right side)
-0.5
1.35
VCCL_GXBLn Supplies power to the transceiver PMA TX, PMA RX, and clocking (left
(1) side)
-0.5
-0.5
-0.5
-0.5
1.35
1.35
1.8
V
V
V
V
VCCL_GXBRn Supplies power to the transceiver PMA TX, PMA RX, and clocking (right
(1)
side)
VCCH_GXBLn
(1)
Supplies power to the transceiver PMA output (TX) buffer (left side)
VCCH_GXBRn
(1)
Supplies power to the transceiver PMA output (TX) buffer (right side)
1.8
TJ
Operating junction temperature
Storage temperature (no bias)
-55
-65
125
150
°C
°C
TSTG
Note to Table 1–2:
(1) n = 0, 1, or 2.
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 1–3 and
undershoot to –2.0 V for magnitude of currents less than 100 mA and periods shorter
than 20 ns.
Table 1–3 lists the Arria II GX and GZ maximum allowed input overshoot voltage and
the duration of the overshoot voltage as a percentage over the device lifetime. The
maximum allowed overshoot duration is specified as a percentage of high-time over
the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example,
a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the
device; for a device lifetime of 10 years, this amounts to 5.41/10ths of a year.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–4
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–3. Maximum Allowed Overshoot During Transitions for Arria II Devices
Overshoot Duration as % of
High Time
Symbol
Description
Condition (V)
Unit
4.0
4.05
4.1
100.000
79.330
46.270
27.030
15.800
9.240
%
%
%
%
%
%
%
%
%
%
%
%
%
4.15
4.2
4.25
4.3
VI (AC)
AC Input Voltage
5.410
4.35
4.4
3.160
1.850
4.45
4.5
1.080
0.630
4.55
4.6
0.370
0.220
Maximum Allowed I/O Operating Frequency
Table 1–4 lists the maximum allowed I/O operating frequency for Arria II GX I/Os
using the specified I/O standards to ensure device reliability.
Table 1–4. Maximum Allowed I/O Operating Frequency for Arria II GX Devices
I/O Standard
HSTL-18 and HSTL-15
I/O Frequency (MHz)
333
400
333
260
SSTL -15
SSTL-18
2.5-V LVCMOS
3.3-V and 3.0-V LVTTL
3.3-V, 3.0-V, 1.8-V, and 1.5-V LVCMOS
PCI and PCI-X
250
200
SSTL-2
1.2-V LVCMOS HSTL-12
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–5
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Arria II GX and GZ devices. All supplies are required to monotonically reach their
full-rail values without plateaus within tRAMP
.
Table 1–5 lists the recommended operating conditions for Arria II GX devices.
Table 1–5. Recommended Operating Conditions for Arria II GX Devices (Note 1) (Part 1 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum
Unit
Supplies power to the core, periphery, I/O
registers, PCIe HIP block, and transceiver
PCS
VCC
—
0.87
0.90
0.93
V
Supplies power to the configuration RAM
bits
VCCCB
—
—
1.425
1.2
1.50
—
1.575
3.3
V
V
VCCBAT
(2)
Battery back-up power supply for design
security volatile key registers
—
—
—
—
—
—
—
—
—
3.135
2.85
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.2
3.465
3.15
V
V
V
V
V
V
V
V
V
Supplies power to the I/O pre-drivers,
differential input buffers, and MSEL
circuitry
VCCPD
(3)
2.375
3.135
2.85
2.625
3.465
3.15
2.375
1.71
2.625
1.89
VCCIO
Supplies power to the I/O banks (4)
1.425
1.14
1.575
1.26
Supplies power to the digital portions of the
PLL
VCCD_PLL
—
0.87
0.90
0.93
V
Supplies power to the analog portions of
VCCA_PLL the PLL and device-wide power
management circuitry
—
2.375
2.5
2.625
V
VI
DC Input voltage
Output voltage
—
—
–0.5
0
—
—
3.6
V
V
VO
VCCIO
Supplies power to the transceiver PMA
regulator
VCCA
—
—
—
2.375
1.045
1.425
2.5
1.1
1.5
2.625
1.155
1.575
V
V
V
Supplies power to the transceiver PMA TX,
PMA RX, and clocking
VCCL_GXB
VCCH_GXB
Supplies power to the transceiver PMA
output (TX) buffer
Commercial
Industrial
0
—
—
85
°C
°C
TJ
Operating junction temperature
–40
100
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–6
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–5. Recommended Operating Conditions for Arria II GX Devices (Note 1) (Part 2 of 2)
Symbol
Description
Condition
Normal POR
Fast POR
Minimum
0.05
Typical
—
Maximum
Unit
ms
100
4
tRAMP
Power Supply Ramp time
0.05
—
ms
Notes to Table 1–5:
(1) For more information about supply pin connections, refer to the Arria II Device Family Pin Connection Guidelines.
(2) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile
security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
(3) VCCPD must be 2.5-V for I/O banks with 2.5-V and lower VCCIO, 3.0-V for 3.0-V VCCIO, and 3.3-V for 3.3-V VCCIO
.
(4) VCCIO for 3C and 8C I/O banks where the configuration pins reside only supports 3.3-, 3.0-, 2.5-, or 1.8-V voltage levels.
Table 1–6 lists the recommended operating conditions for Arria II GZ devices.
Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 1 of 2)
Symbol
VCC
Description
Condition
Minimum
Typical
Maximum Unit
Core voltage and periphery circuitry power
supply
—
0.87
0.90
0.93
1.55
V
V
Supplies power for the configuration RAM
bits
VCCCB
—
1.45
1.50
VCCAUX
Auxiliary supply
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.375
2.85
2.5
3.0
2.5
3.0
2.5
1.8
1.5
1.2
3.0
2.5
1.8
2.5
0.90
2.5
2.625
3.15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.0 V) power supply
I/O buffers (2.5 V) power supply
I/O buffers (1.8 V) power supply
I/O buffers (1.5 V) power supply
I/O buffers (1.2 V) power supply
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
PLL analog voltage regulator power supply
PLL digital voltage regulator power supply
Differential clock input power supply
VCCPD (2)
2.375
2.85
2.625
3.15
2.375
1.71
2.625
1.89
VCCIO
1.425
1.14
1.575
1.26
2.85
3.15
VCCPGM
2.375
1.71
2.625
1.89
VCCA_PLL
VCCD_PLL
VCC_CLKIN
2.375
0.87
2.625
0.93
2.375
2.625
Battery back-up power supply (For design
security volatile key register)
VCCBAT (1)
—
1.2
—
3.3
V
VI
DC input voltage
—
—
—
—
—
—
—
—
—
–0.5
0
—
—
3.6
V
V
VO
Output voltage
VCCIO
VCCA_L
VCCA_R
VCCHIP_L
VCCR_L
VCCR_R
VCCT_L
VCCT_R
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Receiver power (left side)
2.85/2.375 3.0/2.5 (4) 3.15/2.625
V
0.87
1.05
1.05
1.05
1.05
0.9
1.1
1.1
1.1
1.1
0.93
1.15
1.15
1.15
1.15
V
V
V
V
V
Receiver power (right side)
Transmitter power (left side)
Transmitter power (right side)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–7
Electrical Characteristics
Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 2 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum Unit
VCCL_GXBLn
(3)
Transceiver clock power (left side)
—
1.05
1.1
1.15
1.15
V
V
VCCL_GXBRn
(3)
Transceiver clock power (right side)
—
—
—
1.05
1.1
VCCH_GXBLn
(3)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
1.33/1.425 1.4/1.5 (5)
1.575
V
VCCH_GXBRn
(3)
Commercial
Industrial
0
—
—
85
°C
°C
TJ
Operating junction temperature
Power supply ramp time
–40
100
Normal POR
(PORSEL=0)
0.05
0.05
—
—
100
4
ms
ms
tRAMP
Fast POR
(PORSEL=1)
Notes to Table 1–6:
(1) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile
security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
(2) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(3) n = 0, 1, or 2.
(4) VCCA_L/R must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR), or
both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect VCCA_L/R to either 3.0 V or 2.5 V.
(5) VCCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can connect
V
CCH_GXBL/R to either 1.4 V or 1.5 V.
(6) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
DC Characteristics
This section lists the supply current, I/O pin leakage current, on-chip termination
(OCT) accuracy and variation, input pin capacitance, internal weak pull-up and
pull-down resistance, hot socketing, and Schmitt trigger input specifications.
Supply Current
Standby current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Because these currents vary
largely with the resources used, use the Microsoft Excel-based Early Power Estimator
(EPE) to get supply current estimates for your design.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–8
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
I/O Pin Leakage Current
Table 1–7 lists the Arria II GX I/O pin leakage current specifications.
Table 1–7. I/O Pin Leakage Current for Arria II GX Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–10
–10
Typ
—
Max
10
Unit
µA
—
10
µA
Table 1–8 lists the Arria II GZ I/O pin leakage current specifications.
Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices
Symbol
II
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–20
–20
Typ
—
Max
20
Unit
µA
IOZ
—
20
µA
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–9 lists bus hold specifications for Arria II GX devices.
Table 1–9. Bus Hold Parameters for Arria II GX Devices (Note 1)
VCCIO (V)
Parameter Symbol
Cond.
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max
Min
Max
Min
Max
Min
Max Min Max Min Max
Bus-hold
low,
sustaining
current
VIN > VIL
(max.)
ISUSL
8
—
—
12
—
30
—
50
–50
—
—
—
70
–70
—
—
—
70
–70
—
—
—
µA
µA
µA
Bus-hold
high,
sustaining
current
VIN < VIL
(min.)
ISUSH
–8
—
–12
—
—
–30
—
—
Bus-hold
low,
overdrive
current
0 V < VIN <
VCCIO
IODL
125
–125
175
200
300
500
500
Bus-hold
high,
overdrive
current
0 V < VIN <
VCCIO
IODH
—
—
–175
—
–200
—
–300
1.7
—
–500
2
—
–500 µA
Bus-hold
VTRIP
—
0.3
0.9 0.375 1.125 0.68 1.07
0.7
0.8
0.8
2
V
trip point
Note to Table 1–9:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–9
Electrical Characteristics
Table 1–10 lists the bus hold specifications for Arria II GZ devices.
Table 1–10. Bus Hold Parameters for Arria II GZ Devices
VCCIO (V)
1.8
Parameter Symbol
Cond.
1.2
1.5
2.5
3.0
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold
Low
sustaining
current
VIN > VIL
(max.)
ISUSL
22.5
—
25.0
—
30.0
-30.0
—
—
50.0
—
70.0
—
µA
µA
µA
Bus-hold
High
sustaining
current
VIN < VIH
(min.)
ISUSH
-22.5
—
—
-25.0
—
—
—
-50.0
—
—
-70.0
—
—
Bus-hold
Low
overdrive
current
0V < VIN <
VCCIO
IODL
120
160
200
300
500
Bus-hold
High
overdrive
current
0V < VIN <
VCCIO
IODH
—
-120
0.95
—
-160
1.00
—
-200
1.07
—
-300
1.70
—
-500
2.00
µA
V
Bus-hold
VTRIP
—
0.45
0.50
0.68
0.70
0.80
trip point
OCT Specifications
Table 1–11 lists the Arria II GX device and differential OCT with and without
calibration accuracy.
Table 1–11. OCT With and Without Calibration Specification for Arria II GX Device I/Os (Note 1) (Part 1 of 2)
Calibration Accuracy
Symbol
25- RS
Description
Conditions (V)
Unit
Commercial
Industrial
25- series OCT
without calibration
VCCIO = 3.0, 2.5
VCCIO = 3.0, 2.5
VCCIO = 1.8
30
40
%
%
%
%
%
%
3.0, 2.5
50- RS
3.0, 2.5
50- series OCT
without calibration
30
40
40
50
50
40
50
50
50
50
25- RS
1.8
25- series OCT
without calibration
50- RS
1.8
50- series OCT
without calibration
V
CCIO = 1.8
25- RS
1.5, 1.2
25- series OCT
without calibration
V
V
CCIO = 1.5, 1.2
CCIO = 1.5, 1.2
50- RS
1.5, 1.2
50- series OCT
without calibration
25- RS
3.0, 2.5, 1.8, 1.5,
1.2
25- series OCT
with calibration
V
CCIO = 3.0, 2.5,
1.8, 1.5, 1.2
10
10
%
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–10
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–11. OCT With and Without Calibration Specification for Arria II GX Device I/Os (Note 1) (Part 2 of 2)
Calibration Accuracy
Symbol
50- RS
3.0, 2.5, 1.8, 1.5,
1.2
Description
Conditions (V)
Unit
%
Commercial
Industrial
50- series OCT
with calibration
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
10
10
100- differential
OCT without
calibration
100- RD
2.5
VCCIO = 2.5
30
30
%
Note to Table 1–11:
(1) OCT with calibration accuracy is valid at the time of calibration only.
Table 1–12 lists the OCT termination calibration accuracy specifications for
Arria II GZ devices.
Table 1–12. OCT with Calibration Accuracy Specifications for Arria II GZ Devices (Note 1)
Calibration Accuracy
Symbol
25- RS
3.0, 2.5, 1.8, 1.5,
1.2 (2)
Description
Conditions (V)
Unit
C2
C3,I3
C4,I4
25- series OCT
with calibration
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
8
8
8
%
50- RS
3.0, 2.5, 1.8, 1.5,
1.2
50-internal series
OCT with calibration
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
8
8
8
%
%
50- RT
2.5, 1.8, 1.5, 1.2
50- internal parallel
OCT with calibration
VCCIO = 2.5, 1.8,
1.5, 1.2
10
10
10
20- , 40- and
60- RS expanded
range for internal
series OCT with
calibration
20- , 40- , and
60- RS
3.0, 2.5, 1.8, 1.5,
1.2 (3)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
10
10
10
10
10
10
%
%
25- RS_left_shift
internal left shift
series OCT with
calibration
25- RS_left_shif
t
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
3.0, 2.5, 1.8, 1.5,
1.2
Notes to Table 1–12:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25- RS is not supported for 1.5 V and 1.2 V in Row I/O.
(3) 20- RS is not supported for 1.5 V and 1.2 V in Row I/O.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–11
Electrical Characteristics
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change.
Table 1–13 lists the Arria II GZ OCT without calibration resistance tolerance to PVT
changes.
Table 1–13. OCT Without Calibration Resistance Tolerance Specifications for Arria II GZ Devices
Resistance Tolerance
Symbol
Description
Conditions (V)
VCCIO = 3.0, 2.5
VCCIO = 1.8, 1.5
Unit
%
C3,I3
C4,I4
25-internal series
OCT without
25- RS
3.0 and 2.5
40
40
calibration
25- internal series
OCT without
25- RS
1.8 and 1.5
40
50
40
40
40
50
40
40
%
calibration
25-internal series
OCT without
25- RS
1.2
V
CCIO = 1.2
%
calibration
50- internal series
OCT without
50- RS
3.0 and 2.5
VCCIO = 3.0, 2.5
VCCIO = 1.8, 1.5
%
calibration
50-internal series
OCT without
50- RS
1.8 and 1.5
%
calibration
50-internal series
OCT without
50- RS
1.2
V
V
CCIO = 1.2
CCIO = 2.5
50
25
50
25
%
%
calibration
100- RD
2.5
100-internal
differential OCT
OCT calibration is automatically performed at power up for OCT-enabled I/Os.
When voltage and temperature conditions change after calibration, the resistance may
change. Use Equation 1–1 and Table 1–14 to determine the OCT variation when
voltage and temperature vary after power-up calibration for Arria II GX and GZ
devices.
Equation 1–1. OCT Variation (Note 1)
dR
dT
dR
dV
------
-------
V
ROCT = R
1 +
T
SCAL
Notes to Equation 1–1:
(1) ROCT value calculated from Equation 1–1shows the range of OCT resistance with the variation of temperature and
VCCIO
.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–12
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Use the following with Equation 1–1:
■
■
■
■
■
RSCAL is the OCT resistance value at power up.
T is the variation of temperature with respect to the temperature at power up.
V is the variation of voltage with respect to the VCCIO at power up.
dR/dT is the percentage change of RSCAL with temperature.
dR/dV is the percentage change of RSCAL with voltage.
Table 1–14 lists the OCT variation with temperature and voltage after power-up
calibration for Arria II GX devices.
Table 1–14. OCT Variation after Power-up Calibration for Arria II GX Devices
Nominal Voltage VCCIO (V)
dR/dT (%/°C)
0.262
dR/dV (%/mV)
0.035
3.0
2.5
1.8
1.5
1.2
0.234
0.039
0.219
0.086
0.199
0.136
0.161
0.288
Table 1–15 lists the OCT variation with temperature and voltage after power-up
calibration for Arria II GZ devices.
Table 1–15. OCT Variation after Power-Up Calibration for Arria II GZ Devices (Note 1)
Nominal Voltage, VCCIO (V)
dR/dT (%/°C)
0.189
dR/dV (%/mV)
0.0297
3.0
2.5
0.208
0.0344
1.8
0.266
0.0499
1.5
1.2
0.273
0.0744
0.317
0.1241
Note to Table 1–15:
(1) Valid for VCCIO range of 5% and temperature range of 0° to 85°C.
Pin Capacitance
Table 1–16 lists the pin capacitance for Arria II GX devices.
Table 1–16. Pin Capacitance for Arria II GX Devices
Symbol
Description
Typical
Unit
Input capacitance on I/O pins, dual-purpose pins (differential I/O, clock,
Rup, Rdn), and dedicated clock input pins
CIO
7
pF
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–13
Electrical Characteristics
Table 1–17 lists the pin capacitance for Arria II GZ devices.
Table 1–17. Pin Capacitance for Arria II GZ Devices
Symbol
Description
Typical
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
4
4
4
4
5
pF
pF
pF
pF
pF
CIOLR
Input capacitance on the left and right I/O pins
CCLKTB
CCLKLR
COUTFB
Input capacitance on the top and bottom non-dedicated clock input pins
Input capacitance on the left and right non-dedicated clock input pins
Input capacitance on the dual-purpose clock output and feedback pins
C
CLK1, CCLK3, CCLK8
,
Input capacitance for dedicated clock input pins
2
pF
and CCLK10
Internal Weak Pull-Up and Weak Pull-Down Resistors
Table 1–18 lists the weak pull-up and pull-down resistor values for Arria II GX
devices.
Table 1–18. Internal Weak Pull-up and Weak Pull-Down Resistors for Arria II GX Devices (Note 1)
Symbol
Description
Conditions
Min
7
Typ
25
28
35
57
82
143
19
22
25
35
50
Max
41
Unit
k
k
k
k
k
k
k
k
k
k
k
VCCIO = 3.3 V 5% (2)
V
V
V
V
V
CCIO = 3.0 V 5% (2)
CCIO = 2.5 V 5% (2)
CCIO = 1.8 V 5% (2)
CCIO = 1.5 V 5% (2)
CCIO = 1.2 V 5% (2)
7
47
Value of I/O pin pull-up resistor
before and during configuration,
as well as user mode if the
programmable pull-up resistor
option is enabled.
8
61
RPU
10
13
19
6
108
163
351
29
VCCIO = 3.3 V 5%
V
V
V
V
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
CCIO = 1.8 V 5%
CCIO = 1.5 V 5%
6
32
Value of TCK pin pull-down
resistor
RPD
6
42
7
70
8
112
Notes to Table 1–18:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for
JTAG TCK
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–14
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–19 lists the weak pull-up resistor values for Arria II GZ devices.
Table 1–19. Internal Weak Pull-Up Resistor for Arria II GZ Devices (Note 1), (2)
Symbol
Description
Conditions
Min
—
—
—
—
—
Typ
25
25
25
25
25
Max
—
Unit
k
k
k
k
k
VCCIO = 3.0 V 5% (3)
Value of the I/O pin pull-up
resistor before and during
configuration, as well as user
mode if the programmable
pull-up resistor option is enabled.
V
V
CCIO = 2.5 V 5% (3)
CCIO = 1.8 V 5% (3)
—
RPU
—
VCCIO = 1.5 V 5% (3)
CCIO = 1.2 V 5% (3)
—
V
—
Notes to Table 1–19:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
Hot Socketing
Table 1–20 lists the hot-socketing specification for Arria II GX and GZ devices.
Table 1–20. Hot Socketing Specifications for Arria II Devices
Symbol
IIIOPIN(DC)
Description
DC current per I/O pin
Maximum
300 A
IIOPIN(AC)
AC current per I/O pin
8 mA (1)
100 mA
50 mA
IXCVRTX(DC)
DC current per transceiver TX pin
DC current per transceiver RX pin
IXCVRRX(DC)
Note to Table 1–20:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which “C” is I/O pin
capacitance and “dv/dt” is slew rate.
Schmitt Trigger Input
The Arria II GX device supports Schmitt trigger input on the TDI
, TMS, TCK, nSTATUS,
nCONFIG, nCE,
CONF_DONE, and DCLKpins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
slow edge rates.
Table 1–21 lists the hysteresis specifications across the supported VCCIO range for
Schmitt trigger inputs in Arria II GX devices.
Table 1–21. Schmitt Trigger Input Hysteresis Specifications for Arria II GX Devices
Symbol
Description
Condition (V)
Minimum
220
Unit
mV
mV
mV
mV
V
V
CCIO = 3.3
CCIO = 2.5
180
VSchmitt
Hysteresis for Schmitt trigger input
VCCIO = 1.8
CCIO = 1.5
110
V
70
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–15
Electrical Characteristics
I/O Standard Specifications
Table 1–22 through Table 1–35 list input voltage (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by the Arria II device family. They also show the Arria II device family I/O
standard specifications. VOL and VOH values are valid at the corresponding IOH and
I
OL, respectively.
1
For an explanation of terms used in Table 1–22 through Table 1–35, refer to “Glossary”
on page 1–74.
Table 1–22 lists the single-ended I/O standards for Arria II GX devices.
Table 1–22. Single-Ended I/O Standards for Arria II GX Devices
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
VOH (V)
IOL
IOH
I/O Standard
(mA)
(mA)
Min
Typ
3.3
3.3
Max
3.465
3.465
Min
–0.3
–0.3
Min
1.7
1.7
Max
3.6
Max
0.45
0.2
Min
2.4
3.3 V LVTTL
3.135
0.8
0.8
4
2
–4
–2
3.3 V LVCMOS 3.135
3.6
VCCIO -0.2
VCCIO
0.3
+
+
+
+
+
+
+
+
3.0 V LVTTL
2.85
2.85
3
3
3.15
3.15
2.625
1.89
1.575
1.26
3.15
3.15
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
—
0.8
0.8
0.7
1.7
1.7
1.7
0.45
0.2
2.4
VCCIO - 0.2
2
4
0.1
1
–4
–0.1
–1
VCCIO
0.3
3.0 V LVCMOS
VCCIO
0.3
2.5 V LVCMOS 2.375
1.8 V LVCMOS 1.71
1.5 V LVCMOS 1.425
2.5
1.8
1.5
1.2
3
0.4
0.35 ×
VCCIO
0.65 × VCCIO
VCCIO 0.3
VCCIO
0.45
-
0.45
2
–2
0.35 ×
VCCIO
0.65 × VCCIO
VCCIO 0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2
–2
0.35 ×
VCCIO
0.65 × VCCIO
0.25 ×
VCCIO
0.75 ×
VCCIO
1.2 V LVCMOS
3.0-V PCI
1.14
2.85
2.85
2
–2
VCCIO
0.3
0.3 ×
VCCIO
0.5 ×
VCCIO
VCCIO
0.3
0.1 ×
VCCIO
0.9 × VCCIO
0.9 × VCCIO
1.5
1.5
–0.5
–0.5
0.35 ×
VCCIO
0.5 ×
VCCIO
VCCIO
0.3
0.1 ×
VCCIO
3.0-V PCI-X
3
—
Table 1–23 lists the single-ended I/O standards for Arria II GZ devices.
Table 1–23. Single-Ended I/O Standards for Arria II GZ Devices (Part 1 of 2)
V
CCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
VOH (V)
IOL
IOH
I/O Standard
(mA)
(mA)
Min
2.85
2.85
2.375
Typ
3
Max
3.15
Min
-0.3
-0.3
-0.3
Min
1.7
1.7
1.7
Max
3.6
3.6
3.6
Max
0.4
0.2
0.4
Min
2.4
LVTTL
LVCMOS
2.5 V
0.8
0.8
0.7
2
0.1
1
-2
-0.1
-1
3
3.15
VCCIO - 0.2
2
2.5
2.625
0.35 ×
VCCIO
0.65 × VCCIO
VCCIO 0.3
+
VCCIO
0.45
-
1.8 V
1.5 V
1.71
1.8
1.5
1.89
-0.3
-0.3
0.45
2
2
-2
-2
0.35 ×
VCCIO
0.65 × VCCIO
VCCIO 0.3
+
0.25 ×
VCCIO
0.75 ×
VCCIO
1.425
1.575
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–16
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–23. Single-Ended I/O Standards for Arria II GZ Devices (Part 2 of 2)
V
CCIO (V)
Typ
VIL (V)
Max
VIH (V)
Max
0.65 × VCCIO
VOL (V)
Max
VOH (V)
Min
IOL
IOH
I/O Standard
(mA)
(mA)
Min
Max
Min
Min
0.35 ×
VCCIO
+
0.25 ×
VCCIO
0.75 ×
VCCIO
1.2 V
1.14
1.2
3
1.26
-0.3
2
-2
VCCIO
0.3
0.3 ×
VCCIO
0.5 ×
VCCIO
0.1 ×
VCCIO
3.0-V PCI
3.0-V PCI-X
2.85
2.85
3.15
3.15
—
—
3.6
0.9 × VCCIO
0.9 × VCCIO
1.5
1.5
-0.5
-0.5
0.35 ×
VCCIO
0.5 ×
VCCIO
0.1 ×
VCCIO
3
—
Table 1–24 lists the single-ended SSTL and HSTL I/O reference voltage specifications
for Arria II GX devices.
Table 1–24. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria II GX Devices
V
CCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
0.49 ×
VCCIO
0.51 ×
VCCIO
VREF
0.04
-
VREF
0.04
+
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
2.375
2.5
1.8
1.5
2.625
0.5 × VCCIO
0.9
VREF
VREF
VREF
0.04
-
VREF
0.04
+
1.71
1.89
0.833
0.969
0.47 ×
VCCIO
0.53 ×
VCCIO
0.47 ×
VCCIO
0.5 ×
VCCIO
0.53 ×
VCCIO
1.425
1.575
0.5 × VCCIO
HSTL-18 Class I, II
HSTL-15 Class I, II
1.71
1.8
1.5
1.89
0.85
0.71
0.9
0.95
0.79
0.85
0.71
0.9
0.95
0.79
1.425
1.575
0.75
0.75
0.48 ×
VCCIO
0.52 ×
VCCIO
HSTL-12 Class I, II
1.14
1.2
1.26
0.5 × VCCIO
—
VCCIO/2
—
Table 1–25 lists the single-ended SSTL and HSTL I/O reference voltage specifications
for Arria II GZ devices.
Table 1–25. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria II GZ Devices
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
0.49 ×
VCCIO
0.51 ×
VCCIO
VREF
0.04
-
VREF
0.04
+
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
2.375
2.5
1.8
1.5
2.625
0.5 × VCCIO
0.9
VREF
VREF
VREF
0.04
-
VREF
0.04
+
1.71
1.89
0.833
0.969
0.47 ×
VCCIO
0.53 ×
VCCIO
0.47 ×
VCCIO
0.53 ×
VCCIO
1.425
1.575
0.5 × VCCIO
VREF
HSTL-18 Class I, II
HSTL-15 Class I, II
1.71
1.8
1.5
1.89
0.85
0.68
0.9
0.95
0.9
—
—
VCCIO/2
—
—
1.425
1.575
0.75
V
CCIO/2
0.47 ×
VCCIO
0.53 ×
VCCIO
HSTL-12 Class I, II
1.14
1.2
1.26
0.5 × VCCIO
—
VCCIO/2
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–17
Electrical Characteristics
Table 1–26 lists the single-ended SSTL and HSTL I/O standard signal specifications
for Arria II GX devices.
Table 1–26. Single-Ended SSTL and HSTL I/O Standard Signal Specifications for Arria II GX Devices
VIL(DC) (V)
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V)
Max
VIH(AC) (V) VOL (V) VOH (V)
Min Max Min
VTT
IOL
IOH
I/O Standard
(mA) (mA)
Min
Max
VREF
0.18
-
+
VCCIO
0.3
+
+
+
+
+
+
+
+
+
+
+
VREF
+
-
VTT +
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
–0.3
VREF - 0.35
VREF - 0.35
VREF - 0.25
VREF - 0.25
VREF - 0.175
VREF - 0.175
8.1
16.4 –16.4
6.7 –6.7
13.4 –13.4
–8.1
0.18
0.35
0.57
VTT
0.76
VTT
0.57
VREF
0.18
-
VREF
+
VCCIO
0.3
VREF
+
-
VTT +
0.76
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.15
–0.15
0.18
0.35
VREF
0.125
-
VREF
+
VCCIO
0.3
VREF
+
-
VTT +
0.125
0.25
0.475
0.475
VREF
0.125
-
VREF
+
VCCIO
0.3
VREF
0.25
+
VCCIO
0.28
-
0.28
0.125
VREF
0.1
-
-
-
-
-
-
VREF
0.1
+
+
+
+
+
+
+
VCCIO
0.3
VREF
0.175
+
0.2 ×
VCCIO
0.8 ×
VCCIO
8
16
8
–8
–16
–8
VREF
0.1
VREF
0.1
VCCIO
0.3
VREF
0.175
+
0.2 ×
VCCIO
0.8 ×
VCCIO
VREF
0.1
VREF
0.1
VCCIO
0.3
VCCIO
0.4
-
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
0.4
0.4
0.4
0.4
VREF
0.1
VREF
0.1
VCCIO
0.3
VCCIO
0.4
-
-
-
16
8
–16
–8
VREF
0.1
VREF
0.1
VCCIO
0.3
VCCIO
0.4
VREF
0.1
VREF
0.1
VCCIO
0.3
VCCIO
0.4
16
8
–16
–8
VREF
0.08
-
-
VREF
VCCIO
VREF
0.15
+
0.25 × 0.75 ×
VCCIO VCCIO
VREF - 0.15
VREF - 0.15
0.08
VREF
0.08
0.15
VREF
0.08
+
VCCIO
0.15
+
VREF
0.15
+
0.25 × 0.75 ×
VCCIO VCCIO
14
–14
Table 1–27 lists the single-ended SSTL and HSTL I/O standard signal specifications
for Arria II GZ devices.
Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part 1 of 2)
VIL(DC) (V)
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
Max Min Max Min
VTT
IOL
IOH
I/O Standard
(mA)
(mA)
Min
Max
VREF
0.15
-
+
VCCIO
0.3
+
+
+
+
VREF
-
VREF
+
-
VTT +
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
-0.3
8.1
16.2
6.7
13.4
8
-8.1
-16.2
-6.7
-13.4
-8
0.15
0.31
0.31
0.57
VTT
0.76
VTT
0.57
VREF
0.15
-
VREF
0.15
+
VCCIO
0.3
VREF
-
VREF
+
-
VTT +
0.76
-0.3
-0.3
-0.3
—
0.31
0.31
VREF
0.125
-
VREF
0.125
+
VCCIO
0.3
VREF
-
VREF
+
-
VTT +
0.25
0.25
0.475
0.475
VREF
0.125
-
VREF
0.125
+
VCCIO
0.3
VREF
0.25
-
VREF
0.25
+
VCCIO
0.28
-
0.28
VREF
0.1
-
VREF
0.1
+
VREF
0.175
-
VREF
0.175
+
0.2 ×
VCCIO
0.8 ×
VCCIO
—
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–18
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part 2 of 2)
V
IL(DC) (V)
VIH(DC) (V)
Min Max
VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
IOL
(mA)
IOH
(mA)
I/O Standard
Min
Max
Max
Min
Max
Min
VREF
0.1
-
VREF
0.1
+
+
+
+
+
+
VREF
0.175
-
VREF
0.175
+
0.2 ×
VCCIO
0.8 ×
VCCIO
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
—
—
—
—
—
16
8
-16
-8
VREF
0.1
-
-
-
-
-
VREF
0.1
VCCIO
0.4
-
—
—
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
VREF - 0.2 VREF + 0.2
0.4
0.4
0.4
0.4
VREF
0.1
VREF
0.1
VCCIO
0.4
-
-
-
16
8
-16
-8
VREF
0.1
VREF
0.1
VCCIO
0.4
—
VREF
0.1
VREF
0.1
VCCIO
0.4
—
—
16
8
-16
-8
VREF
0.08
VREF
VCCIO
0.15
+
VREF
0.15
-
VREF
0.15
+
0.25×
VCCIO
0.75×
VCCIO
-0.15
-0.15
0.08
VREF
0.08
VREF
0.08
-
+
VCCIO
0.15
+
VREF
0.15
-
VREF
0.15
+
0.25×
VCCIO
0.75 ×
VCCIO
16
-16
Table 1–28 lists the differential SSTL I/O standards for Arria II GX devices.
Table 1–28. Differential SSTL I/O Standards for Arria II GX Devices
VCCIO (V)
Typ Max
VSWING(DC) (V)
Min Max
VX(AC) (V)
Typ
VSWING(AC) (V)
Min Max
VOX(AC) (V)
I/O Standard
SSTL-2 Class I, II
SSTL-18 Class I, II
Min
Min
Max
Min
Typ
Max
VCCIO/2
- 0.2
VCCIO/2
+ 0.2
VCCIO/2
- 0.15
VCCIO/2
+ 0.15
2.375 2.5 2.625 0.36 VCCIO
—
0.7 VCCIO
—
VCCIO/2
-
0.125
VCCIO/2
+
0.125
VCCIO/2
- 0.175
VCCIO/2
+ 0.175
1.71
1.8
1.89 0.25 VCCIO
—
0.5 VCCIO
—
VCCIO
2
/
VCCIO
2
/
SSTL-15 Class I, II 1.425 1.5 1.575 0.2
—
—
—
0.35
—
—
—
Table 1–29 lists the differential SSTL I/O standards for Arria II GZ devices
Table 1–29. Differential SSTL I/O Standards for Arria II GZ Devices
CCIO (V) VSWING(DC) (V)
Typ Max Min Max
V
VX(AC) (V)
Typ
VSWING(AC) (V)
Min Max
VOX(AC) (V)
Typ
I/O Standard
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
Min
Min
VCCIO VCCIO/2
Max
Min
Max
VCCIO/2
+ 0.2
VCCIO VCCIO/2
+ 0.6 - 0.15
VCCIO/2
+ 0.15
2.375 2.5 2.625 0.3
—
0.62
—
+ 0.6
- 0.2
V
CCIO/2
-
VCCIO/2
+
0.175
VCCIO
+ 0.6
VCCIO VCCIO/2
+ 0.6 - 0.125
VCCIO/2
+ 0.125
1.71
1.8
1.89 0.25
—
0.5
—
0.175
VCCIO
2
/
VCCIO
2
/
1.425 1.5 1.575 0.2
—
—
—
0.35
—
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–19
Electrical Characteristics
Table 1–30 lists the HSTL I/O standards for Arria II GX devices.
Table 1–30. Differential HSTL I/O Standards for Arria II GX Devices
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min Max
I/O Standard
Min Typ Max Min Max Min Typ
Max Min
0.95 0.88
0.79 0.71
0.48
Typ
—
Max
0.95
0.79
HSTL-18 Class I
1.71 1.8 1.89 0.2
1.425 1.5 1.575 0.2
—
—
0.85
0.71
—
—
0.4
0.4
—
—
HSTL-15 Class I, II
—
0.5 ×
VCCIO
0.5 × 0.52 ×
VCCIO VCCIO
HSTL-12 Class I, II
1.14 1.2 1.26 0.16
—
—
—
×
VCCIO
0.3
—
Table 1–31 lists the HSTL I/O standards for Arria II GZ devices.
Table 1–31. Differential HSTL I/O Standards for Arria II GZ Devices
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
I/O Standard
Min
Typ
Max Min Max Min
Typ
—
Max
1.12
0.9
Min
0.78
0.68
Typ
—
Max
Min Max
HSTL-18 Class I
1.71
1.8
1.89
0.2
—
—
0.78
0.68
1.12
0.9
0.4
0.4
—
—
HSTL-15 Class I, II
1.425 1.5 1.575 0.2
—
—
VCCIO
+
0.48
VCCIO
+ 0.3
0.5 ×
VCCIO
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
HSTL-12 Class I, II
1.14 1.2 1.26 0.16
—
—
0.3
Table 1–32 lists the differential I/O standard specifications for Arria II GX devices.
Table 1–32. Differential I/O Standard Specifications for Arria II GX Devices (Note 1)
V
CCIO (V)
VID (mV)
VICM (V) (2)
VOD (V) (3)
VOCM (V)
Typ Max
I/O
Standard
Min
Typ Max
Min
Cond. Max Min Max
Min Typ Max
Min
2.5 V
LVDS
VCM =
1.25 V
2.375 2.5 2.625 100
—
—
—
0.05 1.80 0.247
—
0.2
—
0.6
0.6
0.6
1.125 1.25 1.375
RSDS (4) 2.375 2.5 2.625
—
—
—
—
—
—
—
0.1
0.5
1
1.2
1.2
1.4
1.4
Mini-LVDS
2.375 2.5 2.625
(4)
—
0.25
LVPECL
(5)
2.375 2.5 2.625 300
—
—
—
—
0.6
—
1.8
—
—
—
—
—
—
—
—
—
—
—
—
—
BLVDS (6) 2.375 2.5 2.625 100
Notes to Table 1–32:
(1) The 1.5 V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–21.
(2) VIN range: 0 <= VIN <= 1.85 V.
(3) RL range: 90 <= RL <= 110 .
(4) The RSDS and mini-LVDS I/O standards are only supported for differential outputs.
(5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only.
(6) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–20
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–33 lists the differential I/O standard specifications for Arria II GZ devices.
Table 1–33. Differential I/O Standard Specifications for Arria II GZ Devices (Note 1)
I/O
Standard
(2)
VCCIO (V)
Typ
VID (mV)
VICM(DC) (V)
VOD (V) (3)
Typ Max
VOCM (V) (3)
Min
Max
Min Cond. Max Min Max
Min
Min
Typ
Max
2.5 V
LVDS
(HIO)
VCM
1.25 V
=
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
0.05
0.05
1.8 0.247
—
—
0.6 1.125 1.25 1.375
2.5 V
LVDS
(VIO)
VCM
1.25 V
=
1.8 0.247
0.6
1
1.25
1.5
RSDS
(HIO)
VCM
1.25 V
=
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 200
—
—
0.3
0.3
0.4
0.4
1.4
1.4
0.1
0.1
0.2
0.2
—
0.6
0.6
0.6
0.6
0.5
0.5
1
1.2
1.2
1.2
1.2
1.4
1.5
1.4
1.5
RSDS
(VIO)
VCM =
1.25 V
Mini-LVDS
(HIO)
1.32
5
—
600
600
0.25
0.25
Mini-LVDS
(VIO)
1.32
5
2.375 2.5 2.625 200
2.375 2.5 2.625 300
—
—
1
LVPECL
—
—
—
—
0.6
—
1.8
—
—
—
—
—
—
—
—
—
—
—
—
—
BLVDS (4) 2.375 2.5 2.625 100
Notes to Table 1–33:
(1) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–21.
(2) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(3) RL range: 90 RL 110 .
(4) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.
Power Consumption for the Arria II Device Family
Altera offers two ways to estimate power for a design:
■
Using the Microsoft Excel-based Early Power Estimator
Using the Quartus® II PowerPlay Power Analyzer feature
■
The interactive Microsoft Excel-based Early Power Estimator is typically used prior to
designing the FPGA in order to get a magnitude estimate of the device power. The
Quartus II PowerPlay Power Analyzer provides better quality estimates based on the
specifics of the design after place-and-route is complete. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities which, when combined with detailed circuit models, can yield very
accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the
Quartus II Handbook.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Switching Characteristics
This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade
devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers
reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
Transceiver Performance Specifications
Table 1–34 lists the Arria II GX transceiver specifications.
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 1 of 7)
I3
C4
Typ
C5 and I5
Typ
C6
Symbol/
Description
Condition
Unit
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
Input frequency
from REFCLK
input pins
—
50
—
622.08
50
—
622.08
50
—
622.08
50
—
622.08
MHz
Input frequency
from PLD input
—
—
—
50
—
—
—
—
200
2.2
—
50
—
—
—
—
200
2.2
—
50
—
—
—
—
200
2.2
—
50
—
—
—
—
200
2.2
—
MHz
V
Absolute VMAX
for a REFCLKpin
Absolute VMIN for
–0.3
–0.3
–0.3
–0.3
V
a
REFCLKpin
Rise/fall time (2)
—
—
—
45
—
—
0.2
55
—
45
—
—
0.2
55
—
45
—
—
0.2
55
—
45
—
—
0.2
55
UI
%
Duty cycle
Peak-to-peak
differential input
voltage
—
200
30
—
—
2000
33
200
30
—
—
2000
33
200
30
—
—
2000
33
200
30
—
—
2000
33
mV
kHz
Spread-spectrum
modulating clock PCIe
frequency
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 2 of 7)
I3
C4
C5 and I5
Typ
C6
Symbol/
Condition
Unit
—
Description
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
Spread-spectrum
downspread
0 to
–0.5%
0 to
–0.5%
0 to
–0.5%
0 to
–0.5%
PCIe
—
—
—
—
—
—
—
—
On-chip
termination
resistors
—
—
—
100
—
—
100
—
—
100
—
—
100
—
VICM
(AC coupled)
1100 5%
1100 5%
1100 5%
1100 5%
mV
HCSL I/O
standard for
PCIe
reference
clock
VICM
(DC coupled)
250
—
550
250
—
550
250
—
550
250
—
550
mV
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter
REFCLK Phase
Noise
-110
-120
-120
-130
-110
-120
-120
-130
-110
-120
-120
-130
-110
-120
-120
-130
10 KHz
100 KHz
1 MHz
Transmitter
REFCLK Phase
Jitter (rms) for
100 MHz
10 KHz to
20 MHz
—
—
—
3
—
—
—
3
—
—
—
3
—
—
—
3
ps
REFCLK (3)
2000
1%
2000
1%
2000
1%
2000
1%
Rref
—
—
—
—
—
—
Transceiver Clocks
Calibration block
clock frequency
10
—
125
10
—
125
10
—
125
10
—
125
MHz
(
cal_blk_clk)
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 3 of 7)
I3
C4
C5 and I5
Typ
C6
Symbol/
Condition
PCIe
Receiver
Detect
Unit
Description
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
fixedclkclock
frequency
—
125
—
—
125
—
—
125
—
—
125
—
MHz
Dynamic
reconfig.
clock
reconfig_
clkclock
frequency
2.5/
37.5
(4)
2.5/
37.5
(4)
2.5/
37.5
(4)
2.5/
37.5
(4)
—
50
2
—
—
1
50
2
—
50
2
—
50
2
MHz
ms
µs
frequency
Delta time
between
reconfig_
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
1
clks (5)
Transceiverblock
minimum
power-down
pulse width
—
—
—
—
Receiver
Supported I/O
Standards
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate (13)
—
—
600
—
—
—
6375
1.5
600
—
—
—
3750
1.5
600
—
—
—
3750
1.5
600
—
—
—
3125
1.5
Mbps
V
Absolute VMAX
for a receiver pin
(6)
Absolute VMIN for
a receiver pin
—
-0.4
—
—
—
—
-0.4
—
—
—
—
-0.4
—
—
—
—
-0.4
—
—
—
—
V
V
Maximum
VICM = 0.82 V
setting
2.7
2.7
2.7
2.7
peak-to-peak
differential input
voltage VID (diff
p-p)
V
ICM =1.1 V
setting (7)
—
—
1.6
—
—
1.6
—
—
1.6
—
—
1.6
V
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 4 of 7)
I3
C4
C5 and I5
Typ
C6
Symbol/
Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
Minimum
peak-to-peak
differential input
voltage VID (diff
p-p)
—
100
—
—
100
—
—
100
—
—
100
—
—
mV
VICM = 0.82 V
setting
—
—
820
—
—
—
—
820
—
—
—
—
820
—
—
—
—
820
—
—
mV
mV
VICM
VICM =1.1 V
setting (7)
1100
1100
1100
1100
Differential
on-chip
termination
resistors
100
setting
—
100
—
—
100
—
—
100
—
—
100
—
PCIe
XAUI
PCIe
XAUI
50 MHz to 1.25 GHz: –10dB
100 MHz to 2.5 GHz: –10dB
50 MHz to 1.25 GHz: –6dB
100 MHz to 2.5 GHz: –6dB
Return loss
differential mode
Return loss
common mode
Programmable
PPM detector
(8)
62.5, 100, 125, 200,
250, 300, 500, 1000
—
ppm
Run length
—
—
—
—
80
—
—
7
—
—
80
—
—
7
—
—
80
—
—
7
—
—
80
—
—
7
UI
Programmable
equalization
dB
Signal
detect/loss
threshold
PCIe Mode
65
—
175
65
—
175
75
65
—
175
65
—
175
mV
CDR LTR time
(9)
—
—
—
15
—
—
75
—
—
15
—
—
—
15
—
—
75
—
—
15
—
—
75
—
µs
µs
CDR minimum
T1b (10)
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 5 of 7)
I3
C4
C5 and I5
Typ
C6
Symbol/
Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
LTD lock time
(11)
—
0
100
4000
0
100
4000
0
100
4000
0
100
4000
ns
Data lock time
from rx_
freqlocked
(12)
—
—
—
4000
—
—
4000
—
—
4000
—
—
4000
ns
DC Gain
Setting = 0
—
—
—
0
3
6
—
—
—
—
—
—
0
3
6
—
—
—
—
—
—
0
3
6
—
—
—
—
—
—
0
3
6
—
—
—
dB
dB
dB
Programmable
DC gain
DC Gain
Setting = 1
DC Gain
Setting = 2
Transmitter
Supported I/O
Standards
1.5-V PCML
3750
Data rate
—
600
—
—
6375
—
600
—
—
600
—
—
3750
—
600
—
—
3125
—
Mbps
mV
0.65 V
setting
VOCM
650
650
—
650
650
Differential
on-chip
termination
resistors
100
setting
—
100
—
—
100
—
—
100
—
—
100
—
PCIe
XAUI
50 MHz to 1.25 GHz: –10dB
312 MHz to 625 MHz: –10dB
625 MHz to 3.125 GHz: –10dB/decade slope
Return loss
differential mode
Return loss
common mode
PCIe
50 MHz to 1.25 GHz: –6dB
Rise time (2)
—
—
50
50
—
—
200
200
50
50
—
—
200
200
50
50
—
—
200
200
50
50
—
—
200
200
ps
ps
Fall time
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 6 of 7)
I3
C4
C5 and I5
Typ
C6
Symbol/
Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Typ
Max
Intra-
differential pair
skew
—
—
—
15
—
—
15
—
—
15
—
—
15
ps
Intra-transceiver
block skew
PCIe ×4
PCIe ×8
—
—
—
—
120
300
—
—
—
—
120
300
—
—
—
—
120
300
—
—
—
—
120
300
ps
ps
Inter-transceiver
block skew
CMU PLL0 and CMU PLL1
CMU PLL lock
time from
CMUPLL_
reset
deassertion
—
—
25
—
—
100
320
—
25
—
—
100
240
—
25
—
—
100
240
—
25
—
—
100
200
s
PLD-Transceiver Interface
Interface speed
—
MHz
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 7 of 7)
I3
C4
Typ
C5 and I5
Typ
C6
Symbol/
Description
Condition
Unit
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Digital reset
pulse width
—
Minimum is 2 parallel clock cycles
Notes to Table 1–34:
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The rise/fall time is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) The minimum reconfig_clkfrequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clkfrequency is 37.5 MHz if the transceiver channel is
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II Devices.
(5) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
you use different reconfig_clksources for these altgx_reconfiginstances, the delta time between any two of these reconfig_clksources becoming stable must not exceed the maximum
specification listed.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS and the link is DC-coupled.
(8) The rate matcher supports only up to 300 parts per million (ppm).
(9) Time taken to rx_pll_lockedgoes high from rx_analogresetde-assertion. Refer to Figure 1–1.
(10) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_lockedgoes high and before rx_locktodatais asserted in manual mode. Refer to Figure 1–1.
(11) The time taken to recover valid data after the rx_locktodatasignal is asserted in manual mode. Refer to Figure 1–1.
(12) The time taken to recover valid data after the rx_freqlockedsignal goes high in automatic mode. Refer to Figure 1–2.
(13) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
1–28
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35 lists the transceiver specifications for Arria II GZ devices.
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 1 of 5)
–C3 and –I3 (1)
–C4 and –I4
Unit
Symbol/
Conditions
Description
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O Standards
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
Input frequency from
REFCLKinput pins
—
50
—
697
50
—
637.5
MHz
MHz
Phase frequency detector
(CMU PLL and receiver
CDR)
—
50
—
325
50
—
325
Absolute VMAX for a REFCLK
pin
—
—
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
V
V
V
Operational VMAX for a
REFCLKpin
Absolute VMIN for a REFCLK
pin
-0.4
-0.4
Rise/fall time (2)
—
—
—
45
—
—
0.2
55
—
45
—
—
0.2
55
UI
%
Duty cycle
Peak-to-peak differential
input voltage
—
200
30
—
—
1600
33
200
30
—
—
1600
33
mV
kHz
Spread-spectrum
modulating clock frequency
PCIe
0 to
0 to
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
—
—
—
-0.5%
-0.5%
On-chip termination
resistors
—
—
100
100
VICM (AC coupled)
1100 10%
1100 10%
mV
HCSL I/O standard
for PCIe reference
clock
VICM (DC coupled)
250
—
550
250
—
550
mV
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-110
-120
-120
-130
-110
-120
-120
-130
Transmitter REFCLK Phase
Noise
10 KHz
100 KHz
1 MHz
Transmitter REFCLK Phase
Jitter (rms) for 100 MHz
REFCLK (3)
10 KHz to 20 MHz
—
—
—
—
3
—
—
—
3
ps
2000
1%
2000
1%
RREF
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–29
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 5)
–C3 and –I3 (1)
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Max
Transceiver Clocks
Calibration block clock
frequency (cal_blk_clk
—
10
—
—
125
—
10
—
—
125
—
MHz
MHz
)
PCIe Receiver
Detect
fixedclkclock frequency
125
125
Dynamic
reconfiguration
clock frequency
2.5/
37.5
(4)
2.5/
37.5
(4)
reconfig_clkclock
frequency
—
—
50
2
—
—
50
2
MHz
ms
Delta time between
reconfig_clks (5)
—
—
—
Transceiver block minimum
power-down
—
1
—
—
1
—
—
µs
(gxb_powerdown) pulse
width
Receiver
Supported I/O Standards
Data rate (16)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
—
—
600
—
6375
600
—
3750
Mbps
V
Absolute VMAX for a receiver
pin (6)
—
—
1.6
—
—
1.6
Operational VMAX for a
receiver pin
—
—
—
—
—
1.5
—
—
—
—
1.5
—
V
V
Absolute VMIN for a receiver
pin
-0.4
-0.4
Maximum peak-to-peak
differential input voltage VID
(diff p-p) before device
configuration
—
—
—
1.6
—
—
1.6
V
VICM = 0.82 V
setting
Maximum peak-to-peak
differential input voltage VID
(diff p-p) after device
configuration
—
—
—
—
2.7
1.6
—
—
—
—
2.7
1.6
V
V
V
ICM =1.1 V setting
(7)
Data Rate =
600 Mbps to
5 Gbps
100
165
—
—
—
—
165
165
—
—
—
—
mV
mV
Equalization = 0
DC gain = 0 dB
Minimum differential eye
opening at receiver serial
input pins (8)
Data Rate > 5 Gbps
Equalization = 0
DC gain = 0 dB
VICM = 0.82 V
setting
820 10%
820 10%
mV
mV
VICM
VICM = 1.1 V setting
1100 10%
1100 10%
(7)
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–30
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 3 of 5)
–C3 and –I3 (1)
–C4 and –I4
Unit
Symbol/
Conditions
Description
Min
Typ
Max
Min
Typ
Max
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the Transceiver Architecture for Arria II
Devices chapter.
Receiver DC Coupling
Support
—
85 setting
100 setting
120 setting
150- setting
85 20%
100 20%
120 20%
150 20%
85 20%
100 20%
120 20%
150 20%
Differential on-chip
termination resistors
PCIe (Gen 1 and
Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
SRIO SR/LR,
Differential and common
mode return loss
Compliant
—
CPRI LV/HV,
OBSAI,
SATA
Programmable PPM
detector (9)
—
62.5, 100, 125, 200, 250, 300, 500, 1,000
ppm
Run length
—
—
—
—
15
—
—
—
—
—
—
—
—
200
16
—
—
—
15
—
—
—
—
—
—
—
—
200
16
UI
dB
Programmable equalization
tLTR (10)
—
—
—
75
75
µs
tLTR_LTD_Manual (11)
tLTD_Manual (12)
tLTD_Auto (13)
—
—
µs
—
4000
4000
4000
4000
ns
—
ns
PCIe Gen1
PCIe Gen2
2.0 - 3.5
MHz
MHz
40 - 65
(OIF) CEI PHY at
6.375 Gbps
20 - 35
MHz
XAUI
10 - 18
10 - 18
10 - 18
6 - 10
6 - 10
3 - 6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD) mode
SRIO 1.25 Gbps
SRIO 2.5 Gbps
SRIO 3.125 Gbps
GIGE
SONET OC12
SONET OC48
14 - 19
recon
fig_
clk
Receiver buffer and CDR
offset cancellation time (per
channel)
—
—
—
17000
—
—
17000
cycles
DC Gain Setting = 0
DC Gain Setting = 1
DC Gain Setting = 2
—
—
—
0
3
6
—
—
—
—
—
—
0
3
6
—
—
—
dB
dB
dB
Programmable DC gain
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–31
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 4 of 5)
–C3 and –I3 (1)
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Max
Transmitter
Supported I/O Standards
Data rate (14)
VOCM
1.5-V PCML
6375
—
600
—
—
600
—
—
3750
—
Mbps
mV
0.65 V setting
85 setting
100 setting
120 setting
150- setting
650
—
650
85 15%
100 15%
120 15%
150 15%
85 15%
100 15%
120 15%
150 15%
Differential on-chip
termination resistors
PCIe Gen1 and
Gen2 (TX VOD=4),
XAUI (TX VOD=6),
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
Differential and common
mode return loss
Compliant
—
SRIO SR (VOD=6),
SRIO LR (VOD=8),
CPRI LV (VOD=6),
CPRI HV (VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
Rise time (15)
—
—
—
50
50
—
—
—
—
200
200
15
50
50
—
—
—
—
200
200
15
ps
ps
ps
Fall time (15)
Intra-differential pair skew
×4 PMA and PCS
bonded mode
Example: XAUI,
PCIe ×4, Basic ×4
Intra-transceiver block
transmitter
channel-to-channel skew
—
—
—
—
120
500
—
—
—
—
120
500
ps
ps
×8 PMA and PCS
bonded mode
Example: PCIe ×8,
Basic ×8
Inter-transceiver block
transmitter
channel-to-channel skew
CMU0 PLL and CMU1 PLL
Supported Data Range
—
—
600
—
—
1
6375
100
600
—
—
1
3750
100
Mbps
pll_powerdownminimum
pulse width
s
(tpll_powerdown)
CMU PLL lock time from
pll_powerdown
de-assertion
—
—
—
s
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–32
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 5 of 5)
–C3 and –I3 (1)
–C4 and –I4
Unit
Symbol/
Conditions
Description
Min
Typ
Max
Min
Typ
Max
PCIe Gen1
PCIe Gen2
2.5 - 3.5
MHz
MHz
6 - 8
(OIF) CEI PHY at
4.976 Gbps
7 - 11
MHz
MHz
(OIF) CEI PHY at
6.375 Gbps
5 - 10
XAUI
2 - 4
3 - 5.5
3 - 5.5
2 - 4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
-3 dB Bandwidth
SRIO 1.25 Gbps
SRIO 2.5 Gbps
SRIO 3.125 Gbps
GIGE
2.5 - 4.5
1.5 - 2.5
3.5 - 6
SONET OC12
SONET OC48
Transceiver-FPGA Fabric Interface
Interface speed
—
—
25
—
325
25
—
250
MHz
—
Digital reset pulse width
Notes to Table 1–35:
Minimum is two parallel clock cycles
(1) The 3x speed grade is the fastest speed grade offered in the following Arria II GZ devices: EP2AGZ225, EP2AGZ300, and EP2AGZ350.
(2) The rise and fall time transition is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) The minimum reconfig_clkfrequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
reconfig_clkfrequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode.
(5) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx
)
channels physically located on the same side of the device AND if you use different reconfig_clksources for these altgx_reconfig
instances, the delta time between any two of these reconfig_clksources becoming stable must not exceed the maximum specification listed.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS.
(8) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
(9) The rate matcher supports only up to 300 ppm.
(10) Time taken to rx_pll_lockedgoes high from rx_analogresetde-assertion. Refer to Figure 1–1 on page 1–33.
(11) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_lockedgoes high and before rx_locktodatais asserted in
manual mode. Refer to Figure 1–1 on page 1–33.
(12) Time taken to recover valid data after the rx_locktodatasignal is asserted in manual mode. Refer to Figure 1–1 on page 1–33.
(13) Time taken to recover valid data after the rx_freqlockedsignal goes high in automatic mode. Refer to Figure 1–2 on page 1–33.
(14) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the Transceiver
Clocking for Arria II Devices chapter.
(15) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(16) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–33
Switching Characteristics
Figure 1–1 shows the lock time parameters in manual mode.
LTD = lock-to-data. LTR = lock-to-reference.
1
Figure 1–1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_loc
ked
r x_locktodata
r x_dataout
Invalid Data
Valid data
CDR LTR Time
LTD lock time
CDR Minimum T1b
Figure 1–2 shows the lock time parameters in automatic mode.
Figure 1–2. Lock Time Parameters for Automatic Mode
LTR
LTD
CDR status
r x_freqlocked
r x_dataout
Valid
data
Invalid
data
Data lock time from rx_freqlocked
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–34
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Figure 1–3 shows the differential receiver input waveform.
Figure 1–3. Receiver Input Waveform
Single-Ended Waveform
Positive Channel (p)
V
ID
Negative Channel (n)
Ground
V
CM
Differential Waveform
V
(diff peak-peak) = 2 x V (single-ended)
ID
ID
V
ID
p − n = 0 V
V
ID
Figure 1–4 shows the transmitter output waveform.
Figure 1–4. Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
V
OD
Negative Channel (n)
Ground
V
CM
Differential Waveform
V
(diff peak-peak) = 2 x V
OD
(single-ended)
OD
V
OD
p − n = 0 V
V
OD
Table 1–36 lists the typical VOD for TX term that equals 85 . for Arria II GZ devices.
Table 1–36. Typical VOD Setting, TX Term = 85 for Arria II GZ Devices
V
OD Setting (mV)
Symbol
VOD differential
0
1
2
3
4
5
6
7
170
340
510
595
680
765
20%
850
20%
1020
20%
peak-to-peak Typical (mV) 20%
20%
20%
20%
20%
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–35
Switching Characteristics
Table 1–37 lists the typical VOD for TX term that equals 100 . for Arria II GX and GZ
devices.
Table 1–37. Typical VOD Setting, TX Termination = 100 for Arria II Devices
Quartus II Setting
VOD Setting (mV)
1
400
600
2
3 (Arria II GZ)
700
4
5
6
7
800
900
1000
1200
Table 1–38 lists the typical transmitter pre-emphasis levels in dB for the first post tap
under the following conditions: low-frequency data pattern (five 1s and five 0s) at
6.375 Gbps. The levels listed in Table 1–38 are a representation of possible
pre-emphasis levels under these specified conditions only, the pre-emphasis levels
may change with data pattern and data rate.
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Arria II GX HSSI HSPICE models.
Table 1–38. Transmitter Pre-Emphasis Levels for Arria II GX Devices
Arria II GX
(Quartus II
Software)
First Post Tap
Setting
Arria II GX (Quartus II Software) VOD Setting
1
2
4
5
6
7
Unit
0 (off)
0
0
0
0
0
0
—
dB
dB
dB
dB
dB
dB
1
2
3
4
5
6
0.7
2.7
4.9
7.5
—
0
0
0
0
0
1.2
2.4
3.8
5.3
7
0.3
1.2
2.1
3.1
4.3
0
0
0
0.8
1.6
2.4
3.3
0.5
1.2
1.8
2.7
0.2
0.6
1.1
1.7
—
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–36
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–39 lists typical transmitter pre-emphasis levels for Arria II GZ devices (in dB)
for the first post tap under the following conditions (low-frequency data pattern [five
1s and five 0s] at 6.25 Gbps). The levels listed in Table 1–39 are a representation of
possible pre-emphasis levels under the specified conditions only and that the pre-
emphasis levels may change with data pattern and data rate.
f
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Arria II HSSI HSPICE models.
Table 1–39. Transmitter Pre-Emphasis Levels for Arria II GZ Devices (Part 1 of 2)
Pre-
Emphasis
1st
Post-Tap
Setting
VOD Setting
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.7
1
0
0
0
2
0.3
0.6
0.7
1.2
1.3
1.8
2.1
2.4
2.8
3.2
3.5
3.8
4.2
4.5
4.9
5.3
5.7
6.1
6.6
7
0
0
0
0
3
1.5
2
0
0
0
0
4
0.3
0.5
0.8
1.1
1.3
1.6
1.9
2.2
2.6
2.8
3.1
3.4
3.7
4
0
0
0
0
5
2.7
3.1
3.7
4.2
4.9
5.4
6
0.3
0.5
0.7
0.9
1.2
1.4
1.7
1.9
2.1
2.3
2.6
2.9
3.1
3.4
3.6
4
0
0
0
6
0.2
0.4
0.6
0.8
1
0
0
7
0.2
0.3
0.5
0.7
0.9
1.1
1.2
1.3
1.5
1.7
1.8
2
0
8
0
9
0.2
0.3
0.4
0.6
0.6
0.7
0.8
0.9
1.1
1.2
1.4
1.5
1.7
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1.2
1.4
1.6
1.7
1.9
2.2
2.4
2.6
2.8
3.1
3.3
3.8
4.3
4.8
5.4
5.9
6.4
7.1
6.8
7.5
8.1
8.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4.4
4.7
5.1
5.4
6.1
6.8
7.6
8.4
9.4
10.3
11.3
2.2
2.4
2.7
3
4.3
4.8
5.4
6
8
9
3.4
3.9
4.4
4.9
5.3
5.8
2.3
2.6
3
10
11.4
12.6
N/A
N/A
6.8
7.4
8.1
8.8
3.3
3.6
4
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–37
Switching Characteristics
Table 1–39. Transmitter Pre-Emphasis Levels for Arria II GZ Devices (Part 2 of 2)
Pre-
Emphasis
1st
Post-Tap
Setting
VOD Setting
0
1
2
3
4
5
6
7
29
30
31
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.5
N/A
N/A
9.6
7.7
9
6.3
7.4
8.2
4.3
N/A
N/A
11.4
12.9
10
Table 1–40 lists the transceiver jitter specifications for all supported protocols for
Arria II GX devices.
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 1 of 10)
I3
C4
C5, I5
Min Typ
C6
Max Min Typ Max
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
SONET/SDH Transmit Jitter Generation (2)
Peak-to-peak
Pattern =
jitter at
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
UI
UI
UI
UI
PRBS15
622.08 Mbps
RMS jitter at
622.08 Mbps
Pattern =
PRBS15
—
—
—
Peak-to-peak
jitter at
2488.32 Mbps
Pattern =
PRBS15
RMS jitter at
2488.32 Mbps
Pattern =
PRBS15
0.01
0.01
0.01
0.01
SONET/SDH Receiver Jitter Tolerance (2)
Jitter frequency =
0.03 KHz
> 15
> 1.5
> 15
> 1.5
> 15
> 1.5
> 15
> 1.5
UI
UI
UI
Pattern = PRBS15
Jitter frequency =
Jitter tolerance at
25 KHZ
622.08 Mbps
Pattern = PRBS15
Jitter frequency =
250 KHz
> 0.15
> 0.15
> 0.15
> 0.15
Pattern = PRBS15
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–38
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 2 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
Jitter frequency =
0.06 KHz
> 15
> 1.5
> 15
> 1.5
> 15
> 1.5
> 15
> 1.5
UI
Pattern = PRBS15
Jitter frequency =
100 KHZ
UI
UI
UI
Pattern = PRBS15
Jitter tolerance at
2488.32 Mbps
Jitter frequency =
1 MHz
> 0.15
> 0.15
> 0.15
> 0.15
> 0.15
> 0.15
> 0.15
> 0.15
Pattern = PRBS15
Jitter frequency =
10 MHz
Pattern = PRBS15
XAUI Transmit Jitter Generation (3)
Total jitter at
Pattern = CJPAT
3.125 Gbps
—
—
—
—
0.3
—
—
—
—
0.3
—
—
—
—
0.3
—
—
—
—
0.3
UI
UI
Deterministic
jitter at
Pattern = CJPAT
0.17
0.17
0.17
0.17
3.125 Gbps
XAUI Receiver Jitter Tolerance (3)
Total jitter
—
> 0.65
> 0.37
> 0.65
> 0.37
> 0.65
> 0.37
> 0.65
> 0.37
UI
UI
Deterministic
jitter
—
Peak-to-peak
jitter
Jitter frequency =
22.1 KHz
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
UI
UI
UI
Peak-to-peak
jitter
Jitter frequency =
1.875 MHz
Peak-to-peak
jitter
Jitter frequency =
20 MHz
PCIe Transmit Jitter Generation (4)
Total jitter at
2.5 Gbps (Gen1)
Compliance
pattern
—
—
0.25
—
—
0.25
—
—
0.25
—
—
0.25
UI
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–39
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 3 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
PCIe Receiver Jitter Tolerance (4)
Total jitter at
2.5 Gbps (Gen1)
Compliance
pattern
> 0.6
> 0.6
> 0.6
—
> 0.6
UI
PCIe (Gen 1) Electrical Idle Detect Threshold (9)
VRX-IDLE-
DETDIFF (p-p)
Compliance
pattern
65
—
175
65
—
175
65
175
65
—
175
mV
Serial RapidIO® (SRIO) Transmit Jitter Generation (5)
Deterministic
jitter
Data Rate = 1.25,
2.5, 3.125 Gbps
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
UI
UI
(peak-to-peak)
Pattern = CJPAT
Data Rate = 1.25,
2.5, 3.125 Gbps
Total jitter
(peak-to-peak)
Pattern = CJPAT
SRIO Receiver Jitter Tolerance (5)
Data Rate = 1.25,
2.5, 3.125 Gbps
Deterministic
jitter tolerance
(peak-to-peak)
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
> 0.55
UI
UI
Pattern = CJPAT
Combined
Data Rate = 1.25,
2.5, 3.125 Gbps
deterministic and
random jitter
tolerance
Pattern = CJPAT
(peak-to-peak)
Jitter frequency =
22.1 KHz
Data rate = 1.25,
2.5, 3.125 Gbps
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
UI
UI
Pattern = CJPAT
Jitter frequency =
1.875 MHz
Sinusoidal jitter
tolerance
(peak-to-peak)
Data rate = 1.25,
2.5, 3.125 Gbps
Pattern = CJPAT
Jitter frequency =
20 MHz
Data rate = 1.25,
2.5, 3.125 Gbps
> 0.1
> 0.1
> 0.1
> 0.1
UI
UI
Pattern = CJPAT
GIGE Transmit Jitter Generation (6)
Deterministic
jitter
Pattern = CRPAT
—
—
0.14
—
—
0.14
—
—
0.14
—
—
0.14
(peak-to-peak)
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–40
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 4 of 10)
I3
C4
Max Min Typ Max
0.27
C5, I5
Min Typ
C6
Symbol/
Conditions
Unit
Description
Min
Typ
Max Min Typ Max
Total jitter
(peak-to-peak)
Pattern = CRPAT
—
—
—
—
0.279
—
—
0.279
—
—
0.279 UI
9
GIGE Receiver Jitter Tolerance (6)
Deterministic
jitter tolerance
(peak-to-peak)
Pattern = CJPAT
> 0.4
> 0.4
> 0.4
> 0.4
UI
UI
Combined
deterministic and
random jitter
tolerance
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
> 0.66
(peak-to-peak)
HiGig Transmit Jitter Generation (7)
Data rate =
3.75 Gbps
Deterministic
jitter
(peak-to-peak)
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
Pattern = CJPAT
Data rate =
3.75 Gbps
Total jitter
(peak-to-peak)
Pattern = CJPAT
HiGig Receiver Jitter Tolerance (7)
Data rate =
3.75 Gbps
Deterministic
jitter tolerance
(peak-to-peak)
> 0.37
> 0.65
> 0.37
> 0.65
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
Pattern = CJPAT
Combined
Data rate =
3.75 Gbps
deterministic and
random jitter
tolerance
Pattern = CJPAT
(peak-to-peak)
Jitter frequency =
22.1 KHz
Data rate =
3.75 Gbps
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
UI
Pattern = CJPAT
Jitter frequency =
1.875MHz
Sinusoidal jitter
tolerance
(peak-to-peak)
Data rate =
3.75 Gbps
Pattern = CJPAT
Jitter frequency =
20 MHz
Data rate =
3.75 Gbps
Pattern = CJPAT
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–41
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 5 of 10)
I3
C4
C5, I5
Min Typ
C6
Max Min Typ Max
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
SDI Transmitter Jitter Generation (8)
Data rate =
1.485 Gbps (HD)
pattern = Color
Bar Low-
0.2
—
—
—
—
0.2
0.3
—
—
—
—
0.2
0.3
—
—
—
—
0.2
0.3
—
—
—
—
UI
UI
frequency Roll-off
= 100 KHz
Alignment jitter
(peak-to-peak)
Data rate =
2.97 Gbps (3G)
pattern = Color
bar Low-
0.3
frequency Roll-off
= 100 KHz
SDI Receiver Jitter Tolerance (8)
Jitter frequency =
15 KHz
Data rate =
2.97 Gbps (3G)
Pattern = single
line scramble
color bar
> 2
> 2
> 2
> 2
UI
UI
UI
Jitter frequency =
100 KHz
Sinusoidal jitter
tolerance
(peak-to-peak)
Data rate =
2.97 Gbps (3G)
Pattern = single
line scramble
color bar
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
Jitter frequency =
148.5 MHz
Data rate =
2.97 Gbps (3G)
Pattern = single
line scramble
color bar
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–42
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 6 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
Jitter frequency =
20 KHz
Data rate =
1.485 Gbps (HD)
Pattern = 75%
color bar
> 1
> 1
> 1
> 1
UI
Jitter frequency =
100 KHz
Data rate = 1.485
Gbps (HD)
Pattern = 75%
color bar
Sinusoidal jitter
tolerance
(peak-to-peak)
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
UI
UI
Jitter frequency =
148.5 MHz
Data rate =
1.485 Gbps (HD)
Pattern =75%
color bar
SATA Transmit Jitter Generation (10)
Total jitter at
1.5 Gbps (G1)
Compliance
pattern
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
UI
UI
UI
UI
Deterministic
jitter at 1.5 Gbps
(G1)
Compliance
pattern
Total jitter at
3.0 Gbps (G2)
Compliance
pattern
Deterministic
jitter at 3.0 Gbps
(G2)
Compliance
pattern
Total jitter at
6.0 Gbps (G3)
Compliance
pattern
—
—
—
—
0.52
0.18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
Random jitter at
6.0 Gbps (G3)
Compliance
pattern
SATA Receiver Jitter Tolerance (10)
Total jitter
Compliance
tolerance at
pattern
> 0.65
> 0.35
33
> 0.65
> 0.35
33
> 0.65
> 0.35
33
> 0.65
> 0.35
33
UI
UI
1.5 Gbps (G1)
Deterministic
Compliance
jitter tolerance at
pattern
1.5 Gbps (G1)
SSC modulation
Compliance
frequency at
pattern
kHz
1.5 Gbps (G1)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–43
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 7 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Conditions
Unit
ppm
ps
Description
Min
Typ
Max Min Typ Max
Max Min Typ Max
SSC modulation
deviation at
1.5 Gbps (G1)
Compliance
pattern
5700
80
5700
80
5700
80
5700
RX differential
skew at 1.5 Gbps
(G1)
Compliance
pattern
80
150
RX AC common
mode voltage at
1.5 Gbps (G1)
Compliance
pattern
150
150
150
mV
UI
Total jitter
tolerance at
3.0 Gbps (G2)
Compliance
pattern
> 0.65
> 0.35
33
> 0.65
> 0.35
33
> 0.65
> 0.35
33
> 0.65
> 0.35
33
Deterministic
jitter tolerance at
3.0 Gbps (G2)
Compliance
pattern
UI
SSC modulation
frequency at
3.0 Gbps (G2)
Compliance
pattern
kHz
ppm
ps
SSC modulation
deviation at
3.0 Gbps (G2)
Compliance
pattern
5700
75
5700
75
5700
75
5700
75
RX differential
skew at 3.0 Gbps
(G2)
Compliance
pattern
RX AC common
mode voltage at
3.0 Gbps (G2)
Compliance
pattern
150
150
150
150
mV
UI
Total jitter
tolerance at
6.0 Gbps (G3)
Compliance
pattern
> 0.60
> 0.18
33
> 0.60
> 0.18
33
> 0.60
> 0.18
33
> 0.60
> 0.18
33
Random jitter
tolerance at
6.0 Gbps (G3)
Compliance
pattern
UI
SSC modulation
frequency at
6.0 Gbps (G3)
Compliance
pattern
kHz
ppm
ps
SSC modulation
deviation at
6.0 Gbps (G3)
Compliance
pattern
5700
30
5700
30
5700
30
5700
30
RX differential
skew at 6.0 Gbps
(G3)
Compliance
pattern
RX AC common
mode voltage at
6.0 Gbps (G3)
Compliance
pattern
100
100
100
100
mV
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–44
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 8 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
CPRI Transmit Jitter Generation (11)
E.6.HV, E.12.HV
0.27
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
—
—
—
—
—
—
—
—
0.279 UI
Pattern = CJPAT
Total jitter
E.6.LV, E.12.LV,
E.24.LV, E.30.LV
0.35
0.35
0.14
0.17
UI
UI
UI
Pattern = CJTPAT
E.6.HV, E.12.HV
Pattern = CJPAT
0.14
0.17
Deterministic
jitter
E.6.LV, E.12.LV,
E.24.LV, E.30.LV
Pattern = CJTPAT
CPRI Receiver Jitter Tolerance (11)
E.6.HV, E.12.HV
Pattern = CJPAT
E.6.HV, E.12.HV
Pattern = CJPAT
Total jitter
tolerance
> 0.66
> 0.4
> 0.66
> 0.4
> 0.66
> 0.4
> 0.66
> 0.4
UI
UI
Deterministic
jitter tolerance
E.6.LV, E.12.LV,
E.24.LV, E.30.LV
> 0.65
> 0.6
> 0.65
—
> 0.65
—
> 0.65
—
UI
UI
UI
UI
Total jitter
tolerance
Pattern = CJTPAT
E.60.LV
Pattern = PRBS31
E.6.LV, E.12.LV,
E.24.LV, E.30.LV
> 0.37
> 0.45
> 0.37
—
> 0.37
—
> 0.37
—
Deterministic
jitter tolerance
Pattern = CJTPAT
E.60.LV
Pattern = PRBS31
Combined
E.6.LV, E.12.LV,
E.24.LV, E.30.LV
deterministic and
random jitter
tolerance
> 0.55
> 0.55
> 0.55
> 0.55
UI
Pattern = CJTPAT
OBSAI Transmit Jitter Generation (12)
Total jitter at
REFCLK =
768 Mbps,
153.6 MHz
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
UI
UI
1536 Mbps, and
Pattern = CJPAT
3072 Mbps
Deterministic
jitter at
768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK =
153.6 MHz
Pattern = CJPAT
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–45
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 9 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
OBSAI Receiver Jitter Tolerance (12)
Deterministic
jitter tolerance at
768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
Pattern = CJPAT
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
UI
Combined
deterministic and
random jitter
tolerance at
> 0.55
UI
768 Mbps,
1536 Mbps, and
3072 Mbps
Jitter frequency =
5.4 KHz
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
UI
UI
UI
UI
Pattern = CJPAT
Sinusoidal jitter
tolerance at
768 Mbps
Jitter frequency =
460.8 KHz to 20
MHz
Pattern = CJPAT
Jitter frequency =
10.9 KHz
Pattern = CJPAT
Sinusoidal jitter
tolerance at
1536 Mbps
Jitter frequency =
921.6 KHz to 20
MHz
Pattern = CJPAT
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–46
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 10 of 10)
I3
C4
C5, I5
Min Typ
C6
Symbol/
Description
Conditions
Unit
Min
Typ
Max Min Typ Max
Max Min Typ Max
Jitter frequency =
21.8 KHz
> 8.5
> 8.5
> 8.5
> 8.5
UI
Pattern = CJPAT
Sinusoidal jitter
tolerance at
3072 Mbps
Jitter frequency =
1843.2 KHz to 20
MHz
> 0.1
> 0.1
> 0.1
> 0.1
UI
Pattern = CJPAT
Notes to Table 1–40:
(1) Dedicated refclkpins are used to drive the input reference clocks. The jitter numbers are valid for the stated conditions only.
(2) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(3) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(4) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(5) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(6) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(7) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(9) Arria II PCIe receivers are compliant to this specification provided the VTX_CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(10) The jitter numbers for Serial Advanced Technology Attachment (SATA) are compliant to the Serial ATA Revision 3.0 Specification.
(11) The jitter numbers for Common Public Radio Interface (CPRI) are compliant to the CPRI Specification V3.0.
(12) The jitter numbers for Open Base Station Architecture Initiative (OBSAI) are compliant to the OBSAI RP3 Specification V4.1.
Table 1–41 lists the transceiver jitter specifications for all supported protocols for
Arria II GZ devices.
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 1 of 7)
–C3 and –I3
Typ
–C4 and –I4
Typ
Symbol/
Description
Conditions
Unit
Min
Max
Min
Max
SONET/SDH Transmit Jitter Generation (3)
Peak-to-peak jitter at
622.08 Mbps
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
—
—
—
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
UI
UI
UI
UI
RMS jitter at 622.08 Mbps
Peak-to-peak jitter at 2488.32
Mbps
RMS jitter at 2488.32 Mbps
0.01
0.01
SONET/SDH Receiver Jitter Tolerance (3)
Jitter frequency = 0.03 KHz
Pattern = PRBS15
> 15
> 1.5
> 15
> 1.5
UI
UI
UI
Jitter frequency =
25 KHZ
Jitter tolerance at 622.08 Mbps
Pattern = PRBS15
Jitter frequency = 250 KHz
Pattern = PRBS15
> 0.15
> 0.15
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–47
Max
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 2 of 7)
–C3 and –I3
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Jitter frequency = 0.06 KHz
Pattern = PRBS15
> 15
> 15
UI
UI
Jitter frequency = 100 KHZ
Pattern = PRBS15
> 1.5
> 0.15
> 0.15
> 1.5
Jitter tolerance at 2488.32 Mbps
Jitter frequency =
1 MHz
> 0.15
> 0.15
UI
UI
Pattern = PRBS15
Jitter frequency = 10 MHz
Pattern = PRBS15
Fibre Channel Transmit Jitter Generation (4), (5)
Total jitter FC-1
Pattern = CRPAT
—
—
—
—
—
—
—
—
—
—
—
—
0.23
0.11
0.33
0.2
—
—
—
—
—
—
—
—
—
—
—
—
0.23
0.11
0.33
0.2
UI
UI
UI
UI
UI
UI
Deterministic jitter FC-1
Total jitter FC-2
Pattern = CRPAT
Pattern = CRPAT
Pattern = CRPAT
Pattern = CRPAT
Pattern = CRPAT
Deterministic jitter FC-2
Total jitter FC-4
0.52
0.33
0.52
0.33
Deterministic jitter FC-4
Fibre Channel Receiver Jitter Tolerance (4), (6)
Deterministic jitter FC-1
Pattern = CJTPAT
> 0.37
> 0.31
> 0.37
> 0.31
UI
UI
Random jitter
FC-1
Pattern = CJTPAT
Fc/25000
Fc/1667
> 1.5
> 0.1
> 1.5
> 0.1
UI
UI
UI
Sinusoidal jitter FC-1
Deterministic jitter FC-2
Pattern = CJTPAT
> 0.33
> 0.33
Random jitter
FC-2
Pattern = CJTPAT
> 0.29
> 0.29
UI
Fc/25000
Fc/1667
> 1.5
> 0.1
> 1.5
> 0.1
UI
UI
UI
UI
UI
UI
Sinusoidal jitter FC-2
Deterministic jitter FC-4
Random jitter FC-4
Pattern = CJTPAT
Pattern = CJTPAT
Fc/25000
> 0.33
> 0.29
> 1.5
> 0.33
> 0.29
> 1.5
Sinusoidal jitter FC-4
Fc/1667
> 0.1
> 0.1
XAUI Transmit Jitter Generation (7)
Total jitter at 3.125 Gbps
Pattern = CJPAT
Pattern = CJPAT
—
—
—
—
0.3
—
—
—
—
0.3
UI
UI
Deterministic jitter at
3.125 Gbps
0.17
0.17
XAUI Receiver Jitter Tolerance (7)
Total jitter
—
—
> 0.65
> 0.37
> 0.65
> 0.37
UI
UI
Deterministic jitter
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–48
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 3 of 7)
–C3 and –I3
–C4 and –I4
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Typ
Max
Peak-to-peak jitter
Peak-to-peak jitter
Jitter frequency = 22.1 KHz
> 8.5
> 8.5
UI
UI
UI
Jitter frequency =
1.875 MHz
> 0.1
> 0.1
> 0.1
> 0.1
Peak-to-peak jitter
Jitter frequency = 20 MHz
PCIe Transmit Jitter Generation (8)
Total jitter at 2.5 Gbps (Gen1)—
x1, x4, and x8
Compliance pattern
Compliance pattern
—
—
—
—
0.25
0.25
—
—
—
—
0.25
—
UI
UI
Total jitter at 5 Gbps (Gen2)—
x1, x4, and x8
PCIe Receiver Jitter Tolerance (8)
Total jitter at 2.5 Gbps (Gen1)
Total jitter at 5 Gbps (Gen2)
Compliance pattern
Compliance pattern
> 0.6
> 0.6
UI
UI
Not supported
Not supported
PCIe (Gen 1) Electrical Idle Detect Threshold
VRX-IDLE-DETDIFFp-p (9)
Compliance pattern
65
—
175
65
—
175
UI
SRIO Transmit Jitter Generation (10)
Deterministic jitter
(peak-to-peak)
Data rate = 1.25, 2.5, 3.125 Gbps
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
UI
UI
Pattern = CJPAT
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
Total jitter (peak-to-peak)
SRIO Receiver Jitter Tolerance (10)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
Deterministic jitter tolerance
(peak-to-peak)
> 0.37
> 0.55
> 0.37
> 0.55
UI
UI
Combined deterministic and
random jitter tolerance (peak-to-
peak)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
Jitter frequency = 22.1 KHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
UI
UI
UI
Jitter frequency = 1.875 MHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter frequency = 20 MHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
GIGE Transmit Jitter Generation (11)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
Pattern = CRPAT
—
—
—
—
0.14
—
—
—
—
0.14
UI
UI
Total jitter (peak-to-peak)
0.279
0.279
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–49
Max
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 4 of 7)
–C3 and –I3
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
GIGE Receiver Jitter Tolerance (11)
Deterministic jitter tolerance
(peak-to-peak)
Pattern = CJPAT
Pattern = CJPAT
> 0.4
> 0.4
UI
UI
Combined deterministic and
random jitter tolerance (peak-to-
peak)
> 0.66
> 0.66
HiGig Transmit Jitter Generation
Data rate = 3.75 Gbps
Pattern = CJPAT
Deterministic jitter
(peak-to-peak)
—
—
—
—
0.17
0.35
—
—
—
—
—
—
UI
UI
Data rate = 3.75 Gbps
Pattern = CJPAT
Total jitter (peak-to-peak)
HiGig Receiver Jitter Tolerance
Data rate = 3.75 Gbps
Pattern = CJPAT
Deterministic jitter tolerance
(peak-to-peak)
> 0.37
> 0.65
—
—
—
—
—
—
UI
UI
Combined deterministic and
random jitter tolerance (peak-to-
peak)
Data rate = 3.75 Gbps
Pattern = CJPAT
Jitter frequency = 22.1 KHz
Data rate = 3.75 Gbps
Pattern = CJPAT
> 8.5
> 0.1
> 0.1
—
—
—
—
—
—
—
—
—
UI
UI
UI
Jitter frequency = 22.1 KHz
Data rate = 3.75 Gbps
Pattern = CJPAT
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter frequency = 22.1 KHz
Data rate = 3.75 Gbps
Pattern = CJPAT
(OIF) CEI Transmitter Jitter Generation
Data rate = 6.375 Gbps
Pattern = PRBS15 BER = 10-12
Total jitter (peak-to-peak)
—
—
0.3
—
—
0.3
UI
(OIF) CEI Receiver Jitter Tolerance
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
Deterministic jitter tolerance
(peak-to-peak)
> 0.675
> 0.988
—
—
—
—
—
—
UI
UI
Combined deterministic and
random jitter tolerance (peak-to-
peak)
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–50
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 5 of 7)
–C3 and –I3
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Max
Jitter Frequency = 38.2 KHz
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
Jitter Frequency = 3.82 MHz
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
Jitter Frequency = 20 MHz
Data rate = 6.375 Gbps
> 0.5
—
—
—
—
—
UI
Sinusoidal jitter tolerance (peak-
to-peak)
> 0.05
> 0.05
—
—
—
—
UI
UI
Pattern = PRBS31 BER = 10-12
SDI Transmitter Jitter Generation (12)
Data rate = 1.485 Gbps (HD)
Pattern = color bar Low-frequency
roll-off = 100 KHz
0.2
0.3
—
—
—
—
0.2
0.3
—
—
—
—
UI
UI
Alignment jitter
(peak-to-peak)
Data rate = 2.97 Gbps (3G) Pattern
= color bar Low-frequency roll-off
= 100 KHz
SDI Receiver Jitter Tolerance (12)
Jitter frequency = 15 KHz
> 2
> 2
UI
UI
UI
UI
UI
UI
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
Jitter frequency = 100 KHz
Sinusoidal jitter tolerance (peak-
to-peak)
> 0.3
> 0.3
> 1
> 0.3
> 0.3
> 1
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
Jitter frequency = 148.5 MHz
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
Jitter frequency = 20 KHz
Data rate = 1.485 Gbps (HD)
pattern = 75% color bar
Jitter frequency = 100 KHz
Sinusoidal jitter tolerance (peak-
to-peak)
> 0.2
> 0.2
> 0.2
> 0.2
Data rate = 1.485 Gbps (HD)
Pattern = 75% color bar
Jitter frequency = 148.5 MHz
Data rate = 1.485 Gbps (HD)
Pattern = 75% color bar
SAS Transmit Jitter Generation (13)
Total jitter at 1.5 Gbps (G1)
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
—
—
—
—
—
—
0.55
0.35
0.55
—
—
—
—
—
—
0.55
0.35
0.55
UI
UI
UI
Deterministic jitter at 1.5 Gbps
(G1)
Total jitter at 3.0 Gbps (G2)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–51
Switching Characteristics
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 6 of 7)
–C3 and –I3
–C4 and –I4
Typ
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
Max
Deterministic jitter at 3.0 Gbps
(G2)
Pattern = CJPAT
—
—
0.35
—
—
0.35
UI
Total jitter at 6.0 Gbps (G3)
Pattern = CJPAT
Pattern = CJPAT
—
—
—
—
0.25
0.15
—
—
—
—
0.25
0.15
UI
UI
Random jitter at 6.0 Gbps (G3)
SAS Receiver Jitter Tolerance (13)
Total jitter tolerance at 1.5 Gbps
(G1)
Pattern = CJPAT
Pattern = CJPAT
—
—
—
—
0.65
0.35
—
—
—
—
0.65
0.35
UI
UI
Deterministic jitter tolerance at
1.5 Gbps (G1)
Jitter frequency = 900 KHz to 5
MHz
Sinusoidal jitter tolerance at 1.5
Gbps (G1)
> 0.1
> 0.1
UI
Pattern = CJTPAT BER = 1E-12
CPRI Transmit Jitter Generation (14)
E.6.HV, E.12.HV
Pattern = CJPAT
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
UI
UI
UI
UI
Total jitter
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJPAT
E.6.HV, E.12.HV
Pattern = CJPAT
Deterministic jitter
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJPAT
CPRI Receiver Jitter Tolerance (14)
E.6.HV, E.12.HV
Pattern = CJPAT
Total jitter tolerance
> 0.66
> 0.4
> 0.66
> 0.4
UI
UI
UI
UI
UI
E.6.HV, E.12.HV
Deterministic jitter tolerance
Total jitter tolerance
Pattern = CJPAT
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJPAT
> 0.65
> 0.37
> 0.55
> 0.65
> 0.37
> 0.55
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJPAT
Deterministic jitter tolerance
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJPAT
Combined deterministic and
random jitter tolerance
OBSAI Transmit Jitter Generation (15)
REFCLK = 153.6 MHz
Pattern CJPAT
Total jitter at 768 Mbps, 1536
Mbps, and 3072 Mbps
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
UI
UI
REFCLK = 153.6 MHz
Pattern CJPAT
Deterministic jitter at 768 MBps,
1536 Mbps, and 3072 Mbps
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–52
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 7 of 7)
–C3 and –I3
–C4 and –I4
Typ Max
Symbol/
Conditions
Description
Unit
Min
Typ
Max
Min
OBSAI Receiver Jitter Tolerance (15)
Deterministic jitter tolerance at
768 Mbps, 1536 Mbps, and
3072 Mbps
Pattern = CJPAT
Pattern = CJPAT
> 0.37
> 0.55
> 0.37
> 0.55
UI
UI
Combined deterministic and
random jitter tolerance at 768
Mbps, 1536 Mbps, and 3072
Mbps
Jitter frequency = 5.4 KHz
Pattern = CJPAT
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
UI
UI
UI
UI
UI
UI
Sinusoidal jitter tolerance at 768
Mbps
Jitter frequency = 460 MHz to 20
MHz
Pattern = CJPAT
Jitter frequency = 10.9 KHz
Pattern = CJPAT
Sinusoidal jitter tolerance at
1536 Mbps
Jitter frequency = 921.6 MHz to 20
MHz
Pattern = CJPAT
Jitter frequency = 21.8 KHz
Pattern = CJPAT
Sinusoidal jitter tolerance at
3072 Mbps
Jitter frequency = 1843.2 MHz to
20 MHz
Pattern = CJPAT
Notes to Table 1–41:
(1) Dedicated refclkpins were used to drive the input reference clocks.
(2) The jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the T inter operability point.
(6) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at the R interpretability point.
(7) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(8) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(9) Arria II GZ PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(10) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(11) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(14) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(15) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–53
Switching Characteristics
Core Performance Specifications for the Arria II Device Family
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42 lists the clock tree specifications for Arria II GX devices.
Table 1–42. Clock Tree Performance for Arria II GX Devices
Performance
Clock Network
Unit
I3, C4
500
C5,I5
500
C6
GCLK and RCLK
PCLK
400
280
MHz
MHz
420
350
Table 1–43 lists the clock tree specifications for Arria II GZ devices.
Table 1–43. Clock Tree Performance for Arria II GZ Devices
Performance
Clock Network
Unit
–C3 and –I3
700
–C4 and –I4
500
GCLK and RCLK
PCLK
MHz
MHz
500
450
PLL Specifications
Table 1–44 lists the PLL specifications for Arria II GX devices.
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
Symbol
Description
Min
Typ
Max
Unit
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
5
—
670 (1)
MHz
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
fIN
5
5
—
—
622 (1)
500 (1)
MHz
MHz
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
fINPFD
fVCO
fINDUTY
fEINDUTY
Input frequency to the PFD
5
600
40
40
—
—
—
—
—
—
—
—
325
1,400
60
MHz
MHz
%
PLL VCO operating Range (2)
Input clock duty cycle
External feedback clock input duty cycle
Input clock cycle-to-cycle jitter (Frequency 100 MHz)
Input clock cycle-to-cycle jitter (Frequency 100 MHz)
60
%
0.15
750
UI (p–p)
ps (p–p)
tINCCJ (3),
(4)
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–54
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Symbol
Description
Min
Typ
Max
Unit
Output frequency for internal global or regional clock
(–4 Speed Grade)
—
—
500
MHz
Output frequency for internal global or regional clock
(–5 Speed Grade)
fOUT
—
—
—
—
500
400
MHz
MHz
Output frequency for internal global or regional clock
(–6 Speed Grade)
Output frequency for external clock output (–4 Speed Grade)
Output frequency for external clock output (–5 Speed Grade)
Output frequency for external clock output (–6 Speed Grade)
Duty cycle for external clock output (when set to 50%)
Dedicated clock output period jitter (fOUT 100 MHz)
Dedicated clock output period jitter (fOUT 100 MHz)
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
Regular I/O clock output period jitter (fOUT 100 MHz)
Regular I/O clock output period jitter (fOUT 100 MHz)
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
670 (5)
622 (5)
500 (5)
55
MHz
MHz
fOUT_EXT
MHz
tOUTDUTY
tOUTPJ_DC
%
300
ps (p–p)
mUI (p–p)
ps (p–p)
mUI (p–p)
ps (p–p)
mUI (p–p)
ps (p–p)
mUI (p–p)
30
300
tOUTCCJ_DC
30
650
fOUTPJ_IO
65
650
fOUTCCJ_IO
tCONFIGPLL
65
SCANCLK
cycles
Time required to reconfigure PLL scan chains
—
—
3.5
1
—
—
SCANCLK
cycles
tCONFIGPHASE Time required to reconfigure phase shift
fSCANCLK
tLOCK
SCANCLK frequency
—
—
—
—
100
1
MHz
ms
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
—
—
1
ms
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCL B W
tPLL_PSERR
tARESET
—
—
Minimum pulse width on aresetsignal
ns
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–55
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Symbol
tCASC_
Description
Min
Typ
Max
Unit
Period Jitter for dedicated clock output in cascaded PLLs
—
—
425
ps (p-p)
(FOUT 100 MHz)
OUTJITTER_
PERIOD_
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT 100 MHz)
DEDCLK
(6), (7)
—
—
42.5
mUI (p-p)
Notes to Table 1–44:
(1) fIN is limited by the I/O fMAX
.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
less than 200 ps.
(4) FREF is fIN/N when N = 1.
(5) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–62 on page 1–70.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
Max
717 (1)
717 (1)
325
Unit
MHz
MHz
MHz
MHz
MHz
%
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
fIN
fINPFD
fVCO
5
5
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
600
600
40
1,300
1,300
60
tEINDUTY
Output frequency for internal global or regional clock
(–3 speed grade)
—
—
—
—
700 (2)
500 (2)
MHz
MHz
fOUT
Output frequency for internal global or regional clock
(–4 speed grade)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
—
—
45
—
—
—
50
—
717 (2)
717 (2)
55
MHz
MHz
%
fOUT_EXT
tOUTDUTY
tFCOMP
10
ns
scanclk
cycles
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
fSCANCLK
tLOCK
Time required to reconfigure phase shift
scanclk frequency
—
—
—
1
—
100
1
—
—
MHz
Time required to lock from end-of-device configuration or
de-assertion of areset
ms
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–56
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2)
Symbol
tDLOCK
Parameter
Min
Typ
Max
Unit
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
—
—
—
—
10
—
—
—
—
0.3
1.5
4
—
—
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth (7)
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
—
—
50
ps
Minimum pulse width on the aresetsignal
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
Input clock cycle to cycle jitter (FREF < 100 MHz)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
—
ns
0.15
750
175
17.5
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
tINCCJ (3), (4)
tOUTPJ_DC (5)
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
175
17.5
600
60
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
tOUTCCJ_DC (5)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
tOUTPJ_IO (5),
(8)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
600
60
tOUTCCJ_IO (5),
(8)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
250
25
tCASC_OUTPJ_DC
(5), (6)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
Frequency drift after PFDENA is disabled for duration of
100 us
fDRIFT
10
Notes to Table 1–45:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(4) FREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–64 on page 1–71.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–63 on
page 1–71.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–57
Switching Characteristics
DSP Block Specifications
Table 1–46 lists the DSP block performance specifications for Arria II GX devices.
Table 1–46. DSP Block Performance Specifications for Arria II GX Devices (Note 1)
Resources
Used
Performance
Mode
Unit
Number of
Multipliers
C4
I3
C5,I5
C6
9 × 9-bit multiplier
1
1
1
1
380
380
380
350
310
310
310
270
300
300
300
270
250
250
250
220
MHz
MHz
MHz
MHz
12 × 12-bit multiplier
18 × 18-bit multiplier
36 × 36-bit multiplier
18 × 36-bit high-precision multiplier
adder mode
1
350
270
270
220
MHz
18 × 18-bit multiply accumulator
18 × 18-bit multiply adder
4
4
380
380
310
310
300
300
250
250
MHz
MHz
18 × 18-bit multiply adder-signed full
precision
2
2
380
275
310
220
300
220
250
180
MHz
MHz
18 × 18-bit multiply adder with
loopback (2)
36-bit shift (32-bit data)
Double mode
1
1
350
350
270
270
270
270
220
220
MHz
MHz
Notes to Table 1–46:
(1) Maximum is for a fully-pipelined block with Round and Saturation disabled.
(2) Maximum is for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled.
Table 1–47 lists the DSP block performance specifications for Arria II GZ devices.
Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 1 of 2)
Resources
Performance
Used
Mode
Unit
Number of
Multipliers
–3
–4
9 × 9-bit multiplier
1
1
1
1
4
4
460
500
550
440
440
470
400
440
480
380
380
410
MHz
MHz
MHz
MHz
MHz
MHz
12 × 12-bit multiplier
18 × 18-bit multiplier
36 × 36-bit multiplier
18 × 18-bit multiply accumulator
18 × 18-bit multiply adder
18 × 18-bit multiply adder-signed full
precision
2
450
390
MHz
18 × 18-bit multiply adder with
loopback (2)
2
1
350
440
310
380
MHz
MHz
36-bit shift (32-bit data)
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–58
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 2 of 2)
Resources
Performance
Used
Mode
Unit
Number of
Multipliers
–3
–4
380
Double mode
1
440
MHz
Notes to Table 1–47:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Embedded Memory Block Specifications
Table 1–48 lists the embedded memory block specifications for Arria II GX devices.
Table 1–48. Embedded Memory Block Performance Specifications for Arria II GX Devices
Resources Used
Embedded
Performance
Memory
Mode
Unit
ALUTs
I3
C4
C5,I5
450
C6
Memory
Single port 64 × 10
0
0
1
450
270
500
500
378
378
MHz
MHz
Memory
Logic
Array
Simple dual-port 32 × 20 single
clock
1
450
Block
(MLAB)
Simple dual-port 64 × 10 single
clock
0
0
1
1
428
360
500
400
450
360
378
310
MHz
MHz
Single-port 256 × 36
Single-port 256 × 36, with the
read-during-write option set to
Old Data
0
0
1
1
250
360
280
400
250
360
210
310
MHz
MHz
Simple dual-port 256 × 36 single
CLK
Single-port 256 × 36 single CLK,
with the read-during-write option
set to Old Data
M9K
Block
0
0
0
1
1
1
250
360
250
280
400
280
250
360
250
210
310
210
MHz
MHz
MHz
True dual port 512 × 18 single CLK
True dual-port 512 × 18 single CLK,
with the read-during-write option
set to Old Data
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
—
—
—
—
900
730
850
690
950
770
1130
920
ps
ps
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–59
Switching Characteristics
Table 1–49 lists the embedded memory block specifications for Arria II GZ devices.
Table 1–49. Embedded Memory Block Performance Specifications for Arria II GZ Devices (Note 1)
Resources Used
Performance
Memory
Mode
Unit
TriMatrix
ALUTs
C3
I3
C4
I4
Memory
Single port 64 × 10
0
0
0
0
0
0
0
1
1
1
1
1
1
1
500
500
500
500
500
540
490
500
500
500
500
500
540
490
450
450
450
450
450
475
420
450
450
450
450
450
475
420
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Simple dual-port 32 × 20
Simple dual-port 64 × 10
ROM 64 × 10
MLAB
(2)
ROM 32 × 20
Single-port 256 × 36
Simple dual-port 256 × 36
Simple dual-port 256 × 36, with the
read-during-write option set to Old
Data
0
0
0
1
1
1
340
430
335
340
430
335
300
370
290
300
370
290
MHz
MHz
MHz
True dual port 512 × 18
M9K
Block (2)
True dual-port 512 × 18, with the
read-during-write option set to Old
Data
ROM 1 Port
0
0
1
1
540
540
800
625
440
435
540
540
800
625
400
375
475
475
850
690
380
385
475
475
850
690
350
325
MHz
MHz
ps
ROM 2 Port
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
Single-port 2K × 72
—
—
0
—
—
1
ps
MHz
MHz
Simple dual-port 2K × 72
0
1
Simple dual-port 2K × 72, with the
read-during-write option set to Old
Data
0
1
240
225
205
200
MHz
Simple dual-port 2K × 64 (with ECC)
True dual-port 4K × 36
0
0
1
1
300
375
295
350
255
330
250
310
MHz
MHz
M144K
Block (2)
True dual-port 4K × 36, with the
read-during-write option set to Old
Data
0
1
230
225
205
200
MHz
ROM 1 Port
0
0
1
1
500
465
755
625
450
425
860
690
435
400
860
690
420
400
950
690
MHz
MHz
ps
ROM 2 Port
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
—
—
—
—
ps
Notes to Table 1–48:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection CRC feature, there is no degradation in FMAX
.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–60
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Configuration
Table 1–50 lists the configuration mode specifications for Arria II GX and GZ devices.
Table 1–50. Configuration Mode Specifications for Arria II Devices
DCLK Frequency
Programming Mode
Unit
Min
—
Typ
—
—
26
13
—
Max
125
125
40
Passive serial
MHz
MHz
MHz
MHz
MHz
Fast passive parallel
—
Fast active serial (fast clock)
Fast active serial (slow clock)
Remote update only in fast AS mode
17
8.5
—
20
10
JTAG Specifications
Table 1–51 lists the JTAG timing parameters and values for Arria II GX and GZ
devices.
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Symbol
tJCP
Description
Min
30
14
14
1
Max
—
—
—
—
—
—
11
14
14
Unit
TCK clock period
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
TCK clock low time
tJCL
tJPSU (TDI)
TDI JTAG port setup time
tJPSU (TMS) TMS JTAG port setup time
3
tJPH
JTAG port hold time
5
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
—
—
—
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52 lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
and GZ devices.
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Description
Min
Typ
Max
Unit
Dev_CLRn
500
—
—
s
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–61
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfaces, for example the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O (GPIO) standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS
are capable of typical 200 MHz interfacing frequency with 10pF load.
1
Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–53 lists the high-speed I/O timing for Arria II GX devices.
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 1 of 4)
I3
C4
C5,I5
C6
Symbol
Clock
Conditions
Unit
Min
Max
Min
Max
Min
Max
Min
Max
fHSCLK_IN
Clock boost
factor, W =
1 to 40 (1)
(input clock
frequency)–Row
I/O
5
5
5
5
670
500
670
500
5
5
5
5
670
500
670
500
5
5
5
5
622
5
5
5
5
500
472.5
500
MHz
MHz
MHz
MHz
fHSCLK_IN
Clock boost
factor, W =
1 to 40 (1)
(input clock
frequency)–
Column I/O
472.5
622
fHSCLK_OUT
(output clock
frequency)–Row
I/O
—
—
fHSCLK_OUT
(output clock
frequency)–
Column I/O
472.5
472.5
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–62
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 2 of 4)
I3
C4
C5,I5
C6
Symbol
Conditions
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Transmitter
SERDES factor,
J = 3 to 10
(using
1250
(2)
1250
(2)
1050
(2)
150
150
150
150
840
Mbps
Mbps
dedicated
SERDES)
SERDES factor,
J = 4 to 10
(using logic
elements as
SERDES)
fHSDR_TX (true
LVDS output data
rate)
(3)
(3)
(3)
945
(3)
(3)
(3)
(3)
945
(3)
(3)
(3)
(3)
840
(3)
(3)
(3)
(3)
740
(3)
SERDES factor,
J = 2 (using
DDR registers)
and J = 1
(using SDR
register)
Mbps
Mbps
fHSDR_TX_E3R
(emulated
LVDS_E_3R
output data rate)
(7)
SERDES factor,
J = 4 to 10
945
945
840
740
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–63
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 3 of 4)
I3
C4
C5,I5
C6
Symbol
Conditions
Unit
Min
Max
Min
Max
Min
Max
Min
Max
True LVDS with
dedicated
SERDES
(data rate
600–1,250
Mbps)
—
175
—
175
—
225
—
300
ps
UI
True LVDS with
dedicated
SERDES
(data rate
< 600 Mbps)
—
—
0.105
260
—
—
0.105
260
—
—
0.135
300
—
—
0.18
350
True LVDS and
emulated
LVDS_E_3R
with logic
elements as
SERDES (data
rate 600
tTX_JITTER (4)
ps
UI
– 945 Mbps)
True LVDS and
emulated
LVDS_E_3R
with logic
elements as
SERDES
—
0.16
—
0.16
—
0.18
—
0.21
(data rate
< 600 Mbps)
True LVDS and
emulated
LVDS_E_3R
tTX_DCD
45
—
—
—
55
45
—
—
—
55
45
—
—
—
55
45
—
—
—
55
%
ps
ps
ps
True LVDS and
emulated
LVDS_E_3R
tRISE and tFALL
200
150
200
200
150
200
225
175
250
250
200
300
True LVDS (5)
TCCS
Emulated
LVDS_E_3R
Receiver (6)
True differential
I/O standards -
fHSDRDPA (data
rate)
SERDES factor
J = 3 to 10
150
1250
150
1250
150
1050
150
840
Mbps
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–64
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4)
I3
C4
C5,I5
C6
Symbol
Conditions
Unit
Mbps
Mbps
Min
Max
Min
Max
Min
Max
Min
Max
SERDES factor
J = 3 to 10
945
(7)
945
(7)
740
(7)
640
(7)
(3)
(3)
(3)
(3)
SERDES factor
J = 2 (using
DDR registers)
(3)
(3)
(7)
(7)
(3)
(3)
(7)
(7)
(3)
(3)
(7)
(3)
(3)
(7)
(7)
fHSDR (data rate)
SERDES factor
J = 1 (using
(7)
Mbps
SDR registers)
Soft-CDR PPM
tolerance
Soft-CDR
mode
—
—
—
300
10,000
300
—
—
—
300
10,000
300
—
—
—
300
—
—
—
300
10,000
400
PPM
UI
DPA run length
DPA mode
10,000
350
Sampling
window (SW)
Non-DPAmode
ps
(5)
Notes to Table 1–53:
(1) fHSCLK_IN = fHSDR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
(2) Applicable for interfacing with DPA receivers only. For interfacing with non-DPA receivers, you must calculate the leftover timing margin in the
receiver by performing link timing closure analysis. For Arria II GX transmitter to Arria II GX non-DPA receiver, the maximum supported data
rate is 945 Mbps. For data rates above 840 Mbps, perform PCB trace compensation by adjusting the PCB trace length for LVDS channels to
improve channel-to-channel skews.
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
(4) The specification is only applicable under the influence of core noise.
(5) Applicable for true LVDS using dedicated SERDES only.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
Table 1–54 lists the high-speed I/O timing for Arria II GZ devices.
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 1 of 3)
C3, I3
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
Clock
HSCLK_in (input clock
frequency) true
differential I/O
standards
f
Clock boost factor
W = 1 to 40 (3)
5
5
5
—
—
—
717
717
420
5
5
5
—
—
—
717
717
420
MHz
MHz
MHz
fHSCLK_in (input clock
frequency) single
ended I/O standards
(9)
Clock boost factor
W = 1 to 40 (3)
fHSCLK_in (input clock
frequency) single
ended I/O standards
(10)
Clock boost factor
W = 1 to 40 (3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–65
Switching Characteristics
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 2 of 3)
C3, I3
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
fHSCLK_OUT (output
clock frequency)
—
5
—
717 (7)
5
—
717 (7)
MHz
Transmitter
SERDES factor, J = 3
to 10
(using dedicated
SERDES) (8)
(4)
—
1250
(4)
—
1250
Mbps
fHSDR (true LVDS
output data rate)
SERDES factor J = 2,
(using DDR registers)
(4)
(4)
—
—
(5)
(5)
(4)
(4)
—
—
(5)
(5)
Mbps
Mbps
SERDES factor J = 1,
(uses an SDR
register)
fHSDR (emulated
LVDS_E_3R output
data rate) (5)
(4)
(4)
—
—
1152
200
(4)
(4)
—
—
800
200
Mbps
Mbps
SERDES factor J = 4
to 10
fHSDR (emulated
LVDS_E_1R output
data rate)
Total jitter for data
rate, 600 Mbps to
1.6 Gbps
—
—
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
—
—
160
0.1
ps
UI
ps
UI
tx Jitter
Total jitter for data
rate, < 600 Mbps
Total jitter for data
rate, 600 Mbps to
1.25 Gbps
tx Jitter - emulated
differential I/O
standards with three
external output resistor
network
300
0.2
325
0.25
Total jitter for data
rate < 600 Mbps
tx Jitter - emulated
differential I/O
standards with one
external output resistor
network
—
—
45
—
50
0.15
55
—
45
—
50
0.15
55
UI
%
TX output clock duty
cycle for both True
and emulated
tDUTY
differential I/O
standards
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 3 of 3)
C3, I3
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
True differential I/O
standards
—
—
200
—
—
200
ps
Emulated differential
I/O standards with
three external output
resistor networks
—
—
—
250
500
—
—
—
300
500
ps
ps
tRISE & tFALL
Emulated differential
I/O standards with
one external output
resistor
—
—
True LVDS
—
—
—
—
100
250
—
—
—
—
100
250
ps
ps
TCCS
Emulated
LVDS_E_3R
Receiver
True differential I/O
standards - fHSDRDPA
(data rate)
SERDES factor
J = 3 to 10
150
—
1250
150
—
1250
Mbps
SERDES factor
J = 3 to 10
(4)
(4)
—
—
(6)
(5)
(4)
(4)
—
—
(6)
(5)
Mbps
Mbps
SERDES factor J = 2,
uses DDR registers
fHSDR (data rate)
SERDES factor J = 1,
uses an SDR register
(4)
—
—
—
—
—
(5)
10000
300
(4)
—
—
—
—
—
(5)
10000
300
Mbps
UI
DPA run length
DPA mode
Soft-CDR PPM
tolerance
Soft-CDR mode
PPM
Sampling Window
(SW)
Non-DPA mode
—
—
300
—
—
300
ps
Notes to Table 1–54:
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
Table 1–55 lists DPA lock time specifications for Arria II GX and GZ devices.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–67
Switching Characteristics
Table 1–55. DPA Lock Time Specifications for Arria II Devices (Note 1), (2), (3)
Number of Data
Number of
Transitions in One
Repetition of the
Training Pattern
Repetitions per
256 Data
Standard
Training Pattern
Maximum
Transitions (4)
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 1–55:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 1–5 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
Arria II GZ devices at a data rate less than 1.25 Gbps and all the Arria II GX devices.
Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for All Arria II GX Devices and for Arria II GZ
Devices at a Data Rate less than 1.25 Gbps
Sinusoidal Jitter Amplitude (UI)
20db/dec
0.1
P-P
Jitter Frequency (Hz)
20,000,000
baud/1667
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Figure 1–6 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
Arria II GZ devices at 1.25 Gbps data rate.
Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for Arria II GZ Devices at a 1.25 Gbps Data Rate
Sinusoidal Jitter Amplitude (UI)
25
8.5
0.35
0.1
Jitter Frequency (Hz)
50,000,000 (F4)
10,000 (F1) 17,565 (F2)
1,493,000 (F3)
Table 1–56 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
Arria II GZ devices at 1.25 Gbps data rate.
Table 1–56. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Arria II GZ Devices at
1.25 Gbps Data Rate
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
25.000
F1
F2
F3
F4
10,000
17,565
25.000
1,493,000
50,000,000
0.350
0.350
External Memory Interface Specifications
f
For the maximum clock rate supported for Arria II GX and GZ device family, refer to
the External Memory Interface Spec Estimator page on the Altera website.
Table 1–57 lists the external memory interface specifications for Arria II GX devices.
Table 1–57. External Memory Interface Specifications for Arria II GX Devices (Part 1 of 2)
Frequency Range (MHz)
DQS Delay
Buffer Mode
(1)
Frequency
Mode
Resolution
(°)
Number of
Delay Chains
C4
I3, C5, I5
C6
0
1
2
3
4
90-140
110-180
140-220
170-270
220-340
90-130
110-170
140-210
170-260
220-310
90-110
110-150
140-180
170-220
220-270
22.5
30
Low
Low
Low
Low
High
16
12
10
8
36
45
30
12
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–69
Switching Characteristics
Table 1–57. External Memory Interface Specifications for Arria II GX Devices (Part 2 of 2)
Frequency Range (MHz)
DQS Delay
Buffer Mode
(1)
Frequency
Mode
Resolution
(°)
Number of
Delay Chains
C4
I3, C5, I5
C6
5
270-410
320-450
270-380
320-410
270-320
320-370
36
45
High
High
10
8
6
Note to Table 1–57:
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Table 1–58 lists the DLL frequency range specifications for Arria II GZ devices.
Table 1–58. DLL Frequency Range Specifications for Arria II GZ Devices
Frequency Range (MHz)
DQS Delay
Buffer Mode
(1)
Number of
Delay
Chains
Frequency Mode
Available Phase Shift
–3
–4
0
90-130
120-170
150-210
180-260
240-320
290-380
360-450
470-630
90-120
120-160
150-200
180-240
240-290
290-360
360-450
470-590
22.5°, 45°, 67.5°, 90°
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°,135°, 180°
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
60°, 120°, 180°, 240°
Low
Low
Low
Low
High
High
High
High
16
12
10
8
1
2
3
4
12
10
8
5
6
7
6
Note to Table 1–58:
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Table 1–59 lists the DQS phase offset delay per stage for Arria II GX devices.
Table 1–59. DQS Phase Offset Delay Per Setting for Arria II GX Devices (Note 1), (2), (3)
Speed Grade
C4
Min
7.0
7.0
8.5
Max
13.0
15.0
18.0
Unit
ps
I3, C5, I5
C6
ps
ps
Notes to Table 1–59:
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
4 to 5.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear.
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–60 lists the DQS phase shift error for Arria II GX devices.
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GX
Devices (Note 1)
Number of DQS Delay Buffer
C4
I3, C5, I5
C6
Unit
1
2
3
26
52
30
60
36
72
ps
ps
ps
ps
78
90
108
144
4
104
120
Note to Table 1–60:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a C4 speed grade is 78 ps or 39 ps.
Table 1–61 lists the DQS phase shift error for Arria II GZ devices.
Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GZ
Devices (Note 1)
Number of DQS Delay Buffer
–3
–4
Unit
1
2
3
28
56
30
60
ps
ps
ps
ps
84
90
4
112
120
Note to Table 1–61:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a 3 speed grade is 84 ps or 42 ps.
Table 1–62 lists the memory output clock jitter specifications for Arria II GX devices.
Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices (Note 1), (2), (3)
–4
–5
–6
Clock
Network
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Global
Global
Global
tJIT(per)
tJIT(cc)
-100
100
-125
125
-125
125
ps
ps
ps
Cycle-to-cycle period
jitter
-200
-100
200
100
-250
-125
250
125
-250
-125
250
125
Duty cycle jitter
tJIT(duty)
Notes to Table 1–62:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
(3) The memory output clock jitter stated in Table 1–62 is applicable when an input jitter of 30 ps is applied.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–71
Switching Characteristics
Table 1–63 lists the memory output clock jitter specifications for Arria II GZ devices.
Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices (Note 1), (2), (3)
–3
–4
Clock
Parameter
Symbol
Unit
Network
Min
-55
Max
55
Min
-55
Max
55
Clock period jitter
Regional
Regional
Regional
Global
tJIT(per)
tJIT(cc)
ps
ps
ps
ps
ps
ps
Cycle-to-cycle period jitter
Duty cycle jitter
-110
-82.5
-82.5
-165
-90
110
82.5
82.5
165
90
-110
-82.5
-82.5
-165
-90
110
82.5
82.5
165
90
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
Cycle-to-cycle period jitter
Global
Duty cycle jitter
Global
tJIT(duty)
Notes to Table 1–63:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–63 is applicable when an input jitter of 30 ps is applied.
Duty Cycle Distortion (DCD) Specifications
Table 1–64 lists the worst-case DCD specifications for Arria II GX devices.
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices (Note 1)
C4
I3, C5, I5
C6
Symbol
Unit
Min
Max
Min
45
Max
Min
Max
Output Duty Cycle
45
55
55
45
55
%
Note to Table 1–64:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
Table 1–65 lists the worst-case DCD specifications for Arria II GZ devices.
Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices (Note 1)
C3, I3
C4, I4
Symbol
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Note to Table 1–65:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
IOE Programmable Delay
Table 1–66 lists the delay associated with each supported IOE programmable delay
chain for Arria II GX devices.
Table 1–66. IOE Programmable Delay for Arria II GX Devices
Maximum Offset
Available Minimum
Parameter
Settings
Offset
Fast Model
C4
Slow Model
C5
Unit
(1)
(2)
I3
I5
I3
C4
I5
C6
Output
enable pin
delay
7
7
0
0
0.413
0.442
0.413
0.814
0.713
0.796
0.801
0.873
ns
ns
Delay from
output
register to
output pin
0.339
0.362
0.339
0.671
0.585
0.654
0.661
0.722
Input delay
from pin to
internal cell
52
52
4
0
0
0
1.494
1.493
0.074
1.607
1.607
0.076
1.494
1.493
0.074
2.895
2.896
0.140
2.520
2.503
0.124
2.733
2.732
0.147
2.775
2.774
0.147
2.944
2.944
0.167
ns
ns
ns
Input delay
from pin to
input register
DQS bus to
inputregister
delay
Notes to Table 1–66:
(1) The available setting for every delay chain starts with zero and ends with the specified maximum number of settings.
(2) The minimum offset represented in the table does not include intrinsic delay.
Table 1–67 lists the IOE programmable delay settings for Arria II GZ devices.
Table 1–67. IOE Programmable Delay for Arria II GZ Devices
Maximum Offset
Available
Settings
(1)
Minimum
Offset (2)
Parameter
Fast Model
Industrial Commercial
Slow Model
Unit
C3
I3
C4
I4
D1
D2
D3
D4
D5
D6
15
7
0
0
0
0
0
0
0.462
0.234
1.700
0.508
0.472
0.186
0.505
0.232
1.769
0.554
0.500
0.195
0.795
0.372
2.927
0.882
0.799
0.319
0.801
0.371
2.948
0.889
0.817
0.321
0.857
0.407
3.157
0.952
0.875
0.345
0.864
0.405
3.178
0.959
0.882
0.347
ns
ns
ns
ns
ns
ns
7
15
15
6
Notes to Table 1–67:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) Minimum offset does not include the intrinsic delay.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–73
I/O Timing
I/O Timing
Altera offers two ways to determine I/O timing:
■
Using the Microsoft Excel-based I/O Timing.
Using the Quartus II Timing Analyzer.
■
The Microsoft Excel-based I/O Timing provides pin timing performance for each
device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis. The
Quartus II timing analyzer provides a more accurate and precise I/O timing data
based on the specifics of the design after place-and-route is complete.
f
The Microsoft Excel-based I/O Timing spreadsheet is downloadable from the
Literature: Arria II Devices web page.
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Chapter 1: Device Datasheet for Arria II Devices
Glossary
Glossary
Table 1–68 lists the glossary for this chapter.
Table 1–68. Glossary (Part 1 of 4)
Letter
Subject
Definitions
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p − n = 0 V
V
ID
A,
B,
C,
D
Differential I/O
Standards
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p − n = 0 V
V
OD
fHSCLK
fHSDR
Left/Right PLL input clock frequency.
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
E,
F
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–75
Glossary
Table 1–68. Glossary (Part 2 of 4)
Letter
Subject
Definitions
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
J
TMS
G,
H,
I,
TDI
tJCP
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
J
TCK
TDO
tJPXZ
tJPZX
tJPCO
PLL Specification parameters:
Diagram of PLL Specifications (1)
CLKOUT Pins
fOUT_EXT
Switchover
K,
L,
M,
N,
O,
P
CLK
fIN
fINPFD
N
/K
GCLK
RCLK
fVCO
fOUT
PFD
CP
LF
VCO
K
(2)
Counters
C0..C9
Core Clock
PLL
Specifications
M
Key
External Feedback
Reconfigurable in User Mode
Notes:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
(2) This is the VCO post-scale counter K.
Q,
R
RL
Receiver differential input discrete resistor (external to the Arria II device).
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Chapter 1: Device Datasheet for Arria II Devices
Glossary
Table 1–68. Glossary (Part 3 of 4)
Letter
Subject
Definitions
The period of time during which the data must be valid in order to capture it correctly. The setup
and hold times determine the ideal strobe position within the sampling window:
Timing Diagram
SW (sampling
window)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
Voltage
VCCIO
ReferencedI/O
Standard
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver and transmitter input and output clock period.
TCCS
The timing difference between the fastest and slowest output edges, including tCO variation and
clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
(channel-to-
channel-
skew)
High-speed I/O block: Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
T
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%).
tOUTPJ_IO
tOUTPJ_DC
tRISE
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
Chapter 1: Device Datasheet for Arria II Devices
1–77
Document Revision History
Table 1–68. Glossary (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC common mode input voltage.
VICM
Input common mode voltage: The common mode of the differential signal at the receiver.
Input differential voltage swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage: Minimum AC input differential voltage required for switching.
DC differential input voltage: Minimum DC input differential voltage required for switching.
Voltage input high: The minimum positive voltage applied to the input which is accepted by the
device as a logic high.
VIH
U,
V
VIH(AC)
VIH(DC)
High-level AC input voltage.
High-level DC input voltage.
Voltage input low: The maximum positive voltage applied to the input which is accepted by the
device as a logic low.
VIL
VIL(AC)
VIL(DC)
VOCM
Low-level AC input voltage.
Low-level DC input voltage.
Output common mode voltage: The common mode of the differential signal at the transmitter.
Output differential voltage swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VOD
W,
X,
Y,
W
High-speed I/O block: The clock boost factor.
Z
Document Revision History
Table 1–69 lists the revision history for this chapter.
Table 1–69. Document Revision History (Part 1 of 2)
Date
Version
Changes
December 2013
4.4
Updated Table 1–34 and Table 1–35.
■ Updated the VCCH_GXBL/R operating conditions in Table 1–6.
■ Finalized Arria II GZ information in Table 1–20.
July 2012
4.3
4.2
4.1
■ Added BLVDS specification in Table 1–32 and Table 1–33.
■ Updated input and output waveforms in Table 1–68.
■ Updated Table 1–32, Table 1–33, Table 1–34, Table 1–35, Table 1–40, Table 1–41,
Table 1–54, and Table 1–67.
December 2011
June 2011
■ Minor text edits.
■ Added Table 1–60.
■ Updated Table 1–32, Table 1–33, Table 1–38, Table 1–41, and Table 1–61.
■ Updated the “Switching Characteristics” section introduction.
■ Minor text edits.
December 2013 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1–78
Chapter 1: Device Datasheet for Arria II Devices
Document Revision History
Table 1–69. Document Revision History (Part 2 of 2)
Date
Version
Changes
■ Added Arria II GZ information.
■ Added Table 1–61 with Arria II GX information.
■ Updated Table 1–1, Table 1–2, Table 1–5, Table 1–6, Table 1–7, Table 1–11, Table 1–35,
Table 1–37, Table 1–40, Table 1–42, Table 1–44, Table 1–45, Table 1–57, Table 1–61, and
Table 1–63.
December 2010
4.0
■ Updated Figure 1–5.
■ Updated for the Quartus II version 10.0 release.
■ Updated the first paragraph for searchability.
■ Minor text edits.
■ Updated Table 1–1, Table 1–4, Table 1–16, Table 1–19, Table 1–21, Table 1–23,
Table 1–25, Table 1–26, Table 1–30, and Table 1–35
■ Added Table 1–27 and Table 1–29.
■ Added I3 speed grade information to Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Table 1–35.
July 2010
3.0
■ Updated the “Operating Conditions” section.
■ Removed “Preliminary” from Table 1–19, Table 1–21, Table 1–22, Table 1–23,
Table 1–24, Table 1–25, Table 1–26, Table 1–28, Table 1–30, Table 1–32, Table 1–33,
Table 1–34, and Figure 1–4.
■ Minor text edits.
Updated for the Quartus II version 9.1 SP2 release:
■ Updated Table 1–3, Table 1–7, Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25 and Table 1–33.
March 2010
2.3
■ Updated “Recommended Operating Conditions” section.
■ Minor text edits.
February 2010
February 2010
2.2
2.1
Updated Table 1–19.
Updated for Arria II GX v9.1 SP1 release:
■ Updated Table 1–19, Table 1–23, Table 1–28, Table 1–30, and Table 1–33.
■ Added Figure 1–5.
■ Minor text edits.
Updated for Arria II GX v9.1 release:
■ Updated Table 1–1, Table 1–4, Table 1–13, Table 1–14, Table 1–19, Table 1–15,
Table 1–22, Table 1–24, and Table 1–28.
■ Added Table 1–6 and Table 1–33.
■ Added “Bus Hold” on page 1–5.
■ Added “IOE Programmable Delay” section.
■ Minor text edit.
November 2009
2.0
1.2
■ Updated Table 1–1, Table 1–3, Table 1–7, Table 1–8, Table 1–18, Table 1–23, Table 1–25,
Table 1–26, Table 1–29, Table 1–30, Table 1–31, Table 1–32, and Table 1–33.
June 2009
■ Added Table 1–32.
■ Updated Equation 1–1.
Added “I/O Timing” section.
Initial release.
March 2009
1.1
1.0
February 2009
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2013 Altera Corporation
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