EP2S180F1508C3N [INTEL]
Field Programmable Gate Array, 8970 CLBs, 717MHz, 179400-Cell, CMOS, PBGA1508, 40 X 40 MM, 1 MM PITCH, LEAD FREE, FBGA-1508;
| 型号： | EP2S180F1508C3N |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 8970 CLBs, 717MHz, 179400-Cell, CMOS, PBGA1508, 40 X 40 MM, 1 MM PITCH, LEAD FREE, FBGA-1508 时钟 栅 现场可编程门阵列 可编程逻辑 |
| 文件： | 总248页 (文件大小：2983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stratix II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SII5V1-4.5
Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liabil-
ity arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest ver-
sion of device specifications before relying on any published information and before placing orders for
products or services.
ii
Altera Corporation
Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ................................................................................ i
How to Contact Altera ............................................................................................................................... i
Typographic Conventions ......................................................................................................................... i
Section I. Stratix II Device Family Data Sheet
Revision History ....................................................................................................................... Section I–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Document Revision History ................................................................................................................. 1–6
Chapter 2. Stratix II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–4
LAB Control Signals ......................................................................................................................... 2–5
Adaptive Logic Modules ...................................................................................................................... 2–6
ALM Operating Modes ................................................................................................................... 2–9
Register Chain ................................................................................................................................. 2–20
Clear & Preset Logic Control ........................................................................................................ 2–22
MultiTrack Interconnect ..................................................................................................................... 2–22
TriMatrix Memory ............................................................................................................................... 2–28
Memory Block Size ......................................................................................................................... 2–29
Digital Signal Processing Block ......................................................................................................... 2–40
Modes of Operation ....................................................................................................................... 2–44
DSP Block Interface ........................................................................................................................ 2–44
PLLs & Clock Networks ..................................................................................................................... 2–48
Global & Hierarchical Clocking ................................................................................................... 2–48
Enhanced & Fast PLLs ................................................................................................................... 2–57
Enhanced PLLs ............................................................................................................................... 2–68
Fast PLLs .......................................................................................................................................... 2–69
I/O Structure ........................................................................................................................................ 2–69
Double Data Rate I/O Pins ........................................................................................................... 2–77
External RAM Interfacing ............................................................................................................. 2–81
Programmable Drive Strength ..................................................................................................... 2–83
Altera Corporation
iii
Contents
Stratix II Device Handbook, Volume 1
Open-Drain Output ........................................................................................................................ 2–84
Bus Hold .......................................................................................................................................... 2–84
Programmable Pull-Up Resistor .................................................................................................. 2–85
Advanced I/O Standard Support ................................................................................................ 2–85
On-Chip Termination .................................................................................................................... 2–89
MultiVolt I/O Interface ................................................................................................................. 2–93
High-Speed Differential I/O with DPA Support ............................................................................ 2–96
Dedicated Circuitry with DPA Support .................................................................................... 2–100
Fast PLL & Channel Layout ........................................................................................................ 2–102
Document Revision History ............................................................................................................. 2–104
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–4
Configuration ......................................................................................................................................... 3–4
Operating Modes .............................................................................................................................. 3–5
Configuration Schemes ................................................................................................................... 3–7
Configuring Stratix II FPGAs with JRunner ............................................................................... 3–10
Programming Serial Configuration Devices with SRunner ..................................................... 3–10
Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 3–11
PLL Reconfiguration ...................................................................................................................... 3–11
Temperature Sensing Diode (TSD) ................................................................................................... 3–11
Automated Single Event Upset (SEU) Detection ............................................................................ 3–13
Custom-Built Circuitry .................................................................................................................. 3–14
Software Interface ........................................................................................................................... 3–14
Document Revision History ............................................................................................................... 3–14
Chapter 4. Hot Socketing & Power-On Reset
Stratix II
Hot-Socketing Specifications ............................................................................................................... 4–1
Devices Can Be Driven Before Power-Up .................................................................................... 4–2
I/O Pins Remain Tri-Stated During Power-Up ........................................................................... 4–2
Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power Supplies .................................... 4–2
Hot Socketing Feature Implementation in Stratix II Devices .......................................................... 4–3
Power-On Reset Circuitry .................................................................................................................... 4–5
Document Revision History ................................................................................................................. 4–6
Chapter 5. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 5–1
Absolute Maximum Ratings ........................................................................................................... 5–1
Recommended Operating Conditions .......................................................................................... 5–2
DC Electrical Characteristics .......................................................................................................... 5–3
I/O Standard Specifications ........................................................................................................... 5–4
Bus Hold Specifications ................................................................................................................. 5–17
On-Chip Termination Specifications ........................................................................................... 5–17
Pin Capacitance .............................................................................................................................. 5–19
Power Consumption ........................................................................................................................... 5–20
iv
Altera Corporation
Contents
Contents
Timing Model ....................................................................................................................................... 5–20
Preliminary & Final Timing .......................................................................................................... 5–20
I/O Timing Measurement Methodology .................................................................................... 5–21
Performance .................................................................................................................................... 5–27
Internal Timing Parameters .......................................................................................................... 5–34
Stratix II Clock Timing Parameters .............................................................................................. 5–41
Clock Network Skew Adders ....................................................................................................... 5–50
IOE Programmable Delay ............................................................................................................. 5–51
Default Capacitive Loading of Different I/O Standards .......................................................... 5–52
I/O Delays ....................................................................................................................................... 5–54
Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66
Duty Cycle Distortion ......................................................................................................................... 5–77
DCD Measurement Techniques ................................................................................................... 5–78
High-Speed I/O Specifications .......................................................................................................... 5–87
PLL Timing Specifications .................................................................................................................. 5–91
External Memory Interface Specifications ....................................................................................... 5–94
JTAG Timing Specifications ............................................................................................................... 5–96
Document Revision History ............................................................................................................... 5–97
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Document Revision History ................................................................................................................. 6–2
Altera Corporation
v
Contents
Stratix II Device Handbook, Volume 1
vi
Altera Corporation
Chapter Revision Dates
The chapters in this book, Stratix II Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised:
May 2007
Part number: SII51001-4.2
Chapter 2. Stratix II Architecture
Revised:
May 2007
Part number: SII51002-4.3
Chapter 3. Configuration & Testing
Revised:
May 2007
Part number: SII51003-4.2
Chapter 4. Hot Socketing & Power-On Reset
Revised:
May 2007
Part number: SII51004-3.2
Chapter 5. DC & Switching Characteristics
Revised:
April 2011
Part number: SII51005-4.5
Chapter 6. Reference & Ordering Information
Revised:
April 2011
Part number: SII51006-2.2
Altera Corporation
vii
Chapter Revision Dates
Stratix II Device Handbook, Volume 1
viii
Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Stratix® II family of devices.
For the most up-to-date information about Altera products, refer to the
following table.
How to Contact
Altera
Contact
Method
Contact (1)
Address
Technical support
Website
www.altera.com/support
www.altera.com/training
custrain@altera.com
Technical training
Website
Email
Product literature
Email
www.altera.com/literature
literature@altera.com
nacomp@altera.com
Altera literature services
Website
Non-technical support (General) Email
(Software Licensing)
Email
authorization@altera.com
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Typographic
Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital Document titles are shown in italic type with initial capital letters. Example: AN 75:
Letters
High-Speed Board Design.
Altera Corporation
i
Preliminary
Typographic Conventions
Stratix II Device Handbook, Volume 1
Visual Cue
Meaning
Italic type
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters
“Subheading Title”
Courier type
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input.Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
●
•
Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
v
1
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
c
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
w
r
f
The angled arrow indicates you should press the Enter key.
The feet direct you to more information on a particular topic.
ii
Preliminary
Altera Corporation
Section I. Stratix II Device
Family Data Sheet
This section provides the data sheet specifications for Stratix® II devices.
This section contains feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
■
■
■
■
■
■
Chapter 1, Introduction
Chapter 2, Stratix II Architecture
Chapter 3, Configuration & Testing
Chapter 4, Hot Socketing & Power-On Reset
Chapter 5, DC & Switching Characteristics
Chapter 6, Reference & Ordering Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Revision History
Altera Corporation
Section I–1
Stratix II Device Family Data Sheet
Stratix II Device Handbook, Volume 1
Section I–2
Altera Corporation
1. Introduction
SII51001-4.2
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
Introduction
The Stratix II family offers the following features:
Features
■
■
15,600 to 179,400 equivalent LEs; see Table 1–1
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
■
■
■
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrixmemory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
■
■
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
■
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
Altera Corporation
May 2007
1–1
Features
■
■
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
■
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
■
■
■
■
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130 EP2S180
ALMs
6,240
12,480
15,600
104
13,552
27,104
33,880
202
24,176
48,352
60,440
329
36,384
72,768
90,960
488
53,016
106,032
132,540
699
71,760
143,520
179,400
930
Adaptive look-up tables (ALUTs) (1)
Equivalent LEs (2)
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
78
144
255
408
609
768
0
1
2
4
6
9
Total RAM bits
419,328 1,369,728 2,544,192 4,520,488 6,747,840 9,383,040
DSP blocks
12
48
2
16
64
2
36
144
4
48
192
4
63
252
4
96
384
4
18-bit × 18-bit multipliers (3)
Enhanced PLLs
Fast PLLs
4
4
8
8
8
8
Maximum user I/O pins
366
500
718
902
1,126
1,170
Notes to Table 1–1:
(1) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus® II software for logic synthesis.
(2) This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
(3) These multipliers are implemented using the DSP blocks.
1–2
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Introduction
Stratix II devices are available in space-saving FineLine BGA® packages
(see Tables 1–2 and 1–3).
Table 1–2. Stratix II Package Options & I/O Pin Counts
Notes (1), (2)
484-Pin
Hybrid
FineLine
BGA
672-Pin
FineLine
BGA
780-Pin
FineLine
BGA
484-Pin
FineLine BGA
1,020-Pin
FineLine BGA FineLine BGA
1,508-Pin
Device
EP2S15
342
342
334
366
500
492
EP2S30
EP2S60 (3)
EP2S90 (3)
EP2S130 (3)
EP2S180 (3)
718
308
534
534
758
742
742
902
1,126
1,170
Notes to Table 1–2:
(1) All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p, and clk11n) that can be used for data inputs.
(2) The Quartus II software I/O pin counts include one additional pin, PLL_ENA, which is not available as general-
purpose I/O pins. The PLL_ENApin can only be used to enable the PLLs within the device.
(3) The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and
FPLL10CLKp/n) that can be used for data inputs.
Table 1–3. Stratix II FineLine BGA Package Sizes
484-Pin
Hybrid
Dimension
484 Pin
672 Pin
780 Pin
1,020 Pin
1,508 Pin
Pitch (mm)
Area (mm2)
1.00
529
1.00
729
1.00
729
1.00
841
1.00
1,089
1.00
1,600
Length × width
(mm × mm)
23 × 23
27 × 27
27 × 27
29 × 29
33 × 33
40 × 40
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
Altera Corporation
May 2007
1–3
Stratix II Device Handbook, Volume 1
Features
After compilation, check the information messages for a full list of I/O,
DQ, LVDS, and other pins that are not available because of the selected
migration path.
Table 1–4 lists the Stratix II device package offerings and shows the total
number of non-migratable user I/O pins when migrating from one
density device to a larger density device. Additional I/O pins may not be
migratable if migrating from the larger device to the smaller density
device.
1
When moving from one density to a larger density, the larger
density device may have fewer user I/O pins. The larger device
requires more power and ground pins to support the additional
logic within the device. Use the Quartus II Pin Planner to
determine which user I/O pins are migratable between the two
devices.
Table 1–4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths
Vertical Migration
Path
484-Pin
672-Pin
780-Pin
1020-Pin
1508-Pin
FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA
EP2S15 to EP2S30
EP2S15 to EP2S60
EP2S30 to EP2S60
EP2S60 to EP2S90
EP2S60 to EP2S130
EP2S60 to EP2S180
EP2S90 to EP2S130
EP2S90 to EP2S180
EP2S130 to EP2S180
0 (1)
8 (1)
8 (1)
0
0
8
0
0
0
0 (1)
16
16
0
17
0
0
Note to Table 1–4:
(1) Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more
detailed information.
1
To determine if your user I/O assignments are correct, run the
I/O Assignment Analysis command in the Quartus II software
(Processing > Start > Start I/O Assignment Analysis).
f
Refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook for more information on pin migration.
1–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Introduction
Stratix II devices are available in up to three speed grades, -3, -4, and -5,
with -3 being the fastest. Table 1–5 shows Stratix II device speed-grade
offerings.
Table 1–5. Stratix II Device Speed Grades
484-Pin
Hybrid
FineLine
BGA
484-Pin
FineLine
BGA
672-Pin
FineLine
BGA
780-Pin
FineLine
BGA
1,020-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
Temperature
Grade
Device
EP2S15
EP2S30
EP2S60
EP2S90
Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
Commercial
Industrial
-4, -5
-4, -5
-4, -5
-3, -4, -5
-4
-3, -4, -5
-4
EP2S130 Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
EP2S180 Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
Altera Corporation
May 2007
1–5
Stratix II Device Handbook, Volume 1
Document Revision History
Table 1–6 shows the revision history for this chapter.
Document
Revision History
Table 1–6. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v4.2 Moved Document Revision History to the end of the
chapter.
—
—
April 2006, v4.1
●
●
●
Updated “Features” section.
Removed Note 4 from Table 1–2.
Updated Table 1–4.
December 2005,
v4.0
●
●
Updated Tables 1–2, 1–4, and 1–5.
Updated Figure 2–43.
—
—
July 2005, v3.1
●
●
Added vertical migration information, including
Table 1–4.
Updated Table 1–5.
May 2005, v3.0
●
●
Updated “Features” section.
Updated Table 1–2.
—
—
—
—
—
—
March 2005,
v2.1
Updated “Introduction” and “Features” sections.
January 2005,
v2.0
Added note to Table 1–2.
October 2004,
v1.2
Updated Tables 1–2, 1–3, and 1–5.
July 2004, v1.1
●
●
Updated Tables 1–1 and 1–2.
Updated “Features” section.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
1–6
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
2. Stratix II Architecture
SII51002-4.3
Stratix® II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects
between logic array blocks (LABs), memory block structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP)
blocks.
Functional
Description
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is
the Stratix II device family’s basic building block of logic providing
efficient implementation of user logic functions. LABs are grouped into
rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 550 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
420 MHz. Several M-RAM blocks are located individually in the device's
logic array.
DSP blocks can implement up to either eight full-precision 9 × 9-bit
multipliers, four full-precision 18 × 18-bit multipliers, or one
full-precision 36 × 36-bit multiplier with add or subtract features. The
DSP blocks support Q1.15 format rounding and saturation in the
multiplier and accumulator stages. These blocks also contain shift
registers for digital signal processing applications, including finite
impulse response (FIR) and infinite impulse response (IIR) filters. DSP
blocks are grouped into columns across the device and operate at up to
450 MHz.
Altera Corporation
May 2007
2–1
Functional Description
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
TM
transfer at up to 1 Gbps using LVDS or HyperTransport technology I/O
standards.
Figure 2–1 shows an overview of the Stratix II device.
Figure 2–1. Stratix II Block Diagram
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded LVDS, HyperTransport & other
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
Memory Functions
I/O Standards
IOEs
LABs
IOEs
LABs
IOEs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
M-RAM Block
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
DSP
Block
2–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix II devices.
Table 2–1. Stratix II Device Resources
M512 RAM
Columns/Blocks Columns/Blocks
M4K RAM
M-RAM
Blocks
DSP Block
Columns/Blocks Columns
LAB
Device
LAB Rows
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
4 / 104
6 / 202
7 / 329
8 / 488
9 / 699
11 / 930
3 / 78
4 / 144
5 / 255
6 / 408
7 / 609
8 / 768
0
1
2
4
6
9
2 / 12
2 / 16
3 / 36
3 / 48
3 / 63
4 / 96
30
49
26
36
51
68
87
96
62
71
81
100
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus® II Compiler places
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.
Logic Array
Blocks
Altera Corporation
May 2007
2–3
Stratix II Device Handbook, Volume 1
Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
Row Interconnects of
Variable Speed & Length
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
Direct link
interconnect to
adjacent block
interconnect to
adjacent block
Local Interconnect
LAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects. Figure 2–3
shows the direct link connection.
2–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–3. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrix memory
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to right
Direct link
interconnect
to left
Local
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals. This gives a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in Figure 2–4. Each LAB's clock and clock
enable signals are linked. For example, any ALM in a particular LAB
using the labclk1signal also uses labclkena1. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock
signals. De-asserting the clock enable signal turns off the corresponding
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. By default, the Quartus II software uses a NOTgate
push-back technique to achieve preset. If you disable the NOTgate
push-up option or assign a given register to power up high using the
Quartus II software, the preset is achieved using the asynchronous load
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
signal with asynchronous load data input tied high. When the
asynchronous load/preset signal is used, the labclkena0signal is no
longer available.
The LAB row clocks [5..0]and LAB local interconnect generate the
TM
LAB-wide control signals. The MultiTrack interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclr1
labclk0
syncload
labclk1
labclk2
labclkena2
labclkena0
or asyncload
or labpreset
labclkena1
labclr0
synclr
The basic building block of logic in the Stratix II architecture, the adaptive
logic module (ALM), provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based
resources that can be divided between two adaptive LUTs (ALUTs). With
up to eight inputs to the two ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows the ALM to be
Adaptive Logic
Modules
2–6
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
Stratix II Architecture
completely backward-compatible with four-input LUT architectures. One
ALM can also implement any function of up to six inputs and certain
seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects. Figure 2–5 shows a high-level block
diagram of the Stratix II ALM while Figure 2–6 shows a detailed view of
all the connections in the ALM.
Figure 2–5. High-Level Block Diagram of the Stratix II ALM
carry_in
shared_arith_in
reg_chain_in
To general or
local routing
dataf0
datae0
dataa
datab
datac
To general or
local routing
adder0
D
Q
reg0
Combinational
Logic
datad
datae1
dataf1
To general or
local routing
adder1
D
Q
reg1
To general or
local routing
carry_out
shared_arith_out
reg_chain_out
Altera Corporation
May 2007
2–7
Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–6. Stratix II ALM Details
2–8
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register's clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the dataeor datafinput of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see Figure 2–6). For each set of output
drivers, two ALM outputs can drive column, row, or direct link routing
connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output
while the register drives another output. This feature, called register
packing, improves device utilization because the device can use the
register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT
of the same ALM so that the register is packed with its own fan-out LUT.
This provides another mechanism for improved fitting. The ALM can also
drive out registered and unregistered versions of the LUT or adder
output.
f
See the Performance & Logic Efficiency Analysis of Stratix II Devices White
Paper for more information on the efficiencies of the Stratix II ALM and
comparisons with previous architectures.
ALM Operating Modes
The Stratix II ALM can operate in one of the following modes:
■
■
■
■
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Each mode uses ALM resources differently. In each mode, eleven
available inputs to the ALM--the eight data inputs from the LAB local
interconnect; carry-infrom the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection--are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear,
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
synchronous load, and clock enable control for the register. These LAB-
wide signals are available in all ALM modes. See the “LAB Control
Signals” section for more information on the LAB-wide control signals.
The Quartus II software and supported third-party synthesis tools, in
conjunction with parameterized functions such as library of
parameterized modules (LPM) functions, automatically choose the
appropriate mode for common functions such as counters, adders,
subtractors, and arithmetic functions. If required, you can also create
special-purpose functions that specify which ALM operating mode to use
for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In this mode, up to eight data inputs from the
LAB local interconnect are inputs to the combinational logic. The normal
mode allows two functions to be implemented in one Stratix II ALM, or
an ALM to implement a single function of up to six inputs. The ALM can
support certain combinations of completely independent functions and
various combinations of functions which have common inputs.
Figure 2–7 shows the supported LUT combinations in normal mode.
2–10
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–7. ALM in Normal Mode Note (1)
dataf0
datae0
datac
dataa
datab
dataf0
4-Input
LUT
datae0
datac
dataa
5-Input
LUT
combout0
combout1
combout0
combout1
datab
datad
datae1
dataf1
4-Input
LUT
5-Input
LUT
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
dataf0
datae0
dataa
datab
datac
datad
combout0
combout1
6-Input
LUT
combout0
datad
datae1
dataf1
3-Input
LUT
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
combout1
6-Input
LUT
datad
datae1
4-Input
LUT
datae1
dataf1
dataf1
Note to Figure 2–7:
(1) Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of
functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
The normal mode provides complete backward compatibility with four-
input LUT architectures. Two independent functions of four inputs or less
can be implemented in one Stratix II ALM. In addition, a five-input
function and an independent three-input function can be implemented
without sharing inputs.
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May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
For the packing of two five-input functions into one ALM, the functions
must have at least two common inputs. The common inputs are dataa
and datab. The combination of a four-input function with a five-input
function requires one common input (either dataaor datab).
In the case of implementing two six-input functions in one ALM, four
inputs must be shared and the combinational function must be the same.
For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with
common inputs and unique select lines) can be implemented in one ALM,
as shown in Figure 2–8. The shared inputs are dataa, datab, datac, and
datad, while the unique select lines are datae0 and dataf0for
function0, and datae1and dataf1for function1. This crossbar
switch consumes four LUTs in a four-input LUT-based architecture.
Figure 2–8. 4 × 2 Crossbar Switch Example
4 × 2 Crossbar Switch
Implementation in 1 ALM
sel0[1..0]
inputa
inputb
dataf0
datae0
dataa
datab
datac
datad
Six-Input
LUT
(Function0)
out0
combout0
combout1
inputc
inputd
out1
sel1[1..0]
Six-Input
LUT
(Function1)
datae1
dataf1
In a sparsely used device, functions that could be placed into one ALM
may be implemented in separate ALMs. The Quartus II Compiler spreads
a design out to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically utilizes the full potential
of the Stratix II ALM. The Quartus II Compiler automatically searches for
functions of common inputs or completely independent functions to be
placed into one ALM and to make efficient use of the device resources. In
addition, you can manually control resource usage by setting location
assignments.
Any six-input function can be implemented utilizing inputs dataa,
datab, datac, datad, and either datae0and dataf0or datae1and
dataf1. If datae0and dataf0are utilized, the output is driven to
register0, and/or register0is bypassed and the data drives out to
the interconnect using the top set of output drivers (see Figure 2–9). If
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
datae1and dataf1are utilized, the output drives to register1
and/or bypasses register1and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically
selects the inputs to the LUT. Asynchronous load data for the register
comes from the dataeor datafinput of the ALM. ALMs in normal
mode support register packing.
Figure 2–9. 6-Input Function in Normal Mode Notes (1), (2)
To general or
local routing
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
To general or
local routing
D
D
Q
reg0
datae1
dataf1
(2)
To general or
local routing
Q
These inputs are available for register packing.
reg1
Notes to Figure 2–9:
(1) If datae1and dataf1are used as inputs to the six-input function, then datae0
and dataf0are available for register packing.
(2) The dataf1input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs. Figure 2–10 shows the
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–10 occur naturally
in designs. These functions often appear in designs as “if-else” statements
in Verilog HDL or VHDL code.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
5-Input
LUT
datab
To general or
local routing
datad
dataf0
combout0
To general or
local routing
D
Q
5-Input
LUT
reg0
datae1
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–10:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of two four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataaand
databinputs. As shown in Figure 2–11, the carry-in signal feeds to
adder0, and the carry-out from adder0feeds to carry-in of adder1. The
carry-out from adder1drives to adder0of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
2–14
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–11. ALM in Arithmetic Mode
carry_in
datae0
adder0
4-Input
LUT
To general or
local routing
To general or
local routing
D
Q
dataf0
datac
datab
dataa
reg0
4-Input
LUT
adder1
4-Input
LUT
To general or
local routing
datad
datae1
To general or
local routing
D
Q
4-Input
LUT
reg1
dataf1
carry_out
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in Figure 2–12. The
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_outsignal is ‘1.’ The carry_outsignal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncloadsignal. When asserted, syncload
selects the syncdatainput. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncloadsignal is de-asserted and ‘X’ drives the data port of the
registers.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
Adder output
is not used.
ALM 1
X[0]
Y[0]
Comb &
Adder
Logic
X[0]
X[1]
R[0]
R[1]
To general or
local routing
D
D
Q
reg0
syncdata
syncload
syncload
X[1]
Y[1]
Comb &
Adder
Logic
To general or
local routing
Q
reg1
Carry Chain
ALM 2
X[2]
Y[2]
Comb &
Adder
Logic
X[2]
R[2]
To general or
local routing
D
Q
reg0
syncload
Comb &
Adder
Logic
To local routing &
then to LAB-wide
syncload
carry_out
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
2–16
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together
automatically. For enhanced fitting, a long carry chain runs vertically
allowing fast horizontal connections to TriMatrix memory and DSP
blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high
fan-in arithmetic function is implemented, the LAB can support carry
chains that only utilize either the top half or the bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs
in the LAB available for implementing narrower fan-in functions in
normal mode. Carry chains that use the top four ALMs in the first LAB
carry into the top half of the ALMs in the next LAB within the column.
Carry chains that use the bottom four ALMs in the first LAB carry into the
bottom half of the ALMs in the next LAB within the column. Every other
column of LABs is top-half bypassable, while the other LAB columns are
bottom-half bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In
this mode, the ALM is configured with four 4-input LUTs. Each LUT
either computes the sum of three inputs or the carry of three inputs. The
output of the carry computation is fed to the next adder (either to adder1
in the same ALM or to adder0of the next ALM in the LAB) via a
dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder
tree by reducing the number of summation stages required to implement
an adder tree. Figure 2–13 shows the ALM in shared arithmetic mode.
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May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–13. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
4-Input
LUT
To general or
local routing
To general or
local routing
D
Q
datae0
datac
datab
dataa
reg0
4-Input
LUT
4-Input
LUT
To general or
local routing
datad
datae1
To general or
local routing
D
Q
4-Input
LUT
reg1
carry_out
shared_arith_out
Note to Figure 2–13:
(1) Inputs dataf0and dataf1are available for register packing in shared arithmetic mode.
Adder trees can be found in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in Figure 2–14. The partial sum (S[2..0])and the
partial carry (C[2..0])is obtained using the LUTs, while the result
(R[2..0])is computed using the dedicated adders.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
carry_in = '0'
3-Bit Add Example
ALM Implementation
ALM 1
X2 X1 X0
Y2 Y1 Y0
Z2 Z1 Z0
3-Input S0
1st stage add is
implemented in LUTs.
LUT
+
R0
2nd stage add is
implemented in adders.
S2 S1 S0
C2 C1 C0
X0
Y0
Z0
3-Input
LUT
+
C0
S1
R3 R2 R1 R0
X1
Y1
Z1
3-Input
LUT
Decimal
Equivalents
Binary Add
R1
1
1
0
1
0
1
0
1
0
6
5
C1
3-Input
LUT
2
+
+
0
1
0
0
1
1
+
+
1
1
2 x 6
13
ALM 2
1
0
1
S2
C2
'0'
3-Input
LUT
R2
X2
Y2
Z2
3-Input
LUT
3-Input
LUT
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
arithmetic chain runs vertically allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A shared arithmetic chain can
continue as far as a full column.
Similar to the carry chains, the shared arithmetic chains are also top- or
bottom-half bypassable. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the
other half available for narrower fan-in functionality. Every other LAB
column is top-half bypassable, while the other LAB columns are bottom-
half bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in an LAB have
register chain outputs. The register chain routing allows registers in the
same LAB to be cascaded together. The register chain interconnect allows
an LAB to use LUTs for a single combinational function and the registers
to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see Figure 2–15). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
2–20
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–15. Register Chain within an LAB Note (1)
From Previous ALM
Within The LAB
reg_chain_in
To general or
local routing
To general or
local routing
adder0
D
Q
reg0
Combinational
Logic
To general or
local routing
adder1
D
Q
reg1
To general or
local routing
To general or
local routing
To general or
local routing
adder0
D
Q
reg0
Combinational
Logic
To general or
local routing
adder1
D
Q
reg1
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–15:
(1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on register chain interconnect.
Altera Corporation
May 2007
2–21
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and load/preset
signals. The ALM directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Stratix II devices support simultaneous
asynchronous load/preset, and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one load/preset signal.
In addition to the clear and load/preset ports, Stratix II devices provide a
device-wide reset pin (DEV_CLRn) that resets all registers in the device.
An option set before compilation in the Quartus II software controls this
pin. This device-wide reset overrides all other control signals.
In the Stratix II architecture, connections between ALMs, TriMatrix
memory, DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDrive technology. The MultiTrack
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
MultiTrack
Interconnect
TM
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
re-optimization cycles that typically follow design changes and
additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory in the same row. These row resources include:
■
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the
device
2–22
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
Stratix II Architecture
The direct link interconnect allows an LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself. This provides fast communication
between adjacent LABs and/or blocks without using row interconnect
resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a source LAB. These resources are used for fast
row connections in a four-LAB region. Every LAB has its own set of R4
interconnects to drive either left or right. Figure 2–16 shows R4
interconnect connections from an LAB. R4 interconnects can drive and be
driven by DSP blocks and RAM blocks and row IOEs. For LAB
interfacing, a primary LAB or LAB neighbor can drive a given R4
interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 and C16 interconnects for connections
from one row to another. Additionally, R4 interconnects can drive R24
interconnects.
Figure 2–16. R4 Interconnect Connections Notes (1), (2), (3)
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4 and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
R4 Interconnect
Driving Left
LAB
Neighbor
Primary
LAB (2)
LAB
Neighbor
Notes to Figure 2–16:
(1) C4 and C16 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
(3) The LABs in Figure 2–16 show the 16 possible logical outputs per LAB.
Altera Corporation
May 2007
2–23
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect. These column resources include:
■
■
■
■
Shared arithmetic chain interconnects in an LAB
Carry chain interconnects in an LAB and from LAB to LAB
Register chain interconnects in an LAB
C4 interconnects traversing a distance of four blocks in up and down
direction
■
C16 column interconnects for high-speed vertical routing through
the device
Stratix II devices include an enhanced interconnect structure in LABs for
routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB
for fast shift registers. These ALM to ALM connections bypass the local
interconnect. The Quartus II Compiler automatically takes advantage of
these resources to improve utilization and performance. Figure 2–17
shows the shared arithmetic chain, carry chain and register chain
interconnects.
2–24
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–17. Shared Arithmetic Chain, Carry Chain & Register Chain
Interconnects
Local Interconnect
Routing Among ALMs
in the LAB
ALM 1
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
Register Chain
Routing to Adjacent
ALM's Register Inpu
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
Local
Interconnect
ALM 8
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 2–18 shows the C4 interconnect connections
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and column and row IOEs. For LAB interconnection, a
primary LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Altera Corporation
May 2007
2–25
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
Figure 2–18. C4 Interconnect Connections Note (1)
C4 Interconnect
Drives Local and R4
Interconnects
up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–18:
(1) Each C4 interconnect can drive either up or down four rows.
2–26
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, TriMatrix
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local interconnects directly.
All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)
connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. These blocks also have
direct link interconnects for fast connections to and from a neighboring
LAB. All blocks are fed by the row LAB clocks, labclk[5..0].
Table 2–2 shows the Stratix II device’s routing scheme.
Table 2–2. Stratix II Device Routing Scheme (Part 1 of 2)
Destination
Source
Shared arithmetic chain
Carry chain
v
v
v
v
Register chain
Local interconnect
Direct link interconnect
R4 interconnect
R24 interconnect
C4 interconnect
C16 interconnect
ALM
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
M512 RAM block
M4K RAM block
M-RAM block
v
DSP blocks
Altera Corporation
May 2007
2–27
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Table 2–2. Stratix II Device Routing Scheme (Part 2 of 2)
Destination
Source
Column IOE
v
v
v
v
Row IOE
v
v v
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers. Table 2–3 shows the size and features of the different RAM
blocks.
TriMatrix
Memory
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
M512 RAM Block
Memory Feature
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
(32 × 18 Bits)
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
500 MHz
550 MHz
420 MHz
v
v
v
v
v
v
v
v
v
v
v
v
ROM
(1)
v
v
v
v
v
v
v
FIFO buffer
v
Pack mode
v
Byte enable
v
v
Address clock enable
Parity bits
v
v
v
v
v
Mixed clock mode
Memory initialization (.mif)
v
v
2–28
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
M512 RAM Block
Memory Feature
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
(32 × 18 Bits)
Simple dual-port memory
mixed width support
v
v
v
v
v
True dual-port memory
mixed width support
Power-up conditions
Register clears
Outputs cleared
Output registers
Outputs cleared
Output registers
Outputs unknown
Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Notes to Table 2–3:
(1) The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM
function using a dual-port RAM bock. The Stratix II device must write to the dual-port memory once and then
disable the write-enable ports afterwards.
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Altera Corporation
May 2007
2–29
Stratix II Device Handbook, Volume 1
TriMatrix Memory
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
1
Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The read address, rden, and
output registers can be clocked by either of the two clocks driving the
block. This allows the RAM block to operate in read/write or
input/output clock modes. Only the output register can be bypassed. The
six labclksignals or local interconnect can drive the inclock,
outclock, wren, rden, and outclrsignals. Because of the advanced
interconnect between the LAB and M512 RAM blocks, ALMs can also
control the wrenand rdensignals and the RAM clock, clock enable, and
asynchronous clear signals. Figure 2–19 shows the M512 RAM block
control signal generation logic.
The RAM blocks in Stratix II devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, C4, and direct link interconnects
from adjacent LABs. The M512 RAM blocks can communicate with LABs
on either the left or right side through these row interconnects or with
LAB columns on the left or right side with the column interconnects. The
M512 RAM block has up to 16 direct link input connections from the left
adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link
interconnect. The M512 RAM block has equal opportunity for access and
performance to and from LABs on either its left or right side. Figure 2–20
shows the M512 RAM block to logic array interface.
2–30
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–19. M512 RAM Block Control Signals
Dedicated
6
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
outclocken
inclocken
wren
Local
Interconnect
outclr
inclock
outclock
rden
Altera Corporation
May 2007
2–31
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–20. M512 RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
dataout
Direct link
Direct link
M512 RAM
interconnect
interconnect
Block
from adjacent LAB
from adjacent LAB
clocks
datain
control
signals
address
2
6
M512 RAM Block Local LAB Row Clocks
Interconnect Region
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains 4,608
RAM bits (including parity bits). M4K RAM blocks can be configured in
the following modes:
■
■
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The M4K RAM blocks allow for different clocks on their inputs and
outputs. Either of the two clocks feeding the block can clock M4K RAM
block registers (renwe, address, byte enable, datain, and output registers).
Only the output register can be bypassed. The six labclksignals or local
interconnects can drive the control signals for the A and B ports of the
M4K RAM block. ALMs can also control the clock_a, clock_b,
renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b
signals, as shown in Figure 2–21.
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 16 direct link input connections to the M4K RAM Block
are possible from the left adjacent LABs and another 16 possible from the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect. Figure 2–22 shows the M4K
RAM block to logic array interface.
Figure 2–21. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_b
clock_b
renwe_b
aclr_b
Local
Interconnect
renwe_a
aclr_a
clock_a
clocken_a
Altera Corporation
May 2007
2–33
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
datain
byte
enable
control
signals
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain, and
output registers). The output register can be bypassed. The six labclk
signals or local interconnect can drive the control signals for the A and B
ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_bsignals as shown in Figure 2–23.
Figure 2–23. M-RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
clocken_a
renwe_a
clock_b
aclr_b
Local
Local
Interconnect
Interconnect
clocken_b
clock_a
aclr_a
renwe_b
The R4, R24, C4, and direct link interconnects from adjacent LABs on
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure 2–24 shows an example floorplan
for the EP2S130 device and the location of the M-RAM interfaces.
Figures 2–25 and 2–26 show the interface between the M-RAM block and
the logic array.
Altera Corporation
May 2007
2–35
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–24. EP2S130 Device with M-RAM Interface Locations Note (1)
M-RAM blocks interface to
LABs on right and left sides for
easy access to horizontal I/O pins
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M4K
Blocks
M512
Blocks
DSP
Blocks
LABs
DSP
Blocks
Note to Figure 2–24:
(1) The device shown is an EP2S130 device. The number and position of M-RAM blocks varies in other devices.
2–36
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–25. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
L1
R0
R1
M-RAM Block
L2
L3
L4
L5
R2
R3
R4
R5
Port A
Port B
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
LABs in Row
M-RAM Boundary
Note to Figure 2–25:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
Altera Corporation
May 2007
2–37
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16
dataout_a[ ]
16
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
Up to 28
Direct Link
Interconnects
byteena [ ]
A
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Table 2–4 shows the input and output data signal connections along with
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–4. M-RAM Row Interface Unit Signals
Unit Interface Block
Input Signals
Output Signals
L0
datain_a[14..0]
dataout_a[11..0]
byteena_a[1..0]
L1
L2
datain_a[29..15]
byteena_a[3..2]
dataout_a[23..12]
dataout_a[35..24]
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
L3
L4
L5
R0
R1
R2
addressa[15..5]
datain_a[41..36]
dataout_a[47..36]
dataout_a[59..48]
dataout_a[71..60]
dataout_b[11..0]
dataout_b[23..12]
dataout_b[35..24]
datain_a[56..42]
byteena_a[5..4]
datain_a[71..57]
byteena_a[7..6]
datain_b[14..0]
byteena_b[1..0]
datain_b[29..15]
byteena_b[3..2]
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
R3
R4
R5
addressb[15..5]
datain_b[41..36]
dataout_b[47..36]
dataout_b[59..48]
dataout_b[71..60]
datain_b[56..42]
byteena_b[5..4]
datain_b[71..57]
byteena_b[7..6]
f
See the TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook for more information on TriMatrix
memory.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
The most commonly used DSP functions are FIR filters, complex FIR
Digital Signal
Processing
Block
filters, IIR filters, fast Fourier transform (FFT) functions, direct cosine
transform (DCT) functions, and correlators. All of these use the multiplier
as the fundamental building block. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Stratix II devices provide DSP blocks to meet the arithmetic
requirements of these functions.
Each Stratix II device has from two to four columns of DSP blocks to
efficiently implement DSP functions faster than ALM-based
implementations. Stratix II devices have up to 24 DSP blocks per column
(see Table 2–5). Each DSP block can be configured to support up to:
■
■
■
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
As indicated, the Stratix II DSP block can support one 36 × 36-bit
multiplier in a single DSP block. This is true for any combination of
signed, unsigned, or mixed sign multiplications.
1
This list only shows functions that can fit into a single DSP block.
Multiple DSP blocks can support larger multiplication
functions.
2–40
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–27 shows one of the columns with surrounding LAB rows.
Figure 2–27. DSP Blocks Arranged in Columns
DSP Block
Column
DSP Block
4 LAB
Rows
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May 2007
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Digital Signal Processing Block
Table 2–5 shows the number of DSP blocks in each Stratix II device.
Table 2–5. DSP Blocks in Stratix II Devices Note (1)
Total 9 × 9
Multipliers
Total 18 × 18
Multipliers
Total 36 × 36
Multipliers
Device
DSP Blocks
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
12
16
36
48
63
96
96
48
64
12
16
36
48
63
96
128
288
384
504
768
144
192
252
384
Note to Table 2–5:
(1) Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode.
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Stratix II Architecture
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift
Register Inputs from
Previous DSP Block
Output
Selection
Adder Output Block
Multiplier Block
PRN
PRN
D
Multiplexer
Q
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
ENA
CLRN
PRN
From the row
interface block
D
Q
ENA
CLRN
Adder/
Q1.15
Subtractor/
Round/
Accumulator
Saturate
1
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
ENA
CLRN
PRN
D
Q
Summation
Block
ENA
CLRN
Adder
D
Q
ENA
CLRN
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Summation Stage
for Adding Four
ENA
CLRN
PRN
Multipliers Together
D
Q
ENA
CLRN
Adder/
Subtractor/
Accumulator
2
Q1.15
Round/
Saturate
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Optional Serial Shift
Register Outputs to
Next DSP Block
ENA
CLRN
Optional Pipline
Register Stage
PRN
D
Q
in the Column
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
ENA
CLRN
to MultiTrack
Interconnect
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May 2007
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Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
■
■
■
■
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–6 shows the different number of multipliers possible in each DSP
block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions. The DSP blocks also support mixed modes
and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiply-
accumulator mode, while the other half of the DSP block implements four
9 × 9-bit multipliers in simple multiplier mode.
Table 2–6. Multiplier Size & Configurations per DSP Block
DSP Block Mode
9 × 9
18 × 18
36 × 36
Multiplier
Eight multipliers with
eight product outputs
Four multipliers with four One multiplier with one
product outputs
product output
Multiply-accumulator
Two-multipliers adder
-
Two 52-bit multiply-
accumulate blocks
-
Four two-multiplier adder Two two-multiplier adder
(two 9 × 9 complex
multiply)
-
-
(one 18 × 18 complex
multiply)
Four-multipliers adder
Two four-multiplier adder One four-multiplier adder
DSP Block Interface
Stratix II device DSP block input registers can generate a shift register that
can cascade down in the same DSP block column. Dedicated connections
between DSP blocks provide fast connections between the shift register
inputs to cascade the shift register chains. You can cascade registers
within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than
four taps, with additional adder stages implemented in ALMs. If the DSP
block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift
register chain out of the block to cascade multiple columns of DSP blocks.
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Stratix II Architecture
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. Each block unit can be considered one
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local
interconnect region is associated with each DSP block. Like an LAB, this
interconnect region can be fed with 16 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block's local interconnect region.
The outputs also work similarly to LAB outputs as well. Eighteen outputs
from the DSP block can drive to the left LAB through direct link
interconnects and eighteen can drive to the right LAB though direct link
interconnects. All 36 outputs can drive to R4 and C4 routing
interconnects. Outputs can drive right- or left-column routing.
Figures 2–29 and 2–30 show the DSP block interfaces to LAB rows.
Figure 2–29. DSP Block Interconnect Interface
DSP Block
OA[17..0]
OB[17..0]
R4, C4 & Direct
R4, C4 & Direct
Link Interconnects
Link Interconnects
A1[17..0]
B1[17..0]
OC[17..0]
OD[17..0]
A2[17..0]
B2[17..0]
OE[17..0]
OF[17..0]
A3[17..0]
B3[17..0]
OG[17..0]
OH[17..0]
A4[17..0]
B4[17..0]
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May 2007
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Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
Direct Link Interconnect
from Adjacent LAB
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
C4 Interconnect
R4 Interconnect
36
DSP Block
Row Structure
LAB
36
16
LAB
18
16
12
36
Control
36
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
Row Interface
Block
DSP Block to
36 Inputs per Row
36 Outputs per Row
LAB Row Interface
Block Interconnect Region
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
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Stratix II Architecture
The LAB row source for control signals, data inputs, and outputs is
shown in Table 2–7.
Table 2–7. DSP Block Signal Sources & Destinations
LAB Row at
Interface
Control Signals Generated
Data Inputs Data Outputs
0
clock0
aclr0
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
ena0
mult01_saturate
addnsub1_round/ accum_round
addnsub1
signa
sourcea
sourceb
1
2
3
clock1
aclr1
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
A2[17..0]
B2[17..0]
OC[17..0]
OD[17..0]
clock2
aclr2
ena2
mult23_saturate
addnsub3_round/ accum_round
addnsub3
sign_b
sourcea
sourceb
A3[17..0]
B3[17..0]
OE[17..0]
OF[17..0]
clock3
aclr3
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
f
See the DSP Blocks in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook, for more information on DSP blocks.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Stratix II devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
PLLs & Clock
Networks
Global & Hierarchical Clocking
Stratix II devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to
24 clocks per device region with low skew and delay. This hierarchical
clocking scheme provides up to 48 unique clock domains in Stratix II
devices.
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in Figures 2–31 and 2–32. Internal logic and enhanced and fast
PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the
selection of the clock source and dynamically enables/disables the clock
to reduce power consumption. Table 2–8 shows global and regional clock
features.
Table 2–8. Global & Regional Clock Features
Feature
Global Clocks
Regional Clocks
Number per device
16
16
32
8
Number available per
quadrant
Sources
CLKpins, PLL outputs, CLKpins, PLL outputs,
or internal logic
or internal logic
Dynamic clock source
selection
v (1)
Dynamic enable/disable
v
v
Note to Table 2–8:
(1) Dynamic source clock selection is supported for selecting between CLKppins and
PLL outputs only.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
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Stratix II Architecture
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–31 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 2–31. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
CLK[11..8]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks RCLK[7..0]in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0]input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLKclock pins symmetrically drive the RCLKnetworks in
a particular quadrant, as shown in Figure 2–32.
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May 2007
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PLLs & Clock Networks
Figure 2–32. Regional Clocks
RCLK[31..28] RCLK[27..24]
CLK[15..12]
RCLK[3..0]
RCLK[23..20]
CLK[11..8]
CLK[3..0]
RCLK[7..4]
RCLK[19..16]
CLK[7..4]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
PLLs or Core Logic within that Quadrant
RCLK[11..8] RCLK[15..12]
Dual-Regional Clock Network
A single source (CLKpin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–33. Corner PLLs cannot drive dual-regional clocks.
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Stratix II Architecture
Figure 2–33. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[15..12]
CLK[15..12]
CLK[3..0]
CLK[11..8]
CLK[3..0]
CLK[11..8]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form busses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–34).
Figure 2–34. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Regional Clock Network [7..0]
Clock [23..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
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May 2007
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PLLs & Clock Networks
IOE clocks have row and column block regions that are clocked by eight
I/O clock signals chosen from the 24 quadrant clock resources.
Figures 2–35 and 2–36 show the quadrant relationship to the I/O clock
regions.
Figure 2–35. EP2S15 & EP2S30 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
8
8
I/O Clock Regions
8
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
IO_CLKH[7:0]
IO_CLKC[7:0]
IO_CLKD[7:0]
8
8
IO_CLKG[7:0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
8
8
8
IO_CLKF[7:0]
IO_CLKE[7:0]
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Stratix II Architecture
Figure 2–36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
IO_CLKC[7:0]
IO_CLKD[7:0]
8
8
8
8
I/O Clock Regions
IO_CLKE[7:0]
8
8
8
8
8
8
IO_CLKP[7:0]
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
IO_CLKF[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
8
8
IO_CLKM[7:0]
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable/disable)
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May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
1
When using the global or regional clock control blocks in
Stratix II devices to select between multiple clocks or to enable
and disable clock networks, be aware of possible narrow pulses
or glitches when switching from one clock signal to another. A
glitch or runt pulse has a width that is less than the width of the
highest frequency input clock signal. To prevent logic errors
within the FPGA, Altera recommends that you build circuits
that filter out glitches and runt pulses.
Figures 2–37 through 2–39 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
Figure 2–37. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
2
2
CLKn
Pin
Internal
Logic
CLKSELECT[1..0]
2
(1)
Static Clock Select (2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–37:
(1) These clock select signals can be dynamically controlled through internal logic
when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
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Stratix II Architecture
Figure 2–38. Regional Clock Control Blocks
CLKp
Pin
CLKn
Pin
(2)
PLL Counter
Outputs (3)
2
Internal
Logic
Static Clock Select
(1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–38:
(1) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
(2) Only the CLKnpins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
(3) The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
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May 2007
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PLLs & Clock Networks
Figure 2–39. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select
(1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select
(1)
PLL_OUT
Pin
Notes to Figure 2–39:
(1) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUTpin’s IOE. The
PLL_OUTpin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
For the global clock control block, the clock source selection can be
controlled either statically or dynamically. The user has the option of
statically selecting the clock source by using the Quartus II software to set
specific configuration bits in the configuration file (.sof or .pof) or the
user can control the selection dynamically by using internal logic to drive
the multiplexor select inputs. When selecting statically, the clock source
can be set to any of the inputs to the select multiplexor. When selecting
the clock source dynamically, you can either select between two PLL
outputs (such as the C0 or C1 outputs from one PLL), between two PLLs
(such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of
the other PLL), between two clock pins (such as CLK0or CLK1), or
between a combination of clock pins or PLL outputs. The clock outputs
from corner PLLs cannot be dynamically selected through the global
control block.
For the regional and PLL_OUTclock control block, the clock source
selection can only be controlled statically using configuration bits. Any of
the inputs to the clock select multiplexor can be set as the clock source.
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Stratix II Architecture
The Stratix II clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state thereby reducing the overall
power consumption of the device.
The global and regional clock networks can be powered down statically
through a setting in the configuration (.sof or .pof) file. Clock networks
that are not used are automatically powered down through configuration
bit settings in the configuration file generated by the Quartus II software.
The dynamic clock enable/disable feature allows the internal logic to
control power up/down synchronously on GCLK and RCLKnets and
PLL_OUTpins. This function is independent of the PLL and is applied
directly on the clock network or PLL_OUTpin, as shown in Figures 2–37
through 2–39.
1
The following restrictions for the input clock pins apply:
•
•
•
•
CLK0 pin -> inclk[0] of CLKCTRL
CLK1 pin -> inclk[1] of CLKCTRL
CLK2 pin -> inclk[0] of CLKCTRL
CLK3 pin -> inclk[1] of CLKCTRL
In general, even CLK numbers connect to the inclk[0]port of
CLKCTRL, and odd CLK numbers connect to the inclk[1]port
of CLKCTRL.
Failure to comply with these restrictions will result in a no-fit
error.
Enhanced & Fast PLLs
Stratix II devices provide robust clock management and synthesis using
up to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover,
spread-spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Stratix II device’s enhanced PLLs
provide you with complete control of clocks and system timing. The fast
PLLs provide general purpose clocking with multiplication and phase
shifting as well as high-speed outputs for high-speed differential I/O
support. Enhanced and fast PLLs work together with the Stratix II
high-speed I/O and advanced clock architecture to provide significant
improvements in system performance and bandwidth.
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May 2007
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PLLs & Clock Networks
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–9 shows the PLLs available for
each Stratix II device and their type.
Table 2–9. Stratix II Device PLL Availability
Fast PLLs
Enhanced PLLs
Device
1
2
3
4
7
8
9
10
5
6
11
12
EP2S15
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP2S30
EP2S60 (1)
EP2S90 (2)
EP2S130 (3)
EP2S180
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Notes to Table 2–9:
(1) EP2S60 devices in the 1020-pin package contain 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
(2) EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLS 1–4 and enhanced PLLs 5 and 6.
(3) EP2S130 devices in the 1020-pin and 1508-pin packages contain 12PLLs. The EP2S130 device in the 780-pin package
contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
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Stratix II Architecture
Table 2–10 shows the enhanced PLL and fast PLL features in Stratix II
devices.
Table 2–10. Stratix II PLL Features
Feature
Enhanced PLL
Fast PLL
Clock multiplication and division
Phase shift
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
Down to 125-ps increments (3), (4)
Clock switchover
v
v (5)
v
PLL reconfiguration
v
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
v
v
v
v
v
4
6
Three differential/six single-ended
(6)
One single-ended or differential
(7), (8)
Notes to Table 2–10:
(1) For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty
cycle.
(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
(4) For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
(5) Stratix II fast PLLs only support manual clock switchover.
(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
(7) If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
(8) Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input
per PLL.
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PLLs & Clock Networks
Figure 2–40 shows a top-level diagram of the Stratix II device and PLL
floorplan.
Figure 2–40. PLL Locations
CLK[15..12]
11
5
7
10
FPLL7CLK
FPLL10CLK
CLK[8..11]
FPLL9CLK
1
2
4
3
CLK[3..0]
PLLs
FPLL8CLK
8
9
12
6
CLK[7..4]
Figures 2–41 and 2–42 shows the global and regional clocking from the
fast PLL outputs and the side clock pins.
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Stratix II Architecture
Figure 2–41. Global & Regional Clock Connections from Center Clock Pins &
Fast PLL Outputs
Note (1)
Notes to Figure 2–41:
(1) EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the
connectivity from these four PLLs to the global and regional clock networks
remains the same as shown.
(2) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note (1)
Note to Figure 2–42:
(1) The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
2–62
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–43 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLKpins. The connections to the global and
regional clocks from the top clock pins and enhanced PLL outputs is
shown in Table 2–11. The connections to the clocks from the bottom clock
pins is shown in Table 2–12.
Altera Corporation
May 2007
2–63
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure 2–43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs
Notes (1), (2), and (3)
CLK15
CLK14
CLK13
CLK12
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
RCLK27
Regional
Clocks
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
Regional
Clocks
RCLK12
RCLK13
RCLK14
RCLK15
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Notes to Figure 2–43:
(1) EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to
the global and regional clock networks remains the same as shown.
(2) If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin.
(3) The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
2–64
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs (Part 1
of 2)
Top Side Global & Regional
Clock Network Connectivity
Clock pins
CLK12p
v
v
v
v
v
v
v
v
v
v
v
v
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 5 outputs
c0
v
v
v
v
v
v
v
v
v
v
c1
c2
c3
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs (Part 2
of 2)
Top Side Global & Regional
Clock Network Connectivity
c4
v
v
v
v
v
v
v
v
c5
v
v
v
v
v
v
Enhanced PLL 11 outputs
c0
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs (Part 1 of 2)
Bottom Side Global &
Regional Clock Network
Connectivity
Clock pins
CLK4p
v
v
v
v
v
v
v
v
v
v
v
v
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
2–66
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs (Part 2 of 2)
Bottom Side Global &
Regional Clock Network
Connectivity
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 6 outputs
c0
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 12 outputs
c0
v
v
v
v
v
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2007
2–67
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–44 shows a diagram of the enhanced PLL.
Figure 2–44. Stratix II Enhanced PLL Note (1)
From Adjacent PLL
Post-Scale
VCO Phase Selection
Selectable at Each
PLL Output Port
Counters
Clock
Switchover
Circuitry
Spread
Spectrum
/c0
/c1
/c2
Phase Frequency
Detector
INCLK[3..0]
4
4
8
6
Global
Clocks
/n
8
Charge
Pump
Loop
Filter
PFD
VCO
6
Regional
Clocks
Global or
Regional
/c3
/c4
/c5
Clock
(4)
I/O Buffers
(3)
/m
(2)
to I/O or general
routing
Lock Detect
& Filter
FBIN
VCO Phase Selection
Affecting All Outputs
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–44:
(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
(2) If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
2–68
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability. Figure 2–45 shows a diagram of the fast PLL.
Figure 2–45. Stratix II Device Fast PLL Notes (1), (2), (3)
Post-Scale
Counters
VCO Phase Selection
Selectable at each PLL
Output Port
Clock
Switchover
Circuitry (4)
Phase
Frequency
Detector
diffioclk0 (2)
Global or
regional clock (1)
load_en0
(3)
÷c0
÷c1
÷c2
(5)
8
Charge
Pump
(3)
(2)
Loop
Filter
load_en1
diffioclk1
÷k
÷n
PFD
VCO
4
Clock
Input
4
8
Global clocks
4
Global or
regional clock (1)
Regional clocks
÷c3
÷m
8
to DPA block
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–45:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Stratix II fast PLLs only support manual clock switchover.
(5) If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See “High-Speed
Differential I/O with DPA Support” on page 2–96 for more information
on high-speed differential I/O support.
The Stratix II IOEs provide many features, including:
I/O Structure
■
■
■
■
■
■
■
■
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip parallel termination
On-chip termination for differential standards
Programmable pull-up during configuration
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May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
■
■
■
■
■
■
■
■
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
The IOE in Stratix II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–46 shows the Stratix II IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
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Altera Corporation
May 2007
Stratix II Architecture
Figure 2–46. Stratix II IOE Structure
Logic Array
OE Register
D
Q
OE
OE Register
D
Q
Output Register
D
Q
Output A
Output B
CLK
Output Register
D
Q
Input Register
D
Q
Input A
Input B
Input Latch
Input Register
D
Q
D
Q
ENA
The IOEs are located in I/O blocks around the periphery of the Stratix II
device. There are up to four IOEs per row I/O block and four IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–47 shows how a row I/O block connects to the logic array.
Figure 2–48 shows how a column I/O block connects to the logic array.
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May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect Note (1)
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
32
LAB
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
Horizontal I/O
Block Contains
up to Four IOEs
io_clk[7:0]
LAB Local
Interconnect
Note to Figure 2–47:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0]and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
2–72
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–48. Column I/O Block Connection to the Interconnect Note (1)
32 Data &
Control Signals
from Logic Array (1)
Vertical I/O
Block Contains
up to Four IOEs
Vertical I/O Block
32
IO_dataina[3:0]
IO_datainb[3:0]
io_clk[7..0]
I/O Block
Local Interconnect
R4 & R24
Interconnects
LAB
LAB
LAB
LAB Local
Interconnect
C4 & C16
Interconnects
Note to Figure 2–48:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0]and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (see the “PLLs & Clock Networks” section).
Figure 2–49 illustrates the signal paths through the I/O block.
Figure 2–49. Signal Path through the I/O Block
Row or Column
io_clk[7..0]
To Other
IOEs
io_dataina
To Logic
Array
io_datainb
oe
ce_in
io_oe
io_ce_in
io_ce_out
io_aclr
ce_out
Control
Signal
Selection
IOE
aclr/apreset
sclr/spreset
From Logic
Array
clk_in
io_sclr
io_clk
clk_out
io_dataouta
io_dataoutb
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out. Figure 2–50 illustrates the control signal
selection.
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Stratix II Device Handbook, Volume 1
May 2007
Stratix II Architecture
Figure 2–50. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
io_oe
Local
Interconnect
io_sclr
Local
Interconnect
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
io_clk
Local
Interconnect
ce_out
clk_out
sclr/spreset
Local
Interconnect
clk_in
ce_in
aclr/apreset
oe
Notes to Figure 2–50:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oecan be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0]signals. The ioe_clksignals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–51 shows the IOE in bidirectional configuration.
Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
t
Delay
CO
ce_out
V
CCIO
PCI Clamp (2)
V
CCIO
Programmable
Pull-Up
aclr/apreset
Resistor
Chip-Wide Reset
On-Chip
Termination
Output Register
Output
Pin Delay
D
Q
Drive Strength Control
Open-Drain Output
sclr/spreset
ENA
CLRN/PRN
Input Pin to
Logic Array Delay
Bus-Hold
Circuit
Input Pin to
Input Register Delay
Input Register
clkin
D
Q
ce_in
ENA
CLRN/PRN
Notes to Figure 2–51:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
The Stratix II device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinational logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. Programmable delays are no longer
required to ensure zero hold times for logic array register-to-IOE register
transfers. The Quartus II Compiler can create the zero hold time for these
transfers. Table 2–13 shows the programmable delays for Stratix II
devices.
Table 2–13. Stratix II Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Delay to output enable pin
Output enable register tCO delay
The IOE registers in Stratix II devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device's active-low input upon power-up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally, a
synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Stratix II devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix II devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used in the IOE
for DDR input acquisition. The latch holds the data that is present during
the clock high times. This allows both bits of data to be synchronous with
the same clock edge (either rising or falling). Figure 2–52 shows an IOE
configured for DDR input. Figure 2–53 shows the DDR input timing
diagram.
Figure 2–52. Stratix II IOE in DDR Input I/O Configuration Notes (1), (2), (3)
ioe_clk[7..0]
VCCIO
Column, Row,
or Local
PCI Clamp (4)
To DQS Logic
Block (3)
Interconnect
DQS Local
Bus (2)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
I
nput Pin to
Input RegisterDelay
sclr/spreset
Input Register
D
Q
clkin
ENA
CLRN/PRN
ce_in
Bus-Hold
Circuit
aclr/apreset
Chip-Wide Reset
Latch
D Q
Input Register
D
Q
ENA
ENA
CLRN/PRN
CLRN/PRN
Notes to Figure 2–52:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–53. Input Timing Diagram in DDR Mode
Data at
input pin
B0
A0 B1 A1 B2 A2 B3 A3 B4
CLK
A0
B0
A1
B1
A2
B2
A3
B3
Input To
Logic Array
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time. Figure 2–54 shows the IOE configured for DDR output.
Figure 2–55 shows the DDR output timing diagram.
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May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–54. Stratix II IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
Delay
ce_out
t
CO
aclr/apreset
sclr/spreset
V
CCIO
PCI Clamp (3)
Chip-Wide Reset
OE Register
V
CCIO
D
Q
Programmable
Pull-Up
Resistor
Used for
DDR, DDR2
SDRAM
ENA
CLRN/PRN
Output Register
D
Q
On-Chip
Termination
Output
Pin Delay
clk
ENA
CLRN/PRN
Drive Strength
Control
Open-Drain Output
Output Register
D
Q
Bus-Hold
Circuit
ENA
CLRN/PRN
Notes to Figure 2–54:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port. Similarly, the aclrand apresetsignals are also active-high at the input ports
of the DDIO megafunction.
(3) The optional PCI clamp is only available on column I/O pins.
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–55. Output TIming Diagram in DDR Mode
CLK
A1
B1
A2
B2
A3
B3
A4
B4
From Internal
Registers
B1 A1 B2 A2 B3 A3 B4 A4
DDR output
The Stratix II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock.
This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II devices also have
dedicated phase-shift circuitry for interfacing with external memory
interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II
SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every
Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom
(banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–14 shows the number
of DQ and DQS buses that are supported per device.
Table 2–14. DQS & DQ Bus Mode Support (Part 1 of 2)
Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2S15 484-pin FineLine BGA
672-pin FineLine BGA
8
18
8
4
8
0
4
0
4
0
4
8
0
0
0
0
0
0
4
EP2S30 484-pin FineLine BGA
672-pin FineLine BGA
4
18
8
8
EP2S60 484-pin FineLine BGA
672-pin FineLine BGA
4
18
36
8
1,020-pin FineLine BGA
18
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May 2007
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I/O Structure
Table 2–14. DQS & DQ Bus Mode Support (Part 2 of 2)
Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2S90 484-pin Hybrid FineLine BGA
780-pin FineLine BGA
8
4
0
4
8
8
4
8
8
8
8
0
0
4
4
0
4
4
4
4
18
36
36
18
36
36
36
36
8
1,020-pin FineLine BGA
18
18
8
1,508-pin FineLine BGA
EP2S130 780-pin FineLine BGA
1,020-pin FineLine BGA
18
18
18
18
1,508-pin FineLine BGA
EP2S180 1,020-pin FineLine BGA
1,508-pin FineLine BGA
Notes to Table 2–14:
(1) Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]pfeed the phase circuitry on the top of the device and
clock pins CLK[7..4]pfeed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
Figure 2–56 illustrates the phase-shift reference circuit control of each
DQS delay shift on the top of the device. This same circuit is duplicated
on the bottom of the device.
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May 2007
Stratix II Architecture
Figure 2–56. DQS Phase-Shift Circuitry Notes (1), (2), (3), (4)
From PLL 5 (3)
CLK[15..12]p (2)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Phase-Shift
Circuitry
DQS Logic
Blocks
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Notes to Figure 2–56:
(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are
up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
(2) The Δt module represents the DQS logic block.
(3) Clock pins CLK[15..12]pfeed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]pfeed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-
shift circuitry.
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
These dedicated circuits combined with enhanced PLL clocking and
phase-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
f
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have several levels of drive strength that the
user can control. The default setting used in the Quartus II software is the
maximum current strength setting that is used to achieve maximum I/O
performance. For all I/O standards, the minimum setting is the lowest
drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
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May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–15 shows the possible settings for the I/O standards with drive
strength control.
Table 2–15. Programmable Drive Strength Note (1)
IOH / IOL Current Strength IOH / IOL Current Strength
I/O Standard
Setting (mA) for Column Setting (mA) for Row I/O
I/O Pins
Pins
3.3-V LVTTL
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
8, 4
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
12, 8, 4
12, 10, 8, 6, 4, 2
8, 6, 4, 2
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 8
12, 8
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
24, 20, 16
16
12, 10, 8, 6, 4
20, 18, 16, 8
12, 10, 8, 6, 4
20, 18, 16
10, 8, 6, 4
-
12, 10, 8, 6, 4
-
8, 6, 4
-
12, 10, 8, 6, 4
20, 18, 16
Note to Table 2–15:
(1) The Quartus II software default current setting is the maximum setting for each
I/O standard.
Open-Drain Output
Stratix II devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, you do not need an external
pull-up or pull-down resistor to hold a signal level when the bus is
tri-stated.
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May 2007
Stratix II Architecture
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than VCCIO to prevent overdriving
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when the I/O pin has
been configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
See the DC & Switching Characteristics chapter in the Stratix II Device
Handbook, Volume 1, for the specific sustaining current driven through this
resistor and overdrive current used to identify the next-driven input
level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix II device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O
pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the
VCCIO level of the output pin’s bank.
Programmable pull-up resistors are only supported on user I/O pins, and
are not supported on dedicated configuration pins, JTAG pins or
dedicated clock pins.
Advanced I/O Standard Support
Stratix II device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
HyperTransport technology
Differential 1.5-V HSTL Class I and II
Differential 1.8-V HSTL Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-2 Class I and II
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May 2007
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I/O Structure
■
■
■
■
■
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
1.2-V HSTL
SSTL-2 Class I and II
SSTL-18 Class I and II
Table 2–16 describes the I/O standards supported by Stratix II devices.
Table 2–16. Stratix II Supported I/O Standards (Part 1 of 2)
Input Reference
Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
Output Supply
BoardTermination
I/O Standard
Type
LVTTL
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
-
3.3
3.3
-
LVCMOS
-
-
2.5 V
-
2.5
-
1.8 V
-
1.8
-
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
-
1.5
-
-
3.3
-
-
3.3
-
-
2.5 (3)
3.3
-
LVPECL (1)
Differential
-
-
-
-
HyperTransport technology Differential
2.5
Differential 1.5-V HSTL
Differential
0.75
1.5
0.75
Class I and II (2)
Differential 1.8-V HSTL
Class I and II (2)
Differential
0.90
0.90
1.25
1.8
1.8
2.5
0.90
0.90
1.25
Differential SSTL-18 Class Differential
I and II (2)
Differential SSTL-2 Class I Differential
and II (2)
1.2-V HSTL(4)
Voltage-referenced
0.6
0.75
0.9
1.2
1.5
1.8
1.8
0.6
0.75
0.9
1.5-V HSTL Class I and II Voltage-referenced
1.8-V HSTL Class I and II Voltage-referenced
SSTL-18 Class I and II
Voltage-referenced
0.90
0.90
2–86
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–16. Stratix II Supported I/O Standards (Part 2 of 2)
Input Reference
Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
Output Supply
BoardTermination
I/O Standard
Type
SSTL-2 Class I and II
Voltage-referenced
1.25
2.5
1.25
Notes to Table 2–16:
(1) This I/O standard is only available on input and output column clock pins.
(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
(3)
VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12).
The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use VCCINT for LVDS input operations and have no
dependency on the VCCIO level of the bank.
(4) 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
f
For more information on I/O standards supported by Stratix II I/O
banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
Stratix II devices contain eight I/O banks and four enhanced PLL external
clock output banks, as shown in Figure 2–57. The four I/O banks on the
right and left of the device contain circuitry to support high-speed
differential I/O for LVDS and HyperTransport inputs and outputs. These
banks support all Stratix II I/O standards except PCI or PCI-X I/O pins,
and SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
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May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–57. Stratix II I/O Banks Notes (1), (2), (3), (4)
DQS8T
DQS7T
DQS6T
DQS5T
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
PLL11
PLL5
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
PLL7
PLL10
Bank 11
Bank 9
Bank 3
Bank 4
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
standards are supported for both
input and output operations.
standards are supported for both
input and output operations.
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
PLL2
PLL4
PLL3
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 12 Bank 10
Bank 8
Bank 7
PLL8
PLL9
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS8B DQS7B DQS6B DQS5B
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
PLL12
PLL6
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 2–57:
(1) Figure 2–57 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
(2) Depending on the size of the device, different device members have different numbers of VREF groups. Refer to the
pin list and the Quartus II software for exact locations.
(3) Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
(4) Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High
Speed Differential I/O Interfaces in Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2
or the Stratix II GX Device Handbook, Volume 2 for more information on differential I/O standards.
2–88
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Each I/O bank has its own VCCIOpins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
VCCIO level independently. Each bank also has dedicated VREFpins to
support the voltage-referenced standards (such as SSTL-2). The PLL
banks utilize the adjacent VREFgroup when voltage-referenced
standards are implemented. For example, if an SSTL input is
implemented in PLL bank 10, the voltage level at VREFB7is the reference
voltage level for the SSTL input.
I/O pins that reside in PLL banks 9 through 12 are powered by the
VCC_PLL<5, 6, 11, or 12>_OUTpins, respectively. The EP2S60F484,
EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not
support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are
powered by the VCCIO3pin, and any I/O pins that reside in bank 12 are
powered by the VCCIO8pin.
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. Each bank can support one VREF voltage level. For
example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and
3.3-V PCI for inputs and outputs.
On-Chip Termination
Stratix II devices provide differential (for the LVDS or HyperTransport
technology I/O standard), series, and parallel on-chip termination to
reduce reflections and maintain signal integrity. On-chip termination
simplifies board design by minimizing the number of external
termination resistors required. Termination can be placed inside the
package, eliminating small stubs that can still lead to reflections.
Stratix II devices provide four types of termination:
■
■
■
■
Differential termination (RD)
Series termination (RS) without calibration
Series termination (RS) with calibration
Parallel termination (RT) with calibration
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–17 shows the Stratix II on-chip termination support per I/O bank.
Table 2–17. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support
I/O Standard Support
Top & Bottom Banks
Left & Right Banks
Series termination without
calibration
3.3-V LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
v
v
2–90
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May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
I/O Standard Support
Top & Bottom Banks
Left & Right Banks
Series termination with
calibration
3.3-V LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
Parallel termination with
calibration
SSTL-2 Class I and II
SSTL-18 Class I and II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I and II
1.2-V HSTL
LVDS
Differential termination (1)
v
v
HyperTransport technology
Note to Table 2–17:
(1) Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLKdo not support differential on-chip
termination. Clock pins CLK0, CLK2, CLK8, and CLK10do support differential on-chip termination. Clock pins in
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
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May 2007
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I/O Structure
Differential On-Chip Termination
Stratix II devices support internal differential termination with a nominal
resistance value of 100 Ω for LVDS or HyperTransport technology input
receiver buffers. LVPECL input signals (supported on clock pins only)
require an external termination resistor. Differential on-chip termination
is supported across the full range of supported differential data rates as
shown in the DC & Switching Characteristics chapter in volume 1 of the
Stratix II Device Handbook.
f
f
For more information on differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
For more information on tolerance specifications for differential on-chip
termination, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Series Termination Without Calibration
Stratix II devices support driver impedance matching to provide the I/O
driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Stratix II devices support on-chip series
termination for single-ended I/O standards with typical RS values of 25
and 50 Ω. Once matching impedance is selected, current drive strength is
no longer selectable. Table 2–17 shows the list of output standards that
support on-chip series termination without calibration.
On-Chip Series Termination with Calibration
Stratix II devices support on-chip series termination with calibration in
column I/O pins in top and bottom banks. There is one calibration circuit
for the top I/O banks and one circuit for the bottom I/O banks. Each
on-chip series termination calibration circuit compares the total
impedance of each I/O buffer to the external 25- or 50-Ω resistors
connected to the RUPand RDNpins, and dynamically enables or disables
the transistors until they match. Calibration occurs at the end of device
configuration. Once the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
f
For more information on series on-chip termination supported by
Stratix II devices, refer to the Selectable I/O Standards in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
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May 2007
Stratix II Architecture
f
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Parallel Termination with Calibration
Stratix II devices support on-chip parallel termination with calibration for
column I/O pins only. There is one calibration circuit for the top I/O
banks and one circuit for the bottom I/O banks. Each on-chip parallel
termination calibration circuit compares the total impedance of each I/O
buffer to the external 50-Ω resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. Once the calibration
circuit finds the correct impedance, it powers down and stops changing
the characteristics of the drivers.
1
On-chip parallel termination with calibration is only supported
for input pins.
f
f
For more information on on-chip termination supported by Stratix II
devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
MultiVolt I/O Interface
The Stratix II architecture supports the MultiVolt I/O interface feature
that allows Stratix II devices in all packages to interface with systems of
different supply voltages.
The Stratix II VCCINTpins must always be connected to a 1.2-V power
supply. With a 1.2-V VCCINT level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-V
tolerant. The VCCIOpins can be connected to either a 1.5-, 1.8-, 2.5-, or
3.3-V power supply, depending on the output requirements. The output
levels are compatible with systems of the same voltage as the power
supply (for example, when VCCIOpins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems).
The Stratix II VCCPDpower pins must be connected to a 3.3-V power
supply. These power pins are used to supply the pre-driver power to the
output buffers, which increases the performance of the output pins. The
VCCPDpins also power configuration input pins and JTAG input pins.
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May 2007
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I/O Structure
Table 2–18 summarizes Stratix II MultiVolt I/O support.
Table 2–18. Stratix II MultiVolt I/O Support Note (1)
Input Signal (V)
VCCIO (V)
Output Signal (V)
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3 5.0
1.2
1.5
1.8
2.5
3.3
(4)
(4)
(4)
(4)
(4)
v (2)
v
v
v (2)
v
v
v(2)
v(2)
v(2)
v
v(2)
v(2)
v(2)
v
v (4)
v (3)
v
v(3) v(3)
v
v(3) v(3) v(3)
v(3) v(3) v(3)
v
v(3)
v
v
v
v
Notes to Table 2–18:
(1) To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL
and LVCMOS input levels to overdrive input buffer option in the Quartus II software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL
maximum and VO H minimum voltages do not violate the applicable Stratix II VIL maximum and VIH minimum
voltage specifications.
(3) Although VCCIO specifies the voltage necessary for the Stratix II device to drive out, a receiving device powered at
a different level can still interface with the Stratix II device if it has inputs that tolerate the VCCIO value.
(4) Stratix II devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. Stratix II devices support 1.2-V HSTL.
The TDOand nCEOpins are powered by VCCIO of the bank that they reside
in. TDOis in I/O bank 4 and nCEOis in I/O bank 7.
Ideally, the VCC supplies for the I/O buffers of any two connected pins are
at the same voltage level. This may not always be possible depending on
the VCCIO level of TDOand nCEOpins on master devices and the
configuration voltage level chosen by VCCSELon slave devices. Master
and slave devices can be in any position in the chain. Master indicates that
it is driving out TDOor nCEOto a slave device.
For multi-device passive configuration schemes, the nCEOpin of the
master device drives the nCEpin of the slave device. The VCCSELpin on
the slave device selects which input buffer is used for nCE. When VCCSEL
is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When
VCCSELis logic low it selects the 3.3-V/2.5-V input buffer powered by
VCCPD. The ideal case is to have the VCCIO of the nCEObank in a master
device match the VCCSELsettings for the nCEinput buffer of the slave
device it is connected to, but that may not be possible depending on the
application. Table 2–19 contains board design recommendations to
ensure that nCEOcan successfully drive nCEfor all power supply
combinations.
2–94
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–19. Board Design Recommendations for nCEO
Stratix II nCEO VCCIO Voltage Level in I/O Bank 7
nCE Input Buffer Power in I/O
Bank 3
VCCIO
3.3 V
=
VCCIO
=
VCCIO
=
VCCIO
=
VCCIO
=
2.5 V
1.8 V
1.5 V
1.2 V
VCCSELhigh
(VCCIO Bank 3 = 1.5 V)
v(1), (2)
v(1), (2)
v
v(3), (4)
v(3), (4)
v(4)
v(5)
v
v
v
v
Level shifter
required
VCCSELhigh
(VCCIO Bank 3 = 1.8 V)
Level shifter Level shifter
required required
VCCSELlow
(nCE Powered by VCCPD = 3.3V)
v(6)
Notes to Table 2–19:
(1) Input buffer is 3.3-V tolerant.
(2) The nCEOoutput buffer meets VO H (MIN) = 2.4 V.
(3) Input buffer is 2.5-V tolerant.
(4) The nCEOoutput buffer meets VOH (MIN) = 2.0 V.
(5) Input buffer is 1.8-V tolerant.
(6) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDOpin of the first device drives the TDIpin of the
second device in the chain. The VCCSEL input on JTAG input I/O cells
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the
VCCIO of the TDObank from the first device to match the VCCSEL settings
for TDIon the second device, but that may not be possible depending on
the application. Table 2–20 contains board design recommendations to
ensure proper JTAG chain operation.
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Stratix II TDO VCCIO Voltage Level in I/O Bank 4
TDI Input
Device
Buffer Power
VCCI O = 3.3 V VCCIO = 2.5 V VCCIO = 1.8 V VCCIO = 1.5 V VCCI O = 1.2 V
Stratix II
Always
VCCPD (3.3V)
Level shifter
required
Level shifter
required
v(1)
v(2)
v(3)
Altera Corporation
May 2007
2–95
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Stratix II TDO VCCIO Voltage Level in I/O Bank 4
VCCI O = 3.3 V VCCIO = 2.5 V VCCIO = 1.8 V VCCIO = 1.5 V VCCI O = 1.2 V
TDI Input
Buffer Power
Device
Non-Stratix II VCC = 3.3 V
VCC = 2.5 V
Level shifter
required
Level shifter
required
v(1)
v(2)
v(2)
v(3)
v(3)
v
Level shifter
required
Level shifter
required
v(1), (4)
v(1), (4)
v(1), (4)
VCC = 1.8 V
Level shifter
required
Level shifter
required
v(2), (5)
v(2), (5)
VCC = 1.5 V
v(6)
v
v
Notes to Table 2–20:
(1) The TDOoutput buffer meets VOH (MIN) = 2.4 V.
(2) The TDOoutput buffer meets VOH (MIN) = 2.0 V.
(3) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
Stratix II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1 Gbps. The LVDS and HyperTransport
differential I/O standards are supported in the Stratix II device. In
addition, the LVPECL I/O standard is supported on input and output
High-Speed
Differential I/O
with DPA
clock pins on the top and bottom I/O banks.
Support
The high-speed differential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■
■
■
■
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO
HyperTransport technology
There are four dedicated high-speed PLLs in the EP2S15 to EP2S30
devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
Tables 2–21 through 2–26 show the number of channels that each fast PLL
can clock in each of the Stratix II devices. In Tables 2–21 through 2–26 the
first row for each transmitter or receiver provides the number of channels
driven directly by the PLL. The second row below it shows the maximum
channels a PLL can drive if cross bank channels are used from the
adjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15
2–96
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Table 2–21. EP2S15 Device Differential Channels
Note (1)
Center Fast PLLs
Transmitter/
Receiver
Total
Channels
Package
PLL 1
PLL 2
PLL 3
PLL 4
484-pin FineLine BGA
Transmitter
38 (2)
(3)
10
19
11
21
10
19
11
21
9
9
10
19
11
21
10
19
11
21
19
10
21
9
19
10
21
9
Receiver
42 (2)
(3)
672-pin FineLine BGA
Transmitter
Receiver
38 (2)
(3)
19
10
21
19
10
21
42 (2)
(3)
Table 2–22. EP2S30 Device Differential Channels
Note (1)
Center Fast PLLs
Transmitter/
Receiver
Total
Channels
Package
PLL 1
PLL 2
PLL 3
PLL 4
484-pin FineLine BGA
Transmitter
38 (2)
(3)
10
19
11
21
16
29
17
31
9
9
10
19
11
21
16
29
17
31
19
10
21
13
29
14
31
19
10
21
13
29
14
31
Receiver
42 (2)
(3)
672-pin FineLine BGA
Transmitter
Receiver
58 (2)
(3)
62 (2)
(3)
Altera Corporation
May 2007
2–97
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–23. EP2S60 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
484-pin
FineLine BGA
Transmitter
Receiver
38 (2)
(3)
10
19
11
21
16
29
17
31
21
42
21
42
9
9
10
19
11
21
16
29
17
31
21
42
21
42
10
-
9
-
9
-
10
-
19
10
21
13
29
14
31
21
42
21
42
19
10
21
13
29
14
31
21
42
21
42
42 (2)
(3)
11
-
10
-
10
-
11
-
672-pin
FineLine BGA
Transmitter
Receiver
58 (2)
(3)
16
-
13
-
13
-
16
-
62 (2)
(3)
17
-
14
-
14
-
17
-
1,020-pin
FineLine BGA
Transmitter
Receiver
84 (2)
(3)
21
-
21
-
21
-
21
-
84 (2)
(3)
21
-
21
-
21
-
21
-
Table 2–24. EP2S90 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
484-pinHybrid Transmitter
FineLine BGA
38 (2)
(3)
10
19
11
21
16
32
17
34
23
45
23
46
30
59
30
59
9
9
10
19
11
21
16
32
17
34
23
45
23
46
30
59
30
59
-
-
-
-
-
-
-
-
-
-
19
10
21
16
32
17
34
22
45
24
46
29
59
29
59
19
10
21
16
32
17
34
22
45
24
46
29
59
29
59
Receiver
42 (2)
(3)
-
-
-
-
-
-
780-pin
FineLine BGA
Transmitter
Receiver
64 (2)
(3)
-
-
-
-
-
-
-
-
68 (2)
(3)
-
-
-
-
-
-
1,020-pin
FineLine BGA
Transmitter
Receiver
90 (2)
(3)
23
-
22
-
22
-
23
-
94 (2)
(3)
23
-
24
-
24
-
23
-
1,508-pin
FineLine BGA
Transmitter
Receiver
118 (2)
(3)
30
-
29
-
29
-
30
-
118 (2)
(3)
30
-
29
-
29
-
30
-
2–98
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–25. EP2S130 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
780-pin
FineLine BGA
Transmitter
Receiver
64 (2)
(3)
16
32
17
34
22
44
23
46
37
78
37
78
16
32
17
34
22
44
23
46
41
78
41
78
16
32
17
34
22
44
23
46
41
78
41
78
16
32
17
34
22
44
23
46
37
78
37
78
-
-
-
-
-
-
-
-
68 (2)
(3)
-
-
-
-
-
-
1,020-pin
FineLine BGA
Transmitter
Receiver
88 (2)
(3)
22
-
22
-
22
-
22
-
92 (2)
(3)
23
-
23
-
23
-
23
-
1,508-pin
FineLine BGA
Transmitter
Receiver
156 (2)
(3)
37
-
41
-
41
-
37
-
156 (2)
(3)
37
-
41
-
41
-
37
-
Table 2–26. EP2S180 Differential Channels
Note (1)
Center Fast PLLs
Corner Fast PLLs (4)
Transmitter/
Receiver Channels
Total
Package
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
1,020-pin
FineLine BGA
Transmitter
Receiver
88 (2)
(3)
22
44
23
46
37
78
37
78
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
22
44
23
46
37
78
37
78
22
-
22
-
22
-
22
-
92 (2)
(3)
23
-
23
-
23
-
23
-
1,508-pin
FineLine BGA
Transmitter
Receiver
156 (2)
(3)
37
-
41
-
41
-
37
-
156 (2)
(3)
37
-
41
-
41
-
37
-
Notes to Tables 2–21 to 2–26:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
(2) This is the maximum number of channels the PLLs can directly drive.
(3) This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
(4) The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Altera Corporation
May 2007
2–99
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Dedicated Circuitry with DPA Support
Stratix II devices support source-synchronous interfacing with LVDS or
HyperTransport signaling at up to 1 Gbps. Stratix II devices can transmit
or receive serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. For example, a HyperTransport technology application
where the data rate is 1,000 Mbps and the clock rate is 500 MHz would
require that W be set to 2. The SERDES factor J determines the parallel
data width to deserialize from receivers or to serialize for transmitters.
The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to
equal the PLL clock-multiplication W value. A design using the dynamic
phase aligner also supports all of these J factor values. For a J factor of 1,
the Stratix II device bypasses the SERDES block. For a J factor of 2, the
Stratix II device bypasses the SERDES block, and the DDR input and
output registers are used in the IOE. Figure 2–58 shows the block diagram
of the Stratix II transmitter channel.
Figure 2–58. Stratix II Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
Up to 1 Gbps
10
10
Dedicated
Transmitter
Interface
Local
Interconnect
diffioclk
load_en
refclk
Fast
PLL
Regional or
global clock
Each Stratix II receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic source-
synchronous operation of the channel. In addition, you can dynamically
switch between using the DPA block or bypassing the block via a control
signal from the logic array. Figure 2–59 shows the block diagram of the
Stratix II receiver channel.
2–100
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–59. Stratix II Receiver Channel
Data to R4, R24, C4, or
direct link interconnect
+
–
Up to 1 Gbps
D
Q
Data Realignment
Circuitry
10
data
retimed_data
Dedicated
Receiver
Interface
DPA
Synchronizer
DPA_clk
Eight Phase Clocks
8
diffioclk
load_en
refclk
Fast
PLL
Regional or
global clock
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
f
For more information on the fast PLL, see the PLLs in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-to-
channel or clock-to-channel skew. The DPA block locks to a phase closest
to the serial data phase. The phase-aligned DPA clock is used to write the
data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
Altera Corporation
May 2007
2–101
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
For high-speed source synchronous interfaces such as POS-PHY 4,
Parallel RapidIO, and HyperTransport, the source synchronous clock rate
is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Stratix II device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for user-
controlled byte boundary shifting. This simplifies designs while saving
ALM resources. You can use an ALM-based state machine to signal the
shift of receiver byte boundaries until a specified pattern is detected to
indicate byte alignment.
Fast PLL & Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left and right side of the device has one receiver channel and
one transmitter channel per LAB row. Figure 2–60 shows the fast PLL and
channel layout in the EP2S15 and EP2S30 devices. Figure 2–61 shows the
fast PLL and channel layout in the EP2S60 to EP2S180 devices.
Figure 2–60. Fast PLL & Channel Layout in the EP2S15 & EP2S30 Devices Note (1)
4
4
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
4
4
2
2
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
Quadrant
Quadrant
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
4
4
Note to Figure 2–60:
(1) See Table 2–21 for the number of channels each device supports.
2–102
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figure 2–61. Fast PLL & Channel Layout in the EP2S60 to EP2S180 Devices Note (1)
Fast
Fast
PLL 7
PLL 10
2
2
4
4
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
4
4
2
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
2
LVDS
Clock
DPA
Clock
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
4
4
2
2
Fast
PLL 8
Fast
PLL 9
Note to Figure 2–61:
(1) See Tables 2–22 through 2–26 for the number of channels each device supports.
Altera Corporation
2–103
May 2007
Stratix II Device Handbook, Volume 1
Document Revision History
Table 2–27 shows the revision history for this chapter.
Document
Revision History
Table 2–27. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
—
—
—
—
May 2007, v4.3 Updated “Clock Control Block” section.
Updated note in the “Clock Control Block” section.
Deleted Tables 2-11 and 2-12.
Updated notes to:
●
●
●
●
Figure 2–41
Figure 2–42
Figure 2–43
Figure 2–45
—
—
—
Updated notes to Table 2–18.
Moved Document Revision History to end of the chapter.
Updated Table 2–18 with note.
August 2006,
v4.2
April 2006,
v4.1
●
●
●
Updated Table 2–13.
●
●
Added parallel on-
chip termination
description and
specification.
Changed RCLK
names to match the
Quartus II software in
Table 2–13.
Removed Note 2 from Table 2–16.
Updated “On-Chip Termination” section and Table 2–19 to
include parallel termination with calibration information.
Added new “On-Chip Parallel Termination with Calibration”
section.
●
●
Updated Figure 2–44.
December
2005, v4.0
Updated “Clock Control Block” section.
—
July 2005, v3.1
●
●
Updated HyperTransport technology information in Table 2–18.
Updated HyperTransport technology information in
Figure 2–57.
—
●
Added information on the asynchronous clear signal.
May 2005, v3.0
●
●
●
●
●
●
Updated “Functional Description” section.
Updated Table 2–3.
Updated “Clock Control Block” section.
Updated Tables 2–17 through 2–19.
Updated Tables 2–20 through 2–22.
Updated Figure 2–57.
—
—
March 2005,
2.1
●
●
Updated “Functional Description” section.
Updated Table 2–3.
2–104
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Table 2–27. Document Revision History (Part 2 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
January 2005,
v2.0
●
Updated the “MultiVolt I/O Interface” and “TriMatrix Memory”
sections.
—
●
●
Updated Tables 2–3, 2–17, and 2–19.
October 2004,
v1.2
Updated Tables 2–9, 2–16, 2–26, and 2–27.
—
—
July 2004, v1.1
●
●
●
●
●
Updated note to Tables 2–9 and 2–16.
Updated Tables 2–16, 2–17, 2–18, 2–19, and 2–20.
Updated Figures 2–41, 2–42, and 2–57.
Removed 3 from list of SERDES factor J.
Updated “High-Speed Differential I/O with DPA Support”
section.
●
In “Dedicated Circuitry with DPA Support” section, removed
XSBI and changed RapidIO to Parallel RapidIO.
February2004, Added document to the Stratix II Device Handbook.
v1.0
—
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Document Revision History
2–106
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
3. Configuration & Testing
SII51003-4.2
All Stratix® II devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus® II software or hardware
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
IEEE Std. 1149.1
JTAG Boundary-
Scan Support
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCKpin has an internal weak
pull-down resistor, while the TDI,TMSand TRSTpins have weak internal
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the VCCIO power supply of bank 4.
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap® II embedded logic analyzer. Stratix II
devices support the JTAG instructions shown in Table 3–1.
1
Stratix II, Stratix, Cyclone® II, and Cyclone devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
The Stratix II device instruction register length is 10 bits and the
USERCODEregister length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Stratix II devices.
Altera Corporation
May 2007
3–1
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Stratix II JTAG Instructions
JTAG Instruction
Instruction Code
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
SAMPLE/PRELOAD 00 0000 0101
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
EXTEST(1)
BYPASS
00 0000 1111
11 1111 1111 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
00 0000 0111 Selects the 32-bit USERCODEregister and places it between the
TDI and TDOpins, allowing the USERCODEto be serially shifted
out of TDO.
IDCODE
00 0000 0110 Selects the IDCODEregister and places it between TDIand TDO,
allowing the IDCODEto be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions
Used when configuring a Stratix II device via the JTAG port with a
USB Blaster, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II
download cable, or when using a .jam or .jbc via an embedded
processor or JRunner.
PULSE_NCONFIG
00 0000 0001 Emulates pulsing the nCONFIGpin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
CONFIG_IO (2)
00 0000 1101
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IOinstruction holds nSTATUSlow to
reset the configuration device. nSTATUSis held low until the IOE
configuration register is loaded and the TAP controller state
machine transitions to the UPDATE_DRstate.
SignalTap II
instructions
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information on using the CONFIG_IOinstruction, see the MorphIO: An I/O Reconfiguration Solution for
Altera Devices White Paper.
3–2
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May 2007
Stratix II Device Handbook, Volume 1
Configuration & Testing
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the USERCODE
register. Turn on the Auto Usercode option by clicking Device & Pin
Options, then General, in the Settings dialog box (Assignments menu).
Table 3–2. Stratix II Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
1,140
1,692
2,196
2,748
3,420
3,948
Table 3–3. 32-Bit Stratix II Device IDCODE
IDCODE (32 Bits) (1)
Device
Version
ManufacturerIdentity(11
Part Number (16 Bits)
LSB (1 Bit) (2)
(4 Bits)
0000
0000
0001
0000
0000
0000
Bits)
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
0010 0000 1001 0001
0010 0000 1001 0010
0010 0000 1001 0011
0010 0000 1001 0100
0010 0000 1001 0101
0010 0000 1001 0110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
1
1
1
1
1
1
Notes to Table 3–3:
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE'sleast significant bit (LSB) is always 1.
1
Stratix, Stratix II, Cyclone, and Cyclone II devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they fail
configuration. This does not affect SignalTap II.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
SignalTap II Embedded Logic Analyzer
f
For more information on JTAG, see the following documents:
■
The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II &
Stratix II GX Devices chapter of the Stratix II Device Handbook,
Volume 2 or the Stratix II GX Device Handbook, Volume 2
Jam Programming & Test Language Specification
■
Stratix II devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA®
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
SignalTap II
Embedded Logic
Analyzer
The logic, circuitry, and interconnects in the Stratix II architecture are
configured with CMOS SRAM elements. Altera® FPGA devices are
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Configuration
Stratix II devices are configured at system power-up with data stored in
an Altera configuration device or provided by an external controller (e.g.,
a MAX® II device or microprocessor). Stratix II devices can be configured
using the fast passive parallel (FPP), active serial (AS), passive serial (PS),
passive parallel asynchronous (PPA), and JTAG configuration schemes.
The Stratix II device’s optimized interface allows microprocessors to
configure it serially or in parallel, and synchronously or asynchronously.
The interface also enables microprocessors to treat Stratix II devices as
memory and configure them by writing to a virtual memory location,
making reconfiguration easy.
In addition to the number of configuration methods supported, Stratix II
devices also offer the design security, decompression, and remote system
upgrade features. The design security feature, using configuration
bitstream encryption and AES technology, provides a mechanism to
protect your designs. The decompression feature allows Stratix II FPGAs
to receive a compressed configuration bitstream and decompress this
data in real-time, reducing storage requirements and configuration time.
The remote system upgrade feature allows real-time system upgrades
from remote locations of your Stratix II designs. For more information,
see “Configuration Schemes” on page 3–7.
3–4
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Stratix II Device Handbook, Volume 1
May 2007
Configuration & Testing
Operating Modes
The Stratix II architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow Stratix II devices to be reconfigured
in-circuit by loading new configuration data into the device. With real-
time reconfiguration, the device is forced into command mode with a
device pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSELis a dedicated input pin used to select POR delay times of 12 ms
or 100 ms during power-up. When the PORSELpin is connected to
ground, the POR time is 100 ms; when the PORSELpin is connected to
VCC, the POR time is 12 ms.
The nIOPULLUPpin is a dedicated input that chooses whether the
internal pull-ups on the user I/O pins and dual-purpose configuration
I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS,
RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or
off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns
off the weak internal pull-ups, while a logic low turns them on.
Stratix II devices also offer a new power supply, VCCPD, which must be
connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. VCCPD applies to all the JTAG
input pins (TCK, TMS, TDI, and TRST) and the configuration input pins
when VCCSELis connected to ground. See Table 3–4 for more information
on the pins affected by VCCSEL.
The VCCSELpin allows the VCCIO setting (of the banks where the
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting the VCCIO, the VIL and
VIH levels driven to the configuration inputs do not have to be a concern.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
The PLL_ENApin and the configuration input pins (Table 3–4) have a
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSELinput pin selects which input buffer is used. The 3.3-
V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input
buffer is powered by VCCIO. Table 3–4 shows the pins affected by VCCSEL.
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
VCCSEL = HIGH (connected
to VCCPD
VCCSEL = LOW (connected
to GND)
Pin
)
nSTATUS(when
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK(when used
as an input)
1.8/1.5-V input buffer is
selected. Input buffer is
powered by VCCIO of the I/O
bank.
3.3/2.5-V input buffer is
selected. Input buffer is
CS
powered by VCCPD
.
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSELis sampled during power-up. Therefore, the VCCSELsetting
cannot change on the fly or during a reconfiguration. The VCCSELinput
buffer is powered by VCCINT and must be hardwired to VCCPD or ground.
A logic high VCCSELconnection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSELshould be set to
comply with the logic levels driven out of the configuration device or
MAX® II/microprocessor.
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSELto a logic low; you can set the VCCIO of the I/O
bank that contains the configuration inputs to any supported voltage. If
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Configuration & Testing
you need to support configuration input voltages of 1.8 V/1.5 V, you
should set the VCCSELto a logic high and the VCCIO of the bank that
contains the configuration inputs to 1.8 V/1.5 V.
f
For more information on multi-volt support, including information on
using TDOand nCEOin multi-volt systems, refer to the Stratix II
Architecture chapter in volume 1 of the Stratix II Device Handbook.
Configuration Schemes
You can load the configuration data for a Stratix II device with one of five
configuration schemes (see Table 3–5), chosen on the basis of the target
application. You can use a configuration device, intelligent controller, or
the JTAG port to configure a Stratix II device. A configuration device can
automatically configure a Stratix II device at system power-up.
You can configure multiple Stratix II devices in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device.
Stratix II FPGAs offer the following:
■
■
■
Configuration data decompression to reduce configuration file
storage
Design security using configuration data encryption to protect your
designs
Remote system upgrades for remotely updating your Stratix II
designs
Table 3–5 summarizes which configuration features can be used in each
configuration scheme.
Table 3–5. Stratix II Configuration Features (Part 1 of 2)
Configuration
Configuration Method
Scheme
RemoteSystem
Upgrade
Design Security Decompression
FPP
MAX II device or microprocessor and
flash device
v(1)
v(1)
v
Enhanced configuration device
Serial configuration device
v(2)
v
v
v(3)
v
AS
PS
v
v
MAX II device or microprocessor and
flash device
v
Enhanced configuration device
v
v
v
v
v
Download cable (4)
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
Table 3–5. Stratix II Configuration Features (Part 2 of 2)
Configuration
Configuration Method
Scheme
RemoteSystem
Upgrade
Design Security Decompression
PPA
MAX II device or microprocessor and
flash device
v
JTAG
Download cable (4)
MAX II device or microprocessor and
flash device
Notes for Table 3–5:
(1) In these modes, the host system must send a DCLKthat is 4× the data rate.
(2) The enhanced configuration device decompression feature is available, while the Stratix II decompression feature
is not available.
(3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
(4) The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
f
See the Configuring Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information about configuration schemes in Stratix II and
Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry’s first FPGAs with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the Stratix II FPGA. To successfully configure a
Stratix II FPGA that has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.
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May 2007
Configuration & Testing
1
An encryption configuration file is the same size as a non-
encryption configuration file. When using a serial configuration
scheme such as passive serial (PS) or active serial (AS),
configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme us used with the design security or decompression
feature, a 4× DCLKis required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, refer to AN 341: Using the Design Security Feature in
Stratix II Devices. Contact your local Altera sales representative
to request this document.
Device Configuration Data Decompression
Stratix II FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory, and transmit this compressed bit stream to Stratix II FPGAs.
During configuration, the Stratix II FPGA decompresses the bit stream in
real time and programs its SRAM cells.
Stratix II FPGAs support decompression in the FPP (when using a
MAX II device/microprocessor and flash memory), AS and PS
configuration schemes. Decompression is not supported in the PPA
configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by modern system
designers. Stratix II devices can help effectively deal with these
challenges with their inherent re-programmability and dedicated
circuitry to perform remote system updates. Remote system updates help
deliver feature enhancements and bug fixes without costly recalls, reduce
time to market, and extend product life.
Stratix II FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios® processor or user logic)
implemented in the Stratix II device can download a new configuration
image from a remote location, store it in configuration memory, and direct
the dedicated remote system upgrade circuitry to initiate a
reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
error status information. This dedicated remote system upgrade circuitry
avoids system downtime and is the critical component for successful
remote system upgrades.
RSC is supported in the following Stratix II configuration schemes: FPP,
AS, PS, and PPA. RSC can also be implemented in conjunction with
advanced Stratix II features such as real-time decompression of
configuration data and design security using AES for secure and efficient
field upgrades.
f
f
See the Remote System Upgrades With Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX
Device Handbook for more information about remote configuration in
Stratix II devices.
Configuring Stratix II FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including
Stratix II FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files on the Altera web site (www.altera.com).
Programming Serial Configuration Devices with SRunner
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming that
can be easily customized to fit in different embedded systems. SRunner is
able to read a .rpd file (Raw Programming Data) and write to the serial
configuration devices. The serial configuration device programming time
using SRunner is comparable to the programming time when using the
Quartus II software.
f
f
For more information about SRunner, see the SRunner: An Embedded
Solution for EPCS Programming White Paper and the source code on the
Altera web site at www.altera.com.
For more information on programming serial configuration devices, see
the Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet in the
Configuration Handbook.
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May 2007
Configuration & Testing
Configuring Stratix II FPGAs with the MicroBlaster Driver
TM
The MicroBlaster software driver supports an RBF programming input
file and is ideal for embedded FPP or PS configuration. The source code
is developed for the Windows NT operating system, although it can be
customized to run on other operating systems. For more information on
the MicroBlaster software driver, see the Configuring the MicroBlaster Fast
Passive Parallel Software Driver White Paper or the Configuring the
MicroBlaster Passive Serial Software Driver White Paper on the Altera web
site (www.altera.com).
PLL Reconfiguration
The phase-locked loops (PLLs) in the Stratix II device family support
reconfiguration of their multiply, divide, VCO-phase selection, and
bandwidth selection settings without reconfiguring the entire device. You
can use either serial data from the logic array or regular I/O pins to
program the PLL’s counter settings in a serial chain. This option provides
considerable flexibility for frequency synthesis, allowing real-time
variation of the PLL frequency and delay. The rest of the device is
functional while reconfiguring the PLL.
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on Stratix II PLLs.
Stratix II devices include a diode-connected transistor for use as a
temperature sensor in power management. This diode is used with an
external digital thermometer device. These devices steer bias current
through the Stratix II diode, measuring forward voltage and converting
this reading to temperature in the form of an 8-bit signed number (7 bits
plus sign). The external device's output represents the junction
temperature of the Stratix II device and can be used for intelligent power
management.
Temperature
Sensing Diode
(TSD)
The diode requires two pins (tempdiodepand tempdioden) on the
Stratix II device to connect to the external temperature-sensing device, as
shown in Figure 3–1. The temperature sensing diode is a passive element
and therefore can be used before the Stratix II device is powered.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Temperature Sensing Diode (TSD)
Figure 3–1. External Temperature-Sensing Diode
Stratix II Device
Temperature-Sensing
Device
tempdiodep
tempdioden
Table 3–6 shows the specifications for bias voltage and current of the
Stratix II temperature sensing diode.
Table 3–6. Temperature-Sensing Diode Electrical Characteristics
Parameter
Minimum
Typical
Maximum
Unit
IBIAS high
80
8
100
10
120
12
μA
μA
V
IBIAS low
VBP - VBN
VBN
0.3
0.9
0.7
V
Series resistance
3
Ω
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Configuration & Testing
The temperature-sensing diode works for the entire operating range, as
shown in Figure 3–2.
Figure 3–2. Temperature vs. Temperature-Sensing Diode Voltage
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
100 μA Bias Current
10 μA Bias Current
Voltage
(Across Diode)
–55
–30
–5
20
45
70
95
120
Temperature (˚C)
The temperature sensing diode is a very sensitive circuit which can be
influenced by noise coupled from other traces on the board, and possibly
within the device package itself, depending on device usage. The
interfacing device registers temperature based on milivolts of difference
as seen at the TSD. Switching I/O near the TSD pins can affect the
temperature reading. Altera recommends you take temperature readings
during periods of no activity in the device (for example, standby mode
where no clocks are toggling in the device), such as when the nearby I/Os
are at a DC state, and disable clock networks in the device.
Stratix II devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. Some applications that require the device to
operate error free at high elevations or in close proximity to Earth’s North
or South Pole require periodic checks to ensure continued data integrity.
The error detection cyclic redundancy check (CRC) feature controlled by
Automated
Single Event
Upset (SEU)
Detection
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Document Revision History
the Device & Pin Options dialog box in the Quartus II software uses a
32-bit CRC circuit to ensure data reliability and is one of the best options
for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Stratix II devices, eliminating the need for external logic. For Stratix II
devices, CRC is computed by the device during configuration and
checked against an automatically computed CRC during normal
operation. The CRC_ERRORpin reports a soft error when configuration
SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix II devices to perform error
detection automatically. This error detection circuitry in Stratix II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. You can monitor one external pin for the error and
use it to trigger a re-configuration cycle. You can select the desired time
between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the FPGA device.
For more information on CRC, refer to AN 357: Error Detection Using CRC
in Altera FPGA Devices.
Table 3–7 shows the revision history for this chapter.
Document
Revision History
Table 3–7. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v4.2 Moved Document Revision History section to the end
of the chapter.
—
—
Updated the “Temperature Sensing Diode (TSD)”
section.
3–14
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May 2007
Stratix II Device Handbook, Volume 1
Configuration & Testing
Table 3–7. Document Revision History (Part 2 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
April 2006,
v4.1
Updated “Device Security Using Configuration
Bitstream Encryption” section.
—
—
—
December
2005, v4.0
Updated “Software Interface” section.
May 2005, v3.0
●
Updated “IEEE Std. 1149.1 JTAG Boundary-Scan
Support” section.
●
Updated “Operating Modes” section.
January 2005, Updated JTAG chain device limits.
v2.1
—
—
—
January 2005, Updated Table 3–3.
v2.0
July 2004, v1.1
●
●
●
Added “Automated Single Event Upset (SEU)
Detection” section.
Updated “Device Security Using Configuration
Bitstream Encryption” section.
Updated Figure 3–2.
February2004, Added document to the Stratix II Device Handbook.
v1.0
—
Altera Corporation
May 2007
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Document Revision History
3–16
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Stratix II Device Handbook, Volume 1
4. Hot Socketing &
Power-On Reset
SII51004-3.2
Stratix® II devices offer hot socketing, which is also known as hot plug-in
or hot swap, and power sequencing support without the use of any
external devices. You can insert or remove a Stratix II board in a system
during system operation without causing undesirable effects to the
running system bus or the board that was inserted into the system.
The hot socketing feature also removes some of the difficulty when you
use Stratix II devices on printed circuit boards (PCBs) that also contain a
mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the Stratix II hot
socketing feature, you no longer need to ensure a proper power-up
sequence for each device on the board.
The Stratix II hot socketing feature provides:
■
Board or device insertion and removal without external components
or board manipulation
■
■
Support for any power-up sequence
Non-intrusive I/O buffers to system buses during hot insertion
This chapter also discusses the power-on reset (POR) circuitry in Stratix II
devices. The POR circuitry keeps the devices in the reset state until the
VCC is within operating range.
Stratix II devices offer hot socketing capability with all three features
listed above without any external components or special design
requirements. The hot socketing feature in Stratix II devices allows:
Stratix II
Hot-Socketing
Specifications
■
■
The device can be driven before power-up without any damage to
the device itself.
I/O pins remain tri-stated during power-up. The device does not
drive out before or during power-up, thereby affecting other buses in
operation.
■
Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies.
External input signals to I/O pins of the device do not internally
power the VCCIO or VCCINT power supplies of the device via internal
paths within the device.
Altera Corporation
May 2007
4–1
Stratix II Hot-Socketing Specifications
Devices Can Be Driven Before Power-Up
You can drive signals into the I/O pins, dedicated input pins and
dedicated clock pins of Stratix II devices before or during power-up or
power-down without damaging the device. Stratix II devices support any
power-up or power-down sequence (VCCIO, VCCINT, and VCCPD) in order
to simplify system level design.
I/O Pins Remain Tri-Stated During Power-Up
A device that does not support hot-socketing may interrupt system
operation or cause contention by driving out before or during power-up.
In a hot socketing situation, Stratix II device's output buffers are turned
off during system power-up or power-down. Stratix II device also does
not drive out until the device is configured and has attained proper
operating conditions.
Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power
Supplies
Devices that do not support hot-socketing can short power supplies
together when powered-up through the device signal pins. This irregular
power-up can damage both the driving and driven devices and can
disrupt card power-up.
Stratix II devices do not have a current path from I/O pins, dedicated
input pins, or dedicated clock pins to the VCCIO, VCCINT, or VCCPD pins
before or during power-up. A Stratix II device may be inserted into (or
removed from) a powered-up system board without damaging or
interfering with system-board operation. When hot-socketing, Stratix II
devices may have a minimal effect on the signal integrity of the
backplane.
1
You can power up or power down the VCCIO, VCCINT, and VCCPD
pins in any sequence. The power supply ramp rates can range
from 100 μs to 100 ms. All VCC supplies must power down
within 100 ms of each other to prevent I/O pins from driving
out. During hot socketing, the I/O pin capacitance is less than 15
pF and the clock pin capacitance is less than 20 pF. Stratix II
devices meet the following hot socketing specification.
■
■
The hot socketing DC specification is: | IIOPIN | < 300 μA.
The hot socketing AC specification is: | IIOPIN | < 8 mA for 10 ns or
less.
4–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Hot Socketing & Power-On Reset
IIOPIN is the current at any user I/O pin on the device. This specification
takes into account the pin capacitance, but not board trace and external
loading capacitance. Additional capacitance for trace, connector, and
loading needs must be considered separately. For the AC specification,
the peak current duration is 10 ns or less because of power-up transients.
For more information, refer to the Hot-Socketing & Power-Sequencing
Feature & Testing for Altera Devices white paper.
A possible concern regarding hot-socketing is the potential for latch-up.
Latch-up can occur when electrical subsystems are hot-socketed into an
active system. During hot-socketing, the signal pins may be connected
and driven by the active system before the power supply can provide
current to the device's VCC and ground planes. This condition can lead to
latch-up and cause a low-impedance path from VCC to ground within the
device. As a result, the device extends a large amount of current, possibly
causing electrical damage. Nevertheless, Stratix II devices are immune to
latch-up when hot-socketing.
The hot socketing feature turns off the output buffer during the power-up
event (either VCCINT, VCCIO, or VCCPD supplies) or power down. The hot-
socket circuit will generate an internal HOTSCKTsignal when either
VCCINT, VCCIO, or VCCPD is below threshold voltage. The HOTSCKTsignal
will cut off the output buffer to make sure that no DC current (except for
weak pull up leaking) leaks through the pin. When VCC ramps up very
slowly, VCC is still relatively low even after the POR signal is released and
the configuration is finished. The CONF_DONE, nCEO, and nSTATUSpins
fail to respond, as the output buffer can not flip from the state set by the
hot socketing circuit at this low VCC voltage. Therefore, the hot socketing
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. It is expected behavior for
these pins to drive out during power-up and power-down sequences.
Hot Socketing
Feature
Implementation
in Stratix II
Devices
Each I/O pin has the following circuitry shown in Figure 4–1.
Altera Corporation
May 2007
4–3
Stratix II Device Handbook, Volume 1
Hot Socketing Feature Implementation in Stratix II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for Stratix II Devices
Power On
Reset
Monitor
Output
Weak
Pull-Up
R
Output Enable
Resistor
Voltage
Tolerance
Control
Hot Socket
PAD
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors VCCINT voltage level and keeps I/O pins tri-
stated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to VCCIO is present to keep the I/O pins from floating. The
3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V
before VCCIO and/or VCCINT and/or VCCPD are powered, and it prevents
the I/O pins from driving out when the device is not in user mode. The
hot socket circuit prevents I/O pins from internally powering VCCIO
,
VCCINT, and VCCPD when driven by external signals before the device is
powered.
Figure 4–2 shows a transistor level cross section of the Stratix II device
I/O buffers. This design ensures that the output buffers do not drive
when VCCIO is powered before VCCINT or if the I/O pad voltage is higher
than VCCIO. This also applies for sudden voltage spikes during hot
insertion. There is no current path from signal I/O pins to VCCINT or VCCIO
or VCCPD during hot insertion. The VPAD leakage current charges the 3.3-V
tolerant circuit capacitance.
4–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Hot Socketing & Power-On Reset
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
V
Logic Array
Signal
PAD
(1)
(2)
V
CCIO
n+
n+
p+
p+
n-well
n+
p-well
p-substrate
Notes to Figure 4–2:
(1) This is the logic array signal or the larger of either the VCCIO or VPAD signal.
(2) This is the larger of either the VCCIO or VPAD signal.
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the VCCINT, VCCIO, and VCCPD voltage
levels and tri-states all the user I/O pins while VCC is ramping up until
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array
VCCINT voltage, reach an acceptable level before configuration is
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the VCCINT voltage level so that a brown-out
condition during user mode can be detected. If there is a VCCINT voltage
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
Power-On Reset
Circuitry
When power is applied to a Stratix II device, a power-on-reset event
occurs if VCC reaches the recommended operating range within a certain
period of time (specified as a maximum VCC rise time). The maximum
VCC rise time for Stratix II device is 100 ms. Stratix II devices provide a
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSELpin is connected to ground, the POR
time is 100 ms. When the PORSELpin is connected to VCC, the POR time
is 12 ms.
Altera Corporation
May 2007
4–5
Stratix II Device Handbook, Volume 1
Document Revision History
Table 4–1 shows the revision history for this chapter.
Document
Revision History
Table 4–1. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v3.2 Moved the Document Revision History section to the
end of the chapter.
—
April 2006,
v3.1
●
Updated “Signal Pins Do Not Drive the VCCIO,
VCCINT or VCCPD Power Supplies” section.
●
Updated hot socketing AC
specification.
May 2005, v3.0
●
●
Updated “Signal Pins Do Not Drive the VCCIO,
VCCINT or VCCPD Power Supplies” section.
Removed information on ESD protection.
—
January 2005, Updated input rise and fall time.
v2.1
—
—
January 2005, Updated the “Hot Socketing Feature Implementation in
v2.0
Stratix II Devices”, “ESD Protection”, and “Power-On
Reset Circuitry” sections.
July 2004, v1.1
●
●
Updated all tables.
Added tables.
—
—
February2004, Added document to the Stratix II Device Handbook.
v1.0
4–6
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
5. DC & Switching
Characteristics
SII51005-4.5
Stratix® II devices are offered in both commercial and industrial grades.
Industrial devices are offered in -4 speed grades and commercial devices
are offered in -3 (fastest), -4, -5 speed grades.
Operating
Conditions
Tables 5–1 through 5–32 provide information about absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Stratix II devices.
Absolute Maximum Ratings
Table 5–1 contains the absolute maximum ratings for the Stratix II device
family.
Table 5–1. Stratix II Device Absolute Maximum Ratings
Notes (1), (2), (3)
Symbol
VCCINT
VCCIO
Parameter
Conditions
Minimum
–0.5
Maximum
1.8
Unit
V
Supply voltage
With respect to ground
With respect to ground
With respect to ground
With respect to ground
Supply voltage
Supply voltage
–0.5
4.6
V
VCCPD
VCCA
–0.5
4.6
V
Analog power supply for
PLLs
–0.5
1.8
V
VCCD
VI
Digital power supply for PLLs With respect to ground
DC input voltage (4)
–0.5
–0.5
–25
–65
–55
1.8
4.6
40
V
V
IOUT
TSTG
TJ
DC output current, per pin
mA
°C
°C
Storage temperature
Junction temperature
No bias
150
125
BGA packages under bias
Notes to Tables 5–1
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 5–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4) During transitions, the inputs may overshoot to the voltage shown in Table 5–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Altera Corporation
April 2011
5–1
Operating Conditions
Table 5–2. Maximum Duty Cycles in Voltage Transitions
Maximum
Duty Cycles
Symbol
Parameter
Condition
Unit
VI
Maximum duty cycles
in voltage transitions
VI = 4.0 V
VI = 4.1 V
VI = 4.2 V
VI = 4.3 V
VI = 4.4 V
VI = 4.5 V
100
90
50
30
17
10
%
%
%
%
%
%
Recommended Operating Conditions
Table 5–3 contains the Stratix II device family recommended operating
conditions.
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 1 of 2)
Note (1)
Symbol
VCCINT
VCCIO
Parameter
Conditions
Minimum Maximum Unit
Supply voltage for internal logic
100 μs ≤ risetime ≤ 100 ms (3)
100 μs ≤ risetime ≤ 100 ms (3), (6)
1.15
1.25
V
V
Supply voltage for input and
output buffers, 3.3-V operation
3.135
(3.00)
3.465
(3.60)
Supply voltage for input and
output buffers, 2.5-V operation
100 μs ≤ risetime ≤ 100 ms (3)
100 μs ≤ risetime ≤ 100 ms (3)
2.375
2.625
V
V
V
V
V
Supply voltage for input and
output buffers, 1.8-V operation
1.71
1.89
Supply voltage for output buffers, 100 μs ≤ risetime ≤ 100 ms (3)
1.5-V operation
1.425
1.14
1.575
1.26
Supply voltage for input and
output buffers, 1.2-V operation
100 μs ≤ risetime ≤ 100 ms (3)
VCCPD
Supply voltage for pre-drivers as 100 μs ≤ risetime ≤ 100 ms (4)
well as configuration and JTAG
3.135
3.465
I/O buffers.
VCCA
VCCD
VI
Analog power supply for PLLs
Digital power supply for PLLs
Input voltage (see Table 5–2)
Output voltage
100 μs ≤ risetime ≤ 100 ms (3)
100 μs ≤ risetime ≤ 100 ms (3)
(2), (5)
1.15
1.15
–0.5
0
1.25
1.25
4.0
V
V
V
V
VO
VCCIO
5–2
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Minimum Maximum Unit
TJ
Operating junction temperature
For commercial use
For industrial use
For military use (7)
0
85
°C
°C
°C
–40
–55
100
125
Notes to Table 5–3:
(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(2) During transitions, the inputs may overshoot to the voltage shown in Table 5–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
(3) Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VCC
.
(4) VCCPD must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If VC CPD is not ramped up within this specified
time, your Stratix II device does not configure successfully. If your system does not allow for a VCCPD ramp-up time
of 100 ms or less, you must hold nCONFIGlow until all power supplies are reliable.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO
are powered.
(6) VC CIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
(7) For more information, refer to the Stratix II Military Temperature Range Support technical brief.
DC Electrical Characteristics
Table 5–4 shows the Stratix II device family DC electrical characteristics.
Table 5–4. Stratix II Device DC Operating Conditions (Part 1 of 2)
Symbol Parameter Conditions
Note (1)
Minimum Typical Maximum Unit
II
IOZ
Input pin leakage current VI = VCCIOmax to 0 V (2)
–10
–10
10
10
μA
μA
Tri-stated I/O pin
leakage current
VO = VCCIOmax to 0 V (2)
ICCINT0 VCCINT supply current
(standby)
VI = ground, no
load, no toggling
inputs
EP2S15
0.25
0.30
0.50
0.62
0.82
1.12
2.2
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
A
A
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
A
TJ = 25° C
A
A
A
ICCPD0
VCCPD supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25° C,
VCCPD = 3.3V
mA
mA
mA
mA
mA
mA
2.7
3.6
4.3
5.4
6.8
Altera Corporation
April 2011
5–3
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–4. Stratix II Device DC Operating Conditions (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Minimum Typical Maximum Unit
ICCI00
VCCIO supply current
(standby)
VI = ground, no
load, no toggling
inputs
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
4.0
4.0
4.0
4.0
4.0
4.0
25
35
50
75
90
1
(3)
(3)
(3)
(3)
(3)
(3)
50
mA
mA
mA
mA
mA
mA
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
TJ = 25° C
RCONF (4) Value of I/O pin pull-up
resistor before and
Vi = 0; VCCIO = 3.3 V
Vi = 0; VCCIO = 2.5 V
Vi = 0; VCCIO = 1.8 V
Vi = 0; VCCIO = 1.5 V
Vi = 0; VCCIO = 1.2 V
10
15
30
40
50
70
during configuration
100
150
170
2
Recommended value of
I/O pin external
pull-downresistorbefore
and during configuration
Notes to Table 5–4:
(1) Typical values are for TA = 25°C, VCCINT = 1.2 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
(3) Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power
Estimator (available at www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum
values. See the section “Power Consumption” on page 5–20 for more information.
(4) Pin pull-up resistance values are lower if an external source drives the pin higher than VCCIO
.
I/O Standard Specifications
Tables 5–5 through 5–32 show the Stratix II device family I/O standard
specifications.
Table 5–5. LVTTL Specifications (Part 1 of 2)
Symbol
VCCIO (1)
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Conditions
Minimum
3.135
1.7
Maximum
3.465
4.0
Unit
V
V
VIL
–0.3
0.8
V
VOH
IOH = –4 mA (2)
2.4
V
5–4
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–5. LVTTL Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VOL
Low-level output voltage
IOL = 4 mA (2)
0.45
V
Notes to Tables 5–5:
(1) Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
(2) This specification is supported across all the programmable drive strength settings available for this I/O standard
as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–6. LVCMOS Specifications
Symbol
VCCIO (1)
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Conditions
Minimum
3.135
1.7
Maximum
3.465
4.0
Unit
V
V
VIL
–0.3
0.8
V
VOH
VCCIO = 3.0,
V
CCIO – 0.2
V
IOH = –0.1 mA (2)
VOL
Low-level output voltage
VCCIO = 3.0,
0.2
V
IOL = 0.1 mA (2)
Notes to Table 5–6:
(1) Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
(2) This specification is supported across all the programmable drive strength available for this I/O standard as
shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–7. 2.5-V I/O Specifications
Symbol
VCCIO (1)
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Conditions
Minimum
2.375
1.7
Maximum
2.625
4.0
Unit
V
V
VIL
–0.3
0.7
V
IOH = –1mA (2)
IOL = 1 mA (2)
2.0
V
VOH
VOL
Low-level output voltage
0.4
V
Notes to Table 5–7:
(1) Stratix II devices VCC IO voltage level support of 2.5 -5% is narrower than defined in the Normal Range of the
EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Altera Corporation
April 2011
5–5
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–8. 1.8-V I/O Specifications
Symbol
VCCIO (1)
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
Minimum
1.71
Maximum
1.89
Unit
V
0.65 × VCCIO
–0.30
2.25
V
VIL
0.35 × VCCIO
V
VOH
IOH = –2 mA (2)
IOL = 2 mA (2)
VCCIO – 0.45
V
VOL
0.45
V
Notes to Table 5–8:
(1) The Stratix II device family’s VC CIO voltage level support of 1.8 -5% is narrower than defined in the Normal
Range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–9. 1.5-V I/O Specifications
Symbol
VCCIO (1)
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
Minimum
1.425
Maximum
1.575
Unit
V
0.65 × VCCIO
–0.30
VCCIO + 0.30
0.35 × VCCIO
V
VIL
V
VOH
IOH = –2 mA (2)
IOL = 2 mA (2)
0.75 × VCCIO
V
VOL
0.25 × VCCIO
V
Notes to Table 5–9:
(1) The Stratix II device family’s VC CIO voltage level support of 1.5 -5% is narrower than defined in the Normal
Range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Figures 5–1 and 5–2 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS,
LVPECL, and HyperTransport technology).
5–6
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Figure 5–1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p − n = 0 V
V
ID
Figure 5–2. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p − n = 0 V
V
OD
Altera Corporation
April 2011
5–7
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–10. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
2.375
2.500
2.625
V
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
VOD
Input common mode voltage
200
250
1,250
1,800
450
mV
mV
Output differential voltage
(single-ended)
RL = 100 Ω
RL = 100 Ω
VOCM
RL
Output common mode
voltage
1.125
90
1.375
110
V
Receiver differential input
discrete resistor (external to
Stratix II devices)
100
Ω
Table 5–11. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
VCCIO (1)
I/O supply voltage for top
and bottom PLL banks (9,
10, 11, and 12)
3.135
3.300
3.465
V
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
VOD
Input common mode voltage
200
250
1,250
1,800
710
mV
mV
Output differential voltage
(single-ended)
RL = 100 Ω
RL = 100 Ω
VOCM
RL
Output common mode
voltage
840
90
1,570
110
mV
Receiver differential input
discrete resistor (external to
Stratix II devices)
100
Ω
Note to Table 5–11:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUTshould be connected to 3.3 V.
.
5–8
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–12. LVPECL Specifications
Symbol
VCCIO (1)
VID
Parameter
Conditions
Minimum
3.135
Typical
3.300
600
Maximum Unit
I/O supply voltage
3.465
1,000
V
Input differential voltage
swing (single-ended)
300
mV
VICM
VOD
Input common mode voltage
1.0
2.5
V
Output differential voltage
(single-ended)
RL = 100 Ω
RL = 100 Ω
525
970
mV
VOCM
RL
Output common mode
voltage
1,650
90
2,250
110
mV
Receiver differential input
resistor
100
Ω
Note to Table 5–12:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUTshould be connected to 3.3 V.
.
Table 5–13. HyperTransport Technology Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and 6)
2.375
2.500
2.625
V
VID
Input differential voltage swing RL = 100 Ω
300
600
900
mV
(single-ended)
VICM
VOD
Input common mode voltage
RL = 100 Ω
RL = 100 Ω
385
400
600
600
845
820
mV
mV
Output differential voltage
(single-ended)
Δ VOD
Change in VOD between high
and low
RL = 100 Ω
75
mV
VOCM
Output common mode voltage RL = 100 Ω
440
90
600
100
780
50
mV
mV
Δ VOCM
Change in VOCM between high RL = 100 Ω
and low
RL
Receiver differential input
resistor
110
Ω
Table 5–14. 3.3-V PCI Specifications (Part 1 of 2)
Symbol
VCCIO
VIH
Parameter
Output supply voltage
High-level input voltage
Conditions
Minimum
3.0
Typical
Maximum Unit
3.3
3.6
V
V
0.5 × VCCIO
VCCIO + 0.5
Altera Corporation
April 2011
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Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–14. 3.3-V PCI Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
–0.3
Typical
Typical
Maximum Unit
VIL
Low-level input voltage
High-level output voltage
Low-level output voltage
0.3 × VCCIO
V
V
V
VOH
VOL
IOUT = –500 μA
IOUT = 1,500 μA
0.9 × VCCIO
0.1 × VCCIO
Table 5–15. PCI-X Mode 1 Specifications
Symbol
VCCIO
VIH
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
Input pull-up voltage
Conditions
Minimum
3.0
Maximum Unit
3.6
V
V
V
V
V
V
0.5 × VCCIO
–0.30
VCCIO + 0.5
0.35 × VCCIO
VIL
VIPU
0.7 × VCCIO
0.9 × VCCIO
VOH
High-level output voltage
Low-level output voltage
IOUT = –500 μA
IOUT = 1,500 μA
VOL
0.1 × VCCIO
Table 5–16. SSTL-18 Class I Specifications
Symbol
VCCIO
VREF
Parameter
Conditions
Minimum
1.71
Typical
1.80
Maximum Unit
Output supply voltage
Reference voltage
1.89
0.945
V
V
V
V
V
V
V
V
V
0.855
0.900
VREF
VTT
Termination voltage
VREF – 0.04
VREF + 0.125
VREF + 0.04
V
V
V
V
IH (DC)
IL (DC)
IH (AC)
IL (AC)
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
VREF – 0.125
VREF – 0.25
VTT – 0.475
VREF + 0.25
VTT + 0.475
VOH
VOL
IOH = –6.7 mA (1)
IOL = 6.7 mA (1)
Note to Table 5–16:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–10
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April 2011
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DC & Switching Characteristics
Table 5–17. SSTL-18 Class II Specifications
Symbol
VCCIO
VREF
Parameter
Output supply voltage
Reference voltage
Termination voltage
Conditions
Minimum
1.71
Typical
1.80
Maximum Unit
1.89
0.945
V
V
V
V
V
V
V
V
V
0.855
0.900
VREF
VTT
VREF – 0.04
VREF + 0.125
VREF + 0.04
V
V
V
V
IH (DC) High-level DC input voltage
IL (DC) Low-level DC input voltage
IH (AC) High-level AC input voltage
IL (AC) Low-level AC input voltage
VREF – 0.125
VREF – 0.25
0.28
VREF + 0.25
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –13.4 mA (1) VCCIO – 0.28
IOL = 13.4 mA (1)
Note to Table 5–17:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–18. SSTL-18 Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
1.71
Typical
Maximum
Unit
V
VCCIO
Output supply voltage
1.80
1.89
VSWING DC differential input voltage
(DC)
0.25
V
VX (AC) AC differential input cross
point voltage
(VCCIO/2) – 0.175
0.5
(VCCIO/2) + 0.175
V
V
VSWING AC differential input voltage
(AC)
VISO
Input clock signal offset
voltage
0.5 × VCCIO
200
V
ΔVISO
Input clock signal offset
voltage variation
mV
V
VOX
(AC)
AC differential cross point
voltage
(VCCIO/2) – 0.125
(VCCIO/2) + 0.125
Altera Corporation
April 2011
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Operating Conditions
Table 5–19. SSTL-2 Class I Specifications
Symbol
VCCIO
VTT
Parameter
Conditions
Minimum
2.375
Typical
2.500
VREF
Maximum Unit
Output supply voltage
Termination voltage
2.625
VREF + 0.04
1.313
V
V
V
V
V
V
V
V
V
VREF – 0.04
1.188
VREF
Reference voltage
1.250
V
V
IH (DC)
IL (DC)
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
VREF + 0.18
–0.30
3.00
VREF – 0.18
VIH (AC)
VIL (AC)
VOH
VREF + 0.35
VREF - 0.35
VTT – 0.57
IOH = –8.1 mA (1)
IOL = 8.1 mA (1)
VTT + 0.57
VOL
Note to Table 5–19:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–20. SSTL-2 Class II Specifications
Symbol
VCCIO
VTT
Parameter
Conditions
Minimum
2.375
Typical
2.500
VREF
Maximum Unit
Output supply voltage
Termination voltage
2.625
V
V
V
V
V
V
V
V
V
VREF – 0.04
1.188
VREF + 0.04
1.313
VREF
Reference voltage
1.250
V
V
IH (DC)
IL (DC)
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
VREF + 0.18
–0.30
VCCIO + 0.30
VREF – 0.18
VIH (AC)
VIL (AC)
VOH
VREF + 0.35
VREF - 0.35
VTT – 0.76
IOH = –16.4 mA (1) VTT + 0.76
IOL = 16.4 mA (1)
VOL
Note to Table 5–20:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–12
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April 2011
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DC & Switching Characteristics
Table 5–21. SSTL-2 Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
2.375
Typical
Maximum
Unit
V
VCCIO
Output supply voltage
2.500
2.625
VSWING DC differential input voltage
(DC)
0.36
V
VX (AC) AC differential input cross
point voltage
(VCCIO/2) – 0.2
0.7
(VCCIO/2) + 0.2
V
V
VSWING AC differential input voltage
(AC)
VISO
Input clock signal offset
voltage
0.5 × VCCIO
200
V
ΔVISO
Input clock signal offset
voltage variation
mV
V
VOX
(AC)
AC differential output cross
point voltage
(VCCIO/2) – 0.2
(VCCIO/2) + 0.2
Table 5–22. 1.2-V HSTL Specifications
Symbol
VCCIO
Parameter
Output supply voltage
Reference voltage
Conditions
Minimum
Typical
Maximum
1.26
Unit
V
1.14
1.20
VREF
0.48 × VCCIO 0.50 × VCCIO
VREF + 0.08
–0.15
0.52 × VCCIO
VCCIO + 0.15
VREF – 0.08
VCCIO + 0.24
VREF – 0.15
VCCIO + 0.15
VREF – 0.15
V
V
V
V
V
IH (DC) High-level DC input voltage
V
IL (DC) Low-level DC input voltage
IH (AC) High-level AC input voltage
IL (AC) Low-level AC input voltage
V
VREF + 0.15
–0.24
V
V
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 8 mA
VREF + 0.15
–0.15
V
IOH = –8 mA
V
Altera Corporation
April 2011
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Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–23. 1.5-V HSTL Class I Specifications
Symbol
VCCIO
VREF
Parameter
Conditions
Minimum
1.425
Typical
1.500
0.750
0.750
Maximum Unit
Output supply voltage
Input reference voltage
Termination voltage
1.575
0.788
0.788
V
V
V
V
V
V
V
V
V
0.713
VTT
0.713
V
V
V
V
IH (DC)
IL (DC)
IH (AC)
IL (AC)
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.1
–0.3
VREF – 0.1
VREF – 0.2
0.4
VREF + 0.2
VOH
VOL
IOH = 8 mA (1)
IOH = –8 mA (1)
VCCIO – 0.4
Note to Table 5–23:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–24. 1.5-V HSTL Class II Specifications
Symbol
VCCIO
VREF
Parameter
Conditions
Minimum
1.425
Typical
1.500
0.750
0.750
Maximum Unit
Output supply voltage
Input reference voltage
Termination voltage
1.575
0.788
0.788
V
V
V
V
V
V
V
V
V
0.713
VTT
0.713
V
V
V
V
IH (DC)
IL (DC)
IH (AC)
IL (AC)
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.1
–0.3
VREF – 0.1
VREF – 0.2
0.4
VREF + 0.2
VOH
VOL
IOH = 16 mA (1)
IOH = –16 mA (1)
VCCIO – 0.4
Note to Table 5–24:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–14
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April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–25. 1.5-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
1.425
0.2
Typical
Maximum Unit
VCCIO
I/O supply voltage
1.500
1.575
V
V
V
V
V
DIF (DC) DC input differential voltage
CM (DC) DC common mode input
voltage
0.68
0.90
V
V
DIF (AC) AC differential input voltage
0.4
V
V
OX (AC) AC differential cross point
voltage
0.68
0.90
Table 5–26. 1.8-V HSTL Class I Specifications
Symbol
VCCIO
VREF
Parameter
Conditions
Minimum
1.71
Typical
1.80
Maximum Unit
Output supply voltage
Input reference voltage
Termination voltage
1.89
0.95
0.95
V
V
V
V
V
V
V
V
V
0.85
0.90
VTT
0.85
0.90
V
V
V
V
IH (DC)
IL (DC)
IH (AC)
IL (AC)
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.1
–0.3
VREF – 0.1
VREF – 0.2
0.4
VREF + 0.2
VOH
VOL
IOH = 8 mA (1)
IOH = –8 mA (1)
VCCIO – 0.4
Note to Table 5–26:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Altera Corporation
April 2011
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Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–27. 1.8-V HSTL Class II Specifications
Symbol
VCCIO
VREF
Parameter
Conditions
Minimum
1.71
Typical
1.80
Maximum Unit
Output supply voltage
Input reference voltage
Termination voltage
1.89
0.95
0.95
V
V
V
V
V
V
V
V
V
0.85
0.90
VTT
0.85
0.90
V
V
V
V
IH (DC)
IL (DC)
IH (AC)
IL (AC)
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.1
–0.3
VREF – 0.1
VREF – 0.2
0.4
VREF + 0.2
VOH
VOL
IOH = 16 mA (1)
IOH = –16 mA (1)
VCCIO – 0.4
Note to Table 5–27:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–28. 1.8-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
1.71
Typical
Maximum
1.89
Unit
V
VCCIO
I/O supply voltage
1.80
V
V
DIF (DC) DC input differential voltage
0.2
VCCIO + 0.6 V
1.12
V
CM (DC) DC common mode input
voltage
0.78
V
V
V
DIF (AC) AC differential input voltage
0.4
VCCIO + 0.6 V
0.90
V
V
OX (AC) AC differential cross point
voltage
0.68
5–16
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April 2011
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DC & Switching Characteristics
Bus Hold Specifications
Table 5–29 shows the Stratix II device family bus hold specifications.
Table 5–29. Bus Hold Parameters
VCCIO Level
1.8 V
Parameter Conditions
Unit
μA
1.2 V
1.5 V
2.5 V
3.3 V
Min
Max
Min Max Min Max Min
Max Min Max
Low
V
IN > VIL
22.5
25.0
30.0
50.0
70.0
sustaining
current
(maximum)
High
V
IN < VIH
–22.5
–25.0
–30.0
–50.0
–70.0
μA
sustaining
current
(minimum)
Low
overdrive
current
0 V < VIN
VCCIO
<
120
–120
0.95
160
–160
1.00
200
–200
1.07
300
500
μA
High
overdrive
current
0 V < VIN
VCCIO
<
–300
–500 μA
Bus-hold
trip point
0.45
0.50
0.68
0.70
1.70 0.80 2.00
V
On-Chip Termination Specifications
Tables 5–30 and 5–31 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
25-Ω RS Internal series termination with
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
5
10
%
3.3/2.5
Internal series termination without VCCIO = 3.3/2.5 V
30
30
%
calibration (25-Ω setting)
Altera Corporation
April 2011
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Operating Conditions
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
50-Ω RS Internal series termination with
calibration (50-Ω setting)
VCCIO = 3.3/2.5 V
5
10
30
30
10
30
10
30
15
10
36
15
10
50
15
%
3.3/2.5
Internal series termination without VCCIO = 3.3/2.5 V
calibration (50-Ω setting)
30
30
5
%
%
%
%
%
%
%
%
%
%
%
%
%
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
VCCIO = 1.8 V
2.5
25-Ω RS Internal series termination with
calibration (25-Ω setting)
1.8
Internal series termination without VCCIO = 1.8 V
calibration (25-Ω setting)
30
5
50-Ω RS Internal series termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
1.8
Internal series termination without VCCIO = 1.8 V
calibration (50-Ω setting)
30
10
8
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
VCCIO = 1.5 V
1.8
50−Ω RS Internal series termination with
calibration (50-Ω setting)
1.5
Internal series termination without VCCIO = 1.5 V
calibration (50-Ω setting)
36
10
8
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.5 V
VCCIO = 1.2 V
1.5
50−Ω RS Internal series termination with
calibration (50-Ω setting)
1.2
Internal series termination without VCCIO = 1.2 V
calibration (50-Ω setting)
50
10
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.2 V
1.2
Notes for Table 5–30:
(1) The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or
voltage changes over time, the tolerance may also change.
(2) On-chip parallel termination with calibration is only supported for input pins.
5–18
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April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks
Resistance Tolerance
Commercial Industrial
Symbol
Description
Conditions
Unit
Max
Max
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
VCCIO = 3.3/2.5/1.8 V
VCCIO = 1.5 V
30
30
%
50-Ω RS
3.3/2.5/1.8
Internal series termination without
calibration (50-Ω setting)
30
36
20
30
36
25
%
%
%
50-Ω RS 1.5 Internal series termination without
calibration (50-Ω setting)
RD
VCCIO = 2.5 V
Internal differential termination for
LVDS or HyperTransport technology
(100-Ω setting)
Pin Capacitance
Table 5–32 shows the Stratix II device family pin capacitance.
Table 5–32. Stratix II Device Capacitance
Symbol
Note (1)
Parameter
Typical
5.0
Unit
pF
CIOTB
CIOLR
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-
speed differential receiver and transmitter pins.
6.1
pF
CCLKTB
6.0
pF
Input capacitance on top/bottom clock input pins: CLK[4..7]and
CLK[12..15].
CCLKLR
6.1
3.3
pF
pF
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK8, CLK10.
CCLKLR+
Input capacitance on left/right clock inputs: CLK1, CLK3, CLK9, and
CLK11.
COUTFB
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 9, 10, 11, and 12.
6.7
pF
Note to Table 5–32:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within 0.5pF
Altera Corporation
April 2011
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Stratix II Device Handbook, Volume 1
Power Consumption
Altera® offers two ways to calculate power for a design: the Excel-based
PowerPlay Early Power Estimator power calculator and the Quartus® II
PowerPlay Power Analyzer feature.
Power
Consumption
The interactive Excel-based PowerPlay Early Power Estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay Power Analyzer provides better
quality estimates based on the specifics of the design after place-and-
route is complete. The Power Analyzer can apply a combination of user-
entered, simulation-derived and estimated signal activities which,
combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
f
For more information about PowerPlay tools, refer to the PowerPlay Early
Power Estimator User Guide and the PowerPlay Early Power Estimator and
PowerPlay Power Analyzer chapters in volume 3 of the Quartus II
Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site
at www.altera.com. See Table 5–4 on page 5–3 for typical ICC standby
specifications.
TM
TM
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II device densities and speed grades. This
section describes and specifies the performance, internal timing, external
timing, and PLL, high-speed I/O, external memory interface, and JTAG
timing specifications.
Timing Model
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
1
The timing numbers listed in the tables of this section are
extracted from the Quartus II software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 5–33 shows the status of the
Stratix II device timing models.
5–20
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Stratix II Device Handbook, Volume 1
April 2011
DC & Switching Characteristics
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 5–33. Stratix II Device Timing Model Status
Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Preliminary
Final
v
v
v
v
v
v
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (tSU
)
and hold time (tH). The Quartus II software uses the following equations
to calculate tSU and tH timing for Stratix II devices input signals.
tSU = + data delay from input pin to input register
+ micro setup time of the input register
– clock delay from input pin to input register
tH = – data delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
Figure 5–3 shows the setup and hold timing diagram for input registers.
Altera Corporation
April 2011
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Stratix II Device Handbook, Volume 1
Timing Model
Figure 5–3. Input Register Setup & Hold Timing Diagram
Input Data Delay
micro t
micro t
SU
H
Input Clock Delay
For output timing, different I/O standards require different baseline
loading techniques for reporting timing delays. Altera characterizes
timing delays with the required termination for each I/O standard and
with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the
timing is specified up to the output pin of the FPGA device. The
Quartus II software calculates the I/O timing for each I/O standard with
a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in Table 5–34. Use the following equations to calculate
clock pin to output pin timing for Stratix II devices.
tCO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay from
output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay + output
enable pin delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup,
using values from Table 5–34.
2. Record the time to VMEAS
.
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
5–22
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
4. Record the time to VMEAS
.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5–34 using the above equation. Figure 5–4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
V
TT
V
CCIO
Output
Output
R
C
p
n
T
L
R
S
Output
Output
Buffer
R
D
V
MEAS
GND
GND
Notes to Figure 5–4:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCPD is 3.085 V unless otherwise specified.
(3) VCCINT is 1.12 V unless otherwise specified.
Figures 5–5 and 5–6 show the measurement setup for output disable and
output enable timing.
Altera Corporation
April 2011
5–23
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–34. Output Timing Measurement Methodology for Output Pins
Notes (1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω) VCCIO (V) VTT (V) CL (pF)
VMEAS (V)
LVTTL (4)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
0
0
0
0
0
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
LVCMOS (4)
2.5 V (4)
1.8 V (4)
1.5 V (4)
PCI (5)
PCI-X (5)
SSTL-2 Class I
25
25
25
25
50
25
50
50
25
50
25
50
25
50
25
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
0.83
0.83
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
50
50
25
50
25
50
50
25
50
25
50
25
50
25
1.123
1.123
0.790
0.790
0.648
0.648
0.790
0.790
0.83
0.6875
0.6875
0.83
50
25
0.83
100
100
100
1.1625
1.1625
1.5675
HyperTransport
LVPECL
Notes to Table 5–34:
(1) Input measurement point at internal node is 0.5 × VCCINT
.
(2) Output measuring point for VMEAS at buffer output is 0.5 × VCCIO
.
(3) Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
(4) Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
(5) VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
5–24
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Figure 5–5. Measurement Setup for txz
Note (1)
t
, Driving High to Tristate
XZ
Enable
Disable
OE
Din
OE
Dout
½ V
CCINT
“1”
100 mv
Din
100 Ω
Dout
GND
t
hz
t
, Driving Low to Tristate
XZ
Enable
Disable
OE
½ V
CCINT
100 Ω
OE
Din
Dout
Din
“0”
t
lz
V
CCIO
Dout
100 mv
Note to Figure 5–5:
(1) VCCINT is 1.12 V for this measurement.
Altera Corporation
April 2011
5–25
Stratix II Device Handbook, Volume 1
Timing Model
Figure 5–6. Measurement Setup for tzx
t
, Tristate to Driving High
ZX
Disable Enable
½ V
CCINT
OE
Din
OE
Din
Dout
“1”
1 MΩ
t
Dout
zh
½ V
CCIO
t
, Tristate to Driving Low
ZX
Disable Enable
½ V
CCINT
OE
Din
1 MΩ
Dout
OE
Din
“0”
½ V
t
CCIO
zl
Dout
Table 5–35 specifies the input timing measurement setup.
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2)
Notes (1)–(4)
Measurement Conditions
I/O Standard
Measurement Point
VMEAS (V)
VCCIO (V)
VREF (V)
Edge Rate (ns)
LVTTL (5)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
LVCMOS (5)
2.5 V (5)
1.8 V (5)
1.5 V (5)
PCI (6)
PCI-X (6)
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.163
1.163
0.830
0.830
0.830
0.83
0.83
5–26
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–35. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Notes (1)–(4)
Measurement Conditions
I/O Standard
Measurement Point
VCCIO (V)
VREF (V)
VMEAS (V)
Edge Rate (ns)
1.8-V HSTL Class II
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
0.830
0.688
0.688
0.570
1.163
1.163
0.830
0.830
0.688
0.688
0.830
0.830
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
0.100
0.400
0.100
0.83
0.6875
0.6875
0.570
1.1625
1.1625
0.83
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
0.83
0.6875
0.6875
0.83
0.83
1.1625
1.1625
1.5675
HyperTransport
LVPECL
Notes to Table 5–35:
(1) Input buffer sees no load at buffer input.
(2) Input measuring point at buffer input is 0.5 × VCCIO
.
(3) Output measuring point is 0.5 × VCC at internal node.
(4) Input edge rate is 1 V/ns.
(5) Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
(6) VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Performance
Table 5–36 shows Stratix II performance for some common designs. All
performance values were obtained with the Quartus II software
compilation of library of parameterized modules (LPM), or MegaCore®
functions for the finite impulse response (FIR) and fast Fourier transform
(FFT) designs.
Altera Corporation
April 2011
5–27
Stratix II Device Handbook, Volume 1
Timing Model
1
The performance numbers in Table 5–36 are extracted from the
Quartus II software version 5.1 SP1.
Table 5–36. Stratix II Performance Notes (Part 1 of 6)
Note (1)
Resources Used
Performance
-4
-3
-3
TriMatrix
ALUTs Memory
Blocks
-5
Applications
DSP
Speed Speed
Speed Speed Unit
Grade Grade
Blocks Grade Grade
(2)
(3)
LE
16-to-1 multiplexer (4)
32-to-1 multiplexer (4)
16-bit counter
21
38
16
64
0
0
0
0
0
1
0
0
0
0
0
654.87
625.0
523.83
460.4 MHz
519.21 473.26 464.25 384.17 MHz
566.57 538.79 489.23 421.05 MHz
244.31 232.07 209.11 181.38 MHz
500.00 476.19 434.02 373.13 MHz
64-bit counter
TriMatrix Simpledual-portRAM
Memory
M512
block
32 × 18 bit
FIFO 32 x 18 bit
22
0
1
1
0
0
500.00 476.19 434.78 373.13 MHz
540.54 515.46 469.48 401.60 MHz
TriMatrix Simpledual-portRAM
Memory
M4K
block
128 x 36 bit (8)
True dual-port RAM
128 × 18 bit (8)
0
22
0
1
1
1
1
0
0
0
0
540.54 515.46 469.48 401.60 MHz
530.22 499.00 469.48 401.60 MHz
475.28 453.30 413.22 354.10 MHz
475.28 453.30 413.22 354.10 MHz
FIFO
128 × 36 bit
Simpledual-portRAM
128 × 36 bit (9)
True dual-port RAM
0
128 × 18 bit (9)
5–28
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 2 of 6)
Note (1)
Resources Used
Performance
-3
-3
TriMatrix
ALUTs Memory
Blocks
-4
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
TriMatrix Single port
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
349.65 333.33 303.95 261.09 MHz
420.16 400.00 364.96 313.47 MHz
349.65 333.33 303.95 261.09 MHz
354.60 337.83 307.69 263.85 MHz
420.16 400.00 364.96 313.47 MHz
349.65 333.33 303.95 261.09 MHz
364.96 347.22 317.46 271.73 MHz
420.16 400.00 364.96 313.47 MHz
359.71 342.46 313.47 268.09 MHz
364.96 347.22 317.46 271.73 MHz
Memory
M-RAM
block
RAM 4K × 144 bit
Simple dual-port
RAM 4K × 144 bit
True dual-port
RAM 4K × 144 bit
Single port
RAM 8K × 72 bit
Simple dual-port
RAM 8K × 72 bit
True dual-port
RAM 8K × 72 bit
Single port
RAM 16K × 36 bit
Simple dual-port
RAM 16K × 36 bit
True dual-port
RAM 16K × 36 bit
Single port
RAM 32K × 18 bit
Simple dual-port
RAM 32K × 18 bit
420.16
400.0
364.96 313.47 MHz
True dual-port
RAM 32K × 18 bit
359.71 342.46 313.47 268.09 MHz
364.96 347.22 317.46 271.73 MHz
Single port
RAM 64K × 9 bit
Simple dual-port
RAM 64K × 9 bit
420.16
400.0
364.96 313.47 MHz
True dual-port
359.71 342.46 313.47 268.09 MHz
RAM 64K × 9 bit
Altera Corporation
April 2011
5–29
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–36. Stratix II Performance Notes (Part 3 of 6)
Note (1)
Resources Used
Performance
-4
-3
-3
TriMatrix
ALUTs Memory
Blocks
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
DSP
block
9 × 9-bit multiplier (5)
0
0
0
0
1
1
430.29 409.16 373.13 320.10 MHz
410.17 390.01 356.12 305.06 MHz
18 × 18-bit
multiplier (5)
18 × 18-bit
multiplier (7)
0
0
0
0
1
1
1
1
4
9
450.04 428.08 391.23 335.12 MHz
250.00 238.15 217.48 186.60 MHz
410.17 390.01 356.12 305.06 MHz
410.17 390.01 356.12 305.06 MHz
259.06 240.61 217.15 185.01 MHz
398.72 364.03 355.23 306.37 MHz
36 × 36-bit
multiplier (5)
36 × 36-bit multiplier
(6)
0
0
18-bit, four-tap FIR
filter
0
0
Larger
designs
8-bit,16-tap parallel
FIR filter
58
2976
0
8-bit, 1024-point,
streaming, three
22
multipliers and five
adders FFT function
8-bit, 1024-point,
streaming, four
multipliers and two
adders FFT function
2781
984
22
5
12
3
398.56 409.16 347.22 311.13 MHz
425.17 365.76 346.98 292.39 MHz
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst,threemultipliers
and five adders FFT
function
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
919
5
4
427.53 378.78 357.14 307.59 MHz
5–30
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 4 of 6)
Note (1)
Resources Used
Performance
-3
-3
TriMatrix
ALUTs Memory
Blocks
-4
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
Larger
designs
8-bit, 1024-point,
single output, two
parallel FFT engines,
burst, three multiplier
and five adders FFT
function
1725
1594
2361
2165
3996
3604
10
10
10
10
14
14
6
430.29 401.92 373.13 319.08 MHz
422.65 407.33 373.13 329.10 MHz
315.45 342.81 325.73 284.25 MHz
373.13 369.54 317.96 256.14 MHz
378.50 367.10 332.33 288.68 MHz
391.38 361.14 340.25 280.89 MHz
8-bit, 1024-point,
single output, two
parallel FFT engines,
burst, four multipliers
and two adders FFT
function
8
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
burst,threemultipliers
and five adders FFT
function
9
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
12
18
24
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
burst,threemultipliers
and five adders FFT
function
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
burst, four multipliers
and two adders FFT
function
Altera Corporation
April 2011
5–31
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–36. Stratix II Performance Notes (Part 5 of 6)
Note (1)
Resources Used
Performance
-4
-3
-3
TriMatrix
ALUTs Memory
Blocks
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
Larger
designs
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
burst,threemultipliers
and five adders FFT
function
6850
6067
2730
2534
4358
3966
28
28
18
18
30
30
36
48
9
334.11 345.66 308.54 276.31 MHz
367.91 349.04 327.33 268.24 MHz
387.44 388.34 364.56 306.84 MHz
419.28 369.66 364.96 307.88 MHz
396.51 378.07 340.13 291.29 MHz
389.71 398.08 356.53 280.74 MHz
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
burst, four multipliers
two adders FFT
function
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
buffered burst, three
multipliersandadders
FFT function
8-bit, 1024-point,
12
18
24
quadrant output, one
parallel FFT engine,
buffered burst, four
multipliers and two
adders FFT function
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
buffered burst four
multipliers and two
adders FFT function
5–32
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April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 6 of 6)
Note (1)
Resources Used
Performance
-3
-3
TriMatrix
ALUTs Memory
Blocks
-4
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
Larger
designs
8-bit, 1024-point,
7385
60
60
36
359.58 352.98 312.01 278.00 MHz
quadrant output, four
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
8-bit, 1024-point,
6601
48
371.88 355.74 327.86 277.62 MHz
quadrant output, four
parallel FFT engines,
buffered burst, four
multipliers and two
adders FFT function
Notes for Table 5–36:
(1) These design performance numbers were obtained using the Quartus II software version 5.0 SP1.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) This application uses registered inputs and outputs.
(5) This application uses registered multiplier input and output stages within the DSP block.
(6) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
(7) This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
(8) This application uses the same clock source that is globally routed and connected to ports A and B.
(9) This application uses locally routed clocks or differently sourced clocks for ports A and B.
Altera Corporation
April 2011
5–33
Stratix II Device Handbook, Volume 1
Timing Model
Internal Timing Parameters
See Tables 5–37 through 5–42 for internal timing parameters.
Table 5–37. LE_FF Internal Timing Microparameters
-3 Speed
Grade (1)
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(3)
Min
(3)
Min
(4)
Min
(3)
Max
Max
Max
Max
tSU
LE register setup time before
clock
90
95
104
104
121
ps
ps
ps
ps
ps
ps
ps
ps
ps
tH
LE register hold time after clock 149
157
62
172
172
200
62
tCO
LE register clock-to-output
delay
62
94
99
59
62
109
127
tCLR
tPRE
tCLKL
tCLKH
tLUT
tADDER
Minimum clear pulse width
Minimum preset pulse width
Minimum clock low time
Minimum clock high time
204
204
612
612
162
354
214
214
642
642
162
354
234
234
273
273
820
820
162
354
234
234
703
703
703
703
378
619
397
650
162
170
435
712
507
829
354
372
Notes to Table 5–37:
(1) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(2) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(3) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(4) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
5–34
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April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–38. IOE Internal Timing Microparameters
-3 Speed
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Grade (1)
Symbol
Parameter
Unit
Min
Min
(3)
Min
Min
Max
Max
Max
Max
(3)
(4)
(3)
tSU
IOE input and output
register setup time
before clock
122
128
140
140
163
ps
ps
ps
tH
IOE input and output
register hold time after
clock
72
75
82
82
96
tCO
IOE input and output
register clock-to-
output delay
101
169
101
177
97
101
194
101
226
tPIN2COMBOUT_R Row input pin to IOE
combinational output
410
428
760
787
410
428
798
825
391
410
873
904
410 1,018 ps
428 1,054 ps
tPIN2COMBOUT_C Column input pin to
IOE combinational
408
428
output
tCOMBIN2PIN_R
Row IOE data input to 1,101 2,026 1,101 2,127 1,049 2,329 1,101 2,439 ps
combinational output
pin
1,101
tCOMBIN2PIN_C
Column IOE data
input to combinational
output pin
991 1,854 991 1,946 944 2,131 991 2,246 ps
991
tCLR
Minimum clear pulse
width
200
200
600
600
210
210
630
630
229
229
268
268
804
804
ps
ps
ps
ps
tPRE
Minimum preset pulse
width
229
229
tCLKL
tCLKH
Minimum clock low
time
690
690
Minimum clock high
time
690
690
Notes to Table 5–38:
(1) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(2) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(3) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(4) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Altera Corporation
April 2011
5–35
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–39. DSP Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (1)
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
Max
(3)
Min
Max
(3)
Min
(4)
Min
(3)
Max
Max
tSU
Input, pipeline, and
output register setup
time before clock
50
52
57
57
67
ps
ps
ps
tH
Input, pipeline, and
output register hold
time after clock
180
189
206
206
241
0
tCO
Input, pipeline, and
output register clock-
to-output delay
0
0
0
0
0
0
0
0
tINREG2PIPE9
tINREG2PIPE18
tINREG2PIPE36
Input register to DSP 1,312 2,030 1,312 2,030 1,250 2,334 1,312 2,720 ps
block pipeline register
in 9 × 9-bit mode
1,312
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
in 18 × 18-bit mode
1,302
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
in 36 × 36-bit mode
1,302
tPIPE2OUTREG2ADD DSP block pipeline
register to output
924 1,450 924 1,522 880 1,667 924 1,943 ps
924
register delay in two-
multipliers adder
mode
tPIPE2OUTREG4ADD DSP block pipeline
register to output
1,134 1,850 1,134 1,942 1,080 2,127 1,134 2,479 ps
1,134
register delay in four-
multipliers adder
mode
tPD9
Combinational input
to output delay for
9 × 9
2,100 2,880 2,100 3,024 2,000 3,312 2,100 3,859 ps
2,100
tPD18
tPD36
tCLR
Combinational input
to output delay for
18 × 18
2,110 2,990 2,110 3,139 2,010 3,438 2,110 4,006 ps
2,110
Combinational input
to output delay for
36 × 36
2,939 4,450 2,939 4,672 2,800 5,117 2,939 5,962 ps
2,939
Minimum clear pulse 2,212
width
2,322
2,543
2,543
2,964
ps
5–36
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–39. DSP Block Internal Timing Microparameters (Part 2 of 2)
-3 Speed
Grade (1)
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
Max
(3)
Min
Max
(3)
Min
(4)
Min
(3)
Max
Max
tCLKL
tCLKH
Minimum clock low
time
1,190
1,249
1,368
1,368
1,594
ps
ps
Minimum clock high
time
1,190
1,249
1,368
1,368
1,594
Notes to Table 5–39:
(1) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(2) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(3) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(4) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5–40. M512 Block Internal Timing Microparameters (Part 1 of 2)
Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM512RC
Synchronous read cycle 2,089 2,318 2,089 2.433 1,989 2,664 2,089 3,104 ps
time
2,089
tM512WERESU
tM512WEREH
tM512DATASU
tM512DATAH
Write or read enable
setup time before clock
22
203
22
23
213
23
25
25
29
272
29
ps
ps
ps
ps
ps
ps
ps
ps
Write or read enable
hold time after clock
233
233
Data setup time before
clock
25
25
Data hold time after
clock
203
22
213
23
233
233
272
29
tM512WADDRSU Write address setup
time before clock
25
25
tM512WADDRH Write address hold time
after clock
203
22
213
23
233
233
272
29
tM512RADDRSU Read address setup
time before clock
25
25
tM512RADDRH
Read address hold time
after clock
203
213
233
233
272
Altera Corporation
April 2011
5–37
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–40. M512 Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM512DATACO1 Clock-to-output delay
when using output
298
478
298
501
284
298
548
298
640
ps
registers
tM512DATACO2 Clock-to-output delay
without output registers
2,102 2,345 2,102 2,461 2,003 2,695 2,102 3,141 ps
2,102
tM512CLKL
tM512CLKH
tM512CLR
Minimum clock low time 1,315
1,380
1,380
151
1,512
1,512
1,762
1,762
192
ps
ps
ps
Minimum clock high time 1,315
1,512
1,512
Minimum clear pulse
width
144
165
165
Notes to Table 5–40:
(1) FMAX of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5–41. M4K Block Internal Timing Microparameters (Part 1 of 2) Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM4KRC
Synchronous read cycle 1,462 2,240 1,462 2,351 1,393 2,575 1,462 3,000 ps
time
1,462
tM4KWERESU
tM4KWEREH
tM4KBESU
tM4KBEH
Write or read enable
setup time before clock
22
203
22
23
213
23
25
25
29
272
29
ps
ps
ps
ps
Write or read enable
hold time after clock
233
233
Byte enable setup time
before clock
25
25
Byte enable hold time
after clock
203
213
233
233
272
5–38
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–41. M4K Block Internal Timing Microparameters (Part 2 of 2) Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tM4KDATAASU
tM4KDATAAH
A port data setup time
before clock
22
23
25
25
29
ps
ps
ps
ps
ps
ps
ps
ps
ps
A port data hold time
after clock
203
22
213
23
233
233
272
29
tM4KADDRASU A port address setup
time before clock
25
25
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
A port address hold time 203
after clock
213
23
233
233
272
29
B port data setup time
before clock
22
203
22
25
25
B port data hold time
after clock
213
23
233
233
272
29
tM4KRADDRBSU B port address setup
time before clock
25
25
tM4KRADDRBH B port address hold time 203
after clock
213
334
233
233
272
334
tM4KDATACO1
Clock-to-output delay
when using output
registers
334
524
549
319
334
601
701
tM4KDATACO2
(6)
Clock-to-output delay
without output registers
1,616 2,453 1,616 2,574 1,540 2,820 1,616 3,286 ps
1,616
tM4KCLKH
tM4KCLKL
tM4KCLR
Minimum clock high time 1,250
1,312
1,312
151
1,437
1,437
1,675
1,675
192
ps
ps
ps
Minimum clock low time 1,250
1,437
1,437
Minimum clear pulse
width
144
165
165
Notes to Table 5–41:
(1) FMAX of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
(6) Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes
that use locally routed or non-identical sources for the A and B port registers.
Altera Corporation
April 2011
5–39
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
Note (1)
-4 Speed
-3 Speed
-3 Speed
-5 Speed
Grade
Grade (2)
Grade (3)
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
Min
(4)
Max
Max
Max
Max
(5)
tMEGARC
Synchronous read cycle 1,866 2,774 1,866 2,911 1,777 3,189 1,777 3,716 ps
time
1,866
1,866
tMEGAWERESU Write or read enable
setup time before clock
144
39
151
40
165
165
192
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tMEGAWEREH
tMEGABESU
tMEGABEH
Write or read enable
hold time after clock
44
44
52
67
Byte enable setup time
before clock
50
52
57
57
Byte enable hold time
after clock
39
40
44
44
52
tMEGADATAASU A port data setup time
before clock
50
52
57
57
67
tMEGADATAAH
A port data hold time
after clock
243
589
255
618
253
52
279
279
325
789
322
67
tMEGAADDRASU A port address setup
time before clock
677
677
tMEGAADDRAH A port address hold time 241
after clock
277
277
tMEGADATABSU B port setup time before
clock
50
57
57
tMEGADATABH
B port hold time after
clock
243
589
255
618
253
480
279
279
325
789
322
480
tMEGAADDRBSU B port address setup
time before clock
677
677
tMEGAADDRBH B port address hold time 241
after clock
277
277
tMEGADATACO1 Clock-to-output delay
when using output
480
715
749
457
480
821
957
registers
tMEGADATACO2 Clock-to-output delay
without output registers
1,950 2,899 1,950 3,042 1,857 3,332 1,950 3,884 ps
1,950
tMEGACLKL
Minimum clock low time 1,250
1,312
1,437
1,437
1,675
ps
5–40
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Symbol
Parameter
Unit
Min
(4)
Min
(4)
Min
(5)
Min
(4)
Max
Max
Max
Max
tMEGACLKH
tMEGACLR
Minimum clock high
time
1,250
1,312
1,437
1,437
1,675
ps
ps
Minimum clear pulse
width
144
151
165
165
192
Notes to Table 5–42:
(1) FMAX of M-RAM Block obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Stratix II Clock Timing Parameters
See Tables 5–43 through 5–67 for Stratix II clock timing parameters.
Table 5–43. Stratix II Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL inclkpad to I/O input register
Delay from PLL inclkpad to I/O output register
tCOUT
tPLLCIN
tPLLCOUT
Altera Corporation
April 2011
5–41
Stratix II Device Handbook, Volume 1
Timing Model
EP2S15 Clock Timing Parameters
Tables 5–44 though 5–47 show the maximum clock timing parameters for
EP2S15 devices.
Table 5–44. EP2S15 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.445
Commercial
1.512
tCIN
2.487
2.245
0.336
0.094
2.848
2.570
0.373
0.095
3.309
2.985
0.424
0.1
ns
ns
ns
ns
tCOUT
1.288
1.347
tPLLCIN
tPLLCOUT
0.104
0.102
-0.053
-0.063
Table 5–45. EP2S15 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.419
Commercial
1.487
tCIN
2.456
2.214
0.326
0.084
2.813
3.273
ns
ns
ns
ns
tCOUT
1.262
1.322
2.535
0.363
0.085
2.949
0.414
0.09
tPLLCIN
tPLLCOUT
0.094
0.092
-0.063
-0.073
Table 5–46. EP2S15 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.232
Commercial
1.288
tCIN
2.144
2.140
-0.007
-0.011
2.454
2.450
-0.021
-0.025
2.848
2.843
-0.037
-0.042
ns
ns
ns
ns
tCOUT
1.237
1.293
tPLLCIN
tPLLCOUT
-0.109
-0.104
-0.122
-0.117
5–42
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–47. EP2S15 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.206
Commercial
1.262
tCIN
2.113
2.109
-0.023
-0.027
2.422
2.418
-0.038
-0.042
2.815
2.810
-0.056
-0.061
ns
ns
ns
ns
tCOUT
1.211
1.267
tPLLCIN
tPLLCOUT
-0.125
-0.12
-0.138
-0.133
EP2S30 Clock Timing Parameters
Tables 5–48 through 5–51 show the maximum clock timing parameters
for EP2S30 devices.
Table 5–48. EP2S30 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.553
Commercial
1.627
tCIN
2.639
2.397
0.225
-0.017
3.025
2.747
0.248
-0.03
3.509
3.185
0.28
ns
ns
ns
ns
tCOUT
1.396
1.462
tPLLCIN
tPLLCOUT
0.114
0.113
-0.043
-0.052
-0.044
Table 5–49. EP2S30 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.539
Commercial
1.613
tCIN
2.622
2.380
0.209
-0.033
3.008
2.730
0.229
-0.049
3.501
3.177
0.267
-0.057
ns
ns
ns
ns
tCOUT
1.382
1.448
tPLLCIN
tPLLCOUT
0.101
0.098
-0.056
-0.067
Altera Corporation
April 2011
5–43
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–50. EP2S30 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.304
Commercial
1.184
tCIN
1.966
1.962
2.251
2.247
2.616
2.611
ns
ns
ns
ns
tCOUT
1.309
1.189
tPLLCIN
tPLLCOUT
-0.135
-0.13
–0.158
–0.153
–0.208
–0.212
–0.254
–0.258
–0.302
–0.307
Table 5–51. EP2S30 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.289
Commercial
1.352
tCIN
2.238
2.234
-0.169
-0.173
2.567
2.563
-0.205
-0.209
2.990
2.985
-0.254
-0.259
ns
ns
ns
ns
tCOUT
1.294
1.357
tPLLCIN
tPLLCOUT
-0.14
-0.154
-0.135
-0.149
EP2S60 Clock Timing Parameters
Tables 5–52 through 5–55 show the maximum clock timing parameters
for EP2S60 devices.
Table 5–52. EP2S60 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.681
Commercial
1.762
tCIN
2.945
2.703
0.279
0.037
3.381
3.103
0.311
0.033
3.931
3.607
0.348
0.024
ns
ns
ns
ns
tCOUT
1.524
1.597
tPLLCIN
tPLLCOUT
0.066
0.064
-0.091
-0.101
5–44
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–53. EP2S60 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.658
Commercial
1.739
tCIN
2.920
2.678
0.278
0.036
3.350
3.072
0.304
0.026
3.899
3.575
0.355
0.031
ns
ns
ns
ns
tCOUT
1.501
1.574
tPLLCIN
tPLLCOUT
0.06
0.057
-0.097
-0.108
Table 5–54. EP2S60 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.463
Commercial
1.532
tCIN
2.591
2.587
-0.079
-0.083
2.972
2.968
-0.099
-0.103
3.453
3.448
-0.128
-0.133
ns
ns
ns
ns
tCOUT
1.468
1.537
tPLLCIN
tPLLCOUT
-0.153
-0.148
-0.167
-0.162
Table 5–55. EP2S60 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.439
Commercial
1.508
tCIN
2.562
2.558
-0.083
-0.087
2.940
2.936
-0.107
-0.111
3.421
3.416
-0.126
-0.131
ns
ns
ns
ns
tCOUT
1.444
1.513
tPLLCIN
tPLLCOUT
-0.161
-0.156
-0.174
-0.169
Altera Corporation
April 2011
5–45
Stratix II Device Handbook, Volume 1
Timing Model
EP2S90 Clock Timing Parameters
Tables 5–56 through 5–59 show the maximum clock timing parameters
for EP2S90 devices.
Table 5–56. EP2S90 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.768
Commercial
1.850
tCIN
3.033
2.791
0.125
-0.117
3.473
3.195
0.129
-0.149
4.040
3.716
0.144
-0.18
ns
ns
ns
ns
tCOUT
1.611
1.685
tPLLCIN
tPLLCOUT
-0.127
-0.284
-0.117
-0.282
Table 5–57. EP2S90 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.783
Commercial
1.868
tCIN
3.058
2.816
0.115
-0.127
3.502
3.224
0.119
-0.159
4.070
3.746
0.134
-0.19
ns
ns
ns
ns
tCOUT
1.626
1.703
tPLLCIN
tPLLCOUT
-0.137
-0.294
-0.127
-0.292
Table 5–58. EP2S90 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.566
Commercial
1.638
tCIN
2.731
2.727
-0.178
-0.182
3.124
3.120
-0.218
-0.222
3.632
3.627
-0.264
-0.269
ns
ns
ns
ns
tCOUT
1.571
1.643
tPLLCIN
tPLLCOUT
-0.326
-0.321
-0.326
-0.321
5–46
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–59. EP2S90 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.585
Commercial
1.658
tCIN
2.757
2.753
-0.193
-0.197
3.154
3.150
-0.235
-0.239
3.665
3.660
-0.278
-0.283
ns
ns
ns
ns
tCOUT
1.590
1.663
tPLLCIN
tPLLCOUT
-0.341
-0.336
-0.341
-0.336
EP2S130 Clock Timing Parameters
Tables 5–60 through 5–63 show the maximum clock timing parameters
for EP2S130 devices.
Table 5–60. EP2S130 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.889
Commercial
1.981
tCIN
3.405
3.151
0.226
-0.028
3.722
3.444
0.242
-0.036
4.326
4.002
0.277
-0.047
ns
ns
ns
ns
tCOUT
1.732
1.816
tPLLCIN
tPLLCOUT
0.105
0.106
-0.052
-0.059
Table 5–61. EP2S130 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.907
Commercial
1.998
tCIN
3.420
3.166
0.276
0.022
3.740
3.462
0.296
0.018
4.348
4.024
0.338
0.014
ns
ns
ns
ns
tCOUT
1.750
1.833
tPLLCIN
tPLLCOUT
0.134
0.136
-0.023
-0.029
Altera Corporation
April 2011
5–47
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–62. EP2S130 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.680
Commercial
1.760
tCIN
3.070
3.066
-0.12
3.351
3.347
-0.138
-0.142
3.892
3.887
-0.168
-0.173
ns
ns
ns
ns
tCOUT
1.685
1.765
tPLLCIN
tPLLCOUT
-0.113
-0.108
-0.124
-0.119
-0.124
Table 5–63. EP2S130 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.690
Commercial
1.770
tCIN
3.075
3.071
-0.075
-0.079
3.362
3.358
-0.089
-0.093
3.905
3.900
-0.11
ns
ns
ns
ns
tCOUT
1.695
1.775
tPLLCIN
tPLLCOUT
-0.087
-0.082
-0.097
-0.092
-0.115
EP2S180 Clock Timing Parameters
Tables 5–64 through 5–67 show the maximum clock timing parameters
for EP2S180 devices.
Table 5–64. EP2S180 Column Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
2.001
Commercial
2.095
tCIN
3.643
3.389
0.053
-0.201
3.984
3.706
0.046
-0.232
4.634
4.310
0.048
-0.276
ns
ns
ns
ns
tCOUT
1.844
1.930
tPLLCIN
tPLLCOUT
-0.307
-0.464
-0.297
-0.462
5–48
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–65. EP2S180 Column Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
2.003
Commercial
2.100
tCIN
3.652
3.398
0.053
-0.201
3.993
3.715
0.054
-0.224
4.648
4.324
0.058
-0.266
ns
ns
ns
ns
tCOUT
1.846
1.935
tPLLCIN
tPLLCOUT
-0.3
-0.29
-0.457
-0.455
Table 5–66. EP2S180 Row Pins Regional Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.759
Commercial
1.844
tCIN
3.273
3.269
-0.317
-0.321
3.577
3.573
-0.353
-0.357
4.162
4.157
-0.414
-0.419
ns
ns
ns
ns
tCOUT
1.764
1.849
tPLLCIN
tPLLCOUT
-0.542
-0.537
-0.541
-0.536
Table 5–67. EP2S180 Row Pins Global Clock Timing Parameters
Minimum Timing
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Grade
Industrial
1.763
Commercial
1.850
tCIN
3.285
3.281
-0.319
-0.323
3.588
3.584
-0.355
-0.359
4.176
4.171
-0.42
ns
ns
ns
ns
tCOUT
1.768
1.855
tPLLCIN
tPLLCOUT
-0.542
-0.537
-0.542
-0.537
-0.425
Altera Corporation
April 2011
5–49
Stratix II Device Handbook, Volume 1
Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified. Table 5–68 specifies the clock skew between any
two clock networks driving registers in the IOE.
Table 5–68. Clock Network Specifications
Name
Description
Min
Typ
Max
Unit
Clock skew adder
EP2S15, EP2S30,
EP2S60 (1)
Inter-clock network, same side
Inter-clock network, entire chip
50
ps
ps
100
Clock skew adder
EP2S90 (1)
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
55
110
63
ps
ps
ps
ps
ps
ps
Clock skew adder
EP2S130 (1)
125
75
Clock skew adder
EP2S180 (1)
150
Note to Table 5–68:
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
5–50
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
IOE Programmable Delay
See Tables 5–69 and 5–70 for IOE programmable delay.
Table 5–69. Stratix II IOE Programmable Delay on Column Pins
Note (1)
Minimum
Timing (2)
-3 Speed
-4 Speed
Grade
-5 Speed
Grade
Grade (3)
Min Max
Available
Settings
Parameter
Paths Affected
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
Input delay from Pad to I/O
8
64
2
0
0
1,696
1,781
0
0
2,881
3,025
0
3,313
0
3,860
pin to internal
cells
dataout to logic
array
Input delay from Pad toI/O input
0
0
1,955
2,053
0
0
3,275
3,439
0
0
0
3,766
575
0
0
0
4,388
670
pin to input
register
register
Delay from
I/O output
0
0
316
332
0
0
500
525
output register
to output pin
register to pad
Output enable
pin delay
tXZ, tZX
2
0
0
305
320
0
0
483
507
556
647
Notes to Table 5–69:
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
(2) The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
(3) The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Altera Corporation
April 2011
5–51
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–70. Stratix II IOE Programmable Delay on Row Pins
Note (1)
Minimum
Timing (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Available
Settings
Parameter
Paths Affected
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
Input delay from Pad to I/O
8
64
2
0
0
1,697
1,782
0
0
2,876
3,020
0
3,308
0
3,853
pin to internal
cells
dataout to logic
array
Input delay from Pad to I/O input
0
0
1,956
2,054
0
0
3,270
3,434
0
0
0
3,761
575
0
0
0
4,381
670
pin to input
register
register
Delay from
I/O output
0
0
316
332
0
0
525
525
output register
to output pin
register to pad
Output enable
pin delay
tXZ, tZX
2
0
0
305
320
0
0
507
507
556
647
Notes to Table 5–70:
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
(2) The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
(3) The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Default Capacitive Loading of Different I/O Standards
See Table 5–71 for default capacitive loading of different I/O standards.
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 1
of 2)
I/O Standard
CapacitiveLoad Unit
LVTTL
LVCMOS
2.5 V
0
0
pF
pF
pF
pF
pF
pF
pF
pF
0
1.8 V
0
1.5 V
0
PCI
10
10
0
PCI-X
SSTL-2 Class I
5–52
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 2
of 2)
I/O Standard
CapacitiveLoad Unit
SSTL-2 Class II
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
HyperTransport
LVPECL
Altera Corporation
April 2011
5–53
Stratix II Device Handbook, Volume 1
Timing Model
I/O Delays
See Tables 5–72 through 5–76 for I/O delays.
Table 5–72. I/O Delay Parameters
Symbol
Parameter
tDIP
Delay from I/O datain to output pad
tOP
Delay from I/O output register to output pad
Delay from input pad to I/O dataout to core
Delay from input pad to I/O input register
tPCOUT
tPI
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 1 of 3)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
(3)
Unit
Grade
Grade
Industrial Commercial
(2)
LVTTL
tPI
674
408
684
418
747
481
749
483
674
408
507
241
507
241
543
277
543
277
560
294
707
428
717
438
783
504
786
507
707
428
530
251
530
251
569
290
569
290
587
308
1223
787
1282
825
1405
904
1637
1054
1619
1036
1829
1246
1922
1339
1637
1054
1094
511
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
2.5 V
1210
774
1269
812
1390
889
1.8 V
1366
930
1433
976
1570
1069
1650
1149
1405
904
1.5 V
1436
1000
1223
787
1506
1049
1282
825
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
818
857
939
382
400
438
818
857
939
1094
511
tPCOUT
382
400
438
SSTL-18 Class I tPI
tPCOUT
SSTL-18 Class II tPI
tPCOUT
tPI
tPCOUT
898
941
1031
530
1201
618
462
484
898
941
1031
530
1201
618
462
484
1.5-V HSTL
Class I
993
1041
584
1141
640
1329
746
557
5–54
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 2 of 3)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
Unit
Grade
Grade
Industrial Commercial
(2)
(3)
1041
584
941
484
941
484
1273
816
1273
816
857
400
1.5-V HSTL
Class II
tPI
560
294
543
277
543
277
679
413
679
413
507
241
587
308
569
290
569
290
712
433
712
433
530
251
993
557
898
462
898
462
1214
778
1214
778
818
382
1141
640
1329
746
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
1.8-V HSTL
Class I
1031
530
1201
618
1.8-V HSTL
Class II
1031
530
1201
618
PCI
1395
894
1625
1042
1625
1042
1094
511
PCI-X
1395
894
Differential
SSTL-2 Class I
(1)
939
tPCOUT
438
Differential
SSTL-2 Class II
(1)
tPI
507
241
530
251
818
382
857
400
939
438
1094
511
ps
ps
tPCOUT
Differential
SSTL-18 Class I
(1)
tPI
543
277
569
290
898
462
941
484
1031
530
1201
618
ps
ps
tPCOUT
Differential
SSTL-18 Class II
(1)
tPI
543
277
569
290
898
462
941
484
1031
530
1201
618
ps
ps
tPCOUT
1.8-V Differential tPI
543
277
543
277
560
294
560
294
569
290
569
290
587
308
587
308
898
462
898
462
993
557
993
557
941
484
1031
530
1201
618
ps
ps
ps
ps
ps
ps
ps
ps
HSTL Class I (1)
tPCOUT
1.8-V Differential tPI
941
1031
530
1201
618
HSTL Class II (1)
tPCOUT
484
1.5-V Differential tPI
1041
584
1141
640
1329
746
HSTL Class I (1)
tPCOUT
1.5-V Differential tPI
1041
584
1141
640
1329
746
HSTL Class II (1)
tPCOUT
Altera Corporation
April 2011
5–55
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 3 of 3)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
(3)
Unit
Grade
Grade
Industrial Commercial
(2)
1.2-V HSTL
tPI
645
379
677
398
1194
758
1252
795
-
-
-
-
ps
ps
tPCOUT
Notes for Table 5–73:
(1) These I/O standards are only supported on DQS pins.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–74. Stratix II I/O Input Delay for Row Pins (Part 1 of 2)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
(2)
Unit
Grade
Grade
Industrial Commercial
(1)
LVTTL
tPI
715
391
726
402
788
464
792
468
715
391
547
223
547
223
577
253
577
253
602
278
749
410
761
422
827
488
830
491
749
410
573
234
573
234
605
266
605
266
631
292
1287
760
1350
798
1477
873
1723
1018
1704
999
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
2.5 V
1273
746
1335
783
1461
857
1.8 V
1427
900
1497
945
1639
1035
1720
1116
1477
873
1911
1206
2006
1301
1723
1018
1176
471
1.5 V
1498
971
1571
1019
1350
798
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
1287
760
879
921
1008
404
352
369
879
921
1008
404
1176
471
tPCOUT
352
369
SSTL-18 Class I tPI
tPCOUT
SSTL-18 Class II tPI
tPCOUT
tPI
tPCOUT
960
1006
454
1101
497
1285
580
433
960
1006
454
1101
497
1285
580
433
1.5-V HSTL
Class I
1056
529
1107
555
1212
608
1413
708
5–56
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–74. Stratix II I/O Input Delay for Row Pins (Part 2 of 2)
Minimum Timing
-3Speed -3Speed
-4Speed -5Speed
I/O Standard
Parameter
Grade
Grade
Unit
Grade
Grade
Industrial Commercial
(1)
(2)
1107
555
1006
454
1006
454
994
442
994
442
1.5-V HSTL
Class II
tPI
602
278
577
253
577
253
515
191
515
191
631
292
605
266
605
266
540
201
540
201
1056
529
960
433
960
433
948
421
948
421
1212
608
1413
708
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
tPCOUT
tPI
1.8-V HSTL
Class I
1101
497
1285
580
1.8-V HSTL
Class II
1101
497
1285
580
LVDS
1088
484
1269
564
HyperTransport
1088
484
1269
564
tPCOUT
Notes for Table 5–74:
(1) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(2) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 1 of 8)
Minimum Timing
-3
-3
-4
-5
Drive
Strength
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Industrial Commercial
(4)
LVTTL
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1178
1198
1041
1061
976
1236
1258
1091
1113
1024
1046
998
2351
2417
2036
2102
2036
2102
1893
1959
1787
1853
1788
1854
2467
2537
2136
2206
2136
2206
1986
2056
1875
1945
1876
1946
2702
2778
2340
2416
2340
2416
2176
2252
2054
2130
2055
2131
2820
2910
2448
2538
2448
2538
2279
2369
2154
2244
2156
2246
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
16 mA
20 mA
996
951
971
1020
976
931
951
998
24 mA
(1)
924
969
944
991
Altera Corporation
April 2011
5–57
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 2 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
LVCMOS
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1041
1061
952
972
926
946
933
953
921
941
909
929
1004
1024
955
975
934
954
918
938
1091
1113
999
2036
2102
1786
1852
1720
1786
1693
1759
1677
1743
1659
1725
2063
2129
1841
1907
1742
1808
1679
1745
2136
2206
1874
1944
1805
1875
1776
1846
1759
1829
1741
1811
2165
2235
1932
2002
1828
1898
1762
1832
2340
2416
2053
2129
1977
2053
1946
2022
1927
2003
1906
1982
2371
2447
2116
2192
2002
2078
1929
2005
2448
2538
2153
2243
2075
2165
2043
2133
2025
2115
2003
2093
2480
2570
2218
2308
2101
2191
2027
2117
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
1021
971
12 mA
16 mA
20 mA
993
978
1000
965
987
24 mA
(1)
954
976
2.5 V
4 mA
8 mA
12 mA
1053
1075
1001
1023
980
1002
962
16 mA
(1)
984
5–58
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 3 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
1.8 V
2 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1042
1062
1047
1067
974
994
976
996
933
953
934
954
1023
1043
963
983
966
986
926
946
913
933
896
916
876
896
877
897
872
892
1093
1115
1098
1120
1022
1044
1024
1046
978
2904
2970
2248
2314
2024
2090
1947
2013
1882
1948
1833
1899
2505
2571
2023
2089
1923
1989
1878
1944
1715
1781
1672
1738
1609
1675
1598
1664
1596
1662
3048
3118
2359
2429
2124
2194
2043
2113
1975
2045
1923
1993
2629
2699
2123
2193
2018
2088
1970
2040
1799
1869
1754
1824
1688
1758
1676
1746
1674
1744
3338
3414
2584
2660
2326
2402
2238
2314
2163
2239
2107
2183
2879
2955
2325
2401
2210
2286
2158
2234
1971
2047
1921
1997
1849
1925
1836
1912
1834
1910
3472
3562
2698
2788
2434
2524
2343
2433
2266
2356
2209
2299
3002
3092
2433
2523
2315
2405
2262
2352
2041
2131
1991
2081
1918
2008
1905
1995
1903
1993
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
6 mA
8 mA
10 mA
1000
979
12 mA
(1)
1001
1073
1095
1009
1031
1012
1034
971
1.5 V
2 mA
4 mA
6 mA
8 mA (1) tOP
tDIP
993
SSTL-2 Class I 8 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
957
979
12 mA
(1)
940
962
SSTL-2 Class II 16 mA
918
940
20 mA
919
941
24 mA
(1)
915
937
Altera Corporation
April 2011
5–59
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 4 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
SSTL-18
Class I
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
909
929
914
934
894
914
898
918
891
911
883
903
894
914
890
910
890
910
912
932
917
937
896
916
900
920
892
912
953
975
958
980
937
959
942
964
936
958
925
947
937
959
933
955
933
955
956
978
962
984
940
962
944
966
936
958
1690
1756
1656
1722
1640
1706
1638
1704
1626
1692
1597
1663
1578
1644
1585
1651
1583
1649
1608
1674
1595
1661
1586
1652
1591
1657
1585
1651
1773
1843
1737
1807
1721
1791
1718
1788
1706
1776
1675
1745
1655
1725
1663
1733
1661
1731
1687
1757
1673
1743
1664
1734
1669
1739
1663
1733
1942
2018
1903
1979
1885
1961
1882
1958
1869
1945
1835
1911
1813
1889
1821
1897
1819
1895
1848
1924
1833
1909
1823
1899
1828
1904
1821
1897
2012
2102
1973
2063
1954
2044
1952
2042
1938
2028
1904
1994
1882
1972
1890
1980
1888
1978
1943
2033
1928
2018
1917
2007
1923
2013
1916
2006
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
6 mA
8 mA
10 mA
12 mA
(1)
SSTL-18
Class II
8 mA
16 mA
18 mA
20 mA
(1)
1.8-V HSTL
Class I
4 mA
6 mA
8 mA
10 mA
12 mA
(1)
5–60
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 5 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
1.8-V HSTL
Class II
16 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
877
897
879
899
879
899
912
932
917
937
899
919
900
920
893
913
881
901
884
904
886
906
958
978
1028
1048
1028
1048
919
941
921
943
921
943
956
978
961
983
943
965
943
965
937
959
924
946
927
949
929
951
1004
1026
1082
1104
1082
1104
1385
1451
1394
1460
1402
1468
1607
1673
1588
1654
1590
1656
1592
1658
1590
1656
1431
1497
1439
1505
1450
1516
1602
1668
1956
2022
1956
2022
1453
1523
1462
1532
1471
1541
1686
1756
1666
1736
1668
1738
1670
1740
1668
1738
1501
1571
1510
1580
1521
1591
1681
1751
2051
2121
2051
2121
1591
1667
1602
1678
1611
1687
1847
1923
1825
1901
1827
1903
1829
1905
1827
1903
1644
1720
1654
1730
1666
1742
-
1680
1770
1691
1781
1700
1790
1942
2032
1920
2010
1922
2012
1924
2014
1922
2012
1734
1824
1744
1834
1757
1847
-
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
18 mA
20 mA
(1)
1.5-V HSTL
Class I
4 mA
6 mA
8 mA
10 mA
12 mA
(1)
1.5-V HSTL
Class II
16 mA
18 mA
20 mA
(1)
1.2-V HSTL
PCI
-
-
2244
2320
2244
2320
2070
2160
2070
2160
PCI-X
Altera Corporation
April 2011
5–61
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 6 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
Differential
SSTL-2 Class I
8 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
913
933
896
916
876
896
877
897
872
892
909
929
914
934
894
914
898
918
891
911
883
903
894
914
890
910
890
910
957
979
940
962
918
940
919
941
915
937
953
975
958
980
937
959
942
964
936
958
925
947
937
959
933
955
933
955
1715
1781
1672
1738
1609
1675
1598
1664
1596
1662
1690
1756
1656
1722
1640
1706
1638
1704
1626
1692
1597
1663
1578
1644
1585
1651
1583
1649
1799
1869
1754
1824
1688
1758
1676
1746
1674
1744
1773
1843
1737
1807
1721
1791
1718
1788
1706
1776
1675
1745
1655
1725
1663
1733
1661
1731
1971
2047
1921
1997
1849
1925
1836
1912
1834
1910
1942
2018
1903
1979
1885
1961
1882
1958
1869
1945
1835
1911
1813
1889
1821
1897
1819
1895
2041
2131
1991
2081
1918
2008
1905
1995
1903
1993
2012
2102
1973
2063
1954
2044
1952
2042
1938
2028
1904
1994
1882
1972
1890
1980
1888
1978
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
12 mA
16 mA
20 mA
24 mA
4 mA
Differential
SSTL-2 Class II
Differential
SSTL-18
Class I
6 mA
8 mA
10 mA
12 mA
8 mA
Differential
SSTL-18
Class II
16 mA
18 mA
20 mA
5–62
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 7 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
1.8-V
Differential
HSTL Class I
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
912
932
917
937
896
916
900
920
892
912
877
897
879
899
879
899
912
932
917
937
899
919
900
920
893
913
956
978
962
984
940
962
944
966
936
958
919
941
921
943
921
943
956
978
961
983
943
965
943
965
937
959
1608
1674
1595
1661
1586
1652
1591
1657
1585
1651
1385
1451
1394
1460
1402
1468
1607
1673
1588
1654
1590
1656
1592
1658
1590
1656
1687
1757
1673
1743
1664
1734
1669
1739
1663
1733
1453
1523
1462
1532
1471
1541
1686
1756
1666
1736
1668
1738
1670
1740
1668
1738
1848
1924
1833
1909
1823
1899
1828
1904
1821
1897
1591
1667
1602
1678
1611
1687
1847
1923
1825
1901
1827
1903
1829
1905
1827
1903
1943
2033
1928
2018
1917
2007
1923
2013
1916
2006
1680
1770
1691
1781
1700
1790
1942
2032
1920
2010
1922
2012
1924
2014
1922
2012
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
1.8-V
Differential
HSTL Class II
1.5-V
Differential
HSTL Class I
6 mA
8 mA
10 mA
12 mA
Altera Corporation
April 2011
5–63
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
1.5-V
Differential
HSTL Class II
16 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
881
924
946
927
949
929
951
1431
1497
1439
1505
1450
1516
1501
1571
1510
1580
1521
1591
1644
1720
1654
1730
1666
1742
1734
1824
1744
1834
1757
1847
ps
ps
901
884
904
886
906
18 mA
20 mA
Notes to Table 5–75:
(1) This is the default setting in the Quartus II software.
(2) These I/O standards are only supported on DQS pins.
(3) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(4) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3)
Minimum Timing
-3
-3
-4
-5
Drive
Strength
Speed Speed
Grade Grade
(2)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Industrial Commercial
(3)
LVTTL
4 mA
8 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1267
1225
1144
1102
1091
1049
1144
1102
1044
1002
1328
1285
1200
1157
1144
1101
1200
1157
1094
1051
2655
2600
2113
2058
2081
2026
2113
2058
1853
1798
2786
2729
2217
2160
2184
2127
2217
2160
1944
1887
3052
2989
2429
2366
2392
2329
2429
2366
2130
2067
3189
3116
2549
2476
2512
2439
2549
2476
2243
2170
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
12 mA
(1)
LVCMOS
4 mA
8 mA (1) tOP
tDIP
5–64
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 2 of 3)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(2)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(3)
2.5 V
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1128
1086
1030
988
1183
1140
1080
1037
1061
1018
1253
1210
1242
1199
1131
1088
1100
1057
1213
1170
1106
1063
1050
1007
992
2091
2036
1872
1817
1775
1720
2954
2899
2294
2239
2039
1984
1942
1887
2530
2475
2020
1965
1759
1704
1581
1526
1709
1654
1648
1593
1633
1578
1615
1560
2194
2137
1964
1907
1862
1805
3100
3043
2407
2350
2140
2083
2038
1981
2655
2598
2120
2063
1846
1789
1659
1602
1793
1736
1729
1672
1713
1656
1694
1637
2403
2340
2152
2089
2040
1977
3396
3333
2637
2574
2344
2281
2232
2169
2908
2845
2322
2259
2022
1959
1817
1754
1964
1901
1894
1831
1877
1814
1856
1793
2523
2450
2265
2192
2151
2078
3542
3469
2763
2690
2462
2389
2348
2275
3041
2968
2440
2367
2104
2031
1897
1824
2046
1973
1975
1902
1958
1885
1937
1864
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
(1)
1012
970
1.8 V
2 mA
4 mA
6 mA
1196
1154
1184
1142
1079
1037
1049
1007
1158
1116
1055
1013
1002
960
8 mA (1) tOP
tDIP
1.5 V
2 mA
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
SSTL-2 Class I 8 mA
SSTL-2 Class II 16 mA
947
(1)
905
949
SSTL-18
Class I
4 mA
6 mA
8 mA
990
1038
995
948
994
1042
999
952
970
1018
975
928
10 mA
(1)
974
1021
978
932
Altera Corporation
April 2011
5–65
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(2)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(3)
1.8-V HSTL
Class I
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
972
930
975
933
958
916
962
920
953
911
970
928
974
932
960
918
1018
976
1005
963
1019
976
1610
1555
1580
1525
1576
1521
1567
1512
1566
1511
1591
1536
1579
1524
1572
1517
1723
1668
1723
1668
1689
1632
1658
1601
1653
1596
1644
1587
1643
1586
1669
1612
1657
1600
1649
1592
1808
1751
1808
1751
1850
1787
1816
1753
1811
1748
1801
1738
1800
1737
1828
1765
1815
1752
1807
1744
1980
1917
1980
1917
1956
1883
1920
1847
1916
1843
1905
1832
1904
1831
1933
1860
1919
1846
1911
1838
2089
2016
2089
2016
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
6 mA
8 mA
10 mA
1022
979
1004
961
1008
965
12 mA
(1)
999
956
1.5-V HSTL
Class I
4 mA
6 mA
1018
975
1021
978
8 mA (1) tOP
1006
963
tDIP
tOP
tDIP
tOP
LVDS
1067
1024
1053
1010
HyperTransport
tDIP
Notes to Table 5–76:
(1) This is the default setting in the Quartus II software.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
5–66
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–77 specifies the maximum input clock toggle rates. Table 5–78
specifies the maximum output clock toggle rates at 0pF load. Table 5–79
specifies the derating factors for the output clock toggle rate for a non 0pF
load.
To calculate the output toggle rate for a non 0pF load, use this formula:
The toggle rate for a non 0pF load
= 1000 / (1000/ toggle rate at 0pF load + derating factor * load value
in pF /1000)
For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA
I/O standard is 550 MHz on a -3 device clock output pin. The derating
factor is 94ps/pF. For a 10pF load the toggle rate is calculated as:
1000 / (1000/550 + 94 × 10 /1000) = 363 (MHz)
Tables 5–77 through 5–79 show the I/O toggle rates for Stratix II
devices.
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Column I/O Pins (MHz) Row I/O Pins (MHz)
Dedicated Clock Inputs
(MHz)
Input I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
LVTTL
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
450
450
450
450
450
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
450
450
450
450
450
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
400
400
400
400
400
500
500
500
500
500
500
500
2.5-V LVTTL/CMOS
1.8-V LVTTL/CMOS
1.5-V LVTTL/CMOS
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
Altera Corporation
April 2011
5–67
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
Dedicated Clock Inputs
(MHz)
Column I/O Pins (MHz)
Row I/O Pins (MHz)
Input I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.8-V HSTL Class II
PCI (1)
500
500
500
280
500
500
500
500
-
500
450
450
-
500
500
500
500
500
500
280
500
500
500
500
-
500
400
400
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI-X (1)
1.2-V HSTL (2)
Differential SSTL-2 Class I
500
500
500
500
(1), (3)
Differential SSTL-2 Class II
(1), (3)
500
500
500
500
500
500
500
-
500
500
500
500
500
500
500
-
500
500
500
500
500
500
500
-
-
-
-
500
500
500
500
500
500
500
717
500
500
500
500
500
500
500
717
500
500
500
500
500
500
500
640
Differential SSTL-18 Class I
(1), (3)
-
-
-
Differential SSTL-18 Class II
(1), (3)
-
-
-
1.8-V Differential HSTL
Class I (1), (3)
-
-
-
1.8-V Differential HSTL
Class II (1), (3)
-
-
-
1.5-V Differential HSTL
Class I (1), (3)
-
-
-
-
-
-
1.5-V Differential HSTL
Class II (1), (3)
HyperTransport technology
520
520
420
(4)
LVPECL (1)
LVDS (5)
-
-
-
-
-
-
-
-
-
-
520
-
-
520
-
-
420
-
450
717
450
450
717
450
400
640
400
LVDS (6)
Notes to Table 5–77:
(1) Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
(2) 1.2-V HSTL is only supported on column I/O pins.
(3) Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
(6) These numbers apply to dedicated clock pins in the top and bottom I/O banks.
5–68
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 1 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
3.3-V LVTTL
4 mA
8 mA
270
435
580
720
875
1,030
290
565
790
1,020
1,066
1,100
230
430
630
930
120
285
450
660
905
1,131
244
470
550
625
400
400
350
400
400
225
355
475
594
700
794
250
480
710
925
985
1,040
194
380
575
845
109
250
390
570
805
1,040
200
370
430
495
300
400
350
350
400
210
325
420
520
610
670
230
440
670
875
935
1,000
180
380
550
820
104
230
360
520
755
990
180
325
375
420
300
350
300
350
350
270
225
210
270
435
580
720
875
225
355
475
594
700
210
325
420
520
610
670
230
440
670
875
935
435
355
325
12 mA
16 mA
20 mA
24 mA
4 mA
580
475
420
-
-
-
-
-
-
-
290
565
-
-
250
480
-
-
230
440
-
1,030 794
3.3-V LVCMOS
290
565
790
250
480
710
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
-
-
-
1,020 925
1,066 985
-
-
-
-
-
-
1,100 1,040 1,000
2.5-V
LVTTL/LVCMOS
230
430
630
-
194
380
575
-
180
380
550
-
230
430
630
930
120
285
450
660
905
194
380
575
845
109
250
390
570
805
180
380
550
820
104
230
360
520
755
8 mA
12 mA
16 mA
2 mA
1.8-V
LVTTL/LVCMOS
120
285
450
660
-
109
250
390
570
-
104
230
360
520
-
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
-
-
-
1,131 1,040 990
1.5-V
LVTTL/LVCMOS
244
470
-
200
370
-
180
325
-
244
470
550
625
400
400
350
400
400
200
370
430
495
300
400
350
350
400
180
325
375
420
300
350
300
350
350
4 mA
6 mA
8 mA
-
-
-
SSTL-2 Class I
SSTL-2 Class II
8 mA
-
-
-
12 mA
16 mA
20 mA
24 mA
400
350
-
350
350
-
350
300
-
-
-
-
Altera Corporation
April 2011
5–69
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 2 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
SSTL-18 Class I
4 mA
6 mA
200
350
450
500
700
200
400
450
550
300
500
650
700
700
500
550
650
350
500
700
700
700
600
650
700
400
400
350
400
400
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
300
400
350
350
400
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
300
350
300
350
350
200
350
450
500
-
150
250
300
400
-
150
200
300
400
-
200
350
450
500
650
200
400
450
550
300
500
650
700
700
500
550
550
350
500
700
700
700
600
650
700
400
400
350
400
400
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
300
400
350
350
400
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
300
350
300
350
350
8 mA
10 mA
12 mA
8 mA
SSTL-18 Class II
-
-
-
16 mA
18 mA
20 mA
4 mA
-
-
-
-
-
-
-
-
-
1.8-V HSTL
Class I
300
500
650
700
700
-
300
450
600
650
700
-
300
450
600
600
650
-
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
1.8-V HSTL
Class II
-
-
-
-
-
-
1.5-V HSTL
Class I
350
500
700
-
300
500
650
-
300
450
600
-
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
8 mA
-
-
-
1.5-V HSTL
Class II
-
-
-
-
-
-
-
-
-
Differential
SSTL-2 Class I (3)
400
400
350
350
-
300
400
350
350
-
300
350
300
297
-
12 mA
16 mA
20 mA
24 mA
Differential
SSTL-2 Class II
(3)
5–70
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 3 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
Differential
SSTL-18 Class I
(3)
4 mA
6 mA
200
350
450
500
700
200
400
450
550
300
500
650
700
700
500
550
650
350
500
700
700
700
600
650
700
1,000
1,000
-
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
790
790
-
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
670
670
-
200
150
150
200
350
450
500
650
200
400
450
550
300
500
650
700
700
500
550
550
350
500
700
700
700
600
650
700
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
670
670
300
-
350
250
200
8 mA
450
300
300
10 mA
12 mA
8 mA
500
400
400
350
350
297
Differential
SSTL-18 Class II
(3)
-
-
-
16 mA
18 mA
20 mA
4 mA
-
-
-
-
-
-
-
-
-
1.8-V Differential
HSTL Class I (3)
-
-
-
6 mA
-
-
-
8 mA
-
-
-
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
-
-
-
-
-
-
1.8-V Differential
HSTL Class II (3)
-
-
-
-
-
-
-
-
-
1.5-V Differential
HSTL Class I (3)
-
-
-
6 mA
-
-
-
8 mA
-
-
-
10 mA
12 mA
16 mA
18 mA
20 mA
-
-
-
-
-
-
1.5-V Differential
HSTL Class II (3)
-
-
-
-
-
-
-
-
-
-
-
-
3.3-V PCI
3.3-V PCI-X
LVDS (6)
1,000 790
1,000 790
-
-
-
500
500
500
500
500
500
450
-
400
-
HyperTransport
technology (4), (6)
LVPECL (5)
3.3-V LVTTL
2.5-V LVTTL
-
-
-
-
-
-
450
400
350
400
400
350
300
350
300
OCT 50 Ω
OCT 50 Ω
400
350
400
350
350
300
400
350
400
350
350
300
Altera Corporation
April 2011
5–71
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.8-V LVTTL
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
700
350
550
600
600
560
550
280
600
550
350
450
500
550
400
500
-
450
300
400
500
500
350
450
-
700
350
550
600
600
590
-
550
350
450
500
550
400
-
450
300
400
500
500
350
-
700
350
550
600
600
450
550
280
600
550
350
450
500
550
400
500
-
450
300
400
500
500
350
450
-
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II OCT 25 Ω
1.2-V HSTL (2)
OCT 50 Ω
OCT 50 Ω
-
-
-
1.5-V HSTL
Class I
550
500
600
550
500
550
500
1.8-V HSTL
Class I
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
650
500
600
600
560
550
650
500
600
600
500
500
550
400
500
600
500
550
600
450
500
500
350
450
600
450
500
650
-
600
-
600
-
650
500
600
600
560
550
650
500
600
600
500
500
550
400
500
600
500
550
600
450
500
500
350
450
600
450
500
1.8-V HSTL
Class II
Differential
SSTL-2 Class I
600
600
590
-
500
550
400
-
500
500
350
-
Differential
SSTL-2 Class II
Differential
SSTL-18 Class I
Differential
SSTL-18 Class II
1.8-V Differential OCT 50 Ω
HSTL Class I
650
-
600
-
600
-
1.8-V Differential OCT 25 Ω
HSTL Class II
1.5-V Differential OCT 50 Ω
600
550
500
HSTL Class I
5–72
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.2-V Differential OCT 50 Ω
280
-
-
-
-
-
280
-
-
HSTL
Notes to Table 5–78:
(1) The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5pF.
(2) 1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8.
(3) Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) LVPECL is only supported on column clock pins.
(6) Refer to Tables 5–81 through 5–91 if using SERDES block. Use the toggle rate values from the clock output column
for PLL output.
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
3.3-V LVTTL
4 mA
8 mA
478
260
213
136
138
134
377
206
141
108
83
510
333
247
197
187
177
391
212
145
111
88
510
333
247
197
187
177
391
212
145
111
88
478
510
510
466
291
211
166
154
143
377
178
115
86
510
333
247
197
187
177
391
212
145
111
88
510
333
247
197
187
177
391
212
145
111
88
260
333
333
12 mA
16 mA
20 mA
24 mA
4 mA
213
247
247
-
-
-
-
-
-
-
377
206
-
-
391
212
-
-
391
212
-
3.3-V LVCMOS
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
-
-
-
-
-
-
79
65
72
72
-
-
-
74
72
72
2.5-V
LVTTL/LVCMOS
387
163
142
120
427
224
203
182
427
224
203
182
387
163
142
-
427
224
203
-
427
224
203
-
391
170
152
134
427
224
203
182
427
224
203
182
8 mA
12 mA
16 mA
Altera Corporation
April 2011
5–73
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 2 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
1.8-V
LVTTL/LVCMOS
2 mA
4 mA
951
405
261
223
194
174
652
333
182
135
364
163
118
99
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
951
405
261
223
-
1421
516
325
274
-
1421
516
325
274
-
904
393
253
224
199
180
618
270
198
155
350
188
94
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
1421
516
325
274
236
209
963
347
247
194
680
207
147
122
116
570
380
282
220
175
206
160
130
127
680
207
147
122
116
6 mA
8 mA
10 mA
12 mA
2 mA
-
-
-
1.5-V
LVTTL/LVCMOS
652
333
-
963
347
-
963
347
-
4 mA
6 mA
8 mA
-
-
-
SSTL-2 Class I
SSTL-2 Class II
8 mA
364
163
118
-
680
207
147
-
680
207
147
-
12 mA
16 mA
20 mA
24 mA
4 mA
87
91
-
-
-
85
SSTL-18 Class I
SSTL-18 Class II
458
305
225
167
129
173
150
120
109
364
163
118
99
458
305
225
167
-
570
380
282
220
-
570
380
282
220
-
505
336
248
190
148
155
140
110
94
6 mA
8 mA
10 mA
12 mA
8 mA
-
-
-
16 mA
18 mA
20 mA
8 mA
-
-
-
-
-
-
-
-
-
SSTL-2 Class I
SSTL-2 Class II
364
163
118
-
680
207
147
-
680
207
147
-
350
188
94
12 mA
16 mA
20 mA
24 mA
87
91
-
-
-
85
5–74
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
SSTL-18 Class I
4 mA
6 mA
458
305
225
167
129
173
150
120
109
245
164
123
110
97
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
458
570
570
505
336
248
190
148
155
140
110
94
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
305
380
380
8 mA
225
282
282
10 mA
12 mA
8 mA
167
220
220
-
-
-
SSTL-18 Class II
-
-
-
16 mA
18 mA
20 mA
4 mA
-
-
-
-
-
-
-
-
-
1.8-V HSTL
Class I
245
282
282
229
153
114
108
104
99
6 mA
164
188
188
8 mA
123
140
140
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
110
124
124
97
110
110
1.8-V HSTL
Class II
101
98
-
-
-
-
-
-
93
93
-
-
-
88
1.5-V HSTL
Class I
168
112
84
196
131
99
196
131
99
168
196
196
188
125
95
196
131
99
196
131
99
6 mA
112
131
131
8 mA
84
-
99
-
99
-
10 mA
12 mA
16 mA
18 mA
20 mA
8 mA
87
98
98
90
98
98
86
98
98
-
-
-
87
98
98
1.5-V HSTL
Class II
95
101
100
101
680
207
147
122
116
101
100
101
680
207
147
122
116
-
-
-
96
101
100
101
680
207
147
122
116
101
100
101
680
207
147
122
116
95
-
-
-
101
104
350
188
94
94
-
-
-
Differential
SSTL-2 Class II
(3)
364
163
118
99
-
-
-
12 mA
16 mA
20 mA
24 mA
-
-
-
-
-
-
-
-
-
87
91
-
-
-
85
Altera Corporation
April 2011
5–75
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
Differential
SSTL-18 Class I
(3)
4 mA
6 mA
458
305
225
167
129
173
150
120
109
245
164
123
110
97
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
505
336
248
190
148
155
140
110
94
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
8 mA
10 mA
12 mA
8 mA
Differential
SSTL-18 Class II
(3)
16 mA
18 mA
20 mA
4 mA
1.8-V Differential
HSTL Class I (3)
229
153
114
108
104
99
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
1.8-V Differential
HSTL Class II (3)
101
98
93
93
88
1.5-V Differential
HSTL Class I (3)
168
112
84
196
131
99
196
131
99
188
125
95
196
131
99
196
131
99
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
87
98
98
90
98
98
86
98
98
87
98
98
1.5-V Differential
HSTL Class II (3)
95
101
100
101
177
177
-
101
100
101
177
177
-
96
101
100
101
177
177
134
101
100
101
177
177
134
95
101
104
143
143
134
94
3.3-V PCI
3.3-V PCI-X
LVDS
134
134
-
155 (1)
155 (1)
-
155
(1)
155
(1)
HyperTransport
technology
-
-
-
-
-
-
155
(1)
155
(1)
-
-
-
LVPECL (4)
-
-
134
134
134
5–76
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3
-4
-5
3.3-V LVTTL
OCT
50 Ω
133
207
151
300
157
121
56
152
152
133
152
152
147
152
152
2.5-V LVTTL
OCT
50 Ω
274
165
316
171
134
101
123
110
-
274
165
316
171
134
101
123
110
-
207
151
300
157
121
56
274
165
316
171
134
101
123
-
274
165
316
171
134
101
123
-
235
153
263
174
77
274
165
316
171
134
101
123
110
-
274
165
316
171
134
101
123
110
95
1.8-V LVTTL
OCT
50 Ω
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V HSTL (2)
OCT
50 Ω
OCT
50 Ω
OCT
50 Ω
OCT
25 Ω
58
OCT
50 Ω
100
61
100
-
106
59
OCT
25 Ω
OCT
95
-
-
-
-
50 Ω
Notes to Table 5–79:
(1) For LVDS and HyperTransport technology output on row I/O pins, the toggle rate derating factors apply to loads
larger than 5 pF. In the derating calculation, subtract 5 pF from the intended load value in pF for the correct result.
For a load less than or equal to 5 pF, refer to Table 5–78 for output toggle rates.
(2) 1.2-V HSTL is only supported on column I/O pins in I/O banks 4,7, and 8.
(3) Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4) LVPECL is only supported on column clock outputs.
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 5–7. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (Figure 5–7). The maximum
DCD for a clock is the larger value of D1 and D2.
Duty Cycle
Distortion
Altera Corporation
April 2011
5–77
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Figure 5–7. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1
D2
Falling Edge A
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 5–7, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions (Figure 5–8). Therefore, any DCD
present on the input clock signal or caused by the clock input buffer or
different input I/O standard does not transfer to the output signal.
Figure 5–8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
IOE
NOT
DFF
PRN
OUTPUT
inst1
output
D
Q
INPUT
VCC
clk
CLRN
inst
5–78
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 5–9). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 5–9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOE
V
CC DFF
D
PRN
Q
INPUT
VCC
clk
CLRN
inst2
OUTPUT
output
DFF
D
PRN
Q
GND
NOT
inst8
CLRN
inst3
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–80 through 5–87 give the maximum DCD in absolution
derivation for different I/O standards on Stratix II devices. Examples are
also provided that show how to calculate DCD as a percentage.
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1
of 2)
Note (1)
Maximum DCD for Non-DDIO Output
Row I/O Output
Standard
-3 Devices
-4 & -5 Devices
Unit
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
245
125
105
275
155
135
ps
ps
ps
Altera Corporation
April 2011
5–79
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 2
of 2) Note (1)
Maximum DCD for Non-DDIO Output
Row I/O Output
Standard
-3 Devices
-4 & -5 Devices
Unit
1.8 V
180
165
115
95
180
195
145
125
85
ps
ps
ps
ps
ps
ps
ps
ps
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
55
80
100
115
80
85
LVDS/
55
HyperTransport
technology
Note to Table 5–80:
(1) The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see Table 5–80). If the clock frequency is 267 MHz, the clock
period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 95ps) / 3745ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high
boundary)
5–80
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins
Note (1)
Column I/O Output
Standard I/O
Standard
Maximum DCD for Non-DDIO Output
Unit
-3 Devices
-4 & -5 Devices
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
190
140
125
80
220
175
155
110
215
135
130
115
100
110
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
185
105
100
90
70
1.8-V HSTL
Class I
80
1.8-V HSTL
Class II
80
85
50
110
115
80
ps
ps
ps
1.5-V HSTL
Class I
1.5-V HSTL
Class II
1.2-V HSTL (2)
170
55
-
ps
ps
LVPECL
80
Notes to Table 5–81:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
Altera Corporation
April 2011
5–81
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
(No PLL in Clock Path)
Row DDIO Output I/O
Standard
LVDS/
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL HyperTransport
Technology
3.3 & 2.5 V 1.8 & 1.5 V
1.8 & 1.5 V
3.3 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
260
210
195
150
255
175
170
155
150
150
180
380
330
315
265
370
295
290
275
270
270
180
145
100
85
145
100
85
110
65
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
75
1.8 V
85
85
120
105
70
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
140
65
140
65
60
60
75
55
50
90
60
60
95
55
55
90
LVDS/ HyperTransport
technology
180
180
180
Notes to Table 5–82:
(1) The information in Table 5–82 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see Table 5–82). If the clock
frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
boundary)
5–82
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Port (No PLL in the Clock Path)
Row DDIO Output I/O
Standard
LVDS/
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL HyperTransport
Technology
3.3/2.5 V
1.8/1.5 V
1.8/1.5 V
3.3 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
440
390
375
325
430
355
350
335
330
330
180
495
450
430
385
490
410
405
390
385
390
180
170
120
105
90
160
110
95
105
75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
90
1.8 V
100
155
75
135
100
85
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
160
85
80
70
90
65
65
105
110
105
180
60
70
60
70
LVDS/ HyperTransport
technology
180
180
Notes to Table 5–83:
(1) Table 5–83 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
1.2-V
HSTL
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
260
210
195
380
330
315
145
100
85
145
100
85
145
100
85
ps
ps
ps
Altera Corporation
April 2011
5–83
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
1.2-V
HSTL
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
1.8 V
150
255
175
170
155
140
150
150
150
125
240
180
265
370
295
290
275
260
270
270
270
240
360
180
85
140
65
85
140
65
85
140
65
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
60
60
60
55
50
50
70
70
70
60
60
60
60
60
60
55
55
55
85
85
85
155
180
155
180
155
180
LVPECL
Notes to Table 5–84:
(1) Table 5–84 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL
1.8/1.5 V
3.3/2.5 V
1.8/1.5 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
440
390
375
325
430
355
350
495
450
430
385
490
410
405
170
120
105
90
160
110
95
ps
ps
ps
ps
ps
ps
ps
1.8 V
100
155
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
160
85
80
70
5–84
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL
1.8/1.5 V
3.3/2.5 V
1.8/1.5 V
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
335
320
330
330
330
330
420
180
390
375
385
385
390
360
470
180
65
70
65
80
ps
ps
ps
ps
ps
ps
ps
ps
60
70
60
70
60
70
90
100
165
180
155
180
LVPECL
Notes to Table 5–85:
(1) Table 5–85 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2)
Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Row DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
3.3-V LVCMOS
2.5V
110
65
105
75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
75
90
1.8V
85
100
100
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
105
65
60
50
50
70
65
70
55
70
Altera Corporation
April 2011
5–85
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Row DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
LVDS/ HyperTransport
technology
180
180
ps
Note to Table 5–86:
(1) The DCD specification is based on a no logic array noise condition.
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Column DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
145
100
85
160
110
95
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
2.5V
1.8V
85
100
155
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
140
65
60
70
50
65
70
80
60
70
60
70
55
70
85
100
-
155
180
LVPECL
180
Notes to Table 5–87:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
5–86
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–88 provides high-speed timing specifications definitions.
High-Speed I/O
Specifications
Table 5–88. High-Speed Timing Specifications & Definitions
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
fHSCLK
J
W
tRISE
Low-to-high transmission time.
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Input jitter
Output jitter
tDUTY
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
tLOCK
Table 5–89 shows the high-speed I/O timing specifications for -3 speed
grade Stratix II devices.
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 1 of 2)
Symbol Conditions
Notes (1), (2)
-3 Speed Grade
Unit
Min Typ Max
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
16
520
MHz
(3)
fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
16
500
717
MHz
MHz
150
Altera Corporation
April 2011
5–87
Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
Notes (1), (2)
-3 Speed Grade
Symbol
Conditions
Unit
Min Typ Max
fHSDR (data rate)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
150
(4)
(4)
150
-
1,040
760
500
1,040
200
-
Mbps
Mbps
Mbps
Mbps
ps
fHSDRDPA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
TCCS
All differential standards
All differential standards
SW
330
ps
Output jitter
Output tRISE
Output tFALL
tDUTY
190
160
180
55
ps
All differential I/O standards
All differential I/O standards
ps
ps
45
50
%
DPA run length
DPA jitter tolerance
DPA lock time
6,400
UI
Data channel peak-to-peak jitter
0.44
UI
Standard
Training
Pattern
Transition
Density
Numberof
repetitions
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
Miscellaneous
00001111
10010000
10101010
01010101
25%
50%
256
256
256
256
100%
Notes to Table 5–89:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–88
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–90 shows the high-speed I/O timing specifications for -4 speed
grade Stratix II devices.
Table 5–90. High-Speed I/O Specifications for -4 Speed Grade
Symbol Conditions
Notes (1), (2)
-4 Speed Grade
Min Typ Max
Unit
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
16
520
MHz
(3)
fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
16
150
150
(4)
500
717
1,040
760
500
1,040
200
-
MHz
MHz
Mbps
Mbps
Mbps
Mbps
ps
fHSDR (data rate)
(4)
fHSDRDPA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
150
-
TCCS
All differential standards
All differential standards
SW
330
ps
Output jitter
Output tRISE
Output tFALL
tDUTY
190
160
180
55
ps
All differential I/O standards
All differential I/O standards
ps
ps
45
50
%
DPA run length
DPA jitter tolerance
DPA lock time
6,400
UI
Data channel peak-to-peak jitter
0.44
UI
Standard
Training
Pattern
Transition
Density
Numberof
repetitions
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
00001111
10010000
10101010
01010101
25%
50%
256
256
256
256
Miscellaneous
100%
Notes to Table 5–90:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Altera Corporation
April 2011
5–89
Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5–91 shows the high-speed I/O timing specifications for -5 speed
grade Stratix II devices.
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
Notes (1), (2)
-5 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
16
420
MHz
(3)
fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
16
150
150
(4)
500
640
840
700
500
840
200
-
MHz
MHz
Mbps
Mbps
Mbps
Mbps
ps
fHSDR (data rate)
(4)
fHSDRDPA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
150
-
TCCS
All differential I/O standards
All differential I/O standards
SW
440
ps
Output jitter
Output tRISE
Output tFALL
tDUTY
190
290
290
55
ps
All differential I/O standards
All differential I/O standards
ps
ps
45
50
%
DPA run length
DPA jitter tolerance
DPA lock time
6,400
UI
Data channel peak-to-peak jitter
0.44
UI
Standard
Training
Pattern
Transition
Density
Numberof
repetitions
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
Miscellaneous
00001111
10010000
10101010
01010101
25%
50%
256
256
256
256
100%
Notes to Table 5–91:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–90
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Tables 5–92 and 5–93 describe the Stratix II PLL specifications when
operating in both the commercial junction temperature range (0 to 85 °C)
and the industrial junction temperature range (–40 to 100 °C).
PLL Timing
Specifications
Table 5–92. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
2
Typ
Max
500
420
Unit
MHz
MHz
fIN
Input clock frequency
fINPFD
Input frequency to the
PFD
2
fINDUTY
Input clock duty cycle
40
40
60
60
%
%
fEINDUTY
External feedback
input clock duty cycle
tINJITTER
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth ≤
0.5
1.0
ns (p-p)
ns (p-p)
0.85 MHz
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth >
0.85 MHz
tOUTJITTER
tFCOMP
fOUT
Dedicated clock
output period jitter
ps or mUI
(p-p)
250 ps for ≥ 100 MHz outclk
25 mUI for < 100 MHz outclk
External feedback
compensation time
10
ns
Output frequency for
internal global or
regional clock
1.5
(2)
550.0
MHz
tOUTDUTY
Duty cycle for external
clock output (when set
to 50%).
45
50
55
%
fSCANCLK
Scanclk frequency
100
MHz
ns
tCONFIGPLL
Time required to
reconfigure scan
chains for enhanced
PLLs
174/fSCANCLK
fOUT_EXT
PLL external clock
output frequency
1.5
(2)
550.0 (1)
MHz
Altera Corporation
April 2011
5–91
Stratix II Device Handbook, Volume 1
PLL Timing Specifications
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Unit
tLOCK
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
0.03
1
ms
tDLOCK
Time required for the
PLL to lock
1
ms
dynamically after
automatic clock
switchover between
two identical clock
frequencies
fSWITCHOVER
Frequency range
where the clock
switchover performs
properly
4
500
MHz
fCLBW
fVCO
PLL closed-loop
bandwidth
0.13
300
1.20
16.90
1,040
MHz
MHz
PLL VCO operating
range for –3 and –4
speed grade devices
PLL VCO operating
range for –5 speed
grade devices
300
840
MHz
fSS
Spread-spectrum
modulation frequency
30
150
0.6
kHz
%
% spread
Percent down spread
for a given clock
frequency
0.4
0.5
tPLL_PSERR
tARESET
Accuracy of PLL
phase shift
15
ps
ns
ns
Minimum pulse width
on aresetsignal.
10
tARESET_RECONFIG Minimum pulse width
on the aresetsignal
when using PLL
500
reconfiguration. Reset
the PLL after
scandonegoes
high.
Notes to Table 5–92:
(1) Limited by I/O fMA X. See Table 5–78 on page 5–69 for the maximum. Cannot exceed fOUT specification.
(2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
5–92
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–93. Fast PLL Specifications
Name Description
Min
Typ
Max
Unit
fIN
Input clock frequency (for -3 and -4 speed
grade devices)
16.08
717
MHz
Input clock frequency (for -5 speed grade
devices)
16.08
640
MHz
fINPFD
Input frequency to the PFD
Input clock duty cycle
16.08
40
500
60
MHz
%
fINDUTY
tINJITTER
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
0.5
1.0
ns (p-p)
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 2 MHz
ns (p-p)
MHz
fVCO
Upper VCO frequency range for –3 and –4
speed grades
300
300
150
150
1,040
840
Upper VCO frequency range for –5 speed
grades
MHz
Lower VCO frequency range for –3 and –4
speed grades
520
MHz
Lower VCO frequency range for –5 speed
grades
420
MHz
fOUT
4.6875
150
550
1,040
(1)
MHz
MHz
MHz
PLL output frequency to GCLKor RCLK
PLL output frequency to LVDS or DPA clock
fOUT_IO
PLL clock output frequency to regular I/O
pin
4.6875
fSCANCLK
Scanclk frequency
100
MHz
ns
tCONFIGPLL
Time required to reconfigure scan chains
for fast PLLs
75/fSCANCLK
fCLBW
tLOCK
PLL closed-loop bandwidth
1.16
5.00
0.03
28.00
1.00
MHz
ms
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
tPLL_PSERR
Accuracy of PLL phase shift
15
ps
ns
ns
tARESET
10
Minimum pulse width on aresetsignal.
tARESET_RECONFIG
500
Minimum pulse width on the aresetsignal
when using PLL reconfiguration. Reset the
PLL after scandonegoes high.
Note to Table 5–93:
(1) Limited by I/O fMA X. See Table 5–77 on page 5–67 for the maximum.
Altera Corporation
April 2011
5–93
Stratix II Device Handbook, Volume 1
External Memory Interface Specifications
Tables 5–94 through 5–101 contain Stratix II device specifications for the
dedicated circuitry used for interfacing with external memory devices.
External
Memory
Interface
Table 5–94. DLL Frequency Range Specifications
Specifications
Resolution
(Degrees)
Frequency Mode
Frequency Range
0
1
2
3
100 to 175
150 to 230
30
22.5
30
200 to 310
240 to 400 (–3 speed grade)
240 to 350 (–4 and –5 speed grades)
36
36
Table 5–95 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 5–95. DQS Delay Buffer Maximum Delay in Fast Timing Model
Maximum Delay Per Delay Buffer
Frequency Mode
Unit
(Fast Timing Model)
0
0.833
0.416
ns
ns
1, 2, 3
Table 5–96. DQS Period Jitter Specifications for DLL-Delayed Clock
(tDQS_JITTER) Note (1)
Number of DQS Delay Buffer
Commercial
Industrial
Unit
Stages (2)
1
2
3
4
80
110
130
180
210
ps
ps
ps
ps
110
130
160
Notes to Table 5–96:
(1) Peak-to-peak period jitter on the phase shifted DQS clock.
(2) Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
5–94
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
DC & Switching Characteristics
Table 5–97. DQS Phase Jitter Specifications for DLL-Delayed Clock
(tDQS PHASE_JITTER) Note (1)
Number of DQS Delay
Buffer Stages (2)
DQS Phase Jitter
Unit
1
2
3
4
30
60
ps
ps
ps
ps
90
120
Notes to Table 5–97:
(1) Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
(2) Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
Table 5–98. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR)
(1)
Number of DQS Delay Buffer Stages (2) –3 Speed Grade –4 Speed Grade –5 Speed Grade
Unit
1
2
3
4
25
50
30
60
35
70
ps
ps
ps
ps
75
90
105
140
100
120
Notes to Table 5–98:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer
stages in a C3 speed grade is 75 ps or 37.5 ps.
(2) Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the
Quartus II software.
Table 5–99. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder
Unit
×4 DQ per DQS
×9 DQ per DQS
×18 DQ per DQS
×36 DQ per DQS
40
70
75
95
ps
ps
ps
ps
Note to Table 5–99:
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×4 DQ group is 40 ps or 20 ps.
Altera Corporation
April 2011
5–95
Stratix II Device Handbook, Volume 1
JTAG Timing Specifications
Table 5–100. DQS Phase Offset Delay Per Stage
Notes (1), (2), (3)
Max Unit
Speed Grade
Min
-3
-4
-5
9
9
9
14
14
15
ps
ps
ps
Notes to Table 5–100:
(1) The delay settings are linear.
(2) The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
(3) The typical value equals the average of the minimum and maximum values.
Table 5–101. DDIO Outputs Half-Period Jitter
Name Description
Notes (1), (2)
Max
Unit
tOUTHALFJITTER Half-period jitter (PLL driving DDIO outputs) 200
ps
Notes to Table 5–101:
(1) The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
(2) The half-period jitter was characterized using a PLL driving DDIO outputs.
Figure 5–10 shows the timing requirements for the JTAG signals.
JTAG Timing
Specifications
Figure 5–10. Stratix II JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
5–96
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–102 shows the JTAG timing parameters and values for Stratix II
devices.
Table 5–102. Stratix II JTAG Timing Parameters & Values
Symbol
tJCP
Parameter
TCKclock period
Min
30
13
13
3
Max Unit
ns
ns
ns
ns
ns
tJCH
TCKclock high time
tJCL
TCKclock low time
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
5
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
11 (1)
14 (1)
14 (1)
ns
ns
ns
Note to Table 5–102:
(1) A 1 ns adder is required for each VCC IO voltage step down from 3.3 V. For
example, tJPCO = 12 ns if VC CIO of the TDO I/O bank = 2.5 V, or 13 ns if it equals
1.8 V.
Table 5–103 shows the revision history for this chapter.
Document
Revision History
Table 5–103. Document Revision History (Part 1 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
April 2011, v4.5 Updated Table 5–3.
Added operating junction temperature
for military use.
July 2009, v4.4
May 2007, v4.3
Updated Table 5–92.
Updated the spread spectrum
modulation frequency (fSS) from
(100 kHz–500 kHz) to
(30 kHz–150 kHz).
●
●
●
Updated RCONF in Table 5–4.
Updated fIN (min) in Table 5–92.
Updated fIN and fINPFD in Table 5–93.
—
Moved the Document Revision History section to the
end of the chapter.
—
Altera Corporation
April 2011
5–97
Stratix II Device Handbook, Volume 1
Document Revision History
Table 5–103. Document Revision History (Part 2 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
August, 2006,
v4.2
Updated Table 5–73, Table 5–75, Table 5–77,
Table 5–78, Table 5–79, Table 5–81, Table 5–85, and
Table 5–87.
—
April 2006, v4.1
●
●
●
●
Updated Table 5–3.
Updated Table 5–11.
Updated Figures 5–8 and 5–9.
●
●
●
Changed 0.2 MHz to 2 MHz in
Table 5–93.
Added new spec for half period
jitter (Table 5–101).
Added support for PLL clock
switchover for industrial
temperature range.
Changed fINPFD (min) spec from
4 MHz to 2 MHz in Table 5–92.
Fixed typo in tOUTJITTER
specification in Table 5–92.
Updated VDIF AC & DC max
specifications in Table 5–28.
Updated minimum values for tJCH
tJCL, and tJPSU in Table 5–102.
Update maximum values for tJPCO
tJPZX, and tJPXZ in Table 5–102.
Added parallel on-chip termination information to
“On-Chip Termination Specifications” section.
Updated Tables 5–28, 5–30,5–31, and 5–34.
Updated Table 5–78, Tables 5–81 through 5–90,
and Tables 5–92, 5–93, and 5–98.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
●
●
●
●
●
●
●
●
●
●
●
Added Tables 5–95 and 5–101.
Updated “JTAG Timing Specifications” section,
including Figure 5–10 and Table 5–102.
,
,
December 2005,
v4.0
●
Updated “External Memory Interface
Specifications” section.
—
●
●
Updated timing numbers throughout chapter.
July 2005, v3.1
Updated HyperTransport technology information in
Table 5–13.
—
●
●
●
Updated “Timing Model” section.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
May 2005, v3.0
●
●
●
●
Updated tables throughout chapter.
Updated “Power Consumption” section.
Added various tables.
Replaced “Maximum Input & Output Clock Rate”
section with “Maximum Input & Output Clock Toggle
Rate” section.
—
●
●
Added “Duty Cycle Distortion” section.
Added “External Memory Interface Specifications”
section.
March 2005,
v2.2
Updated tables in “Internal Timing Parameters”
section.
—
—
January 2005,
v2.1
Updated input rise and fall time.
5–98
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–103. Document Revision History (Part 3 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
January 2005,
v2.0
●
●
Updated the “Power Consumption” section.
Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
Removed the ESD Protection Specifications
section.
Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
Updated tables in “Timing Model” section.
Added Tables 5–30 and 5–31.
—
●
●
●
●
October 2004,
v1.2
●
●
Updated Table 5–3.
Updated introduction text in the “PLL Timing
Specifications” section.
—
—
July 2004, v1.1
●
●
●
Re-organized chapter.
Added typical values and COUTFB to Table 5–32.
Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
●
●
●
Added Note (1) to Tables 5–5 and 5–6.
Added VID and VICM to Table 5–10.
Added “I/O Timing Measurement Methodology”
section.
●
●
Added Table 5–72.
Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
—
Altera Corporation
April 2011
5–99
Stratix II Device Handbook, Volume 1
Document Revision History
5–100
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
6. Reference & Ordering
Information
SII51006-2.2
Stratix® II devices are supported by the Altera® Quartus® II design
software, which provides a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap® II logic analyzer,
and device configuration. See the Quartus II Handbook for more
information on the Quartus II software features.
Software
The Quartus II software supports the Windows XP/2000/NT/98, Sun
Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also
supports seamless integration with industry-leading EDA tools through
the NativeLink® interface.
Device pin-outs for Stratix II devices are available on the Altera web site
at (www.altera.com).
Device Pin-Outs
Figure 6–1 describes the ordering codes for Stratix II devices. For more
information on a specific package, refer to the Package Information for
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device
Handbook or the Stratix II GX Device Handbook.
Ordering
Information
Altera Corporation
April 2011
6–1
Document Revision History
Figure 6–1. Stratix II Device Packaging Ordering Information
EP2S
90
F
1508
C
7
ES
Family Signature
Optional Suffix
EP2S: Stratix II
Indicates specific device options or
shipment method.
ES: Engineering sample
Device Type
15
30
Speed Grade
3, 4, or 5, with 3 being the fastest
60
90
130
180
Operating Temperature
C: Commercial temperature (t = 0
°
C to 85
°
C)
C)
J
I: Industrial temperature (t = -40
°
C to 100°
J
Military temperature (t = -55
°
C to 125
°
C) (1)
J
Package Type
Pin Count
Number of pins for a particular FineLine BGA package
F: FineLine BGA
H: Hybrid FineLine BGA
Note to Figure 6–1:
(1) Applicable to I4 devices. For more information, refer to the Stratix II Military Temperature Range Support technical
brief.
Table 6–1 shows the revision history for this chapter.
Document
Revision History
Table 6–1. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
April 2011,
v2.2
Updated Figure 6–1.
Added operating junction temperature
for military use.
May 2007,
v2.1
Moved the Document Revision History section to the end
of the chapter.
—
—
—
—
January
2005, v2.0
Contact information was removed.
October
2004, v1.1
Updated Figure 6–1.
February
Added document to the Stratix II Device Handbook.
2004, v1.0
6–2
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
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