EP3CLS200F780C8N [INTEL]
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE, FBGA-780;
| 型号： | EP3CLS200F780C8N |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE, FBGA-780 时钟 栅 可编程逻辑 |
| 文件： | 总32页 (文件大小：760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2. Cyclone III LS Device Datasheet
July 2012
CIII52002-1.4
CIII52002-1.4
This chapter describes the electric characteristics, switching characteristics, and I/O
timing for Cyclone® III LS devices. A glossary is also included for your reference.
Electrical Characteristics
The following sections provide information about the absolute maximum ratings,
recommended operating conditions, DC characteristics, and other specifications for
Cyclone III LS devices.
Operating Conditions
When Cyclone III LS devices are implemented in a system, they are rated according to
a set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone III LS devices, you must consider the operating requirements in
this chapter. Cyclone III LS devices are offered in commercial and industrial grades.
Commercial devices are offered in –7 (fastest) and –8 speed grades. Industrial devices
are offered only in –7 speed grade.
1
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades—commercial with a “C” prefix; industrial with an “I” prefix. For
example, commercial devices are described as C7 and C8 per respective speed grades.
Industrial devices are described as I7.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for
Cyclone III LS devices. The values are based on experiments conducted with the
device and theoretical modeling of breakdown and damage mechanisms. The
functional operation of the device is not implied at these conditions. Table 2–1 lists the
absolute maximum ratings for Cyclone III LS devices.
Conditions beyond those listed in Table 2–1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device. All parameters representing
voltages are measured with respect to ground.
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1) (Part 1 of 2)
Symbol
VCCINT
Parameter
Supply voltage for internal logic
Supply voltage for output buffers
Min
–0.5
–0.5
Max
1.8
Unit
V
VCCIO
3.9
V
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 2
July 2012
Subscribe
2–2
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1) (Part 2 of 2)
Symbol
VCCA
VCCD_PLL
Parameter
Min
–0.5
–0.5
Max
3.75
1.8
Unit
V
Supply (analog) voltage for PLL regulator
Supply (digital) voltage for PLL
V
Battery back-up power supply for design
security volatile key register
(2)
VCCBAT
–0.5
3.75
V
VI
DC input voltage
–0.5
–25
3.95
40
V
IOUT
DC output current, per pin
mA
Electrostatic discharge voltage using the human
body model
VESDHBM
VESDCDM
—
—
2000
500
V
V
Electrostatic discharge voltage using the
charged device model
TSTG
TJ
Storage temperature
–65
–40
150
125
°C
°C
Operating junction temperature
Notes to Table 2–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
power supply.
(2) VCCBAT is tied to Power-on reset (POR). If the VCCBAT is below 1.2 V, the device will not power up.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2–2 and
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods
shorter than 20 ns.
Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage over the lifetime of the device. The maximum
allowed overshoot duration is specified as percentage of high-time over the lifetime of
the device.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–3
Electrical Characteristics
1
A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for a
device lifetime of 10 years, this is equivalent to 10.74% of ten years, which is 12.89
months.
Table 2–2. Cyclone III LS Devices Maximum Allowed Overshoot During Transitions over a 10-Year
Time Frame
Symbol
Parameter
Condition
VI = 3.95 V
VI = 4.0 V
Overshoot Duration as % of High Time
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
100
95.67
55.24
31.97
18.52
10.74
6.23
VI = 4.05 V
VI = 4.10 V
VI = 4.15 V
VI = 4.20 V
VI = 4.25 V
VI = 4.30 V
VI = 4.35 V
VI = 4.40 V
VI = 4.45 V
VI = 4.50 V
VI = 4.60 V
VI = 4.70 V
AC Input
Voltage
Vi
3.62
2.1
1.22
0.71
0.41
0.14
0.047
Figure 2–1 shows the methodology to determine the overshoot duration. In this
example, overshoot voltage is shown in red and is present on the input pin of the
Cyclone III LS device at over 4.1 V but below 4.2 V. From Table 2–1, for an overshoot
of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over a
10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This
10-year period assumes the device is always turned on with 100% I/O toggle rate and
50% duty cycle signal. For lower I/O toggle rates and situations in which the device is
in an idle state, lifetimes are increased.
Figure 2–1. Cyclone III LS Devices Overshoot Duration
4.2 V
4.1 V
3.3 V
ΔT
T
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–4
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III LS devices.
The steady-state voltage and current values expected from Cyclone III LS devices are
provided in Table 2–3. All supplies must be strictly monotonic without plateaus.
Table 2–3. Cyclone III LS Devices Recommended Operating Conditions (1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(3)
VCCINT
Supply voltage for internal logic
—
1.15
1.2
1.25
V
Supply voltage for output buffers, 3.3-V
operation
—
—
—
—
—
—
3.135
2.85
3.3
3.0
2.5
1.8
1.5
1.2
3.465
3.15
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V
operation
Supply voltage for output buffers, 2.5-V
operation
2.375
1.71
2.625
1.89
(3), (7)
VCCIO
Supply voltage for output buffers, 1.8-V
operation
Supply voltage for output buffers, 1.5-V
operation
1.425
1.14
1.575
1.26
Supply voltage for output buffers, 1.2-V
operation
(3)
VCCA
Supply (analog) voltage for PLL regulator
Supply (digital) voltage for PLL
—
—
2.375
1.15
2.5
1.2
2.625
1.25
V
V
(3)
VCCD_PLL
Battery back-up power supply for design
security volatile key register
(4)
VCCBAT
—
1.2
3.0
3.3
V
VI
Input voltage
—
–0.5
0
—
—
—
—
—
—
3.6
VCCIO
85
V
VO
Output voltage
—
V
For commercial use
0
°C
°C
—
—
TJ
Operating junction temperature
Power supply ramptime
For industrial use
–40
50 µs
50 µs
100
(5)
Standard POR
50 ms
3 ms
tRAMP
IDiode
(6)
Fast POR
Magnitude of DC current across
PCI-clamp diode when enabled
—
—
—
10
mA
Notes to Table 2–3:
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when you do not use phase
locked-loops [PLLs}), and must be powered up and powered down at the same time.
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.
(3) VCC must rise monotonically.
(4) VCCBAT is tied to POR. If the VCCBAT is below 1.2 V, the device will not power up.
(5) POR time for Standard POR ranges from 50 to 200 ms. Each individual power supply must reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges from 3 to 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.
(7) All input buffers are powered by the VCCIO supply.
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III LS devices.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–5
Electrical Characteristics
Supply Current
Supply current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Use the Excel-based Early
Power Estimator (EPE) to get the supply current estimates for your design because
these currents vary largely with the resources you use. Table 2–4 lists the I/O pin
leakage current for Cyclone III LS devices.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Table 2–4. Cyclone III LS Devices I/O Pin Leakage Current (1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
II
Input Pin Leakage Current VI = VCCIOMAX to 0 V
Tri-stated I/O Pin Leakage VO = VCCIOMAX to 0
–10
—
10
A
IOZ
–10
—
10
A
Current
V
Notes to Table 2–4:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
V
(2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be
observed when the diode is on.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 2–5 lists the bus hold specifications for Cyclone III LS devices. Also listed are the
input pin capacitances and OCT tolerance specifications.
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
low,
sustaining
current
VIN > VIL
(maximum)
8
—
—
12
–12
—
—
—
30
–30
—
—
—
50
–50
—
—
—
70
–70
—
—
—
70
–70
—
—
—
A
A
Bus-hold
high,
sustaining
current
VIN < VIL
(minimum)
–8
—
Bus-hold
low,
overdrive
current
0 V < VIN
VCCIO
<
125
175
200
300
500
500 A
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–6
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
high,
overdrive
current
0 V < VIN
VCCIO
<
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500 A
Bus-hold
trip point
—
0.3
0.9 0.375 1.125 0.68 1.07 0.7
1.7 0.8 2.0 0.8 2.0
V
Note to Table 2–5:
(1) Bus-hold trip points are based on calculated input voltages from the JEDEC standard.
OCT Specifications
Table 2–6 lists the variation of OCT without calibration across process, temperature,
and voltage (PVT).
Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
V
CCIO (V)
Unit
Commercial Max
Industrial Max
3.0
2.5
1.8
1.5
1.2
30
30
40
50
50
40
40
50
50
50
%
%
%
%
%
Series OCT without
calibration
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Table 2–7 lists the OCT calibration accuracy at device power-up.
Table 2–7. Cyclone III LS Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
V
CCIO (V)
Unit
Commercial Max
Industrial Max
3.0
2.5
1.8
1.5
1.2
10
10
10
10
10
10
10
10
10
10
%
%
%
%
%
Series Termination with
power-up calibration
OCT resistance may vary with the variation of temperature and voltage after
power-up calibration. Use Table 2–8 and Equation 2–1 to determine the final OCT
resistance considering the variations after power-up calibration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–7
Electrical Characteristics
Table 2–8 lists the percentage change of the OCT resistance with voltage and
temperature.
Table 2–8. Cyclone III LS Devices OCT Variation After Calibration at Device Power-Up (1)
Nominal Voltage
dR/dT (%/°C)
0.262
dR/dV (%/mV)
–0.026
3.0
2.5
1.8
1.5
1.2
0.234
–0.039
0.219
–0.086
0.199
–0.136
0.161
–0.288
Note to Table 2–8:
(1) Use this table to calculate the final OCT resistance with the variation of temperature and voltage.
(1), (2), (3), (4), (5), (6)
Equation 2–1.
(7)
RV = (V2 – V1) × 1000 × dR/dV –––––
(8)
RT = (T2 – T1) × dR/dT –––––
(9)
For Rx < 0; MFx = 1/ (|Rx|/100 + 1) –––––
(10)
For Rx > 0; MFx = Rx/100 + 1 –––––
(11)
MF = MFV × MFT –––––
(12)
Rfinal = Rinitial × MF –––––
Notes to Equation 2–1:
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript × refers to both V and T.
(7) RV is variation of resistance with voltage.
(8) RT is variation of resistance with temperature.
(9) dR/dT is the percentage change of resistance with temperature.
(10) dR/dV is the percentage change of resistance with voltage.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–8
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Example 2–1 shows you how to calculate the change of 50 I/O impedance from
25°C at 3.0 V to 85°C at 3.15 V.
Example 2–1.
RV = (3.15 – 3) × 1000 × –0.026 = –3.83
RT = (85 – 25) × 0.262 = 15.72
Because RV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because RT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
R
final = 50 × 1.114 = 55.71
Pin Capacitance
Table 2–9 lists the pin capacitance for Cyclone III LS devices.
Table 2–9. Cyclone III LS Devices Pin Capacitance
Typical – Typical –
Symbol
Parameter
Unit
QFP
FBGA
CIOTB
CIOLR
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
7
6
5
pF
pF
7
Input capacitance on left/right I/O pins with true LVDS
output
CLVDSLR
8
21
23
7
7
21
23
6
pF
pF
pF
pF
pF
CVREFLR
Input capacitance on left/right dual-purpose VREFpin
when used as VREF or user I/O pin
(1)
CVREFTB
Input capacitance on top/bottom dual-purpose VREF
pin when used as VREF or user I/O pin
(1)
Input capacitance on top/bottom dedicated clock input
pins
CCLKTB
CCLKLR
Input capacitance on left/right dedicated clock input
pins
6
5
Note to Table 2–9:
(1) When you use the VREFpin as a regular input or output, you can expect a reduced performance of toggle rate and
CO due to higher pin capacitance.
t
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–9
Electrical Characteristics
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 2–10 lists the weak pull-up and pull-down resistor values for Cyclone III LS
devices.
Table 2–10. Cyclone III LS Devices Internal Weak Pull-Up Weak and Pull-Down Resistor (1)
Symbol
Parameter
Conditions
Min
7
Typ
25
28
35
57
82
143
19
22
25
35
50
Max
41
Unit
(2), (3)
VCCIO = 3.3 V 5%
k
k
k
k
k
k
k
k
k
k
k
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(4)
V
V
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
7
47
Value of I/O pin pull-up resistor before
and during configuration, as well as
user mode if the programmable
pull-up resistor option is enabled
8
61
R_PU
VCCIO = 1.8 V 5%
10
13
19
6
108
163
351
30
V
V
V
V
V
V
V
CCIO = 1.5 V 5%
CCIO = 1.2 V 5%
CCIO = 3.3 V 5%
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
CCIO = 1.8 V 5%
CCIO = 1.5 V 5%
(4)
6
36
Value of I/O pin pull-down resistor
before and during configuration
(4)
R_PD
6
43
(4)
7
71
(4)
8
112
Notes to Table 2–10:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(3) R_PU = (VCCIO – VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5%;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Hot Socketing
Table 2–11 lists the hot-socketing specifications for Cyclone III LS devices.
Table 2–11. Cyclone III Devices LS Hot-Socketing Specifications
Symbol
Parameter
DC current per I/O pin
AC current per I/O pin
Maximum
IIOPIN(DC)
IIOPIN(AC)
300 A
(1)
8 mA
Note to Table 2–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin
capacitance and dv/dt is the slew rate.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–10
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III LS devices support Schmitt trigger input on TDI
CONF_DONE, and DCLKpins. A Schmitt trigger feature introduces
,
TMS, TCK, nSTATUS,
nCONFIG, nCE,
hysteresis to the input signal for improved noise immunity, especially for signals with
a slow edge rate. Table 2–12 lists the hysteresis specifications across supported VCCIO
range for Schmitt trigger inputs in Cyclone III LS devices.
Table 2–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III LS Devices
Symbol
Parameter
Conditions
Minimum
200
Typical
—
Maximum
Unit
mV
mV
mV
mV
VCCIO = 3.3 V
—
—
—
—
V
V
CCIO = 2.5 V
CCIO = 1.8 V
200
—
Hysteresis for Schmitt trigger
input
VSCHMITT
140
—
VCCIO = 1.5 V
110
—
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Cyclone III LS devices.
Table 2–13 through Table 2–18 provide Cyclone III LS devices I/O standard
specifications.
Table 2–13. Cyclone III LS Devices Single-Ended I/O Standard Specifications (1)
VCCIO (V)
Typ
VIL (V)
Max Min Max
VIH (V)
Max
VOL (V)
VOH (V)
IOL
IOH
I/O Standard
(mA) (mA)
Min
Min
1.7
1.7
1.7
1.7
Max
0.45
0.2
Min
2.4
(2)
3.3-V LVTTL
3.135 3.3 3.465
3.135 3.3 3.465
—
—
0.8
0.8
0.8
0.8
3.6
4
2
4
–4
–2
(2)
(2)
3.3-V LVCMOS
3.6
VCCIO – 0.2
2.4
(2)
3.0-V LVTTL
2.85
2.85
3.0
3.0
3.15 –0.3
3.15 –0.3
VCCIO + 0.3
VCCIO + 0.3
0.45
0.2
–4
3.0-V LVCMOS
VCCIO – 0.2 0.1
–0.1
2.5-V LVTTL and
LVCMOS
2.375 2.5 2.625 –0.3
1.71 1.8 1.89 –0.3
1.425 1.5 1.575 –0.3
0.7
1.7
3.6
0.4
2.0
1
2
2
2
–1
–2
(2)
1.8-V LVTTL and
LVCMOS
0.35* 0.65*
VCCIO VCCIO
VCCIO
0.45
–
2.25
0.45
0.35* 0.65*
VCCIO VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.5-V LVCMOS
1.2-V LVCMOS
PCI
VCCIO + 0.3
VCCIO + 0.3
–2
0.35* 0.65*
VCCIO VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.14
2.85
2.85
1.2
3.0
3.0
1.26 –0.3
–2
0.30* 0.50*
VCCIO VCCIO
3.15
3.15
—
—
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO 1.5
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO 1.5
–0.5
–0.5
0.35* 0.50*
VCCIO VCCIO
PCI-X
Notes to Table 2–13:
(1) AC load CL = 10 pF.
(2) For more information about interfacing Cyclone III LS devices with 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS I/O standards,
refer to AN 447: Interfacing Cyclone III and Cyclone iV Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–11
Electrical Characteristics
Table 2–14. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (4)
(3)
V
CCIO (V)
VREF (V)
Typ
VTT (V)
Typ
I/O
Standard
Min
Typ Max
Min
Max
Min
Max
SSTL-2
Class I, II
VREF
0.04
–
VREF
0.04
+
2.375 2.5 2.625
1.7 1.8 1.9
1.19
1.25
0.9
1.31
VREF
VREF
0.9
SSTL-18
Class I, II
VREF
0.04
–
VREF
0.04
+
0.833
0.85
0.71
0.969
0.95
HSTL-18
Class I, II
1.71 1.8 1.89
1.425 1.5 1.575
0.9
0.85
0.71
0.95
0.79
HSTL-15
Class I, II
0.75
0.79
0.75
0.48 * VCCIO
(1)
(2)
(1)
(2)
0.5 * VCCIO
0.5 * VCCIO
0.52 * VCCIO
0.53 * VCCIO
(1)
HSTL-12
Class I, II
0.5 *
VCCIO
1.14 1.2 1.26
—
—
0.47 * VCCIO
(2)
Notes to Table 2–14:
(1) The value shown refers to the DC input reference voltage, VREF(DC)
(2) The value shown refers to the AC input reference voltage, VREF(AC)
(3) VTT of the transmitting device must track VREF of the receiving device.
(4) For an explanation of the terms used in Table 2–14, refer to “Glossary” on page 2–26.
.
.
Table 2–15. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications
VIL(DC) (V)
Min Max
VREF
VIH(DC) (V)
Max
VIL(AC) (V)
Min Max
VREF
VIH(AC) (V)
Min Max
VOL (V) VOH (V)
Max Min
I/O
IOL
IOH
Standard
(mA) (mA)
Min
SSTL-2
Class I
–
VREF
0.18
+
–
VREF
0.35
+
VTT
0.57
–
VTT +
0.57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.1
16.4 –16.4
6.7 –6.7
13.4 –13.4
–8.1
0.18
0.35
SSTL-2
Class II
VREF
0.18
–
VREF
0.18
+
VREF
–
VREF
0.35
+
VTT
0.76
–
VTT
0.76
+
—
0.35
SSTL-18
Class I
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VTT
0.475
–
VTT +
0.475
—
0.125
0.25
SSTL-18
Class II
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VCCIO
0.28
–
—
0.28
0.4
0.4
0.4
0.4
0.125
0.25
HSTL-18
Class I
VREF
0.1
–
–
–
–
–
VREF
0.1
+
+
+
+
+
VREF
0.2
–
VREF
0.2
+
VCCIO
0.4
–
—
8
16
8
–8
–16
–8
HSTL-18
Class II
VREF
0.1
VREF
0.1
VREF
0.2
–
–
–
–
VREF
0.2
+
+
+
+
VCCIO
0.4
–
–
–
—
HSTL-15
Class I
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
16
8
–16
–8
HSTL-12
Class I
VREF
0.08
VREF
VREF
VREF
VCCIO
+
+
0.25 × 0.75 ×
VCCIO VCCIO
–0.15
–0.15
VCCIO + 0.15 –0.24
VCCIO + 0.15 –0.24
0.08
VREF
0.08
0.15
0.15
0.24
HSTL-12
Class II
VREF
0.08
–
+
VREF
–
VREF
+
VCCIO
0.24
0.25 × 0.75 ×
VCCIO VCCIO
14
–14
0.15
0.15
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–12
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
f
For more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the High-Speed Differential Interfaces in
Cyclone III Devices chapter.
Table 2–16. Cyclone III LS Devices Differential SSTL I/O Standard Specifications (1)
VSwing(DC)
(V)
VSwing(AC)
VCCIO (V)
VX(AC) (V)
Typ
VOX(AC) (V)
Typ Max
(V)
I/O Standard
Min Typ Max Min Max
Min
Max
Min Max
Min
SSTL-2
Class I, II
V
+ 0.2
CCIO/2
VCCI VCCIO/2 –
V
CCIO/2
2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2
VCCIO/2 –
—
—
0.7
0.5
—
—
0.125
+ 0.125
O
SSTL-18
Class I, II
V
CCIO/2
VCCI VCCIO/2 –
V
CCIO/2
1.7
1.8 1.90 0.25 VCCIO
0.175
+ 0.175
0.125
+ 0.125
O
Note to Table 2–16:
(1) Differential SSTL requires a VREF input.
Table 2–17. Cyclone III LS Devices Differential HSTL I/O Standard Specifications (1)
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
VDIF(AC) (V)
I/O Standard
Min Typ Max Min Max
Min
Max
Min
Typ
Max
Min Max
HSTL-18
Class I, II
1.71 1.8 1.89 0.2
1.425 1.5 1.575 0.2
—
—
0.85
—
—
—
0.95
0.85
—
0.95
0.4
0.4
0.3
—
—
HSTL-15
Class I, II
0.71
0.79
0.71
—
—
0.79
HSTL-12
Class I, II
0.48 *
VCCIO
0.52 * 0.48 *
VCCIO VCCIO
0.52 *
VCCIO
0.48 *
VCCIO
1.14 1.2 1.26 0.16 VCCIO
Note to Table 2–17:
(1) Differential HSTL requires a VREF input.
Table 2–18. Differential I/O Standard Specifications (1) (Part 1 of 2)
(2)
(2)
V
CCIO (V)
VID (mV)
VICM (V)
VOD (mV)
VOS (V)
I/O
Standard
Min Typ Max Min Max Min
Condition
Max Min Typ Max Min Typ Max
0
DMAX500 Mbps 1.85
LVPECL
(Row
I/Os)
500 Mbps DMAX
700 Mbps
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
—
0.5
1.85
1.6
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
1
0
DMAX > 700 Mbps
D
MAX 500 Mbps 1.85
LVPECL
(Column
500 Mbps DMAX
700 Mbps
0.5
1.85
1.6
(3)
I/Os)
1
0
D
D
MAX > 700 Mbps
MAX 500 Mbps 1.85
LVDS
(Row
I/Os)
500 Mbps DMAX
700 Mbps
0.5
1
1.85 247
1.6
600 1.125 1.25 1.375
D
MAX > 700 Mbps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–13
Electrical Characteristics
Table 2–18. Differential I/O Standard Specifications (1) (Part 2 of 2)
(2)
(2)
VCCIO (V)
VID (mV)
VICM (V)
VOD (mV)
VOS (V)
I/O
Standard
Min Typ Max Min Max Min
Condition
Max Min Typ Max Min Typ Max
0
DMAX 500 Mbps 1.85
LVDS
(Column
I/Os)
500 Mbps DMAX
700 Mbps
2.375 2.5 2.625 100
—
0.5
1
1.85 247
1.6
—
600 1.125 1.25 1.35
D
MAX > 700 Mbps
BLVDS
(Row
I/Os)
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
BLVDS
(Column
—
—
—
—
—
—
—
—
(4)
I/Os)
mini-LVDS
(Row
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
—
—
—
—
—
—
—
300
300
600
600
1.0
1.0
0.5
0.5
0.5
0.5
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.5
1.5
1.4
1.4
(5)
I/Os)
mini-LVDS
(Column
—
—
—
—
—
(5)
I/Os)
RSDS
(Row
I/Os)
100 200 600
100 200 600
100 200 600
100 200 600
(5)
RSDS
(Column
(5)
I/Os)
PPDS
(Row
I/Os)
(5)
PPDS
(Column
(5)
I/Os)
Notes to Table 2–18:
(1) For an explanation of the terms used in Table 2–18, refer to “Transmitter Output Waveform” in “Glossary” on page 2–26.
(2) RL range: 90 RL 110 .
(3) The LVPECL input standard is only supported at clock input. The output standard is not supported.
(4) There is no fixed VICM, VOD, and VOS specification for BLVDS. They are dependent on the system topology.
(5) Mini-LVDS, RSDS, and PPDS standards are only supported at output pins of Cyclone III LS devices.
Power Consumption
Use the following methods to estimate power for your design:
■
The Excel-based EPE
■
The Quartus II® PowerPlay power analyzer feature
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–14
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Use the interactive Excel-based EPE before designing your device to get a magnitude
estimate of the device power. The Quartus II PowerPlay power analyzer provides
better quality estimates based on the specifics of the design after place-and-route is
complete. The PowerPlay power analyzer can apply a combination of user-entered,
simulation-derived, and estimated signal activities which, combined with detailed
circuit models, can yield very accurate power estimates.
f
For more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section describes performance characteristics of the core and periphery blocks for
Cyclone III LS devices.
Core Performance Specifications
Table 2–19 through Table 2–25 describe the core performance specifications for
Cyclone III LS devices.
Clock Tree Specifications
Table 2–19 lists the clock tree specifications for Cyclone III LS devices.
Table 2–19. Cyclone III LS Devices Clock Tree Performance
Performance
Device
Unit
C7
C8
I7
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
437.5
437.5
437.5
437.5
402
402
402
402
437.5
437.5
437.5
437.5
MHz
MHz
MHz
MHz
PLL Specifications
Table 2–20 lists the PLL specifications for Cyclone III LS devices when operating in
the commercial junction temperature range (0°C to 85°C) and the industrial junction
temperature range (-40°C to 100°C). For more information about the PLL block, refer
to “PLL Block” in “Glossary” on page 2–26.
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 1 of 2)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
Max
450
325
1300
60
Unit
MHz
MHz
MHz
%
(1)
fIN
fINPFD
Input clock frequency
PFD input frequency
5
(6)
fVCO
PLL internal VCO operating range
600
40
—
—
fINDUTY
Input clock duty cycle
Input clock cycle-to-cycle jitter for FINPFD 100 MHz
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz
0.15
750
UI
(5)
tINJITTER_CCJ
ps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–15
Switching Characteristics
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 2 of 2)
Symbol
Parameter
PLL output frequency
Min
Typ
Max
Unit
fOUT_EXT (external clock
—
—
450
MHz
(1)
output)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
—
—
—
—
450
MHz
MHz
fOUT (to global clock)
402.5
Duty cycle for external clock output (when set to
50%)
tOUTDUTY
tLOCK
45
—
50
—
55
1
%
Time required to lock from end of device
configuration
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
tDLOCK
—
—
1
ms
Dedicated clock output period jitter FOUT 100 MHz
—
—
—
—
300
30
ps
(3)
tOUTJITTER_PERIOD_DEDCLK
FOUT < 100 MHz
mUI
Dedicated clock output cycle-to-cycle jitter
—
—
300
ps
(3)
FOUT 100 MHz
tOUTJITTER_CCJ_DEDCLK
F
OUT < 100 MHz
—
—
—
—
—
—
10
—
—
—
—
—
—
—
30
650
75
mUI
ps
Regular I/O period jitter FOUT 100 MHz
OUT < 100 MHz
Regular I/O cycle-to-cycle jitter FOUT 100 MHz
OUT < 100 MHz
(3)
tOUTJITTER_PERIOD_IO
F
mUI
ps
650
75
(3)
tOUTJITTER_CCJ_IO
F
mUI
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
50
Minimum pulse width on areset signal.
—
ns
scanclk
cycles
(2)
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
—
3.5
—
fSCANCLK
scanclkfrequency
—
100
MHz
Notes to Table 2–20:
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) With 100-MHz scanclkfrequency.
(3) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
(4) VCCD_PLL must be connected to VCCINT through the decoupling capacitor and ferrite bead.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(6) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–16
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Embedded Multiplier Specifications
Table 2–21 lists the embedded multiplier specifications for Cyclone III LS devices.
Table 2–21. Cyclone III LS Devices Embedded Multiplier Specifications
EP3CLS70, EP3CLS100,
Resources Used
EP3CLS150, and EP3CLS200
Performance
Mode
Unit
Number of Multipliers
C7 and I7
300
C8
9 × 9-bit multiplier
1
1
260
200
MHz
MHz
18 × 18-bit multiplier
250
Memory Block Specifications
Table 2–22 lists the M9K memory block and logic element (LE) specifications for
Cyclone III LS devices.
Table 2–22. Cyclone III LS Devices Memory Block Performance Specifications
EP3CLS70, EP3CLS100,
EP3CLS150, and EP3CLS200
Performance
Resources Used
Memory
Mode
Unit
M9K
Memory
LEs
C7 and I7
C8
FIFO 256 × 36
47
0
1
1
1
1
274
274
274
274
238
238
238
238
MHz
MHz
MHz
MHz
Single-port 256 × 36
M9K Block
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
0
0
Configuration and JTAG Specifications
Table 2–23 lists the configuration mode specifications for Cyclone III LS devices.
Table 2–23. Cyclone III LS Devices Configuration Mode Specifications
Programming Mode
Passive Serial (PS)
Fast Passive Parallel (FPP)
DCLK fMAX
133
Unit
MHz
MHz
100
Table 2–24 lists the active configuration mode specifications for Cyclone III LS
devices.
Table 2–24. Cyclone III LS Devices Active Configuration Mode Specifications
Programming Mode
Active Serial (AS)
DCLK Range
Unit
20 to 40
MHz
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–17
Switching Characteristics
Table 2–25 lists the JTAG timing parameters and values for Cyclone III LS devices.
Table 2–25. Cyclone III LS Devices JTAG Timing Parameters (1)
Symbol
tJCP
Parameter
Min
40
20
20
2
Max
—
—
—
—
—
—
16
15
15
—
—
25
25
25
Unit
TCK clock period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
TCK clock low time
tJCL
tJPSU_TDI JTAG port setup time for TDI
tJPSU_TMS JTAG port setup time for TMS
3
tJPH
JTAG port hold time
10
—
—
—
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
Capture register hold time
10
—
—
—
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Notes to Table 2–25:
(1) For more information, refer to “JTAG Waveform” in “Glossary” on page 2–26.
(2) The specification shown is for the 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For the 1.8-V
LVTTL/LVCMOS and the 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several systems interfacing, for example, the high-speed
I/O interface, external memory interface, and PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are
capable of typical 200 MHz interfacing frequency with 10 pF load.
1
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–18
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
High-Speed I/O Specification
Table 2–26 through Table 2–31 list the high-speed I/O timing for Cyclone III LS
devices. For more information about the definitions of high-speed timing
specifications, refer to “Glossary” on page 2–26.
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification (1), (2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
fHSCLK
(input clock
frequency)
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311
311
311
311
311
Device operation
in Mbps
311
311
311
311
311
311
tDUTY
55
55
TCCS
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
CLOAD = 5 pF
(3)
tLOCK
—
ms
Notes to Table 2–26:
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–19
Switching Characteristics
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
85
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
85
5
85
f
HSCLK (input
clock
frequency)
5
85
5
85
5
85
5
85
5
85
5
85
5
170
170
170
170
170
170
170
55
5
170
170
170
170
170
170
170
55
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
Device
operation in
Mbps
tDUTY
TCCS
200
200
ps
Output jitter
(peak to
peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(2)
tLOCK
ms
Notes to Table 2–27:
(1) Emulated RSDS with one-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1), (2) (Part 1 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–20
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1), (2) (Part 2 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
311
311
311
311
311
311
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
311
311
311
311
311
311
55
×10
×8
×7
×4
×2
×1
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
70
70
Device operation
in Mbps
40
40
20
20
10
10
tDUTY
45
45
TCCS
—
200
—
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
LOAD = 5 pF
20 – 80%,
tRISE
500
500
C
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(3)
tLOCK
ms
Notes to Table 2–28:
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
network transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–21
Switching Characteristics
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
370
370
370
370
370
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
740
740
740
740
740
402.5
55
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 2–29:
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 1 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
320
320
320
320
320
Min
5
Max
275
275
275
275
275
402.5
550
550
550
550
550
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
640
640
640
640
640
402.5
55
5
100
80
70
40
20
10
45
100
80
70
40
20
10
45
HSIODR
tDUTY
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–22
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 2 of 2)
C7 and I7
C8
Symbol
TCCS
Modes
Unit
Min
Max
Min
Max
—
—
—
—
200
—
200
ps
ps
Output jitter
(peak to peak)
—
—
500
1
—
—
550
1
(2)
tLOCK
ms
Notes to Table 2–30:
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
370
370
370
370
370
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
400
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
740
5
100
80
70
40
20
10
—
100
80
70
40
20
10
—
740
740
HSIODR
SW
740
740
402.5
400
Input jitter
tolerance
—
—
—
—
500
1
—
—
550
1
ps
ps
(2)
tLOCK
Notes to Table 2–31:
(1) True LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32 and Table 2–33 list the external memory interface specifications for
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–23
Switching Characteristics
f
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side (1)
Column I/Os (ps)
Memory Standard
Row I/Os (ps)
Wraparound Mode (ps)
Setup
Hold
Setup
Hold
Setup
Hold
C7
C8
I7
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
705
675
900
650
620
845
770
795
910
715
740
855
985
970
930
915
1085
1030
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
785
800
720
740
990
930
915
870
855
1115
1185
1210
1055
1125
1150
1050
1065
1005
DDR2 SDRAM
DDR SDRAM
765
745
945
710
690
890
855
880
955
800
825
900
1040
1000
1130
985
945
QDRII SRAM
1075
Note to Table 2–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 1 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory Standard
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
C7
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
915
1025
880
410
545
340
380
450
570
915
1025
880
410
545
340
380
450
570
1015
1125
980
510
645
440
480
550
670
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1010
910
1010
910
1010
1010
1110
1010
1010
C8
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1140
1280
1110
1260
1140
1290
540
700
460
510
590
730
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–24
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 2 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory Standard
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
I7
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
961
1076
924
431
572
357
399
473
599
961
1076
924
431
572
357
399
473
599
1061
1176
1024
1161
1056
1161
531
672
457
499
573
699
DDR2 SDRAM
DDR SDRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1061
956
1061
956
QDRII SRAM
1061
1061
Note to Table 2–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
Table 2–34 lists the Cyclone III LS devices memory ouput clock jitter specifications.
Table 2–34. Cyclone III LS Devices Memory Output Clock Jitter Specifications (1), (2)
Parameter
Clock period jitter
Symbol
tJIT (per)
Min
–125
–200
–150
Max
125
200
150
Unit
ps
Cycle-to-cycle period jitter
Duty cycle jitter
t
JIT (cc)
JIT (duty)
ps
t
ps
Notes to Table 2–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specification
Table 2–35 lists the worst case duty cycle distortion for Cyclone III LS devices.
Table 2–35. Duty Cycle Distortion on Cyclone III LS Devices I/O Pins (1), (2)
C7, I7
C8
Symbol
Output Duty Cycle
Unit
Min
Max
Min
Max
45
55
45
55
%
Notes to Table 2–35:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and I/O element
(IOE) driving the dedicated and general purpose I/O pins.
(2) Cyclone III LS devices meet the DCD specifications at the maximum output toggle rate for each combination of
the I/O standard and current strength.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–25
Switching Characteristics
OCT Calibration Timing Specification
Table 2–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III LS devices.
Table 2–36. Cyclone III LS Devices Timing Specification for Series OCT with Calibration at Device
(1)
Power-Up
Symbol
Description
Maximum
Unit
Duration of series OCT with
calibration at device power-up
tOCTCAL
20
µs
Note to Table 2–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 2–37 and Table 2–38 list the IOE programmable delay for Cyclone III LS devices.
(1), (2)
Table 2–37. Cyclone III LS Devices IOE Programmable Delay on the Column Pins
Max Offset
Slow Corner
C8
Number
of
setting
Min
Offset
Parameter
Paths Affected
Fast Corner
I7 C7
Unit
C7
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
8
2
0
0
0
1.211 1.314 2.339 2.416 2.397
1.203 1.307 2.387 2.540 2.430
0.518 0.559 1.065 1.151 1.082
ns
ns
ns
Input delay from the pin to the
input register
Pad to I/O input
register
Delay from the output register to I/O output
the output pin
register to pad
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
12
0
0.533 0.56 1.077 1.182 1.087
ns
Notes to Table 2–37:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1), (2)
Max Offset
Number
Min
Offset
Parameter
Paths Affected
of
Fast Corner
I7 C7
Slow Corner
C8
Unit
setting
C7
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
8
2
0
0
0
1.209 1.314 2.352 2.514 2.432
1.207 1.312 2.402 2.558 2.447
0.549 0.595 1.135 1.226 1.151
ns
ns
ns
Input delay from the pin to the
input register
Pad to I/O input
register
Delay from the output register to I/O output
the output pin
register to pad
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–26
Chapter 2: Cyclone III LS Device Datasheet
I/O Timing
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1), (2)
Max Offset
Number
Min
Parameter
Paths Affected
of
Fast Corner
I7 C7
Slow Corner
C8
Unit
Offset
setting
C7
I7
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
12
0
0.52 0.54 1.052 1.16 1.061
ns
Notes to Table 2–38:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
I/O Timing
DirectDrive technology and MultiTrack interconnect ensure predictable performance,
accurate simulation, and accurate timing analysis across all Cyclone III LS device
densities and speed grades.
Use the following methods to determine I/O timing:
■
The Excel-based I/O timing
■
The Quartus II Timing Analyzer
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used before designing the FPGA to get a timing
budget estimation as part of the link timing analysis. The Quartus II Timing Analyzer
provides a more accurate and precise I/O timing data based on the specifics of the
design after place-and-route is complete.
f
f
For more information about the Excel-based I/O timing spreadsheet, refer to the
Cyclone III Devices Literature page on the Altera website.
All specifications are representative of worst-case supply voltage and junction
temperature conditions. Altera characterizes timing delays at the worst-case process,
minimum voltage, and maximum temperature for input register setup time (tSU) and
hold time (tH).
For more information about timing delay from the FPGA output to the receiving
device for system-timing analysis, refer to AN 366: Understanding I/O Output Timing
for Altera Devices.
Glossary
Table 2–39 lists the glossary for this chapter.
Table 2–39. Glossary (Part 1 of 6)
Letter
Term
—
Definitions
A
B
C
—
—
—
—
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–27
Glossary
Table 2–39. Glossary (Part 2 of 6)
Letter
Term
—
Definitions
D
E
F
—
—
—
fHSCLK
GCLK
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
G
H
GCLK PLL
HSIODR
Input pin to the global clock network through the PLL.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
VIH
Input Waveforms
for the SSTL
Differential I/O
Standard
I
VSWING
VREF
VIL
TMS
TDI
tJCP
tJPSU_TDI
tJPSU_TMS
tJCH
t JCL
tJPH
TCK
TDO
J
JTAG Waveform
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
K
L
—
—
—
—
—
—
—
—
—
—
M
N
O
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–28
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 3 of 6)
Letter
Term
Definitions
The following block diagram highlights the PLL specification parameters.
CLKOUT Pins
fOUT_EXT
Switchover
CLK
fIN
fINPFD
N
fVCO
VCO
PFD
CP
LF
fOUT
GCLK
Counters
Core Clock
C0..C4
P
Q
PLL Block
Phase tap
M
Key
Reconfigurable in User Mode
—
—
RL
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
Single-Ended Waveform
Positive Channel (p) = V
IH
VID
Negative Channel (n) = V
Ground
IL
V
CM
Receiver Input
Waveform
R
Differential Input Waveform
VID
0 V
VID
p - n
RSKM (Receiver
input skew
margin)
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–29
Glossary
Table 2–39. Glossary (Part 4 of 6)
Letter
Term
Definitions
VCCIO
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
Single-ended
Voltage
referenced I/O
Standard
VOL
VSS
S
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■ The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
■ The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
SW (Sampling
Window)
tC
High-speed receiver and transmitter input and output clock period.
TCCS (Channel-
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
to-channel-skew) including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
tCO
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
tcout
tDUTY
tFALL
tH
Delay from the clock pad to the I/O output register.
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80 to 20%).
Input register hold time.
T
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
tOUTJITTER_IO
tpllcin
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
tpllcout
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–30
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 5 of 6)
Letter
Term
Definitions
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS, and RSDS differential I/O
standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
V
os
Transmitter
Ground
Output Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VOD
0 V
VOD
p − n (1)
tRISE
tSU
Signal low-to-high transition time (20–80%).
Input register setup time.
—
U
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–31
Glossary
Table 2–39. Glossary (Part 6 of 6)
Letter
Term
VCM(DC)
Definitions
DC common mode input voltage.
AC differential Input Voltage—The minimum AC input differential voltage required for
switching.
VDIF(AC)
DC differential Input Voltage—The minimum DC input differential voltage required for
switching.
VDIF(DC)
VICM
Input Common Mode Voltage—The common mode of the differential signal at the receiver.
Input differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
Voltage Input High—The minimum positive voltage applied to the input that is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage.
High-level DC input voltage.
Voltage Input Low—The maximum positive voltage applied to the input that is accepted by
the device as a logic low.
VIL
VIL (AC)
VIL (DC)
VIN
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
Output Common Mode Voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
V
Output differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
Voltage Output High—The maximum positive voltage from an output that the device
considers will be accepted as the minimum positive high level.
VOH
Voltage Output Low—The maximum positive voltage from an output that the device considers
will be accepted as the maximum positive low level.
VOL
VOS
Output offset voltage—VOS = (VOH + VOL) / 2.
AC differential Output cross point voltage—The voltage at which the differential output signals
must cross.
VOX (AC)
VREF
Reference voltage for the SSTL and HSTL I/O standards.
AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise.
VREF (AC)
VREF (DC)
VSWING (AC)
The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC)
.
DC input reference voltage for the SSTL and HSTL I/O standards.
AC differential Input Voltage—AC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
DC differential Input Voltage—DC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
VSWING (DC)
VTT
Termination voltage for the SSTL and HSTL I/O standards.
AC differential Input cross point Voltage—The voltage at which the differential input signals
must cross.
VX (AC)
W
X
Y
Z
—
—
—
—
—
—
—
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–32
Chapter 2: Cyclone III LS Device Datasheet
Document Revision History
Document Revision History
Table 2–40 lists the revision history for this document.
Table 2–40. Document Revision History
Date
Version
Changes
■ Updated minimum fHSCLK value to 5 MHz.
July 2012
1.4
■ Updated absolute maximum TJ to 125 °C in Table 2–1.
■ Finalized all preliminary information.
■ Updated “Supply Current” on page 2–5, “Periphery Performance” on page 2–17, and
“External Memory Interface Specifications” on page 2–22.
December 2011
1.3
■ Updated Table 2–1, Table 2–3, Table 2–13, Table 2–16, Table 2–17, Table 2–20, and
Table 2–25.
■ Updated Table 2–19 through Table 2–34, Table 2–37, and Table 2–38.
■ Updated the “Periphery Performance” on page 2–17 section.
■ Minor changes to the text.
December 2009
1.2
July 2009
June 2009
1.1
1.0
Minor edit to the hyperlinks.
Initial release.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
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