FLLXT3108BE [INTEL]
Digital Transmission Interface, PBGA256;
| 型号： | FLLXT3108BE |
| 厂家： | 
INTEL |
| 描述： | Digital Transmission Interface, PBGA256 |
| 文件： | 总108页 (文件大小：1783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® LXT3108
Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Preliminary Datasheet
The Intel® LXT3108 is an octal 3.3 V Long/Short Haul (LH/SH) T1/E1/J1 Line Interface Unit
(LIU). This flexible LIU allows for the design of T1/E1/J1 LH/SH multi-service cards with a
single design and requires no external component changes and can be configured on a
per-port basis through internal registers. Intel’s proven design makes the LXT3108 the perfect
device for high-density T1/E1/J1 applications. To increase network reliability, the LXT3108
incorporates a DSP-based architecture with features, such as Intel® Hitless Protection Switching
(Intel® HPS) and Intel® Pulse Template Matching (Intel® PTM). The DSP-based architecture is
less sensitive to power supply and temperature variations and allows the LIU to adapt to varying
line conditions. Intel® HPS allows for the design of 1+1 redundant cards without the use of
relays, and has the ability to switch from one card to another, without loss of frame
synchronization. Intel® PTM software allows the transmitter to shape the output pulse to meet
various board conditions, without the need to change any external components.
Applications
■ Voice-over-packet gateways
■ Wireless base stations
■ Integrated Multi-service Access Platforms ■ Routers
(IMAPs)
■ Frame relay access devices
■ Integrated Access Devices (IADs)
■ Inverse multiplexing for ATM (IMA)
■ CSU/DSU equipment
Product Features
■ Intel® HPS for 1+1 protection without
■ On-chip Clock Adaptor (CLAD) that
allows one master clock for T1/E1/J1
applications (1X, 2X, 4X, or 8X T1 or E1
clock)
relays
■ Intel® PTM software for pulse output
adjustment through software without
component or board change
■ 16-bit BPV/Excess Zero counters per port
■ Interfaces with the Intel® IXF3208, Octal
T1/E1/J1 Framer with Intel® On-chip
Performance Report Messaging
(Intel® On-Chip PRM)
■ T1 (100 Ohm), E1 (75 and 120 Ohm), J1
(110 Ohm) termination and LH/SH
selectable per port through software
without component change
■ Receiver sensitivity exceeds 36 dB @ 772
KHz and 38 dB @ 1024 KHz of cable
attenuation providing margin for board and
cable variations
■ B8ZS/HDB3 encoders and decoders, and
unipolar/bipolar I/O modes selectable per
port
■ Digital Jitter Attenuator (DJA) in either
receive or transmit path
■ Will substantially conform to publicly
available specifications in ANSI T1.102,
T1.403, and T1.408; ITU I.431, CTR12/13,
G.703, G.736, G.775, and G.823;
ETSI 300-166 and 300-233; and AT&T
Pub 62411
■ Available in a 17 x 17 mm 256 PBGA
(LXT3108 BE), or 28 x 28 mm 208 QFP
(LXT3108 HE) package
■ 3.3 V power supply with 5 V tolerant
inputs
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT3108 Octal T1/E1/J1 Long/Short Haul Line Interface Unit may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-
4725, or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2003
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Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
Contents
Contents
1.0 Pin Assignments .........................................................................................................................13
2.0 Signal Descriptions .....................................................................................................................15
3.0 Intel® LXT3108 LIU Nomenclature..............................................................................................28
4.0 Functional Description................................................................................................................29
5.0 Port Descriptions.........................................................................................................................31
6.0 Software Support.........................................................................................................................34
7.0 Initialization..................................................................................................................................35
7.1
7.2
CLAD Initialization ..............................................................................................................35
Reset Operation..................................................................................................................35
8.0 Power Supply Requirements......................................................................................................36
8.1
8.2
5 V Tolerant I/O Pins ..........................................................................................................36
Layout Considerations ........................................................................................................36
8.2.1 Ground Plane.........................................................................................................36
8.2.2 Analog Power Supply ............................................................................................37
8.2.3 Digital Power Supply..............................................................................................37
9.0 Transmitter...................................................................................................................................38
9.1
Transmit Line Interface .......................................................................................................39
9.1.1 Transmit Impedance Termination ..........................................................................40
9.1.2 Transmit Return Loss Performance.......................................................................40
9.1.2.1 Intel® Pulse Template Matching (Intel® PTM)........................................41
Transmit Digital Interface....................................................................................................42
9.2.1 Transmit Idle Operation and Three-stating Drivers................................................42
9.2
10.0 Receiver........................................................................................................................................44
10.1 Master Reference Clock .....................................................................................................44
10.2 Receiver Digital Interface....................................................................................................44
10.2.1 Receiver Idle Conditions........................................................................................44
10.3 Receiver Line Interface.......................................................................................................45
10.3.1 Receive Termination Impedance ...........................................................................45
10.3.2 Programming the Intel® LXT3108..........................................................................45
10.3.3 Guidelines for Programming the Intel® LXT3108 Receiver....................................46
10.3.4 Receiver Operation with Transients.......................................................................46
10.3.5 Receiver Sensitivity Programming.........................................................................46
10.3.5.1 Receiver Monitor Mode..........................................................................47
10.4 Receiver Status Information ...............................................................................................48
11.0 Jitter Attenuation (JA).................................................................................................................49
11.1 Digital Jitter Attenuator (DJA) Status..................................................................................49
12.0 Network Control and Maintenance Functions ..........................................................................50
12.1 Diagnostic Modes ...............................................................................................................50
Preliminary Datasheet
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Contents
12.1.1 In-Band Network Loop Up or Down Code Generator/Detector..............................50
12.1.2 Analog Loopback...................................................................................................50
12.1.3 Digital Loopback ....................................................................................................51
12.1.4 Remote Loopback..................................................................................................51
12.1.5 Transmit All Ones (TAOS).....................................................................................52
12.2 Line Coding.........................................................................................................................53
12.2.1 Alternate Mark Inversion (AMI)..............................................................................54
12.2.1.1 Bipolar with Eight Zero Substitution (B8ZS)...........................................54
12.2.1.2 High Density Bipolar Three (HDB3).......................................................55
12.3 Network Maintenance Functions ........................................................................................55
12.3.1 Loss Of Signal (LOS).............................................................................................55
12.3.1.1 Operation of USER LOS with Amplitude Detection ...............................57
12.3.1.2 Operation of USER LOS with Marks Density Detection.........................58
12.3.2 Alarm Indication Signal (AIS).................................................................................58
12.3.3 NLOOP Status.......................................................................................................59
12.3.3.1 T1 AMI/B8ZS BPVs ...............................................................................59
12.3.3.2 E1 AMI/HDB3 BPVs...............................................................................59
12.3.3.3 Excess Zeros (EXZ)...............................................................................60
12.3.4 Monitoring BPV and EXZ Line Coding Violations..................................................60
13.0 Host Interface...............................................................................................................................61
13.1 Supported Processors and Connections............................................................................61
13.1.1 MPC860.................................................................................................................61
13.1.2 M68302* ................................................................................................................62
13.1.3 Intel® i960®/i486TM ................................................................................................62
13.2 Interrupts.............................................................................................................................63
13.2.1 Interrupt Enabling ..................................................................................................63
13.2.2 Interrupt Clearing...................................................................................................63
14.0 Register Definitions.....................................................................................................................65
14.1 Global Registers .................................................................................................................65
14.2 Port Page Register Bank (PPRB).......................................................................................67
15.0 JTAG Boundary Scan..................................................................................................................81
15.1 Architecture.........................................................................................................................81
15.2 TAP Controller....................................................................................................................81
15.3 JTAG Register Description .................................................................................................84
15.3.1 Boundary Scan Register (BSR).............................................................................84
15.3.2 Device Identification Register (IDR).......................................................................84
15.3.3 Bypass Register (BYR)..........................................................................................84
15.3.4 Instruction Register (IR).........................................................................................84
16.0 Test Specifications......................................................................................................................86
16.1 Microprocessor Interface Timing Diagrams........................................................................97
16.2 Referenced Standards......................................................................................................104
17.0 Mechanical Specification..........................................................................................................105
18.0 Glossary.....................................................................................................................................107
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Preliminary Datasheet
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Revision #: 008
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Contents
Figures
1
2
3
4
5
6
7
8
9
Intel® LXT3108 LIU Block Diagram.............................................................................................11
Intel® LXT3108 HE 208 Pin Assignment ....................................................................................13
Intel® LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments........................................14
T1/E1/J1 LIU Block Diagram ......................................................................................................29
Intel® LXT3108 LIU Port Block Diagram.....................................................................................31
Intel® LXT3108 LIU Port Circuit ..................................................................................................32
Transmitter Circuit for Twisted Pair and Coaxial Cable..............................................................33
Diode Protection Network When Inputs Power Up Before Supplies...........................................36
50% AMI Encoding .....................................................................................................................38
10 Typical Transmitter Interface Connections .................................................................................39
11 T1, T1.102 Mask Templates.......................................................................................................41
12 Transmit Interface Timing...........................................................................................................42
13 TCLK Power Down Timing .........................................................................................................43
14 Typical Receiver Interface ..........................................................................................................45
15 Jitter Attenuation Loop ...............................................................................................................49
16 Analog Loopback........................................................................................................................51
17 Digital Loopback .........................................................................................................................51
18 Remote Loopback.......................................................................................................................52
19 TAOS Data Path.........................................................................................................................52
20 TAOS with Digital Loopback.......................................................................................................52
21 TAOS with Analog Loopback......................................................................................................53
22 Interrupt Processing FlowChart ..................................................................................................64
23 Intel® LXT3108 LIU JTAG Architecture.......................................................................................81
24 JTAG State Diagram...................................................................................................................83
25 Transmit Clock Timing Diagram .................................................................................................90
26 Receive Clock Timing Diagram ..................................................................................................92
27 Intel® LXT3108 LIU Output Jitter for CTR12/13 Applications .....................................................93
28 JTAG Timing...............................................................................................................................93
29 E1, G.703 Mask Templates ........................................................................................................94
30 Intel® LXT3108 LIU Jitter Tolerance Performance......................................................................95
31 Intel® LXT3108 LIU Jitter Transfer Performance ........................................................................96
32 MPC860 Write Timing.................................................................................................................97
33 MPC860 Read Timing ................................................................................................................98
34 M68302 Write Timing..................................................................................................................99
35 M68302 Read Timing ...............................................................................................................100
36 Intel® i486TM/i960® Non-muxed Mode Write Timing.................................................................101
37 Intel® i960® Muxed Mode Write Timing ....................................................................................101
38 Intel® i486TM/i960® Non-muxed Mode Read Timing.................................................................102
39 Intel® i960® Muxed Mode Read Timing....................................................................................103
40 Intel® LXT3108 LIU 256 PBGA Mechanical Specification ........................................................105
41 Intel® LXT3108 LIU 208 Pin QFP Mechanical Specifications ..................................................106
Preliminary Datasheet
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Revision #: 008
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Contents
Tables
1
2
3
4
5
6
7
8
9
LXT3108 Pin Description............................................................................................................15
CLAD Initialization Options.........................................................................................................35
Transformer Specifications for the Intel® LXT3108 LIU..............................................................39
Transmit Return Loss Specifications for Frequency Range and Magnitude ..............................40
Powering Down the Transmitter with Static TCLK......................................................................43
Programming Receiver Sensitivity..............................................................................................47
Jitter Attenuation Specifications .................................................................................................49
LOS Criteria for Intel® LXT3108 LIU...........................................................................................56
LOS Register Configurations......................................................................................................56
10 LOS Selection Defaults ..............................................................................................................56
11 AIS Service Condition Variations................................................................................................58
12 Excess Zero (EXZ) Definitions ...................................................................................................60
13 Interfacing the Intel® LXT3108 LIU to the MPC860 Processor...................................................61
14 Interfacing the Intel® LXT3108 LIU to the M68302 Processor....................................................62
15 Intel® i960®/i486TM Mode ...........................................................................................................62
16 Global Register Addresses.........................................................................................................65
17 Port Page Select Register, CPS, 00h.........................................................................................66
18 ID Register, ID, 01h ....................................................................................................................66
19 Interrupt Port Register, ICR, 02h................................................................................................66
20 CLAD Configuration Register1, 11h ...........................................................................................67
21 Port Page Register Bank Addresses..........................................................................................68
22 Port Master Control Page Register, 01h.....................................................................................69
23 Port Receiver Enable Page Register, 02h..................................................................................69
24 Transmit Control Page Register, 03h .........................................................................................70
25 Receive Control Page Register, 04h ..........................................................................................71
26 Termination Control Page Register, 05h ....................................................................................71
27 Receiver Equalizer Status Zero Page Register, 06h ..................................................................71
28 Receiver Equalizer Status One Page Register, 07h...................................................................72
29 Receiver Equalizer Status Two Page Register, 08h...................................................................72
30 LOS Window Page Register, 0Bh ..............................................................................................72
31 LOS Set Threshold One Page Register, 0Ch.............................................................................73
32 LOS Reset Threshold Two Page Register, 0Dh.........................................................................73
33 Loopback Enable Page Register, 10h ........................................................................................74
34 Interrupt Enable Page Register, 11h ..........................................................................................75
35 Alarm Status One Page Register, 12h .......................................................................................76
36 Interrupt Status Two Page Register, 13h ...................................................................................77
37 Line Coding Control One Page Register, 1Ch............................................................................78
38 JA Control Two Page Register, 1Dh...........................................................................................79
39 DJA Corner Frequency Selection ...............................................................................................79
40 BPV Counter High Byte Page Register, 1Eh..............................................................................79
41 BPV Counter Low Byte Page Register, 1Fh...............................................................................79
42 Receiver Activation Logic Control Page Register 33h...............................................................80
43 Receiver Control Page Register 1, 34h......................................................................................80
44 Transmit Coefficient Page Register Range, 40h-6Fh.................................................................80
45 Receiver Control Page Register, 3Ch ........................................................................................80
46 TAP State Description ................................................................................................................81
47 Device Identification Register (IDR) ...........................................................................................84
48 Instruction Register (IR)..............................................................................................................84
49 Absolute Maximum Ratings........................................................................................................86
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Preliminary Datasheet
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Rev. Date: January 08, 2003
Contents
50 Recommended Operating Conditions.........................................................................................86
51 Electrical Characteristics (Over Recommended Operating Conditions).....................................87
52 E1 Transmitter Analog Characteristics .......................................................................................87
53 E1 Receiver Analog Characteristics ...........................................................................................87
54 T1 Transmitter Analog Characteristics .......................................................................................88
55 T1 Receiver Analog Characteristics ...........................................................................................89
56 Master and Transmit Clock Timing Characteristics ....................................................................89
57 Jitter Attenuator Characteristics..................................................................................................91
58 Receive Timing Characteristics for T1 Operation.......................................................................92
59 Receive Timing Characteristics for E1 Operation.......................................................................92
60 JTAG Timing Characteristics......................................................................................................93
61 G.703 2.048 Mbps Pulse Mask Specifications ...........................................................................94
62 T1.102 1.544 Mbps Pulse Mask Specifications..........................................................................94
63 MPC860 Write Timing Characteristics........................................................................................97
64 MPC860 Read Timing Characteristics........................................................................................98
65 M68302 Write Timing Characteristics.........................................................................................99
66 M68302 Read Timing Characteristics.......................................................................................100
67 Intel® i486TM/i960® Write Timing Characteristics......................................................................102
68 Intel® i486TM/i960® Read Timing Characteristics .....................................................................103
Preliminary Datasheet
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Contents
Revision History
Revision #: 008
Revision Date: January 2003
Page #
Description
62
Updated the description in section 13.1.3
Updated Table 45.
Updated Table 51.
80
87
Revision #: 007
Revision Date: October 2002
Page #
Description
1
Updated Product Features.
Updated section: 10.3.2.
Updated section: 10.3.3.
45
46
Revision #: 006
Revision Date: September 2002
Page #
Description
45
46
Added new section: 10.3.2.
Added new sections: 10.3.3 and 10.3.4.
Adjusted Table 6: Maximum Receiver Sensitivity (dB), first four columns were -43, -40, -36,
and -34. Last two columns were 2 and -43.
47
80
Added Table 42.
102
Updated Figure 38.
Revision #: 005
Revision Date: August 2002
Page #
Description
1
2
–
–
–
Receiver sensitivity exceeds 36 dB @ 772 KHz, was 43 dB.
Updated Legal information.
Modified Tables: 2, 5, 7, 9, 10, 18, 19, 20, 21, 23, 24, 25, 26, 27, 31, 32, 34 -38, 43, and 46.
Removed Table 4.
Added Footnote to Table 7.
Modified sections 8.1, 9.22, 10.2, 10.2.1, 11.2.1, 13.2, 13.2.1, 13.2.1.1, 13.3.1, 13.3.1.1,
13.3.1.2, and 13.3.4.
–
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Preliminary Datasheet
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Contents
Revision #: 004
Revision Date: May 2002
Page #
Description
–
–
–
–
Modified Figures: 2, 3, 5, 6, 7, 10, 32, 33, 34, and 35.
Modified Tables: 1, 4, 6, 8, 11, 12, 13, 14, 15, 18, 23, 24, 25, 26, 30, 44, 52, 63, 64, 66.
Modified sections: 3.0, 4.0, 5.0, 6.0, 8.0, 9.0, 9.2, 10.1.2.1, 11.3.1, 11.3.2.1, 14.1.1, 14.1.2.
Added Table 43.
Revision #: 003
Revision Date: January 2002
Page #
Description
–
Modified Figures: 1 - 3, 5 - 7, 10, 14, 15, 32 - 36, and 38.
Modified Tables: 1, 5, 9 - 11, 14 - 18, 20, 22, 23, 26, 29 - 31, 33 - 36, 39, 40, 45, 47, 48, 50 - 55,
61 - 63, 65, and 66.
–
Modified Sections: 8.1, 8.2, 9.0, 9.2.1, 10.1, 10.2, 10.2.1, 10.3.1, 10.3.2, 11.0, 12.1.5, 12.3.2,
12.3.3.1, 12.3.3.2, 12.3.4, 13.0, 13.1, 13.2, 13.2.1, and 16.2.
–
–
Deleted Section: 16.1 and 16.1.1.
Deleted Tables: 58 - 61.
Revision #: 002
Revision Date: January 2001
Page #
Description
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–
–
Modified Pages: 1, 22 - 28, and 30.
Modified Tables: 1, 2, 44 - 53.
Modified Figures: 1-3, 5-7, 10, 11, 15, 26, 38 & 39.
Modified: TOC, LOF and LOT.
Deleted Tables: 58 - 61.
Revision #: 001
Revision Date: January 2001
Page #
Description
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Initial release.
Preliminary Datasheet
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Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 1. Intel® LXT3108 LIU Block Diagram
REMOTE LOOPBACK
DIGITAL LOOPBACK
ANALOG LOOPBACK
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
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Preliminary Datasheet
Document Number: 249543
Revision #: 008
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
1.0
Pin Assignments
Figure 2. Intel® LXT3108 HE 208 Pin Assignment
VCCIO .....53
DVCC .....54
DVSS .....55
AVCC .....56
RRING0 .....57
RTIP0 .....58
AVSS .....59
TXVSS .....60
TXVCC .....61
TVSS .....62
TRING0 .....63
TTIP0 .....64
TVSS .....65
DVSS .....66
DVCC .....67
TVSS .....68
TTIP1 .....69
TRING1 .....70
TVSS .....71
TXVCC .....72
TXVSS .....73
AVSS .....74
RTIP1 .....75
RRING1 .....76
AVCC .....77
DVSS .....78
DVCC .....79
AVCC .....80
RRING2 .....81
RTIP2 .....82
AVSS .....83
TXVSS .....84
TXVCC .....85
TVSS .....86
TRING2 .....87
TTIP2 .....88
TVSS .....89
DVCC .....90
DVSS .....91
TVSS .....92
TTIP3 .....93
TRING3 .....94
TVSS .....95
TXVCC .....96
TXVSS .....97
AVSS .....98
RTIP3 .....99
RRING3 .....100
AVCC .....101
DVSS .....102
DVCC .....103
GNDIO .....104
208..... GNDI0
207..... DVCC
206..... DVSS
205..... AVCC
204..... RRING7
203..... RTIP7
202..... AVSS
201..... TXVSS
200..... TXVCC
199..... TVSS
198..... TRING7
197..... TTIP7
196..... TVSS
195..... DVSS
194..... DVCC
193..... TVSS
192..... TTIP6
191..... TRING6
190..... TVSS
189..... TXVCC
188..... TXVSS
187..... AVSS
186..... RTIP6
185..... RRING6
184..... AVCC
183..... DVSS
182..... DVCC
181..... AVCC
180..... RRING5
179..... RTIP5
178..... AVSS
177..... TXVSS
176..... TXVCC
175..... TVSS
174..... TRING5
173..... TTIP5
172..... TVSS
171..... DVCC
170..... DVSS
169..... TVSS
168..... TTIP4
167..... TRING4
166..... TVSS
165..... TXVCC
164..... TXVSS
163..... AVSS
162..... RTIP4
161..... RRING4
160..... AVCC
159..... DVSS
158..... DVCC
157..... INTR
®
Intel
LXT3108 HE
(Top View)
B0013-01
Preliminary Datasheet
Document Number: 249543
Revision #: 008
13
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 3. Intel® LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments
1
2
3
RRING7
VSS
4
5
6
7
8
9
10 11 12 13 14 15 16
TTIP7
TTIP6 TXVCC AVCC
RRING5 TTIP5
TRING4 TXVCC
AVCC
INTR
A7
DVCC
RW
A4
VCCIO DVCC
TXVCC
TTIP4
TRING5
VSS
RRING4
A
B
C
D
E
F
A
B
C
D
E
F
RPOS7 RNEG7
RTIP7 TRING7 DVCC TRING6
AVCC
TXVCC
DVCC
VSS
VSS
VSS
VSS
DVCC
RDY
VSS
VSS
DS
RTIP4
RTIP6
RTIP5
ALE/
MPI_CLK
VSS
VSS
TPOS7 TNEG7 AVCC
VSS
VSS
RRING6
VSS
VSS
A5
A3
A1
RNEG6
RPOS6
TNEG6
RCLK7
VSS
VSS
VSS
RCLK6
TCLK7
TPOS6
RNEG5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCIO
DB5
A0
DB7
A6
A2
TCLK6 RPOS5
VSS
VSS
VSS
VSS
VSS
VSS
DB6
VCCIO
TNEG5
RCLK5
TPOS5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DB3
DB0
VSS
DB1
OE
RCLK4
VSS
RPOS4
TNEG4
RNEG4 TCLK5
G
H
J
G
H
J
TCLK4 TPOS4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DB4
DB2
VCCIO
VSS
VSS
VSS
RBIAS
GND
VCCIO RCLK3 RNEG3 RPOS3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VMOAT GND
RNEG2 TCLK3 TNEG3
VSS
VSS
TYPE1
LOS5
TPOS3
K
T
K
L
CS
VSS
NC
VSS
VSS
QVCC
MCLK
TYPE2
LOS4
TPOS2
RPOS2 TCLK2
RCLK2
VSS
VSS
VSS
L
VSS
VSS
VSS
LOS6
LOS1
LOS2
TCK
TPOS1 RNEG1 RPOS1
TNEG2
M
N
P
R
T
M
N
P
R
T
RCLK1 RPOS0
RNEG0 RCLK0
VSS
DVCC
VSS
AVCC
LOS7
LOS3
VSS
TNEG1
LOS0
TDI
TCLK1 TNEG0 TCLK0
VSS
VSS
VSS
TXVCC RRING1 AVCC
VSS
TXVCC
VSS
RSTB
DVCC
TDO
VSS
TPOS0 VCCIO
JRST
RRING0
AVCC
TRING2
TXVCC
TXVCC
RTIP0
RTIP2
DVCC
TTIP2
RTIP3
TMS
VSS
TRING0 TTIP1
RTIP1
AVCC
VSS
DVCC
DVCC
DVCC TRING1
TTIP3 TRING3 RRING3
VCCIO
TTIP0
RRING2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
B0014-01
14
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
2.0
Signal Descriptions
Table 1. LXT3108 Pin Description (Sheet 1 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
1
A1
VCCIO
S
Power (I/O)
Receive Positive Data/Receive Data Output (Port 7)
Acts as the positive side of the
bipolar data output pair, RPOS7
and RNEG7, recovered from the
line interface.
RDATA7 digital framer interface pin
acts as a single Non-Return-to-Zero
(NRZ) output of the data recovered
from the line interface.
RPOS7 acts as an active high
Non-Return-to-Zero (NRZ) receive
data output. A High signal on RPOS7
corresponds to receipt of a positive
pulse on RTIP/RRING. A High signal
on RNEG7 corresponds to receipt of
a negative pulse on RTIP/RRING. As
a default, this signal along with
RNEG7 is valid on the falling edge of
RCLK7. The LXT3108 can be
RPOS7/
RDATA7
2
B1
DO
programmed to validate the RPOS7
and RNEG7data on the rising edge of
the RCLK7.
NOTE: This rule applies to all ports
(0 through 7).
Receive Negative Data (Port 7)
This digital framer interface pin acts
as the negative side of the bipolar
data output pair, RPOS7 and
RNEG7, recovered from the
line interface.
RBPV7 indicates a receive BiPolar
Violation (BPV). It goes High on
receipt of a bipolar violation at the
receiver. This is a NRZ output, valid
by default on the falling edge of the
RCLK. The clock edge validating this
signal can be changed from falling
edge to rising edge by software.
RNEG7/
RBPV7
3
B2
DO
RNEG7 acts as an active high NRZ
receive signal output. A High signal
on RNEG7 corresponds to receipt of
a negative pulse on RTIP/RRING.
This signal along with RPOS7 is valid NOTE: This description applies to
on the falling edge of RCLK7. ports 0 through 7.
Receive Clock Output (Port 7): This digital framer interface pin provides the
recovered clock from the signal received at RTIP7 and RRING7. Under LOS
conditions, there is a transition from the RCLK7 signal (derived from the
recovered data) to an internal clock (synthesized from the MCLK signal by
CLock ADapter, or CLAD circuitry) at the RCLK7 output.
4
D5
RCLK7
DO
Preliminary Datasheet
Document Number: 249543
Revision #: 008
15
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 2 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Transmit Positive Data/Transmit Data Input (Port 7)
Digital framer interface pin acts as the TDATA7 acts as a single NRZ data
positive side of the bipolar data input input controlling the signal
pair, TPOS7 and TNEG7, which
controls the signal transmitted to the
line interface.
transmitted to the line interface.
TPOS7 is an active high NRZ input
that operates together with TNEG7.
TPOS7 starts the transmission of a
positive pulse on TTIP7/TRING7,
whereas TNEG7 starts the
TPOS7/
TDATA7
5
C1
DI
transmission of a negative pulse on
TTIP7/TRING7.
TPOS7 TNEG7 Selection
0
1
0
0
Space
Positive Mark
Negative
Mark
0
1
1
1
Space
Transmit Negative Data (Port 7)
This digital framer interface pin acts
as the negative side of the bipolar
data input pair, TPOS7 and TNEG7,
which controls the signal transmitted
to the line interface.
Tie TNEG7 to ground in unipolar
mode.
6
C2
TNEG7
DI
Transmit Clock Input (Port 7)
During normal operation TCLK7 toggles at the line rate, which is 1.544 MHz
for T1/J1 operation, and 2.048 MHz for E1 operation. TPOS7 and TNEG7, or
TDATA7, are sampled on the falling edge of TCLK7.
TCLK
Operating Mode
Clocked Normal operation
Driver outputs three
7
D4
TCLK7
DI
L
stated, but powered on
for redundancy.
Driver outputs three
stated and powered
down for reduced
power draw.
H
NOTE: The Transmit All Ones (TAOS) generator uses MCLK as a timing
reference. To ensure that the output frequency is within specification
limits, MCLK must have the applicable stability.
Receive Positive Data/Receive Data Output (Port 6)
RPOS6 acts as the positive side of
the bipolar data output pair, RPOS6
and RNEG6, recovered from the line line interface.
interface.
RDATA6 acts as a single NRZ output
of the data recovered from the
RPOS6/
RDATA6
8
D3
DO
16
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 3 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Receive Negative Data (Port 6)
RNEG6/
RBPV6
RNEG6 acts as the negative side of
the bipolar data output pair, RPOS6
and RNEG6, recovered from the
line interface.
RBPV6 indicates receive BPV for port
6.
9
D1
DO
Receive Clock Output (Port 6):This digital framer interface pin provides the
recovered clock from the signal received at RTIP6 and RRING6. Under LOS
conditions there is a transition from the RCLK6 signal (derived from the
recovered data) to an internal clock (synthesized from the MCLK signal by
CLAD circuitry) at the RCLK6 output.
10
11
D2
E4
RCLK6
DO
DI
Transmit Positive Data/Transmit Data Input (Port 6)
TPOS6 acts as the positive side of
the bipolar data input pair, TPOS6
TDATA6 acts as a single NRZ input
data controlling the signal transmitted
TPOS6/
TDATA6
and TNEG6, which controls the signal to the line interface.
transmitted to the line interface.
Transmit Negative Data (Port 6)
TNEG6 acts as the negative side of
the bipolar data input pair, TPOS6
and TNEG6, which controls the signal
transmitted to the line interface.
Tie TNEG6 to ground in unipolar
mode.
12
13
14
E3
E1
E2
TNEG6
TCLK6
DI
DI
Transmit Clock Input (Port 6)
Receive Positive Data/Receive Data Output (Port 5)
RPOS5 acts as the positive side of
the bipolar data output pair, RPOS5
and RNEG5, recovered from the line interface.
interface.
RDATA5 acts as a single NRZ output
of the data recovered from the line
RPOS5/
RDATA5
DO
Receive Negative Data (Port 5)
RNEG5/
RBPV5
RNEG5 acts as the negative side of
the bipolar data output pair, RPOS5
and RNEG5, recovered from the line
interface.
RBPV5 indicates Receive BPV for
port 5.
15
16
17
F4
F1
F3
DO
DO
DI
RCLK5
Receive Clock Output (Port 5)
Transmit Positive Data/Transmit Data Input (Port 5)
TPOS5 acts as the positive side of
the bipolar data input pair, TPOS5
and TNEG5, which controls the signal to the line interface.
TDATA5 acts as a single NRZ input
data controlling the signal transmitted
TPOS5/
TDATA5
transmitted to the line interface.
Transmit Negative Data (Port 5)
TNEG5 acts as the negative side of
the bipolar data input pair, TPOS5
and TNEG5, which controls the signal
transmitted to the line interface.
Tie TNEG5 to ground in unipolar
mode.
18
19
20
F2
G4
G1
TNEG5
TCLK5
DI
DI
Transmit Clock Input (Port 5)
Receive Positive Data/Receive Data Output (Port 4)
RPOS4 acts as the positive side of
the bipolar data output pair, RPOS4
and RNEG4, recovered from the
line interface.
RDATA4 acts as a single NRZ output
of the data recovered from the line
interface.
RPOS4/
RDATA4
DO
Preliminary Datasheet
Document Number: 249543
Revision #: 008
17
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 4 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Receive Negative Data (Port 4)
RNEG4/
RBPV4
RNEG4 acts as the negative side of
the bipolar data output pair, RPOS4
and RNEG4, recovered from the line
interface.
RBPV4 indicates Receive BPV for
port 4.
21
22
23
G3
G2
H4
DO
RCLK4
DO Receive Clock Output (Port 4)
Transmit Positive Data/Transmit Data Input (Port 4)
TPOS4 acts as the positive side of
the bipolar data input pair, TPOS4
and TNEG4, which controls the signal to the line interface.
TDATA4 acts as a single NRZ input
data controlling the signal transmitted
TPOS4/
TDATA4
DI
transmitted to the line interface.
Transmit Negative Data (Port 4)
TNEG4 acts as the negative side of
the bipolar data input pair, TPOS4
and TNEG4, which controls the signal
transmitted to the line interface.
Tie TNEG4 to ground in unipolar
mode.
24
H1
TNEG4
DI
25
26
27
H3
H2
J1
TCLK4
GNDIO
VCCIO
DI
S
Transmit Clock Input (Port 4)
Ground (I/O)
S
Power (I/O)
Receive Positive Data/Receive Data Output (Port 3)
RPOS3 acts as the positive side of
the bipolar data output pair, RPOS3
and RNEG3, recovered from the line interface.
interface.
RDATA3 acts as a single NRZ output
of the data recovered from the line
RPOS3/
RDATA3
28
J4
DO
DO
Receive Negative Data (Port 3)
RNEG3/
RBPV3
RNEG3 acts as the negative side of
the bipolar data output pair, RPOS3
and RNEG3, recovered from the
line interface.
This output indicates Receive BPV
for port 3.
29
30
31
J3
J2
K1
RCLK3
DO Receive Clock Output (Port 3)
Transmit Positive Data/Transmit Data Input (Port 3)
TPOS3 acts as the positive side of
the bipolar data input pair, TPOS3
and TNEG3, which controls the signal to the line interface.
TDATA3 acts as a single NRZ input
data controlling the signal transmitted
TPOS3/
TDATA3
DI
transmitted to the line interface.
Transmit Negative Data (Port 3)
TNEG3 acts as the negative side of
the bipolar data input pair, TPOS3
and TNEG3, which controls the signal
transmitted to the line interface.
Tie TNEG3 to ground in unipolar
mode.
32
33
K4
K3
TNEG3
TCLK3
DI
DI
Transmit Clock Input (Port 3)
Receive Positive Data/Receive Data Output (Port 2)
RPOS2 acts as the positive side of
the bipolar data output pair, RPOS2
and RNEG2, recovered from the
line interface.
RDATA2 acts as a single NRZ output
of the data recovered from the
line interface.
RPOS2/
RDATA2
34
L1
DO
18
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 5 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Receive Negative Data (Port 2)
RNEG2/
RBPV2
RNEG2 acts as the negative side of
the bipolar data output pair, RPOS2
and RNEG2, recovered from the line
interface.
This output indicates Receive BPV
for port 2.
35
36
37
K2
L4
L3
DO
DO
DI
RCLK2
Receive Clock Output (Port 2)
Transmit Positive Data/Transmit Data Input (Port 2)
TPOS2 acts as the positive side of
the bipolar data input pair, TPOS2
and TNEG2, which controls the signal to the line interface.
TDATA2 acts as a single NRZ input
data controlling the signal transmitted
TPOS2/
TDATA2
transmitted to the line interface.
Transmit Negative Data (Port 2)
TNEG2 acts as the negative side of
the bipolar data input pair, TPOS2
and TNEG2, which controls the signal
transmitted to the line interface.
Tie TNEG2 to ground in unipolar
mode.
38
39
40
M1
L2
TNEG2
TCLK2
DI
DI
Transmit Clock Input (Port 2)
Receive Positive Data/Receive Data Output (Port 1)
RPOS1 acts as the positive side of
the bipolar data output pair, RPOS1
and RNEG1, recovered from the line line interface.
interface.
RDATA1 acts as a single NRZ output
of the data recovered from the
RPOS1/
RDATA1
M4
DO
Receive Negative Data (Port 1)
RNEG1/
RBPV1
RNEG1 acts as the negative side of
the bipolar data output pair, RPOS1
and RNEG1, recovered from the line
interface.
This output indicates Receive BPV
for port 0.
41
42
43
M3
N1
M2
DO
DO
DI
Receive Clock Output (Port 1): This digital framer interface pin provides the
recovered clock from the signal received at RTIP1 and RRING1. Under LOS
conditions there is a transition from the RCLK1 signal (derived from the
recovered data) to an internal clock (synthesized from the MCLK signal by
CLAD circuitry) at the RCLK1 output.
RCLK1
Transmit Positive Data/Transmit Data Input (Port 1)
TPOS1 acts as the positive side of
the bipolar data input pair, TPOS1
and TNEG1, which controls the signal to the line interface.
TDATA1 acts as a single NRZ input
data controlling the signal transmitted
TPOS1/
TDATA1
transmitted to the line interface.
Transmit Negative Data (Port 1)
TNEG1 acts as the negative side of
the bipolar data input pair, TPOS1
and TNEG1, which controls the signal
transmitted to the line interface.
Tie TNEG1 to ground in unipolar
mode.
44
45
46
N3
P1
N2
TNEG1
TCLK1
DI
DI
Transmit Clock Input (Port 1)
Receive Positive Data/Receive Data Output (Port 0)
RPOS0 acts as the positive side of
the bipolar data output pair, RPOS0
and RNEG0, recovered from the line interface.
interface.
RDATA0 acts as a single NRZ output
of the data recovered from the line
RPOS0/
RDATA0
DO
Preliminary Datasheet
Document Number: 249543
Revision #: 008
19
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 6 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Receive Negative Data (Port 0)
RNEG0/
RBPV0
RNEG0 acts as the negative side of
the bipolar data output pair, RPOS0
and RNEG0, recovered from the line
interface.
This output indicates Receive BPV
for port 0.
47
N4
DO
Receive Clock Output (Port 0): This digital framer interface pin provides the
recovered clock from the signal received at RTIP0 and RRING0. Under LOS
48
49
N5
R1
RCLK0
DO conditions there is a transition from the RCLK0 signal (derived from the
recovered data) to an internal clock (synthesized from the MCLK signal by
CLAD circuitry) at the RCLK0 output.
Transmit Positive Data/Transmit Data Input (Port 0)
TPOS0 acts as the positive side of
the bipolar data input pair, TPOS0
and TNEG0, which controls the signal to the line interface.
TDATA0 acts as a single NRZ input
data controlling the signal transmitted
TPOS0/
TDATA0
DI
DI
transmitted to the line interface.
Transmit Negative Data (Port 0)
TNEG0 acts as the negative side of
the bipolar data input pair, TPOS0
and TNEG0, which controls the signal
transmitted to the line interface.
Tie TNEG0 to ground in unipolar
mode.
50
P2
TNEG0
51
52
53
54
55
56
P3
P4
R2
T1
L6
T3
TCLK0
GNDIO
VCCIO
DVCC
DVSS
AVCC
DI
S
S
S
S
S
Transmit Clock Input (Port 0)
Ground (I/O)
Power (I/O)
Digital Power 3.3 V
Digital Ground
Analog Power 3.3 V
Receive Ring Input (Port 0): RRING0 is one of the pair of inputs, RRING0/
RTIP0, to the differential line receiver at the line interface for the port. Data
and clock are recovered and output at the digital framer interface output pins.
57
58
R3
T4
RRING0
RTIP0
AI
AI
Receive Tip Input (Port 0): RTIP0 is one of the pair of inputs, RRING0/
RTIP0, to the differential line receiver at the line interface for the port. Data
and clock are recovered and output at the digital framer interface output pins.
59
60
61
62
P5
P6
P7
N6
AVSS
TXVSS
TXVCC
TVSS
S
S
S
S
Analog Ground
Transmit Ground: Ground pin for transmit logic.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Driver Ground: Ground pin for the output driver.
Transmit Ring Output (Port 0): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP0/TRING0. TTIP0/TRING0 will be
in a high impedance state if the TCLK pin is static or if the OE pin is Low.
TTIP0/TRING0 can be in a the high impedance state on a port-by-port basis
by writing a ‘1’ to the TXPD bit in “Port Master Control Page Register, 01h” on
page 69, or the OES bit in “Transmit Control Page Register, 03h” on page 70.
Please refer to “Transmit Idle Operation and Three-stating Drivers” on
page 42 for details.
63
64
R5
T5
TRING0
TTIP0
AO
AO
Transmit Tip Output (Port 0): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP0/TRING0.
20
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 7 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
65
66
67
68
N7
T8
T6
N9
TVSS
DVSS
DVCC
TVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Digital Ground
Digital Power 3.3 V
Transmit Driver Ground: Ground pin for the output driver.
Transmit Tip Output (Port 1): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP1/TRING1.
69
70
R6
T7
TTIP1
AO
AO
Transmit Ring Output (Port 1:. This is one of the pair of differential line
driver outputs to the line interface pins, TTIP1/TRING1.
TRING1
71
72
73
74
P10
R4
TVSS
TXVCC
TXVSS
AVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Ground: Ground pin for transmit logic.
Analog Ground
P11
G13
Receive Tip Input (Port 1): RTIP1 is one of the pair of inputs, RRING1/
RTIP1, to the differential line receiver at the line interface for the port.
75
76
R7
P8
RTIP1
AI
AI
Receive Ring Input (port 1): RRING1 is one of the pair of inputs, RRING1/
RTIP1, to the differential line receiver at the line interface for the port.
RRING1
77
78
79
80
P9
N10
R11
R8
AVCC
DVSS
DVCC
AVCC
S
S
S
S
Analog Power 3.3 V
Digital Ground
Digital Power 3.3 V
Analog Power 3.3 V
Receive Ring Input (Port 2): RRING2 is one of the pair of inputs, RRING2/
RTIP2, to the differential line receiver at the line interface for the port.
81
82
T9
R9
RRING2
RTIP2
AI
AI
Receive Tip Input (port 2): RTIP2 is one of the pair of inputs, RRING2/
RTIP2, to the differential line receiver at the line interface for the port.
83
84
85
86
L5
AVSS
TXVSS
TXVCC
TVSS
S
S
S
S
Analog Ground
R12
P12
P13
Transmit Ground: Ground pin for transmit logic.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Driver Ground: Ground pin for the output driver.
Transmit Ring Output (Port 2): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP2/TRING2.
87
88
R10
T11
TRING2
TTIP2
AO
AO
Transmit Tip Output (Port 2): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP2/TRING2.
89
90
91
92
T15
R14
M11
M12
TVSS
DVCC
DVSS
TVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Digital Power 3.3 V
Digital Ground
Transmit Driver Ground: Ground pin for the output driver.
Transmit Tip Output (Port 3): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP3/TRING3.
93
94
T12
T13
TTIP3
AO
AO
Transmit Ring Output (Port 3): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP3/TRING3.
TRING3
Preliminary Datasheet
Document Number: 249543
Revision #: 008
21
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 8 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
95
96
97
98
M10
T10
M7
TVSS
TXVCC
TXVSS
AVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Ground: Ground pin for transmit logic.
Analog Ground
M8
Receive Tip Input (Port 3): RTIP3 is one of the pair of inputs, RRING3/
RTIP3, to the differential line receiver at the line interface for the port.
99
R13
T14
RTIP3
AI
AI
Receive Ring Input (Port 3): RRING3 is one of the pair of inputs, RRING3/
RTIP3, to the differential line receiver at the line interface for the port.
100
RRING3
101
102
103
104
105
N11
M6
N8
AVCC
DVSS
DVCC
GNDIO
VCCIO
S
S
S
S
S
Analog Power 3.3 V
Digital Ground
Digital Power 3.3 V
Ground (I/O)
M5
T16
Power (I/O)
JTAG Controller Reset Input: Input is used to reset the JTAG controller.
JRST should be tied to ground through a 1K resistor if JTAG is not used. For
systems that use JTAG, follow IEEE 1149 standards to initialize this device.
106
107
108
R16
R15
P16
JRST
TMS
TDO
DI
DI
JTAG Test Mode Select Input: Used to control the test logic state machine.
Sampled on rising edge of TCK. TMS is pulled up internally and may be left
disconnected.
JTAG Data Output: During JTAG operation, TDO is Test Data Output for
DO JTAG. Used for reading all serial configuration and test data from internal test
logic. It is updated on falling edge of TCK.
JTAG Data Input: TDI is Test Data input for JTAG. Used for loading serial
109
110
P15
N16
TDI
DI
DI
instructions and data into internal test logic. Sampled on rising edge of TCK.
TDI is pulled up internally and may be left disconnected.
JTAG Clock Input: TCK is clock input for JTAG. Connect to GND when not
used.
TCK
Reset: RSTB is the reset pin for the LXT3108 octal LIU. One microsecond
111
P14
RSTB
DI
after RSTB goes Low, the internal registers will be restored to their default
values.
Loss of Signal Output (Port 0): When the LOS0 output is High, it indicates a
loss of signal at the port’s line interface receiver. LOS goes active after the
incoming signal has insufficient transitions for a specified time interval, which
112
N15
LOS0
DO is determined by the page and global register settings. The LOS condition is
cleared and the output pin returns to Low when the incoming signal has a
sufficient number of transitions in a specified time interval, as determined by
the register settings.
113
114
115
116
117
118
119
N14
M16
N13
M15
L16
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
DO Loss of Signal Output (Port 1)
DO Loss of Signal Output (Port 2)
DO Loss of Signal Output (Port 3)
DO Loss of Signal Output (Port 4)
DO Loss of Signal Output (Port 5)
DO Loss of Signal Output (Port 6)
DO Loss of Signal Output (port 7)
M14
N12
22
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 9 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
120
L15
TYPE2
DI
Microprocessor Type Select Inputs: These pins control which
microprocessor interface is active:
Type2Type1Microprocessor
•
•
•
•
00MPC860, M68360
01i960, i486
121
122
K16
L14
TYPE1
CS
DI
DI
10M68302
11Reserved
Chip Select: This active Low input initiates each access to the parallel
microprocessor interface. For each read or write operation, CS must transition
from High to Low, and remain Low.
Master Clock Input: MCLK is an independent, free-running reference clock.
After initialization the frequency can be set to 8, 4, 2 or 1x of the T1/E1/J1
frequency. Refer to CLAD Configuration Register (Address 11h) for MCLK
frequency selection.
This reference clock is used to generate several internal reference signals:
123
M13
MCLK
DI
•
•
•
•
•
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Generation of RCLK signal during a loss of signal condition.
Reference clock during a blue alarm transmit all ones (TAOS) condition.
Reference timing for the parallel processor wait state generation logic.
124
125
126
K15
J16
K14
GND
GND
Ground
Ground
VMOAT
AI
AI
Substrate Ground
Resistor Bias Input: A 30.1 K Ω, 1% ±100 PPM/°C, resistor must be
connected from this pin to analog ground. The Panasonic ERJ-8ENF3012 V
resistor is recommended.
127
J14
RBIAS
128
129
K13
L13
QVSS
QVCC
AI
AI
Ground for Analog Bias Circuit
Power for Analog Bias Circuit. 3.3 V
Output Driver Enable Input: If this pin is asserted low every port’s analog
driver/transmitter output immediately enters a high impedance state to
support redundancy applications without external mechanical relays. All other
internal circuitry stays active. TTIP and TRING for each port can also be
placed in the high impedance state individually by writing a ‘1’ to the TXPD bit
in “Port Master Control Page Register, 01h” on page 69 or the OES bit in the
“Transmit Control Page Register, 03h” on page 70. Please refer to “Transmit
Idle Operation and Three-stating Drivers” on page 42 for details.
130
H16
OE
DI
131
132
L12
GNDIO
VCCIO
S
S
Ground (I/O)
Power (I/O)
H15
133
134
135
136
H14
G16
J13
DB0
DB1
DB2
DB3
DI/O Data Bus Input/Output. When a non-multiplexed microprocessor interface is
selected, these pins function as a bi-directional 8-bit data bus. When a
multiplexed microprocessor interface is selected, these pins carry both
bi-directional 8-bit data and address inputs A0-A7.
DI/O
DI/O
G14
DI/O
137
138
J15
F16
GNDIO
VCCIO
S
S
Ground (I/O)
Power (I/O)
Preliminary Datasheet
Document Number: 249543
Revision #: 008
23
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 10 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
139
140
141
142
H13
F14
F15
E16
DB4
DB5
DB6
DB7
DI/O Data Bus Input/Output: When a non-multiplexed microprocessor interface is
selected, these pins function as a bi-directional 8-bit data bus. When a
multiplexed microprocessor interface is selected, these pins carry both bi-
directional 8-bit data and address inputs A0 -A7.
DI/O
DI/O
DI/O
143
144
G15
E14
GNDIO
VCCIO
S
S
Ground (I/O)
Power (I/O)
145
146
147
148
149
150
151
152
E15
D16
F13
D15
C16
D14
E13
C15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
DI
DI
DI
DI
DI
DI
DI
DI
Address Bus Input: In non-multiplexed mode these inputs function as
address input pins for the microprocessor bus.
RW has one of two functions depending on the microprocessor interface
selected by the TYPE1 and TYPE2 inputs.
153
154
B16
D13
RW
DS
DI
•
•
Read/Write Input (Motorola Mode).
Write Enable Active Low Input (Intel mode).
DS has one of two functions depending on the microprocessor interface
selected by the TYPE1 and TYPE2 inputs.
DII
•
•
Data Strobe Input (Motorola Mode).
Read Enable Active Low Input (Intel mode)
RDY has one of two functions depending on the microprocessor interface
selected by the TYPE1 and TYPE2 inputs.
•
•
Data Transfer Acknowledge Output. (Motorola Mode).
Ready Output (Intel mode).
155
D12
RDY
DO
A Low signal on RDY during a read operation indicates that the information on
the data bus is valid. A Low signal during a write operation acknowledges that
a data transfer into the addressed register has been accepted (acknowledge
signal).
This pin has one of two functions depending on the microprocessor interface
selected by the TYPE1 and TYPE2 inputs.
Microprocessor Clock (Intel i486 Mode and Mot 860 mode).
MPI_CLK/
ALE
•
MPI_CLK is used to input the microprocessor clock in the synchronous
i486/ i960 and Mot 860 mode.
156
157
C14
B15
DI
Address Latch Enable Input (Intel Mode).
•
The address on the multiplexed address/data bus is clocked into the
device with the falling edge of ALE.
Interrupt: This is an active Low output. If the corresponding interrupt enable
bit is enabled, INTR goes Low to flag the microprocessor when the LXT3108
changes state (see details in the interrupt handling section). The
microprocessor interrupt input should be set to level triggering.
INTR
DO
158
159
160
A16
E12
A15
DVCC
DVSS
AVCC
S
S
S
Digital Power 3.3 V
Digital Ground
Analog Power 3.3 V
24
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 11 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Receive Ring Input (Port 4): RRING4 is one of the pair of inputs, RRING4/
RTIP4, to the differential line receiver at the line interface for the port.
161
162
A14
B14
RRING4
RTIP4
AI
AI
Receive Tip Input (Port 4). RTIP4 is one of the pair of inputs, RRING4/RTIP4,
to the differential line receiver at the line interface for the port.
163
164
165
166
C13
D11
A13
B13
AVSS
TXVSS
TXVCC
TVSS
S
S
S
S
Analog Ground
Transmit Ground: Ground pin for transmit logic.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Driver Ground. Ground pin for the output driver.
Transmit Ring Output (Port 4): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP4/TRING4.
167
168
A12
A11
TRING4
TTIP4
AO
AO
Transmit Tip Output (Port 4): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP4/TRING4.
169
170
171
172
B12
C11
C12
D10
TVSS
DVSS
DVCC
TVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Digital Ground
Digital Power 3.3 V
Transmit Driver Ground: Ground pin for the output driver.
Transmit Tip Output (Port 5): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP5/TRING5.
173
174
A10
B11
TTIP5
AO
AO
Transmit Ring Output (Port 5): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP5/TRING5.
TRING5
175
176
177
178
E10
A7
TVSS
TXVCC
TXVSS
AVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Ground. Ground pin for transmit logic.
Analog Ground
B10
C10
Receive Tip Input (Port 5): RTIP5 is one of the pair of inputs, RRING5/
RTIP5, to the differential line receiver at the line interface for the port.
179
180
C8
A9
RTIP5
AI
AI
Receive Ring Input (Port 5): RRING5 is one of the pair of inputs, RRING5/
RTIP5, to the differential line receiver at the line interface for the port.
RRING5
181
182
183
184
A8
B6
D6
B9
AVCC
DVCC
DVSS
AVCC
S
S
S
S
Analog Power 3.3 V
Digital Power 3.3 V
Digital Ground
Analog Power 3.3 V
Receive Ring Input (Port 6): RRING6 is one of the pair of inputs, RRING6/
RTIP6, to the differential line receiver at the line interface for the port.
185
186
C7
B8
RRING6
RTIP6
AI
AI
Receive Tip Input (Port 6): RTIP6 is one of the pair of inputs, RRING6/
RTIP6, to the differential line receiver at the line interface for the port.
187
188
189
190
D7
E6
C9
B3
AVSS
TXVSS
TXVCC
TVSS
S
S
S
S
Analog Ground
Transmit Ground: Ground pin for transmit logic.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Driver Ground: Ground pin for the output driver.
Preliminary Datasheet
Document Number: 249543
Revision #: 008
25
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 12 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Unipolar Mode
Transmit Ring Output (Port 6): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP6/TRING6.
191
192
B7
A6
TRING6
TTIP6
AO
AO
Transmit Tip Output (Port 6): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP6/TRING6.
193
194
195
196
C4
A2
C5
C6
TVSS
DVCC
DVSS
TVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Digital Power 3.3 V
Digital Ground
Transmit Driver Ground: Ground pin for the output driver.
Transmit Tip Output (Port 7): This is one of the pair of differential line driver
outputs to the line interface pins, TTIP7/TRING7.
197
198
A5
B5
TTIP7
AO
AO
Transmit Ring Output (Port 7): This is one of the pair of differential line
driver outputs to the line interface pins, TTIP7/TRING7.
TRING7
199
200
201
202
E5
A4
E8
E7
TVSS
TXVCC
TXVSS
AVSS
S
S
S
S
Transmit Driver Ground: Ground pin for the output driver.
Transmit Power Supply: Power supply pin for the transmit logic, 3.3 V.
Transmit Ground: Ground pin for transmit logic.
Analog Ground
Receive Tip Input (Port 7): RTIP7 is one of the pair of inputs, RRING7/
RTIP7, to the differential line receiver at the line interface for the port.
203
204
B4
A3
RTIP7
AI
AI
Receive Ring Input (Port 7): RRING7 is one of the pair of inputs, RRING7/
RTIP7, to the differential line receiver at the line interface for the port.
RRING7
205
206
207
208
C3
E9
AVCC
DVSS
DVCC
GNDIO
S
S
S
S
Analog Power 3.3 V
Digital Ground
D9
Digital Power 3.3 V
Ground (I/O)
E11
26
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 1. LXT3108 Pin Description (Sheet 13 of 13)
Description
QFP
PBGA
Symbol
I/O
Bipolar Mode
Digital Power 3.3 V
Unipolar Mode
T2
DVCC
S
M9
This Pin Must be Left Floating
Ground
D8, F5,
F6, F7,
F8, F9,
F10, F11,
F12, G5,
G6, G7,
G8, G9,
G10,
G11,
G12, H5,
H6, H7,
H8, H9,
H10,
VSS
S
H11,
H12, J5,
J6, J7,
J8, J9,
J10, J11,
J12, K5,
K6, K7,
K8, K9,
K10,K11,
K12, L7,
L8, L9,
L10, L11,
M8
Preliminary Datasheet
Document Number: 249543
Revision #: 008
27
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
3.0
Intel® LXT3108 LIU Nomenclature
The Intel® LXT3108 LIU is an octal device that supports up to eight T1/E1/J1 ports, which are
numbered sequentially, beginning with zero (0) and ending with seven (7). In addition, a port is
defined as the standard 4-wire receive/transmit pair of a T1/E1/J1 interface; port and channel are
used interchangeably in this document, and all related documents.
28
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
4.0
Functional Description
Each port consists of a transmitter and a receiver with a jitter attenuator switched between each
path. Access to the host device is through a microprocessor parallel interface, configured in either
Intel® or Motorola* mode. JTAG built-in test chains enable on-board verification of digital pins
and functions.
Figure 4. T1/E1/J1 LIU Block Diagram
TCLK
Transmit PLL
TTIP
TRING
TPOS
TNEG
Transmit DAC
Transmit DSP/Control
Analog
Loopback
Switchable
DJA
Remote
Loopback
RPOS
RNEG
RCLK
Internal
Line
Termination
RTIP
Analog
Noise
Filter
Line
Equalizer
Timing/Data
Recovery
ADC
AGC
RRING
Clock
Generator
MCLK
ENABLE
LOS
Activation/
Control Logic
LOS
Each of the eight transmitters consists of:
• A current mode output driver
• A second-order charge pump Phase Lock Loop (PLL)
• A simple digital Finite Infinite Response (FIR) filter
• A switched-current Digital to Analog Converter (DAC)
Each of the eight receivers’ Analog Front Ends (AFE) consists of:
• An Automatic Gain Control (AGC) amplifier
• An anti-aliasing filter
• An Analog to Digital Converter (ADC)
Preliminary Datasheet
Document Number: 249543
Revision #: 008
29
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
The digital section consists of:
• A digital noise filter
• A root-f equalizer
• A decision feedback equalizer
• A timing recovery
• An adaptation control logic, as shown in Figure 4 on page 29.
Note: A ROM is used to store coefficients and settings for the receiver digital filters.
The programmer controls overall device operation of the LXT3108 LIU through global registers.
Each individual LIU is separately controlled by a set of Port Page Registers (PPRs). There are eight
sets of PPRs, one for each port. However, it is also possible to write to all ports at the same time in
the case where all ports need to be set up with the same configuration.
The LXT3108 LIU jitter attenuator enhances compatibility with the existing network by complying
with jitter control standards The jitter performance of the LXT3108 LIU conforms to the stringent
specifications of AT&T* Pub. 62411 and ITU* TBR12/13. The jitter attenuator is completely
digital and does not require an external crystal. The LXT3108 LIU has the capability to insert a
Jitter Attenuator (JA) in either the transmit or receive data path individually for each port.
30
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
5.0
Port Descriptions
The Intel® LXT3108 LIU is a port-by-port programmable, fully integrated eight-port with jitter
attenuator, as well as network control and maintenance functions. Each LXT3108 LIU port is
suitable for mixed LH or SH, T1/E1/J1 telecommunications applications allowing full-duplex
transmission of digital data over existing cable installations. Under microprocessor control and
with a single MCLK source, each port can individually operate:
• At either T1/J1 or E1 line rates
• At separate line termination impedance settings
• With default or programmable transmit signal
• With preset or customized receiver sensitivity
• With the jitter attenuator in either the transmit or receive path, or disabled
• With or without zero (0) suppression line coding
Figure 5. Intel® LXT3108 LIU Port Block Diagram
Transmitter
TCLK
TPOS
TNEG
TTIP
TRING
JA*
Network Control and
Maintenance
RCLK
RPOS
RNEG
RTIP
RRING
Receiver
*Jitter Attenuator in either
transmitter or receiver path.
Can be disabled.
An eight-bit wide data bus conveys commands from a microprocessor to each port individually, or
to all ports at the same time by a two-step process.
1. Writing the port number to the global register described in Table 17, “Port Page Select
Register, CPS, 00h” on page 66 chooses the port.
2. The next read or write operation can then reach one of the 32 Port Page Registers (PPRs)
adjusting preset port parameters. Besides the PPRs, the designer can also access 48 ATWG
registers, as described in Table 44, “Transmit Coefficient Page Register Range, 40h-6Fh” on
page 80.
Preliminary Datasheet
Document Number: 249543
Revision #: 008
31
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
The LXT3108 LIU is fully T1/E1/J1 selectable without the need to change any external
components for twisted pair applications, allowing the development of a single board design to
support T1 and E1 designs. The J1 line rate and transformer configuration are the same for T1 and
J1 cable.
The line interface to the cables is through standard T1 and E1 telecommunications transformers
and resistors. Each front-end interfaces with two twisted pairs: one pair for transmit, and one pair
for receive. These two pairs comprise a digital data loop for full duplex operation.
Figure 6. Intel® LXT3108 LIU Port Circuit
VCC
Intel®
1 CT:1
TTIP
LXT3108
Port
C1
100pF
Tx Line
R1
1KΩ
1
TRING
1 CT:1
RTIP
Rx Line
121 Ω
RRING
A9933-01
1. Actual values of R1 and C1 may vary depending on design.
Framed or unframed data clocked by TCLK to TPOS/TNEG or TDATA inputs activates the
wave-shaping and line driver circuits. The port’s transmitter will drive T1 or E1 lines from TTIP
and TRING pins out to standard telecommunications T1 or E1 transformers. The line driver can
handle both LH and SH lines for T1/E1/J1.
Preset and programmable pulse shaping suits both LH and SH environments. Each port provides
eight built-in equalization settings for SH applications and six line build outs for LH applications.
In addition, the Intel® PTM software allows the transmitter performance to be tuned for a wide
variety of line conditions or special applications. The PTM software provides eight bits of
amplitude resolution and either 15 (T1) or 16 (E1) phases of time resolution for up to three Unit
Intervals (UI). The combination of proven preset wave-shaping settings and the PTM software
means the designer has increased flexibility in meeting the design challenges of copper interfaces.
A simplified transmitter circuit configuration offers:
• Port-by-port programmable line impedance matching.
• Reduced port component count.
• Current limiting for short-circuits.
By programming the internal transmitter termination, matching the line impedance requires no
component changes for twisted pair and coaxial cable applications, as shown in Figure 7.
32
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 7. Transmitter Circuit for Twisted Pair and Coaxial Cable
Tx Line
75 Ω
VCC
1
TTIP
C1
100 pF
R1
1KΩ
100 / 120 Ω
TRING
1 CT:1:0.8
A9934-01
NOTE: 1. Actual values of R1 and C1 may vary depending on design.
Trimming each port’s transmitter circuit components to a single transformer and a capacitor
increases design flexibility. The transmitter’s current mode driver is self-limiting to provide
built-in short circuit protection. Efficient and flexible line circuit configuration increases designer
options and maintains line protection.
A single mandatory clock reference, MCLK, shared between all eight clock recovery circuits,
enables each receiver in the Intel® LXT3108 LIU to recover the clock and data signals from the
line interface. When selected, after smoothing the recovered signals through the jitter attenuator,
RCLK clocks out RDATA or RPOS/RNEG at the port’s digital framer interface. Each port’s
receiver dynamic range is from 0 to -36 dB for E1 operation and 0 to -36 dB for T1 operation. This
translates to cable reach of at least 2.1 kilometers on 0.63 mm cables (E1) and at least 6000 feet on
22 AWG cables (T1).
The analog AMI waveform from the E1, T1, or J1 line is transformer-coupled into the port’s RTIP
and RRING pins through the LXT3108 LIU’s internal receive termination. This programmable
input termination can select between 100, 110, or 120 Ω applications, eliminating the need to
change external components for twisted-pair cable. The designer has the option of selecting by
software the internal receive line termination, or bypassing this option with external terminating
resistors (see Figure 7 for operating 75 Ω cable for more information).
Preliminary Datasheet
Document Number: 249543
Revision #: 008
33
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
6.0
Software Support
The Intel® LXT3108 LIU comes with a complete set of software support. The various software
modules allow the user to:
• Configure the device through a Graphical User Interface (GUI)—The Intel® LXT3108
LIU GUI software allows you to configure the LXT3108 LIU without having to worry about
which bits to set in a particular register. Configuration of the LXT3108 LIU can be
accomplished by a series of mouse clicks within the GUI. Configurations can be saved as a
series of LXT3108 LIU API messages, which can be used by client applications. Additionally,
the LXT3108 LIU GUI allows the user to monitor the performance of the device, as well as
poll the interrupts.
• Develop customized applications using the LXT3108 LIU Application Programming
Interface (API)—The LXT3108 LIU API is an open source, ANSI C standard library that
allows you to develop custom applications for communicating with the device. Programming
with the API improves development time by relieving the programmer of having to know the
register specifics of the LXT3108 LIU. The LXT3108 LIU API complies with the Intel® IXA
architecture for compatibility with other Intel® communication building blocks.
• Fine-tune the pulse shape of the device using the Intel® Pulse Template Matching
(Intel® PTM) software—The Intel® PTM software provides a graphical view of the
transmitting pulse shape (T1, J1 or E1) that the LXT3108 LIU generates. PTM allows you to
adjust the pulse shape to fit its respective template, without having to manually manipulate
register settings. The PTM software, through the use of graphical controls, automatically
adjusts the register settings of the LXT3108 LIU. This simplifies the process of fine-tuning the
pulse shape and leads to faster development time.
34
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
7.0
Initialization
During power up, the Power-On-Reset (POR) circuit initiates a reset sequence after the power
supply reaches threshold of approximately 60% of V . On crossing this threshold, the device
CC
begins a 32 ms reset cycle to calibrate internal phase lock loops. During power-up, an internal
reset, resets all register default values, status, and state machines for Loss of Signal (LOS) and AIS.
Note: MCLK is mandatory and must be present at power on for chip operation.
7.1
CLAD Initialization
As a first step after the LXT3108 has powered up, it is required to initialize the CLAD
Configuration Register (Addr: 0x11). The value written into this register depends on the frequency
of the MCLK input signal. The following table can be used for programming the CLAD register
(refer to Table 20, “CLAD Configuration Register1, 11h” on page 67).
Table 2. CLAD Initialization Options
MCLK Input1
Value to be written to CLAD (Addr: 0x11) after power on reset.
8x E1 clock
4x E1 clock
2x E1 clock
1x E1 clock
8x T1 clock
4x T1 clock
2x T1 clock
1x T1 clock
80h
88h
84h
8Ch
90h
98h
94h
9Ch
1. E1 clock is 2.048 MHz and T1 clock is 1.544 MHz.
7.2
Reset Operation
The Intel® LXT3108 LIU can be reset in two ways:
1. Writing to the reset bit as shown in the “Port Page Select Register, CPS, 00h” on page 66. This
soft reset initiates a 32 ms reset cycle.
2. Asserting the reset pin RSTB low—The reset pulse width must be a minimum of 1 ms. It is
recommended to wait for another 32 ms after the reset pulse is de-asserted before performing
any read/write access to the port registers. The operation sets all LXT3108 registers to their
default values, including the CLAD Configuration Register1, 11h on page 67.
Caution: During the reset cycle, users should not access the internal registers (register values are undefined).
Furthermore, the reset bit does not initialize the CLAD Configuration Register1, 11h on page 67.
Preliminary Datasheet
Document Number: 249543
Revision #: 008
35
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
8.0
Power Supply Requirements
8.1
5 V Tolerant I/O Pins
All digital input pins will tolerate 5.0 volts and are compatible with TTL logic. The 5.0 V-tolerance
of the Intel® LXT3108 LIU is only applicable when the 3.3 V (nominal) supplies are present.
Caution: Keep digital input pins less than 2 volts above the analog and digital supplies. In addition, external
devices such as pull-up resistors, TTL logic, microprocessors, and system-bus peripherals are
potential sources of 5 V signals to the digital pins. Power-cycling and power-supply failure can
potentially cause situations where the Intel® LXT3108 LIU is powered down, while external 5 V
devices are powered up. When the power supply is not guaranteed to prevent this situation, a diode
network can be used as shown in Figure 8. The diodes must be capable of handling the entire load
capacity of either the 3.3 V or 5 V supply, whichever is greater.
Figure 8. Diode Protection Network When Inputs Power Up Before Supplies
5 V Supply
3.3 V Supply
Should the 5 V supply fail, it be will held up to around 2.6 V by the 3.3 V supply. In the event that
the 3.3 V supply fails, it will be held up to around 2.9 V by the 5 V supply. Each of these conditions
is safe for the 5 V tolerant pins.
8.2
Layout Considerations
This section identifies recommended practice for layout and decoupling of power and ground
planes.
Caution: Long-term reliability of this device might be compromised when these guidelines are not followed.
8.2.1
Ground Plane
Connect all ground pins to a solid ground plane with the shortest possible path to minimize
inductive effects. All pins with names containing: GND, VSS, or SUB are ground pins. Also,
connect the VMOAT pin to the ground plane.
36
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
8.2.2
Analog Power Supply
The analog supply pins listed below require a 3.3 V (nominal) supply, which should be filtered
separately from the digital supply:
• TXVCC
• AVCC
• QVCC
Connect all analog pins to a wide PCB trace, and connect one end of the PCB trace to the power
plane. Bypass capacitors from the ground plane to the analog supply trace should be placed as close
as possible to the following pins:
• A 0.082 µF capacitor between each TXVCC pin and ground.
• A 0.082 µF capacitor between each AVCC pin and ground.
• A 0.082 µF capacitor between each DVCC pin and ground.
Caution: To prevent excessive current through the device, due to one of the supplies failing or sequential
power-cycling, connect back to the original analog and digital power sources (your original power
supply).
8.2.3
Digital Power Supply
Connect digital power supply pins, I/O power, and DVCC to a solid power plane with the shortest
possible path. Place four 0.01 µF bypass capacitors, one per side (as close as possible) to the Intel®
LXT3108 LIU to filter the ground and power planes of the circuit board. In addition, the circuit
board must contain 10 µF tantalum and 0.01 µF ceramic capacitors where power is supplied to the
board.
Caution: To prevent excessive current through the device, due to one of the supplies failing or
sequential power-cycling, connect back to the original analog and digital power sources (your
original power).
Preliminary Datasheet
Document Number: 249543
Revision #: 008
37
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
9.0
Transmitter
Each of the eight ports’ transmitters offers several features when interfacing with the framer
device’s port transmitter signals TCLK and TDATA or TPOS/TNEG. With TCLK clocking at the
line rate and TDATA or TPOS/TNEG carrying digital traffic, the line driver will output a T1/E1/J1
signal through a center tapped 1:1 transformer to the transmit cable pair.
The eight low-power transmitters of the LXT3108 LIU are identical. Along with fourteen
pre-programmed pulse shapes, as shown in Table 24, “Transmit Control Page Register, 03h” on
page 70, the designer may choose the PTM software to tailor pulse shapes to the application. The
PTM implements 48 8-bit registers described in Table 44, “Transmit Coefficient Page Register
Range, 40h-6Fh” on page 80 that customizes the AMI transmit waveform. The user must assert bit
zero, ATWG_EN, of Transmit Control Page Register, 03h on page 70, to enable this feature.
The analog current driver uses programmable internal resistive feedback to synthesize an output
impedance of either 100, 110, or 120 Ω for twisted-pair applications. The impedance is
programmable through the port page register in Table 26, “Termination Control Page Register,
05h” on page 71. When TCLK is not supplied, the transmitter remains powered down and the
TTIP/TRING outputs are held in a high impedance state. All eight transmitters can be
simultaneously three-stated by setting the OE pin low. Also, the programmer can set the port’s
output enable control bit to individually three-state port transmitters as shown in “Transmit
Control Page Register, 03h” on page 70. Please refer to Section 9.2.1, “Transmit Idle Operation and
Three-stating Drivers” on page 42 for more details.
Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA
in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O
is selected by setting the appropriate bits, as described in Table 37, “Line Coding Control One Page
Register, 1Ch” on page 78. The transmitter samples TPOS/TNEG or TDATA inputs on the falling
edge of TCLK. Refer to the Test Specifications Section, Table 56, “Master and Transmit Clock
Timing Characteristics” on page 89, for MCLK and TCLK timing characteristics.
Figure 9. 50% AMI Encoding
TTIP
Bit Cell
1
1
0
TRING
38
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
9.1
Transmit Line Interface
Each of the eight transmitters has pre-programmed and preset pulse shapes suited for driving T1
and E1 twisted-pair cables in LH or SH applications. The signal from TTIP and TRING of each
port is coupled to a 1:1 center-tapped transformer, as shown in Figure 10.
Figure 10. Typical Transmitter Interface Connections
VCC
1 CT:1
TTIP
Tx Line
1
C1
100pF
R1
1KΩ
TRING
A9935-01
NOTE:
1. Actual values of R1 and C1 may vary depending on design.
The 1:1 center-tapped transformer is readily available in many packages, as shown in Table 3.
Table 3. Transformer Specifications for the Intel® LXT3108 LIU
Primary
Inductance
µH
Leakage
Inductance
µH
Interwinding
Capacitance
pF
Dielectric1
Breakdown
V
DCR
Ω
(maximum)
Frequency
MHz
Tx/Rx
Turns Ratio
(minimum)
(max)
(max)
(minimum)
0.70 pri
1.20 sec
2
Tx
Rx
1.544/2.048
1.544/2.048
1 CT:1
1:1
600
600
0.80
1.10
60
60
1500 VRMS
1.10 pri
1.10 sec
2
1500 VRMS
1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage.
2. Some applications require transformers with center tap on the line side of the transformer (LH applications with DC current in
the E1/T1 loop).
Programmers can control the following from the Port Page Register Bank:
• Matching line impedance of the transmitter in, as described in “Termination Control Page
Register, 05h” on page 71.
• LH or SH pulse shape, as described in “Transmit Control Page Register, 03h” on page 70.
• T1 or E1 port line clock rate, as described in “Port Master Control Page Register, 01h” on
page 69.
Preliminary Datasheet
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Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
9.1.1
Transmit Impedance Termination
The Intel® LXT3108 LIU’s transmitter will synthesize its output impedance to match either a 100
Ω, a 110 Ω, or a 120 Ω line as set by the TXTERM bits in “Termination Control Page Register,
05h” on page 71.
Note: For 75 Ω E1 coax applications, set the termination to 120 Ω and use a 1 CT: 0.8 transformer. Refer
to Figure 7 for more information.
Preset pulse shaping controls the transmit pulse equalization to determine the transmitted pulse
shape as shown in Table 24, “Transmit Control Page Register, 03h” on page 70. For the port to
accurately produce the desired pulse, software must:
• Set T1 or E1 line clock rate in Port Master Control Page Register, 01h.
• Set transmit line termination in Termination Control Page Register, 05h.
• Load preset pulse shape setting in Transmit Control Page Register, 03h.
9.1.2
Transmit Return Loss Performance
The LXT3108 LIU transmitter will meet the applicable standard for transmit return loss, but there
are several requirements. Because transmit return loss depends on the match between transmitter
circuit output impedance and the characteristic cable impedance, ITU limits the reflections due to
mismatch by specifying minimum transmit return loss. Currently, ANSI currently does not specify
this parameter. To compare T1 performance to E1 performance, the ITU standard is adapted to
show a similar T1 minimum return loss. This is a benchmark that might be suitable for some T1
applications.
By appropriate software control of the internal transmit impedance in Termination Control Page
Register, 05h, the transmit return loss will be maximized. There are two standards that can be
checked for minimum transmit return loss:
• E1 line rate, ITU G.703 recommends ETSI 300166.
• T1 line rate, 0 dB is the standard; however, ETSI 300166 can be adapted to 1.544 MHz, as
shown in Table 4.
Table 4. Transmit Return Loss Specifications for Frequency Range and Magnitude
Transmit Return Loss
Frequency
T1/E1
Actual
Performance
(in dB)
Band
ETS 300 166
Notes
51-102 KHz
16
9
6 dB
8 dB
ITU G.703
specification
102-2048 KHz
E1
T1
Test with 215-1
2048 - 3072 KHz
9
8 dB
HDB3 encoded
signal pattern
39-77 KHz
77-1544 KHz
15
12
9
6 dB
8 dB
8 dB
Test with QRSS
pattern.
1544 - 2316 KHz
40
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 11. T1, T1.102 Mask Templates
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-1.00
-0.50
0.00
0.50
1.00
1.50
-0.20
-0.40
-0.60
Time [UI]
9.1.2.1
Intel® Pulse Template Matching (Intel® PTM)
Each transmit baud, or UI is divided into either 16 (E1) or 15 (T1) sub-phases. The pulse amplitude
during each phase is described by an 8-bit, 2’s complement, byte. Thus, each pulse can be
described with a timing resolution of T/16 and an amplitude resolution of Full Scale/128. Up to 48
transmit bytes can be used, allowing each shaped pulse to extend up to three baud. Typically, SH
pulses use only 15 or 16 bytes, although all 48 bytes are available. LH pulse shaping may extend up
to three baud.
To use the PTM, two operations must take place:
1. The desired 8-bit values must be loaded into the Intel® LXT3108 LIU’s local memory. This
can be done through a host API at the application level or on the register level. The coding is
2’s complement from +127 to -127 where a code of +127 creates a full scale pulse at the
output. Each LSB is approximately 1/127 of FS. Care must be taken by the users, as it is
possible to create invalid pulse shapes either by mis-coding or by saturating the DAC.
2. After the bytes are loaded, assert ATWG_EN by loading value “01h”, as shown in “Transmit
Control Page Register, 03h” on page 70.
These settings are maintained as long as power is applied to the device and reset is not asserted.
They can be overwritten at any time and are not lost when the transmitter is powered-down as
shown in Figure 13 on page 43. The contents of the local memory are lost when power is removed
from the chip and initialized to zeros (0’s) when reset is asserted.
Caution: Do not assert ATWG_EN if the contents of the local memory has not been properly initialized.
The Intel® PTM® software can be used on the Intel® Evaluation System (IXF3208D) or ported to
customer board for adjustment to the output signal. The Intel® PTM® software simplifies the
process of modifying the output signal by handling all of the register manipulation for you.
Preliminary Datasheet
Document Number: 249543
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41
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
9.2
Transmit Digital Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs, and TDATA accepts unipolar data. Software controls how
input data passes through:
• The jitter attenuator, according to “JA Control Two Page Register, 1Dh” on page 79.
• The B8ZS/HDB3 encoder, according to “Line Coding Control One Page Register, 1Ch” on
page 78.
• Data is clocked on the falling edge of TCLK as shown in Figure 12, “Transmit Interface
Timing” on page 42.
Figure 12. Transmit Interface Timing
V
TCLK
t
sut
t
ht
TPOS
TNEG
9.2.1
Transmit Idle Operation and Three-stating Drivers
When the transmitter is not being used, the designer conserves power by powering down the driver
circuit. There are two ways to power down the transmitter:
1. Set bit five, Transmit Clock Detect Enable in the Transmit Control Register 03h to 0 and hold
TCLK input High for 16 clock cycles.
2. Assert the TXPD bit in “Port Master Control Page Register, 01h” on page 69, in software.
In this state, TTIP and TRING are at high impedance, and all of the analog circuitry associated
with the transmitter is turned off. After restarting TCLK or clearing the TXPD bit, it may take
several milliseconds for the transmitter to achieve steady state performance.
For redundancy applications, it is required to three-state the redundant transmitter while leaving the
active transmitter circuitry turned on. In this case, there are two ways to three-state the transmitter:
1. Set the OE pin low, which affects all eight ports at the same time.
2. Set the OES bit high in “Transmit Control Page Register, 03h” on page 70. In this case, the
transmitter three-state is done on a per port basis.
In this three-state mode, TTIP and TRING will enter a high impedance state. However, in this state
the transmitter will remain powered up. This will allow two transmitters to be connected in parallel
for redundancy applications.
42
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 5. Powering Down the Transmitter with Static TCLK
TXCLK
Effect
Transmitter enters Powered-down State. TTIP and TRING enter
high_impedence state.
TXCLK = 1 > 16 MCLK cycles OR TXPD = 1
TXCLK = 0 > 16 MCLK cycles
TTIP and TRING enter high-impedance state.
Figure 13. TCLK Power Down Timing
MCLK
TCLK
16 MCLK cycles
Tx
Power
Preliminary Datasheet
Document Number: 249543
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
10.0
Receiver
The eight receivers in the LXT3108 LIU are identical and operate independently. The following
paragraphs describe the operation of one receiver. The receiver is coupled to the line through a 1:1
transformer. The input common mode level is set on-chip. Recovered data is presented at the port’s
RPOS/RNEG or RDATA pins. The recovered clock is present at the port’s RCLK pin. Upon loss of
signal, RCLK is derived from MCLK. Refer to the test specification section for receiver timing.
10.1
Master Reference Clock
The MCLK input to the LXT3108 LIU requires Master Clock (MCLK) for operation. This clock is
used by the on-chip Clock Adapter (CLAD). The MCLK can be one of the following: 1x, 2x, 4x,
8x (T1 or E1). The LXT3108 LIU requires only one clock (e.g., 2.408 MHz) for all modes (T1/E1/
J1). The on-chip CLAD configuration is specified in CLAD_CONFIG1 register in Table 20.
Data and timing recovery circuits provide input jitter tolerance shown significant improvement
over the requirements set by AT&T Pub 62411 and ITU G.823. See the Test Specifications section
Table 49 through Table 59 and Figure 25 through 31 for more information.
10.2
Receiver Digital Interface
The recovered data goes to the Loss of Signal (LOS) Monitor, and through the Alarm Indication
Signal (AIS, Blue Alarm) Monitor. Received data may go through either the B8ZS or HDB3
decoder or neither. Finally, the data is sent to the framer either as unipolar or bipolar data on the
RDATA or RPOS/RNEG pins, and the recovered clock drives the RCLK pin. Received data is
clocked out of the LIU on the active edge of RCLK. The user can specify either the rising or falling
edge of RCLK for clocking out data on RDATA or RPOS/RNEG. The receiver LOS function
monitors the received signal level and indicates when the signal drops below the levels given in
Table 6. In the unipolar mode, the RNEG output indicates received BPV. BPVs are also counted in
the internal BPV counter when BPV count is enabled. Refer to “Monitoring BPV and EXZ Line
Coding Violations” on page 60 for more information.
10.2.1
Receiver Idle Conditions
The receiver is idle under either of the following conditions:
• When the RXPD bit described in “Port Master Control Page Register, 01h” on page 69 is set.
• When bit 0 in RENEN register described in “Port Receiver Enable Page Register, 02h” on
page 69 is set to 0. This bit puts the receiver into a reset when set to 0.
In the powered down condition, the RPOS, RNEG, and RDATA are not defined. The RCLK signal
stays at 1.544 MHz +/- 32ppm when the LIU port is configured in T1 or J1 mode. The RCLK
signal stays at 2.048 MHz +/- 50ppm when the LIU port is configured in E1 mode.
44
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
10.3
Receiver Line Interface
The LXT3108 LIU Receiver Line Interface provides:
• Programmable line termination, as described in “Termination Control Page Register, 05h” on
page 71.
• Programmable sensitivity, as described in “Receive Control Page Register, 04h” on page 71.
• Monitor mode, as described in Receive Control Page Register, 04h.
The LXT3108 LIU internally terminates the input line for twisted pair applications with a
combination of a single external resistor and programming the termination register to match the
line impedance. An advanced DSP- based receiver provides equalization and timing recovery for
signals with up to -36dB of cable loss (E1) or -36dB of cable loss (T1) in the presence of input
noise and jitter as specified in ANSI T1.408. The receiver provides up to -36 dB of sensitivity @
1024 KHz (E1) or up to 36 dB of sensitivity @ 772 KHz (T1) in steps of approximately 2 db under
software control as described in Receive Control Page Register, 04h.
Note: Component changes are not required, as these features provide industry standard performance.
10.3.1
Receive Termination Impedance
The receiver is coupled to the line through a 1:1 transformer. In E1 mode, the receiver input
impedance is high (above 10 KΩ).
Figure 14. Typical Receiver Interface
1:1
RTIP
Rx LINE
2 Ω
RRING
For E1 120 Ω, the receiver termination is set by the parallel combination of a precision 121 Ω ± ± 1±
external resistor and the internal impedance. Figure 14 shows a typical receiver interface. The total
input impedance can be set by the user by setting the appropriate bits in register RXTERM, address
05h, in the page registers. For T1 100±Ω, the internal resistor value is 580 Ω ± ±ꢀ1.±For J1 110 Ω,±
the internal resistor value is 1200 Ω ± ±ꢀ1.±For E1 120 Ω, the internal resistance has a value of
10 ΚΩ±or higher.
10.3.2
Programming the Intel® LXT3108
The LXT3108 is programmed using registers defined in this datasheet, or by using the available
Design Assistant CD-ROM.
Preliminary Datasheet
Document Number: 249543
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45
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
10.3.3
Guidelines for Programming the Intel® LXT3108 Receiver
To help ensure reliable operation, use the following sequence:
1. Program the page port registers for desired mode of operation (T1, E1, LH, SH, 100 Ω, 120 Ω,
and so on.)
2. Write the value 40h into Receiver Activation Logic Control register 33h.
3. Write the value 11h into Receiver Control Page Register register 3Ch.
4. Write the value 01h into page port register x02h, which enables the receiver.
Note: If enabling the receiver is not the last step (instruction) in receiver programming, receiver failure is
likely.
10.3.4
Receiver Operation with Transients
The LXT3108 receiver is initialized when a signal is detected on the line. When the operator
connects a cable to the port or a relay switches the line this signal may have transients. It usually
takes several milliseconds for the transients to go away and for the signal to the receiver to
stabilize. Transients distort the signal applied to the receiver. As a result, the receiver will require a
second initialization to acquire the valid (transients-free) signal.
The second receiver initialization should be done upon detection of LOS Cleared (an interrupt is
generated for LOS clear) using the following sequence:
• Disable the receiver (write 00h into register 2h).
• Wait at least 3 RCLK cycles.
• Enable the receiver (write 01h into register 2h).
This operation will result in LOS declare, because the data to LOS logic is all zeros during receiver
initialization. After this initialization is completed another LOS clear will occur providing a good
signal is applied to this port. This (second) LOS clear indicates that the receiver operates reliably.
This is the normal initialization procedure for the LXT3108. In addition to the Interrupts being
generated, the LOS status register (RX Equalizer Status 2, 08h) should also be checked. Interrupt
Servicing is further described in Section 13.2, “Interrupts” on page 63.
10.3.5
Receiver Sensitivity Programming
Under some conditions it may be desirable to limit the sensitivity of the receiver. This can be done
by programing “Receive Control Page Register, 04h” on page 71. This limits the range of the
receiver equalizer to the approximate values shown in Table 6. The designer selects the affected
port (as described in the “Port Page Select Register, CPS, 00h” on page 66) for all ports
simultaneously, or for each port individually.
46
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 6. Programming Receiver Sensitivity
RXCON
RX[4:0] hex
Maximum Receiver
Sensitivity (dB)a
Maximum Receiver
Sensitivity (dB)
T1/E1
T1/E1
00
01
-36
-35
-35
-34
-34
-32
-30
-28
-26
-24
-22
-20
-18
-16
-14
-12
-10
-8
-36
-34
-32
-30
-28
-26
-24
-22
-20
-18
-16
-14
-12
-10
-8
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
E1
T1
-6
10
-4
11
-2
12
-6
0
13
-4
-36
-36
-36
14
-2
15 - 1F
-36
a.
The numbers in Maximum Receiver Sensitivity Columns (in dB) represent an approximation of the maximum cable attenu-
ation the receiver can work with. For example, when RXCON bits [4:0] is 06H the receiver will work reliably with approxi-
mately 30dB of 22AWG cable in E1 mode and approximately 24dB of cable (22AWG) in T1 mode.
10.3.5.1
Receiver Monitor Mode
The receive equalizer of the Intel® LXT3108 LIU can be used in Monitor Mode applications.
Monitor Mode applications require a resistive attenuation of the signal in addition to a small
amount of cable attenuation (less than 6 dB). Asserting the MON bit in “Receive Control Page
Register, 04h” on page 71 configures the device to work in its Monitor Mode. The device must be
in its LH receiver mode for Monitor Mode which, is controlled by the RXSH bit in Receive Control
Page Register, 04h.
With the device in Monitor Mode, the receive equalizer handles signals attenuated resistively by 20
to 30 dB, plus 0 to 6 dB of cable attenuation for both E1 and T1 applications.
Note: The receiver in the T1 Monitoring Mode complies with G.824 jitter standard.
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
10.4
Receiver Status Information
The status of the receiver can be monitored though “Receiver Equalizer Status Zero Page Register,
06h” on page 71, while equalizer settings can be checked with “Receiver Equalizer Status One
Page Register, 07h” on page 72 and “Receiver Equalizer Status Two Page Register, 08h” on
page 72. Receiver Equalizer Status Two Page Register, 08h contains status bits that indicate LOS.
The contents of Receiver Equalizer Status Zero Page Register, 06hand Receiver Equalizer Status
One Page Register, 07h can be used to estimate the line attenuation, which can be translated to line
length.
48
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
11.0
Jitter Attenuation (JA)
A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) FIFO provides Jitter
attenuation. The FIFO depth is selectable for either 32 or 64-bits, through “JA Control Two Page
Register, 1Dh” on page 79. The JAL is internal and does not require an external crystal or a high-
frequency (higher than line rate) reference clock. The JA can be placed in either the receive or
transmit data path. The JA Control Two Page Register, 1Dh selects JA enabled or disabled, and
selects either the receive or the transmit path.
Figure 15. Jitter Attenuation Loop
TPOS
TPOSo
RPOS
RPOSi
TNEG
TNEGo
RNEG
FIFO
RNEGi
IN CK
OUT CK
TCLK
TCLK
RCLK
IN
OUT
DPLL
RCLKi
1.544/2.048 MHz
x 32
The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the register x1D). Data is clocked into
the FIFO with the associated clock signal (TCLK or RCLK) and clocked out of the FIFO with the
de-jittered JAL clock, as seen in Figure 15. When the FIFO is within two bits of overflowing or
underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator
produces a delay of up to 16 or 32-bits in the associated path. Please refer to Test Specifications for
details. This advanced digital jitter attenuator meets the latest jitter attenuation specifications
shown in Table 7.
Table 7. Jitter Attenuation Specifications
T1
E1
AT&T Pub 62411
GR-253-CORE
TR-TSY-000009
ITU-T G.736
ETSI CTR12/13
11.1
Digital Jitter Attenuator (DJA) Status
DJA status detection for both underflow and overflow conditions is reported in “Alarm Status One
Page Register, 12h” on page 76. Two maskable processor interrupts for the DJA are controlled by
“Interrupt Enable Page Register, 11h” on page 75. Details about both types of DJA interrupt status
are reported in “Interrupt Status Two Page Register, 13h” on page 77.
Preliminary Datasheet
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49
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
12.0
Network Control and Maintenance Functions
12.1
Diagnostic Modes
The LXT3108 LIU offers the following diagnostic modes:
• Network Loop (NLOOP) Code Generator/Detector.
• Analog loopback (ALOOP) digital transmitter to analog transmitter/receiver pins back to
digital receiver pins.
• Remote loopback (RLOOP) analog receiver to analog transmitter pins.
• Digital loopback (DLOOP) digital transmitter to digital receiver pins.
• Transmit All Ones (TAOS) signal sent by transmitter driver to line.
The LXT3108 LIU offers three loopback modes for diagnostic purposes: Analog, Remote, and
Digital Loopback. Network Loop codes activate Remote Loopback from a pattern contained in the
signal traffic passing through the LIU receiver. Loopbacks are selected by writing to the
appropriate port’s ALOOP bit in “Port Master Control Page Register, 01h” on page 69, or DLOOP,
NLOOP, or RLOOP bits in “Loopback Enable Page Register, 10h” on page 74. The Transmit All
Ones control bit is set in “Transmit Control Page Register, 03h” on page 70.
12.1.1
In-Band Network Loop Up or Down Code Generator/Detector
The LXT3108 can transmit in-band Network Loop Up or Loop Down codes. The Loop Up code is
00001. The Loop Down code is 001.
A Loop Up or Loop Down code transmission occurs when the respective bits in the Loopback
Loopback Enable Page Register, 10h on page 74, are set.
Network Loopback (NLOOP) can be initiated only when the Network Loopback detect function is
enabled. Writing a “1” to the NLOOP bit in Loopback Enable Page Register, 10h enables this
mode.
With NLOOP detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable,
001 = disable) in the input data stream. When the receiver detects an NLOOP enable data pattern
repeated for a minimum of five seconds, the device enables RLOOP. The device responds to both
framed and unframed NLOOP patterns. Once NLOOP detection is enabled at the chip and
activated by the appropriate data pattern, it is identical to Remote Loopback (RLOOP). NLOOP is
disabled by receiving the 001 pattern for five seconds, or by activating RLOOP or ALOOP, or by
disabling NLOOP detection in software.
12.1.2
Analog Loopback
Analog Loopback (ALOOP) exercises the maximum number of functional blocks. ALOOP
operation disconnects the RTIP/RRING signal path inputs from the line and routes the transmit
outputs back into the receive inputs. This tests the transmitter, receiver and timing recovery
sections. The ALOOP function overrides all other loopback modes. When analog loopback is
selected the receive line is still terminated by the internal termination. When selected, the
transmitter outputs (TTIP and TRING) are connected internally to the receiver inputs (RTIP and
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
RRING), as shown in Figure 16. Data and clock are output at RCLK, RPOS, and RNEG pins for
the corresponding LIU. Note that signals on the RTIP and RRING pins are ignored during analog
loopback. The ALOOP bit is in Loopback Enable Page Register, 10h.
Figure 16. Analog Loopback
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA*
JA*
TRING
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
12.1.3
Digital Loopback
When digital loopback is selected, the transmit clock and data inputs (TCLK, TPOS and TNEG)
are looped back and are output on the RCLK, RPOS and RNEG pins (see Figure 17). The data
presented on TCLK, TPOS and TNEG is also output on the TTIP and TRING pins.
Note: Signals on the RTIP and RRING pins are ignored during digital loopback.
Figure 17. Digital Loopback
MCLK
TAOS Mode
Timing &
Control
TTIP
TCLK
TPOS
TNEG
JA*
JA*
TRING
(ALL 1s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
12.1.4
Remote Loopback
During remote loopback as shown in Figure 18, the RTIP and RRING inputs are routed to the
transmit circuits and are output on the TTIP and TRING pins.
Note: Input signals on the TCLK, TPOS, and TNEG pins are ignored during remote loopback.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 18. Remote Loopback
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA*
JA*
TRING
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
12.1.5
Transmit All Ones (TAOS)
The TAOS mode is set by asserting the TAOS bit in Transmit Control Page Register, 03h. Note
that the TAOS generator uses MCLK as a timing reference. To assure that the output frequency is
within specification limits, MCLK must have the applicable stability as shown in Table 56,
“Master and Transmit Clock Timing Characteristics” on page 89.
Both DLOOP and ALOOP modes function correctly with TAOS active. However, RLOOP is
inhibited when TAOS mode is active.
Figure 19. TAOS Data Path
MCLK
TAOS mode
Timing &
Control
TTIP
TCLK
TPOS
TNEG
TRING
(ALL 1s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
JA*
RRING
* If Enabled
Figure 20. TAOS with Digital Loopback
MCLK
TAOS Active
Timing
&
TTIP
TCLK
TPOS
TNEG
Control
TRING
(ALL 1s)
RCLK
RTIP
Timing
Recovery
RPOS
RNEG
RRING
* If Enabled
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 21. TAOS with Analog Loopback
MCLK
TAOS Mode
Timing &
Control
TCLK
TPOS
TNEG
TTIP
TRING
(ALL 1s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
JA*
RRING
* If Enabled
12.2
Line Coding
This section describes the Intel® LXT3108 LIU functionality related to line coding and monitoring.
The LIU’s digital framer interface performs two functions:
1. Provides a bipolar or unipolar interface to a framer.
2. Offers line coding and decoding of AMI, B8ZS and HDB3.
The LIU digital framer interface can be operated in one of two functional modes as described in
Table 37, “Line Coding Control One Page Register, 1Ch” on page 78:
• BIPOLAR—Digital Positive/Negative/Clock signals, indicating signal polarity.
• UNIPOLAR—Digital Data/Clock, indicating NRZ data.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
12.2.1
Alternate Mark Inversion (AMI)
(per: ITU G.703)
AMI is a Return-to-Zero (RZ) format where a binary “one” (mark) is represented by either a
positive or negative going pulse and a binary “zero” (space) is represented by the absence of a
pulse. The LXT3108 LIU supports two standards for maximum number of consecutive zeros and
minimum ones density. The standards are ANSI T1.403 and FCC Part 68.318.
Note: AMI coding—No specific methods are used to suppress excess zeros in the signal. In addition, the
AMI coding alone does not provide any method of ensuring compliance to mark/space
requirements.
• ANSI T1.403:
— No more than 15 consecutive zeros.
— At least N ones in each and every time window of 8*(N+1) bits, where N = 1 through 23.
• FCC Part 68.318:
— No more than 80 consecutive zeros.
— An average ones density of at least 12.5%.
Note: Table 37, “Line Coding Control One Page Register, 1Ch” on page 78 offers line coding options.
Each consecutive pulse should alternate in polarity (for example, a positive pulse should always be
followed by a negative pulse; a negative pulse should always be followed by a positive pulse),
regardless of the number of intervening spaces between the two pulses.
Two consecutive pulses of the same polarity are known as a bipolar violation (BPV). The
LXT3108 LIU actively monitors the line signal and provides a count of detected BPVs for
performance monitoring purposes. By definition, all T1 line signals use basic AMI line coding.
However, because T1 receivers rely on the presence of marks in the signal to recover clocking,
various standards specify maximum space and minimum mark density requirements.
12.2.1.1
Bipolar with Eight Zero Substitution (B8ZS)
(per: ANSI T1.102)
The LXT3108 LIU allows separately controlled transmit and receive B8ZS encoding/decoding for
each port at T1 line rate described in “Line Coding Control One Page Register, 1Ch” on page 78.
The LXT3108 LIU performs both B8ZS coding (on the T1 transmitted signal) and B8ZS decoding
(on the T1 received signal). Received BPVs that are part of the B8ZS pattern are not counted as
BPV errors in the coding error counter.
B8ZS overcomes limitations of ZCS and allows for the support of clear port (64 kbps) data. It is
compatible with all standard T1 framing formats. In B8ZS coding, eight consecutive zeros in the
T1 data stream will be replaced by the B8ZS substitution pattern of “000VB0VB” in which “V” is
an intentional BiPolar Violation (BPV) and “B” is a valid bipolar mark. Note that the polarity of the
BPVs and marks depends upon the polarity of the last mark before the “eighth zero” occurs. This
substitution is made regardless of where the eight consecutive zeros occur in the data stream,
including framing, signaling, and alarm bits. As opposed to ZCS, which operates on data within a
DS0 port, B8ZS coding can occur across frame boundaries.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
12.2.1.2
High Density Bipolar Three (HDB3)
(per: ITU G.703)
The LXT3108 LIU allows separately controlled transmit and receive HDB3 encoding for each port
at E1 line rates described in “Line Coding Control One Page Register, 1Ch” on page 78.
Receive side HDB3 decoding is selected by setting the decoding bit in Line Coding Control One
Page Register, 1Ch. Similarly, transmit side HDB3 encoding is selected by setting the encoding bit
in Line Coding Control One Page Register, 1Ch. Received BPVs that are part of the HDB3 pattern
are not counted as BPVs in the coding violation error counter.
In HDB3 coding, four consecutive zeros in the E1 data stream will be replaced by the HDB3
substitution pattern of either “000V” or “B00V, in which “V” is an intentional bipolar violation
(BPV) and “B” is a valid bipolar mark. This limits the maximum number of consecutive spaces to
three. The choice of substitution pattern is made so that the number of B pulses between
consecutive V pulses is odd (for example, successive V pulses are of alternate polarity). This
substitution is made regardless of where the four consecutive zeros occur in the data stream,
including framing, signaling, and alarm bits. The LXT3108 LIU performs both HDB3 coding on
the E1 transmitted signal and HDB3 decoding on the E1 received signal.
12.3
Network Maintenance Functions
12.3.1
Loss Of Signal (LOS)
While LOS appears at each port’s LOS pin, it can be detected by software reading the LOS bit in
the “Receiver Equalizer Status Two Page Register, 08h” on page 72. A maskable processor
interrupt controlled by “Interrupt Enable Page Register, 11h” on page 75 is available. Details about
LOS interrupt status are reported in “Interrupt Status Two Page Register, 13h” on page 77.
Depending on whether the port is configured for T1 or E1 service, the LOS will be cleared when
required marks (ones) density is met after the detection of LOS.
Each receiver has a multi-function LOS detector that is used to meet ITU T1.231 or G.775
requirements for T1 or E1 systems. The default values are given in Table 10. These detectors
monitor both the received signal amplitude and the received marks density according to Table 8.
The user may change these values by setting the USR_LOS bit in “Port Master Control Page
Register, 01h” on page 69. When this bit is set, the desired LOS Window, LOS Set, and LOS Reset
values must be programmed for proper LOS operation.
Three user registers are provided for customizing the received marks density LOS detector. Users
can select:
• The number of consecutive spaces that must be received to declare LOS in “LOS Window
Page Register, 0Bh” on page 72.
• The number of marks that must be received within that window to clear LOS “LOS Set
Threshold One Page Register, 0Ch” on page 73.
• The number of consecutive zeros that, when received while LOS is asserted, will continue to
re-assert LOS in “LOS Reset Threshold Two Page Register, 0Dh” on page 73.
These detectors monitor both the received signal amplitude and the received marks density
according to Table 8.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Note: For E1 SH operation the LOS operates based on the peak received amplitude during a fixed
window. For G.775 the window length can be programmed by LOS Window Page Register, 0Bh. A
minimum data density of 1 in 16 is required to clear LOS.
Table 8. LOS Criteria for Intel® LXT3108 LIU
Standard
T1.231
LOS Declared
LOS Cleared
No pulse transitions for 175 consecutive
clock cycles
12.5% mark density in 175 clock cycles
and less than 100 consecutive zeros
Less than 20dB, and 12.5% mark density
in a 32-bit window, and less than 15
consecutive zeros
More than 26dB below nominal output
level, for 1544-bit periods
T1 ITU I.431
E1 G.775
Less than12dB, and 12.5% mark density
in a 32-bit window, and less than 15
consecutive zeros
More than 18dB below nominal output
level, for 32-bit periods
Less than 15dB, and 12.5% mark density
in a 32-bit window, and less than 15
consecutive zeros
More than 18dB below nominal output
level, for 2048-bit periods
E1 ITU I.431
Less than 15dB, and 12.5% mark density
in a 32-bit window, and less than 15
consecutive zeros
More than 18dB below nominal output
level, for 2048-bit periods
E1 ETSI 300 233
E1 long haul
No pulse transitions for 175 consecutive
clock cycles
12.5% mark density in a 32-bit window,
and less than 15 consecutive zeros
Table 9. LOS Register Configurations
Reg addr: 01H (master)
04H (rxcon)
LOS Criteria
Description
bit-4
bit-3
I431
bit-0
bit-7
rxah
usr_los
E1/T1
0
0
0
0
0
1
0
1
0
0
1
1
x
x
1
x
T1.231
I.431
Marks density detection
Amplitude detection
Amplitude detection
Amplitude detection
G.775
I.431/ETSI
Marks density detection
(same criteria as T1.231)
0
0
1
0
E1 long haul
1
1
0
1
x
x
x
x
User LOS 1
User LOS 2
Marks density detection
Amplitude detection
NOTE:
1. x: don’t care.
.
Table 10. LOS Selection Defaults
Number of Spaces in
Window to Reset the LOS
Counter
Number of Marks in
Window to Clear LOS
T1/E1
Window Size
T1
E1
175
32
21
4
100
16
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
The receiver monitor loads a digital counter at the RCLK frequency. The counter will increment
each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the
operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is
replaced by MCLK at the RCLK output with a minimum amount of phase errors. (MCLK is
required for receive operation.) When the LOS condition is cleared, the LOS flag is reset and
another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will be high
during the entire LOS detection period for that port.
12.3.1.1
Operation of USER LOS with Amplitude Detection
In some applications you might be required to customize the LOS criteria. This criteria might differ
from those listed in Table 9. This type of customized LOS is called “User LOS” and it includes two
criterion:
1. LOS with Amplitude Detection.
2. User LOS with Marks Density detection.
For practical reasons, the User LOS with amplitude detection will be available for signals on the
line with amplitude at 1 V and below:
• LOS will be declared when the received signal level is below the LOSTHRES1 x 4m V level
for evaluation period of time specified in the LOS Window Page Register, 0Bh on page 72.
LOSTHRES1 x 4m V creates so called LOS set threshold and it is called LOSSET. LOS is
asserted when input signal drops below LOSSET limit.
• LOS will be cleared when the received signal is above the LOSTHRES2 x 4mV threshold.
This voltage level is called LOSCLR. The LOS will be cleared when the input signal to the
receiver is above LOSCLR level. The receiver makes the decision using marks density criteria
of at least 12.5% marks density in 32-bit period. This limits options for the value in the LOS
Window Page Register, 0Bh on page 72 to be 04h or higher. Refer to Tables 22, 30, 31, and 32
for more details.
Examples of user LOS with Amplitude Detection, include:
• LOS declaration: Input signal amplitude (peak differential) <89m V for 400-bit period.
• LOS clearance: Input signal amplitude (peak differential) > 190m V.
• Register settings calculation:
• Step 1: Reg 0Bh = 400/8 =50dec = 32h
• Step 2: Reg 0Ch = 89/4 = 22dec = 16h
• Step 3: Reg 0dh = 190/4 = 47dec = 2Fh
Caution: The above register settings must be done before enabling the receiver. Incorrectly setting the
register value may incur improper receiver operation. The LOS actual declaration/clearance levels
might deviate from the set values. Therefore, users might need to adjust the register values for
desired levels.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
12.3.1.2
Operation of USER LOS with Marks Density Detection
LOS will be declared when no marks has been received during the evaluation period specified in
the LOS Window Page Register, 0Bh on page 72. The value in the LOS Window Page Register,
0Bh on page 72 should be 20h or higher.
LOS will be cleared when during the LOS evaluation period, the number of consecutive zeros
(spaces) is less than MAXZERO (listed in the LOS Set Threshold One Page Register, 0Ch on
page 73 and the number of marks is more than MINMARKS—Reg. 0Dh). Refer to Tables 22, 30,
31, and 32 for more details.
Examples of User LOS with Marks Density Detection, include:
• LOS declaration: no marks for 200-bit period minimum
• LOS clear: in 200-bit period, maximum number of consecutive zeros is <40 and minimum
number of marks >30. This will give the following register settings:
• step1: Reg 0Bh = 200dec = C8h
• step2: Reg 0Ch = 40dec = 28h
• step3: Reg 0Dh = 30dec = 1Eh
12.3.2
Alarm Indication Signal (AIS)
Alarm Indication Signal reports all ones signal received at the RTIP and RRING pins. Once AIS is
detected, the port status flag is set in “Alarm Status One Page Register, 12h” on page 76. A
maskable processor interrupt controlled by “Interrupt Enable Page Register, 11h” on page 75 is
available. Details about AIS interrupt status are reported in “Interrupt Status Two Page Register,
13h” on page 77. Depending on whether the port is configured for T1 or E1 service, the AIS will be
cleared for the appropriate zeros density after the detection of AIS, as described in Table 11.
.
Table 11. AIS Service Condition Variations
Maximum number of spaces
within the window to declare
AIS.
Number of Spaces in Window to
Clear AIS
T1/E1
Window Size
T1
E1
3 ms.
9
3
8
2
512-bit
(per: ETSI 300233)
E1 AIS is declared when less than three spaces (for example, 2 or less zeros) are detected in a 250
µsec period of data (512-bit window). This condition should be reliably detected in the presence of
a 1.0E-03-bit Error Rate (BER), implying that a framed all-ones pattern will not be mistaken as an
AIS.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
(per ITU G.775)
E1 AIS is detected when less than three spaces are detected in two consecutive 512-bit wide
windows. The AIS is cleared when three or more zeros are detected in two consecutive 512-bit
wide windows.
(per: ANSI T1.231)
T1 AIS (Blue Alarm) is declared when less than nine spaces (for example, 8 or less zeros) are
detected in a 8192-bit wide window. When AIS is detected, the appropriate bit in the AIS status
register is set and a microprocessor interrupt is generated (unless masked). AIS is cleared when 9
or more zeros are detected in a 8192-bit wide window.
12.3.3
NLOOP Status
With NLOOP detection enabled in “Loopback Enable Page Register, 10h” on page 74, the receiver
looks for the NLOOP data patterns (00001 = enable, 001 = disable) in the input data stream. When
the receiver detects an NLOOP enable data pattern repeated for a minimum of five seconds, the
device enables RLOOP and the port status flag is set in “Alarm Status One Page Register, 12h” on
page 76. The device responds to both framed and unframed NLOOP patterns. NLOOP is cleared
by:
• Receiving the 001 pattern for five seconds.
• Activating RLOOP in “Loopback Enable Page Register, 10h” on page 74 or ALOOP in “Port
Master Control Page Register, 01h” on page 69.
• Disabling NLOOP detection in Loopback Enable Page Register, 10h.
A maskable processor interrupt for NLOOP is controlled by “Interrupt Enable Page Register, 11h”
on page 75. Details about NLOOP interrupt status are reported in “Interrupt Status Two Page
Register, 13h” on page 77.
12.3.3.1
T1 AMI/B8ZS BPVs
In T1 service, only one type of T1 BPV line coding violation is used:
• A Bipolar Violation (BPV) is defined as any two consecutive pulses (marks) of the same
polarity with AMI coded bit stream. BPVs that are part of the B8ZS zero-substitution coding
will not be reported—All other BPVs are reported and counted.
• The LXT3108 LIU actively monitors the line signal for this type of coding violation and
increments the BPV counter for performance monitoring purposes. BPVs detected in the
receive direction are also reported on RNEG/RBPV output, when the LIU is configured in the
unipolar mode of operation.
12.3.3.2
E1 AMI/HDB3 BPVs
Two basic types of E1 line coding violations are defined as:
1. ITU G.703—A BiPolar Violation (BPV) is defined as any two consecutive pulses (marks) of
the same polarity with AMI coded bit stream.
2. ITU O.161—An HDB3 coding violation is defined as the occurrence of two consecutive BPVs
of the same polarity that are not part of the HDB3 zero substitution coding.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
The LXT3108 LIU actively monitors the line signal for both types coding violations and
increments the BPV counter for performance monitoring purposes. Receive BPVs are also reported
on the RNEG/RBPV output, when the LIU operates in unipolar mode.
12.3.3.3
Excess Zeros (EXZ)
The definition of an EXZ depends upon the line coding format, as defined in Table 12. The line
signal is monitored for any violations of the maximum space rule as set in “Line Coding Control
One Page Register, 1Ch” on page 78. When selected, EXZ occurrences increment the BPV counter
for performance monitoring purposes.
Table 12. Excess Zero (EXZ) Definitions
Coding
Method
EXZ Definition
(ANSI)
EXZ Definition
(FCC)
Any string with greater than 80 consecutive
zeros
AMI
Any string greater than 15 consecutive zeros
Any string greater than 3 consecutive zeros
Any string greater than 8 consecutive zeros
Any string with greater than 3 consecutive
zeros
HDB3
B8ZS
Any string with greater than 8 consecutive
zeros
12.3.4
Monitoring BPV and EXZ Line Coding Violations
BPV and EXZ line coding violations are reported on signal traffic received at RTIP and RRING
pins. Once a BPV or EXZ condition is detected, the port status flag is set in “Alarm Status One
Page Register, 12h” on page 76. The Intel® LXT3108 LIU has two registers that form a 16-bit
counter for each port to monitor BPVs and excess zeros. The counter mode is set by bits 7 through
5 in Line Coding Control One Page Register, 1Ch. The counter can be enabled to count both BPVs
and excess zeros or, for troubleshooting purposes, to count either BPVs or Excess Zeros only.
These counters, BPV Counter High Byte Page Register, 1Eh and BPV Counter Low Byte Page
Register, 1Fh, will increment when there is a valid code violation. The counter has a shadow
register that is updated at one second intervals. This is done with an internal one second timer. The
one second timer is based on the RCLK. Each port uses its own one second timer. The user should
read the 16-bit shadow register (addr 1Eh and 1Fh) for BPV count accumulated during the previous
one second time frame. The count value stored in the shadow register can be read by the host.
Note: It is recommended to read Application Note “Making Modifications to Embedded software to
precisely count bipolar violations” before implementing BPV Monitoring feature. This application
note is available on Intel web site under the LXT3108 documentation.
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Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
13.0
Host Interface
The microprocessor interface is used to relay configuration, control, status, and data information
between the LXT3108 LIU and an external microprocessor or micro controller.
The microprocessor interface supports MPC860/M68360 (memory like bus), M68302 (standard
Motorola bus), the i960®/i486TM processor bus. 8-bit address and data buses are supported.
Non-multiplexed address and data busses are supported. The user selects the processor type by
tying the MPI_TYPE 1 and 2 pins appropriately. The processor interface can operate up to a bus
cycle of 33 Mhz. The MPC860 requires five wait states and the i960® CPU also requires five wait
states. Handshaking and automatic wait state generation are supported. The latency of processor
access is fixed so the use of the wait state signal is optional.
The LXT3108 LIU provides extensive interrupt support. All interrupts are independently
maskable—One interrupt output is provided.
13.1
Supported Processors and Connections
The LXT3108 LIU supports direct connection to the MPC860, M68360, M68302 (M68000*
family), i486TM, and i960® processors. The user selects the type of processor by tying the TYPEx
pins to the appropriate GND and V connections. The connections between the processor pins and
cc
the MPI_TYPE programming are defined as below.
13.1.1
MPC860
The LXT3108 LIU host interface address and data pins follow the MPC860 endian fashion. The
LXT3108 LIU requires five wait states from the microprocessor in order to satisfy its internal
timing.
.
Table 13. Interfacing the Intel® LXT3108 LIU to the MPC860 Processor
Intel® LXT3108 LIU
Intel® LXT3108 LIU Pin
Motorola MPC860 Pin
I/O
TYPE1 = 0
TYPE2 = 0
DB(7:0) a
AD(7:0) b
CS
i
-
-
I
I/O
D(31:24)
A(31:24)
CS
I
I
DS
I
TS
RW
I
R/W#
CLK
TA
MPI_CLK/ALE
RDY
I
O
a.
b.
Bits: DB0, AD0, are the MSB bits.
Bits: DB0, AD0, are the MSB bits.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
13.1.2
M68302*
The M68302 (or the M68000 family) is supported in this mode. Notice that DTACK is not used in
this case. The user is required to generate their own internal wait states when needed. The number
of wait states needed depends on the clock frequency of the microprocessor. When clock frequency
of 16.67 MHz is used, no wait states are needed. When 20 MHz or 25 MHz clock is used, one wait
state is needed.
Table 14. Interfacing the Intel® LXT3108 LIU to the M68302 Processor
Intel® LXT3108 LIU
Intel® LXT3108 LIU Pin
I/O
Motorola M68302 Pin
TYPE1 = 0
TYPE2 = 1
DB(7:0)
I
-
I
-
I/O
D(7:0)
A(7:0)
CS
AD(7:0)
I
I
I
I
I
CS
DS
LDS
R/W#
-
RW
MPI_CLK/ALE = 1
13.1.3
Intel® i960®/i486TM
The Intel® i960®/i486TM family is supported in this mode. This is a synchronous bus interface with
the timing being derived from the MPI_CLK input. Internally, all operations will be performed on
the next cycle after ADS is asserted—Five wait states are required.
The Intel® i960®/i486TM can operate in Muxed and Non-Muxed mode. For Muxed mode of
operation, the address and data busses of the LXT3108 should be connected together externally to
the device.
Table 15. Intel® i960®/i486TM Mode
Pin
i960®/i486TM
TYPE1
TYPE2
DB0
1
0
D0
DB1
D1
DB7
D7
AD0
A0
AD7
A7
CS
CS
DS
ADS
W/R#
CLKO1
READY
RW
MPI_CLK
RDY
62
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
13.2
Interrupts
There are four interrupt sources:
1. Status change in the Loss of Signal (LOS) bit of Receiver Equalizer Status Two Page Register,
08h—The Intel® LXT3108 LIU’s analog/digital LOS processor continuously monitors the
receiver signal and updates the specific LOS status bit to indicate presence or absence of a
LOS condition.
2. Status change in the AIS (Alarm Indication Signal) bit of Alarm Status One Page Register,
12h—The Intel® LXT3108 LIU’s receiver monitors the incoming data stream and updates the
specific AIS status bit to indicate presence or absence of an AIS condition.
3. Status change in NLOOP (Network Loop Code) bit of Alarm Status One Page Register, 12h.
4. Elastic Store overflow or underflow (DJA overflow or underflow) bits of Alarm Status One
Page Register, 12h.—The Intel® LXT3108 LIU jitter attenuator updates these based on DJA
response to jitter on incoming signal.
13.2.1
Interrupt Enabling
The LXT3108 LIU provides a latched interrupt output (INT). An interrupt occurs any time there is
a transition on any enabled bit in the Interrupt Status Register (Addr. 13h.). Writing a logic “1” into
the enable register will enable the respective bit in the respective Interrupt status register to
generate an interrupt. The power-on default value is all zeros. The setting of the interrupt enable bit
does not affect the operation of the status registers.
When there is a transition on any enabled bit in a status register, the associated bit of the interrupt
status register is set and an interrupt is generated (when one is not already pending). When an
interrupt occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a
pull-down device.
13.2.2
Interrupt Clearing
Reading register 13h (Interrupt Status Register) clears the corresponding interrupt with the rising
edge of the read or data strobe. When there are no pending interrupts left INT pin will go back
high. Refer to Figure 22, “Interrupt Processing FlowChart” on page 64 for more details.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 22. Interrupt Processing FlowChart
Start
No
Enable
Interrupts?
Disable
Interrups?
No
Yes
Yes
Write "1" into corresponding
interrupt bit in reg 11h
Write "0" into corresponding
interrupt bit in reg. 11h
No
Does interrupt
conditions exist?
Yes
Pin INT* goes Low
Read reg. ISR at addr. 02h
for port#
Read interrupt status Register(ISR), addr 13h
for each port that shows an interrupt.
Pin INT* on the device goes High when
interrupts on all ports are cleared.
DJAx, NLOOP, AIS
LOS
Which Interrupt
condition exists?
Read reg. 12h to
get status of DJAx,
NLOOP and AIS
Read reg. 08h to
get status of LOS
Is DJAx,
NLOOP or AIS
active?
No
No
Is LOS active?
DJAx, NLOOP or
AIS condition
cleared
Yes
LOS Cleared
Yes
DJAx, NLOOP or
AIS condition
exists
LOS condition
exists
64
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
14.0
Register Definitions
Since the Intel® LXT3108 LIU has both global registers and Page Port Registers (PPRs), the first
subsection covers the global registers and the second subsection covers the PPRs. The global
registers control parameters affecting operation for the entire device. One set of PPR registers
controls parameters affecting operation for a single port. Of the nine sets of PPR registers, there is
one for each of the eight ports and there is an additional set that controls all eight ports at the same
time.
Because global registers are programmed differently than PPRs, this section describes the
differences:
• Access a global register by reading or writing directly to the global register address. This is a
single operation to read or write a global register. The CPS register must be set to 00h first.
• Access PPRs by writing to a global register, Port Page Select (CPS) at address 00h, with the
selected port number. Immediately following this action, access the PPR for the selected port
by reading or writing to the chosen PPR address. This is a double operation, one write access
to the PPS with the port number followed by a single read or write to a PPR.
14.1
Global Registers
This subsection is organized with a summary of the global registers in Table 16 followed by a
descriptive listing of each global register starting at Table 17 on page 66 and ending at Table 44 on
page 80. Table 16 includes the global register names and addresses for the LXT3108 LIU.
Table 16. Global Register Addresses
Binary Address
A7-A0
Name
Symbol
HEX Address
Mode
Port Page Select Register
ID Register
CPS
00000000
00000001
00000010
00010001
00
01
W
R
ID
ICR
Interrupt Port Register
CLAD Configuration Register 1
02
R
CLAD_CONFIG1
11H
R/W
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 17. Port Page Select Register, CPS, 00h
Bit
Name
Bit
Function
Soft-reset, set bit 7 for device software reset. Bit 7 automatically clears itself on
reset. Soft-reset, resets all ports, and the entire device except for the CLAD circuitry.
Only a hardware reset or power up reset can reset the CLAD.
7
6:4
Not used
Bits 3:0
0000
0001
0010
0011
0100
0101
0110
0111
Index/Page
Selects Global Register Page
Selects Page 1 - control registers for Port 0
Selects Page 2 - control registers for Port 1
Selects Page 3 - control registers for Port 2
Selects Page 4 - control registers for Port 3
Selects Page 5 - control registers for Port 4
Selects Page 6 - control registers for Port 5
Selects Page 7 - control registers for Port 6
Selects Page 8 - control registers for Port 7
Selects write to all page control registers at one time.
PS4-PS0
7:0
(Write Only
Registers)
3:0
1000
1001
NOTE: Writing to this register selects the index to the page for individual port control registers.
Table 18. ID Register, ID, 01h
Bit
Name
Function
This register contains a unique revision code and is mask programmed. For rev. B2 silicon
the value of this register is B2h, for B3 silicon rev. the value is B3h.
7:0
ID7-ID0
Table 19. Interrupt Port Register, ICR, 02h
Bit
Name
Function
This register is read by the CPU when an interrupt has occurred. Value in this register
identifies the port (or ports) on which the interrupt (or interrupts) was generated.
A “1” indicates that an interrupt occurred in the respective port.
Bit 0 = 1, interrupt occurred on Port 0.
Bit 1 = 1, interrupt occurred on Port 1.
Bit 2 = 1, interrupt occurred on Port 2.
Bit 3 = 1, interrupt occurred on Port 3.
Bit 4 = 1, interrupt occurred on Port 4.
Bit 5 = 1, interrupt occurred on Port 5.
Bit 6 = 1, interrupt occurred on Port 6.
Bit 7 = 1, interrupt occurred on Port 7.
7:0
ICR7-ICR0
66
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 20. CLAD Configuration Register1, 11h
Address
Description
Name
Status
Bit
Function
This bit initializes the CLAD. Default for this bit is “0”. It
must be set to “1” for CLAD to work. In the event that a
“0” is written into this bit by accident during operation,
the CLAD will stop working. A hardware Reset (pull
CLAD_PSRST
7
RSTB pin low) must follow and the CLAD has to be
re-initialized.
CLAD_PWDN
CLAD_CSSEL
6
5
RESERVED - write as “0”
RESERVED - write as “0”
MCLK definition bit. When set, clock applied to MCLK
pin must be T1- based. When clear (default) MCLK
must be E1- based
CLAD Configuration
Register 1
(CLAD_CONFIG1)
CLAD_OT1E1
4
11h3
R/W
MCLK definition bits. Bits 4,3, and 2 define MCLK
frequency
00 = 8x (T1 or E1) (default)
10 = 4x (T1 or E1)
DIV<1:0>
3:2
01 = 2x (T1 or E1)
11 = 1x (T1 or E1)
CLAD_TFB
1
0
RESERVED - write as “0”
RESERVED - write as “0”
CLAD_TRST
NOTES:
1. Upon reset, restored default value is 00h.
2. In the event that an accidental write of 1 during normal operation into any of the RESERVED bits occurs, a hardware RESET
must be applied and followed by CLAD initialization.
3. This register is not affected by the soft reset bit. The CLAD configuration register should only be written after reset operation
initiated by the RSTB pin or after device power up.
14.2
Port Page Register Bank (PPRB)
Each of the eight LIU ports in the Intel® LXT3108 LIU has independent register control available
through its Port Page Register Bank. Reading or writing to each bank of registers is a two-step
process:
1. Select the port by writing the port number to the global register Port Page Select (CPS),
address 00h.
2. Program the selected PPRB register or read its status.
There is an additional mode where all eight ports can be set up to the identical settings by first
writing to address 00h with a value of 09h. Table 21 on page 68 provides an overview of the PPRB
structure for each port’s LIU. Each port in the LXT3108 LIU has an individual PPRB. The registers
in the port bank structure are descriptively listed in the range of Table 22 on page 69 through Table
44 on page 80.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 21. Port Page Register Bank Addresses
Binary Address
Name
Port Master Control
Symbol
Address
Mode
A7-A0
MASTER
RENEN
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1011
0000 1100
0000 1101
0001 0000
0001 0001
0001 0010
0001 0011
0001 1100
0001 1101
0001 1110
0001 1111
0011011
01h
02h
03h
04h
05h
06h
07h
08h
0Bh
0Ch
0Dh
10h
11h
R/W
R/W
R/W
R/W
R/W
R
Port Receiver Enable
Transmit Control
TXCON
Receiver Control
RXCON
Termination Control
TERM
RX Equalizer Status 0
RX Equalizer Status 1
RX Equalizer Status 2
LOS Window
RXSTATUS0
RXSTATUS1
RXSTATUS2
LOSWINLEN
LOSTHRES1
LOSTHRES2
LER
R
R
R/W
R/W
R/W
R/W
R/W
R
LOS Set Threshold
LOS Reset Threshold
Loopback Enable Register
Interrupt Enable Register
Alarm Status Register 1
Interrupt Status Register 2
Control Register 1
IER
SR1
12h
13h
1Ch
1Dh
1Eh
1F
SR2
R
CR1
R/W
R/W
R
Control Register 2
CR2
BPV counter High Byte
BPV counter Low Byte
Receiver activation logic control
Receiver Control Register 1
Receiver Control Page Register
Transmit Pulse Shape Coefficients
BPVCTRHB
BPVCTRLB
RALC
R
33h
34h
3Ch
40h-6Fh
R/W
R/W
W
RWFCTRL
RWFCTRL
TXCOEF
00110100
0011 1100
R/W
68
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 22. Port Master Control Page Register, 01h
Address
Description
Name
Status
Bit
Description
7
6
5
Reserved; write as “0”
TXPD, “1” powers down transmitter circuitry.
RXPD, “1” powers down receiver circuitry.
BIt 4 Bit 3
0
1
This registers setting enables LOS criteria
as defined in I.431 standard. Refer toTable
9 for more details.
1
0
This register setting enables USER LOS
with Marks Density Detection (criteria for
“Digital LOS”). Refer to Tables 9, 30, 31,
and 32 for more details.
Port Master
Control
4, 3
01h
MASTER
R/W
1
0
1
0
This register setting enables USER LOS
with Amplitude Detection (criteria for
“Analog LOS”). Refer to Tables 9, 30, 31,
and 32 for more details.
This option must be considered in context
with settings of bit 0 and register 04h.
Refer to Table 9 for details.
2
1
Reserved; write as “0”
ALOOP, “1” enable analog loopback diagnostic mode
T1E1, “0” enables T1, 1.544 MHz operation, while “1”
enables E1, 2.048 MHz operation
0
NOTE: Upon reset, restored default value is 0h.
G25
Table 23. Port Receiver Enable Page Register, 02h
Address
Description
Name
Status Function
This register enables or disables the receiver on per port basis.
The receiver has to be enabled for proper LIU operation.
•
•
When bit 0 is set to 0, port receiver is disabled.
When bit 0 is set to 1, port receiver is enabled.
This register is used to perform two important functions:
1. To start the receiver—This function is a part of device
configuration. It is recommended to set this register to 00h,
configure the receiver at first (parameters such as T1 or E1,
impedance, and so on.) and to set this register to 01h as the
last step in receiver configuration.
Port Receiver
Enable
02h
RENEN
R/W
2. To perform receiver restart upon receiver failure—For a
successful receiver restart (reinitialization) it is required to write
00h into this register, wait at least 3 RCLK cycles and write
01h into this register. Receiver restart does not change receiver
configuration.
NOTE: Upon reset, restored default value is 0h.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 24. Transmit Control Page Register, 03h
Address
Description
Name
Status Bit
Function
7
Transmit All Ones enable (TAOS) when this bit is set to 1.
Transmit output high impedance (OES) is enabled when
this bit is set to 1. In this setting the driver of this port is
powered up and its output is in high impedance mode.
This is a typical configuration for HPS application.
6
5
NOTE: Set this bit to 0 for normal LIU operation.
Transmit Clock Detect Enable
TCLK presence detection is enabled when this bit is set to
zero. When the TCLK is stopped (no transitions) for more
than 16 cycles the transmitter on this port is powered
down.
NOTE: Write 1 to disable TCLK detection.
Bits
4:1
Decode bits 4 to 0 for pre-programmed pulse
shapes.
•
T1 SH 0-133 ft. Write this value for T1, SH
application and expected cable in front of
the transmitter to be 0-133 ft.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
T1 SH 134 -266 ft.
T1 SH 267 - 399 ft.
T1 SH 400 -533 ft.
T1 SH 534 - 655 ft.
T1 0dB LH
03h
Transmit Control
TXCON
R/W
T1 LH -7.5 dB
T1 LH -15 dB
T1 LH -22.5 dB
E1 SH 75 Ω
E1 SH 120 Ω
E1 LH 75 Ω
E1 LH 120 Ω
J1
4:1
Not used
Not used
Bit 0 controls ATWG operation. ATWG is enabled when it
is set to 1. Normal operation is with ATWG being disabled
(write 0 into this bit).
0
NOTE: Upon reset, restored default value is 0h.
70
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 25. Receive Control Page Register, 04h
Address
Description
Name
Status
Bit
Function
Set this bit to 1 for T1/E1 SH operation. Set to 0 for all
other modes of operation.
RXSH
7
Set this bit to 1 for Monitoring Mode. For Monitoring Mode
bit 7 of this register (RXSH) must be set to 0.
MON_MOD
RXCON
6
5
Not used
04h
Receiver Control
R/W
bits 4 to 0 select receiver sensitivity in dB.
•
For Short Haul operation set bits[4:0] to 0 or don’t
care.
Bits
4:0
•
For Monitoring Mode set bits[4:0] to 0 or “don’t care.”
•
For Long Haul Mode bits [4:0] define receiver
sensitivity. Refer to Table 6 for more details.
Table 26. Termination Control Page Register, 05h
Address
Description
Name
Status
Bit
Function
Bits
7:6
Bits 7 and 6 select transmit termination
0
•
•
•
•
100 Ω
110 Ω
120 Ω
120 Ω
7:6
5:2
1:0
1
2
3
Termination
Control TX/RX
05h
TERM
R/W
Bit 5 through 2 are not assigned
Bits
1:0
Bits 1 and 0 select receiver termination
0
1
2
3
•
•
•
•
100 Ω
110 Ω
120 Ω
100 Ω
NOTE: Upon reset, restored default value is 0h.
Table 27. Receiver Equalizer Status Zero Page Register, 06h
Address
Description
Name
Status
Bit
Function
RX Equalizer
Status0
06h
RXSTATUS0
R
7:0
Reserved
NOTE: Upon reset, restored default value is 0h.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 28. Receiver Equalizer Status One Page Register, 07h
Address
Description
Name
Status
Bit
Function
7:4
Reserved
RX Equalizer
Status1
07h
RXSTATUS1
R
Decode AGC state settings. Bits 0 through 3 can be used
to determine the cable/attenuation length.
3:0
NOTE: Upon reset, restored default value is 0h.
Table 29. Receiver Equalizer Status Two Page Register, 08h
Address
Description
Name
Status
Bit
Function
7:5
Reserved
LOS status bit, 1 = LOS has occurred. 0 = LOS cleared.
A change in the LOS status will generate a LOS interrupt
if LOS interrupt is enabled.
4
RX Equalizer
Status 2
08h
RXSTATUS2
R
3
2
1
0
Not used
Reserved
Reserved
Reserved
NOTE: Upon reset, restored default value is 0h.
Table 30. LOS Window Page Register, 0Bh
Address
Description
Name
Status
Function
LOS Window for User
Programmed LOS. Two
modes of operation are
available:
Evaluation window for LOS detection.
1. User LOS with Amplitude
Detection. Refer to Table
22.
Value in this register specifies Evaluation period for LOS
declaration. The actual evaluation time (in UI or baud) is
eight times the value specified in the register.
0Bh
LOSWINLEN R/W
2. User LOS with Marks
Density Detection.
In User LOS with Amplitude Detection the actual
evaluation time (in UI or baud) for LOS declaration
is LOSWINLEN x 8UI.
In User LOS with Marks Density Detection the actual time
for both LOS declare and LOS clear is LOSWINLEN
x 1UI.
NOTE: Upon reset, restored default value is 0h.
72
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 31. LOS Set Threshold One Page Register, 0Ch
Address
Description
Name
Status
Function
This register controls two functions:
1. User LOS with Amplitude Detection. Refer to Table
22. User LOS with Amplitude Detection works only for
line signal below 1 V. In this mode the value in this
register represents the maximum level of the received
signal (multiply the register decimal value by 4mv) to
declare LOS. This variable is named LOSSET.
LOSSET must be less or equal than LOSCLR
(defined in Table 32).
LOS Set
Threshold
0Ch
LOSTHRES1
R/W
2. User LOS with Marks Density Detection. Refer to
Table 22. In this mode the value in this register
represents the upper limit of the number of
consecutive zeros allowed during evaluation time
(specified in the LOS Window Page Register, 0Bh),
before digital LOS is cleared. This variable is named
MAXZERO.
NOTE: Upon reset, restored default value is 0h.
Table 32. LOS Reset Threshold Two Page Register, 0Dh
Address
Description
Name
Status
Function
This register controls two functions:
1. User LOS with Amplitude Detection. Refer to Table 22.
In this mode the value in register 0Dh represents the minimum
level of the received signal (multiply the register decimal value
by 4mv) to clear Analog LOS. This variable is named LOSCLR.
LOSCLR must be larger than or equal to LOS declare
threshold (LOSSET).
LOS Reset
Threshold
0Dh
LOSTHRES2
R/W
2. User LOS with Marks Density Detection (digital LOS). Refer to
Table 22. In this mode the register value represents the
minimum number of marks required to clear digital LOS. This
variable is named MINMARKS.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 33. Loopback Enable Page Register, 10h
Address
Description
Name
Status
Bit
Function
Bit 7 inverts the RCLK, when set to 1.
This bit controls the RCLK qualifying edge for RPOS/
RNEG/RDATA. In default Bit 7 is 0 and the data is
clocked out from the LIU on RPOS/RNEG/RDATA with
falling edge of the RCLK.
7
When bit 7 is set to 1 the RPOS/RNEG/RDATA is clocked
on the rising edge of RCLK.
6, 5
4
Reserved: write as “0”
DLOOP, Digital, Loopback is enabled this bit is set to 1.
NOTE: Write 0 to disable DLOOP.
Transmit Network Loop Down code is enabled when this
bit is set to 1.
Loopback
Enable Register
10h
LER
R/W
3
NOTE: Write 0 to disable Transmit Loop Down code
Transmit Network Loop Up code is enabled when this bit
is set to 1.
2
1
0
NOTE: Write 0 to disable Transmit Loop Up code
NLOOP, Network Loopback detection is enabled when
this bit is set to ‘1’.
RLOOP, Remote loopback is enabled when this bit is set
to ‘1’.
NOTE: Write 0 into this bit to disable RLOOP.
NOTE: Upon reset, restored default value is 0h.
74
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 34. Interrupt Enable Page Register, 11h
Address
Description
Name
Status
Bit
Function
7:5
Reserved: write as “0”
DJA Underflow Interrupt Enable. When this bit is set to 1,
an interrupt will be generated when DJA Underflow
occurs.
4
3
NOTE: Write 0 to mask this interrupt
DJA Overflow Interrupt Enable. When this bit is set to 1,
an interrupt will be generated when DJA overflow occurs.
NOTE: Write 0 to mask this interrupt
NLOOP detection Interrupt Enable. This bit enables
NLOOP detection interrupt when set to 1. The device
responds to two different NLOOP codes; loop up and
loop down.
Interrupt Enable
Register
11h
IER
R/W
2
NOTE: Write 0 to disable NLOOP detection interrupt.
AIS Interrupt Enable. AIS interrupt will be generated
when this bit is set to 1 and AIS is received on this port.
1
0
NOTE: Write 0 to disable AIS interrupt
LOS Interrupt Enable. LOS interrupt will be generated
when this bit is set to 1 and LOS occurs.
NOTE: Write 0 into this bit to disable LOS interrupt.
NOTE: Upon reset, restored default value is 0h.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 35. Alarm Status One Page Register, 12h
Address
Description
Name
Status
Bit
Function
7:4
Bits 7 to 4 not used.
DJA overflow status bit. 1 = DJA overflow has occurred.
•
•
0 = No oveflow in DJA.
3
2
A change in the status of this bit will generate DJA
Overflow Interrupt if enabled.
DJA underflow status bit:
•
•
•
1 = DJA underflow has occurred.
0 = No underflow in DJA.
A change in the status of this bit will generate DJA
Underflow Interrupt if enabled.
NLOOP detection status bit:
•
NLOOP detection works only after bit 1 in register
10h is set to 1.
Alarm Status
Register 1
12h
SR1
R
•
This bit is 1 when Loop up code is detected and it
remains in this status until Loop down code is
detected.
1
•
•
Loop down code detection will terminate the
loopback and clear this bit.
Each transition of this bit results in an Interrupt if
enabled.
AIS (All Ones) detection status:
•
1 = All Ones data pattern is detected. The device will
generate an AIS interrupt if enabled.
0
•
•
0 = data pattern different than All Ones.
A transition in the status of this bit results in AIS
interrupt generation if enabled.
NOTE: Upon reset, restored default value is 0h.
76
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 36. Interrupt Status Two Page Register, 13h
Address
Description
Name
Status
Bit
Function
7:5
Bits 7 to 5 not used.
LOS interrupt status:
•
1 = LOS Interrupt is generated. Reading this bit by
CPU will clear this interrupt.
4
3
2
1
0
•
0 = Interrupt cleared or no interrupt.
DJA overflow interrupt status:
•
1 = DJA underflow Interrupt is generated. Reading
this bit by CPU will clear this interrupt.
•
0 = Interrupt cleared or no interrupt.
DJA underflow interrupt status:
Interrupt Status
Register 2
13h
SR2
R
•
1 = DJA underflow Interrupt is generated. Reading
this bit by CPU will clear this interrupt.
•
0 = Interrupt cleared or no interrupt.
NLOOP interrupt status:
•
1 = NLOOP Interrupt is generated. Reading this bit
by CPU will clear this interrupt.
•
0 = Interrupt cleared or no interrupt.
AIS interrupt status:
•
1 = AIS Interrupt is generated. Reading this bit by
CPU will clear this interrupt.
•
0 = Interrupt cleared or no interrupt.
NOTE: Upon reset, restored default value is 0h.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 37. Line Coding Control One Page Register, 1Ch
Address
Description
Name
Status
Bit
Function
Excess Zeros mode. This bit defines criterion for
excess zeros detection.
•
0 = Excess Zeros criterion are defined by ANSI
(see Table 13)
7
•
1 = Excess Zeros criterion are defined by FCC
(see Table 13 for more information)
Bits
6:5
Decode bits 6 to 5 selecting BPV Counter
mode
•
Enable counting of both BPVs and
Excess Zero
0h
6:5
1h
2h
3h
•
•
•
Enable counting of BPVs only
Enable counting of Excess Zeros only
Invalid code
E1AIS_Sel. This bit selects AIS standard (refer to
Chapter 12.0, “Alarm Indication Signal (AIS)” for more
information).
4
•
•
0 = AIS complies with ITU G.775
1 = ETSI 300233
1Ch
Control Register 1
CR1
R/W
Transmit B8ZS/HDB3 enable
3
2
•
•
0 = AMI encoder is enabled
1 = HDB3/B8ZS encoder is enabled
Receive B8ZS/HDB3 enable
•
•
0 = AMI decoder is enabled
1 = HDB3/B8ZS decoder is enabled
Transmit Unipolar/Bipolar select
•
0 = Bipolar Mode is enabled in the transmit
direction
1
0
•
1 = Unipolar Mode is enabled in the transmit
direction. Data is transmitted as TXDATA, not
TPOS/TNEG.
Receive Unipolar/Bipolar select
•
0 = Bipolar Mode is enabled in the receive
direction
•
1 = Unipolar Mode is enabled in the receive
direction. The receive data is output on RXDATA
not on RPOS/RNEG lines.
NOTE: Upon reset, restored default value is 0h.
78
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 38. JA Control Two Page Register, 1Dh
Address
Description
Name
Status
Bit
Function
JARES
JARST
JAJC
7
6
5
1 = reset DJA’s elastic store
1 = completely reset DJA
0=jamming enabled, 1=jamming disabled
DJA depth select, 0 = 32-bits, 1 = 64-bits, bits 2, 3,
and 4 determine the DJA corner frequency.
ES64
4
3
2
JABW1, bits 2, 3, and 4 determine the DJA corner
frequency. Refer to Table 39.
1Dh
Control Register 2
R/W
JABW1
JABW0
JABW0, bits 2, 3, and 4 determine the DJA corner
frequency. Refer to Table 39.
JA transmit or
receive path
1
0
0 = JA in receive path; 1 = JA in transmit path
1 = JA enable
JA enable
NOTE: Upon reset, restored default value is 0h.
Table 39. DJA Corner Frequency Selectiona
JA Control Register
Bit 4
JA Control Register
Bit 3
JA Control Register
Bit 2
DJA Corner
Frequency
T1/E1 Mode
T1
T1
T1
T1
T1
T1
E1
E1
0
0
0
1
1
1
0
1
0
0
1
0
0
1
x
x
0
1
x
0
1
x
x
x
3
6
14
3
6
8
3
3
a.
“don’t care”
Table 40. BPV Counter High Byte Page Register, 1Eh
Address
Description
Name
Status Function
High byte of the 16-bit BPV counter shadow register
BPV counter
high byte
1Eh
BPVCTRHB
R
NOTE: Upon reset, restored default value is 0h.
Table 41. BPV Counter Low Byte Page Register, 1Fh
Address
Description
Name
Status Function
Low byte of the 16-bit BPV counter shadow register
BPV counter low
byte
1Fh
BPVCTRLB
R
NOTE: Upon reset, restored default value is 0h.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 42. Receiver Activation Logic Control Page Register 33h
Address
Description
Name
Status Function
Receiver
Activation Logic
Control
This register controls receiver activation logic. Users must write a
value of 40h into this register.
33h
RALC
R/W
Table 43. Receiver Control Page Register 1, 34h
Address
Description
Name
Status Function
Write value 00h into this register during receiver configuration
procedure. This ensures that RCLK stability stays within required
industry limits (2.048 MHz +/- 50ppm for E1 and 1.5544 MHz +/-
32ppm for T1) under LOS conditions. This register must be written
before receiver is enabled.
Receiver
Settings
34h
RWFCTRL 1
R/W
NOTE: Upon reset, restored default value is 06h.
Table 44. Transmit Coefficient Page Register Range, 40h-6Fh
Address
Description
Name
Status Function
Address
48 8-bit TX filter coefficients. Allows the user to modify
three Unit Intervals of the transmit signal.
Transmit
Coefficients for
pulse shaping
40-4F
R/W
Register Controlling coefficients for UI #1
Register Controlling coefficients for UI #2
Register Controlling coefficients for UI #3
40-6F
TXCOEF
50-5F
60-6F
NOTE: Upon reset, restored default value is 0h.
NOTE: In some cases, register 4D hex needs to be set to value FE hex (default values is FB hex) to compensate for distortion in
the undershoot section of the DSX-1 Pulse. This applies only to 0-133 ft. selection in T1 Short Haul mode.
Table 45. Receiver Control Page Register, 3Ch
Address
Description
Name
Status Function
Write value 11h to enhance receiver performance. This register
must be written before receiver is enabled. This is a write only
register.
Receiver
Settings
3Ch
RWFCTRL
W
NOTE: Upon reset, restored default value is 0h.
80
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
15.0
JTAG Boundary Scan
The LXT3108 LIU supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows
easy access to the interface pins for board testing purposes.
15.1
Architecture
Figure 23 represents the LXT3108 LIU basic JTAG architecture:
Figure 23. Intel® LXT3108 LIU JTAG Architecture
Boundry Scan Data Register
BSR
Analog Port Scan Register
ASR
Device Identification Register
MUX
TDO
TDI
IDR
Bypass Register
BYR
Instruction Register
IR
TCK
TAP
Controller
TMS
TRST
The LXT3108 LIU JTAG architecture includes a TAP Test Access Port Controller, data registers
and an instruction register. The following paragraphs describe these blocks in detail.
15.2
TAP Controller
The TAP controller is a 16-state synchronous state machine controlled by the TMS input and
clocked by TCK (see Figure 24). The TAP controls whether the LXT3108 LIU is in reset mode,
receiving an instruction, receiving data, transmitting data or in an idle state. Table 46 describes
each of the states represented in Figure 24.
.
Table 46. TAP State Description (Sheet 1 of 2)
State
Description
In this state the test logic is disabled. The device is set to normal operation mode. While
in this state, the instruction register is set to the ICODE instruction.
Test Logic Reset
Run -Test/Idle
Capture - DR
Shift - DR
The TAP controller stays in this state as long as TMS is low. Used to perform tests.
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shifts the selected test data registers by one stage toward its serial output.
Data is latched into the parallel output of the BSR when selected.
Update - DR
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 46. TAP State Description (Sheet 2 of 2)
State
Description
Capture - IR
Shift - IR
Used to load the instruction register with a fixed instruction.
Shifts the instruction register by one stage.
Update - IR
Loads a new instruction into the instruction register.
Pause - IR
Pause - DR
Momentarily pauses shifting of data through the data/instruction registers.
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
Temporary states that can be used to terminate the scanning process.
82
Preliminary Datasheet
Document Number: 249543
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 24. JTAG State Diagram
1
TEST-LOGIC
RESET
0
0
1
1
1
RUN TEST/IDLE
SELECT-DR
SELECT-IR
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
0
SHIFT-DR
SHIFT-IR
1
1
1
0
1
0
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
0
UPDATE-DR
UPDATE-IR
1
0
1
0
Preliminary Datasheet
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Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
15.3
JTAG Register Description
The following paragraphs describe each of the registers represented in Figure 23.
15.3.1
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply
and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register.
Bidirectional pins or three-statable pins require more than one position in the register. Data into the
BSR is shifted in LSB first.
15.3.2
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT3108 LIU
revision. The register is arranged per IEEE 1149.1 and is represented in Table 47. Data into the IDR
is shifted in LSB first.
Table 47. Device Identification Register (IDR)
Bit #
Value
Comments
Revision Number “B2”
0010
0011
31 - 28
Revision Number “B3”
27 - 12
11 - 1
0
0000110000100100
Part Number = 3108
Manufacturer ID
Set to “1”
00000001001
1
15.3.3
15.3.4
Bypass Register (BYR)
The Bypass Register is a 1-bit register that allows direct connection between the TDI input and the
TDO output.
Instruction Register (IR)
The IR is a 3-bit shift register that loads the instruction to be performed. The instructions are
shifted LSB first. Table 48 shows the valid instruction codes and the corresponding instruction
description.
Table 48. Instruction Register (IR) (Sheet 1 of 2)
Instruction
Code #
Comments
Connects the BSR to TDI and TDO. Input pins values are loaded
into the BSR. Output pins values are loaded from the BSR.
EXTEST
000
Connects the ASR to TDI and TDO. Allows voltage forcing/
sensing through AT1 and AT2.
INTEST_ANALOG
010
84
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 48. Instruction Register (IR) (Sheet 2 of 2)
Instruction
Code #
Comments
Connects the BSR to TDI and TDO. The normal path between the
Intel® LXT3108 LIU logic and the I/O pins is maintained. The BSR
is loaded with the signals in the I/O pins.
SAMPLE/PRELOAD
100
IDCODE
BYPASS
110
111
Connects the IDR to the TDO pin.
Serial data from the TDI input is passed to the TDO output through
the 1-bit Bypass Register.
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
16.0
Test Specifications
Table 49. Absolute Maximum Ratings
Parameter
Sym
Min
Max
Unit
TXVCC, AVCC,
QVCC, VCCIO
DC supply (reference to GND)
-0.5
3.6
V
Input voltage, RTIP/RRING
VRX
VIN
GND - 0.5
VCCIO + 0.5
V
V
Input voltage, any digital pin
Input current, any pin
GND-0.5
5.5
10
IIN
-
mA
°C
Storage temperature
TSTG
θJA
θJA
VIN
-65
150
16
Thermal Resistance, junction to ambient, QFP
Thermal Resistance, junction to ambient, PBGA
ESD voltage, any pin1, 2
°C/W
°C/W
V
17.7
–
2000
Caution: Operation at these limits may permanently damage the device. Normal operation at these extremes not guaranteed.
1. Human body model.
2. This is a design target and not a product specification.
Table 50. Recommended Operating Conditions
Parameter
Sym
Min
Typ1
Max
Unit
Test Conditions
TXVCC,
AVCC,
QVCC,
VCCIO
DC supply
3.135
3.3
3.465
V
3.3 V +/- 5%
Ambient operating temperature
SH
TA
PD
PD
PD
PD
PD
PD
-40
–
–
85
2.95
2.3
2.5
–
° C
W
W
W
W
W
W
2.5
1.9
2.1
1.8
2.4
1.9
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
–
T1
Total
–
power
LH
dissipation2
–
–
2.8
2.25
SH/
LH
E1
–
25
27.5
30
For T1 mode.
For J1 mode.
Recommended line load to TTIP/
TRING3
RL
–
–
Ω
For E1, 120 Ω±twisted pair.
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Power dissipation specifications include power to the load and power dissipated on the device.
3. This is the load applied directly to the transmitter (TTIP/TRING). The load on the line-side is 100 Ω±for T1 110 Ω±for J1, and
120 Ω±E1.
86
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 51. Electrical Characteristics (Over Recommended Operating Conditions)
Parameter
High level input voltage1
Sym
Min
Typ
Max
Unit
Test Conditions
VIH
VIL
2
–
–
–
5
0.8
VCCIO
0.4
10
V
V
In idle and power down
Low level input voltage1
Output High voltage2
VOH
VOL
IDDQ
ILL
2.4
–
V
Iout = 400 µ A
Output Low voltage2
–
–
–
–
–
–
V
Iout = 2.0 mA
Quiescent current
–
µA
µA
µA
µA
ns
Input leakage current
–
50
Three-state leakage current (all outputs)
TTIP/TRING leakage current
Rise time on the signal on digital I/Os
I3L
–
10
ITR
–
8.3
10
In idle and power down
1 pF load
TR
–
1. Intel® LXT3108 LIU interface via CMOS logic levels.
2. Output drivers will output TTL logic levels.
Table 52. E1 Transmitter Analog Characteristics
Parameter
Sym
Min.
Typ.
Max.
Unit
Test Condition
Internal transmitter impedance tolerance
–
–
3
5
%
Matching line load
Output pulse
120 Ω±Twisted pair
amplitude
–
–
2.7
3.0
–
3.3
0.3
V
V
Tested at the line side
Peak voltage of a
120 Ω±Twisted pair
space
-0.3
0
Transmit amplitude variation with supply
Difference between pulse sequences
–
–
–
–
±0.5
–
±1
200
–
%
mV
dB
dB
For 17 consecutive pulses
Transmit return loss 51 kHz to 102 kHz
6
8
16
12
120 Ω±twisted pair
102 kHz to 2.048 MHz
cable. Measured
–
with PRBS
pattern.1
2.048 MHz to 3.072 MHz
–
8
10
–
dB
Transmit intrinsic jitter; 20 Hz to 100 kHz
–
–
–
–
.025
500
500
.05
550
550
UI
ns
ns
Tx path TCLK is jitter free
Bipolar mode
Transmit path delay
500
500
JA Disabled, encoders are
disabled.
Unipolar mode
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
Table 53. E1 Receiver Analog Characteristics (Sheet 1 of 2)
Parameter
Sym
Min.
Typ.1
Max.
Unit
Test Condition
@1024 kHz
Permissible cable attenuation
–
–
–
–
38
–
dB
dB
Receiver
sensitivity
@ 1024 kHz
(E1 line loss)
(E1 SH/12 dB)
(E1 LH/36 dB)
13.6
15
Receiver sensitivity
@ 1024 kHz
–
38
39
–
dB
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
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Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 53. E1 Receiver Analog Characteristics (Sheet 2 of 2)
Parameter
Sym
Min.
Typ.1
Max.
Unit
Test Condition
Per G.703, O.151 @ 6 dB
cable Attenuation
Signal to noise interference margin
S/I
16
–
–
dB
1 Hz
–
–
–
–
–
–
–
–
–
–
–
37
1.5
0.2
–
–
–
–
–
UI
UI
Low limit
G.823 recommendation
Cable Attenuation is 6 dB
input jitter
tolerance 2
20 Hz to 2.4 kHz
100 kHz
–
–
UI
Differential receiver input impedance
Common mode input impedance to ground
51 kHz - 102 kHz
Input return
102 - 2048 kHz
loss2
10
3.5
14
22
19
0.06
5
12
3.8
–
k Ω
M Ω
dB
dB
dB
UI
@1.024 MHz
–
12
18
14
–
–
2048 kHz - 3072 kHz
–
Receive intrinsic jitter, RCLK output
0.1
6
Wide band jitter
Bipolar mode
Receivepath
–
UI
JA disabled, decoder
disabled.
delay
Unipolar mode
–
5
6
UI
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
Table 54. T1 Transmitter Analog Characteristics (Sheet 1 of 2)
Parameter
Sym
Min.
Typ.1
Max.
Unit
Test Condition
Internal transmitter impedance tolerance
Output pulse amplitude
–
–
–
–
± 3
3.0
–
± 5
3.6
%
V
Matching line load
2.4
Measured at the DSX
Peak voltage of a space
-0.15
+0.15
V
Transmit amplitude variation with power
supply
–
–
±0.5
±1
%
Difference between pulse sequences
Pulse width variation at half amplitude1
–
–
–
–
–
–
200
20
mV
ns
For 17 consecutive
pulses, GR-499-CORE
mA
RMS
Line-side short circuit current (T1)
10Hz - 8 KHz
–
–
80
100
–
–
–
–
–
–
–
–
–
–
–
–
0.025
0.025
0.05
UIpk-pk
UIpk-pk
UIpk-pk
UIpk-pk
8KHz - 40 KHz
Jitter added by
AT&T Pub 62411
TCLK is jitter free
Transmitter2
10Hz - 40 KHz
Wide Band
0.05
Output power
T1.102 - 1993
levels3
@ 772 KHz
–
12.6
–
17.9
dBm
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
3. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern.
88
Preliminary Datasheet
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LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 54. T1 Transmitter Analog Characteristics (Sheet 2 of 2)
Parameter
Sym
Min.
Typ.1
Max.
Unit
Test Condition
39 KHz - 77 KHz
77- 1544 KHz
–
–
–
–
–
6
8
10
13
–
–
dB
dB
dB
ns
Transmit Return
Loss 2
1544 KHz - 2316KHz
Bipolar mode
8
11
–
600
600
650
650
700
700
JA disabled, encoders
are disabled.
Transmit path delay
Unipolar mode
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
3. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern.
Table 55. T1 Receiver Analog Characteristics
Parameter
Sym
Min.
Typ.1
Max.
Unit
Test Condition
@ 772 KHz
Permissible cable attenuation
–
–
–
–
–
36
36
dB
dB
Receiver
(T1 SH/12 dB)
13.6
sensitivity
@ 772 kHz
(T1 line loss)
Receiver sensitivity
@ 772 kHz (T1 line loss)
(T1 LH/36 dB)
–
40
–
–
dB
Signal to noise interference margin
S/I
–
16
138
28
0.4
–
14
–
–
–
dB
UI
1 Hz
Low limit
input jitter
10 Hz to 300 Hz
–
–
–
UI
AT&T Pub. 62411
@772 kHz
tolerance 2
10 KHz to 100 KHz
–
–
–
UI
Differential receiver input impedance
Common mode input impedance to ground
39 KHz - 77KHz
Input return
77- 1544 KHz
loss1
–
600
3.5
21
26
20
630
3.8
–
Ω
–
–
MΩ
dB
dB
dB
–
12
18
14
–
–
1544 KHz - 2316 KHz
–
–
Wide band jitter, JA is
disabled.
Receive intrinsic jitter, RCLK output2
–
–
0.03
0.05
UI
Bipolar mode
Receive
–
–
–
–
55
66
–
UI
UI
JA disabled
path delay
Unipolar mode
TBD
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
Table 56. Master and Transmit Clock Timing Characteristics
Parameter
Master clock frequency2
Sym
Min
Typ1
Max
Unit
Notes
Must be
supplied
MCLK
1.544
–
16.384
MHz
Master clock tolerance
Master clock duty cycle
MCLKt
MCLKd
–
±50
–
–
ppm
%
40
60
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. MCLK frequency options are listed in Table 2 on page 35.
Preliminary Datasheet
Document Number: 249543
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89
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 56. Master and Transmit Clock Timing Characteristics
Parameter
Sym
Min
Typ1
Max
Unit
Notes
T1 Transmit clock frequency
E1 Transmit clock frequency
Transmit clock tolerance
TCLK
TCLK
TCLKt
TCLKd
Tsut
–
–
1.544
–
–
MHz
MHz
ppm
%
2.048
–
–
–
–
–
±50
90
–
Transmit clock duty cycle
10
10
10
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
ns
Tht
–
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. MCLK frequency options are listed in Table 2 on page 35.
Figure 25. Transmit Clock Timing Diagram
TCLK
Tsut
Tht
TPOS
TNEG
90
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 57. Jitter Attenuator Characteristics
Parameter
Min.
Typ.1
Max.
Unit
Test Condition
32bit
FIFO
–
2.5
–
Hz
JACF=0
JACF=1
JACF=0
JACF=1
64bit
FIFO
–
–
–
–
–
–
–
3.5
2.5
3.5
3
–
–
–
–
–
–
–
Hz
Hz
Hz
Hz
Hz
Hz
Hz
E1 jitter attenuator 3dB
corner frequency
32bit
FIFO
64bit
FIFO
32bit
FIFO
Sinusoidal jitter modulation
64bit
FIFO
3
T1 jitter attenuator 3dB
corner frequency
32bit
FIFO
6
64bit
FIFO
6
E1
T1
–
–
3.5
6
–
–
Hz
Hz
Jitter attenuator 3dB corner frequency2
32bit
FIFO
–
–
–
–
16
32
24
56
–
–
–
–
UI
UI
UI
UI
Delay through the Jitter attenuator
only.
Data latency
64bit
FIFO
32bit
FIFO
Input jitter tolerance before FIFO
overflow or underflow
64bit
FIFO
@ 3 Hz
–
–
–
–
–
–
–
–
–
-0.5
-0.5
+19.5
+19.5
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
@ 40 Hz
E1 jitter
ITU-T G.736
attenuation3
@ 400 Hz
@ 100 KHz
@ 1 Hz
@ 20 Hz
0
T1 jitter
attenuation
@ 1 KHz
33.3
40
AT&T Pub. 62411
@ 1.4 KHz
@ 70 KHz
40
(See
Note 3)
Output jitter in remote loopback2
–
–
–
UI
ETSI CTR12/13 Output jitter
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Guaranteed by design and other correlation methods.
3. See Figure 27, “Intel® LXT3108 LIU Output Jitter for CTR12/13 Applications” on page 93.
Preliminary Datasheet
Document Number: 249543
Revision #: 008
91
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 58. Receive Timing Characteristics for T1 Operation
Parameter
Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
T1 Receive clock pulse width 2, 3
T1 Receive clock pulse width High
T1 Receive clock pulse width Low1,3
RPOS/RNEG to RCLK rising time
RCLK rising to RPOS/RNEG hold time
648
324
324
274
274
tPWH
tPWL
tSUR
tHR
–
–
260
–
388
–
–
–
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are
for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 59. Receive Timing Characteristics for E1 Operation
Parameter
E1 Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
E1 Receive clock pulse width 2, 3
E1 Receive clock pulse width High
E1 Receive clock pulse width Low1,3
RPOS/RNEG to RCLK rising time
RCLK rising to RPOS/RNEG hold time
488
244
244
194
194
tPWH
tPWL
tSUR
tHR
–
–
195
–
293
–
–
–
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are
for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Figure 26. Receive Clock Timing Diagram
tPW
RCLK
tPWH
tSUR
tPWL
tHR
RPOS
RNEG
RCLK_INV = 0 (bit 7 in reg. 10h = 0)
tSUR
tHR
RPOS
RNEG
RCLK _INV = 1 (bit 7 in reg. 10h = 1
92
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 27. Intel® LXT3108 LIU Output Jitter for CTR12/13 Applications
0.2
0.15
0.1
Minimum CTR12/13 Performance Requirement
Intel® LXT3108 LIU Typical Performance
0.05
0
10 Hz
20 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
B0015-01
Figure 28. JTAG Timing
tCYC
TCK
tSUR
tHT
TMS
TDI
tDOD
TDO
Table 60. JTAG Timing Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
Cycle time
Tcyc
Tsut
Tht
200
50
50
-
–
–
–
–
–
–
ns
ns
ns
ns
J-TMS/J-TDI to J-TCK rising edge time
J-CLK rising to J-TMS/L-TDI hold time
J-TCLK falling to J-TDO valid
–
Tdod
50
Preliminary Datasheet
Document Number: 249543
Revision #: 008
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Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 61. G.703 2.048 Mbps Pulse Mask Specifications
Cable
Parameter
Unit
TWP
Coax
Test load impedance
120
3.0
75
Ω
V
Nominal peak mark voltage
2.37
Nominal peak space voltage
0 ±0.30
244
0 ±0.237
244
V
Nominal pulse width
ns
%
%
Ratio of positive and negative pulse amplitudes at center of pulse
Ratio of positive and negative pulse amplitudes at nominal half amplitude
95-105
95-105
95-105
95-105
Figure 29. E1, G.703 Mask Templates
Table 62. T1.102 1.544 Mbps Pulse Mask Specifications
Cable
Parameter
Unit
TWP
Test load impedance
100
3.0
Ω
V
Nominal peak mark voltage
Nominal peak space voltage
Nominal pulse width
0 ±0.15
324
V
ns
%
Ratio of positive and negative pulse amplitudes
95-105
94
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 30. Intel® LXT3108 LIU Jitter Tolerance Performance
1000 UI
TBD
Intel®
LXT3108 LIU
100 UI
10 UI
28 UI @
4.9 Hz
AT&T 62411, Dec 1990 (T1)
18 UI @
1.8 Hz
28 UI @
300 Hz
GR-499-CORE, Dec 1995 (T1)
5 UI @
500 Hz
ITU G.823, Mar 1993 (E1)
1 UI
1.5 UI @
2.4 kHz
1.5 UI @
20 Hz
0.4 UI @
10 kHz
0.2 UI @
18 kHz
0.1 UI @
8 kHz
0.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
B0342-01
Preliminary Datasheet
Document Number: 249543
Revision #: 008
95
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 31. Intel® LXT3108 LIU Jitter Transfer Performance
E1
10 dB
ITU G.736 Template
0.5 dB @ 3 Hz
0.5 dB @ 40 Hz
0 dB
-10 dB
-19.5 dB @ 20 kHz
-19.5 dB @ 400 Hz
-20 dB
-30 dB
Intel® LXT3108 LIU
-40 dB
-60 dB
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
B0343-01
T1
10 dB
0 dB
0 dB @ 20 Hz
0.1 dB @ 20 Hz
0.5 dB @ 350 Hz
0 dB @ 1 Hz
AT&T Pub 62411
GR-253 CORE
TR-TSY-000009
-6 dB @ 2 Hz
-10 dB
-20 dB
-30 dB
-33.3 dB @ 1 kHz
Intel®
LXT3108 LIU
-33.7 dB @ 2.5 kHz
-40 dB @ 1.4 kHz
-40 dB @ 70 kHz
-49.2 dB @ 15 kHz
-40 dB
-60 dB
-60 dB @ 57 Hz
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
B0344-01
96
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
16.1
Microprocessor Interface Timing Diagrams
Figure 32. MPC860 Write Timing
Table 63. MPC860 Write Timing Characteristics
Symbol
Parameter
Min.
Max
Unit
Tadrs
Tadrh
Tadss
Tadsh
Trws
Tcss
Address setup to clock
Address hold from clock
TS# setup to clock
15
13
6
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
--
TS# hold from clock
2
--
R/W# setup to clock
10
5
--
CS# setup to clock
--
Trwh
Tds
R/W# and CS# hold from clock
Data setup to clock
0
--
7
--
Tdh
Data hold from clock
clock to TA# asserted
clock to TA# deasserted
16
12
12
--
Trdys
Trdyh
16
16
Preliminary Datasheet
Document Number: 249543
Revision #: 008
97
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 33. MPC860 Read Timing
Table 64. MPC860 Read Timing Characteristics
Symbol
Tadrsr
Parameter
Min.
Max
Unit
Address setup to clock
Address hold from clock
TS# setup to clock
10
10
6
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tadrhr
Tadss
Tadsh
Trwsr
Tcss
--
TS# hold from clock
R/W# setup to clock
CS# setup to clock
2
--
8
--
5
--
Trwh
R/W#, CS hold to clock
clock to data valid
0
--
Tdd
--
41
26
23
16
16
Tdhwr
Tdhcs
Trdys
Trdyh
Data hold from R/W#
Data hold from CS#
clock to TA# asserted
clock to TA# deasserted
18
16
12
12
98
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 34. M68302 Write Timing
Table 65. M68302 Write Timing Characteristics
Symbol
Parameter
Min.
Max
Unit
Tadss
Tadsh
Trdss
Address setup to LDS asserted
Address hold from LDS asserted
R/W# setup to LDS asserted
R/W# hold from LDS asserted
Data setup to LDS asserted
Data hold from LDS asserted
LDS minimum width
-8
44
0
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
Trdsh
0
Tddss
Tddsh
Tdsmin
Tcsdss
Tcsdsh
-17
46
60
3
CS to DS setup
CS to DS hold
4
Preliminary Datasheet
Document Number: 249543
Revision #: 008
99
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 35. M68302 Read Timing
Table 66. M68302 Read Timing Characteristics
Symbol
Parameter
Min.
Max
Unit
Tadss
Tadsh
Trdss
Address setup to LDS asserted
Address hold from LDS assserted
R/W# setup to LDS asserted
R/W# hold from LDS asserted
LDS low to data valid
24
41
0
--
--
ns
ns
ns
ns
ns
ns
ns
--
Trdsh
Tdsdd
Tdsdh
Tdsmin
0
--
--
71
--
Data hold from LDS deasserted
LDS minimum width
17
71
--
100
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 36. Intel® i486TM/i960® Non-muxed Mode Write Timing
CLK (MPI_CLK)
Tadrh
Tadrs
ADR (AD)
Tadsh
Tadss
ADS# (DS)
W/R# (RW)
CS# (CS)
Trws
Trwh
Trws
Trwh
Tdh
Tds
Data (D(7:0))
RDY# (RDY)
Trdyh
Trdys
Figure 37. Intel® i960® Muxed Mode Write Timing
CLK (MPI_CLK)
Tadrh
Tadrs
Tdh
Tds
AD (AD)
Tadsh
Tadss
ADS# (DS)
W/R# (RW)
CS# (CS)
Trws
Trws
Trwh
Trwh
Trdyh
Trdys
RDY# (RDY)
Preliminary Datasheet
Document Number: 249543
Revision #: 008
101
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Table 67. Intel® i486TM/i960® Write Timing Characteristics
Symbol
Parameter
Min.
Max
Unit
Tadrs
Tadrh
Tadss
Tadsh
Trws
Trwh
Tds
Address setup to clock
Address hold from clock
ADS setup to clock
7
5
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
--
ADS hold from clock
2
--
W/R# and CS# setup to clock
W/R# and CS# hold from clock
Data setup to clock
10
0
--
--
7
--
Tdh
Data hold from clock
16
13
13
--
Trdys
Trdyh
clock to READY# asserted
clock to READY# deasserted
16
16
Figure 38. Intel® i486TM/i960® Non-muxed Mode Read Timing
102
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 39. Intel® i960® Muxed Mode Read Timing
CLK (MPI_CLK)
Tadrh
Tadrs
Tdd
AD (AD)
Tadsh
Tadss
ADS# (DS)
W/R# (RW)
CS# (CS)
Tdhwr
Tdhcs
Trwh
Trwsr
Trwsr
Trwh
Trdys
Trdyh
RDY# (RDY)
Table 68. Intel® i486TM/i960® Read Timing Characteristics
Symbol
Parameter
Min.
Max
Unit
Tadrs
Tadrh
Tadss
Tadsh
Trwsr
Trwh
Address setup to clock
Address hold from clock
ADS setup to clock
7
5
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
--
ADS hold from clock
2
--
W/R# and CS setup to clock
W/R# and CS hold from clock
clock to Data valid
8
--
0
--
Tdd
--
41
27
24
16
16
Tdhwr
Tdhcs
Trdys
Trdyh
Data hold from R/W#
18
16
13
13
Data hold from CS#
clock to READY# asserted
clock to READY# deasserted
Preliminary Datasheet
Document Number: 249543
Revision #: 008
103
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
16.2
Referenced Standards
AT&T Pub 62411 Accunet T1.5 Service
Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives
Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria
Bellcore GR-499-CORE Transport Systems Generic Requirements
ANSI T1.102 - 199X Digital Hierarchy Electrical Interface
ANSI T1.231 -1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance
Monitoring
ETSI CTR12/13 Business TeleCommunications (BTC): 2048 Kbps Digital Unstructured/
Structured Leased Line.
ETS 300166 Physical and Electrical Characteristics
G.703 Physical/electrical characteristics of hierarchical digital interfaces
G.735 Characteristics of Primary PCM multiplex equipment operating at 2048 kbps and offering
digital access at 384 kbps and/or synchronous digital access at 64 kbps
G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbps
G.742 General Aspects of Digital Transmission Systems
G.772
Protected Monitoring Points provided on Digital Transmission Systems
G.775 Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria
G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks
G.823
The control of jitter and wander within digital networks which are based on the 2048
kbps hierarchy
O.161 In - service code violations monitors for digital systems. Blue Book Fasc.IV.4
BAPT220 Short Circuit Current Requirements
ITU I.431Primary Rate ISDN User-Network Interface - Layer 1
ETS 300 233Integrated Services Digital Network (ISDN); Access digital section for ISDN primary
rate.
104
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
17.0
Mechanical Specification
Figure 40. Intel® LXT3108 LIU 256 PBGA Mechanical Specification
17.00 ±0.10
7.00 REF
1.00 REF
15.00
PIN #A1
CORNER
1.00
PIN #A1
CORNER
A
B
C
D
E
F
PIN #A1 ID
0.50
7.00
REF
1.00
G
H
J
17.00
±0.10
15.00 ±0.05
K
L
M
N
P
R
T
16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
1.00 REF
TOP VIEW
BOTTOM VIEW
1.80
MAX
0.70
±0.05
NOTE:
1. ALL DIMENSIONS IN MILLIMETERS.
0.35
MIN
2. ALL DIMENSIONS AND TOLERANCES
CONFORM TO ASME Y 14.5M-1994.
3. TOLERANCE = ± 0.05 UNLESS
SPECIFIED OTHERWISE.
0.56
± 0.04
SEATING PLANE
SIDE VIEW
Preliminary Datasheet
Document Number: 249543
Revision #: 008
105
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Figure 41. Intel® LXT3108 LIU 208 Pin QFP Mechanical Specifications
Millimeters
Dim
D
Min
Max
D1
A
-
4.10
-
A1
A2
0.25
3.20
3.60
0.27
e
b
0.17
E1
E
D
30.30
27.70
30.30
27.70
30.90
28.30
30.90
28.30
D1
E
e
/
2
E1
e
.50 BASIC
1.30 REF
L
0.50
0.75
θ2
L1
θ1
θ2
θ3
L1
0°
5°
5°
7°
A2
A
16°
16°
θ
A1
θ3
b
L
106
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
18.0
Glossary
Term Categories
Term
ADC
Term Definition
Analog to Digital Converter
AFE
Analog Front End
AGC
Automatic Gain Control
ATWG
Arbitrary Transmit Wave Generation
BPV
BSR
BYR
CLAD
DAC
DJA
DSP
FIR
Bi-Polar Violation
Boundary Scan Register
BYpass Register
CLock ADapter
Digital to Analog Converter
Digital Jitter Attenuator
Digital Signal Processor
Finite Infinite Response
Graphical User Interface
Intel® Hitless Protection Switching, Intel® HPS
Integrated Access Devices
Device Identification Register
Integrated Multi-service Access Platforms
Instruction Register
GUI
HPS
IADs
IDR
IMAPs
IR
JTAG
LIU
Joint Test Action Group
Line Interface Unit
LH
Long Haul
LH/SH
LOS
NRZ
PBGA
Long/Short Haul
Loss Of Signal
Non-Return-to-Zero
Plastic Ball Grid Array
Preliminary Datasheet
Document Number: 249543
Revision #: 008
107
Rev. Date: January 08, 2003
LXT3108 LIU Octal T1/E1/J1 Long/Short Haul Line Interface Unit
POR
PPR
PPRB
PPS
Power On Reset
Port Page Register
Port Page Register Bank
Port Page Select
PTM
QFP
SH
Intel® Pulse Template Matching, Intel® PTM
Quad Flat Pack
Short Haul
TBD
TAOS
UI
To Be Determined
Transmit All Ones
Unit Interval
108
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
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