GD80960JS-25_技术文档

PRELIMINARY

80960JD

EMBEDDED 32-BIT MICROPROCESSOR

■ Pin/Code Compatible with all 80960Jx

■ High Bandwidth Burst Bus

Processors

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

■ High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is 2x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

■ New Instructions

— Conditional Add, Subtract and Select

— Processor Management

— User/Supervisor Protection Model

■ High-Speed Interrupt Controller

— 31 Programmable Priorities

■ Two-Way Set Associative Instruction Cache

— 80960JD - 4 Kbyte

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

— Programmable Cache Locking

Mechanism

■ Two On-Chip Timers

■ Direct Mapped Data Cache

— 80960JD - 2 Kbyte

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

— Write Through Operation

■ Halt Mode for Low Power

■ On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

Interrupts

■ IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

■ Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack (PQFP)

■ On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

132

PIN 1

99

A80960JD

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i960

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19xx

i

NG80960JD

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M

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33

66

Figure 1. 80960JD Microprocessor

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

September 1995

Order Number: 272596-002

80960JD

EMBEDDED 32-BIT MICROPROCESSOR

1.0 PURPOSE ..................................................................................................................................................1

2.0 80960JD OVERVIEW ................................................................................................................................1

2.1 80960 Processor Core ........................................................................................................................2

2.2 Burst Bus ............................................................................................................................................2

2.3 Timer Unit ...........................................................................................................................................3

2.4 Priority Interrupt Controller ..................................................................................................................3

2.5 Instruction Set Summary ....................................................................................................................3

2.6 Faults and Debugging .........................................................................................................................3

2.7 Low Power Operation .........................................................................................................................4

2.8 Test Features ......................................................................................................................................4

2.9 Memory-Mapped Control Registers ....................................................................................................4

2.10 Data Types and Memory Addressing Modes ....................................................................................4

3.0 PACKAGE INFORMATION .......................................................................................................................6

3.1 Pin Descriptions ..................................................................................................................................6

3.1.1 Functional Pin Definitions .........................................................................................................6

3.1.2 80960Jx 132-Lead PGA Pinout ..............................................................................................13

3.1.3 80960Jx PQFP Pinout ............................................................................................................17

3.2 Package Thermal Specifications ......................................................................................................20

3.3 Thermal Management Accessories ..................................................................................................22

4.0 ELECTRICAL SPECIFICATIONS ...........................................................................................................23

4.1 Absolute Maximum Ratings ..............................................................................................................23

4.2 Operating Conditions ........................................................................................................................23

4.3 Connection Recommendations .........................................................................................................24

4.4 DC Specifications .............................................................................................................................24

4.5 AC Specifications ..............................................................................................................................26

4.5.1 AC Test Conditions and Derating Curves ..............................................................................33

4.5.2 AC Timing Waveforms ...........................................................................................................34

5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................42

6.0 DEVICE IDENTIFICATION ......................................................................................................................56

7.0 REVISION HISTORY ...............................................................................................................................56

ii

PRELIMINARY

80960JD

FIGURES

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

80960JD Microprocessor ............................................................................................................ i

80960JD Block Diagram ............................................................................................................ 2

132-Lead Pin Grid Array Bottom View - Pins Facing Up ......................................................... 13

132-Lead Pin Grid Array Top View - Pins Facing Down .......................................................... 14

132-Lead PQFP - Top View ..................................................................................................... 17

50 MHz Maximum Allowable Ambient Temperature ................................................................ 21

40 MHz Maximum Allowable Ambient Temperature ................................................................ 22

AC Test Load ........................................................................................................................... 33

Output Delay or Hold vs. Load Capacitance ............................................................................ 33

Rise and Fall Time Derating .................................................................................................... 34

CLKIN Waveform ..................................................................................................................... 34

Output Delay Waveform for T_OV1............................................................................................ 35

Output Float Waveform for T_OF............................................................................................... 35

Input Setup and Hold Waveform for T_IS1and T_IH1.................................................................. 36

Input Setup and Hold Waveform for T_IS2and T_IH2.................................................................. 36

Input Setup and Hold Waveform for T_IS3and T_IH3.................................................................. 37

Input Setup and Hold Waveform for T_IS4and T_IH4.................................................................. 37

Relative Timings Waveform for T_LXLand T_LXA........................................................................ 38

DT/R and DEN Timings Waveform .......................................................................................... 38

TCK Waveform ........................................................................................................................ 39

Input Setup and Hold Waveforms for T_BSIS1and T_BSIH1......................................................... 39

Output Delay and Output Float Waveform for TBSOV1 AND TBSOF1 ................................... 40

Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .................................... 40

Input Setup and Hold Waveform for T_BSIS2and T_{BSIH2 ...........................................................................41}

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .............................. 42

Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ............................................... 44

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45

Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus .................................................................................. 46

Figure 30.

Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian .......................... 47

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

HOLD/HOLDA Waveform For Bus Arbitration ......................................................................... 48

Cold Reset Waveform .............................................................................................................. 49

Warm Reset Waveform ........................................................................................................... 50

Entering the ONCE State ......................................................................................................... 51

Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54

Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 55

PRELIMINARY

iii

80960JD

TABLES

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

80960Jx Instruction Set ................................................................................................................5

Pin Description Nomenclature ......................................................................................................6

Pin Description — External Bus Signals ......................................................................................7

Pin Description — Processor Control Signals, Test Signals and Power ....................................10

Pin Description — Interrupt Unit Signals ....................................................................................12

132-Lead PGA Pinout — In Signal Order ...................................................................................15

132-Lead PGA Pinout — In Pin Order .......................................................................................16

132-Lead PQFP Pinout — In Signal Order ................................................................................18

132-Lead PQFP Pinout — In Pin Order .....................................................................................19

132-Lead PGA Package Thermal Characteristics ......................................................................20

132-Lead PQFP Package Thermal Characteristics ...................................................................21

80960JD Operating Conditions ..................................................................................................23

80960JD DC Characteristics ......................................................................................................24

80960JD ICC Characteristics .....................................................................................................25

80960JD AC Characteristics (50 MHz) ......................................................................................26

Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) .......................................28

80960JD AC Characteristics (40 MHz) ......................................................................................28

80960JD AC Characteristics (33 MHz) ......................................................................................31

Natural Boundaries for Load and Store Accesses .....................................................................52

Summary of Byte Load and Store Accesses ..............................................................................52

Summary of Short Word Load and Store Accesses ...................................................................52

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ..................................................53

80960JD Die and Stepping Reference .......................................................................................56

Data Sheet Version -001 to -002 Revision History .....................................................................56

iv

PRELIMINARY

80960JD

ration registers enable the processor to operate with

all combinations of bus width and data object

alignment. The processor supports a homogeneous

byte ordering model.

1.0 PURPOSE

This document contains advance information for the

80960JD microprocessor, including electrical

characteristics and package pinout information.

Detailed functional descriptions

— other than

This processor integrates two important peripherals:

a timer unit and an interrupt controller. These and

other hardware resources are programmed through

memory-mapped control registers, an extension to

the familiar 80960 architecture.

parametric performance — are published in the

i960^®Jx Microprocessor User’s Guide (272483).

Throughout this data sheet, references to “80960Jx”

indicate features which apply to all of the following:

The timer unit (TU) offers two independent 32-bit

timers for use as real-time system clocks and

general-purpose system timing. These operate in

either single-shot or auto-reload mode and can

generate interrupts.

• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte

data cache

• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache

• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache and clock doubling

The interrupt controller unit (ICU) provides a flexible

means for requesting interrupts. The ICU provides

full programmability of up to 240 interrupt sources

into 31 priority levels. The ICU takes advantage of a

cached priority table and optional routine caching to

minimize interrupt latency. Clock doubling reduces

interrupt latency by 40% compared to the

80960JA/JF. Local registers may be dedicated to

high-priority interrupts to further reduce latency.

Acting independently from the core, the ICU

compares the priorities of posted interrupts with the

current process priority, off-loading this task from the

core. The ICU also supports the integrated timer

interrupts.

• 80L960JA — 3.3 V version of the 80960JA

• 80L960JF — 3.3 V version of the 80960JF

2.0 80960JD OVERVIEW

The 80960JD offers high performance to cost-

sensitive 32-bit embedded applications. The

80960JD is object code compatible with the 80960

Core Architecture and is capable of sustained

execution at the rate of one instruction per clock.

This processor’s features include generous

instruction cache, data cache and data RAM. It also

boasts a fast interrupt mechanism, dual program-

mable timer units and new instructions.

The 80960JD features a Halt mode designed to

support applications where low power consumption

is critical. The halt instruction shuts down instruction

execution, resulting in a power savings of up to 90

percent.

The 80960JD’s clock doubler operates the processor

core at twice the bus clock rate to improve execution

performance without increasing the complexity of

board designs.

The 80960JD’s testability features, including ONCE

(On-Circuit Emulation) mode and Boundary Scan

(JTAG), provide a powerful environment for design

debug and fault diagnosis.

Memory subsystems for cost-sensitive embedded

applications often impose substantial wait state

penalties. The 80960JD integrates considerable

storage resources on-chip to decouple CPU

execution from the external bus.

The Solutions960® program features a wide variety

of development tools which support the i960

processor family. Many of these tools are developed

by partner companies; some are developed by Intel,

such as profile-driven optimizing compilers. For

more information on these products, contact your

local Intel representative.

The 80960JD rapidly allocates and deallocates local

register sets during context switches. The processor

needs to flush a register set to the stack only when it

saves more than seven sets to its local register

cache.

A 32-bit multiplexed burst bus provides a high-speed

interface to system memory and I/O.

A full

complement of control signals simplifies the

connection of the 80960JD to external components.

The user programs physical and logical memory

attributes through memory-mapped control registers

(MMRs) — an extension not found on the i960 Kx,

Sx or Cx processors. Physical and logical configu-

PRELIMINARY

1

80960JD

Control

21

Physical Region

Configuration

32-bit buses

address / data

CLKIN

PLL, Clocks,

Power Mgmt

Bus

Control Unit

4 KByte Instruction Cache

Two-Way Set Associative

Address

Data Bu

Bus Request

Queues

TAP

5

Boundary Scan

Controller

32

Instruction Sequencer

Two 32-Bit

Timers

Constants

Control

Interrup

Port

Programmable

Interrupt Controller

9

8-Set

Local Register Cache

Execution

and

Memory

Interface

Unit

Memory-Mapped

Register Interface

Multiply

Divide

Unit

Address

Generation

128

Unit

1 Kbyte

32-bit Address

32-bit Data

Global / Local

Register File

effective

address

Data RAM

SRC1 SRC2 DEST

2 Kbyte Direct

Mapped Data

Cache

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

Figure 2. 80960JD Block Diagram

• 128-bit register bus speeds local register caching

2.1 80960 Processor Core

• 4 Kbyte two-way set associative, integrated

instruction cache

The 80960Jx family is a scalar implementation of the

80960 Core Architecture. Intel designed this

processor core as a very high performance device

that is also cost-effective. Factors that contribute to

the core’s performance include:

• 2 Kbyte direct-mapped, integrated data cache

• 1 Kbyte integrated data RAM delivers zero wait

state program data

• Core operates at twice the bus speed (80960JD

only)

2.2 Burst Bus

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

A 32-bit high-performance bus controller interfaces

the 80960JD to external memory and peripherals.

The BCU fetches instructions and transfers data at

the rate of up to four 32-bit words per six clock

cycles. The external address/data bus is multi-

plexed.

• Efficient instruction pipeline minimizes pipeline

break latency

• Register and resource scoreboarding allow

overlapped instruction execution

2

PRELIMINARY

80960JD

Users may configure the 80960JD’s bus controller to

match an application’s fundamental memory organi-

zation. Physical bus width is register-programmed

for up to eight regions. Byte ordering and data

caching are programmed through a group of logical

memory templates and a defaults register.

Non-Maskable Interrupt (NMI) pin. Interrupts are

serviced according to their priority levels relative to

the current process priority.

Low interrupt latency is critical to many embedded

applications. As part of its highly flexible interrupt

mechanism, the 80960JD exploits several

techniques to minimize latency:

The BCU’s features include:

• Multiplexed external bus to minimize pin count

• Interrupt vectors and interrupt handler routines can

be reserved on-chip

• 32-, 16- and 8-bit bus widths to simplify I/O

interfaces

• Register frames for high-priority interrupt handlers

can be cached on-chip

• External ready control for address-to-data, data-to-

data and data-to-next-address wait state types

• The interrupt stack can be placed in cacheable

memory space

• Support for big or little endian byte ordering to

facilitate the porting of existing program code

• Interrupt microcode executes at twice the bus

frequency

• Unaligned bus accesses performed transparently

• Three-deep load/store queue to decouple the bus

from the core

2.5 Instruction Set Summary

Upon reset, the 80960JD conducts an internal self

test. Then, before executing its first instruction, it

performs an external bus confidence test by

performing a checksum on the first words of the

initialization boot record (IBR).

The 80960Jx adds several new instructions to the

i960 core architecture. The new instructions are:

• Conditional Move

• Conditional Add

• Conditional Subtract

• Byte Swap

The user may examine the contents of the caches at

any time by executing special cache control instruc-

tions.

• Halt

• Cache Control

• Interrupt Control

2.3 Timer Unit

Table 1 identifies the instructions that the 80960Jx

supports. Refer to i960^®Jx Microprocessor User’s

Guide (272483) for a detailed description of each

instruction.

The timer unit (TU) contains two independent 32-bit

timers which are capable of counting at several clock

rates and generating interrupts. Each is programmed

by use of the TU registers. These memory-mapped

registers are addressable on 32-bit boundaries. The

timers have a single-shot mode and auto-reload

capabilities for continuous operation. Each timer has

an independent interrupt request to the 80960JD’s

interrupt controller. The TU can generate a fault

when unauthorized writes from user mode are

detected. Clock prescaling is supported.

2.6 Faults and Debugging

The 80960Jx employs a comprehensive fault model.

The processor responds to faults by making implicit

calls to a fault handling routine. Specific information

collected for each fault allows the fault handler to

diagnose exceptions and recover appropriately.

2.4 Priority Interrupt Controller

The processor also has built-in debug capabilities. In

software, the 80960Jx may be configured to detect

as many as seven different trace event types. Alter-

natively, mark and fmark instructions can generate

trace events explicitly in the instruction stream.

Hardware breakpoint registers are also available to

trap on execution and data addresses.

A programmable interrupt controller manages up to

240 external sources through an 8-bit external

interrupt port. Alternatively, the interrupt inputs may

be configured for individual edge- or level-triggered

inputs. The interrupt unit (IU) also accepts interrupts

from the two on-chip timer channels and a single

PRELIMINARY

3

80960JD

2.7 Low Power Operation

2.9 Memory-Mapped Control

Registers

Intel fabricates the 80960Jx using an advanced sub-

micron manufacturing process. The processor’s sub-

micron topology provides the circuit density for

optimal cache size and high operating speeds while

dissipating modest power. The processor also uses

dynamic power management to turn off clocks to

unused circuits.

The 80960JD, though compliant with i960 series

processor core, has the added advantage of

memory-mapped, internal control registers not found

on the i960 Kx, Sx or Cx processors. These give

software the interface to easily read and modify

internal control registers.

Users may program the 80960Jx to enter Halt mode

for maximum power savings. In Halt mode, the

processor core stops completely while the integrated

peripherals continue to function, reducing overall

power requirements up to 90 percent. Processor

execution resumes from internally or externally

generated interrupts.

Each of these registers is accessed as a memory-

mapped, 32-bit register. Access is accomplished

through regular memory-format instructions. The

processor ensures that these accesses do not

generate external bus cycles.

2.10 Data Types and Memory

Addressing Modes

2.8 Test Features

As with all i960 family processors, the 80960Jx

instruction set supports several data types and

formats:

The 80960Jx incorporates numerous features which

enhance the user’s ability to test both the processor

and the system to which it is attached. These

features include ONCE (On-Circuit Emulation) mode

and Boundary Scan (JTAG).

• Bit

• Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

• Triple word (96 bits)

• Quad word (128 bits)

The 80960Jx provides testability features compatible

with IEEE Standard Test Access Port and Boundary

Scan Architecture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ,

forces the processor to float all its output pins

(ONCE mode). ONCE mode can also be initiated at

reset without using the boundary scan mechanism.

The 80960Jx provides a full set of addressing modes

for C and assembly programming:

• Two Absolute modes

ONCE mode is useful for board-level testing. This

feature allows a mounted 80960JD to electrically

“remove” itself from a circuit board. This allows for

system-level testing where a remote tester — such

• Five Register Indirect modes

• Index with displacement

• IP with displacement

as an in-circuit emulator

processor system.

— can exercise the

The provided test logic does not interfere with

component or circuit board behavior and ensures

that components function correctly, connections

between various components are correct, and

various components interact correctly on the printed

circuit board.

The JTAG Boundary Scan feature is an attractive

alternative to conventional “bed-of-nails” testing. It

can examine connections which might otherwise be

inaccessible to a test system.

4

PRELIMINARY

80960JD

Table 1. 80960Jx Instruction Set

Arithmetic Logical

Data Movement

Load

Bit, Bit Field and Byte

Add

And

Set Bit

Store

Subtract

Not And

And Not

Or

Clear Bit

Move

Multiply

Not Bit

*Conditional Select

Load Address

Divide

Alter Bit

Remainder

Exclusive Or

Not Or

Scan For Bit

Span Over Bit

Extract

Modulo

Shift

Or Not

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

*Conditional Add

*Conditional Subtract

Rotate

Nor

Modify

Exclusive Nor

Not

Scan Byte for Equal

*Byte Swap

Nand

Comparison

Branch

Call/Return

Fault

Compare

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Conditional Fault

Conditional Compare

Call Extended

Call System

Return

Synchronize Faults

Compare and

Increment

Compare and

Decrement

Branch and Link

Test Condition Code

Check Bit

Processor

Management

Debug

Atomic

Modify Trace Controls

Mark

Flush Local Registers

Atomic Add

Modify Arithmetic

Controls

Atomic Modify

Force Mark

Modify Process

Controls

*Halt

System Control

*Cache Control

*Interrupt Control

NOTE:

Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB

implementations.

PRELIMINARY

5

80960JD

3.0 PACKAGE INFORMATION

Table 2. Pin Description Nomenclature

The 80960JD is offered in several speed and

package types. The 132-pin Pin Grid Array (PGA)

device will be specified for operation at

Symbol

Description

Input pin only.

I

O

I/O

–

V_cc= 5.0 V ± 5% over a case temperature range of

Output pin only.

0° to 85°C:

• A80960JD-50 (50 MHz core, 25 MHz bus)

Pin can be either an input or output.

Pin must be connected as described.

The 132-pin Pin Grid Array (PGA) device will be

specified for operation at V_cc= 5.0 V ± 5% over a

case temperature range of 0° to 100°C:

S

Synchronous. Inputs must meet setup

and hold times relative to CLKIN for

proper operation.

• A80960JD-40 (40 MHz core, 20 MHz bus)

S(E) Edge sensitive input

S(L) Level sensitive input

• A80960JD-33 (33.33 MHz core, 16.67 MHz bus)

The 132-pin Plastic Quad Flatpack (PQFP) devices

will be specified for operation at V_cc= 5.0 V ± 5%

over a case temperature range of 0° to 100°C:

A (...)

R (...)

Asynchronous. Inputs may be

asynchronous relative to CLKIN.

A(E) Edge sensitive input

A(L) Level sensitive input

• NG80960JD-40 (40 MHz core, 20 MHz bus)

• NG80960JD-33 (33.33 MHz core, 16.67 MHz bus)

While the processor’s RESET pin is

asserted, the pin:

For complete package specifications and infor-

mation, refer to Intel’s Packaging Handbook

(240800).

R(1) is driven to V_CC

R(0) is driven to V_SS

R(Q) is a valid output

R(X) is driven to unknown state

R(H) is pulled up to V_CC

3.1 Pin Descriptions

H (...)

While the processor is in the hold state,

the pin:

This section describes the pins for the 80960JD in

the 132-pin ceramic Pin Grid Array (PGA) package

and 132-lead Plastic Quad Flatpack Package

(PQFP).

H(1) is driven to V_CC

H(0) is driven to V_SS

H(Q) Maintains previous state or

continues to be a valid output

H(Z) Floats

Section 3.1.1, Functional Pin Definitions

describes pin function; Section 3.1.2, 80960Jx 132-

Lead PGA Pinout and Section 3.1.3, 80960Jx

PQFP Pinout define the signal and pin locations for

the supported package types.

P (...)

While the processor is halted, the pin:

P(1) is driven to V_CC

P(0) is driven to V_SS

P(Q) Maintains previous state or

3.1.1 Functional Pin Definitions

continues to be a valid output

Table 2 presents the legend for interpreting the pin

descriptions which follow. Pins associated with the

bus interface are described in Table 3. Pins

associated with basic control and test functions are

described in Table 4. Pins associated with the

Interrupt Unit are described in Table 5.

6

PRELIMINARY

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

AD31:0

I/O

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data

S(L)

R(X)

H(Z)

P(Q)

to and from memory. During an address (T ) cycle, bits 31:2 contain a physical word

a

address (bits 0-1 indicate SIZE; see below). During a data (T ) cycle, read or write

d

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,

AD15:8 and AD7:0. During write operations, unused pins are driven to determinate

values.

SIZE, which comprises bits 0-1 of the AD lines during a T cycle, specifies the

a

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

0

1

0

1

0

1

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

• write — AD31:2 are driven with the last data value on the AD bus.

• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are

driven with the value of A3:2 from the last data cycle.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ALE

ADS

A3:2

O

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a T cycle and deasserted before the beginning of the T state. It is

R(0)

H(Z)

P(0)

a

d

active HIGH and floats to a high impedance state during a hold cycle (T ).

h

O

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the

inverted version of ALE. This signal gives the 80960JD a high degree of compatibility

with existing 80960Kx systems.

R(1)

H(Z)

P(1)

O

ADDRESS STROBE indicates a valid address and the start of a new bus access.

R(1)

H(Z)

P(1)

The processor asserts ADS for the entire T cycle. External bus control logic typically

a

samples ADS at the end of the cycle.

O

ADDRESS3:2 comprise a partial demultiplexed address bus.

R(X)

H(Z)

P(Q)

32-bit memory accesses: the processor asserts address bits A3:2 during T . The

partial word address increments with each assertion of RDYRCV during a burst.

a

16-bit memory accesses: the processor asserts address bits A3:1 during T_awith A1

driven on the BE1 pin. The partial short word address increments with each assertion

of RDYRCV during a burst.

8-bit memory accesses: the processor asserts address bits A3:0 during T , with A1:0

a

driven on BE1:0. The partial byte address increments with each assertion of

RDYRCV during a burst.

PRELIMINARY

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80960JD

Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)

NAME

TYPE

DESCRIPTION

BE3:0

O

BYTE ENABLES select which of up to four data bytes on the bus participate in the

current bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

R(1)

H(Z)

P(1)

32-bit bus:

BE3 enables data on AD31:24

BE2 enables data on AD23:16

BE1 enables data on AD15:8

BE0 enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enable (enables data on AD15:8)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3 is not used (state is high)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during T .

a

Since unaligned bus requests are split into separate bus transactions, these signals

do not toggle during a burst. They remain active through the last T_dcycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in

conjunction with A3:2 described above.

WIDTH/

O

WIDTH/HALTED signals denote the physical memory attributes for a bus trans-

HLTD1:0

R(0)

H(Z)

P(1)

action:

WIDTH/HLTD1

WIDTH/HLTD0

0

1

0

1

0

1

8 Bits Wide

16 Bits Wide

32 Bits Wide

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in

response to a HOLD request, regardless of prior operating state.

D/C

O

DATA/CODE indicates that a bus access is a data access (1) or an instruction

R(X)

H(Z)

P(Q)

access (0). D/C has the same timing as W/R.

0 = instruction access

1 = data access

W/R

O

WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or

a

R(0)

H(Z)

P(Q)

read (0). It is latched on-chip and remains valid during T cycles.

d

0 = read

1 = write

8

PRELIMINARY

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Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)

NAME

DT/R

TYPE

DESCRIPTION

O

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

R(0)

H(Z)

P(Q)

address/data bus. It is low during T_aand T /T cycles for a read; it is high during T

a

w

d

and T_w/T cycles for a write. DT/R never changes state when DEN is asserted.

d

0 = receive

1 = transmit

DEN

O

DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted

at the start of the first data cycle in a bus access and deasserted at the end of the last

data cycle. DEN is used with DT/R to provide control for data transceivers connected

to the data bus.

R(1)

H(Z)

P(1)

0 = data cycle

1 = not data cycle

BLAST

RDYRCV

O

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the

last data transfer of burst and non-burst accesses. BLAST remains active as long as

wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final

data transfer in a bus cycle.

R(1)

H(Z)

P(1)

0 = last data transfer

1 = not last data transfer

I

READY/RECOVER indicates that data on AD lines can be sampled or removed. If

S(L)

RDYRCV is not asserted during a T cycle, the T_dcycle is extended to the next cycle

by inserting a wait state (T ).

w

d

0 = sample data

1 = don’t sample data

The RDYRCV pin has another function during the recovery (T_r) state. The processor

continues to insert additional recovery states until it samples the pin HIGH. This

function gives slow external devices more time to float their buffers before the

processor begins to drive address again.

0 = insert wait states

1 = recovery complete

LOCK/

ONCE

I/O

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The

LOCK output is asserted in the first clock of an atomic operation and deasserted in

the last data transfer of the sequence. The processor does not grant HOLDA while it

is asserting LOCK. This prevents external agents from accessing memory involved in

semaphore operations.

S(L)

R(H)

H(Z)

P(1)

0 = Atomic read-modify-write in progress

1 = Atomic read-modify-write not in progress

ONCE MODE: The processor samples the ONCE input during reset. If it is asserted

LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the

processor stops all clocks and floats all output pins. The pin has a weak internal

pullup which is active during reset to ensure normal operation when the pin is left

unconnected.

0 = ONCE mode enabled

1 = ONCE mode not enabled

PRELIMINARY

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80960JD

Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)

NAME

TYPE

DESCRIPTION

HOLD

I

HOLD: A request from an external bus master to acquire the bus. When the

S(L)

processor receives HOLD and grants bus control to another master, it asserts

HOLDA, floats the address/data and control lines and enters the T state. When

h

HOLD is deasserted, the processor deasserts HOLDA and enters either the T or T

i

state, resuming control of the address/data and control lines.

a

0 = no hold request

1 = hold request

HOLDA

BSTAT

O

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has

relinquished control of the bus. The processor can grant HOLD requests and enter

the T_hstate during reset and while halted as well as during regular operation.

R(Q)

H(1)

P(Q)

0 = hold not acknowledged

1 = hold acknowledged

O

BUS STATUS indicates that the processor may soon stall unless it has sufficient

access to the bus; see i960^®Jx Microprocessor User’s Guide (272483). Arbitration

logic can examine this signal to determine when an external bus master should

acquire/relinquish the bus.

R(0)

H(Q)

P(0)

0 = no potential stall

1 = potential stall

Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)

NAME

CLKIN

TYPE

I

DESCRIPTION

CLOCK INPUT provides the processor’s fundamental time base; the processor core

operates at twice the CLKIN rate while the external bus operates at the CLKIN rate.

All input and output timings are specified relative to a rising CLKIN edge.

RESET

I

RESET initializes the processor and clears its internal logic. During reset, the

processor places the address/data bus and control output pins in their idle (inactive)

states.

A(L)

During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST

and HOLD.

The RESET pin has an internal synchronizer. To ensure predictable processor initial-

ization during power up, RESET must be asserted a minimum of 10,000 CLKIN

cycles with V_CCand CLKIN stable. On a warm reset, RESET should be asserted for

a minimum of 15 cycles.

STEST

I

SELF TEST enables or disables the processor’s internal self-test feature at initial-

ization. STEST is examined at the end of reset. When STEST is asserted, the

processor performs its internal self-test and the external bus confidence test. When

STEST is deasserted, the processor performs only the external bus confidence test.

S(L)

0 = self test disabled

1 = self test enabled

10

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Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)

NAME

FAIL

TYPE

DESCRIPTION

O

FAIL indicates a failure of the processor’s built-in self-test performed during initial-

ization. FAIL is asserted immediately upon reset and toggles during self-test to

indicate the status of individual tests:

R(0)

H(Q)

P(1)

• When self-test passes, the processor deasserts FAIL and begins operation from

user code.

• When self-test fails, the processor asserts FAIL and then stops executing.

0 = self test failed

1 = self test passed

TCK

I

TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1

Boundary Scan Testing (JTAG). State information and data are clocked into the

processor on the rising edge; data is clocked out of the processor on the falling edge.

TDI

I

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising

S(L)

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

TDO

O

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling

edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At

other times, TDO floats. TDO does not float during ONCE mode.

R(Q)

HQ)

P(Q)

TRST

I

TEST RESET asynchronously resets the Test Access Port (TAP) controller function

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan

feature, connect a pulldown resistor between this pin and V_SS. If TAP is not used,

this pin must be connected to V_SS; however, no resistor is required. See Section 4.3,

Connection Recommendations (pg. 24).

A(L)

TMS

I

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation

S(L)

of the test logic for IEEE 1149.1 Boundary Scan testing.

V_CC

–

POWER pins intended for external connection to a V_CCboard plane.

V_CCPLL

PLL POWER is a separate V_CCsupply pin for the phase lock loop clock generator. It

is intended for external connection to the V_CCboard plane. In noisy environments,

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects

on timing relationships.

V_SS

NC

–

GROUND pins intended for external connection to a V_SSboard plane.

NO CONNECT pins. Do not make any system connections to these pins.

PRELIMINARY

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80960JD

Table 5. Pin Description — Interrupt Unit Signals

NAME

TYPE

DESCRIPTION

XINT7:0

I

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0

A(E/L)

pins can be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs

can be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins

are level sensitive in this mode.

Mixed Mode:

The XINT7:5 pins act as dedicated sources and the XINT4:0 pins

act as the five most significant bits of a vectored source. The

least significant bits of the vectored source are set to 010₂

internally.

Unused external interrupt pins should be connected to V_CC

.

NMI

I

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

A(E)

NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is

unused, it should be connected to V_CC

.

12

PRELIMINARY

80960JD

3.1.2 80960Jx 132-Lead PGA Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

14

P

AD22 AD19 AD18 V_CC

V_CC

V_CCAD13

AD11 AD6

AD25

N

AD27 AD26 AD24 AD20 V_SS

V_SS

V_SSAD10 AD7

AD3

M

AD23 AD21

AD12

AD9

AD17

AD16 AD15 AD14

AD8 AD4

AD5 AD1

AD0

V_CC

AD30 AD29 NC

L

K

J

L

K

J

BE2

V_CC

BE3

V_SS

AD28

AD31

V_SS

V_CC

AD2

NC

V_SS

V_CC

V_SS

BE1

BE0

H

G

F

H

G

F

V_CCPLLV_SSCLKIN

V_CC

V_SS

V_CC

V_SSALE

NC

V_SS

V_CC

BSTAT

DEN

V_CC

V_SS

RDYRCV V_SS

RESET V_SS

V_CC

E

D

E

D

V_CC

V_SS

V_CC

V_SSDT/R

V_SS

TDI

C

B

A

C

B

A

LOCK/

ONCE

HOLDA BLAST A3

A2

FAIL

V_SS

V_CC

NC

V_SS

V_CC

HOLD XINT1 XINT0 TRST STEST NC

NC

XINT4 TCK

XINT3

NC

W/R

D/C WIDTH/ TDO NC

HLTD0

V_SS

V_SSXINT6

ALE

NC

ADS WIDTH/

HLTD1

V_CCV_CC

NMI XINT7 XINT5 XINT2 TMS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up

PRELIMINARY

13

80960JD

A

B

C

D

E

F

G

H

J

K

L

M

N

P

14

TMS

NC

V_CC

V_SS

TDI

V_CC

V_CCCLKIN V_CC

V_CC

V_SS

AD2

V_CC

AD1

AD5

AD0

AD4

AD3

AD7

AD6

13

12

13

12

XINT2 TCK STEST

V_SS

NC

AD11

XINT5 XINT3 TRST

XINT7 XINT4 XINT0

RESET RDYRCV NC

AD8

AD9

AD10 AD13

V_CCPLL

11

10

9

11

10

9

V_SS

V_CC

AD12

V_SS

V_CC

NMI

V_CC

XINT6 XINT1

HOLD

NC

V_SS

AD14

AD15

V_SS

V_CC

A80960JD

8

V_CC

7

M

AD16

NC

V_CC

i

6

5

6

5

FAIL

A2

V_CC

NC

V_SS

NC

AD17 V_SS

XXXXXXXX A2

V_CC

AD21

V_SS

V_CC

4

A3

NC

TDO

AD23 AD20 AD18

3

2

1

3

2

1

BSTAT ALE

BE0

V_SS

V_CC

BE1

V_SS

V_CC

AD31 AD28

AD19

AD22

AD24

AD26

WIDTH/

HLTD0

NC

BLAST

ALE

DT/R

DEN

WIDTH/

HLTD1

HOLDA V_SS

D/C

V_SS

BE3

BE2

AD29

ADS

V_CC

AD30 AD27 AD25

W/R LOCK/

ONCE

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down

14

PRELIMINARY

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Table 6. 132-Lead PGA Pinout — In Signal Order

Signal

A2

C5

Signal

AD31

ADS

K3

Signal

TDI

D12

B4

Signal

V_SS

B9

A3

C4

A1

TDO

TMS

TRST

V_CC

V_CCPLL

V_SS

D2

AD0

M14

L13

K12

N14

M13

L12

P14

N13

M12

M11

N12

P13

M10

P12

M9

ALE

G3

A3

A14

C12

A6

V_SS

D13

E2

AD1

ALE

V_SS

AD2

BE0

H3

V_SS

E13

F2

AD3

BE1

J3

A7

V_SS

AD4

BE2

L1

A8

V_SS

F13

G2

AD5

BE3

L2

A9

V_SS

AD6

BLAST

BSTAT

CLKIN

D/C

C3

D1

V_SS

G13

H2

AD7

F3

D14

E1

V_SS

AD8

H14

B2

V_SS

H13

J2

AD9

E14

F1

V_SS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

DEN

DT/R

FAIL

E3

V_SS

J13

K2

D3

F14

G1

G14

H1

V_SS

C6

V_SS

K13

N5

HOLD

HOLDA

LOCK/ONCE

NC

C9

V_SS

C2

V_SS

N6

M8

C1

J1

V_SS

N7

M7

A4

J14

K1

V_SS

N8

M6

NC

A5

V_SS

N9

P4

NC

B5

K14

L14

P5

V_SS

N10

N11

B1

P3

NC

B14

C7

V_SS

N4

NC

W/R

M5

NC

C8

P6

WIDTH/HLTD0

WIDTH/HLTD1

XINT0

XINT1

XINT2

XINT3

XINT4

XINT5

XINT6

XINT7

B3

P2

NC

C14

G12

J12

M3

A10

F12

E12

C13

B13

P7

A2

M4

NC

P8

C11

C10

A13

B12

B11

A12

B10

A11

N3

NC

P9

P1

NC

P10

P11

H12

B6

N2

NMI

N1

RDYRCV

RESET

STEST

TCK

L3

M2

V_SS

B7

M1

V_SS

B8

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRELIMINARY

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80960JD

Table 7. 132-Lead PGA Pinout — In Pin Order

A1

Signal

ADS

C6

Signal

FAIL

NC

H1

Signal

V_CC

M10

M11

M12

M13

M14

N1

Signal

AD12

AD9

AD8

AD4

AD0

AD27

AD26

AD24

AD20

V_SS

A2

WIDTH/HLTD1

ALE

C7

H2

V_SS

A3

C8

NC

H3

BE0

A4

NC

C9

HOLD

XINT1

XINT0

TRST

STEST

NC

H12

H13

H14

J1

V_CCPLL

V_SS

A5

NC

C10

C11

C12

C13

C14

D1

A6

V_CC

CLKIN

V_CC

A7

V_CC

N2

A8

V_CC

J2

V_SS

N3

A9

V_CC

J3

BE1

N4

A10

A11

A12

A13

A14

B1

NMI

V_CC

J12

J13

J14

K1

NC

N5

XINT7

XINT5

XINT2

TMS

D2

V_SS

N6

V_SS

D3

DT/R

TDI

V_CC

N7

V_SS

D12

D13

D14

E1

V_CC

N8

V_SS

K2

V_SS

N9

V_SS

W/R

V_CC

K3

AD31

AD2

N10

N11

N12

N13

N14

P1

V_SS

B2

D/C

V_CC

K12

K13

K14

L1

V_SS

B3

WIDTH/HLTD0

TDO

E2

V_SS

AD10

AD7

AD3

AD25

AD22

AD19

AD18

V_CC

B4

E3

DEN

RESET

V_SS

V_CC

B5

NC

E12

E13

E14

F1

BE2

B6

V_SS

L2

BE3

B7

V_SS

V_CC

L3

AD28

AD5

P2

B8

V_SS

V_CC

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

M8

M9

P3

B9

V_SS

F2

V_SS

AD1

P4

B10

B11

B12

B13

B14

C1

XINT6

XINT4

XINT3

TCK

F3

BSTAT

RDYRCV

V_SS

V_CC

P5

F12

F13

F14

G1

AD30

AD29

NC

P6

V_CC

P7

V_CC

P8

V_CC

NC

V_CC

AD23

AD21

AD17

AD16

AD15

AD14

P9

V_CC

LOCK/ONCE

HOLDA

BLAST

A3

G2

V_SS

P10

P11

P12

P13

P14

V_CC

C2

G3

ALE

V_CC

C3

G12

G13

G14

NC

AD13

AD11

AD6

C4

V_SS

C5

A2

V_CC

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

16

PRELIMINARY

80960JD

3.1.3 80960Jx PQFP Pinout

AD9

V_CC(I/O)

_SS(I/O)

AD10

AD11

TRST

TCK

TMS

HOLD

XINT0

XINT1

XINT2

1

99

98

2

3

4

5

6

7

V

97

96

95

94

93

V

_CC(I/O)

_SS(I/O)

_CC(Core)

XINT3

V_CC(I/O)

_SS(I/O)

XINT4

XINT5

XINT6

92

91

90

8

9

10

V_SS(Core)

AD12

V

89

88

87

86

85

84

83

82

81

80

79

78

11

12

13

14

15

16

17

18

19

20

21

22

AD13

AD14

AD15

V

_CC(I/O)

XINT7

NMI

V_SS(I/O)

AD16

V_CC(Core)

_SS(Core)

V

®

AD17

AD18

AD19

NC

i960

V_CC(I/O)

NC

FAIL

ALE

TDO

V_SS(I/O)

AD20

AD21

AD22

NG80960JX

77

76

75

74

73

72

71

23

24

25

26

27

28

29

XXXXXXXX A2

AD23

V_CC(Core)

V_SS(Core)

V

_CC(I/O)

_SS(I/O)

WIDTH/HLTD1

_CC(Core)

_SS(Core)

M

i

V

_CC(I/O)

_SS(I/O)

V

AD24

70

69

68

67

30

31

32

33

V

WIDTH/HLTD0

A2

AD25

AD26

NC

A3

Figure 5. 132-Lead PQFP - Top View

PRELIMINARY

17

80960JD

Table 8. 132-Lead PQFP Pinout — In Signal Order

Signal

60

Signal

ALE

24

36

33

32

55

54

53

52

28

31

35

37

42

43

34

132

50

4

Signal

47

Signal

V_SS(I/O)

NC

10

27

40

48

56

64

71

79

85

93

97

106

112

131

18

19

20

21

22

67

121

122

126

127

14

13

12

11

8

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

V_CC(Core)

61

ADS

59

62

A3

V

_CC(Core)

74

63

A2

V

92

66

BE3

V_CC(Core)

V_CC(I/O)

113

115

123

9

68

BE2

69

BE1

70

BE0

75

WIDTH/HLTD1

WIDTH/HLTD0

D/C

V

_CC(I/O)

26

76

V

41

77

V_CC(I/O)

49

78

W/R

57

81

DT/R

65

82

DEN

72

83

BLAST

RDYRCV

LOCK/ONCE

HOLD

HOLDA

BSTAT

CLKIN

RESET

STEST

FAIL

80

84

86

NC

87

94

NC

88

V_CC(I/O)

98

NC

89

44

51

117

125

128

23

2

105

111

129

119

118

17

NC

90

NC

95

NC

96

V_CCPLL

NC

99

V

_SS(CLK)

NC

AD8

100

101

102

103

104

107

108

109

110

45

V_SS(Core)

NC

AD7

TCK

V

_SS(Core)

30

XINT7

XINT6

XINT5

XINT4

XINT3

XINT2

XINT1

XINT0

NMI

AD6

TDI

130

25

1

38

AD5

TDO

46

AD4

TRST

TMS

V_SS(Core)

_SS(Core)

58

AD3

3

V

73

AD2

V

_CC(CLK)

120

16

29

39

V_SS(Core)

91

7

AD1

V

_CC(Core)

114

116

124

6

AD0

5

ALE

15

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

18

PRELIMINARY

80960JD

Table 9. 132-Lead PQFP Pinout — In Pin Order

1

Signal

TRST

TCK

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

Signal

BLAST

D/C

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

Signal

NC

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

Signal

AD8

AD7

2

AD26

3

TMS

ADS

AD25

AD6

4

HOLD

XINT0

XINT1

XINT2

XINT3

W/R

AD24

AD5

5

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

DT/R

V_SS(I/O)

V_CC(I/O)

V_SS(Core)

V_CC(Core)

AD23

AD4

6

V_CC(I/O)

V_SS(I/O)

AD3

7

8

9

V_CC(I/O)

AD2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

V

_SS(I/O)

XINT4

XINT5

XINT6

XINT7

NMI

DEN

AD22

AD1

HOLDA

ALE

AD21

AD0

AD20

V_CC(I/O)

V_SS(I/O)

V_CC(Core)

V_SS(Core)

V_CC(Core)

V_SS(Core)

CLKIN

V_SS(CLK)

V_CCPLL

V_{CC (CLK)}

NC

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

LOCK/ONCE

BSTAT

BE0

V_SS(I/O)

V_CC(I/O)

AD19

V

_CC(Core)

_SS(Core)

NC

AD18

V

AD17

AD16

NC

V_SS(I/O)

V_CC(I/O)

AD15

NC

BE1

NC

BE2

NC

BE3

AD14

FAIL

V_SS(I/O)

V_CC(I/O)

AD13

NC

ALE

AD12

V_CC(Core)

V_SS(Core)

RESET

NC

TDO

V

_SS(Core)

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

V_CC(Core)

AD31

V_SS(I/O)

WIDTH/HLTD1

AD30

V_CC(I/O)

NC

V

_CC(Core)

_SS(Core)

AD29

AD11

STEST

V_CC(I/O)

TDI

V

AD28

AD10

WIDTH/HLTD0

V_SS(I/O)

V_CC(I/O)

AD9

A2

A3

V_CC(I/O)

V_SS(I/O)

RDYRCV

AD27

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRELIMINARY

19

80960JD

T_J= T_C+ P (θ_JC

)

3.2 Package Thermal Specifications

Similarly, if T_Ais known, the corresponding case

temperature (T_C) can be calculated as follows:

The 80960JD is specified for operation when T_C

(case temperature) is within the range of 0°C to 85°C

for the (PGA) 80960JD-50, or 0°C to 100°C for the

(PQFP and PGA) 80960JD-40 and 80960JD-33.

Case temperature may be measured in any

environment to determine whether the 80960JD is

within specified operating range. The case temper-

ature should be measured at the center of the top

surface, opposite the pins.

T

_C= T_A+ P (θ_CA

Compute P by multiplying I_CCfrom Table 13 and

_CC. Values for θ_JCand θ_CAare given in Table 10

)

V

for the PGA package and Table 11 for the PQFP

package. For high speed operation, the processor’s

θ_JAmay be significantly reduced by adding

a

heatsink and/or by increasing airflow.

θ_CAis the thermal resistance from case to ambient.

Use the following equation to calculate T_A, the

maximum ambient temperature to conform to a

particular case temperature:

Figure 6 shows the maximum ambient temperature

(T_A) permitted without exceeding T_Cfor the

80960JD-50 in a PGA package. Figure 7 illustrates

this for the 80960JD-40 in PGA and PQFP

packages. The curves are based on minimum I_CC

(hot) and maximum V_CCof +5.25 V, with a T_CASEof

+85°C for the 80960JD-50, or a T_CASEof +100°C for

the 80960JD-40.

T

_A= T_C- P (θ_CA)

Junction temperature (T_J) is commonly used in

reliability calculations. T_Jcan be calculated from θ_JC

(thermal resistance from junction to case) using the

following equation:

Table 10. 132-Lead PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

200 400 600 800

(1.01) (2.03) (3.04) (4.06) (5.08)

Parameter

0

1000

(0)

θ_JC(Junction-to-Case)

3

12

9

3

11

8

3

11

8

3

11

8

θ_CA(Case-to-Ambient) (No Heatsink)

18

15

14

15

12

11

θ_CA(Case-to-Ambient) (Omnidirectional Heatsink)

θ_CA(Case-to-Ambient) (Unidirectional Heatsink)

8

7

θ_JA

θ_CA

θ_JC

θ_J-PIN

θ_J-CAP

NOTES:

1. This table applies to a PGA device plugged into a socket or soldered directly into a board.

2.

3.

4.

5.

θ

= θ + θ

JC

JA

CA

= 4°C/W (approx.)

J-CAP

J-PIN

= 4°C/W (inner pins) (approx.)

= 8°C/W (outer pins) (approx.)

20

PRELIMINARY

80960JD

Table 11. 132-Lead PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

0

50

100

200

400

600

800

(0)

(0.25)

(0.50)

(1.01)

(2.03)

(3.04)

(4.06)

θ_JC(Junction-to-Case)

6

7

9

7

8

θ_CA(Case-to-Ambient -No Heatsink)

23

20

18

14

10

θ_CA

θ_JC

θ_JA

θ_JB

θ_JL

NOTES:

1. This table applies to a PQFP device soldered directly into board.

2.

3.

4.

θ

= θ

+ θ

JA

JL

JB

JC CA

= 18°C/W (approx.)

65

60

55

50

45

40

35

30

0

100

200

300

400

500

600

700

800

AIRFLOW (ft/min)

PGA with unidirectional heatsink

PGA with no heatsink

PGA with omnidirectional heatsink

Figure 6. 50 MHz Maximum Allowable Ambient Temperature

PRELIMINARY

21

80960JD

85

80

75

70

65

60

55

50

45

40

0

50

100

200

300

400

500

600

PGA with unidirectional heatsink

700

800

AIRFLOW (ft/min)

PQFP

PGA with no heatsink

PGA with omnidirectional heatsink

Figure 7. 40 MHz Maximum Allowable Ambient Temperature

2. Wakefield Engineering

3.3 Thermal Management

Accessories

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

The following is a list of suggested sources for

80960JD thermal solutions. This is neither an

endorsement or a warranty of the performance of

any of the listed products and/or companies.

3. Aavid Thermal Technologies, Inc.

One Kool Path

Laconia, NH 03247-0400

(603) 528-3400

Heatsinks

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(214) 243-4321 FAX: (214) 241-4656

22

PRELIMINARY

80960JD

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

NOTICE: This data sheet contains preliminary information

on new products in production. The specifications are

subject to change without notice.

Parameter

Maximum Rating

Storage Temperature............................. –65° C to +150° C

WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause perma-

nent damage. These are stress ratings only. Opera-

tion beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

Case Temperature Under Bias .............. –65° C to +110° C

Supply Voltage wrt. V ..............................–0.5V to + 4.6V

SS

Voltage on Other Pins wrt. V ........... –0.5V to V

+ 0.5V

CC

SS

4.2 Operating Conditions

Table 12. 80960JD Operating Conditions

Symbol

Parameter

Supply Voltage

Min

Max

Units

Notes

V

CC

80960JD-50

80960JD-40

80960JD-33

4.75

5.25

V

f

Input Clock Frequency

CLKIN

80960JD-50

80960JD-40

80960JD-33

8

25

20

16.67

MHz

T_C

Operating Case Temperature

A80960JD-50 (132 PGA)

A80960JD-40 (132 PGA)

A80960JD-33 (132 PGA)

0

85

100

°C

NG80960JD-40 (132 PQFP)

NG80960JD-33 (132 PQFP)

0

100

PRELIMINARY

23

80960JD

Pay special attention to the Test Reset (TRST) pin. It

is essential that the JTAG Boundary Scan Test

Access Port (TAP) controller initializes to a known

state whether it will be used or not. If the JTAG

Boundary Scan function will be used, connect a

pulldown resistor between the TRST pin and V_SS. If

the JTAG Boundary Scan function will not be used

(even for board-level testing), connect the TRST pin

to V_SS. Also, do not connect the TDI, TDO, and TCK

pins if the TAP Controller will not be used.

4.3 Connection Recommendations

For clean on-chip power distribution, V_CCand V_SS

pins separately feed the device’s functional units.

Power and ground connections must be made to all

80960JD power and ground pins. On the circuit

board, every V_CCpin should connect to a power

plane and every V_SSpin should connect to a ground

plane. Place liberal decoupling capacitance near the

80960JD, since the processor can cause transient

power surges.

Pins identified as NC must not be connected in

the system.

4.4 DC Specifications

Table 13. 80960JD DC Characteristics

Symbol

V_IL

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Min

-0.3

2.0

Typ

Max

0.8

Units

Notes

V

V_IH

V_CC+ 0.3

0.45

V_OL

V_OH

I_OL= 5 mA

I_OH= -1 mA

_OH= -200 µA

2.4

V

_CC- 0.5

I

V_OLP

C_IN

Output Ground Bounce

< 0.8

V

(1,2)

Input Capacitance

PGA

PQFP

f

= f_MIN(2)

CLKIN

12

10

pF

C_OUT

I/O or Output Capacitance

PGA

PQFP

f

CLKIN

12

10

pF

C_CLK

CLKIN Capacitance

PGA

PQFP

12

10

f

= f_MIN(2)

CLKIN

NOTES:

1. Typical is measured with V_CC= 5.0V and temperature = 25 °C.

2. Not tested.

24

PRELIMINARY

80960JD

Table 14. 80960JD I_CCCharacteristics

Symbol

Parameter

Typ

Max

Units

Notes

0 ≤ V_IN≤ V_CC

I_LI1

Input Leakage Current for

each pin except TCK, TDI,

TRST and TMS

± 1

µA

I_LI2

I_LO

Input Leakage Current for

TCK, TDI, TRST and TMS

-140

-250

± 1

µA

V_IN= 0.45V (1)

Output Leakage Current

µA

0.4 ≤ V_OUT≤ V_CC

I_CCActive

(Power Supply)

80960JD-50

80960JD-40

80960JD-33

640

530

450

mA

(2,3)

I_CCActive

(Thermal)

80960JD-50

80960JD-40

80960JD-33

525

430

365

mA

(2,4)

I_CCTest

Reset mode

80960JD-50

80960JD-40

80960JD-33

(Power modes)

510

430

370

(5)

Halt mode

80960JD-50

80960JD-40

80960JD-33

48

41

36

(5)

ONCE mode

10

(5)

NOTES:

1. These pins have internal pullup devices. Typical leakage current is not tested.

2. Measured with device operating and outputs loaded to the test condition in Figure 8, AC Test Load (pg.

33).

3. I_CCActive (Power Supply) value is provided for selecting your system’s power supply. It is measured

using one of the worst case instruction mixes with V

tested.

= 5.25V. This parameter is characterized but not

CC

4.

I

_CCActive (Thermal) value is provided for your system’s thermal management. Typical I_CCis measured

with V_CC= 5.0V and temperature = 25° C. This parameter is characterized but not tested.

5. I_CCTest (Power modes) refers to the I_CCvalues that are tested when the 80960JD is in Reset mode,

Halt mode or ONCE mode with V

= 5.25V.

CC

PRELIMINARY

25

80960JD

4.5 AC Specifications

The 80960JD AC timings are based upon device characterization.

Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Units

Notes

INPUT CLOCK TIMINGS

T_F

CLKIN Frequency

8

25

MHz

ns

T_C

CLKIN Period

40

125

T_CS

T_CH

T_CL

T_CR

T_CF

CLKIN Period Stability

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

± 250

ps

(1, 2)

16

ns

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

ns

25

5

ns

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

T_OV1

Output Valid Delay, Except

ALE/ALE Inactive and DT/R

3.5

17

ns

(3)

(4)

T_OV2

T_OF

Output Valid Delay, DT/R

Output Float Delay

0.5T_C+ 3.5 0.5T_C+ 17

3.5 15

ns

SYNCHRONOUS INPUT TIMINGS

T_IS1

T_IH1

T_IS2

T_IH2

T_IS3

T_IH3

T_IS4

T_IH4

NOTE:

Input Setup to CLKIN —

AD31:0, NMI, XINT7:0

8

ns

(5)

(6)

(7)

(8)

Input Hold from CLKIN —

AD31:0, NMI, XINT7:0

2

9

1

8

2

8

Input Setup to CLKIN —

RDYRCV and HOLD

Input Hold from CLKIN —

RDYRCV and HOLD

Input Setup to CLKIN —

RESET

Input Hold from CLKIN —

RESET

Input Setup to RESET —

ONCE, STEST

Input Hold from RESET —

ONCE, STEST

2

See Table 16 on page 28 for note definitions for this table.

26

PRELIMINARY

80960JD

Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Notes

RELATIVE OUTPUT TIMINGS

T_LXL

T_LXA

ALE/ALE Width

(9)

Address Hold from ALE/ALE

Inactive

Equal Loading (9)

0.5T_C- 7.5

ns

T_DXD

DT/R Valid to DEN Active

Equal Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

T_BSF

TCK Frequency

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

0.5T_F

MHz

ns

T_BSCH

T_BSCL

T_BSCR

T_BSCF

T_BSIS1

T_BSIH1

15

5

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

ns

5

ns

2.0 V to 0.8 V (1)

Input Setup to TCK — TDI, TMS

4

6

ns

Input Hold from TCK — TDI,

TMS

ns

T_BSOV1

T_BSOF1

T_BSOV2

TDO Valid Delay

TDO Float Delay

3

30

ns

(1,10)

All Outputs (Non-Test) Valid

Delay

T_BSOF2

T_BSIS2

T_BSIH2

NOTE:

All Outputs (Non-Test) Float

Delay

3

4

6

30

ns

(1,10)

Input Setup to TCK — All Inputs

(Non-Test)

Input Hold from TCK — All

Inputs (Non-Test)

See Table 16 on page 28 for note definitions for this table.

PRELIMINARY

27

80960JD

NOTES:

Table 16. Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) (pg. 26)

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is

LO

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-

nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 1 of 3)

Symbol

Parameter

Min

Max

Units

Notes

INPUT CLOCK TIMINGS

T_F

CLKIN Frequency

8

20

MHz

ns

T_C

CLKIN Period

50

125

T_CS

T_CH

CLKIN Period Stability

CLKIN High Time

±250

ps

(1, 2)

20

ns

Measured at

1.5 V (1)

T_CL

T_CR

T_CF

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

ns

Measured at

1.5 V (1)

7

0.8 V to 2.0

V (1)

2.0 V to 0.8

V (1)

SYNCHRONOUS OUTPUT TIMINGS

T_OV1

Output Valid Delay, Except ALE/ALE

Inactive and DT/R

3.5

18

ns

(3)

28

PRELIMINARY

80960JD

Notes

Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 2 of 3)

Symbol

T_OV2

Parameter

Output Valid Delay, DT/R

Output Float Delay

Min

0.5T_C+ 3.5

3.5

Max

0.5T_C+ 18

16

Units

ns

T_OF

ns

(4)

SYNCHRONOUS INPUT TIMINGS

T_IS1

T_IH1

T_IS2

T_IH2

Input Setup to CLKIN — AD31:0, NMI,

XINT7:0

8

2

9

1

ns

(5)

(6)

Input Hold from CLKIN — AD31:0, NMI,

XINT7:0

Input Setup to CLKIN — RDYRCV and

HOLD

Input Hold from CLKIN — RDYRCV and

HOLD

T_IS3

T_IH3

T_IS4

T_IH4

Input Setup to CLKIN — RESET

8

2

8

2

ns

(7)

(8 )

(8)

Input Hold from CLKIN — RESET

Input Setup to RESET — ONCE, STEST

Input Hold from RESET — ONCE,

STEST

RELATIVE OUTPUT TIMINGS

T_LXL

T_LXA

ALE/ALE Width

(9)

Address Hold from ALE/ALE Inactive

Equal

Loading (9)

0.5T_C- 7.5

ns

T_DXD

DT/R Valid to DEN Active

Equal

Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

0.5T_F

T_BSF

TCK Frequency

TCK High Time

MHz

ns

T_BSCH

15

Measured at

1.5 V (1)

T_BSCL

T_BSCR

T_BSCF

TCK Low Time

TCK Rise Time

TCK Fall Time

15

ns

Measured at

1.5 V (1)

5

0.8 V to 2.0

V (1)

2.0 V to 0.8

V (1)

T_BSIS1

T_BSIH1

T_BSOV1

T_BSOF1

Input Setup to TCK — TDI, TMS

Input Hold from TCK — TDI, TMS

TDO Valid Delay

4

6

3

ns

30

(1, 10)

TDO Float Delay

PRELIMINARY

29

80960JD

Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 3 of 3)

Symbol

T_BSOV2

T_BSOF2

T_BSIS2

Parameter

Min

3

Max

30

Units

ns

Notes

(1, 10)

All Outputs (Non-Test) Valid Delay

All Outputs (Non-Test) Float Delay

3

30

ns

Input Setup to TCK — All Inputs (Non-

Test)

4

ns

T_BSIH2

Input Hold from TCK — All Inputs (Non-

Test)

6

ns

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is

LO

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-

nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

30

PRELIMINARY

80960JD

Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Units

Notes

INPUT CLOCK TIMINGS

T_F

CLKIN Frequency

8

16.67

MHz

ns

T_C

CLKIN Period

60

125

T_CS

T_CH

T_CL

T_CR

T_CF

CLKIN Period Stability

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

± 250

ps

(1, 2)

24

ns

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

ns

8

ns

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

T_OV1

T_OV2

T_OF

Output Valid Delay, Except

ALE/ALE Inactive and DT/R

3.5

19

0.5T_C+ 19

18

ns

(3)

Output Valid Delay, DT/R

0.5T_C

3.5

+

Output Float Delay

3.5

(4)

SYNCHRONOUS INPUT TIMINGS

T_IS1

T_IH1

T_IS2

T_IH2

Input Setup to CLKIN — AD31:0,

NMI, XINT7:0

8

2

9

1

ns

(5)

(6)

Input Hold from CLKIN — AD31:0,

NMI, XINT7:0

Input Setup to CLKIN — RDYRCV

and HOLD

Input Hold from CLKIN —

RDYRCV and HOLD

T_IS3

T_IH3

T_IS4

Input Setup to CLKIN — RESET

Input Hold from CLKIN — RESET

8

2

8

ns

(7)

(8)

Input Setup to RESET — ONCE,

STEST

T_IH4

Input Hold from RESET — ONCE,

STEST

2

ns

(8)

RELATIVE OUTPUT TIMINGS

T_LXL

T_LXA

ALE/ALE Width

(9)

Address Hold from ALE/ALE Inac-

tive

Equal Loading (9)

0.5T_C- 8

ns

T_DXD

DT/R Valid to DEN Active

Equal Loading (9)

PRELIMINARY

31

80960JD

Symbol

Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 2 of 2)

Parameter Min Max Units

Notes

BOUNDARY SCAN TEST SIGNAL TIMINGS

T_BSF

TCK Frequency

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

0.5T_F

MHz

ns

T_BSCH

T_BSCL

T_BSCR

T_BSCF

T_BSIS1

T_BSIH1

T_BSOV1

T_BSOF1

T_BSOV2

T_BSOF2

T_BSIS2

15

5

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

5

2.0 V to 0.8 V (1)

Input Setup to TCK — TDI, TMS

Input Hold from TCK — TDI, TMS

TDO Valid Delay

4

6

3

4

30

(1, 10)

TDO Float Delay

All Outputs (Non-Test) Valid Delay

All Outputs (Non-Test) Float Delay

Input Setup to TCK — All Inputs

(Non-Test)

T_BSIH2

Input Hold from TCK — All Inputs

(Non-Test)

6

ns

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is

LO

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation.

NMI and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees

recognition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted

for a minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at

a particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

32

PRELIMINARY

80960JD

4.5.1 AC Test Conditions and Derating Curves

The AC Specifications in Section 4.5, AC Specifications are tested with the 50 pF load indicated in Figure 8.

Figure 9 shows how timings vary with load capacitance; Figure 10 shows how output rise and fall times vary

with load capacitance.

Output Pin

C

= 50 pF for all signals

L

C

L

Figure 8. AC Test Load

AC Derating Curves

nom +6

nom +4

nom +2

nom

High-to-Low Transitions

Low-to-High Transitions

nom -2

50

100

150

C

(pF)

L

Figure 9. Output Delay or Hold vs. Load Capacitance

PRELIMINARY

33

80960JD

10

8

2.0V to 0.8V Transitions

0.8V to 2.0V Transitions

6

4

2

50

100

150

C

(pF)

L

Figure 10. Rise and Fall Time Derating

4.5.2 AC Timing Waveforms

T

CR

CF

2.0V

1.5V

0.8V

T

CH

T

CL

T

C

Figure 11. CLKIN Waveform

34

PRELIMINARY

80960JD

1.5V

OV1

1.5V

CLKIN

T

AD31:0,

ALE (active),

1.5V

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DEN,

BLAST, LOCK,

HOLDA, BSTAT, FAIL

Figure 12. Output Delay Waveform for T_OV1

1.5V

CLKIN

T

OF

AD31:0,

ALE, ALE

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DT/R,

DEN, BLAST, LOCK

Figure 13. Output Float Waveform for T_OF

PRELIMINARY

35

80960JD

1.5V

IH1

1.5V

CLKIN

T

IS1

AD31:0

NMI

Valid

1.5V

XINT7:0

Figure 14. Input Setup and Hold Waveform for T

and T

IH1

IS1

1.5V

CLKIN

T

IH2

T

IS2

HOLD,

1.5V

Valid

1.5V

RDYRCV

Figure 15. Input Setup and Hold Waveform for T

and T

IH2

IS2

36

PRELIMINARY

80960JD

1.5V

CLKIN

T

IS3

IH3

RESET

Figure 16. Input Setup and Hold Waveform for T

and T

IH3

IS3

RESET

T

IH4

T

IS4

ONCE,

STEST

Valid

Figure 17. Input Setup and Hold Waveform for T

and T

IH4

IS4

PRELIMINARY

37

80960JD

T

T /T

w

a

d

1.5V

CLKIN

T

LXL

ALE

1.5V

Valid

1.5V

T

LXA

1.5V

AD31:0

Valid

Figure 18. Relative Timings Waveform for T

and T

LXA

LXL

T

T /T

w d

a

CLKIN

1.5V

T

OV2

Valid

DT/R

DEN

T

DXD

T

OV1

Figure 19. DT/R and DEN Timings Waveform

38

PRELIMINARY

80960JD

T

BSCR

BSCF

2.0V

1.5V

0.8V

T

BSCH

T

BSCL

Figure 20. TCK Waveform

1.5V

TCK

T

BSIH1

BSIS1

TMS

TDI

1.5V

Valid

1.5V

Figure 21. Input Setup and Hold Waveforms for T

and T

BSIS1

BSIH1

PRELIMINARY

39

80960JD

TCK

1.5V

T

BSOV1

BSOF1

Valid

1.5V

TDO

Figure 22. Output Delay and Output Float Waveform for T

AND T

BSOF1

BSOV1

TCK

1.5V

T

BSOF2

BSOV2

Non-Test

Outputs

Valid

1.5V

Figure 23. Output Delay and Output Float Waveform for T

and T

BSOF2

BSOV2

40

PRELIMINARY

80960JD

TCK

1.5V

T

BSIH2

BSIS2

Non-Test

Inputs

1.5V

Valid

1.5V

Figure 24. Input Setup and Hold Waveform for T

and T

BSIS2

BSIH2

PRELIMINARY

41

80960JD

5.0 BUS FUNCTIONAL WAVEFORMS

Figures 25 through 30 illustrate typical 80960JD bus transactions. Figure 31 depicts the bus arbitration

sequence. Figure 32 illustrates the processor reset sequence from the time power is applied to the device.

Figure 33 illustrates the processor reset sequence when the processor is in operation. Figure 34 illustrates the

processor ONCE sequence from the time power is applied to the device. Figures 35 and 36 also show

accesses on 32-bit buses. Tables 19 through 22 summarize all possible combinations of bus accesses across

8-, 16-, and 32-bit buses according to data alignment.

T

i

a

d

r

i

a

d

r

i

CLKIN

D

In

ADDR

Invalid

DATA Out

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

10

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF030A

Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus

42

PRELIMINARY

80960JD

T

a

d

r

a

d

r

CLKIN

DATA

Out

D

In

DATA

Out

DATA

Out

D

In

DATA

Out

ADDR

AD31:0

ALE

ADS

00 or 10

01 or 11

00

01

10

11

A3:2

BE3:0

1 0

WIDTH1:0

D/C

1 0

W/R

BLAST

DT/R

DEN

RDYRCV

Figure 26. Burst Read and Write Transactions Without Wait States, 32-Bit Bus

PRELIMINARY

43

80960JD

T

r

a

w

d

w

d

w

d

w

d

CLKIN

AD31:0

ALE

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ADS

A3:2

0 0

0 1

1 0

1 1

BE3:0

WIDTH1:0

D/C

1 0

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF032A

Figure 27. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus

44

PRELIMINARY

80960JD

T

r

a

d

r

a

d

CLKIN

DATA

Out

DATA

Out

D

In

DATA DATA

D

In

ADDR

AD31:0

Out

ALE

ADS

A3:2

00,01,10 or 11

01 or

BE1/A1

BE0/A0

00

01

10

11

00 or 10

11

WIDTH1:0

D/C

00

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF033A

Figure 28. Burst Read and Write Transactions Without Wait States, 8-Bit Bus

PRELIMINARY

45

80960JD

T

r

T

w

d

r

a

w

d

a

CLKIN

AD31:0

ALE

D

In

D

In

DATA

Out

DATA

Out

ADDR

ADS

00,01,10, or 11

A3:2

0

1

BE1/A1

1

BE3/BHE

BE0/BLE

01

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

F_JF034A

RDYRCV

Figure 29. Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus

46

PRELIMINARY

80960JD

T

r

a

d

r

a

d

r

a

d

r

a

d

CLKIN

AD31:0

ALE

D

In

D

In

D

In

D

In

A

ADS

A3:2

00

01

10

BE3:0

WIDTH1:0

D/C

0 0 0 0

1 1 1 0

0 0 1 1

1 1 0 1

1 0

Valid

W/R

BLAST

DT/R

DEN

RDYRCV

Figure 30. Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian

PRELIMINARY

47

80960JD

T or T

T

T or T

i a

i

r

h

CLKIN

Outputs:

AD31:0,

ALE, ALE,

ADS, A3:2,

BE3:0,

Valid

WIDTH/HLTD1:0,

D/C, W/R,

DT/R, DEN,

BLAST, LOCK

HOLD

HOLDA

(Note)

NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the

same edge in which it recognizes HOLD if the last state was T or the last T of a bus transaction. Similarly,

i

r

the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.

Figure 31. HOLD/HOLDA Waveform For Bus Arbitration

48

PRELIMINARY

80960JD

Figure 32. Cold Reset Waveform

PRELIMINARY

49

80960JD

Figure 33. Warm Reset Waveform

50

PRELIMINARY

80960JD

Figure 34. Entering the ONCE State

PRELIMINARY

51

80960JD

Table 19. Natural Boundaries for Load and Store Accesses

Data Width

Byte

Natural Boundary (Bytes)

1

2

Short Word

Word

4

Double Word

Triple Word

Quad Word

8

16

Table 20. Summary of Byte Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus Accesses on 16 Bit Bus Accesses on 32 Bit Bus

(WIDTH1:0=00)

(WIDTH1:0=01)

(WIDTH1:0=10)

+0 (aligned)

• byte access

Table 21. Summary of Short Word Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus Accesses on 16 Bit Bus Accesses on 32 Bit Bus

(WIDTH1:0=00)

(WIDTH1:0=01)

(WIDTH1:0=10)

+0 (aligned)

+1

• burst of 2 bytes

• 2 byte accesses

• short-word access

• 2 byte accesses

• short-word access

• 2 byte accesses

52

PRELIMINARY

80960JD

Table 22. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)

Address Offset

from Natural

Boundary in Bytes

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit Bus

(WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

• n burst(s) of 4 bytes

• case n=1:

• burst of n word(s)

(n =1, 2, 3, 4)

burst of 2 short words

• case n=2:

burst of 4 short words

• case n=3:

burst of 4 short words

burst of 2 short words

• case n=4:

2 bursts of 4 short words

+1 (n =1, 2, 3, 4)

+5 (n = 2, 3, 4)

+9 (n = 3, 4)

• byte access

• short-word access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• byte access

• short-word access

• burst of 2 bytes

• n-1 burst(s) of 4 bytes

• byte access

+13 (n = 3, 4)

• byte access

+2 (n =1, 2, 3, 4)

+6 (n = 2, 3, 4)

+10 (n = 3, 4)

+14 (n = 3, 4)

• burst of 2 bytes

• n-1 burst(s) of 4 bytes

• burst of 2 bytes

• short-word access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• short-word access

+3 (n =1, 2, 3, 4)

+7 (n = 2, 3, 4)

+11 (n = 3, 4)

+15 (n = 3, 4)

• byte access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• short-word access

• byte access

• n-1 burst(s) of 4 bytes

• burst of 2 bytes

• byte access

• short-word access

• byte access

+4 (n = 2, 3, 4)

+8 (n = 3, 4)

• n burst(s) of 4 bytes

• n burst(s) of 2 short words

• n word access(es)

+12 (n = 3, 4)

PRELIMINARY

53

80960JD

0

4

1

8

2

12

3

16

4

20

5

24

6

Byte Offset

Word Offset

Short Access (Aligned)

Byte, Byte Accesses

Short-Word

Load/Store

Short Access (Aligned)

Byte, Byte Accesses

Word Access (Aligned)

Byte, Short, Byte, Accesses

Short, Short Accesses

Word

Load/Store

Byte, Short, Byte Accesses

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Accesses

Short, Word, Short Accesses

Double-Word

Load/Store

Byte, Word, Short, Byte Accesses

Word, Word Accesses

One Double-Word

Burst (Aligned)

Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus)

54

PRELIMINARY

80960JD

0

4

1

8

2

12

3

16

4

20

5

24

6

Byte Offset

Word Offset

0

One Three-Word

Burst (Aligned)

Byte, Short, Word,

Word, Byte Accesses

Short, Word, Word,

Short Accesses

Triple-Word

Load/Store

Byte, Word, Word,

Short, Byte Accesses

Word, Word,

Word Accesses

Word, Word,

Word Accesses

Word,

Word

Accesses

One Four-Word

Burst (Aligned)

Byte, Short, Word, Word,

Word, Byte Accesses

Short, Word, Word, Word,

Short Accesses

Quad-Word

Load/Store

Byte, Word, Word, Word,

Short, Byte Accesses

Word, Word, Word,

Word Accesses

Word,

Accesses

Figure 36. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)

PRELIMINARY

55

80960JD

6.0 DEVICE IDENTIFICATION

80960JD processors may be identified electrically according to device type and stepping (see Table 23). The

32-bit identifier is accessible in three ways:

• Upon reset, the identifier is placed into the g0 register.

• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID register at

address FF008710H.

• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the IDCODE

instruction.

The device and stepping letter is also printed on the top side of the product package.

Table 23. 80960JD Die and Stepping Reference

Device and

Stepping

Version

Number

Complete ID

(Hex)

Part Number

Manufacturer

X

80960JD A, A2

0000

1000 1000 0010 0000

0000 0001 001

1

08820013

NOTE: This data sheet applies to the 80960JD A and 80960JD A2 steppings.

7.0 REVISION HISTORY

This data sheet supersedes revision 272596-001. Table 24 indicates significant changes since the previous

revision.

Table 24. Data Sheet Version -001 to -002 Revision History (Sheet 1 of 2)

Table 13, 80960JD DC Characteristics (pg.

24)

Removed Icc characteristics. Added V_OLP(output

ground bounce) specification

Table 13, 80960JD DC Characteristics (pg.

24)

New table for comprehensible Icc characteristics.

Added Icc’s for reset mode. Halt Icc for: 80960JD-50

(max) improved from 56 mA to 48 mA, 80960JD-40

(max) improved from 44 mA to 41mA. ONCE Icc

Improved from 30 mA to 10 mA.

Section 4.5, AC Specifications (pg. 26)

Grouped AC Specifications tables by frequency.

Added 40 MHz and 33 MHz AC specifications.

Table 15, 80960JD AC Characteristics (50

MHz) (pg. 26) Section INPUT CLOCK

TIMINGS

T

_CS(max) improved from ±0.1% to ±250 ps

Table 15, 80960JD AC Characteristics (50

MHz) (pg. 26) Section SYNCHRONOUS

OUTPUT TIMINGS

T

_ov1(min) improved from 3.0 ns to 3.5 ns. T_ov2(min)

improved from 0.45T_C+ 3.0 ns to 0.5T_C+ 3.5 ns. T_oF

(min) improved from 3.0 ns to 3.5 ns. T_oF(max)

improved from 17 ns to 15 ns.

56

PRELIMINARY

80960JD

Table 24. Data Sheet Version -001 to -002 Revision History (Sheet 2 of 2)

Table 15, 80960JD AC Characteristics (50

MHz) (pg. 26) Section SYNCHRONOUS

INPUT TIMINGS

T

_IS2(min) improved from 10 ns to 9 ns

Table 15, 80960JD AC Characteristics (50

MHz) (pg. 26) Section RELATIVE OUTPUT

TIMINGS

T

_LXL, T_LXA, and T_DXD(min) improved from .45T_C- 3 ns

to .5T_C- 7.5 ns.

Table 15, 80960JD AC Characteristics (50

MHz) (pg. 26) Section BOUNDARY SCAN

TEST SIGNAL TIMINGS

T_BSF(max) improved from 8 MHz to .5T_F. T_BSIS1(min)

improved from 8 ns to 4 ns. T_BSIH1(min) improved

from 10 ns to 6 ns. T_BSIS2(min) improved from 8 ns to

4 ns. T_BSIH2(min) improved from 10 ns to 6 ns.

PRELIMINARY

57


型号：	GD80960JS-25
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 25MHz, CMOS, PBGA196, PLASTIC, BGA-196 时钟外围集成电路
文件：	总61页 (文件大小：725K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GD80960JS-25 [INTEL]

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