GE28F128W18BE80 [INTEL]
Flash Memory;
| 型号： | GE28F128W18BE80 |
| 厂家： | 
INTEL |
| 描述： | Flash Memory |
| 文件： | 总105页 (文件大小：1195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Wireless Flash Memory
(W18)
128-Mbit W18 Family
Datasheet
Product Features
■ High Performance Read-While-Write/
Erase
■ Architecture
—Multiple 4-Mbit partitions
—Dual Operation: RWW or RWE
—Parameter block size = 4 Kword
—Main block size = 32 Kword
—Top or bottom parameter devices
—16-bit wide data bus
—Burst frequency at 66 MHz
(zero wait states)
—60 ns Initial access read speed
—11 ns Burst mode read speed
—20 ns Page mode read speed
—4-, 8-, 16-, and Continuous-Word Burst
mode reads
—Burst and Page mode reads in all
Blocks, across all partition boundaries
—Burst Suspend feature
■ Software
—5 µs (typ.) Program and Erase Suspend
latency time
—Flash Data Integrator (FDI) and
Common Flash Interface (CFI)
Compatible
—Enhanced Factory Programming at
3.1 µs/word (typ. for 130 nm)
—Programmable WAIT signal polarity
■ Security
■ Packaging and Power
—128-bit OTP Protection Register:
64 unique pre-programmed bits +
64 user-programmable bits
—Absolute Write Protection with VPP at
ground
—Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
Capability
—90 nm: 64 Mb in VF BGA Package
—130 nm: 32 Mb, 64 Mb, and 128 Mb in
VF BGA package; 128 Mb in QUAD+
package
—180 nm: 32 Mb and 128 Mb densities in
VF BGA Package
—56 Active Ball Matrix, 0.75 mm Ball-
Pitch
—VCC = 1.70 V to 1.95 V
—VCCQ = 1.70 V to 2.24 V or 1.35 V to
1.80 V (130 nm and 180 nm)
—Standby current (130 nm): 8 µA (typ.)
—Read current: 8 mA (4-word burst, typ.)
■ Quality and Reliability
—Temperature Range: –40 °C to +85 °C
—100K Erase Cycles per Block
—90 nm ETOX™ IX Process
—130 nm ETOX™ VIII Process
—180 nm ETOX™ VII Process
The Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual-operation
architecture, provides high-performance Asynchronous and Synchronous Burst reads. It is an
ideal memory for low-voltage burst CPUs. Combining high read performance with flash
memory intrinsic non-volatility, the W18 device eliminates the traditional system-performance
paradigm of shadowing redundant code memory from slow nonvolatile storage to faster
execution memory. It reduces total memory requirement that increases reliability and reduces
overall system power consumption and cost. The W18 device’s flexible multi-partition
architecture allows program or erase to occur in one partition while reading from another
partition. This allows for higher data write throughput compared to single-partition architectures
and designers can choose code and data partition sizes. The dual-operation architecture allows
two processors to interleave code operations while program and erase operations take place in
the background.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
290701-012
June 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® WirelessFlash Memory may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2004, Intel Corporation.
*Other names and brands may be claimed as the property of others.
2
Preliminary Datasheet
Contents
Contents
1.0 Introduction ...............................................................................................................................9
1.1
1.2
Nomenclature .......................................................................................................................9
Conventions..........................................................................................................................9
2.0 Functional Overview ............................................................................................................11
2.1 Memory Map and Partitioning.............................................................................................12
3.0 Package Information............................................................................................................15
3.1
3.2
W18 - 180 nm Lithography .................................................................................................15
W18 - 130 nm Lithography .................................................................................................18
4.0 Ballout and Signal Descriptions......................................................................................21
4.1
4.2
Signal Ballout......................................................................................................................21
Signal Descriptions.............................................................................................................23
5.0 Maximum Ratings and Operating Conditions ...........................................................26
5.1
5.2
Absolute Maximum Ratings................................................................................................26
Operating Conditions..........................................................................................................27
6.0 Electrical Specifications.....................................................................................................28
6.1
6.2
DC Current Characteristics.................................................................................................28
DC Voltage Characteristics.................................................................................................30
7.0 AC Characteristics................................................................................................................31
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Read Operations – 90 nm and 130 nm Lithography...........................................................31
Read Operations – 180 nm Lithography.............................................................................33
AC Write Characteristics.....................................................................................................43
Erase and Program Times..................................................................................................49
Reset Specifications ...........................................................................................................50
AC I/O Test Conditions.......................................................................................................51
Device Capacitance............................................................................................................52
8.0 Power and Reset Specifications .....................................................................................52
8.1
8.2
8.3
8.4
Active Power.......................................................................................................................52
Automatic Power Savings (APS) ........................................................................................52
Standby Power ...................................................................................................................52
Power-Up/Down Characteristics.........................................................................................53
8.4.1 System Reset and RST# .......................................................................................53
8.4.2 VCC, VPP, and RST# Transitions .........................................................................53
Power Supply Decoupling...................................................................................................53
8.5
9.0 Bus Operations Overview..................................................................................................54
9.1
Bus Operations...................................................................................................................54
9.1.1 Reads ....................................................................................................................54
9.1.2 Writes.....................................................................................................................55
9.1.3 Output Disable .......................................................................................................55
9.1.4 Burst Suspend .......................................................................................................55
Preliminary Datasheet
3
Contents
9.1.5 Standby..................................................................................................................56
9.1.6 Reset .....................................................................................................................56
Device Commands .............................................................................................................56
Command Sequencing .......................................................................................................60
9.2
9.3
10.0 Read Operations....................................................................................................................61
10.1 Asynchronous Page Read Mode........................................................................................61
10.2 Synchronous Burst Read Mode..........................................................................................61
10.3 Read Array..........................................................................................................................62
10.4 Read Identifier ....................................................................................................................62
10.5 CFI Query ...........................................................................................................................63
10.6 Read Status Register.......................................................................................................... 63
10.7 Clear Status Register..........................................................................................................65
11.0 Program Operations.............................................................................................................65
11.1 Word Program ....................................................................................................................65
11.2 Factory Programming .........................................................................................................66
11.3 Enhanced Factory Program (EFP) .....................................................................................67
11.3.1 EFP Requirements and Considerations ................................................................67
11.3.2 Setup .....................................................................................................................68
11.3.3 Program.................................................................................................................68
11.3.4 Verify...................................................................................................................... 68
11.3.5 Exit.........................................................................................................................69
12.0 Program and Erase Operations.......................................................................................71
12.1 Program/Erase Suspend and Resume...............................................................................71
12.2 Block Erase.........................................................................................................................73
12.3 Read-While-Write and Read-While-Erase..........................................................................75
13.0 Security Modes.......................................................................................................................76
13.1 Block Lock Operations........................................................................................................76
13.1.1 Lock .......................................................................................................................77
13.1.2 Unlock....................................................................................................................77
13.1.3 Lock-Down.............................................................................................................77
13.1.4 Block Lock Status ..................................................................................................78
13.1.5 Lock During Erase Suspend..................................................................................78
13.1.6 Status Register Error Checking .............................................................................78
13.1.7 WP# Lock-Down Control .......................................................................................79
13.2 Protection Register .............................................................................................................79
13.2.1 Reading the Protection Register............................................................................80
13.2.2 Programing the Protection Register.......................................................................80
13.2.3 Locking the Protection Register.............................................................................81
13.3 VPP Protection ...................................................................................................................82
14.0 Set Read Configuration Register....................................................................................83
14.1 Read Mode (RCR[15])........................................................................................................85
14.2 First Access Latency Count (RCR[13:11])..........................................................................85
14.2.1 Latency Count Settings..........................................................................................86
14.3 WAIT Signal Polarity (RCR[10])..........................................................................................87
14.4 WAIT Signal Function.........................................................................................................87
14.5 Data Hold (RCR[9]).............................................................................................................88
4
PreliminaryDatasheet
Contents
14.6 WAIT Delay (RCR[8]) .........................................................................................................89
14.7 Burst Sequence (RCR[7])...................................................................................................89
14.8 Clock Edge (RCR[6]) ..........................................................................................................90
14.9 Burst Wrap (RCR[3])...........................................................................................................91
14.10 Burst Length (RCR[2:0]) .....................................................................................................91
Appendix A Write State Machine States...............................................................................92
Appendix B Common Flash Interface (CFI).........................................................................95
Appendix C Ordering Information.........................................................................................106
Preliminary Datasheet
5
Contents
Revision History
Date of
Revision
Version
Description
09/13/00
-001
Initial Release
Deleted 16-Mbit density
Revised ADV#, Section 2.2
Revised Protection Registers, Section 4.16
Revised Program Protection Register, Section 4.18
Revised Example in First Access Latency Count, Section 5.0.2
Revised Figure 5, Data Output with LC Setting at Code 3
Added WAIT Signal Function, Section 5.0.3
Revised WAIT Signal Polarity, Section 5.0.4
Revised Data Output Configuration, Section 5.0.5
Added Figure 7, Data Output Configuration with WAIT Signal Delay
Revised WAIT Delay Configuration, Section 5.0.6
Changed V
Extended Temperature Operation
Spec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2,
CCQ
Changed I
Characteristics
Spec from 15 µA to 18 µA in Section 8.4, DC
CCS
01/29/01
-002
Changed I
Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13
CCR
mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in
Section 8.4, DC Characteristics
Changed I
Characteristics
Spec from 15 µA to 18 µA in Section 8.4, DC
Spec from 15 µA to 18 µA in Section 8.4, DC
Spec from 5 ns to 3 ns in Section 8.6, AC Read
CCWS
Changed I
Characteristics
CCES
Changed t
Characteristics
CHQX
Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation
Waveform
Added Figure 26, WAIT Signal in Asynchronous Page Mode Read
Operation Waveform
Added Figure 27, WAIT Signal in Asynchronous Single Word Read
Operation Waveform
Revised Appendix E, Ordering Information
Revised entire Section 4.10, Enhanced Factory Program Command (EFP)
and Figure 6, Enhanced Factory Program Flowchart
Revised Section 4.13, Protection Register
Revised Section 4.15, Program Protection Register
Revised Section 7.3, Capacitance, to include 128-Mbit specs
Revised Section 7.4, DC Characteristics, to include 128-Mbit specs
06/12/01
-003
Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device
specifications
Added t
Spec in Section 7.6, AC Read Characteristics
VHGL
Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device
specifications
Minor text edits
6
PreliminaryDatasheet
Contents
Date of
Revision
Version
Description
New Sections Organization
Added 16-Word Burst Feature
Added Burst Suspend Section
Revised Block Locking State Diagram
Revised Active Power Section
Revised Automatic Power Savings Section
Revised Power-Up/Down Operation Section
Revised Extended Temperature Operation
Added 128 Mb DC Characteristics Table
Added 128 Mb AC Read Characteristics
04/05/02
-004
Revised Table 17. Test Configuration Component Values for Worst Case
Speed Conditions
Added 0.13 µm Product DC and AC Read Characteristics
Revised AC Write Characteristics
Added Read to Write and Write to Read Transition Waveforms
Revised Reset Specifications
Various text edits
Various text edits
Updated Latency Count Section, including adding Latency Count Tables
Added section 8.4 WAIT Function and WAIT Summary Table
Updated Package Drawing and Dimensions
10/10/02
11/12/02
01/14/03
-005
-006
-007
Various text clarifications
Removed Intel Burst Order
Revised Table 22, DC Current Characteristics, I
Revised Table 22, DC Current Characteristics, I
Various text edits
CCS
CCAPS
Revised Table 22, Read Operations, t
APA
03/21/03
-008
Added note to table 15, Configuration Register Descriptions
Added note to section 3.1.1, Read
Updated Block-Lock Operations (Section 7.1 and Figure 11)
Updated Table 21 (128 Mb I
)
CCR
12/17/03
02/12/04
-009
-010
Updated Table 4 (WAIT behavior)
Added QUAD+ ballout, package mechanicals, and order information
Various text edits including latest product-naming convention
Added 90 nm product line. Removed µBGA* package. Added Page- and
Burst-Mode descriptions. Minor text edits
Fixed omitted text for Table 21, note 1 regarding max DC voltage on I/O
pins. Removed Extended I/O Supply Voltage for 90 nm product
05/06/04
06/03/04
-011
-012
Minor text edits
Updated the title and layout of the datasheet.
Preliminary Datasheet
7
Contents
8
PreliminaryDatasheet
Intel® Wireless Flash Memory (W18)
1.0 Introduction
1.0
Introduction
This datasheet contains information about the Intel® Wireless Flash Memory (W18) device family.
This section describes nomenclature used in the datasheet. Section 2.0 provides an overview of the
W18 flash memory device. Section 6.0, Section 7.0, and Section 8.0 describe the electrical
specifications for extended temperature product offerings. Ordering information can be found in
Appendix C.
1.1
Nomenclature
Acronyms that describe product features or usage are defined here:
APS
BBA
CFI
Automatic Power Savings
Block Base Address
Common Flash Interface
Command User Interface
Don’t Use
CUI
DU
EFP
FDI
Enhanced Factory Programming
Flash Data Integrator
No Connect
NC
OTP
PBA
RCR
RWE
RWW
SCSP
SRD
VF BGA
WSM
One-Time Programmable
Partition Base Address
Read Configuration Register
Read-While-Erase
Read-While-Write
Stacked Chip Scale Package
Status Register Data
Very-thi, Fine-pitch, Ball Grid Array
Write State Machine
1.2
Conventions
The following list describes abbreviated terms and phrases used throughout this document:
Refers to the full V voltage range of 1.7 V – 1.95 V (except where noted) and “V = 12 V” refers to 12
CC
PP
“1.8 V”
V
5%.
Set
Refers to registers means the bit is a logical 1 and cleared means the bit is a logical 0.
Often used interchangeably to refer to the external signal connections on the package (ball is the term
used for VF BGA).
Pin and signal
Preliminary Datasheet
9
Intel® Wireless Flash Memory (W18)
1.0 Introduction
Word
2 bytes or 16 bits.
Signal
Voltage
Names are in all CAPS (see Section 4.2, “Signal Descriptions” on page 23.)
Applied to the signal is subscripted for example V
.
PP
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
Block
A group of bits (or words) that erase simultaneously with one block erase instruction.
Main block
Parameter block
Contains 32 Kwords.
Contains 4 Kwords.
Block Base
Address (BBA)
The first address of a block.
Partition
A group of blocks that share erase and program circuitry and a common Status Register.
Partition Base
Address (PBA)
The first address of a partition. For example, on a 32-Mbit top-parameter device partition number 5 has a
PBA of 0x140000.
Located at the highest physical device address. This partition may be a main partition or a parameter
partition.
Top partition
Located at the lowest physical device address. This partition may be a main partition or a parameter
partition.
Bottom partition
Main partition
Contains only main blocks.
Parameter
partition
Contains a mixture of main blocks and parameter blocks.
Top parameter
device (TPD)
Has the parameter partition at the top of the memory map with the parameter blocks at the top of that
partition. This was formerly referred to as a Top-Boot device.
Bottom parameter Has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of
device (BPD) that partition. This was formerly referred to as a Bottom-Boot Block flash device.
10
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
2.0 Functional Overview
2.0
Functional Overview
This section provides an overview of the W18 device features and architecture.
The W18 device provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability
with high-performance synchronous and asynchronous reads on package-compatible densities with
a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or
bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W18 device consists of multiple 4-Mbit partitions, the exact
number depending on device density. By dividing the memory array into partitions, program or
erase operations can take place simultaneously during read operations. Burst reads can traverse
partition boundaries, but user application code is responsible for ensuring that they don’t extend
into a partition that is actively programming or erasing. Although each partition has burst-read,
write, and erase capabilities, simultaneous operation is limited to write or erase in one partition
while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the W18 device defaults to asynchronous page-mode read
configuration. Writing to the device’s Read Configuration Register (RCR) enables synchronous
burst-mode read operation. In synchronous mode, the CLK input increments an internal burst
address generator. CLK also synchronizes the flash memory with the host CPU and outputs data on
every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output
signals to the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the W18 device incorporates Enhanced
Factory Programming (EFP), a feature that enables fast programming and low-power designs. The
EFP feature provides the fastest currently-available program performance, which can increase a
factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
V
PP ≤ VPPLK.
This device (130 nm and 180 nm) allows I/O operation at voltages even lower than the minimum
VCCQ of 1.7 V. This Extended VCCQ range, 1.35 V – 1.8 V, permits even greater system design
flexibility.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
Preliminary Datasheet
11
Intel® Wireless Flash Memory (W18)
2.0 Functional Overview
The Command User Interface (CUI) is the system processor’s link to internal flash memory
operation. A valid command sequence written to the CUI initiates device Write State Machine
(WSM) operation that automatically executes the algorithms, timings, and verifications necessary
to manage flash memory program and erase. An internal Status Register provides ready/busy
indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal Status
Registers, and provides an additional level of flash write protection.
2.1
Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or
RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The
device’s memory array is asymmetrically blocked, which enables system code and data integration
within a single flash device. Each block can be erased independently in block erase mode.
Simultaneous program and erase operations are not allowed; only one partition at a time can be
actively programming or erasing. See Table 1, “Bottom Parameter Memory Map” on page 13 and
Table 2, “Top Parameter Memory Map” on page 14.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
12
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
2.0 Functional Overview
Table 1.
Bottom Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
32
32
32
32
32
32
32
32
32
32
32
262
7F8000-7FFFFF
135
134
71
70
39
38
31
30
23
22
400000-407FFF
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
134
71
70
39
38
31
30
23
22
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
70
39
38
31
30
23
22
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
32
32
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
32
4
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
4
0
000000-000FFF
0
000000-000FFF
0
000000-000FFF
Preliminary Datasheet
13
Intel® Wireless Flash Memory (W18)
2.0 Functional Overview
Table 2.
Top Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
4
70
1FF000-1FFFFF
134
3FF000-3FFFFF
262
7FF000-7FFFFF
4
63
62
1F8000-1F8FFF
1F0000-1F7FFF
127
126
3F8000-3F8FFF
3F0000-3F7FFF
255
254
7F8000-7F8FFF
7F0000-7F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
56
55
48
47
40
39
32
31
0
1C0000-1C7FFF
1B8000-1BFFFF
18000-187FFF
178000-17FFFF
140000-147FFF
138000-13FFFF
100000-107FFF
0F8000-0FFFFF
000000-007FFF
120
119
112
111
104
103
96
3C0000-3C7FFF
3B8000-3BFFFF
380000-387FFF
378000-37FFFF
340000-347FFF
338000-33FFFF
300000-307FFF
2F8000-2FFFFF
200000-207FFF
1F8000-1FFFFF
000000-007FFF
248
247
240
239
232
231
224
223
192
191
128
127
0
7C0000-7C7FFF
7B8000-7BFFFF
780000-787FFF
778000-77FFFF
740000-747FFF
738000-73FFFF
700000-707FFF
6F8000-6FFFFF
600000-607FFF
5F8000-5FFFFF
400000-407FFF
3F8000-3FFFFF
000000-007FFF
95
64
63
0
14
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
3.0 Package Information
3.0
Package Information
This section describes the following package descriptions:
• “W18 - 180 nm Lithography” on page 15
— Figure 1, “32Mb VFBGA Package Drawing“
— Figure 2, “128Mb VFBGA Package Drawing“
• “W18 - 130 nm Lithography” on page 18
• “W18 - 90 nm Lithography” on page 19
3.1
W18 - 180 nm Lithography
Figure 1.
32Mb VFBGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S
1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2 1
S
2
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
G
b
Top View - Bump Side Down
A1
BottomView -Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawingnot to scale
Preliminary Datasheet
15
Intel® Wireless Flash Memory (W18)
3.0 Package Information
Figure 2.
128Mb VFBGA Package Drawing
Ball A1
Corner
Ball A1
Corner
S1
D
S2
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
H
J
G
H
J
b
Top View - Bump Side
Down
Bottom View - Ball Side
Up
A1
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Table 3.
32Mb and 128Mb VF BGA Package Dimensions (Sheet 1 of 2)
Millimeters
Inches
Nom
Dimension
Symbol
Min
Nom
Max
Min
Max
Package Height
Ball Height
A
0.850
0.150
0.615
0.325
7.600
8.900
12.400
11.900
-
-
1.000
-
0.0335
0.0059
0.0242
0.0128
0.2992
0.3503
0.4882
0.4685
-
-
0.0394
-
A
A
-
-
1
2
Package Body Thickness
Ball (Lead) Width
0.665
0.375
7.700
9.000
12.500
12.000
0.750
56
0.715
0.425
7.800
9.100
12.600
12.100
-
0.0262
0.0148
0.3031
0.3543
0.4921
0.4724
0.0295
56
0.0281
0.0167
0.3071
0.3583
0.4961
0.4764
-
b
Package Body Width 32 Mb
Package Body Length 32 Mb
Package Body Width 128 Mb
Package Body Length 128 Mb
Pitch
D
E
D
E
[e]
N
N
Y
Ball (Lead) Count 32 Mb
Ball (Lead) Count 128 Mb
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D 32 Mb
-
-
-
-
-
60
-
-
60
-
-
-
0.100
1.325
-
-
0.0039
0.0522
S
1.125
1.225
0.0443
0.0482
1
16
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
3.0 Package Information
Table 3.
32Mb and 128Mb VF BGA Package Dimensions (Sheet 2 of 2)
Millimeters
Nom
Inches
Nom
Dimension
Symbol
Min
Max
Min
Max
Corner to Ball A1 Distance Along E 32 Mb
Corner to Ball A1 Distance Along D 128 Mb
Corner to Ball A1 Distance Along E 128 Mb
S
S
S
2.150
2.775
2.900
2.250
2.875
3.000
2.350
2.975
0.0846
0.1093
0.1142
0.0886
0.1132
0.1181
0.0925
0.1171
0.1220
2
1
2
3.1000
Preliminary Datasheet
17
Intel® Wireless Flash Memory (W18)
3.0 Package Information
3.2
W18 - 130 nm Lithography
Figure 3.
32Mb, 64Mb, and 128Mb VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
S
2
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
G
b
Top View - Bump Side Down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Table 4.
32Mb, 64Mb, and 128Mb VFBGA Package Dimensions
Millimeters
Inches
Nom
Dimension
Symbol
Min
Nom
Max
Min
Max
Package Height
Ball Height
A
-
0.150
-
-
1.000
-
-
-
0.0394
-
A
A
-
0.0059
-
-
1
2
Package Body Thickness
0.665
0.375
7.700
11.000
9.000
0.750
56
-
0.0262
0.0148
0.3031
0.4331
0.3543
0.0295
56
-
Ball (Lead) Width
b
0.325
7.600
10.900
8.900
-
0.425
7.800
11.100
9.100
-
0.0128
0.2992
0.4291
0.3504
-
0.0167
0.3071
0.4370
0.3583
-
Package Body Width (32 Mb, 64 Mb)
Package Body Width (128 Mb)
Package Body Length (32 Mb, 64 Mb, 128 Mb)
Pitch
D
D
E
[e]
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Y
-
-
0.100
1.325
2.975
-
-
0.0039
0.0522
0.1171
Corner to Ball A1 Distance Along D (32 Mb, 64 Mb)
Corner to Ball A1 Distance Along D (128 Mb)
S
S
1.125
2.775
1.225
2.2875
0.0443
0.1093
0.0482
0.1132
1
1
Corner to Ball A1 Distance Along E (32 Mb, 64
Mb,128 Mb)
S
2.150
2.250
2.350
0.0846
0.0886
0.0925
2
18
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
3.0 Package Information
Figure 4.
128Mb QUAD+ Package Drawing
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
D
e
G
G
H
J
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball Up
A
Top View - Ball Down
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Symbol
A
A1
A2
b
D
E
e
N
Min
Max Notes
1.200
Min
Max
0.0472
0.200
0.0079
0.860
0.375
10.000
8.000
0.800
88
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.325
9.900
7.900
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
Y
S1
S2
0.100
1.300
0.700
0.0039
0.0512
0.0276
1.100
0.500
1.200
0.600
0.0433
0.0197
0.0472
0.0236
W18
-
90 nm Lithography
Preliminary Datasheet
19
Intel® Wireless Flash Memory (W18)
3.0 Package Information
Figure 5.
32Mb and 64Mb VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
S
2
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
G
b
Top View - Bump Side Down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Table 5.
32Mb and 64Mb VF BGA Package Dimensions
Millimeters
Inches
Dimension
Symbol
Min
Nom
Max
Min
Nom
Max
Package Height
Ball Height
A
-
-
1.000
-
-
-
0.0394
-
A
A
0.150
-
-
0.0059
-
1
2
Package Body Thickness
Ball (Lead) Width
0.665
0.375
7.700
9.000
0.750
56
-
-
0.0262
0.0148
0.3031
0.3543
0.0295
56
-
b
0.325
7.600
8.900
-
0.425
7.800
9.100
-
0.0128
0.2992
0.3504
-
0.0167
0.3071
0.3583
-
Package Body Width
Package Body Length
Pitch
D
E
[e]
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Y
-
-
0.100
1.325
2.350
-
-
0.0039
0.0522
0.0925
S
S
1.125
2.150
1.225
2.250
0.0443
0.0846
0.0482
0.0886
1
2
20
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
4.0 Ballout and Signal Descriptions
4.0
Ballout and Signal Descriptions
4.1
Signal Ballout
The W18 device is available in a 56-ball VF BGA and µBGA Chip SCale Package with 0.75 mm
ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. Figure 6 shows the device
ballout for the VF BGA package. Figure 7 shows the device ballout for the QUAD+ package.
Figure 6.
56-Ball VF BGA Ballout
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
A
B
C
D
E
F
VCC
CLK
A18
A17
A19
A6
A5
A7
A6
A5
A7
A18
A17
A19
VCC
CLK
A11
A8
A9
VSS
A20
A21
VPP
A4
A3
A2
A4
VPP
VSS
A20
A21
A8
A9
A11
A12
A13
B
C
D
E
F
A12
A13
A3
A2
RST#
WE#
RST#
WE#
A10
A10
ADV#
ADV#
A15
A14 WAIT
DQ15 DQ6
A16
DQ12
DQ2
WP#
DQ1
A22
CE#
A1
A0
A1
A0
A22
WP#
DQ1
DQ12
DQ2
A16
WAIT A14
DQ6 DQ15
A15
VCCQ
DQ4
CE#
DQ4
VCCQ
VSS
DQ7
DQ14 DQ13
VSSQ DQ5
DQ11 DQ10
DQ9
DQ0
OE#
OE#
DQ0
DQ9
DQ10 DQ11
DQ13 DQ14
DQ5 VSSQ
VSS
DQ7
G
G
VCC
DQ3
VCCQ DQ8
VSSQ
VSSQ
DQ8 VCCQ
DQ3
VCC
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
Notes:
1.
On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A21 and A22 are
NC).
2.
See Appendix , “W18 - 180 nm Lithography” on page 15 for mechanical specifications for the package.
Preliminary Datasheet
21
Intel® Wireless Flash Memory (W18)
4.0 Ballout and Signal Descriptions
Figure 7.
88-Ball (80 Active Balls) QUAD+ Ballout
1
2
3
4
5
6
7
8
DU
DU
DU
DU
A
B
C
D
E
F
A4
A5
A18
R-LB#
A17
A7
A19
A23
A24
A25
VSS
VSS
F1-VCC F2-VCC
A21
A22
A9
A11
A12
A13
A15
A16
S-CS2
CLK
F-VPP,
F-VPEN
A3
R-WE# P1-CS#
A2
F-WP# ADV#
A20
A8
A10
A14
A1
A6
R-UB# F-RST# F-WE#
G
A0
D8
D2
D10
D5
D13
WAIT F2-CE#
H
J
R-OE#
D0
D1
D9
D3
D12
D4
D14
D6
D7
F2-OE#
VCCQ
S-CS1# F1-OE#
D11
D15
K
L
P-Mode,
P-CRE
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ
VSS
DU
VSS
DU
VCCQ F1-VCC VSS
VSS
VSS
DU
VSS
DU
M
Top View - Ball Side Down
Legend:
SRAM/PSRAM specific
Flash specific
Global
Notes:
1.
2.
Unused upper address balls can be treated as NC (for 128Mb device, A[25:23] are not used).
See “Package Information” on page 15 for the mechanical specifications for the package.
22
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
4.0 Ballout and Signal Descriptions
4.2
Signal Descriptions
Table 6 describes the signals used on the VF BGA package. Table 7 on page 24 describes the
signals used on the QUAD+ package.
Table 6.
Signal Descriptions - VF BGA Package
Symbol
Type
Name and Function
A[22:0]
Input
ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
Input/
Output
D[15:0]
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or the next valid CLK edge with
ADV# low, whichever occurs first.
ADV#
CE#
Input
Input
Input
Input
Input
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z.
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.
CLK
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
OE#
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
RST#
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to
Output be asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-
stated if CE# is deasserted. WAIT is not gated by OE#.
WAIT
WE#
WP#
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
Input
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 76 for details on block locking.
Input
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V ≤ V
voltages should not be attempted.
. Block erase and program at invalid V
PP
PPLK
PP
Set V = V for in-system program and erase operations. To accommodate resistor or diode drops
PP
CC
VPP
VCC
Power
Power
from the system supply, the V level of V can be as low as V
min to perform in-system flash modification. VPP may be 0 V during read operations.
min. V must remain above V
IH
PP
PP1 PP PP1
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
PP2
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at V ≤ V
voltages should not be attempted.
. Device operations at invalid V
CC
CC
LKO
OUTPUT POWER SUPPLY: Enables all outputs to be driven at V
to VCC.
. This input may be tied directly
CCQ
VCCQ
VSS
Power
Power
Power
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
VSSQ
DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
DU
NC
—
—
NO CONNECT: No internal connection; can be driven or floated.
Preliminary Datasheet
23
Intel® Wireless Flash Memory (W18)
4.0 Ballout and Signal Descriptions
Table 7.
Signal Descriptions - QUAD+ Package (Sheet 1 of 3)
Symbol
Type
Description
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 256-Mbit Die : AMAX= A23
• 128-Mbit Die : AMAX = A22
• 64-Mbit Die : AMAX = A21
A[MAX:MIN]
Input
• 32-Mbit Die : AMAX = A20
• 8-Mbit Die : AMAX = A18
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future device densities.
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data are internally latched
during writes on the flash device.
Input/
Output
D[15:0]
FLASH CHIP ENABLE: Low-true input.
F[3:1]-CE# low selects the associated flash memory die. When asserted, flash internal control logic,
input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is
deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state.
F[3:1]-CE#
Input
Input
Input
F1-CE# selects or deselects flash die #1; F2-CE# selects or deselects flash die #2 and is RFU on
combinations with only one flash die. F3-CE# selects or deselects flash die #3 and is RFU on stacked
combinations with only one or two flash dies.
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).
When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When either/both SRAM Chip Select signals are
deasserted, the SRAM is deselected and its power is reduced to standby levels.
S-CS1#
S-CS2
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked
combinations without SRAM die.
PSRAM CHIP SELECT: Low-true input.
When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active.
When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
P[2:1]-CS#
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This
ball is an RFU on stacked combinations without PSRAM. P2-CS# selects PSRAM die #2 and is
available only on stacked combinations with two PSRAM dies. This ball is an RFU on stacked
combinations without PSRAM or with a single PSRAM.
FLASH OUTPUT ENABLE: Low-true input.
Fx-OE# low enables the selected flash’s output buffers. F[2:1]-OE# high disables the selected flash’s
output buffers, placing them in High-Z.
F[2:1]-OE#
R-OE#
Input
Input
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and flash die
#3. F2-OE# is available on stacked combinations with two or three flash die and is RFU on stacked
combinations with only one flash die.
RAM OUTPUT ENABLE: Low-true input.
R-OE# low enables the selected RAM’s output buffers. R-OE# high disables the RAM output buffers,
and places the selected RAM outputs in High-Z.
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
FLASH WRITE ENABLE: Low-true input.
F-WE#
R-WE#
Input
Input
F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of F-
WE#.
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SRAM die and is an RFU on flash-only
stacked combinations.
24
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
4.0 Ballout and Signal Descriptions
Table 7.
Signal Descriptions - QUAD+ Package (Sheet 2 of 3)
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and
increments the internal address generator.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next
valid CLK edge with ADV# low, whichever occurs first.
CLK
Input
In asynchronous mode, addresses are latched on the rising edge ADV#, or are continuously flow-
through when ADV# is kept asserted.
WAIT: Output signal.
Indicates invalid data during synchronous array or non-array flash reads. Read Configuration Register
bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
WAIT
Output
•
In synchronous array or non-array flash read modes, WAIT indicates invalid data when asserted
and valid data when deasserted.
•
In asynchronous flash page read, and all flash write modes, WAIT is asserted.
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash die.
•
F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked with
software commands.
F-WP#
ADV#
Input
Input
•
F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with
software commands.
ADDRESS VALID: Low-true input.
During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on
the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are
continuously flow-through when ADV# is kept asserted.
RAM UPPER / LOWER BYTE ENABLES: Low-true input.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and R-
LB# low enables the RAM low-order bytes on D[7:0].
R-UB#
R-LB#
Input
Input
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on
flash-only stacked combinations.
FLASH RESET: Low-true input.
F-RST#
F-RST# low initializes flash internal circuitry and disables flash operations. F-RST# high enables flash
operation. Exit from reset places the flash in asynchronous read array mode.
P-Mode (PSRAM Mode): Low-true input.
P-Mode is used to program the Configuration Register, and enter/exit Low Power Mode of PSRAM die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-CRE (PSRAM Configuration Register Enable): High-true input.
P-Mode,
P-CRE
Input
P-CRE is high, write operations load the refresh control register or bus control register.
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-V voltage on this ball enables flash program/
PP
erase operations.
F-VPP,
Flash memory array contents cannot be altered when F-V (F-V
) < V
(V
). Erase /
PENLK
PP
PEN
PPLK
Power
Power
program operations at invalid F-V (F-V
product datasheet for additional details.
) voltages should not be attempted. Refer to flash discrete
F-VPEN
PP
PEN
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.
FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies
power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-V
<
CC
V
. Device operations at invalid F-V voltages should not be attempted.
F[2:1]-VCC
LKO
CC
F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked
combinations with only one flash die.
Preliminary Datasheet
25
Intel® Wireless Flash Memory (W18)
5.0 Maximum Ratings and Operating Conditions
Table 7.
Signal Descriptions - QUAD+ Package (Sheet 3 of 3)
SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC
Power
Power
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations
without SRAM die.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations
without PSRAM die.
VCCQ
VSS
Power
Power
DEVICE I/O POWER: Supply power for the device input and output buffers.
DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact Intel
regarding the use of balls designated RFU.
RFU
DU
—
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended,
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Notice: This datasheet contains information on products in the design phase of development. The information
here is subject to change without notice. Do not finalize a design with this information.
Table 8.
Absolute Maximum Ratings
Parameter
Maximum Rating
–40 °C to +85 °C
Notes
Temperature under Bias
Storage Temperature
–65 °C to +125 °C
–0.5 V to +2.45 V
–0.2 V to +14 V
–0.2 V to +2.45 V
100 mA
Voltage on Any Pin (except V , V
, V
)
CC
CCQ
PP
V
V
Voltage
1,2,3
PP
CC
and V
Voltage
1
4
CCQ
Output Short Circuit Current
Notes:
1.
All specified voltages are relative to V . Minimum DC voltage is –0.5 V on input/output pins and
SS
–0.2 V on V and V pins. During transitions, this level may undershoot to –2.0 V for periods
CC
PP
< 20 ns. Maximum DC voltage on input/output pins is V +0.5 V which, during transitions, may
CC
overshoot to V +2.0 V for periods < 20 ns.
CC
2.
3.
Maximum DC voltage on V may overshoot to +14.0 V for periods < 20 ns.
PP
V
program voltage is normally V
. V can be 12 V 0.6 V for 1000 cycles on the main
PP
PP1 PP
blocks and 2500 cycles on the parameter blocks during program/erase.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
26
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
5.0 Maximum Ratings and Operating Conditions
5.2
Operating Conditions
Table 9.
Extended Temperature Operation
Symbol
Parameter1
Min
Nom
Max
Unit
Note
T
Operating Temperature
–40
1.7
25
1.8
1.8
1.5
1.80
12.0
-
85
1.95
2.24
1.8
°C
A
V
Supply Voltage
3
3
4
2
2
2
2
2
2
CC
I/O Supply Voltage
1.7
Extended I/O Supply Voltage (130 nm and 180 nm)
1.35
0.90
11.4
-
V
V
V
Voltage Supply (Logic Level)
1.95
12.6
80
PP1
PP
Programming V
PP
t
Maximum V Hours
V
V
V
V
= 12 V
Hours
PPH
PP
PP
PP
PP
PP
Main and Parameter Blocks
Main Blocks
≤ V
100,000
-
-
-
CC
Block
Erase
Cycles
= 12 V
= 12 V
-
1000
2500
Cycles
Parameter Blocks
-
-
Notes:
1.
2.
See Section 6.1 and Section 6.2, “DC Voltage Characteristics” on page 30 for specific voltage-range specifications.
VPP is normally V . VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended
PP1
temperatures and 2500 cycles on parameter blocks at extended temperature.
Contact your Intel field representative for V /V operations down to 1.65 V.
3.
4.
CC CCQ
See the tables in Section 5.0, “Maximum Ratings and Operating Conditions” on page 26 and in Section 7.0, “AC
Characteristics” on page 31 for operating characteristics within the Extended V voltage range.
CCQ
Preliminary Datasheet
27
Intel® Wireless Flash Memory (W18)
6.0 Electrical Specifications
6.0
Electrical Specifications
6.1
DC Current Characteristics
Table 10.
DC Current Characteristics (Sheet 1 of 2)
V
= 1.35 V
CCQ
V
= 1.8 V
– 1.8 V (2)
CCQ
Symbol
Parameter (1)
32/64/128
Mbit
Unit
Test Condition
Note
32/64 Mbit
128 Mbit
Typ
Max
Typ Max Typ Max
V
V
V
= V Max
CC
CC
I
I
Input Load
-
-
TBD
TBD
-
-
1
1
-
-
1
1
µA
µA
= V Max
10
LI
CCQ
= V
CCQ
or GND
CCQ
IN
V
V
V
= V Max
CC
CC
Output
Leakage
D[15:0]
= V
Max
or GND
LO
CCQ
CCQ
= V
IN
CCQ
V
V
= V Max
CC
CC
180 nm
= V
Max
CCQ
CCQ
TBD
TBD
TBD
5
8
18
50
5
8
25
70
I
CE# = V
RST# =V
CCS
CC
SSQ
V
Standby
µA
11
CC
130 nm
TBD
TBD
I
CCS
90 nm
TBD TBD TBD TBD TBD
I
CCS
V
V
= V Max
CC
CC
= V
Max
CCQ
CCQ
180 nm
CE# = V
RST# =V
SSQ
CCQ
TBD
TBD
5
18
5
25
I
CCAPS
All other inputs =V
or
CCQ
V
APS
µA
12
SSQ
130 nm
TBD
TBD
TBD
8
50
8
70
I
CCAPS
90 nm
I
TBD TBD TBD TBD TBD
CCAPS
Asynchronous
Page Mode
f=13 MHz
TBD
TBD
3
6
4
7
mA 4 Word Read
3
3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
6
13
14
18
20
16
18
22
25
6
13
14
19
20
16
18
22
25
mA Burst length = 4
mA Burst length = 8
mA Burst length =16
8
8
Synchronous
Average CLK = 40 MHz
10
11
7
11
11
7
I
V
Read
CCR
CC
mA Burst length = Continuous
mA Burst length = 4
10
12
13
10
12
13
mA Burst length = 8
Synchronous
CLK = 54 MHz
3
mA Burst length = 16
mA Burst length = Continuous
28
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
6.0 Electrical Specifications
Table 10.
DC Current Characteristics (Sheet 2 of 2)
V
= 1.35 V
CCQ
V
= 1.8 V
– 1.8 V (2)
CCQ
Symbol
Parameter (1)
32/64/128
Mbit
Unit
Test Condition
Note
32/64 Mbit
128 Mbit
Typ
Max
Typ Max Typ Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8
17
20
25
30
N.A. N.A. mA Burst length = 4
N.A. N.A. mA Burst length = 8
N.A. N.A. mA Burst length = 16
N.A. N.A. mA Burst length = Continuous
Average
11
14
16
Synchronous
CLK = 66 MHz
I
I
V
3, 4
CCR
CC
Read
V
= V
Program in
PP
PP1,
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
18
8
40
15
40
15
18
18
18
8
40
15
40
15
25
25
mA
mA
mA
mA
µA
Progress
V
V
Program
4,5,6
4,5,6
CCW
CC
CC
V
= V Program in
PP2,
PP
Progress
V
= V
Block Erase in
Block Erase in
Program Sus-
Erase Sus-
PP
PP1,
18
8
18
8
Progress
I
I
Block Erase
CCE
V
= V
PP
PP2,
Progress
CE# = V
pended
CC,
V
V
Program Suspend
Erase Suspend
5
5
7
7
CCWS
CC
CE# = V
pended
CC,
I
I
5
5
µA
CCES
PPS
CC
V
V
V
Standby
PP
PP
PP
Program Suspend
Erase Suspend
TBD
TBD
TBD
0.2
2
5
0.2
2
5
µA
µA
V
<V
4
(I
I
PP
CC
PPWS,
PPES
)
V
V
≤ V
I
V
Read
TBD
TBD
15
15
PP
CC
PPR
PP
= V
Program in
Program in
Erase in
PP
PP1,
TBD 0.05 0.10 0.05 0.10
TBD 22 16 37
TBD 0.05 0.10 0.05 0.10
TBD 22 22
Progress
I
V
Program
mA
mA
5
5
PPW
PPE
PP
V
= V
PP
PP2,
TBD
TBD
TBD
8
Progress
V
= V
PP
PP1,
Progress
I
V
Erase
PP
V
= V
Erase in
PP2,
PP
8
8
Progress
Notes:
1.
2.
3.
All currents are RMS unless noted. Typical values at typical V , T = +25° C.
CC A
V
= 1.35 V - 1.8V is available on 130 nm and 180 nm products only.
CCQ
Automatic Power Savings (APS) reduces I
specification for details.
to approximately standby levels in static operation. See I
CCR
CCRQ
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Sampled, not 100% tested.
V
V
read + program current is the sum of V read and V program currents.
read + erase current is the sum of V read and V erase currents.
is specified with device deselected. If device is read while in erase suspend, current is I
CC
CC
CC
CC
CC CC
I
plus I
.
CCES
CCES
CCR
V
V
<= V
inhibits erase and program operations. Don’t use V
and V
outside their valid ranges.
PP
IL
PPLK
PPL
PPH
can undershoot to –0.4 V and V can overshoot to V
+0.4V for durations of 20 ns or less.
IH
CCQ
If V >V the input load current increases to 10 µA max.
IN CC
I
is the average current measured over any 5 ms time interval 5 µs after a CE# de-assertion.
CCS
Refer to section Section 8.2, “Automatic Power Savings (APS)” on page 52 for I
TBD values are to be determined pending silicon characterization.
measurement details.
CCAPS
Preliminary Datasheet
29
Intel® Wireless Flash Memory (W18)
6.0 Electrical Specifications
6.2
DC Voltage Characteristics
Table 11.
DC Voltage Characteristics
V
=1.35 V – 1.8 V
CCQ
V
= 1.8 V
(2)
CCQ
Symbol
Parameter (1)
Unit
Test Condition Note
32/64/128 Mbit
32/64 Mbit
128 Mbit
Min
Max
Min
Max
0.4
Min
Max
V
V
V
Input Low
Input High
Output Low
0
0.2
0
0
0.4
V
V
9
IL
V
– 0.2
V
– 0.4
V
CCQ
CCQ
CCQ
V
V
V
CCQ
IH
OL
CCQ
CCQ
– 0.4
V
V
= V Min
CC
CC
-
0.1
-
0.1
-
0.1
V
V
= V
Min
CCQ
CCQ
I
= 100 µA
OL
V
Output High
V
V
= V Min
CC CC
OH
V
– 0.1
V
– 0.1
V
CCQ
– 0.1
CCQ
CCQ
-
-
-
= V
= –100 µA
Min
CCQ
CCQ
I
OH
V
V
V
V
V
V
Lock-Out
Lock
-
0.4
-
0.4
-
0.4
V
V
V
8
PPLK
PP
1.0
TBD
-
-
1.0
0.9
-
-
1.0
0.9
-
-
LKO
CC
Lock
ILKOQ
CCQ
Note: For all numbered note references in this table, refer to the notes in Table 10, “DC Current Characteristics” on
page 28.
30
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.0
AC Characteristics
7.1
Read Operations – 90 nm and 130 nm Lithography
Table 12.
Read Operations— 90 nm and 130 nm Lithography (Sheet 1 of 2)
V
=
V
=
CCQ
CCQ
1.35 V – 1.8 V (3)
-65 -85
Min Max Min Max Min Max Min Max
1.7 V – 2.24 V
#
Parameter 1,2
Unit Notes
-60 -80
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
65
-
-
65
65
25
150
-
85
-
-
60
-
-
60
60
20
150
-
80
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8,9
8,9
8,9
5
AVAV
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
RST# High to Output Valid
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
OE# High to Output High-Z
CE# (OE#) High to Output Low-Z
85
85
30
150
80
80
25
150
-
-
-
-
-
-
-
-
-
-
-
-
0
0
-
0
0
-
0
0
-
0
0
-
6
-
-
-
5,6
6
17
14
-
20
14
14
14
-
17
14
-
-
-
-
-
5,6
5,6
0
0
0
0
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
t
t
t
t
t
t
t
Address Setup to ADV# High
CE# Low to ADV# High
7
10
-
-
-
7
10
-
-
-
7
10
-
-
-
7
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
AVVH
ELVH
VLQV
VLVH
VHVL
VHAX
APA
ADV# Low to Output Valid
ADV# Pulse Width Low
65
-
85
-
60
-
80
-
8,9
4
7
7
7
7
-
7
7
7
-
7
ADV# Pulse Width High
7
-
-
-
7
-
Address Hold from ADV# High
Page Address Access Time
7
-
-
-
7
-
-
25
30
20
-
25
Clock Specifications
R200
R201
R202
R203
f
t
t
t
CLK Frequency
-
18.5
4.5
-
54
-
-
25
9.5
-
40
-
-
15
3.5
-
66
-
-
18.5
4.5
-
54
-
MHz
ns
CLK
CLK Period
CLK
CLK High or Low Time
CLK Fall or Rise Time
-
-
-
-
ns
CH/L
CHCL
3
3
3
3
ns
Preliminary Datasheet
31
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Table 12.
Read Operations— 90 nm and 130 nm Lithography (Sheet 2 of 2)
V
=
V
=
CCQ
CCQ
1.35 V – 1.8 V (3)
-65 -85
Min Max Min Max Min Max Min Max
1.7 V – 2.24 V
#
Parameter 1,2
Unit Notes
-60 -80
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R308
R309
R310
t
t
t
t
t
t
t
t
t
t
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Valid
7
7
7
-
-
-
7
7
7
-
-
-
7
7
7
-
-
-
7
7
7
-
-
-
ns
ns
ns
AVCH
VLCH
ELCH
CHQV
CHQX
CHAX
CHTV
ELTV
-
-
-
-
14
-
20
-
11
-
14
-
ns
ns
ns
ns
ns
ns
ns
9
Output Hold from CLK
Address Hold from CLK
CLK to WAIT Valid
3
7
-
3
7
-
3
7
-
3
7
-
-
-
-
-
4
9
14
14
14
-
20
20
20
-
11
11
11
-
14
14
14
-
CE# Low to WAIT Valid
CE# High to WAIT High-Z
CE# Pulse Width High
-
-
-
-
7
-
-
-
-
6,7
7
EHTZ
EHEL
14
14
14
14
Notes:
1.
See Figure 22, “AC Input/Output Reference Waveform” on page 51 for timing measurements and
maximum allowable input slew rate.
2.
AC specifications assume the data bus voltage is less than or equal to V
initiated.
when a read operation is
CCQ
3.
4.
V
= 1.35 V - 1.8V is available on 130 nm and 180 nm products only.
CCQ
Address hold in synchronous-burst mode is defined as t
satisfied first.
or t
, whichever timing specification is
VHAX
CHAX
5.
6.
7.
8.
OE# may be delayed by up to t
Sampled, not 100% tested.
Applies only to subsequent synchronous reads.
During the initial access of a synchronous burst read, data from the first word may begin to be driven
onto the data bus as early as the first clock edge after t
All the preceding specifications apply to all densities.
– t
after the falling edge of CE# without impact to t
.
ELQV
ELQV GLQV
.
AVQV
9.
32
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.2
Read Operations – 180 nm Lithography
Table 13.
Read Operations — 180 nm Lithography (Sheet 1 of 2)
32/64 Mbit
128 Mbit
-85
#
Sym
Parameter (1,2)
–70
–85
Unit
Notes
Min
Max
Min
Max
Min
Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
-
-
70
70
30
150
-
85
-
-
85
85
30
150
-
85
-
-
85
85
30
150
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
Address to Output Delay
CE# Low to Output Delay
OE# Low to Output Delay
RST# High to Output Delay
CE# Low to Output in Low-Z
OE# Low to Output in Low-Z
CE# High to Output in High-Z
OE# High to Output in High-Z
CE# (OE#) High to Output in Low-Z
-
-
-
-
-
-
5
-
-
-
0
0
-
0
0
-
0
0
-
6
-
-
-
5,6
6
20
14
-
20
14
-
20
14
-
-
-
-
5,6
5,6
0
0
0
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
t
t
t
t
t
t
t
Address Setup to ADV# High
CE# Low to ADV# High
10
10
-
-
-
10
10
-
-
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
AVVH
ELVH
VLQV
VLVH
VHVL
VHAX
APA
ADV# Low to Output Delay
ADV# Pulse Width Low
70
-
85
-
85
-
10
10
9
10
10
9
10
10
9
ADV# Pulse Width High
-
-
-
Address Hold from ADV# High
Page Address Access Time
-
-
-
4
-
20
-
25
-
25
Clock Specifications
R200
R201
R202
R203
f
t
t
t
CLK Frequency
-
19
5
52
-
-
25
5
40
-
-
25
5
40
-
MHz
ns
CLK
CLK Period
CLK
CLK High or Low Time
CLK Fall or Rise Time
-
-
-
ns
CH/L
CHCL
-
3
-
3
-
3
ns
Preliminary Datasheet
33
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Table 13.
Read Operations — 180 nm Lithography (Sheet 2 of 2)
32/64 Mbit
128 Mbit
-85
#
Sym
Parameter (1,2)
–70
–85
Unit
Notes
Min
Max
Min
Max
Min
Max
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R308
R309
R310
t
t
t
t
t
t
t
t
t
t
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Valid
9
10
9
-
-
9
10
9
-
-
9
10
9
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVCH
VLCH
ELCH
CHQV
CHQX
CHAX
CHTV
ELTV
-
-
-
-
14
-
-
18
-
-
18
-
Output Hold from CLK
Address Hold from CLK
CLK to WAIT Valid
3.5
10
-
3.5
10
-
3.5
10
-
-
-
-
4
14
14
20
-
18
18
25
-
18
18
25
-
CE# Low to WAIT Valid
CE# High to WAIT High-Z
CE# Pulse Width High
-
-
-
7
6,7
7
-
-
-
EHTZ
EHEL
15
20
20
xNo
Note: For all numbered note references in this table, refer to the notes in Table 12, “Read Operations— 90 nm
and 130 nm Lithography” on page 31.
34
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 8.
Asynchronous Read Operation Waveform
R1
VIH
Valid
Address [A]
Address
VIL
R2
R3
VIH
VIL
CE# [E]
OE# [G]
R8
R9
VIH
VIL
R4
R7
VIH
VIL
WE# [W]
WAIT [T]
VOH
VOL
High Z
High Z
Note 1
VOH
VOL
High Z
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Notes:
1.
2.
WAIT shown asserted (RCR[10]=0)
ADV# assumed to be driven to VIL in this waveform
Preliminary Datasheet
35
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 9.
Latched Asynchronous Read Operation Waveform
R1
VIH
VIL
Valid
Address
Valid
Address
A[MAX:2] [A]
VIH
VIL
Valid
Address
Valid
Address
A[1:0] [A]
R2
R101
R104
R102
R105
VIH
R106
R103
ADV# [V]
CE# [E]
VIL
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
Data [Q]
RST# [P]
R7
VIH
VIL
VOH
VOL
High Z
Valid
Output
R5
R10
VIH
VIL
36
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 10.
Page-Mode Read Operation Waveform
R1
VIH
Valid
A[MAX:2] [A]
Address
VIL
R2
VIH
Valid
Valid
Valid
Valid
A[1:0] [A]
ADV# [V]
CE# [E]
Address
Address
Address
Address
VIL
R101
R105
VIH
R106
R103
VIL
R104
R102
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
OE# [G]
R7
VIH
WE# [W]
WAIT [T]
VIL
VOH
High Z
High Z
R108
Note 1
VOL
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Note: WAIT shown asserted (RCR[10] = 0).
Preliminary Datasheet
37
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 11.
Single Synchronous Read-Array Operation Waveform
VIH
VIL
Note 1
CLK [C]
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
RST# [P]
R303
R7
VIH
VIL
R309
R10
R308
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
R5
VIH
VIL
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 85 describes how to insert clock cycles during the initial
access.
2.
3.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data.
This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-
assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low)
WAIT signal would have remained asserted (low) as long as CE# is asserted (low).
38
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 12.
Synchronous 4-Word Burst Read Operation Waveform
VIH
VIL
Note 1
CLK [C]
0
1
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
R310
R8
VIH
VIL
R3
R102
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
R303
R7
R9
VIH
VIL
R309
R10
R308
R307
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
VIL
RST# [P]
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 85 describes how to insert clock cycles during the initial
access.
2.
WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle before, valid data.
Preliminary Datasheet
39
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 13.
WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform
VIH
VIL
Note 1
CLK [C]
0
1
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
R303
R7
VIH
VIL
R308
R307
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
RST# [P]
VIL
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 85 describes how to insert clock cycles during the initial
access.
2.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data
(assumed wait delay of two clocks, for example).
40
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 14.
WAIT Signal in Synchronous Non-Read Array Operation Waveform
VIH
Note 1
CLK [C]
VIL
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
RST# [P]
R303
R7
VIH
VIL
R309
R10
R308
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
R5
VIH
VIL
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 85 describes how to insert clock cycles during the initial
access.
2.
WAIT shown asserted (RCR[10]=0).
Preliminary Datasheet
41
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 15.
Burst Suspend
R304
R305
R305
R305
CLK
R1
R2
Address [A]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
R3
R8
R9
R4
R9
R4
R13
R12
WAIT [T]
WE# [W]
R7
R6
R304
Q1
R304
Q2
DATA [D/Q]
Q0
Q1
Note: During Burst Suspend, Clock signal can be held high or low.
42
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.3
AC Write Characteristics
Table 14.
AC Write Characteristics – 90 nm and 130 nm Lithography
V
=
V
=
CCQ
CCQ
1.35 V – 1.8 V
-65 -85
Min Max Min Max Min Max Min Max
1.7 V – 2.24 V
#
Sym
Parameter 1,2
Unit Notes
-60 -80
RST# High Recovery to WE#
(CE#) Low
W1
W2
t
(t
)
150
0
-
-
150
0
-
-
150
0
-
-
150
0
-
-
ns
ns
3
4
PHWL PHEL
CE# (WE#) Setup to WE# (CE#)
Low
t
(t
)
ELWL WLEL
WE# (CE#) Write Pulse Width
Low
W3
W4
W5
t
(t
)
50
50
50
-
-
-
60
60
60
-
-
-
40
40
40
-
-
-
60
60
60
-
-
-
ns
ns
ns
WLWH ELEH
t
(t
)
Data Setup to WE# (CE#) High
DVWH DVEH
Address Setup to WE# (CE#)
High
t
(t
)
AVWH AVEH
t
(t
CE# (WE#) Hold from WE# (CE#)
High
WHEH
EHWH
W6
W7
W8
0
0
0
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
)
t
(t
)
)
Data Hold from WE# (CE#) High
WHDX EHDX
Address Hold from WE# (CE#)
High
t
(t
WHAX EHAX
W9
t
(t
)
)
WE# (CE#) Pulse Width High
VPP Setup to WE# (CE#) High
VPP Hold from Valid SRD
20
200
0
-
-
-
-
-
-
25
200
0
-
-
-
-
-
-
20
200
0
-
-
-
-
-
-
25
200
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
5,6,7
3
WHWL EHEL
W10
W11
W12
W13
W14
t
(t
VPWH VPEH
t
t
3,8
3,8
3
QVVL
QVBL
WP# Hold from Valid SRD
WP# Setup to WE# (CE#) High
Write Recovery before Read
0
0
0
0
t
(t
)
)
200
0
200
0
200
0
200
0
BHWH BHEH
t
(t
WHGL EHGL
tAVQV
+ 25
tAVQV
+ 55
tAVQV
+20
tAVQV
+50
W16
t
WE# High to Valid Data
-
-
-
-
ns
3,6,10
WHQV
W18
W19
W20
t
WE# High to Address Valid
WE# High to CLK Valid
WE# High to ADV# High
0
-
-
-
0
-
-
-
0
-
-
-
0
-
-
-
ns
ns
ns
3,9,10
3,10
WHAV
WHCV
WHVH
t
t
16
16
20
20
12
12
20
20
3,10
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as during write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
high (whichever occurs first). Hence, t
Write pulse width high (t
(whichever is last). Hence, t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE#
WLWH
ELEH
= t
= t
= t
.
ELWH
WLWH
ELEH
WLEH
5.
6.
or t
) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
WHWL
EHEL
= t
= t
= t
.
EHWL
WHWL
EHEL
WHEL
System designers should take this into account and may insert a software No-Op instruction to delay the first
read after issuing a command.
7.
8.
9.
10.
tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH
both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever
occurs first).
Preliminary Datasheet
43
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
l
Table 15.
AC Write Characteristics – 180 nm Lithography
32-Mbit
64-Mbit
128-Mbit
#
Sym
Parameter 1,2
Unit
Notes
-70
-85
Min
Max
Min
Max
W1
W2
t
(t
)
RST# High Recovery to WE# (CE#) Low
CE# (WE#) Setup to WE# (CE#) Low
WE# (CE#) Write Pulse Width Low
Data Setup to WE# (CE#) High
Address Setup to WE# (CE#) High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
PHWL PHEL
t
(t
)
ELWL WLEL
W3
t
(t
)
45
45
45
0
60
60
60
0
WLWH ELEH
W4
t
(t
)
DVWH DVEH
W5
t
(t
)
AVWH AVEH
W6
t
(t
)
WHEH EHWH
W7
t
(t
)
0
0
WHDX EHDX
W8
t
(t
)
)
)
0
0
WHAX EHAX
W9
t
(t
25
200
0
25
200
0
5,6,7
3
WHWL EHEL
W10
W11
W12
W13
W14
t
(t
VPP Setup to WE# (CE#) High
VPP Hold from Valid SRD
VPWH VPEH
t
t
3,8
3,8
3
QVVL
QVBL
WP# Hold from Valid SRD
0
0
t
(t
)
)
WP# Setup to WE# (CE#) High
Write Recovery before Read
200
0
200
0
BHWH BHEH
t
(t
WHGL EHGL
tAVQV
+ 40
tAVQV
+ 50
W16
t
WE# High to Valid Data
-
-
ns
3,6,10
WHQV
W18
W19
W20
t
WE# High to Address Valid
WE# High to CLK Valid
WE# High to ADV# High
0
-
-
-
0
ns
ns
ns
3,9,10
3,10
WHAV
WHCV
WHVH
t
t
20
20
20
20
-
-
3,10
Notes:
1.
2.
3.
4.
WE# high (whichever occurs first). Hence, t
= t
= t
= t
.
WLWH
ELEH
WLEH
ELWH
5.
6.
Write pulse width high (t
low (whichever is last). Hence, t
or t
WHWL
) is defined from CE# or WE# high (whichever is first) to CE# or WE#
WHWL
EHEL
= t
= t
= t
.
EHWL
EHEL
WHEL
System designers should take this into account and may insert a software No-Op instruction to delay the first
read after issuing a command.
7.
8.
9.
10.
tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and
tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge,
whichever occurs first).
44
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 16.
Write Operations Waveform
VIH
CLK [C]
VIL
W19
Note 1
Note 2
W5
Note 3
Note 4
W18
Note 5
VIH
VIL
Valid
Address
Valid
Address
Valid
Address
Address [A]
R101
R105
VIH
R106
W8
ADV# [V]
VIL
R104
W2
W20
VIH
VIL
Note 6
CE# (WE#) [E(W)]
OE# [G]
W6
VIH
VIL
W3
W14
W9
VIH
VIL
Note 6
WE# (CE#) [W(E)]
Data [Q]
W1
W7
W16
VIH
VIL
Valid
SRD
Data In
Data In
W4
VIH
VIL
RST# [P]
W12
W11
W13
W10
VIH
VIL
WP# [B]
VPPH
VPPLK
VIL
VPP [V]
Notes:
1.
2.
3.
4.
5.
6.
7.
V
power-up and standby.
CC
Write Program or Erase Setup command.
Write valid address and data (for program) or Erase Confirm command.
Automated program/erase delay.
Read Status Register data (SRD) to determine program/erase operation completion.
OE# and CE# must be asserted and WE# must be deasserted for read operations.
CLK is ignored. (but may be kept active/toggling)
Preliminary Datasheet
45
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 17.
Asynchronous Read to Write Operation Waveform
R1
R2
W5
W8
Address [A]
R3
R8
CE# [E}
OE# [G]
R4
R9
W3
W2
W6
WE# [W]
R7
R6
W7
R10
W4
Data [D/Q]
RST# [P]
Q
D
R5
Figure 18.
Asynchronous Write to Read Operation
W5
W8
R1
Address [A]
W2
W6
R10
CE# [E}
WE# [W]
OE# [G]
W3
W18
W14
R4
W7
R2
R3
R9
W4
R8
Data [D/Q]
RST# [P]
D
Q
W1
46
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 19.
Synchronous Read to Write Operation
Latency Count
R301
R302
R306
CLK[C]
R2
W5
R101
W18
Address [A]
R105
R106
R102
R104
W20
ADV# [V]
R303
R3
R11
W6
CE# [E]
OE# [G]
R4
R8
W15
W19
W9
W3
W2
W8
WE#
R12
R307
R304
WAIT [T]
R13
R7
R305
W7
Data [D/Q]
Q
D
D
Preliminary Datasheet
47
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
Figure 20.
Synchronous Write To Read Operation
Latency Count
R2
R302
R301
CLK
W5
W8
R306
R106
Address [A]
W20
R104
ADV#
W6
R303
W2
R11
CE# [E}
W18
W19
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R12
R307
W7
R304
R304
R305
W4
R3
Data [D/Q]
RST# [P]
D
Q
Q
W1
48
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.4
Erase and Program Times
Table 16.
Erase and Program Times
V
V
PP2
PP1
Operation
Symbol
Parameter
Description1
Notes
Unit
Typ
Max
Typ
Max
Erasing and Suspending
W500
Erase Time
tERS/PB
4-Kword Parameter Block
32-Kword Main Block
Program Suspend
2,3
2,3
2
0.3
0.7
5
2.5
4
0.25
0.4
5
2.5
4
s
s
W501
t
t
t
ERS/MB
SUSP/P
SUSP/E
W600
10
20
10
20
µs
µs
Suspend
Latency
W601
Erase Suspend
2
5
5
Programming
W200
tPROG/W
tPROG/PB
tPROG/MB
Single Word
2
12
0.05
0.4
150
.23
1.8
8
130
0.07
0.6
µs
s
Program
Time
W201
4-Kword Parameter Block
32-Kword Main Block
2,3
2,3
0.03
0.24
W202
s
Enhanced Factory Programming5
W400
W401
W402
W403
W404
W405
tEFP/W
tEFP/PB
tEFP/MB
Single Word
4
N/A
N/A
N/A
-
N/A
-
3.1
15
16
-
µs
ms
ms
µs
Program
4-Kword Parameter Block
32-Kword Main Block
EFP Setup
2,3
2,3
-
120
-
-
t
t
t
N/A
N/A
N/A
5
EFP/SETUP
EFP/TRAN
EFP/VERIFY
Operation
Latency
Program to Verify Transition
Verify
N/A
N/A
2.7
1.7
5.6
130
µs
µs
Notes:
1.
Unless noted otherwise, all parameters are measured at T = +25 °C and nominal voltages, and they are sampled, not
A
100% tested.
2.
3.
4.
Excludes external system-level overhead.
Exact results may vary based on system overhead.
W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming
within a new word-line.
5.
Some EFP performance degradation may occur if block cycling exceeds 10.
Preliminary Datasheet
49
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.5
Reset Specifications
Table 17.
Reset Specifications
#
Symbol
Parameter1
Notes
Min
Max
Unit
P1
t
t
t
RST# Low to Reset during Read
RST# to
1, 2, 3, 4
1, 3, 4, 5
1, 3, 4, 5
1,3,4,5,6
100
-
ns
µs
µs
µs
PLPH
-
-
P2
PLRH
VCCPH
RST# to Reset during
VCC Power Valid to Reset
P3
60
-
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all product versions (packages and speeds).
The device may reset if t < t Min, but this is not guaranteed.
PLPH PLPH
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
If RST# is tied to VCC, the device is not ready until t
occurs after when V ≥ V Min.
CC CC
VCCPH
If RST# is tied to any supply/signal with V
voltage levels, the RST# input voltage must not exceed V until V
≥
CC
CCQ
CC
V
Min.
CC
Figure 21.
Reset Operations Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
RST# [P]
RST# [P]
RST# [P]
VCC
read mode
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
50
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
7.0 AC Characteristics
7.6
AC I/O Test Conditions
Figure 22.
AC Input/Output Reference Waveform
VCCQ
Test P
oints
Input
VCCQ/2
VCCQ/2
Output
0V
Note: Input timing begins, and output timing ends, at V
/2. Input rise and fall times (10% to 90%) < 5 ns.
CCQ
Worst case speed conditions are when V = V Min.
CC
CC
Figure 23.
Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 17 for component values.
Table 18.
Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration
C
(pF)
R (kΩ)
R (kΩ)
L
1
2
30
30
13.5
16.7
13.5
16.7
Note:
C
includes jig capacitance.
L
Figure 24.
Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Preliminary Datasheet
51
Intel® Wireless Flash Memory (W18)
8.0 Power and Reset Specifications
7.7
Device Capacitance
TA = +25 °C, f = 1 MHz
Symbol
Parameter§
Typ
Max
Unit
Condition
V = 0.0 V
IN
C
Input Capacitance
Output Capacitance
CE# Input Capacitance
6
8
8
pF
pF
pF
IN
C
12
12
V
= 0.0 V
OUT
OUT
C
10
V
= 0.0 V
IN
CE
§Sampled, not 100% tested.
8.0
Power and Reset Specifications
Intel® Wireless Flash Memory (W18) devices have a layered approach to power savings that can
significantly reduce overall system power consumption. The APS feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the memory enters its
standby mode, where current consumption is even lower. Asserting RST# provides current savings
similar to standby mode. The combination of these features can minimize memory power
consumption, and therefore, overall system power consumption.
8.1
8.2
Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 6.1, “DC
Current Characteristics” on page 28, for ICC values. When the device is in “active” state, it
consumes the most power from the system. Minimizing device active current therefore reduces
system power consumption, especially in battery-powered applications.
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during a read’s active state. During
APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 µs after the
following events happen:
• There is no internal sense activity;
• CE# is asserted;
• The address lines are quiescent, and at VSSQ or VCCQ
.
OE# may be asserted during APS.
8.3
Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables
most device circuitry and substantially reduces power consumption. Outputs are placed in a high-
impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or
52
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
8.0 Power and Reset Specifications
program operations, the device continues the operation and consumes corresponding active power
until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5
µs after a CE# de-assertion.
8.4
Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it
doesn’t matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the
system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs
should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur
when RST# is low.
8.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because
the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. To allow proper CPU/flash initialization
at system reset, connect RST# to the system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above VLKO
.
Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits
writes to the device. The CUI architecture provides additional protection because alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RST# is brought to VIH, regardless of its control input states. By
holding the device in reset (RST# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
8.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions
or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage). After completing program or block erase
operations (even after VPP transitions below VPPLK), the Read Array command must reset the CUI
to read-array mode if flash memory array access is desired.
8.5
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise. To minimize the effect
of this transient noise, device decoupling capacitors are required. Transient current magnitudes
depend on the device outputs’ capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should
have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground
(VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close as
possible to package signals.
Preliminary Datasheet
53
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
9.0
Bus Operations Overview
This section provides an overview of device bus operations. The Intel® Wireless Flash Memory
(W18) family includes an on-chip WSM to manage block erase and program algorithms. Its
Command User Interface (CUI) allows minimal processor overhead with RAM-like interface
timings. Device commands are written to the CUI using standard microprocessor timings.
9.1
Bus Operations
Bus cycles to/from the W18 device conform to standard microprocessor bus operations. Table 19
summarizes the bus operations and the logic levels that must be applied to the device’s control
signal inputs.
Table 19.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
Burst Suspend
V
V
V
V
V
V
X
L
L
L
L
L
L
L
H
X
L
L
H
H
H
L
Asserted
Driven
Output
IH
IH
IH
IH
IH
IH
Read
Write
Running
Output
Output
Input
1
Halted
X
L
H
H
H
X
X
Active
X
X
X
X
Asserted
Asserted
High-Z
2
3
Output Disable
Standby
X
X
X
H
X
X
High-Z
High-Z
High-Z
3
Reset
V
High-Z
3,4
IL
Notes:
1.
2.
3.
4.
WAIT is only valid during synchronous array-read operations.
Refer to the Table 21, “Bus Cycle Definitions” on page 59 for valid DQ[15:0] during a write operation.
X = Don’t Care (H or L).
RST# must be at V
0.2 V to meet the maximum specified power-down current.
SS
9.1.1
Reads
Device read operations are performed by placing the desired address on A[22:0] and asserting CE#
and OE#. ADV# must be low, and WE# and RST# must be high. All read operations are
independent of the voltage level on VPP.
CE#-low selects the device and enables its internal circuits. OE#-low or WE#-low determine
whether DQ[15:0] are outputs or inputs, respectively. OE# and WE# must not be low at the same
time - indeterminate device operation will result.
In asynchronous-page mode, the rising edge of ADV# can be used to latch the address. If only
asynchronous read mode is used, ADV# can be tied to ground. CLK is not used in asynchronous-
page mode and should be tied high.
In synchronous-burst mode, ADV# is used to latch the initial address - either on the rising edge of
ADV# or the rising (or falling) edge of CLK with ADV# low, whichever occurs first. CLK is used
in synchronous-burst mode to increment the internal address counter, and to output read data on
DQ[15:0].
Each device partition can be placed in any of several read states:
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
• Read Array: Returns flash array data from the addressed location.
• Read Identifier (ID): Returns manufacturer ID and device ID codes, block lock status, and
protection register data. Read Identifier information can be accessed from any 4-Mbit partition
base address.
• CFI Query: Returns Common Flash Interface (CFI) information. CFI information can be
accessed starting at 4-Mbit partition base addresses.
• Read Status Register: Returns Status Register (SR) data from the addressed partition.
The appropriate CUI command must be written to the partition in order to place it in the desired
read state (see Table 20, “Command Codes and Descriptions” on page 57). Non-array read
operations (Read ID, CFI Query, and Read Status Register) execute as single synchronous or
asynchronous read cycles. WAIT is asserted throughout non-array read operations.
9.1.2
Writes
Device write operations are performed by placing the desired address on A[22:0] and asserting
CE# and WE#. OE# and RST# must be high. Data to be written at the desired address is placed on
DQ[15:0]. ADV# must be held low throughout the write cycle or it can be toggled to latch the
address. If ADV# is held low, the address and data are latched on the rising edge of WE#. CLK is
not used during write operations, and is ignored; it can be either free-running or halted at VIL or
VIH. All write operations are asynchronous.
Table 20, “Command Codes and Descriptions” on page 57 shows the available device commands.
Appendix A, “Write State Machine States” on page 92 provides information on moving between
different device operations by using CUI commands.
9.1.3
9.1.4
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance
(High-Z) state.
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous-burst read
operation. This can be useful if the system needs to access another device on the same address and
data bus as the flash during a burst-read operation.
Synchronous-burst accesses can be suspended during the initial latency (before data is received) or
after the device has output data. When a burst access is suspended, internal array sensing continues
and any previously latched internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent
CLK edges resume the burst sequence where it left off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT is still driven. This
can cause contention with another device attempting to control the system’s READY signal during
a Burst Suspend. Systems using the Burst Suspend feature should not connect the device’s WAIT
signal directly to the system’s READY signal. Refer to Figure 15, “Burst Suspend” on page 42.
Preliminary Datasheet
55
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
9.1.5
9.1.6
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device
power consumption. In standby mode, outputs are placed in a high-impedance state independent of
OE#. If deselected during a program or erase algorithm, the device shall consume active power
until the program or erase operation completes.
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is
required before a write sequence can be initiated. After this wake-up interval, normal operation is
restored. The device defaults to read-array mode, the Status Register is set to 80h, and the
Configuration Register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See Figure 21, “Reset Operations Waveforms”
on page 50 for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory array. Automated flash
memories provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel flash memories allow
proper CPU initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal.
9.2
Device Commands
The device’s on-chip WSM manages erase and program algorithms. This local CPU (WSM)
controls the device’s in-system read, program, and erase operations. Bus cycles to or from the flash
memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV#
control signals dictate data flow into and out of the device. WAIT informs the CPU of valid data
during burst reads. Table 19, “Bus Operations Summary” on page 54 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s CUI. Table 20,
“Command Codes and Descriptions” on page 57 lists all possible command codes and
descriptions. Table 21, “Bus Cycle Definitions” on page 59 lists command definitions. Because
commands are partition-specific, it is important to issue write commands within the target address
range.
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
Table 20.
Command Codes and Descriptions (Sheet 1 of 2)
Device
Code
Operation
Description
Command
FFh
70h
Read Array
Places selected partition in Read Array mode.
Places selected partition in Status Register read mode. After issuing this
command, reading from the partition outputs SR data on DQ[15:0]. A partition
automatically enters this mode after issuing the Program or Erase command.
Read Status
Register
Places the selected partition in Read ID mode. Device reads from partition
addresses output manufacturer/device codes, Configuration Register data, block
lock status, or protection register data on DQ[15:0].
90h
98h
50h
Read Identifier
CFI Query
Read
Puts the addressed partition in CFI Query mode. Device reads from the partition
addresses output CFI information on DQ[7:0].
The WSM can set the Status Register’s block lock (SR[1]), V (SR[3]), program
PP
(SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can
only be cleared by a device reset or through the Clear Status Register command.
Clear Status
Register
This preferred program command’s first cycle prepares the CUI for a program
operation. The second cycle latches address and data, and executes the WSM
program algorithm at this location. Status register updates occur when CE# or
OE# is toggled. A Read Array command is required to read array data after
programming.
Word Program
Setup
40h
10h
30h
Alternate Setup
EFP Setup
Equivalent to a Program Setup command (40h).
Program
This program command activates EFP mode. The first write cycle sets up the
command. If the second cycle is an EFP Confirm command (D0h), subsequent
writes provide program data. All other commands are ignored after EFP mode
begins.
If the first command was EFP Setup (30h), the CUI latches the address and data,
and prepares the device for EFP mode.
D0h
20h
EFP Confirm
Erase Setup
This command prepares the CUI for Block Erase. The device erases the block
addressed by the Erase Confirm command. If the next command is not Erase
Confirm, the CUI sets Status Register bits SR[5:4] to indicate command
sequence error and places the partition in the read Status Register mode.
Erase
If the first command was Erase Setup (20h), the CUI latches address and data,
and erases the block indicated by the erase confirm cycle address. During
program or erase, the partition responds only to Read Status Register, Program
Suspend, and Erase Suspend commands. CE# or OE# toggle updates Status
Register data.
D0h
Erase Confirm
This command, issued at any device address, suspends the currently executing
program or erase operation. Status register data indicates the operation was
successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend)
and SR[7] are set. The WSM remains in the suspended state regardless of
control signal states (except RST#).
Program
Suspend or
Erase Suspend
B0h
D0h
Suspend
Suspend
Resume
This command, issued at any device address, resumes the suspended program
or erase operation.
Preliminary Datasheet
57
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
Table 20.
Command Codes and Descriptions (Sheet 2 of 2)
Device
Command
Operation
Code
Description
This command prepares the CUI lock configuration. If the next command is not
Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate
command sequence error.
60h
01h
Lock Setup
If the previous command was Lock Setup (60h), the CUI locks the addressed
block.
Lock Block
Block Locking
If the previous command was Lock Setup (60h), the CUI latches the address and
unlocks the addressed block. If previously locked-down, the operation has no
effect.
D0h Unlock Block
If the previous command was Lock Setup (60h), the CUI latches the address and
locks-down the addressed block.
2Fh
Lock-Down
This command prepares the CUI for a protection register program operation. The
second cycle latches address and data, and starts the WSM’s protection register
program or lock algorithm. Toggling CE# or OE# updates the flash Status
Register data. To read array data after programming, issue a Read Array
command.
Protection
C0h Program
Setup
Protection
This command prepares the CUI for device configuration. If Set Configuration
Register is not the next command, the CUI sets SR[5:4] to indicate command
sequence error.
Configuration
Setup
60h
03h
Configuration
Set
Configuration
Register
If the previous command was Configuration Setup (60h), the CUI latches the
address and writes the data from A[15:0] into the configuration register.
Subsequent read operations access array data.
Note: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.
58
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
Table 21.
Bus Cycle Definitions
First Bus Cycle
Second Bus Cycle
Bus
Operation
Command
Cycles
Oper
Addr1
Data2,3
Oper
Addr1
Data2,3
Read
Address
Array
Data
Read Array/Reset
≥1
Write
PnA
FFh
Read
Read Identifier
CFI Query
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
PnA
PnA
PnA
XX
90h
98h
Read
Read
Read
PBA+IA
PBA+QA
PnA
IC
Read
QD
Read Status Register
Clear Status Register
Block Erase
70h
SRD
1
50h
2
BA
20h
Write
Write
Write
BA
WA
WA
D0h
WD
D0h
Word Program
EFP
2
WA
WA
XX
40h/10h
30h
Program
and
Erase
>2
1
Program/Erase Suspend
Program/Erase Resume
Lock Block
B0h
D0h
60h
1
XX
2
BA
Write
Write
Write
BA
BA
BA
01h
D0h
2Fh
Lock
Unlock Block
2
BA
60h
Lock-Down Block
2
BA
60h
Protection Program
2
2
2
Write
Write
Write
PA
LPA
CD
C0h
C0h
60h
Write
Write
Write
PA
LPA
CD
PD
FFFDh
03h
Protection
Lock Protection Program
Configuration Set Configuration Register
Notes:
1.
First-cycle command addresses should be the same as the operation’s target address. Examples: the first-cycle address
for the Read Identifier command should be the same as the Identification code address (IA); the first-cycle address for
the Word Program command should be the same as the word address (WA) to be programmed; the first-cycle address
for the Erase/Program Suspend command should be the same as the address within the block to be suspended; etc.
XX = Any valid address within the device.
IA = Identification code address.
BA = Block Address. Any address within a specific block.
LPA = Lock Protection Address is obtained from the CFI (through the CFI Query command). The Intel Wireless Flash
Memory family’s LPA is at 0080h.
PA = User programmable 4-word protection address.
PnA = Any address within a specific partition.
PBA = Partition Base Address. The very first address of a particular partition.
QA = CFI code address.
WA = Word address of memory location to be written.
SRD = Status register data.
WD = Data to be written at location WA.
IC = Identifier code data.
PD = User programmable 4-word protection data.
QD = Query code data on DQ[7:0].
CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can select any
partition. See Table 29, “Read Configuration Register Descriptions” on page 83 for Configuration Register bits
descriptions.
Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
2.
3.
Preliminary Datasheet
59
Intel® Wireless Flash Memory (W18)
9.0 Bus Operations Overview
9.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur
between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed
partition into read-status mode, so if the same partition is read before the second “confirm” write
cycle is issued, Status Register data will be returned. Reads from other partitions, however, can
return actual array data assuming the addressed partition is already in read-array mode. Figure 25
on page 60 and Figure 26 on page 60 illustrate these two conditions.
Figure 25.
Normal Write and Read Cycles
Address [A]
WE# [W]
OE# [G]
Partition A
Partition A
Partition A
Data [Q]
20h
Block Erase Setup
D0h
Block Erase Confirm
FFh
Read Array
Figure 26.
Figure 27.
60
Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A]
WE# [W]
OE# [G]
Partition B
Partition A
Partition B
Partition A
Data [Q]
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Confirm
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a
command sequence error to appear in the Status Register. Figure 27 illustrates a command
sequence error.
Improper Command Sequencing
Address [A]
WE# [W]
Partition X
Partition Y
Partition X
Partition X
OE# [G]
Data [D/Q]
20h
FFh
D0h
SR Data
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
10.0 Read Operations
10.0
Read Operations
The device supports two read modes - asynchronous page and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register (RCR) must be configured to enable synchronous burst reads of the flash
memory array (see Section 14.0, “Set Read Configuration Register” on page 83).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or CFI Query. Upon power-up, or after a reset, all partitions of the device default to the Read
Array state. To change a partition’s read state, the appropriate read command must be written to the
device (see Section 9.2, “Device Commands” on page 56).
The following sections describe device read modes and read states in detail.
10.1
Asynchronous Page Read Mode
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 14.0, “Set Read Configuration Register” on page 83).
To perform an asynchronous page mode read, an address is driven onto A[MAX:0], and CE#, OE#
and ADV# are asserted. WE# and RST# must be deasserted. WAIT is asserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time tAVQ V delay. (see Section 7.0, “AC Characteristics” on page 31).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2
Synchronous Burst Read Mode
Section 14.0, “Set Read Configuration Register” on page 83continuous wordsTo perform a
synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and OE# are
asserted. WE# and RST# must be deasserted. ADV# is asserted, and then deasserted to latch the
address. Alternately, ADV# can remain asserted throughout the burst access, in which case the
address is latched on the next valid CLK edge after ADV# is asserted.
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61
Intel® Wireless Flash Memory (W18)
10.0 Read Operations
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see Section 14.2, “First Access
Latency Count (RCR[13:11])” on page 85). Subsequent data is output on valid CLK edges
following a minimum delay. However, for a synchronous non-array read, the same word of data
will be output on successive clock edges until the burst length requirements are satisfied.
Section 7.0, “AC Characteristics” on page 31
10.3
Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read
data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions
from VIL to VIH), all partitions default to asynchronous read-array mode. To read array data from
the flash device, first write the Read Array command (FFh) to the CUI and specify the desired
word address. Then read from that address. If a partition is already in read-array mode, issuing the
Read Array command is not required to read from that partition.
If the Read Array command is written to a partition that is erasing or programming, the device
presents invalid data on the bus until the program or erase operation completes. After the program
or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program
Suspend command suspends the WSM, a subsequent Read Array command places the addressed
partition in read-array mode. The Read Array command functions independently of VPP.
10.4
Read Identifier
The Read Identifier mode outputs the manufacturer/device identifier, block lock status, protection
register codes, and Configuration Register data. The identifier information is contained within a
separate memory space on the device and can be accessed along the 4-Mbit partition address range
supplied by the Read Identifier command (90h) address. Reads from addresses in Table 22 retrieve
ID information. Issuing a Read Identifier command to a partition that is programming or erasing
places that partition’s outputs in read ID mode while the partition continues to program or erase in
the background.
Table 22.
Device Identification Codes (Sheet 1 of 2)
Address1
Item
Data
Description
Base
Offset
Manufacturer ID
Partition
00h
0089h
8862h
8863h
8864h
8865h
8866h
8867h
D0 = 0
D0 = 1
Intel
32-Mbit TPD
32-Mbit BPD
64-Mbit TPD
64-Mbit BPD
128-Mbit TPD
128-Mbit BPD
Block is unlocked
Block is locked
Device ID
Partition
Block
01h
02h
Block Lock Status(2)
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
10.0 Read Operations
Table 22.
Device Identification Codes (Sheet 2 of 2)
Address1
Item
Data
Description
Base
Offset
D1 = 0
D1 = 1
Block is not locked-down
Block is locked down
Block Lock-Down Status(2)
Block
02h
Configuration Register
Partition
Partition
05h
80h
Register Data
Lock Data
Protection Register Lock Status
Multiple reads required to read
Register Data the entire 128-bit Protection
Register.
Protection Register
Partition
81h - 88h
Notes:
1.
The address is constructed from a base address plus an offset. For example, to read the Block Lock
Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e.
0F8002h. Then examine bit 0 of the data to determine if the block is locked.
2.
See Section 13.1.4, “Block Lock Status” on page 78 for valid lock status.
10.5
10.6
CFI Query
This device contains a separate CFI query database that acts as an “on-chip datasheet.” The CFI
information within this device can be accessed by issuing the Read Query command and supplying
a specific address. The address is constructed from the base address of a partition plus a particular
offset corresponding to the desired CFI field. Appendix B, “Common Flash Interface (CFI)” on
page 95 shows accessible CFI fields and their address offsets.
Issuing the Read Query command to a partition that is programming or erasing puts that partition in
read query mode while the partition continues to program or erase in the background.
Read Status Register
The device’s Status Register displays program and erase operation status. A partition’s status can
be read after writing the Read Status Register command to any location within the partition’s
address range. Read-status mode is the default read mode following a Program, Erase, or Lock
Block command sequence. Subsequent single reads from that partition will return its status until
another valid command is written.
The read-status mode supports single synchronous and single asynchronous reads only; it doesn’t
support burst reads. The first falling edge of OE# or CE# latches and updates Status Register data.
The operation doesn’t affect other partitions’ modes. Because the Status Register is 8 bits wide,
only DQ [7:0] contains valid Status Register data; DQ [15:8] contains zeros. See Table 23, “Status
Register Definitions” on page 64 and Table 24, “Status Register Descriptions” on page 64.
Each 4-Mbit partition contains its own Status Register. Bits SR[6:0] are unique to each partition,
but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides
program and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit,
SR[0], provides program and erase status of the addressed partition only. Status register bits
SR[6:1] present information about partition-specific program, erase, suspend, VPP, and block-lock
states. Table 25, “Status Register Device WSM and Partition Write Status Description” on page 64
presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Preliminary Datasheet
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Intel® Wireless Flash Memory (W18)
10.0 Read Operations
Table 23.
Status Register Definitions
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
DPS
1
PWS
0
Table 24.
Status Register Descriptions
Bit
Name
State
Description
SR[7] indicates erase or program completion in the
device. SR[6:1] are invalid while SR[7] = 0. See Table
25 for valid SR[7] and SR[0] combinations.
DWS
0 = Device WSM is Busy
1 = Device WSM is Ready
7
Device WSM Status
After issuing an Erase Suspend command, the WSM
halts and sets SR[7] and SR[6]. SR[6] remains set until
the device receives an Erase Resume command.
ESS
0 = Erase in progress/completed
6
Erase Suspend Status 1 = Erase suspended
ES
0 = Erase successful
1 = Erase error
SR[5] is set if an attempted erase failed. A Command
Sequence Error is indicated when SR[7,5:4] are set.
5
4
Erase Status
PS
0 = Program successful
1 = Program error
SR[4] is set if the WSM failed to program a word.
Program Status
The WSM indicates the V level after program or
PP
VPPS
0 = V OK
PP
3
2
erase completes. SR[3] does not provide continuous
VPP Status
1 = V low detect, operation aborted
PP
V
feedback and isn’t guaranteed when V ≠ V
.
PP
PP
PP1/2
PSS
After receiving a Program Suspend command, the
WSM halts execution and sets SR[7] and SR[2]. They
remain set until a Resume command is received.
0 = Program in progress/completed
1 = Program suspended
Program Suspend
Status
0 = Unlocked
If an erase or program operation is attempted to a
DPS
1
0
locked block (if WP# = V ), the WSM sets SR[1] and
1 = Aborted erase/program attempt on
locked block
IL
Device Protect Status
aborts the operation.
Addressed partition is erasing or programming. In EFP
mode, SR[0] indicates that a data-stream word has
finished programming or verifying depending on the
particular EFP phase. See Table 25 for valid SR[7] and
SR[0] combinations.
0 = This partition is busy, but only if
SR[7]=0
PWS
Partition Write Status 1 = Another partition is busy, but only if
SR[7]=0
Table 25.
Status Register Device WSM and Partition Write Status Description
DWS
(SR[7])
PWS
(SR[0])
Description
The addressed partition is performing a program/erase operation.
0
0
0
1
EFP: device has finished programming or verifying data, or is ready for data.
A partition other than the one currently addressed is performing a program/erase operation.
EFP: the device is either programming or verifying data.
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])
indicate whether other partitions are suspended.
1
1
0
1
EFP: the device has exited EFP mode.
Won’t occur in standard program or erase modes.
EFP: this combination does not occur.
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Intel® Wireless Flash Memory (W18)
11.0 Program Operations
10.7
Clear Status Register
The Clear Status Register command clears the Status Register and leaves all partition output states
unchanged. The WSM can set all Status Register bits and clear bits SR[7:6,2,0]. Because bits
SR[5,4,3,1] indicate various error conditions, they can only be cleared by the Clear Status Register
command. By allowing system software to reset these bits, several operations (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) can be
performed before reading the Status Register to determine error occurrence. If an error is detected,
the Status Register must be cleared before beginning another command or sequence. Device reset
(RST# = VIL) also clears the Status Register. This command functions independently of VPP.
11.0
Program Operations
11.1
Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed
events to program a word at the desired address and verify that the bits are sufficiently
programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not
change the memory cell contents.
Programming can occur in only one partition at a time. All other partitions must be in either a read
mode or erase suspend mode. Only one partition can be in erase suspend mode at a time.
The Status Register can be examined for program progress by reading any address within the
partition that is busy programming. However, while most Status Register bits are partition-specific,
the Device WSM Status bit, SR[7], is device-specific; that is, if the Status Register is read from any
other partition, SR[7] indicates program status of the entire device. This permits the system CPU to
monitor program progress while reading the status of other partitions.
CE# or OE# toggle (during polling) updates the Status Register. Several commands can be issued
to a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and
Read Query. The Read Array command can also be issued, but the read data is indeterminate.
After programming completes, three Status Register bits can signify various possible error
conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM couldn’t execute the
Word Program command because VPP was outside acceptable limits. If SR[1] is set, the program
was aborted because the WSM attempted to program a locked block.
After the Status Register data is examined, clear it with the Clear Status Register command before
a new command is issued. The partition remains in Status Register mode until another command is
written to that partition. Any command can be issued after the Status Register indicates program
completion.
If CE# is deasserted while the device is programming, the devices will not enter standby mode until
the program operation completes.
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Intel® Wireless Flash Memory (W18)
11.0 Program Operations
Figure 28.
Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = 40h
Write
Write
Read
Setup
Addr = Location to program (WA)
Write 40h,
Word Address
Data = Data to program (WD)
Addr = Location to program (WA)
Data
Write Data
Word Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Program
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Yes
Suspend
Program
0
SR[7] =
1
Repeat for subsequent programming operations.
Full status register check can be done after each program or
after a sequence of program operations.
Full Program
Status Check
(if desired)
Program
Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
VPP Range
Error
1
1
1
SR[3] =
0
Check SR[4]
1 = Data program error
Check SR[1]
Program
Error
SR[4] =
0
Standby
1 = Attempted program to locked block
Program aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts
Device
Protect Error
SR[1] =
0
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
11.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through
VCC. If VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform in-
system flash modifications. When VPP is connected to a 12 V power supply, the device draws
program and erase current directly from VPP. This eliminates the need for an external switching
transistor to control the VPP voltage. Figure 37, “Examples of VPP Power Supply Configurations”
on page 82 shows examples of flash power supply usage in various configurations.
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
11.0 Program Operations
The 12-V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use.12 V may be
applied to VPP during program and erase operations as specified in Section 5.2, “Operating
Conditions” on page 27. VPP may be connected to 12 V for a total of tPPH hours maximum.
Stressing the device beyond these limits may cause permanent damage.
11.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements
to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm
eliminates the traditional overhead delays of the conventional word program mode in both the host
programming system and the flash device. Changes to the conventional word programming
flowchart and internal WSM routine were developed because of today's beat-rate-sensitive
manufacturing environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the device and checks the Status Register to determine when
the data has completed programming. This modification essentially cuts write bus cycles in half.
Following each internal program pulse, the WSM increments the device's address to the next
physical location. Now, programming equipment can sequentially stream program data throughout
an entire block without having to setup and present each new address. In combination, these
enhancements reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this, PROM
programmers can rely on the device to verify that it has been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 29, “Enhanced
Factory Program Flowchart” on page 70 for a detailed graphical representation of how to
implement EFP.
11.3.1
EFP Requirements and Considerations
Ambient temperature: TA = 25 °C 5 °C
V
V
within specified operating range
CC
PP
EFP Requirements
EFP Considerations
within specified V
range
PP2
Target block unlocked
Block cycling below 100 erase cycles 1
RWW not supported2
EFP programs one block at a time
EFP cannot be suspended
Notes:
1.
Recommended for optimum performance. Some degradation in performance may
occur if this limit is exceeded, but the internal algorithm will continue to work
properly.
2.
Code or data cannot be read from another partition during EFP.
Preliminary Datasheet
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Intel® Wireless Flash Memory (W18)
11.0 Program Operations
11.3.2
Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions
from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP
level and block lock status). If an error is detected, Status Register bits SR[4], SR[3], and/or SR[1]
are set and EFP operation terminates.
Note:
After the EFP Setup and Confirm command sequence, reads from the device automatically output
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to program at WA0.
11.3.3
Program
After setup completion, the host programming system must check SR[0] to determine “data-stream
ready" status (SR[0]=0). Each subsequent write after this is a program-data write to the flash array.
Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional
pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the
program pulse.
The host programmer must poll the device's Status Register for the "program done" state after each
data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory
location have received their single WSM program pulse, and that the device is now ready for the
next word. Although the host may check full status for errors at any time, it is only necessary on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
The address can either hold constant or it can increment. The device compares the incoming
address to that stored from the setup phase (WA0); if they match, the WSM programs the new data
word at the next sequential memory location. If they differ, the WSM jumps to the new address
location.
The program phase concludes when the host programming system writes to a different block
address, and data supplied must be FFFFh. Upon program phase completion, the device enters the
EFP verify phase.
11.3.4
Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that
do not completely program on their first attempt, EFP internal verification identifies them and
applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of programming
incoming data, the WSM compares the verify-stream data to that which was previously
programmed into the block. If the data compares correctly, the host programmer proceeds to the
next word. If not, the host waits while the WSM applies an additional pulse(s).
The host programmer must reset its initial verify-word address to the same starting location
supplied during the program phase. It then reissues each data word in the same order as during the
program phase. Like programming, the host may write each subsequent data word to WA0 or it may
increment up through the block addresses.
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Intel® Wireless Flash Memory (W18)
11.0 Program Operations
The verification phase concludes when the interfacing programmer writes to a different block
address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the
EFP exit phase.
11.3.5
Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full status check
should be performed at this time to ensure the entire block programmed successfully. After EFP
exit, any valid CUI command can be issued.
Preliminary Datasheet
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Intel® Wireless Flash Memory (W18)
11.0 Program Operations
Figure 29.
Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE
EFP Setup
EFP Program
EFP Verify
EFP Exit
Read
Status Register
Read
Status Register
Read
Status Register
Start
VPP = 12V
Unlock Block
SR[0]=1=N
SR[0]=1=N
SR[7]=0=N
Data Stream
Ready?
Verify Stream
Ready?
EFP
Exited?
SR[0] =0=Y
SR[0] =0=Y
SR[7]=1=Y
Write 30h
Address = WA
0
Write Data
Address = WA
Write Data
Address = WA
Full Status Check
Procedure
0
0
Write D0h
Address = WA
0
Read
Status Register
Read
Status Register
Operation
Complete
EFP setup time
Program
Done?
Verify
Done?
Read
Status Register
SR[0]=0=Y
SR[0]=0=Y
N
N
Last
Data?
Last
Data?
EFP Setup
Done?
Y
Y
SR[7]=1=N
Check VPP & Lock
errors (SR[3,1])
Write FFFFh
Write FFFFh
Address ≠ BBA
Address
≠
BBA
Exit
EFP Setup
EFP Program
EFP Verify
Bus
State
Bus
State
Bus
State
Comments
Comments
Comments
Read
Status Register
Check SR[0]
Read
Status Register
Verify Check SR[0]
Unlock VPP = 12V
Block Unlock block
Write
Data
Standby Stream 0 = Ready for data
Standby Stream 0 = Ready for verify
EFP
Data = 30h
Write
Write
Ready? 1 = Not ready for data
Ready? 1 = Not ready for verify
Setup Address = WA
0
EFP
Data = D0h
Write
Data = Data to program
Write
Data = Word to verify
Confirm Address = WA
(note 1)
Address = WA
(note 2)
Address = WA
0
0
0
Read
Status Register
Read
Status Register
Standby
Read
EFP setup time
Check SR[0]
0 = Program done
1 = Program not done
Check SR[0]
0 = Verify done
1 = Verify not done
Program
Done?
Standby Verify
(note 3) Done?
Status Register
Check SR[7]
Standby
EFP
Standby Setup 0 = EFP ready
Done? 1 = EFP not ready
Last
Device automatically
Last
Device automatically
Standby
Standby
Data? increments address.
Data? increments address.
If SR[7] = 1:
Error
Exit Data = FFFFh
Write Program Address not within same
Phase BBA
Exit Data = FFFFh
Verify Addressnot within same
Phase BBA
Check SR[3,1]
Standby Condition
SR[3] = 1 = VPP error
Check
Write
SR[1] = 1 = locked block
EFP Exit
Status Register
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base
Read
Address) must remain constant throughout the program phase data stream; WA can be held
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur, the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal tWo A
terminates the EFP verify phase, and instructs the device to exit EFP.
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
Check SR[7]
EFP
Standby
0 = Exit not finished
Exited?
1 = Exit completed
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
See the Full Status Check procedure in the
Word Program flowchart.
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12.0 Program and Erase Operations
12.0
Program and Erase Operations
12.1
Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase
operation. The command can be issued at any device address. The partition corresponding to the
command’s address remains in its previous state. A suspend command allows data to be accessed
from memory locations other than the one being programmed or the block being erased.
A program operation can be suspended only to perform a read operation. An erase operation can be
suspended to perform either a program or a read operation within any block, except the block that
is erase suspended. A program command nested within a suspended erase can subsequently be
suspended to read yet another location. Once a program or erase process starts, the Suspend
command requests that the WSM suspend the program or erase sequence at predetermined points
in the algorithm. The partition that is actually suspended continues to output Status Register data
after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6]
and/or SR[2] are set.
To read data from blocks within the partition (other than an erase-suspended block), you can write
a Read Array command. Block erase cannot resume until the program operations initiated during
erase suspend are complete. Read Array, Read Status Register, Read Identifier (ID), Read Query,
and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear
Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-
Down Block are valid commands during erase suspend.
To read data from a block in a partition that is not programming or erasing, the operation does not
need to be suspended. If the other partition is already in Read Array, ID, or Query mode, issuing a
valid address returns corresponding data. If the other partition is not in a read mode, one of the read
commands must be issued to the partition before data can be read.
During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP
must remain at its program level and WP# must remain unchanged while in suspend mode.
A resume command instructs the WSM to continue programming or erasing and clears Status
Register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition.
When read at the partition that is programming or erasing, the device outputs data corresponding to
the partition’s last mode. If Status Register error bits are set, the Status Register can be cleared
before issuing the next instruction. RST# must remain at VIH. See Figure 30, “Program Suspend /
Resume Flowchart” on page 72, and Figure 31, “Erase Suspend / Resume Flowchart” on page 73.
If a suspended partition was placed in Read Array, Read Status Register, ID, or Query mode during
the suspend, the device remains in that mode and outputs data corresponding to that mode after the
program or erase operation is resumed. After resuming a suspended operation, issue the read
command appropriate to the read operation. To read status after resuming a suspended operation,
issue a Read Status Register command (70h) to return the suspended partition to status mode.
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Intel® Wireless Flash Memory (W18)
12.0 Program and Erase Operations
Figure 30.
Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = B0h
Write
Program Suspend
Write B0h
Suspend Addr = Block to suspend (BA)
Any Address
Read
Data = 70h
Read Status
Write 70h
Same Partition
Write
Read
Status Addr = Same partition
Status register data
Toggle CE# or OE# to update Status
register
Addr = Suspended block (BA)
Read Status
Register
Check SR.7
Standby
Standby
1 = WSM ready
0 = WSM busy
0
0
SR.7 =
1
Check SR.2
1 = Program suspended
0 = Program completed
Program
Completed
SR.2 =
Data = FFh
Addr = Any address within the
suspended partition
1
Read
Array
Write
Read
Write
Read Array
Write FFh
Susp Partition
Read array data from block other than
the one being programmed
Read Array
Data
Program Data = D0h
Resume Addr = Suspended block (BA)
If the suspended partition was placed in Read Array mode:
Done
No
Reading
Return partition to Status mode:
Read
Write
Data = 70h
Yes
Status
Addr = Same partition
Program Resume
Read Array
Write FFh
Write D0h
Any Address
Pgm'd Partition
Program
Resumed
Read Array
Data
Read Status
Write 70h
Same Partition
PGM_SUS.WMF
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Intel® Wireless Flash Memory (W18)
12.0 Program and Erase Operations
Figure 31.
Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Erase
Data = B0h
Erase Suspend
Write B0h
Any Address
Write
Write
Suspend Addr = Any address
Read
Status
Data = 70h
Addr = Same partition
Read
Status
Write 70h
Same Partition
Status register data. Toggle CE# or
OE# to update Status register
Addr = Same partition
Read
Read Status
Register
Check SR.7
Standby
1 = WSM ready
0 = WSM busy
0
0
SR.7 =
1
Check SR.6
1 = Erase suspended
0 = Erase completed
Standby
Write
Erase
Completed
SR.6 =
1
Read Array Data = FFh or 40h
or Program Addr = Block to program or read
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
Read Array
Data
Program
Loop
Program Data = D0h
Resume Addr = Any address
No
Write
If the suspended partition was placed in
Read Array mode or a Program Loop:
Done?
Yes
Return partition to Status mode:
Data = 70h
Addr = Same partition
Read
Status
Erase Resume
Read
Array
Write
Write D0h
Any Address
Write FFh
Erased Partition
Read Array
Data
Erase Resumed
Read
Status
Write 70h
Same Partition
ERAS_SUS.WMF
12.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm
(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode
at a time; other partitions must be in a read mode. The Erase Confirm command internally latches
the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared
while the erase executes.
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Intel® Wireless Flash Memory (W18)
12.0 Program and Erase Operations
After writing the Erase Confirm command, the selected partition is placed in read Status Register
mode and reads performed to that partition return the current status data. The address given during
the Erase Confirm command does not need to be the same address used in the Erase Setup
command. So, if the Erase Confirm command is given to partition B, then the selected block in
partition B will be erased even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase
Setup command must be immediately followed by the Erase Confirm command in order to execute
properly. If a different command is issued between the setup and confirm commands, the partition
is placed in read-status mode, the Status Register signals a command sequence error, and all
subsequent erase commands to that partition are ignored until the Status Register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the Status Register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent Status Register reads.
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12.0 Program and Erase Operations
Figure 32.
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Write
Write
Read
Write 20h
Block Address
Erase
Data = D0h
Confirm Addr = Block to be erased (BA)
Write D0h and
Block Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Erase
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
Standby
VPP Range
Error
1
1
1
1
SR[3] =
0
Check SR[5:4]
Both 1 = Command sequence error
Command
Sequence Error
Check SR[5]
1 = Block erase error
SR[5:4] =
0
Check SR[1]
Standby
1 = Attempted erase of locked block
Erase aborted
Block Erase
Error
SR[5] =
0
SR[3,1] must be cleared before the WSM will allow further
erase attempts.
Erase of
Locked Block
Aborted
SR[1] =
0
Only the Clear Status Register command clears SR[5:3,1].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
12.3
Read-While-Write and Read-While-Erase
The Intel® Wireless Flash Memory (W18) supports flexible multi-partition dual-operation
architecture. By dividing the flash memory into many separate partitions, the device can read from
one partition while programing or erasing in another partition; hence the terms, RWW and RWE.
Both of these features greatly enhance data storage performance.
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
The product does not support simultaneous program and erase operations. Attempting to perform
operations such as these results in a command sequence error. Only one partition can be
programming or erasing while another partition is reading. However, one partition may be in erase
suspend mode while a second partition is performing a program operation, and yet another partition
is executing a read command. Table 20, “Command Codes and Descriptions” on page 57 describes
the command codes available for all functions.
13.0
Security Modes
The Intel Wireless Flash Memory offers both hardware and software security features to protect the
flash data. The software security feature is used by executing the Lock Block command. The
hardware security feature is used by executing the Lock-Down Block command and by asserting
the WP# signal.
Refer to Figure 33, “Block Locking State Diagram” on page 77 for a state diagram of the flash
security features. Also see Figure 34, “Locking Operations Flowchart” on page 79.
13.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection. The first allows
software-only control of block locking (useful for frequently changed data blocks), while the
second requires hardware interaction before locking can be changed (protects infrequently changed
code blocks).
The following sections discuss the locking system operation. The term “state [abc]” specifies
locking states; for example, “state [001],” where a = WP# value, b = block lock-down status bit
D1, and c = Block Lock Status Register bit D0. Figure 33, “Block Locking State Diagram” on
page 77 defines possible locking states.
The following summarizes the locking functionality.
• All blocks power-up in a locked state.
• Unlock commands can unlock these blocks, and lock commands can lock them again.
• The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP# is
deasserted.
— The lock-down status bit is cleared only when the device is reset or powered-down.
Block lock registers are not affected by the VPP level. They may be modified and read even if VPP
≤ VPPLK
.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the
following sections. See Figure 34, “Locking Operations Flowchart” on page 79.
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13.0 Security Modes
Figure 33.
Block Locking State Diagram
Locked-
Down4,5
[011]
Hardware
Locked5
[011]
Locked
Power-Up/Reset
[X01]
WP# Hardware Control
Software
Locked
Unlocked
Unlocked
[111]
[110]
[X00]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
Notes:
1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to
this block. D1 = ‘1’, Lock-down has been issued to this block.
3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-Down states.
13.1.1
13.1.2
13.1.3
Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully
protected from alteration. Attempted program or erase operations to a locked block will return an
error in SR[1]. Unlocked blocks can be locked by using the Lock Block command sequence.
Similarly, a locked block’s status can be changed to unlocked or lock-down using the appropriate
software commands.
Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return
to the locked state when the device is reset or powered-down. An unlocked block’s status can be
changed to the locked or locked-down state using the appropriate software commands. A locked
block can be unlocked by writing the Unlock Block command sequence if the block is not locked-
down.
Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection beyond that
of a regular locked block. A block that is locked-down cannot have it’s state changed by software if
WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
Down command should be issued prior asserting WP# will put that block back to the locked-down
state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then
be unlocked by the Unlock Block command.
13.1.4
Block Lock Status
Every block’s lock status can be read in read identifier mode. To enter this mode, issue the Read
Identifier command to the device. Subsequent reads at BBA + 02h will output that block’s lock
status. For example, to read the block lock status of block 10, the address sent to the device should
be 50002h (for a top-parameter device). The lowest two data bits of the read data, DQ1 and DQ0,
represent the lock status. DQ0 indicates the block lock status. It is set by the Lock Block command
and cleared by the Block Unlock command. It is also set when entering the lock-down state. DQ1
indicates lock-down status and is set by the Lock-Down command. The lock-down status bit
cannot be cleared by software–only by device reset or power-down. See Table 26.
Table 26.
Write Protection Truth Table
VPP
WP#
RST#
Write Protection
Device inaccessible
X
X
X
V
IL
IH
IH
IH
V
V
V
V
Word program and block erase prohibited
All lock-down blocks locked
IL
X
V
IL
X
V
All lock-down blocks can be unlocked
IH
13.1.5
Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using the
standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful
when another block requires immediate updating.
To change block locking during an erase operation, first write the Erase Suspend command. After
checking SR[6] to determine the erase operation has suspended, write the desired lock command
sequence to a block; the lock status will be changed. After completing lock, unlock, read, or
program operations, resume the erase operation with the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits change immediately. When the erase operation is resumed, it will complete normally.
Locking operations cannot occur during program suspend. Appendix A, “Write State Machine
States” on page 92 shows valid commands during erase suspend.
13.1.6
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into Status Register results.
Because locking changes require 2-cycle command sequences, for example, 60h followed by 01h
to lock a block, following the Configuration Setup command (60h) with an invalid command
produces a command sequence error (SR[5:4]=11b). If a Lock Block command error occurs during
erase suspend, the device sets SR[4] and SR[5] to 1 even after the erase is resumed. When erase is
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
complete, possible errors during the erase cannot be detected from the Status Register because of
the previous locking command error. A similar situation occurs if a program operation error is
nested within an erase suspend.
13.1.7
WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# only affects blocks
that once had the Lock-Down command written to them. After the lock-down status bit is set for a
block, asserting WP# forces that block into the lock-down state [011] and prevents it from being
unlocked. After WP# is deasserted, the block’s state reverts to locked [111] and software
commands can then unlock the block (for erase or program operations) and subsequently re-lock it.
Only device reset or power-down can clear the lock-down status bit and render WP# ineffective.
Figure 34.
Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Operation
Command
Comments
Write 60h
Block Address
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Write
Write 01,D0,2Fh
Block Address
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
Write
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Write 90h
BBA + 02h
Write
Read ID Data = 90h
(Optional)
Plane
Addr = BBA + 02h
Read Block Lock
Status
Read
(Optional)
Block Lock Block Lock status data
Status Addr = BBA + 02h
Locking
Change?
No
Confirm locking change on DQ[1:0].
(See Block Locking State Transitions Table
for valid combinations.)
Standby
(Optional)
Yes
Read
Array
Data = FFh
Addr = Any address in same partition
Write
Write FFh
Partition Address
Lock Change
Complete
13.2
Protection Register
The Intel Wireless Flash Memory includes a 128-bit Protection Register. This protection register is
used to increase system security and for identification purposes. The protection register value can
match the flash component to the system’s CPU or ASIC to prevent device substitution.
The lower 64 bits within the protection register are programmed by Intel with a unique number in
each flash device. The upper 64 OTP bits within the protection register are left for the customer to
program. Once programmed, the customer segment can be locked to prevent further programming.
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
Note:
The individual bits of the user segment of the protection register are OTP, not the register in total.
The user may program each OTP bit individually, one at a time, if desired. After the protection
register is locked, however, the entire user segment is locked and no more user bits can be
programmed.
The protection register shares some of the same internal flash resources as the parameter partition.
Therefore, RWW is only allowed between the protection register and main partitions. Table 27
describes the operations allowed in the protection register, parameter partition, and main partition
during RWW and RWE.
Table 27.
Simultaneous Operations Allowed with the Protection Register
Parameter
Main
Protection
Register
Partition
Description
Partitions
Array Data
While programming or erasing in a main partition, the protection register can be
read from any other partition. Reading the parameter partition data is not
allowed if the protection register is being read from addresses within the
parameter partition.
See
Description
Read
Write/Erase
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers from parameter
partition addresses is not allowed.
See
Description
Read
Read
Write/Erase
Write/Erase
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers in a partition that
is different from the one being programmed or erased, and also different from
the parameter partition, is allowed.
Read
Write
While programming the protection register, reads are only allowed in the other
main partitions. Access to the parameter partition is not allowed. This is
because programming of the protection register can only occur in the
parameter partition, so it will exist in status mode.
No Access
Allowed
Read
Read
While programming or erasing the parameter partition, reads of the protection
registers are not allowed in any partition. Reads in other main partitions are
supported.
No Access
Allowed
Write/Erase
13.2.1
Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time
from addresses shown in Table 22, “Device Identification Codes” on page 62. The protection
register is read from the Read Identifier command and can be read in any partition.Writing the
Read Array command returns the device to read-array mode.
13.2.2
Programing the Protection Register
The Protection Program command should be issued only at the parameter (top or bottom) partition
followed by the data to be programmed at the specified location. It programs the upper 64 bits of
the protection register 16 bits at a time. Table 22, “Device Identification Codes” on page 62 shows
allowable addresses. See also Figure 35, “Protection Register Programming Flowchart” on
page 81. Issuing a Protection Program command outside the register’s address space results in a
Status Register error (SR[4]=1).
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
13.2.3
Locking the Protection Register
PR-LK.0 is programmed to 0 by Intel to protect the unique device number. PR-LK.1 can be
programmed by the user to lock the user portion (upper 64 bits) of the protection register (See
Figure 36, “Protection Register Locking“). This bit is set using the Protection Program command
to program “FFFDh” into PR-LK.
After PR-LK register bits are programmed (locked), the protection register’s stored values can’t be
changed. Protection Program commands written to a locked section result in a Status Register error
(SR[4]=1, SR[5]=1).
Figure 35.
Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMINGPROCEDURE
Bus
Start
Command
Comments
Operation
Protection
Program
Setup
Data = C0h
Addr = Protection address
Write
Write C0h
Addr=Prot addr
Protection Data = Data to program
Program Addr = Protection address
Write
Read
Write Protect.
Register
Address / Data
Read SRD
Toggle CE# or OE# to update SRD
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Standby
No
SR[7] = 1?
Yes
Protection Program operations addresses must be within the
protection register address space. Addresses outside this
space will return an error.
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full status register check can be done after each program or
after a sequence of program operations.
Program
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read SRD
SR[4:3] =
Command
Comments
SR[1] SR[3] SR[4]
Standby
Standby
Standby
0
0
1
0
1
1
VPP Error
1,1
1,0
1,1
VPP Range Error
Protection register
program error
1
0
1
Register locked;
SR[4,1] =
SR[4,1] =
Programming Error
Operation aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts.
Locked-Register
Program Aborted
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
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Intel® Wireless Flash Memory (W18)
13.0 Security Modes
Figure 36.
Protection Register Locking
0x88
User-Programmable
0x85
0x84
Intel Factory-Programmed
PR Lock Register 0
0x81
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x80
13.3
VPP Protection
The Intel® Wireless Flash Memory (W18) provides in-system program and erase at VPP1. For
factory programming, it also includes a low-cost, backward-compatible 12 V programming
feature.(See “Factory Programming” on page 66.) The EFP feature can also be used to greatly
improve factory program performance as explained in Section 11.3, “Enhanced Factory Program
(EFP)” on page 67.
In addition to the flexible block locking, holding the VPP programming voltage low can provide
absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or
erase operations result in an error displayed in SR[3]. (See Figure 37.)
Figure 37.
Examples of VPP Power Supply Configurations
System supply
12 V supply
System supply
VCC
VPP
VCC
VPP
Prot# (logic signal)
≤
Ω
10K
•
•
•
•
12 V fast programming
Absolute write protection with VPP VPPLK
Low-voltage programming
Absolute write protection via logic signal
≤
System supply
VCC
System supply
VCC
(Note 1)
VPP
VPP
12 V supply
•
•
Low voltage and 12 V fast programming
Low-voltage programming
Note: If the V supply can sink adequate current, you can use an appropriately valued resistor.
CC
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
14.0
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The Read Configuration Register data
is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Read
Configuration Register command is written along with the configuration data (on the address bus).
This is followed by a second write that confirms the operation and again presents the Read
Configuration Register data on the address bus. The Read Configuration Register data is latched on
the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions
independently of the applied VPP voltage. After executing this command, the device returns to
read-array mode. The Read Configuration Register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. See Table 28 and Table 29.
Table 28.
Read Configuration Register Summary
First Access
Burst Length
Latency Count
DO
C
RM
15
R
LC2 LC1 LC0 WT
13 12 11 10
WC
8
BS
7
CC
6
R
5
R
4
BW BL2 BL1 BL0
14
9
3
2
1
0
Table 29.
Read Configuration Register Descriptions (Sheet 1 of 2)
Bit
Name
Description1
Notes
RM
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
15
14
2
5
Read Mode
R
Reserved
LC[2:0]
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
13-11
10
6
3
6
6
First Access Latency
Count
WT
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
WAIT Signal Polarity
DOC
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
9
Data Output
Configuration
WC
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
8
7
WAIT Configuration
BS
1 = Linear Burst Order (Default)
Burst Sequence
CC
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
6
Clock
Configuration
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Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
Table 29.
Read Configuration Register Descriptions (Sheet 2 of 2)
Bit
Name
Description1
Notes
5
4
R
R
Reserved
Reserved
5
5
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by
CR[2:0].(Default)
BW
3
Burst Wrap
001 = 4-Word Burst
010 = 8-Word Burst
BL[2:0]
2-0
4
011 = 16-Word Burst
111 = Continuous Burst (Default)
Burst Length
Notes:
1.
2.
Undocumented combinations of bits are reserved by Intel for future implementations.
Synchronous and page read mode configurations affect reads from main blocks and parameter
blocks. Status Register and configuration reads support single read cycles. RCR[15]=1 disables
configuration set by RCR[14:0].
3.
4.
5.
6.
Data is not ready when WAIT is asserted.
Set the synchronous burst length. In asynchronous page mode, the page size equals four words.
Set all reserved Read Configuration Register bits to zero.
Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2
(RCR[13:11] = 010), data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before
delay (RCR[8] =1) is not supported.
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
14.1
Read Mode (RCR[15])
All partitions support two high-performance read configurations: synchronous burst mode and
asynchronous page mode (default). RCR[15] sets the read configuration to one of these modes.
Status register, query, and identifier modes support only asynchronous and single-synchronous read
operations.
14.2
First Access Latency Count (RCR[13:11])
The First Access Latency Count (RCR[13:11]) configuration tells the device how many clocks
must elapse from ADV# de-assertion (VIH) before the first data word should be driven onto its data
pins. The input clock frequency determines this value. See Table 29, “Read Configuration Register
Descriptions” on page 83 for latency values. Figure 38 shows data output latency from ADV#
assertion for different latencies. Refer to Section 14.2.1, “Latency Count Settings” on page 86 for
Latency Code Settings.
Figure 38.
First Access Latency Configuration
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
Code 3
Code 4
Code 5
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Note: Other First Access Latency Configuration settings are reserved.
)
Figure 39.
Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0 1 2 3 4 5 6 7 8 9 A B C D E F
16 Word Boundary
4 Word Boundary
Preliminary Datasheet
85
Note: The 16-word boundary is the end of the device sense word-line.
14.2.1
Latency Count Settings
Table 30.
Latency Count Settings for V
= 1.35 V - 1.8 V (130 nm lithography)
CCQ
VCCQ = 1.35 V - 1.8 V
Unit
t
/t
(65ns/14ns)
t
/t (85ns/20ns)
AVQV CHQV
AVQV CHQV
Latency Count
2
3, 4, 5
< 54
2
3, 4, 5
< 40
Settings
Frequency
< 39
< 30
MHz
Table 31.
Latency Count Setting for V
= 1.7 V - 2.24 V (90 nm and 130 nm lithography)
CCQ
VCCQ = 1.7 - 2.24 V
Unit
t
/t
(60ns/11ns)
t
/t
(80ns/14ns)
3
AVQV CHQV
AVQV CHQV
Latency Count
Settings
2
3
4, 5
< 66
2
4, 5
Frequency
Support
< 40
< 61
< 30
< 45
< 54
MHz
Table 32.
Latency Count Setting for V
= 1.7 V - 2.24 V (180 nm lithography)
CCQ
VCCQ = 1.7 - 2.24 V
Unit
t
/t
(70ns/14ns)
3, 4, 5
t
/t
(85ns/18ns)
3, 4, 5
AVQV CHQV
AVQV CHQV
Latency Count
2
2
Settings
Frequency
Support
< 35
<52
< 29
< 40
MHz
Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
Figure 40.
Example: Latency Count Setting at 3
tADD-DELAY
tDATA
2rd
0st
1nd
3th
4th
CLK (C)
CE# (E)
ADV# (V)
AMAX-0 (A)
Valid Address
High Z
Code 3
Valid
Output
Valid
Output
DQ15-0 (D/Q)
R103
14.3
14.4
WAIT Signal Polarity (RCR[10])
If the WT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. This means that
a 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data.
Conversely, if RCR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted,
then data is ready and valid. WAIT is asserted during asynchronous page mode reads.
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT
signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 14, “WAIT
Signal in Synchronous Non-Read Array Operation Waveform” on page 41.
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 10, “Page-Mode Read
Operation Waveform” on page 37, and Figure 8, “Asynchronous Read Operation Waveform” on
page 35.
From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or if the device is operating in asynchronous mode (RCR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity of what is appearing on the data bus.
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Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
Table 33.
WAIT Signal Conditions
CONDITION
WAIT
CE# = VIH
CE# = VIL
Tri-State
Active
OE#
No-Effect
Active
Synchronous Array Read
Synchronous Non-Array Read
Asserted
All Asynchronous Read and all Write Asserted
14.5
Data Hold (RCR[9])
The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word remains valid
on the data bus for one or two clock cycles. The processor’s minimum data set-up time and the
flash memory’s clock-to-data output delay determine whether one or two clocks are needed.
A DOC set at 1-clock data hold corresponds to a 1-clock data cycle; a DOC set at 2-clock data hold
corresponds to a 2-clock data cycle. The setting of this configuration bit depends on the system and
CPU characteristics. For clarification, see Figure 41, “Data Output Configuration with WAIT
Signal Delay” on page 89.
A method for determining this configuration setting is shown below.
To set the device at 1-clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
As an example, use a clock frequency of 66 MHz and a clock period of 15 ns. Assume the data
output hold time is one clock. Apply this data to the formula above for the subsequent reads:
11 ns + 4 ns ≤ 15 ns
This equation is satisfied, and data output will be available and valid at every clock period. If tDATA
is long, hold for two cycles.
During page-mode reads, the initial access time can be determined by the formula:
tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)
Subsequent reads in page mode are defined by:
tAPA (ns) + tDATA (ns)
(minimum time)
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Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
Figure 41.
Data Output Configuration with WAIT Signal Delay
CLK [C]
WAIT (CR.8 = 1)
Note 1
Note 1
tCHQV
WAIT (CR.8 = 0)
1 CLK
Data Hold
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [Q]
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
Note 1
Note 1
tCHTL/H
tCHQV
2 CLK
Data Hold
Valid
Output
Valid
Output
DQ15-0 [Q]
Note: WAIT shown asserted high (RCR[10]=1).
14.6
WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be
asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or continuous-word
burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary
(16-word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur.
If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read
sequence. The WAIT signal informs the system of this delay.
14.7
Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 34, “Sequence and
Burst Length” on page 90). When operating in a linear burst mode, either 4-, 8-, or 16-word burst
length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the device may incur an
output delay when the burst sequence crosses the first 16-word boundary. (See Figure 39, “Word
Boundary” on page 85 for word boundary description.) This depends on the starting address. If the
starting address is aligned to a 4-word boundary, there is no delay. If the starting address is the end
of a 4-word boundary, the output delay is one clock cycle less than the First Access Latency Count;
this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses
a 16-word boundary. The WAIT pin informs the system of this delay. For timing diagrams of WAIT
functionality, see these figures:
• Figure 11, “Single Synchronous Read-Array Operation Waveform” on page 38
• Figure 12, “Synchronous 4-Word Burst Read Operation Waveform” on page 39
Preliminary Datasheet
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Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
• Figure 13, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform” on
page 40
Table 34.
Sequence and Burst Length
Burst Addressing Sequence (Decimal)
4-Word Burst
RCR[2:0]=001b
8-Word Burst
RCR[2:0]=010b
16-Word Burst
RCR[2:0]=011b
Continuous Burst
RCR[2:0]=111b
Linear
Linear
Linear
Linear
0
1
2
3
4
5
6
7
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2...14-15
1-2-3...14-15-0
2-3-4...15-0-1
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
3-4-5...15-0-1-2
4-5-6...15-0-1-2-3
5-6-7...15-0-1...4
6-7-8...15-0-1...5
7-8-9...15-0-1...6
14
15
0
14-15-0-1...13
15-0-1-2-3...14
0-1-2...14-15
1-2-3...15-16
2-3-4...16-17
3-4-5...17-18
4-5-6...18-19
5-6-7...19-20
6-7-8...20-21
7-8-9...21-22
14-15-16-17-18-19-20-...
15-16-17-18-19-...
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
1
2
2-3-4-5-6-7-8-9
3
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4
5
6
7
14
15
14-15...28-29
15-16...29-30
14-15-16-17-18-19-20-...
15-16-17-18-19-20-21-...
14.8
Clock Edge (RCR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst
CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on
the clock’s rising or falling edge.
90
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
14.0 Set Read Configuration Register
14.9
Burst Wrap (RCR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst-
length boundary or whether they cross word-length boundaries to perform linear accesses. No-
wrap mode (RCR[3]=1) enables WAIT to hold off the system processor, as it does in the
continuous burst mode, until valid data is available. In no-wrap mode (RCR[3]=0), the device
operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-
word bursts.
For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst
sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for
example, consumes power during the initial access, again during the internal pipeline lookup as the
processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the device pipelines the next 4-word sequence. RCR[3]=1 while in 4-word burst mode
(no-wrap mode) reduces this excess power consumption.
14.10
Burst Length (RCR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in synchronous read
access of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous
word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 34, “Sequence and Burst Length” on page 90). When a burst cycle begins, the device outputs
synchronous burst data until it reaches the end of the “burstable” address space.
Preliminary Datasheet
91
Intel® Wireless Flash Memory (W18)
Appendix A Write State Machine States
Appendix A Write State Machine States
This table shows the command state transitions based on incoming commands. Only one partition
can be actively programming or erasing at a time.
Figure 42.
Write State Machine — Next State Table (Sheet 1 of 2)
C h iN e x t S ta te a fte r C o m m a n d In p u t
E n h a n c e d
B E C o n firm ,
C le a r
S ta tu s
R e g is te r(6
P ro g ra m /
E ra s e
S u s p e n d
R e a d
A rra y ( 3
P ro g ra m
E ra s e
S e tu p ( 4
F a c to ry
P g m
P /E R e s u m e ,
U L B
R e a d
S ta tu s
R e a d
ID /Q u e ry
C u r r e n t C h ip
)
,5
)
,5 )
S e tu p (4
)
S ta te (8 )
)
(9 )
S e tu p ( 4
C o n firm
(F F H )
R e a d y
(1 0 H /4 0 H )
(2 0 H )
(3 0 H )
(D 0 H )
(B 0 H )
(7 0 H )
(5 0 H )
(9 0 H , 9 8 H )
P ro g ra m
S e tu p
E ra s e
S e tu p
E F P
S e tu p
R e a d y
R e a d y
L o c k /C R S e tu p
O T P
R e a d y (L o c k E rro r)
R e a d y
R e a d y (L o c k E rro r)
S e tu p
B u s y
O T P B u s y
S e tu p
B u s y
P ro g ra m B u s y
P ro g ra m
P ro g ra m B u s y
P ro g ra m S u s p e n d
R e a d y (E rro r)
E ra s e B u s y
P g m S u s p
P ro g ra m B u s y
P ro g ra m S u s p e n d
R e a d y (E rro r)
E ra s e B u s y
S u s p e n d
S e tu p
B u s y
P g m B u s y
E ra s e B u s y
E ra s e S u s p
E ra s e
P g m in
E ra s e
S u s p S e tu p
E ra s e
S u s p e n d
S u s p e n d
E ra s e S u s p e n d
E ra s e B u s y
E ra s e S u s p e n d
S e tu p
B u s y
P ro g ra m in E ra s e S u s p e n d B u s y
P g m S u s p in
E ra s e S u s p
P ro g ra m in
E ra s e S u s p e n d
P ro g ra m in E ra s e S u s p e n d B u s y
P ro g ra m in E ra s e S u s p e n d B u s y
P g m in E ra s e
S u s p B u s y
S u s p e n d
P ro g ra m S u s p e n d in E ra s e S u s p e n d
P ro g ra m S u s p e n d in E ra s e S u s p e n d
L o c k /C R S e tu p in E ra s e
S u s p e n d
E ra s e S u s p e n d
(L o c k E rro r)
E ra s e S u s p e n d (L o c k E rro r)
R e a d y (E rro r)
E ra s e S u s p
S e tu p
E F P B u s y
E F P (7
V e r(7
R e a d y (E rro r)
E n h a n c e d
F a c to ry
)
E F P B u s y
E F P V e rify
P ro g ra m
)
O u tp u t N e x t S ta te a fte r C o m m a n d In p u t
P g m S e tu p ,
E ra s e S e tu p ,
O T P S e tu p ,
P g m in E ra s e S u s p S e tu p ,
E F P S e tu p ,
S ta tu s
E F P B u s y ,
V e rify B u s y
L o c k /C R S e tu p ,
L o c k /C R S e tu p in E ra s e S u s p
S ta tu s
O T P B u s y
S ta tu s
R e a d y ,
P g m B u s y ,
P g m S u s p e n d ,
E ra s e B u s y ,
E ra s e S u s p e n d ,
P g m In E ra s e S u s p B u s y ,
P g m S u s p In E ra s e S u s p
O u tp u t
d o e s n o t
c h a n g e
)
A rra y ( 3
S ta tu s
O u tp u t d o e s n o t c h a n g e
S ta tu s
ID /Q u e ry
92
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Intel® Wireless Flash Memory (W18)
Appendix A Write State Machine States
Figure 42.
Write State Machine — Next State Table (Sheet 2 of 2)
C h iN e x t S ta t e a f te r C o m m a n d In p u t
L o c k ,
U n lo c k ,
L o c k -d o w n ,
C R s e tu p (5
L o c k -
D o w n
B lo c k
E n h a n c e d
F a c t P g m
E x it ( b lk a d d
L o c k
B lo c k
Ille g a l
c o m m a n d s o r
E F P d a ta (2
O
T P
W
r ite C R
(9
W
S M
C u r r e n t C h ip
S t a t e ( 8 )
)
)
S e tu p (5
C o n firm
O p e r a tio n
C o m p le te s
(9
)
)
C o n firm
( 0 1 H )
)
(9 )
< >
W A 0 )
C o n firm
( 6 0 H )
( C 0 H )
( 2 F H )
(0 3 H )
( X X X X H )
( o th e r c o d e s )
L o c k /C R
S e tu p
O
T P
R e a d y
R e a d y
S e tu p
N /A
L o c k /C R S e tu p
O T P
R e a d y (L o c k E rr o r )
R e a d y
R e a d y
R e a d y
R e a d y ( L o c k E rr o r)
S e tu p
B u s y
O T P B u s y
R e a d y
N /A
S e tu p
B u s y
P r o g r a m B u s y
P r o g r a m B u s y
P ro g r a m
R e a d y
S u s p e n d
S e tu p
B u s y
P ro g r a m S u s p e n d
R e a d y (E r ro r )
N /A
E r a s e B u s y
E ra s e B u s y
R e a d y
E ra s e
L o c k /C R
S e tu p in
S u s p e n d
E r a s e S u s p e n d
N /A
E ra s e S u s p
S e tu p
B u s y
P r o g ra m in E ra s e S u s p e n d B u s y
P r o g ra m in E ra s e S u s p e n d B u s y
E r a s e
S u s p e n d
P ro g r a m in
E ra s e S u s p e n d
S u s p e n d
P r o g r a m S u s p e n d in E ra s e S u s p e n d
L o c k /C R S e tu p in E ra s e
S u s p e n d
E ra s e S u s p e n d
(L o c k E rr o r )
E r a s e S u s p
E r a s e S u s p
E r a s e S u s p
E ra s e S u s p e n d ( L o c k E r r o r)
N /A
S e tu p
R e a d y (E r ro r )
E n h a n c e d
F a c to ry
P ro g r a m
)
)
E F P (7
E F P (7
E F P V e r ify
E F P B u s y
E F P V e r ify
V e r(7
E F P V e r(7
)
)
R e a d y
R e a d y
O u t p u t N e x t S t a t e a f te r C o m m a n d In p u t
P g m S e tu p ,
E ra s e S e tu p ,
O T P S e tu p ,
P g m in E ra s e S u s p S e tu p ,
E F P S e tu p ,
S ta tu s
E F P B u s y ,
V e r ify B u s y
L o c k /C R S e tu p ,
L o c k /C R S e tu p in E ra s e S u s p
S ta tu s
A r r a y
S ta tu s
O u tp u t d o e s
n o t c h a n g e
O T P B u s y
R e a d y ,
P g m B u s y ,
P g m S u s p e n d ,
E ra s e B u s y ,
O u tp u t d o e s
n o t c h a n g e
S ta tu s
O u tp u t d o e s n o t c h a n g e
A rr a y
E ra s e S u s p e n d ,
P g m In E r a s e S u s p B u s y ,
P g m S u s p In E ra s e S u s p
Notes:
1.
The output state shows the type of data that appears at the outputs if the partition address is the same as the command
address.
A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.
Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state
does not depend on the partition's output state.
For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every read from
partition #4 (without issuing a new command) outputs the Status register.
Preliminary Datasheet
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Intel® Wireless Flash Memory (W18)
Appendix A Write State Machine States
2.
3.
Illegal commands are those not defined in the command set.
All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in
undermined data when a partition address is read.
4.
Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to different partitions,
the second write determines the active partition. Both partitions will output status information when read.
If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Intel devices.
The Clear Status command clears Status Register error bits except when the WSM is running (Pgm Busy, Erase Busy,
Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In
Erase Suspend).
5.
6.
7.
EFP writes are allowed only when Status Register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm
command. Any other commands are treated as data.
8.
9.
The "current state" is that of the WSM, not the partition.
Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then
move to the Ready State.
10.
In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block", and "CR
Write". Both cycles of other two cycle commands ("OEM CAM program & confirm", "Program OTP & confirm", "EFP Setup
& confirm", "Erase setup & confirm") will be ignored. In Program suspend or Program suspend in Erase suspend, both
cycles of all two cycle commands will be ignored.
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Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Appendix B Common Flash Interface (CFI)
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper
bytes. The device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 35.
Summary of Query Strucutre Output as a Function of Device and Mode
Hex
Offset
Hex
Code
ASCII
Value
Device
00010
00011
00012
51
52
59
“Q”
“R”
“Y”
Device Addresses
Preliminary Datasheet
95
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 36.
Example of Query Structure Output of x16 and x8 Devices
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
Value
Offset
Value
AX - A0
AX - A0
D16 - D0
D7 - D0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
0051
0052
0059
“Q”
“R”
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
51
52
59
“Q”
“R”
“Y”
“Y”
P ID
P rVendor
ID #
P ID
P ID
P rVendor
ID #
ID #
...
LO
LO
LO
P ID
HI
P
P rVendor
TblAdr
AltVendor
ID #
P ID
...
LO
HI
P
HI
A ID
...
...
LO
A ID
...
...
HI
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 37.
Query Structure
Description(1)
Manufacturer Code
Offset
00000h
Sub-Section Name
00001h
Device Code
Block-specific information
(BA+2)h(2)
Block Status register
00004-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
0001Bh
00027h
CFI query identification string
System interface information
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Intel-specific Extended Query Table
Notes:
1.
2.
3.
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as
a function of device bus width and mode.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size
is 32K-word).
Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
B.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
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Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation.
Table 38.
Block Status Register
Offset
Length
Description
Block Lock Status Register
Add.
BA+2 --00 or --01
Value
(BA+2)h(1)
1
BSR.0 Block lock status
0 = Unlocked
BA+2 (bit 0): 0 or 1
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
BA+2 (bit 1): 0 or 1
BA+2 (bit 2–7): 0
BSR 2–7: Reserved for future use
Notes:
1.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size
is 32K-word).
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Preliminary Datasheet
97
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 39.
CFI Identification
Hex
Code
Offset Length
Description
Addr.
Value
10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
10h
3
Query-unique ASCII string “QRY”
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specific algorithms.
13:
14:
--03
--00
13h
15h
17h
19h
2
2
2
2
—
—
—
—
15:
16:
--39
--00
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists.
17:
18:
--00
--00
Secondary algorithm Extended Query Table address.
0000h means none exists.
19:
1A:
--00
--00
Table 40.
System Interface Information
Hex
Add. Code Value
Offset
Length
Description
1Bh
1
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
1B:
1C:
1D:
1E:
--17 1.7V
--19 1.9V
--B4 11.4V
--C6 12.6V
--04 16µs
1Ch
1Dh
1Eh
1
1
1
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
PP [programming] supply minimum program/erase voltage
V
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP [programming] supply maximum program/erase voltage
V
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µ-sec
“n” such that typical max. buffer write time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
NA
1s
NA
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
--04 256µs
--00
--03
--00
NA
8s
NA
98
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
B.5
Device Geometry Definition
Table 41.
Device Geometry Definition
Offset
27h
Length
Description
Code
See table below
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
1
27:
28:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
2
1
0
28h
2
—
—
—
—
x64
x32
x16
9
x8
8
--01
x16
0
15
14
13
12
11
10
—
—
—
—
—
—
—
—
29:
2A:
2B:
2C:
--00
--00
--00
“n” such that maximum number of bytes in write buffer = 2n
2
1
2Ah
2Ch
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
4
4
4
2Dh
31h
35h
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
32 Mbit
64 Mbit
128 Mbit
–B –T
Address
–B
–T
–B
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--00
--00
--00
--00
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--07
--00
--20
--00
--7E
--00
--00
--01
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--7E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--07
--00
--20
--00
--FE
--00
--00
--01
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--FE
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
Preliminary Datasheet
99
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
B.6
Intel-Specific Extended Query Table
Table 42.
Primary Vendor-Specific Extended Query
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Primary extended query table
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
39:
3A:
3B:
3C:
3D:
3E:
3F:
40:
41:
--50
--52
--49
--31
--33
--E6
--03
--00
--00
"P"
"R"
"I"
"1"
"3"
Unique ASCII string “PRI“
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
No
Yes
Yes
Yes
Yes
Yes
bit 9 Simultaneous operations supported
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
(P+9)h
1
2
42:
--01
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bit 0 = 1
Yes
(P+A)h
(P+B)h
43:
44:
--03
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
(P+C)h
(P+D)h
1
1
45:
--18 1.8V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
PP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
V
46:
--C0 12.0V
100
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 43.
Protection Register Information
Offset
P = 39h
Lengt
h
Description
(Optional Flash Features and Commands)
Hex
Code
Add.
Value
Number of Protectuib Register fields in JEDEC ID space.
“00h” indicates that 256 protection fields are available.
(P + E)h
1
47:
--01
1
Protection Field 1: Protection Description
This field describes user-available One Time
Programmable (OTP) Protection Register bytes, Some
are pre-programmed with device-unique serial numbers.
Others are user-programmable. Bits are 0-15 point to the
Protection Register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-
programmable:
(P + E)h
(P + 10)h
(P + 11)h
(P + 12)h
48:
49:
4A:
4B:
--80
--00
--03
--03
80h
00h
4
8 byte
8 byte
•
•
•
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bites 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
•
bits 24-31 = “n” such that 2n = user-programmable bytes
Table 44.
Burst Read Information for Non-muxed Device
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Add. Code Value
(P+13)h
1
Page Mode Read capability
4C:
--03 8 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+14)h
(P+15)h
1
1
Number of synchronous mode read configuration fields that
4D:
4E:
--04
--01
4
4
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
(P+16)h
(P+17)h
(P+18)h
1
1
1
4F:
50:
51:
--02
--03
--07 Cont
8
16
Table 45.
Partition and Erase-block Region Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features and commands)
Len
(P+19)h (P+19)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
52:
52:
Preliminary Datasheet
101
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 46.
Partition Region 1 Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
53:
54:
55:
Top
53:
54:
55:
Bottom
Top
(P+1A)h (P+1A)h
(P+1B)h (P+1B)h
(Optional flash features and commands)
Number of identical partitions within the partition region
Len
2
(P+1C)h (P+1C)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
1
1
bits 4–7 = number of simultaneous Erase operations
(P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1E)h (P+1E)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1F)h (P+1F)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
56:
57:
58:
56:
57:
58:
1
1
(P+20)h (P+20)h Partition Region 1 Erase Block Type 1 Information
4
59:
5A:
5B:
5C:
5D:
5E:
5F:
59:
5A:
5B:
5C:
5D:
5E:
5F:
(P+21)h (P+21)h
(P+22)h (P+22)h
(P+23)h (P+23)h
(P+24)h (P+24)h
(P+25)h (P+25)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 1 (Erase Block Type 1)
Minimum block erase cycles x 1000
2
1
(P+26)h (P+26)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+27)h (P+27)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
60:
60:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+28)h
(P+29)h
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase block Type 2)
Minimum block erase cycles x 1000
61:
62:
63:
64:
65:
66:
67:
2
1
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+2F)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
68:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
102
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 47.
Partition Region 2 Information
P = 39h
Description
Address
Bot
69:
6A:
6B:
Top
61:
62:
63:
Bottom
Top
(Optional flash features and commands)
Len
2
(P+30)h (P+28)h Number of identical partitions within the partition region
(P+31)h (P+29)h
(P+32)h (P+2A)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
1
1
1
1
(P+33)h (P+2B)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+34)h (P+2C)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+35)h (P+2D)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
6C:
6D:
6E:
64:
65:
66:
(P+36)h (P+2E)h Partition Region 2 Erase Block Type 1 Information
4
6F:
70:
71:
72:
73:
74:
75:
67:
68:
69:
6A:
6B:
6C:
6D:
(P+37)h (P+2F)h
(P+38)h (P+30)h
(P+39)h (P+31)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3A)h (P+32)h Partition 2 (Erase block Type 1)
(P+3B)h (P+33)h Minimum block erase cycles x 1000
(P+3C)h (P+34)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+3D)h (P+35)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
76:
6E:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+36)h Partition Region 2 Erase Block Type 2 Information
6F:
70:
71:
72:
73:
74:
75:
(P+37)h
(P+38)h
(P+39)h
(P+3A)h
(P+3B)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 2 (Erase Block Type 2)
Minimum block erase cycles x 1000
2
1
(P+3C)h Partition 2 (Erase Block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserved for future use
(P+3D)h Partition 2 (Erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
76:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+3E)h (P+3E)h Features Space definitions (Reserved for future use)
(P+3F)h (P+3F)h Reserved for future use
TBD
Resv'd 78:
77:
77:
78:
Preliminary Datasheet
103
Intel® Wireless Flash Memory (W18)
Appendix B Common Flash Interface (CFI)
Table 48.
Partition and Erase Block Region Information
Address
32 Mbit
64Mbit
128Mbit
–B
–T
–B
–T
–B
–T
52:
53:
54:
55:
56:
57:
58:
59:
5A:
5B:
5C:
5D:
5E:
5F:
60:
61:
62:
63:
64:
65:
66:
67:
68:
69:
6A:
6B:
6C:
6D:
6E:
6F:
70:
71:
72:
73:
74:
75:
76:
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
Notes:
1.
2.
3.
The variable P is a pointer which is defined at CFI offset 15h.
TPD - Top parameter device; BPD - Bottom parameter device.
Partition: Each partition is 4 Mb in size. It can contain main blocks OR a combination of both main and
parameter blocks.
4.
Partition Region: Symmetrical partitions form a partition region. There are two partition regions: A
contains all the partitions that are made up of main blocks only; B contains the partition made up of the
parameter and the main blocks.
104
Preliminary Datasheet
Intel® Wireless Flash Memory (W18)
Appendix C Ordering Information
Appendix C Ordering Information
Figure 43.
VF BGA Ordering Information
G E 2 8 F 6 4 0 W 1 8 T E 6 0
Access Speed (ns)
(60,80)
Package:
GE = VF BGA, Leaded
PH = VF BGA, Pb-free
Process Identifier:
C = 180 nm
D = 130 nm
E = 90 nm
Product Line Designator:
for all Intel Flash Products
Parameter Location:
T = Top Parameter
B = Bottom Parameter
Device Density:
320 = 32Mbit
640 = 64Mbit
128 = 128Mbit
Product Family:
W18 = Intel® Wireless Flash
Memory
Figure 44.
SCSP Ordering Information
R D 4 8 F 3 0 0 0 W 0 Y B Q 0
Device Details:
0 = Initial Version
Package:
RD = SCSP, Leaded
PF = SCSP, Pb-Free
Ballout Indicator:
Q= QUAD+
Product Line:
48F = Flash Only
Parameter Location:
T = Top Parameter
B = Bottom Parameter
Flash Density:
0 = No die
3 = 128 Mbit
Voltage:
Y = 1.8 Volt I/O
Product Family Designator:
W = Intel® Wireless Flash Memory
Preliminary Datasheet
105
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