GT28F320C3T90_技术文档

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

8-, 16-, 32-MBIT

FLASH MEMORY FAMILY

28F008C3, 28F016C3, 28F032C3

28F800C3, 28F160C3, 28F320C3

Flexible SmartVoltage Technology

2.7 V–3.6 V Read/Program/Erase

Easy-12 V

Faster Production Programming

2.7 V or 1.65 V I/O Option Reduces

Overall System Power

12 V for Fast Production

Programming

No Additional System Logic

128-bit Protection Register

64-bit Unique Device Identifier

64-bit User Programmable OTP

Cells

High Performance

2.7 V–3.6 V: 90 ns Max Access Time

3.0 V–3.6 V: 80 ns Max Access Time

Extended Cycling Capability

Minimum 100,000 Block Erase

Cycles

Optimized Architecture for Code Plus

Data Storage

Flash Data Integrator Software

Flash Memory Manager

Eight 8-Kbyte Blocks,

Top or Bottom Locations

Up to Sixty-Three 64-KB Blocks

Fast Program Suspend Capability

Fast Erase Suspend Capability

System Interrupt Manager

Supports Parameter Storage,

Streaming Data (e.g., voice)

Automated Word/Byte Program and

Block Erase

Flexible Block Locking

Lock/Unlock Any Block

Full Protection on Power-Up

WP# Pin for Hardware Block

Protection

Command User Interface

Status Registers

SRAM-Compatible Write Interface

V_PP= GND Option

V_CCLockout Voltage

Cross-Compatible Command Support

Intel Basic Command Set

Common Flash Interface

Low Power Consumption

9 mA Typical Read Power

10 µA Typical Standby Power with

Automatic Power Savings Feature

x 16 for High Performance

48-Ball µBGA* Package

48-Lead TSOP Package

Extended Temperature Operation

–40 °C to +85 °C

x 8 I/O for Space Savings

48-Ball µBGA* Package

40-Lead TSOP Package

0.25 µ ETOX™ VI Flash Technology

The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a

feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage

capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking

allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data

Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on

the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP,

and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing

Intel’s WWW page: http://www.intel.com/design/flcomp.

May 1998

Order Number: 290645-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F008C3, 28F016C3, 28F032C3, 28F800C3, 28F160C3, 28F320C3 may contain design defects or errors known as

errata which may cause the product to deviate from published specifications. Current characterized errata are available on

request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call 1-800-548-4725

or visit Intel’s website at http:\\www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners.

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3 VOLT ADVANCED+ BOOT BLOCK

CONTENTS

PAGE

3.4 128-Bit Protection Register.........................21

3.4.1 Reading the Protection Register ..........21

3.4.2 Programming the Protection Register ..21

3.4.3 Locking the Protection Register ...........22

3.5 V_PPProgram and Erase Voltages...............22

1.0 INTRODUCTION .............................................5

1.1 3 Volt Advanced+ Boot Block Flash Memory

Enhancements............................................5

1.2 Product Overview.........................................6

2.0 PRODUCT DESCRIPTION..............................6

2.1 Package Pinouts ..........................................6

2.2 Block Organization.....................................10

2.2.1 Parameter Blocks................................10

2.2.2 Main Blocks.........................................10

3.5.1 Easy-12 V Operation for Fast

Manufacturing Programming...............22

3.5.2 V_PP≤ V_PPLKfor Complete Protection ...22

3.5.3 V_PPUsage...........................................22

3.6 Power Consumption...................................23

3.6.1 Active Power (Program/Erase/Read)...23

3.6.2 Automatic Power Savings (APS) .........23

3.6.3 Standby Power ....................................23

3.6.4 Deep Power-Down Mode.....................24

3.7 Power-Up/Down Operation.........................24

3.7.1 RP# Connected to System Reset ........24

3.7.2 V_CC, V_PPand RP# Transitions .............24

3.8 Power Supply Decoupling ..........................24

3.0 PRINCIPLES OF OPERATION .....................11

3.1 Bus Operation............................................11

3.1.1 Read....................................................11

3.1.2 Output Disable.....................................11

3.1.3 Standby...............................................11

3.1.4 Reset...................................................12

3.1.5 Write....................................................12

3.2 Modes of Operation....................................12

3.2.1 Read Array..........................................12

3.2.2 Read Configuration..............................13

3.2.3 Read Status Register ..........................13

3.2.3.1 Clearing the Status Register .........13

3.2.4 Read Query.........................................13

3.2.5 Program Mode.....................................14

4.0 ABSOLUTE MAXIMUM RATINGS................25

4.2 Operating Conditions..................................25

4.3 Capacitance ...............................................26

4.4 DC Characteristics .....................................26

4.5 AC Characteristics—Read Operations—

Extended Temperature..............................30

4.6 AC Characteristics—Write Operations—

Extended Temperature..............................32

3.2.5.1 Suspending and Resuming

Program.......................................14

4.7 Erase and Program Timings.......................33

4.8 Reset Operations .......................................35

3.2.6 Erase Mode.........................................14

3.2.6.1 Suspending and Resuming Erase.15

3.3 Flexible Block Locking................................19

3.3.1 Locking Operation ...............................19

3.3.2 Locked State .......................................19

3.3.3 Unlocked State....................................19

3.3.4 Lock-Down State.................................19

3.3.5 Reading a Block’s Lock Status ............20

5.0 ORDERING INFORMATION..........................36

6.0 ADDITIONAL INFORMATION.......................37

APPENDIX A: WSM Current/Next States ..........38

APPENDIX B: Program/Erase Flowcharts........40

3.3.6 Locking Operations during Erase

Suspend.............................................20

APPENDIX C: Common Flash Interface Query

Structure......................................................46

3.3.7 Status Register Error Checking ...........20

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APPENDIX D: Architecture Block Diagram......52

APPENDIX G: Device ID Table ..........................57

APPENDIX E: Word-Wide Memory Map

APPENDIX H: Protection Register

Diagrams .....................................................53

Addressing ..................................................58

APPENDIX F: Byte-Wide Memory Map

Diagrams .....................................................55

REVISION HISTORY

Date of

Revision

Version

Description

05/12/98

-001

Original version

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3 VOLT ADVANCED+ BOOT BLOCK

1.0 INTRODUCTION

1.1

3 Volt Advanced+ Boot Block

Flash Memory Enhancements

This document contains the specifications for the

3 Volt Advanced+ Boot Block flash memory family.

These flash memories add features which can be

used to enhance the security of systems: instant

block locking and a protection register.

The 3 Volt Advanced+ Boot Block flash memory

features:

•

Zero-latency, flexible block locking

128-bit Protection Register

Throughout this document, the term “2.7 V” refers

to the full voltage range 2.7 V–3.6 V (except where

noted otherwise) and “V_PP= 12 V” refers to 12 V

±5%. Sections 1 and 2 provide an overview of the

flash memory family including applications, pinouts,

pin descriptions and memory organization. Section

3 describes the operation of these products. Finally,

Section 4 contains the operating specifications.

Simple system implementation for 12 V

production programming with 2.7 V in-field

programming

•

Ultra-low power operation at 2.7 V

Minimum 100,000 block erase cycles

Common Flash Interface for software query of

device specs and features

Table 1. 3 Volt Advanced+ Boot Block Feature Summary

8 M⁽²⁾

16 M

8 M⁽²⁾

16 M

32 M

Feature

Reference

Table 8

32 M⁽¹⁾

V_CCOperating Voltage

V_PPVoltage

2.7 V – 3.6 V

Provides complete write protection with

optional 12V Fast Programming

Table 8

V_CCQI/O Voltage

Bus Width

2.7 V– 3.6 V

Note 3

8-bit

16-bit

Table 2

Table 11

Speed (ns)

90, 110 @ 2.7 V and 80, 100 @ 3.0 V

Blocking (top or bottom)

8 x 8-Kbyte parameter

8 x 4-Kword parameter

Section 2.2

Appendix E and F

4-Mb: 7 x 64-Kbyte main

8-Mb: 15 x 64-Kbyte main

4-Mb: 7 x 32-Kword main 8-

Mb: 15 x 32-Kword main

16-Mb: 31 x 64-Kbyte main 16-Mb: 31 x 32-Kword main

32-Mb: 63 x 64-Kbyte main 32-Mb: 63 x 32-Kword main

Operating Temperature

Program/Erase Cycling

Packages

Extended: –40 °C to +85 °C

100,000 cycles

Table 8

40-Lead TSOP⁽¹⁾

48-Lead TSOP

48-Ball µBGA* CSP⁽²⁾

Figures 1, 2, 3,

and 4

48-Ball µBGA* CSP⁽²⁾

Block Locking

Flexible locking of any block with zero latency

Section 3.3

Protection Register

64-bit unique device number, 64-bit user programmable Section 3.4

NOTES:

1. 32-Mbit density not available in 40-lead TSOP.

2. 8-Mbit density not available in µBGA* CSP.

3. V_CCQoperation at 1.65 V — 2.5 V available upon request.

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3 VOLT ADVANCED+ BOOT BLOCK

1.2 Product Overview

E

The status register indicates the status of the WSM

by signifying block erase or word program

completion and status.

Intel provides secure low voltage memory solutions

with the Advanced Boot Block family of products. A

new block locking feature allows instant

locking/unlocking of any block with zero-latency. A

128-bit protection register allows unique flash

device identification.

Program and erase automation allows program and

erase operations to be executed using an industry-

standard two-write command sequence to the CUI.

Program operations are performed in word or byte

increments. Erase operations erase all locations

within a block simultaneously. Both program and

erase operations can be suspended by the system

software in order to read from any other block. In

addition, data can be programmed to another block

during an erase suspend.

Discrete supply pins provide single voltage read,

program, and erase capability at 2.7 V while also

allowing 12 V V_PPfor faster production

programming. Easy-12 V, a new feature designed

to reduce external logic, simplifies board designs

when combining 12 V production programming with

2.7 V in-field programming.

The 3 Volt Advanced+ Boot Block flash memories

offer two low power savings features: Automatic

Power Savings (APS) and standby mode. The

device automatically enters APS mode following the

completion of a read cycle. Standby mode is

initiated when the system deselects the device by

driving CE# inactive. Combined, these two power

savings features significantly reduce power

consumption.

The 3 Volt Advanced+ Boot Block flash memory

products are available in either x8 or x16 packages

in the following densities: (see Section 6, Ordering

Information)

•

8-Mbit (8,388,608 bit) flash memories organized

as either 512 Kwords of 16 bits each or 1024

Kbytes or 8 bits each.

The device can be reset by lowering RP# to GND.

This provides CPU-memory reset synchronization

and additional protection against bus noise that

may occur during system reset and power-up/down

sequences (see Section 3.5 and 3.6).

16-Mbit (16,777,216 bit) flash memories

organized as either 1024 Kwords of 16 bits

each or 2048 Kbytes of 8 bits each.

32-Mbit (33,554,432 bit) flash memories

organized as either 2048 Kwords of 16 bits

each or 4096 Kbytes of 8 bits each.

Refer to the DC Characteristics Section 4.4 for

complete current and voltage specifications. Refer

to the AC Characteristics Sections 4.5 and 4.6, for

read and write performance specifications. Program

and erase times and shown in Section 4.7.

Eight 8-KB parameter blocks are located at either

the top (denoted by -T suffix) or the bottom (-B

suffix) of the address map in order to accommodate

different microprocessor protocols for kernel code

location. The remaining memory is grouped into 64-

Kbyte main blocks.

2.0 PRODUCT DESCRIPTION

This section provides device pin descriptions and

package pinouts for the 3 Volt Advanced+ Boot

Block flash memory family, which is available in 40-

Lead TSOP (x8, Figure 1), 48-lead TSOP (x16,

Figure 2) and 48-ball µBGA packages (Figures 3

and 4).

All blocks can be locked or unlocked instantly to

provide complete protection for code or data. (see

Section 3.3 for details).

The Command User Interface (CUI) serves as the

interface

between

the

microprocessor

or

microcontroller and the internal operation of the

flash memory. The internal Write State Machine

(WSM) automatically executes the algorithms and

timings necessary for program and erase

2.1

Package Pinouts

operations,

including

verification,

thereby

In each diagram, upgrade pins from one density to

the next are circled.

unburdening the microprocessor or microcontroller.

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3 VOLT ADVANCED+ BOOT BLOCK

A₁₆

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₉

A₁₇

GND

A₂₀

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

2

16M

8M

3

A₁₉

A₁₀

DQ₇

DQ₆

DQ₅

DQ₄

V_CCQ

V_CC

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A₈

WE#

RP#

V_PP

Advanced Boot

40-Lead TSOP

10 mm x 20 mm

NC

WP#

DQ₃

DQ₂

DQ₁

DQ₀

OE#

GND

A₁₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

TOP VIEW

CE#

A₀

NOTES:

1. 40-Lead TSOP available for 8- and 16-Mbit densities only.

2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.

Figure 1. 40-Lead TSOP Package for x8 Configurations

A₁₆

V_CCQ

GND

DQ₁₅

DQ₇

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

A₉

A₈

A₂₀

NC

WE#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ₁₄

DQ₆

DQ₁₃

DQ₅

DQ₁₂

DQ⁴

V_CC

DQ₁₁

DQ₃

DQ₁₀

DQ₂

DQ₉

DQ₁

DQ₈

DQ₀

OE#

GND

CE#

A₀

32M

Advanced Boot Block

48-Lead TSOP

12 mm x 20 mm

RP#

V_PP

TOP VIEW

WP#

A₁₉

16M

8M

A₁₈

A₁₇

A₇

A₆

A₅

A₄

A₃

A₂

A₁

NOTE:

Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.

Figure 2. 48-Lead TSOP Package for x16 Configurations

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3 VOLT ADVANCED+ BOOT BLOCK

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1

2

3

4

5

6

7

8

16M

A

V

WP#

A

13

A

B

C

D

E

F

11

10

12

8

PP

19

17

7

5

3

4

2

1

0

A

WE# RP#

A

14

15

16

18

32M

A

D

A

D

A

D

9

5

6

20

11

6

8

9

D

2

CE#

14

V

D

3

D

0

GND

OE#

CCQ

15

12

GND

D

V

D

1

7

13

4

CC

10

NOTES:

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address

solder balls. Routing is not recommended in this area. A₁₉is the upgrade address for the 16-Mbit device. A₂₀is the

upgrade address for the 32-Mbit device.

2. 8-Mbit not available on µBGA* CSP.

Figure 3. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)

1

2

3

4

5

6

7

8

16M

A

V

WP#

14

12

8

PP

20

7

4

A

B

C

D

E

F

A

WE#

RP#

15

10

19

18

5

2

32M

A

9

A

16

17

13

21

6

3

1

0

A

D

5

D

2

A

NC

A

NC

CE#

V

D

6

D

3

D

0

GND

OE#

CCQ

11

D

4

V

D

1

GND

NC

7

CC

NOTES:

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address

solder balls. Routing is not recommended in this area. A₂₀is the upgrade address for the 16-Mbit device. A₂₁is the

upgrade address for the 32-Mbit device.

2. 8-Mbit not available on µBGA* CSP.

Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)

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3 VOLT ADVANCED+ BOOT BLOCK

Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions

Symbol

Type

Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a program or erase cycle.

8-Mbit x 8 A[0-19], 16-Mbit x 8 A[0-20], 32-Mbit x 8 A[0-21]

8-Mbit x 16 A[0-18], 16-Mbit x 16 A[0-19], 32-Mbit x 16 A[0-20]

A₀–A₂₁

INPUT

DQ₀–DQ₇

INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Inputs commands to the

Command User Interface when CE# and WE# are active. Data is

internally latched. Outputs array, configuration and status register data.

The data pins float to tri-state when the chip is de-selected or the outputs

are disabled.

DQ₈–DQ₁₅INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Data is internally latched.

Outputs array and configuration data. The data pins float to tri-state when

the chip is de-selected. Not included on x8 products.

CE#

INPUT

CHIP ENABLE: Activates the internal control logic, input buffers,

decoders and sense amplifiers. CE# is active low. CE# high de-selects

the memory device and reduces power consumption to standby levels.

OE#

WE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data

buffers during a read operation. OE# is active low.

WRITE ENABLE: Controls writes to the Command Register and

memory array. WE# is active low. Addresses and data are latched on

the rising edge of the second WE# pulse.

RP#

INPUT

RESET/DEEP POWER-DOWN: Uses two voltage levels (V_IL, V_IH) to

control reset/deep power-down mode.

When RP# is at logic low, the device is in reset/deep power-down

mode, which drives the outputs to High-Z, resets the Write State

Machine, and minimizes current levels (I_CCD).

When RP# is at logic high, the device is in standard operation.

When RP# transitions from logic-low to logic-high, the device resets all

blocks to locked and defaults to the read array mode.

WP#

INPUT

WRITE PROTECT: Controls the lock-down function of the flexible

Locking feature

When WP# is a logic low, the lock-down mechanism is enabled and

blocks marked lock-down cannot be unlocked through software.

When WP# is logic high, the lock-down mechanism is disabled and

blocks previously locked-down are now locked and can be unlocked and

locked through software. After WP# goes low, any blocks previously

marked lock-down revert to that state.

See Section 3.3 for details on block locking.

V_CC

SUPPLY

DEVICE POWER SUPPLY: [2.7 V–3.6 V] Supplies power for device

operations.

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Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions (Continued)

Symbol

Type

Name and Function

I/O POWER SUPPLY: Supplies power for input/output buffers.

[2.7 V–3.6 V] This input should be tied directly to V_CC

V_CCQ

INPUT

.

[1.65 V– 2.5 V] Lower I/O power supply voltage available upon request.

Contact your Intel representative for more information.

V_PP

INPUT/

SUPPLY

PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.6 V or 11.4 V–12.6 V]

Operates as a input at logic levels to control complete device protection.

Supplies power for accelerated program and erase operations in 12 V ±

5% range. This pin cannot be left floating.

Lower V_PP≤ V_PPLK, to protect all contents against Program and

Erase commands.

Set V_PP= V_CCfor in-system read, program and erase operations. In

this configuration, V_PPcan drop as low as 1.65 V to allow for resistor or

diode drop from the system supply. Note that if V_PPis driven by a logic

signal, V_{IH =}1.65. That is, V_PPmust remain above 1.65V to perform in-

system flash modifications.

Raise V_PPto 12 V ± 5% for faster program and erase in a production

environment. Applying 12 V ± 5% to V_PPcan only be done for a

maximum of 1000 cycles on the main blocks and 2500 cycles on the

parameter blocks. V_PPmay be connected to 12 V for a total of 80 hours

maximum. See Section 3.4 for details on V_PPvoltage configurations.

GND

NC

SUPPLY

GROUND: For all internal circuitry. All ground inputs must be

connected.

NO CONNECT: Pin may be driven or left floating.

2.2.1

PARAMETER BLOCKS

2.2

Block Organization

The 3 Volt Advanced+ Boot Block flash memory

architecture includes parameter blocks to facilitate

storage of frequently updated small parameters

(i.e., data that would normally be stored in an

EEPROM). Each device contains eight parameter

blocks of 8-Kbytes/4-Kwords (8,192 bytes/4,096

words).

The 3 Volt Advanced+ Boot Block is an

asymmetrically-blocked architecture that enables

system integration of code and data within a single

flash device. Each block can be erased

independently of the others up to 100,000 times.

For the address locations of each block, see the

memory maps in Appendix E and F.

2.2.2

MAIN BLOCKS

After the parameter blocks, the remainder of the

array is divided into equal size (64-Kword/32-

Kword; 65,536 bytes/32,768 words) main blocks for

data or code storage. Each 8-Mbit, 16-Mbit, or

32-Mbit device contains 15, 31, or 63 main blocks,

respectively.

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3 VOLT ADVANCED+ BOOT BLOCK

the V_PPvoltage. The appropriate read mode

command must be issued to the CUI to enter the

corresponding mode. Upon initial device power-up

or after exit from reset, the device automatically

defaults to read array mode.

3.0 PRINCIPLES OF OPERATION

The 3 Volt Advanced+ Boot Block flash memory

family utilizes a CUI and automated algorithms to

simplify program and erase operations. The CUI

allows for 100% CMOS-level control inputs and

fixed power supplies during erasure and

programming.

CE# and OE# must be driven active to obtain data

at the outputs. CE# is the device selection control;

when active it enables the flash memory device.

OE# is the data output control and it drives the

selected memory data onto the I/O bus. For all read

modes, WE# and RP# must be at V_IH. Figure 9

illustrates a read cycle.

The internal WSM completely automates program

and erase operations while the CUI signals the start

of an operation and the status register reports

status. The CUI handles the WE# interface to the

data and address latches, as well as system status

requests during WSM operation.

3.1.2

OUTPUT DISABLE

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins are placed in a

high-impedance state.

3.1

Bus Operation

The 3 Volt Advanced+ Boot Block flash memory

devices read, program and erase in-system via the

local CPU or microcontroller. All bus cycles to or

from the flash memory conform to standard

microcontroller bus cycles. Four control pins dictate

the data flow in and out of the flash component:

CE#, OE#, WE# and RP#. These bus operations

are summarized in Table 3.

3.1.3

STANDBY

Deselecting the device by bringing CE# to a logic-

high level (V_IH) places the device in standby mode,

which substantially reduces device power

consumption without any latency for subsequent

read accesses. In standby, outputs are placed in a

high-impedance state independent of OE#. If

deselected during program or erase operation, the

device continues to consume active power until the

program or erase operation is complete.

3.1.1

READ

The flash memory has four read modes available:

read array, read configuration, read status and read

query. These modes are accessible independent of

Table 3. Bus Operations⁽¹⁾

RP# CE# OE#

V_IHV_IL

Mode

Note

WE#

DQ_0–7

DQ_8-15

Read (Array, Status,

2-4

V_IL

V_IH

D_OUT

Configuration, or Query)

Output Disable

Standby

Reset

2

V_IH

V_IL

V_IH

V_IL

V_IH

X

V_IH

X

V_IH

X

High Z

D_IN

High Z

D_IN

2,7

2,5-7

X

Write

V_IL

V_IH

V_IL

NOTES:

1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]

2. X must be V_IL, V_IHfor control pins and addresses.

3. See DC Characteristics for V_PPLK, V_PP1, V_PP2, V_PP3, voltages.

4. Manufacturer and device codes may also be accessed in read configuration mode (A –A₂₀= 0). See Table 4.

1

5. Refer to Table 5 for valid D_INduring a write operation.

6. To program or erase the lockable blocks, hold WP# at V .

IH

7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

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3.1.4 RESET

E

addressable memory location. The address and

data buses are latched on the rising edge of the

second WE# or CE# pulse, whichever occurs first.

Figure 10 illustrates a program and erase operation.

The available commands are shown in Table 6, and

From read mode, RP# at V_ILfor time t_PLPH

deselects the memory, places output drivers in a

high-impedance state, and turns off all internal

circuits. After return from reset, a time t_PHQVis

required until the initial read access outputs are

valid. A delay (t_PHWLor t_PHEL) is required after

return from reset before a write can be initiated.

After this wake-up interval, normal operation is

restored. The CUI resets to read array mode, and

the status register is set to 80H. This case is shown

in Figure 11A.

Appendix

A

provides detailed information on

moving between the different modes of operation

using CUI commands.

There are two commands that modify array data:

Program (40H) and Erase (20H). Writing either of

these commands to the internal Command User

Interface (CUI) initiates a sequence of internally-

timed functions that culminate in the completion of

the requested task (unless that operation is aborted

by either RP# being driven to V_ILfor t_PLRHor an

appropriate suspend command).

If RP# is taken low for time t_PLPHduring a program

or erase operation, the operation will be aborted

and the memory contents at the aborted location

(for a program) or block (for an erase) are no longer

valid, since the data may be partially erased or

written. The abort process goes through the

following sequence: When RP# goes low, the

device shuts down the operation in progress, a

process which takes time t_PLRHto complete. After

this time t_PLRH, the part will either reset to read

3.2

Modes of Operation

The flash memory has four read modes and two

write modes. The read modes are read array, read

configuration, read status, and read query. The

write modes are program and block erase. Three

additional modes (erase suspend to program, erase

suspend to read and program suspend to read) are

available only during suspended operations. These

modes are reached using the commands

summarized in Tables 5 and 6. A comprehensive

chart showing the state transitions is in Appendix A.

array mode (if RP# has gone high during t_PLRH

,

Figure 11B) or enter reset mode (if RP# is still logic

low after t_PLRH, Figure 11C). In both cases, after

returning from an aborted operation, the relevant

time t_PHQVor t_PHWL/t_PHELmust be waited before a

read or write operation is initiated, as discussed in

the previous paragraph. However, in this case,

these delays are referenced to the end of t_PLRH

rather than when RP# goes high.

3.2.1

READ ARRAY

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, processor expects to read from

the flash memory. Automated flash memories

provide status information when read during

program or block erase operations. If a CPU reset

occurs with no flash memory reset, proper CPU

initialization may not occur because the flash

memory may be providing status information

instead of array data. Intel’s flash memories allow

proper CPU initialization following a system reset

through the use of the RP# input. In this application,

RP# is controlled by the same RESET# signal that

resets the system CPU.

When RP# transitions from V_IL(reset) to V_IH, the

device defaults to read array mode and will respond

to the read control inputs (CE#, address inputs, and

OE#) without any additional CUI commands.

When the device is in read array mode, four control

signals control data output:

•

WE# must be logic high (V_IH)

CE# must be logic low (V_IL)

OE# must be logic low (V_IL)

RP# must be logic high (V_IH)

In addition, the address of the desired location must

be applied to the address pins. If the device is not

in read array mode, as would be the case after a

program or erase operation, the Read Array

command (FFH) must be written to the CUI before

array reads can take place.

3.1.5

WRITE

A write takes place when both CE# and WE# are

low and OE# is high. Commands are written to the

Command User Interface (CUI) using standard

microprocessor write timings to control flash

operations. The CUI does not occupy an

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3 VOLT ADVANCED+ BOOT BLOCK

3.2.2

READ CONFIGURATION

command causes subsequent reads to output data

from the status register until another command is

issued. To return to reading from the array, issue a

Read Array (FFH) command.

The Read Configuration mode outputs the

manufacturer/device identifier. The device is

switched to this mode by writing the Read

Configuration command (90H). Once in this mode,

read cycles from addresses shown in Table 4

retrieve the specified information. To return to read

array mode, write the Read Array command (FFH).

The status register bits are output on DQ₀–DQ₇.

The upper byte, DQ₈–DQ₁₅, outputs 00H during a

Read Status Register command.

The contents of the status register are latched on

the falling edge of OE# or CE#, whichever occurs

last. This prevents possible bus errors which might

occur if status register contents change while being

read. CE# or OE# must be toggled with each

subsequent status read, or the status register will

not indicate completion of a program or erase

operation.

The Read Configuration mode outputs three types

of information: the manufacturer/device identifier,

the block locking status, and the protection register.

The device is switched to this mode by writing the

Read Configuration command (90H). Once in this

mode, read cycles from addresses shown in Table

4 retrieve the specified information. To return to

read array mode, write the Read Array command

(FFH).

When the WSM is active, SR.7 will indicate the

status of the WSM; the remaining bits in the status

register indicate whether the WSM was successful

in performing the desired operation (see Table 7).

Table 4. Read Configuration Table

Item

Address

00000

Data

0089

89

Manufacturer Code (x16)

Manufacturer Code (x8)

Device ID (See Appendix G)

Block Lock Configuration²

• Block Is Unlocked

3.2.3.1

Clearing the Status Register

00000

The WSM sets status bits 1 through 7 to “1,” and

clears bits 2, 6 and 7 to “0,” but cannot clear status

bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and

5 indicate various error conditions, these bits can

only be cleared through the use of the Clear Status

Register (50H) command. By allowing the system

software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several addresses or

erasing multiple blocks in sequence) before reading

the status register to determine if an error occurred

during that series. Clear the Status Register before

beginning another command or sequence. Note

that the Read Array command must be issued

before data can be read from the memory array.

Resetting the device also clears the status register.

00001

ID

XX002⁽¹⁾LOCK

DQ₀= 0

• Block Is Locked

DQ₀= 1

• Block Is Locked-Down

Protection Register Lock³

Protection Register (x16)

DQ₁= 1

80

PR-LK

PR

81-88

Protection Register (x8)

(App. H)

PR

NOTES:

1. “XX” specifies the block address of lock configuration

being read.

2. See Section 3.3.4 for valid lock status outputs.

3. See Section 3.4 for protection register information.

3.2.4

READ QUERY

4. Other locations within the configuration address space

are reserved by Intel for future use.

The Read Query mode outputs Common Flash

Interface (CFI) data when the device is read. This

can be accessed by writing the Read Query

Command (98H). The CFI data structure contains

information such as block size, density, command

set and electrical specifications. Once in this mode,

read cycles from addresses shown in Appendix C

retrieve the specified information. To return to read

array mode, write the Read Array command (FFH).

3.2.3

READ STATUS REGISTER

The status register indicates the status of device

operations, and the success/failure of that

operation. The Read Status Register (70H)

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3.2.5 PROGRAM MODE

Programming is executed using

sequence. The Program Setup command (40H) is

written to the CUI followed by a second write which

specifies the address and data to be programmed.

The WSM will execute a sequence of internally

timed events to program desired bits of the

addressed location, then verify the bits are

sufficiently programmed. Programming the memory

results in specific bits within an address location

being changed to a “0.” If the user attempts to

program “1”s, the memory cell contents do not

change and no error occurs.

E

A Read Array command can now be written to the

CUI to read data from blocks other than that which

is suspended. The only other valid commands,

while program is suspended, are Read Status

Register, Read Configuration, Read Query, and

Program Resume. After the Program Resume

command is written to the flash memory, the WSM

will continue with the programming process and

status register bits SR.2 and SR.7 will automatically

be cleared. The device automatically outputs status

register data when read (see Figure 13 in Appendix

B, Program Suspend/Resume Flowchart) after the

Program Resume command is written. V_PPmust

remain at the same V_PPlevel used for program

while in program suspend mode. RP# must also

remain at V_IH.

a

two-write

The status register indicates programming status:

while the program sequence executes, status bit 7

is “0.” The status register can be polled by toggling

either CE# or OE#. While programming, the only

valid commands are Read Status Register,

Program Suspend, and Program Resume.

3.2.6

ERASE MODE

To erase a block, write the Erase Set-up and Erase

Confirm commands to the CUI, along with an

address identifying the block to be erased. This

address is latched internally when the Erase

Confirm command is issued. Block erasure results

in all bits within the block being set to “1.” Only one

block can be erased at a time. The WSM will

execute a sequence of internally timed events to

program all bits within the block to “0,” erase all bits

within the block to “1,” then verify that all bits within

the block are sufficiently erased. While the erase

executes, status bit 7 is a “0.”

When programming is complete, the Program

Status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status

register is set to indicate a program failure. If SR.3

is set then V_PPwas not within acceptable limits, and

the WSM did not execute the program command. If

SR.1 is set, a program operation was attempted on

a locked block and the operation was aborted.

The status register should be cleared before

attempting the next operation. Any CUI instruction

can follow after programming is completed;

however, to prevent inadvertent status register

reads, be sure to reset the CUI to read array mode.

When the status register indicates that erasure is

complete, check the erase status bit to verify that

the erase operation was successful. If the Erase

operation was unsuccessful, SR.5 of the status

register will be set to a “1,” indicating an erase

failure. If V_PPwas not within acceptable limits after

the Erase Confirm command was issued, the WSM

will not execute the erase sequence; instead, SR.5

of the status register is set to indicate an erase

error, and SR.3 is set to a “1” to identify that V_PP

supply voltage was not within acceptable limits.

3.2.5.1

Suspending and Resuming

Program

The Program Suspend command halts an in-

progress program operation so that data can be

read from other locations of memory. Once the

programming process starts, writing the Program

Suspend command to the CUI requests that the

WSM suspend the program sequence (at

predetermined points in the program algorithm).

The device continues to output status register data

after the Program Suspend command is written.

Polling status register bits SR.7 and SR.2 will

determine when the program operation has been

suspended (both will be set to “1”). t_WHRH1/t_EHRH1

specify the program suspend latency.

After an erase operation, clear the status register

(50H) before attempting the next operation. Any

CUI instruction can follow after erasure is

completed; however, to prevent inadvertent status

register reads, it is advisable to place the flash in

read array mode after the erase is complete.

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3.2.6.1

Suspending and Resuming Erase

A Read Array/Program command can now be

written to the CUI to read/program data from/to

blocks other than that which is suspended. This

nested Program command can subsequently be

suspended to read yet another location. The only

valid commands while erase is suspended are

Read Status Register, Read Configuration, Read

Query, Program Setup, Program Resume, Erase

Resume, Lock Block, Unlock Block and Lock-Down

Block. During erase suspend mode, the chip can be

placed in a pseudo-standby mode by taking CE# to

V_IH. This reduces active current consumption.

Since an erase operation requires on the order of

seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in

order to read data from or program data to another

block in memory. Once the erase sequence is

started, writing the Erase Suspend command to the

CUI suspends the erase sequence at

a

predetermined point in the erase algorithm. The

status register will indicate if/when the erase

operation has been suspended. Erase suspend

latency is specified by t_WHRH2/t_EHRH2

.

Erase Resume continues the erase sequence when

CE# = V_IL. As with the end of a standard erase

operation, the status register must be read and

cleared before the next instruction is issued.

Table 5. Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Read Array

Notes

Oper

Write

Addr

X

Data

FFH

90H

Oper

Addr

Data

4

2, 4

4

Read Configuration

Read Query

X

Read

IA

QA

X

ID

X

98H

QD

Read Status Register

Clear Status Register

Program

X

70H

SRD

4

X

50H

3,4

4

X

40H/10H

20H

Write

PA

BA

PD

Block Erase/Confirm

Program/Erase Suspend

Program/Erase Resume

Lock Block

X

D0H

4

X

B0H

D0H

60H

4

X

4

X

Write

BA

PA

01H

D0H

2FH

PD

Unlock Block

4

X

60H

Lock-Down Block

Protection Program

X = Don’t Care

4

X

60H

4

X

C0H

PA = Prog Addr BA = Block Addr IA = Identifier Addr. QA = Query Addr.

SRD = Status Reg. Data PD = Prog Data

ID = Identifier Data QD = Query Data

NOTES:

1. Bus operations are defined in Table 3.

2. Following the Read Configuration or Read Query commands, read operations output device configurationor CFI query

information, respectively. See Section 3.2.2 and 3.2.4.

3. Either 40H or 10H command is valid, but the Intel standard is 40H.

4. When writing commands, the upper data bus [DQ₈–DQ₁₅] should be either V_ILor V_IH, to minimize current draw.

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E

Table 6. Command Codes and Descriptions

Description

Code Device Mode

FF

Read Array

Places device in read array mode, such that array data will be output on the

data pins.

40

Program

Set-Up

This is a two-cycle command. The first cycle prepares the CUI for a program

operation. The second cycle latches addresses and data information and

initiates the WSM to execute the Program algorithm. The flash outputs status

register data when CE# or OE# is toggled. A Read Array command is required

after programming to read array data. See Section 3.2.5.

20

Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not

an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the

status register to a “1,” (b) place the device into the read status register mode,

and (c) wait for another command. See Section 3.2.6.

D0

Erase Confirm If the previous command was an Erase Set-Up command, then the CUI will

close the address and data latches, and begin erasing the block indicated on the

address pins. During program/erase, the device will respond only to the Read

Status Register, Program Suspend and Erase Suspend commands and will

output status register data when CE# or OE# is toggled.

Program/Erase If a program or erase operation was previously suspended, this command will

Resume

resume that operation.

If the previous command was Configuration Set-Up, the CUI will latch the

address and unlock the block indicated on the address pins. If the block had

been previously set to Lock-Down, this operation will have no effect. (Sect. 3.3)

Unlock Block

B0

Program

Suspend

Issuing this command will begin to suspend the currently executing

program/erase operation. The status register will indicate when the operation

has been successfully suspended by setting either the program suspend (SR.2)

or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The

WSM will continue to idle in the SUSPEND state, regardless of the state of all

input control pins except RP#, which will immediately shut down the WSM and

the remainder of the chip if RP# is driven to V_IL. See Sections 3.2.5.1 and

3.2.6.1.

Erase

Suspend

70

50

Read Status

Register

This command places the device into read status register mode. Reading the

device will output the contents of the status register, regardless of the address

presented to the device. The device automatically enters this mode after a

program or erase operation has been initiated. See Section 3.2.3.

Clear Status

Register

The WSM can set the Block Lock Status (SR.1) , V_PPStatus (SR.3), Program

Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it

cannot clear them to “0.” Issuing this command clears those bits to “0.”

90

60

Read

Configuration

Puts the device into the Read Configuration mode, so that reading the device

will output the manufacturer/device codes or block lock status. Section 3.2.2.

Configuration

Set-Up

Prepares the CUI for changes to the device configuration, such as block locking

changes. If the next command is not Block Unlock, Block Lock, or Block Lock-

Down, then the CUI will set both the Program and Erase Status register bits to

indicate a command sequence error. See Section 3.3.

01

Lock-Block

If the previous command was Configuration Set-Up, the CUI will latch the

address and lock the block indicated on the address pins. (Section 3.3)

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Table 6. Command Codes and Descriptions (Continued)

Code Device Mode

Description

2F

Lock-Down

If the previous command was a Configuration Set-Up command, the CUI will

latch the address and lock-down the block indicated on the address pins.

(Section 3.3)

98

Read

Query

Puts the device into the Read Query mode, so that reading the device will

output Common Flash Interface information. See Section 3.2.4 and Appendix C.

C0

Protection

Program

Setup

This is a two-cycle command. The first cycle prepares the CUI for an program

operation to the Protection Register. The second cycle latches addresses and

data information and initiates the WSM to execute the Protection Program

algorithm to the Protection Register. The flash outputs status register data when

CE# or OE# is toggled. A Read Array command is required after programming

to read array data. See Section 3.4.

10

00

Alt. Prog Set-Up Operates the same as Program Set-up command. (See 40H/Program Set-Up)

Invalid/

Unassigned commands that should not be used. Intel reserves the right to

redefine these codes for future functions.

Reserved

NOTE:

See Appendix A for mode transition information.

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Table 7. Status Register Bit Definition

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

PSS

2

BLS

1

R

0

NOTES:

SR.7 WRITE STATE MACHINE STATUS

Check Write State Machine bit first to determine Word

Program or Block Erase completion, before checking

Program or Erase Status bits.

1 = Ready

0 = Busy

(WSMS)

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts execution

and sets both WSMS and ESS bits to “1.” ESS bit

remains set to “1” until an Erase Resume command is

issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erase

0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the max.

number of erase pulses to the block and is still unable to

verify successful block erasure.

SR.4 = PROGRAM STATUS (PS)

1 = Error in Programming

When this bit is set to “1,” WSM has attempted but failed

to program a word/byte.

0 = Successful Programming

SR.3 = V_PPSTATUS (VPPS)

1 = V_PPLow Detect, Operation Abort

0 = V_PPOK

The V_PPstatus bit does not provide continuous indication

of V_PPlevel. The WSM interrogates V_PPlevel only after

the Program or Erase command sequences have been

entered, and informs the system if V_PPhas not been

switched on. The V_PPis also checked before the

operation is verified by the WSM. The V_PPstatus bit is

not guaranteed to report accurate feedback between

V

_PPLKand V_PP1Min.

SR.2 = PROGRAM SUSPEND STATUS

(PSS)

1 = Program Suspended

0 = Program in Progress/Completed

When Program Suspend is issued, WSM halts execution

and sets both WSMS and PSS bits to “1.” PSS bit

remains set to “1” until a Program Resume command is

issued.

SR.1 = BLOCK LOCK STATUS

1 = Prog/Erase attempted on a locked

block; Operation aborted.

If a program or erase operation is attempted to one of the

locked blocks, this bit is set by the WSM. The operation

specified is aborted and the device is returned to read

status mode.

0 = No operation to locked blocks

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

This bit is reserved for future use and should be masked

out when polling the status register.

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LOCKED STATE

3.3.2

3.3

Flexible Block Locking

The Intel^®3 Volt Advanced+ Boot Block products

offer an instant, individual block locking scheme

that allows any block to be locked or unlocked with

no latency, enabling instant code and data

protection.

The default status of all blocks upon power-up or

reset is locked (states [001] or [101]). Locked

blocks are fully protected from alteration. Any

program or erase operations attempted on a locked

block will return an error on bit SR.1 of the status

register. The status of a locked block can be

changed to Unlocked or Lock-Down using the

appropriate software commands. An Unlocked

block can be locked by writing the Lock command

sequence, 60H followed by 01H.

This locking scheme offers two levels of protection.

The first level allows software-only control of block

locking (useful for data blocks that change

frequently), while the second level requires

hardware interaction before locking can be changed

(useful for code blocks that change infrequently).

3.3.3

UNLOCKED STATE

The following sections will discuss the operation of

the locking system. The term “state [XYZ]” will be

used to specify locking states; e.g., “state [001],”

where X = value of WP#, Y = bit DQ₁of the Block

Lock status register, and Z = bit DQ₀of the Block

Lock status register. Table 9 defines all of these

possible locking states.

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return

to the Locked state when the device is reset or

powered down. The status of an unlocked block can

be changed to Locked or Locked-Down using the

appropriate software commands. A Locked block

can be unlocked by writing the Unlock command

sequence, 60H followed by D0H.

3.3.1

LOCKING OPERATION

3.3.4

LOCK-DOWN STATE

The following concisely summarizes the locking

functionality.

Blocks that are Locked-Down (state [011]) are

protected from program and erase operations (just

like Locked blocks), but their protection status

cannot be changed using software commands

alone. A Locked or Unlocked block can be Locked-

down by writing the Lock-Down command

sequence, 60H followed by 2FH. Locked-Down

blocks revert to the Locked state when the device is

reset or powered down.

•

All blocks power-up locked, then can be

unlocked or locked with the Unlock and Lock

commands.

•

The Lock-Down command locks a block and

prevents it from being unlocked when WP# = 0.

When WP# = 1, Lock-Down is overridden

and commands can unlock/lock locked-

down blocks.

The Lock-Down function is dependent on the WP#

input pin. When WP# = 0, blocks in Lock-Down

[011] are protected from program, erase, and lock

status changes. When WP# = 1, the Lock-Down

function is disabled ([111]) and locked-down blocks

can be individually unlocked by software command

to the [110] state, where they can be erased and

programmed. These blocks can then be relocked

[111] and unlocked [110] as desired while WP#

remains high. When WP# goes low, blocks that

were previously locked-down return to the

Lock-Down state [011] regardless of any changes

made while WP# was high. Device reset or power-

down resets all blocks, including those in Lock-

Down, to Locked state.

When WP# returns to 0, locked-down

blocks return to Lock-Down.

Lock-Down is cleared only when the device

is reset or powered-down.

The locking status of each block can set to Locked,

Unlocked, and Lock-Down, each of which will be

described

comprehensive state table for the locking functions

is shown in Table 9, and a flowchart for locking

operations is shown in Figure 16.

in

the

following

sections.

A

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3.3.5 READING A BLOCK’S LOCK STATUS

E

the lock status will be changed. After completing

any desired lock, read, or program operations,

resume the erase operation with the Erase Resume

command (D0H).

The lock status of every block can be read in the

Configuration Read mode of the device. To enter

this mode, write 90H to the device. Subsequent

reads at Block Address + 00002 will output the lock

status of that block. The lock status is represented

by the lowest two output pins, DQ₀and DQ₁. DQ₀

indicates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. It is also automatically set when entering

Lock-Down. DQ₁indicates Lock-Down status and is

set by the Lock-Down command. It cannot be

cleared by software, only by device reset or power-

down.

If a block is locked or locked-down during a

suspended erase of the same block, the locking

status bits will be changed immediately, but when

the erase is resumed, the erase operation will

complete.

Locking operations cannot be performed during a

program suspend. Refer to Appendix A for detailed

information on which commands are valid during

erase suspend.

Table 8. Block Lock Status

3.3.7

STATUS REGISTER ERROR

CHECKING

Item

Address

Data

Block Lock Configuration

• Block Is Unlocked

• Block Is Locked

XX002

LOCK

Using nested locking or program command

sequences during erase suspend can introduce

ambiguity into status register results.

DQ₀= 0

DQ₀= 1

DQ₁= 1

Since locking changes are performed using a two

cycle command sequence, e.g., 60H followed by

01H to lock a block, following the Configuration

Setup command (60H) with an invalid command will

produce a lock command error (SR.4 and SR.5 will

be set to 1) in the status register. If a lock

command error occurs during an erase suspend,

SR.4 and SR.5 will be set to 1, and will remain at 1

after the erase is resumed. When erase is

complete, any possible error during the erase

cannot be detected via the status register because

of the previous locking command error.

• Block Is Locked-Down

3.3.6

LOCKING OPERATIONS DURING

ERASE SUSPEND

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock, or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

A similar situation happens if an error occurs during

a program operation error nested within an erase

suspend.

To change block locking during an erase operation,

first write the erase suspend command (B0H), then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired lock command sequence to a block and

20

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

Table 9. Block Locking State Transitions

Erase/Prog Lock Command Input Result [Next State]

Current State

DQ₀

WP# DQ₁

Name

Allowed?

Yes

No

Lock

Unlock

Lock-Down

0

1

0

1

0

1

0

1

0

1

0

1

“Unlocked”

“Locked” (Default)

“Locked-Down”

“Unlocked”

Goes To [001] No Change Goes To [011]

No Change Goes To [000] Goes To [011]

No

No Change

Yes

No

Goes To [101] No Change Goes To [111]

No Change Goes To [100] Goes To [111]

Goes To [111] No Change Goes To [111]

No Change Goes To [110] No Change

“Locked”

Lock-Down Disabled

Yes

No

1

NOTES:

1. In this table, the notation [XYZ] denotes the locking state of a block, where X= WP#, Y = DQ₁, and Z = DQ₀. The current

locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ , DQ₁). DQ₀indicates if

0

a block is locked (1) or unlocked (0). DQ₁indicates if a block has been locked-down (1) or not (0).

2. At power-up or device reset, all blocks default to Locked state [001] (if WP#= 0). Holding WP# = 0 is the recommended

default.

3. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No)

in that block’s current locking state.

4. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,

Unlock, Lock-Down) in the current locking state. For example,“Goes To [001]” would mean that writing the command to a

block in the current locking state would change it to [001].

3.4.1

READING THE PROTECTION

REGISTER

3.4

128-Bit Protection Register

The Advanced+ Boot Block architecture includes a

128-bit protection register than can be used to

increase the security of a system design. For

example, the number contained in the protection

register can be used to “mate” the flash component

with other system components such as the CPU or

ASIC, preventing device substitution. Additional

application information can be found in Intel

application note AP-657 Designing with the

Advanced+ Boot Block Flash Memory Architecture.

The protection register is read in the configuration

read mode. The device is switched to this mode by

writing the Read Configuration command (90H).

Once in this mode, read cycles from addresses

shown in Appendix

H retrieve the specified

information. To return to read array mode, write the

Read Array command (FFH).

3.4.2

PROGRAMMING THE PROTECTION

REGISTER

The 128-bits of the protection register are divided

into two 64-bit segments. One of the segments is

programmed at the Intel factory with a unique 64-bit

number, which is unchangeable. The other segment

is left blank for customer designs to program as

desired. Once the customer segment is

programmed, it can be locked to prevent

reprogramming.

The protection register bits are programmed using

the two-cycle Protection Program command. The

64-bit number is programmed 16 bits at a time for

word-wide parts and eight bits at a time for byte-

wide parts. First write the Protection Program Setup

command, C0H. The next write to the device will

latch in address and data and program the specified

location. The allowable addresses are shown in

Appendix H. See Figure 17 for the Protection

Register Programming Flowchart.

21

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

3.5.1

EASY-12 V OPERATION FOR FAST

MANUFACTURING PROGRAMMING

Any attempt to address Protection Program

commands outside the defined protection register

address space will result in a Status Register error

(Program Error bit SR.4 will be set to 1). Attempting

to program or to a previously locked protection

register segment will result in a status register error

(program error bit SR.4 and lock error bit SR.1 will

be set to 1).

Intel’s 3 Volt Advanced+ Boot Block products

provide in-system programming and erase in the

2.7 V–3.6 V

programming, 3 Volt Advanced+ Boot Block

includes low-cost, backward-compatible 12 V

programming feature.

range.

For

fast

production

a

3.4.3

LOCKING THE PROTECTION

REGISTER

When V_PPis between 1.65 V and 3.6 V, all program

and erase current is drawn through the V_CCpin.

Note that if V_PPis driven by

a logic signal,

The user-programmable segment of the protection

register is lockable by programming Bit 1 of the

PR-LOCK location to 0. Bit 0 of this location is

programmed to 0 at the Intel factory to protect the

unique device number. This bit is set using the

Protection Program command to program “FFFD” to

the PR-LOCK location. After these bits have been

programmed, no further changes can be made to

the values stored in the protection register.

Protection Program commands to a locked section

will result in a status register error (Program Error

bit SR.4 and Lock Error bit SR.1 will be set to 1).

Protection register lockout state is not reversible.

V_{IH =}1.65 V. That is, V_PPmust remain above 1.65 V

to perform in-system flash modifications. When V_PP

is connected to a 12 V power supply, the device

draws program and erase current directly from the

V_PPpin. This eliminates the need for an external

switching transistor to control the voltage V_PP

.

Figure 6 shows examples of how the flash power

supplies can be configured for various usage

models.

The 12 V V_PPmode enhances programming

performance during the short period of time typically

found in manufacturing processes; however, it is

not intended for extended use. 12 V may be applied

to V_PPduring program and erase operations for a

maximum of 1000 cycles on the main blocks and

2500 cycles on the parameter blocks. V_PPmay be

connected to 12 V for a total of 80 hours maximum.

Stressing the device beyond these limits may cause

permanent damage.

88H

4 Words

User Programmed

85H

84H

3.5.2

V

_PP≤ V_PPLKFOR COMPLETE

4 Words

Factory Programmed

PROTECTION

81H

In addition to the flexible block locking, the V_PP

programming voltage can be held low for absolute

hardware write protection of all blocks in the flash

device. When V_PPis below V_PPLK, any program or

erase operation will result in a error, prompting the

corresponding status register bit (SR.3) to be set.

1 Word Lock

80H

0645_05

Figure 5. Protection Register Memory Map

3.5.3

V_PPUSAGE

The V_PPpin is used for two functions: Absolute data

protection and fast production programming.

3.5

V

Program and Erase

PP

Voltages

When V_PP≤ V_PPLK, then all program or erase

operations to the device are inhibited, providing

absolute data protection.

Intel’s 3 Volt Advanced+ Boot Block products

provide in-system writes plus a V_PPpin for 12 V

production programming and complete write

protection.

22

PRODUCT PREVIEW

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3 VOLT ADVANCED+ BOOT BLOCK

System Supply

12 V Supply

V_CC

V_PP

V_CC

V_PP

Prot#

(Logic Signal)

10 K

Ω

12 V Fast Programming

Low-Voltage Programming Only

Complete Write Protection When V _PP

≠

12 V

Logic Control of Complete Device Protection

System Supply

V_CC

V_PP

(Note 1)

12 V Supply

V_PP

12 V Fast Programming

Low-Voltage Programming Only

Full Array Protection Unavailable

0645_06

NOTE:

1. A resistor can be used if the V supply can sink adequate current based on resistor value. See AP-657Designing with

CC

the Advanced+ Boot Block Flash Memory Architecture for details.

Figure 6. Example Power Supply Configurations

3.6.1

ACTIVE POWER

When V_PPis raised to 12 V, such as in

a

(Program/Erase/Read)

manufacturing situations, the device directly applies

the high voltage to achieve faster program and

erase.

With CE# at a logic-low level and RP# at a logic-

high level, the device is in the active mode. Refer to

the DC Characteristic tables for I_CCcurrent values.

Active power is the largest contributor to overall

system power consumption. Minimizing the active

current could have a profound effect on system

power consumption, especially for battery-operated

devices.

Designing for in-system writes to the flash memory

requires special consideration of power supply

traces by the printed circuit board designer.

Adequate power supply traces, and decoupling

capacitors placed adjacent to the component, will

decrease spikes and overshoots.

3.6.2

AUTOMATIC POWER SAVINGS (APS)

3.6

Power Consumption

Automatic Power Savings provides low-power

operation during read mode. After data is read from

the memory array and the address lines are

quiescent, APS circuitry places the device in a

Intel’s flash devices have a tiered approach to

power savings that can significantly reduce overall

system power consumption. The Automatic Power

Savings (APS) feature reduces power consumption

when the device is selected but idle. If the CE# is

deasserted, the flash enters its standby mode,

where current consumption is even lower. The

combination of these features can minimize

memory power consumption, and therefore, overall

system power consumption.

mode where typical current is comparable to I_CCS

.

The flash stays in this static state with outputs valid

until a new location is read.

3.6.3

STANDBY POWER

With CE# at a logic-high level (V_IH) and device in

read mode, the flash memory is in standby mode,

which disables much of the device’s circuitry and

23

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

substantially reduces power consumption. Outputs

are placed in a high-impedance state independent

of the status of the OE# signal. If CE# transitions to

proper CPU/flash initialization following system

reset.

a

logic-high level during erase or program

System designers must guard against spurious

writes when V_CCvoltages are above V_LKO. Since

both WE# and CE# must be low for a command

write, driving either signal to V_IHwill inhibit writes to

the device. The CUI architecture provides additional

protection since alteration of memory contents can

only occur after successful completion of the two-

step command sequences. The device is also

disabled until RP# is brought to V_IH, regardless of

the state of its control inputs. By holding the device

in reset (RP# connected to system PowerGood)

during power-up/down, invalid bus conditions during

power-up can be masked, providing yet another

level of memory protection.

operations, the device will continue to perform the

operation and consume corresponding active power

until the operation is completed.

System engineers should analyze the breakdown of

standby time versus active time and quantify the

respective power consumption in each mode for

their specific application. This will provide a more

accurate measure of application-specific power and

energy requirements.

3.6.4

DEEP POWER-DOWN MODE

The deep power-down mode is activated when

RP# = V_IL(GND ± 0.2 V). During read modes, RP#

going low de-selects the memory and places the

outputs in a high impedance state. Recovery from

deep power-down requires a minimum time of t_PHQV

for read operations and t_PHWL/t_PHELfor write

operations.

3.7.2

V_CC, V_PPAND RP# TRANSITIONS

The CUI latches commands as issued by system

software and is not altered by V_PPor CE#

transitions or WSM actions. Its default state upon

power-up, after exit from reset mode or after V_CC

transitions above V_LKO(Lockout voltage), is read

array mode.

During program or erase modes, RP# transitioning

low will abort the in-progress operation. The

memory contents of the address being programmed

or the block being erased are no longer valid as the

data integrity has been compromised by the abort.

During deep power-down, all internal circuits are

switched to a low power savings mode (RP#

transitioning to V_ILor turning off power to the device

clears the status register).

After any program or block erase operation is

complete (even after V_PPtransitions down to

V

_PPLK), the CUI must be reset to read array mode

via the Read Array command if access to the flash

memory array is desired.

3.8

Power Supply Decoupling

3.7

Power-Up/Down Operation

Flash memory’s power switching characteristics

require careful device decoupling. System

designers should consider three supply current

issues:

The device is protected against accidental block

erasure or programming during power transitions.

Power supply sequencing is not required, since the

device is indifferent as to which power supply, V_PP

or V_CC, powers-up first.

1. Standby current levels (I_CCS

)

2. Read current levels (I_CCR

)

3. Transient peaks produced by falling and rising

edges of CE#.

3.7.1

RP# CONNECTED TO SYSTEM

RESET

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress these transient voltage peaks. Each

The use of RP# during system reset is important

with automated program/erase devices since the

system expects to read from the flash memory

when it comes out of reset. If a CPU reset occurs

flash device should have

a 0.1 µF ceramic

capacitor connected between each V_CCand GND,

and between its V_PPand GND. These high-

frequency, inherently low-inductance capacitors

should be placed as close as possible to the

package leads.

without

a

flash memory reset, proper CPU

initialization will not occur because the flash

memory may be providing status information

instead of array data. Intel recommends connecting

RP# to the system CPU RESET# signal to allow

24

PRODUCT PREVIEW

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3 VOLT ADVANCED+ BOOT BLOCK

4.0 ABSOLUTE MAXIMUM

RATINGS*

NOTICE: This datasheet contains preliminary information on

products in the design phase of development. The

specifications are subject to change without notice. Verify

with your local Intel Sales office that you have the latest

datasheet before finalizing a design.

Extended Operating Temperature

During Read .......................... –40 °C to +85 °C

* WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent damage. These

are stress ratings only. Operation beyond the "Operating

Conditions" is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

During Block Erase

and Program.......................... –40 °C to +85 °C

Temperature Under Bias ....... –40 °C to +85 °C

Storage Temperature................. –65 °C to +125 °C

Voltage on Any Pin

(except V_CCand V_PP

)

NOTES:

with Respect to GND............. –0.5 V to +5.0 V¹

1. Minimum DC voltage is –0.5 V on input/output pins.

During transitions, this level may undershoot to–2.0 V

for periods < 20 ns. Maximum DC voltage on

input/output pins is V_CC+ 0.5 V which, during

transitions, may overshoot to V_CC+ 2.0 V for periods

< 20 ns.

V_PPVoltage (for Block

Erase and Program)

with Respect to GND.......–0.5 V to +13.5 V^1,2,4

V_CCand V_CCQSupply Voltage

with Respect to GND............. –0.2 V to +5.0 V¹

2. Maximum DC voltage on V_PPmay overshoot to +14.0 V

for periods < 20 ns.

Output Short Circuit Current...................... 100 mA³

3. Output shorted for no more than one second.No more

than one output shorted at a time.

4. V_PPvoltage is normally 1.65 V–3.6 V. Connection to

supply of 11.4 V–12.6 V can only be done for 1000

cycles on the main blocks and 2500 cycles on the

parameter blocks during program/erase. V_PPmay be

connected to 12 V for a total of 80 hours maximum.

See Section 3.5 for details.

4.2

Operating Conditions

Table 10. Temperature and Voltage Operating Conditions

Symbol

Parameter

Operating Temperature

V_CCSupply Voltage

Notes

Min

–40

Max

+85

3.6

Units

°C

T_A

V_CC1

V_CC2

V_CCQ1

V_PP1

V_PP2

1

2.7

Volts

3.0

3.6

I/O Supply Voltage

Supply Voltage

1

2.7

3.6

Volts

1

1.65

11.4

100,000

3.6

1, 2

2

12.6

Volts

Cycling

Block Erase Cycling

Cycles

NOTES:

1. V_CCand V_CCQmust share the same supply when they are in the V_CC1range.

2. Applying V_{PP =}11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum. See Section

PP

^{3.5 for details}.

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PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

4.3 Capacitance

E

T_{A =}25 °C, f ₌1 MHz

Sym

Parameter

Input Capacitance

Notes

Typ

6

Max

8

Units

pF

Conditions

C_IN

1

V_IN= 0 V

V_OUT= 0 V

C_OUTOutput Capacitance

10

12

pF

NOTE:

1. Sampled, not 100% tested.

4.4

DC Characteristics

V_CC

2.7 V–3.6 V

V_CCQ

Note

1,7

2.7 V–3.6 V

Sym

Parameter

Typ

Max

Unit

Test Conditions

V_CC= V_CCMax

I_LI

Input Load Current

± 1

µA

V_CCQ= V_CCQMax

V

_IN= V_CCQor GND

V_CC= V_CCMax

I_LO

Output Leakage Current

V_CCStandby Current

1,7

0.2

± 10

µA

V

_CCQ= V_CCQMax

_IN= V_CCQor GND

I_CCS

1

10

7

25

20

µA

V_CC= V_CCMax

CE# = RP# = V_CC

V_CC= V_CCMax

I_CCD

V_CCDeep Power-Down

Current

1,7

V

_CCQ= V_CCQMax

_IN= V_CCQor GND

RP# = GND ± 0.2 V

V_CC= V_CCMax

I_CCR

V_CCRead Current

1,5,7

9

18

mA

V

_CCQ= V_CCQMax

OE# = V_IH, CE# = V_IL

f = 5 MHz, I_OUT= 0 mA

Inputs = V_ILor V_IH

V_PP= V_PP1

Program in Progress

I_CCWV_CCProgram Current

1,4

18

8

55

15

45

15

25

mA

µA

V_PP= V_PP2(12 V)

Program in Progress

V_PP= V_PP1

V_CCErase Current

16

8

I_CCE

Erase in Progress

V_PP= V_PP2(12 V)

Erase in Progress

I_CCESV_CCErase Suspend

Current

1,2,4

10

CE# = V_IH, Erase Suspend in

Progress

I_CCWSV_CCProgram Suspend

Current

10

25

µA

CE# = V_IH, Program

Suspend in Progress

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PRODUCT PREVIEW

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3 VOLT ADVANCED+ BOOT BLOCK

4.4

DC Characteristics, Continued

V_CC

V_CCQ

Note

1

2.7 V–3.6 V

Sym

Parameter

Typ

0.2

Max

Unit

Test Conditions

I_PPD

V_PPDeep Power-Down

Current

5

µA

RP# = GND ± 0.2 V

I_PPS

I_PPR

V_PPStandby Current

V_PPRead Current

1

0.2

2

5

µA

mA

V

_PP≤ V_CC

_PP≥ V_CC

1

±15

200

0.1

1,4

50

V_PP=V_PP1

Program in Progress

I_PPW

V_PPProgram Current

V_PPErase Current

0.05

V_PP= V_PP2(12 V)

Program in Progress

8

0.05

8

22

0.1

22

5

mA

µA

V_PP= V_PP1

Program in Progress

I_PPE

1,4

V_PP= V_PP2(12 V)

Program in Progress

V_PP= V_PP1

Erase Suspend in Progress

I_PPESV_PPErase Suspend Current

I_PPWSV_PPProgram Suspend Current

0.2

50

V_PP= V_PP2(12 V)

Erase Suspend in Progress

200

5

µA

V_PP= V_PP1

Program Suspend in

Progress

0.2

µA

V_PP= V_PP2(12 V)

Program Suspend in

Progress

50

200

µA

27

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

4.4

DC Characteristics, Continued

V_CC

2.7 V–3.6 V

V_CCQ

2.7 V–3.6 V

Sym

Parameter

Input Low Voltage

Note

Min

-0.4

V_CCQ

Max

0.4

Unit

V

Test Conditions

V_IL

V_IH

-

Input High Voltage

Output Low Voltage

V

0.4 V

V_OL

7

-0.10

0.10

V

V_CC= V_CCMin

_CCQ= V_CCQMin

_OL= 100 µA

V_CC= V_CCMin

_CCQ= V_CCQMin

_OH= –100 µA

V

I

V_OH

Output High Voltage

V_CCQ

0.1 V

-

V

I

V_PPLKV_PPLock-Out Voltage

3

1.0

3.6

V

Complete Write Protection

V_PP1

V_PP2

V_LKO

V_LKO2

V_PPduring Program / Erase

Operations

1.65

11.4

1.5

3,6

12.6

V_CCProg/Erase Lock Voltage

V

V_CCQProg/Erase Lock

Voltage

1.2

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V_CC, T_A= +25 °C.

2. I_CCESand I_CCWSare specified with device de-selected. If device is read while in erase suspend, current draw is sum of

I_CCESand I_CCR. If the device is read while in program suspend, current draw is the sum of I_CCWSand I_CCR

.

3. Erase and Program are inhibited when V_PP< V_PPLKand not guaranteed outside the valid V_PPranges of V_PP1and V_PP2

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto approximately standby levels in static operation (CMOS inputs).

6. Applying V_PP= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum. See Section

PP

3.4 for details.

7. The test conditions V_CCMax, V_CCQMax, V_CCMin, and V_CCQMin refer to the maximum or minimum V_CCor V_CCQvoltage

listed at the top of each column.

28

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3 VOLT ADVANCED+ BOOT BLOCK

V_CCQ

2

V_CCQ

OUTPUT

2

TEST POINTS

INPUT

0.0

0645_07

Figure 7. Input Range and Measurement Points

Test Configuration Component Values Table

Test Configuration

C_L(pF) R₁(Ω) R₂(Ω)

50 25K 25K

V_CCQ

2.7 V–3.6 V Standard

Test

R₁

R₂

NOTE:

Device

Under Test

C_Lincludes jig capacitance.

Out

C_L

0645_08

Figure 8. Test Configuration

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PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

(1)

4.5

AC Characteristics—Read Operations —Extended Temperature

Product

–90

–110

V_CC

3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V

#

Sym

Parameter

Read Cycle Time

Note

Min Max Min Max Min Max Min Max Unit

R1

R2

t_AVAV

80

90

100

110

ns

t_AVQVAddress to

Output Delay

80

90

100

30

110

30

R3

R4

R5

R6

R7

R8

R9

t_ELQV

CE# to Output

Delay

2

ns

t_GLQVOE# to Output

Delay

30

t_PHQVRP# to Output

Delay

150

t_ELQX

CE# to Output in

Low Z

3

0

t_GLQXOE# to Output in

Low Z

t_EHQZCE# to Output in

High Z

20

t_GHQZOE# to Output in

High Z

R10 t_OH

Output Hold from

Address, CE#, or

OE# Change,

Whichever

0

Occurs First

NOTES:

1. See AC Waveform: Read Operations.

2. OE# may be delayed up to t_ELQV–t_GLQVafter the falling edge of CE# without impact on t_ELQV

.

3. Sampled, but not 100% tested.

4. See Test Configuration (Figure 8).

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PRODUCT PREVIEW

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3 VOLT ADVANCED+ BOOT BLOCK

Device and

Address Selection

Data

Valid

Standby

V_IH

ADDRESSES (A)

V_IL

Address Stable

R1

V_IH

CE# (E)

V_IL

R8

R9

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

R4

R3

Valid Output

R7

R10

V_IL

V_OH

DATA (D/Q)

V_OL

R6

High Z

R2

V_IH

RP#(P)

R5

V_IL

Figure 9. AC Waveform: Read Operations

31

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

(1)

4.6 AC Characteristics—Write Operations —Extended Temperature

Product

-90

-110

3.0 V – 3.6 V

2.7 V – 3.6 V

Note

80

100

90

110

Min

150

#

Symbol

Parameter

Min

150

Min

Unit

t_PHWL

t_PHEL

t_ELWL

t_WLEL

t_ELEH

/

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

RP# High Recovery to WE#

(CE#) Going Low

150

ns

/

CE# (WE#) Setup to WE#

(CE#) Going Low

0

50

0

60

50

60

0

70

60

70

0

70

60

70

0

ns

/

WE# (CE#) Pulse Width

4

2

t_WLWH

t_DVWH

t_DVEH

t_AVWH

t_AVEH

t_WHEH

t_EHWH

t_WHDX

t_EHDX

t_WHAX

t_EHAX

/

Data Setup to WE# (CE#)

Going High

/

Address Setup to WE# (CE#)

Going High

CE# (WE#) Hold Time from

WE# (CE#) High

Data Hold Time from WE#

(CE#) High

2

4

3

0

Address Hold Time from WE#

(CE#) High

0

t_{WHWL /}

t_EHEL

t_VPWH

t_VPEH

WE# (CE#) Pulse Width High

30

200

0

30

200

0

30

200

0

30

200

0

/

V_PPSetup to WE# (CE#) Going

High

W11

t_QVVL

V_PPHold from Valid SRD

NOTES:

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. Refer to Table 5 for valid A_INor D_IN

.

3. Sampled, but not 100% tested.

4. Write pulse width (t_WP) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going high

(whichever goes high first). Hence, t_WP= t_WLWH= t_ELEH= t_WLEH= t_ELWH. Similarly, Write pulse width high (t_WPH) is defined

from CE# or WE# going high (whichever goes high first)to CE# or WE# going low (whichever goes low first). Hence,

t_WPH= t_WHWL= t_EHEL= t_WHEL= t_EHWL

.

5. See Test Configuration (Figure 8).

32

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

(1)

4.7

Erase and Program Timings

V_PP

Note

2, 3

1.65 V–3.6 V

11.4 V–12.6 V

Symbol

t_BWPB

Parameter

Typ⁽¹⁾

Max

Typ⁽¹⁾

Max

Unit

8-KB Parameter Block

Program Time (Byte)

0.16

0.48

0.08

0.24

s

4-KW Parameter Block

Program Time (Word)

2, 3

0.10

1.2

0.30

3.7

0.03

0.6

0.12

1.7

1

s

t_BWMB

64-KB Main Block

Program Time (Byte)

32-KW Main Block

0.8

2.4

0.24

Program Time(Word)

t_WHQV1/ t_EHQV1

Byte Program Time

2, 3

17

22

1

165

200

5

8

185

4.8

µs

s

Word Program Time

t_WHQV2/ t_EHQV2

8-KB Parameter Block

Erase Time (Byte)

0.8

4-KW Parameter Block

Erase Time (Word)

2, 3

0.5

1

5

8

0.4

1

4.8

7

s

t_WHQV3/ t_EHQV3

64-KB Main Block

Erase Time (Byte)

32-KW Main Block

Erase Time (Word)

1

0.6

7

t_WHRH1/ t_EHRH1

t_WHRH2/ t_EHRH2

Program Suspend Latency

Erase Suspend Latency

3

5

10

20

5

10

20

µs

NOTES:

1. Typical values measured at T_A= +25 °C and nominal voltages.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

33

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

A

B

C

D

E

F

V_IH

ADDRESSES [A]

CE#(WE#) [E(W)]

A_IN

V_IL

V_IH

W8

(Note 1)

W5

V_IL

V_IH

W6

W2

OE# [G]

V_IL

V_IH

W9

(Note 1)

WE#(CE#) [W(E)]

V_IL

W3

W4

W7

V_IH

V_IL

High Z

W1

Valid

SRD

DATA [D/Q]

D_IN

V_IH

V_IL

V_IH

RP# [P]

WP#

V_IL

W10

W11

V_PPH

2

V_PPH

V_PPLK

V_IL

1

V

[V]

PP

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register

Data.

A.

V

Power-Up and Standby.

CC

B. Write Program or Erase Setup Command.

C. Write Valid Address and Data (for Program) or Erase Confirm Command.

D. Automated Program or Erase Delay.

E. Read Status Register Data (SRD): reflects completed program/erase operation.

F. Write Read Array Command.

Figure 10. AC Waveform: Program and Erase Operations

34

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

4.8

Reset Operations

V

IH

RP# (P)

t_PHQV

t_PHWL

t_PHEL

V_IL

t _PLPH

(A) Reset during Read Mode

Abort

Complete

t _PLRH

t_PHQV

t_PHWL

t_PHEL

V_IH

V_IL

RP# (P)

t _PLPH

t_PLPH

t _PLRH

<

(B) Reset during Program or Block Erase,

Abort Deep

Complete Power-

t_PHQV

t_PHWL

t_PHEL

Down

t _PLRH

V_IH

V_IL

RP# (P)

t _PLPH

(C) Reset Program or Block Erase,

>

t _PLPHt _PLRH

Figure 11. AC Waveform: Reset Operation

Table 11. Reset Specifications⁽¹⁾

V_CC2.7V–3.6V

Symbol

Parameter

Notes

Min

100

Max

Unit

t_PLPH

RP# Low to Reset during Read

(If RP# is tied to V_CC, this specification is not

applicable)

2,4

ns

t_PLRH1

RP# Low to Reset during Block Erase

3,4

22

µs

t_PLRH2

RP# Low to Reset during Program

3,4

12

NOTES:

1. See Section 3.1.4 for a full description of these conditions.

2. If t_PLPHis < 100 ns the device may still reset but this is not guaranteed.

3. If RP# is asserted while a block erase orword program operation is not executing, the reset will complete within 100 ns.

4. Sampled, but not 100% tested.

35

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

5.0 ORDERING INFORMATION

E

T E 2 8 F 3 2 0 C 3 T 9 0

Package

TE = 48-Lead TSOP

GT = 48-Ball µBGA* CSP

Access Speed (ns)

(90, 110)

T = Top Blocking

B = Bottom Blocking

Product line designator

for all Intel^®Flash products

Device Density

320 = x16 (32 Mbit)

032 = x8 (32 Mbit)

160 = x16 (16 Mbit)

800 = x16 (8 Mbit)

016 = x8 (16 Mbit)

008 = x8 (8 Mbit)

Product Family

C3 = Advanced+ Boot Block

V_CC= 2.7 V - 3.6 V

V_PP= 2.7 V - 3.6 V or 11.4 V - 12.6 V

VALID COMBINATIONS (All Extended Temperature)

40-Lead TSOP

48-Ball µBGA* CSP⁽¹⁾48-Lead TSOP

GT28F032C3T90

GT28F032C3B90

48-Ball µBGA CSP⁽¹⁾

TE28F320C3T90 GT28F320C3T90

TE28F320C3B90 GT28F320C3B90

Extended 32M

GT28F032C3T110

GT28F032C3B110

Extended 16M TE28F016C3T90 GT28F016C3T90

TE28F320C3T110 GT28F320C3T110

TE28F320C3B110 GT28F320C3B110

TE28F160C3T90 GT28F160C3T90

TE28F160C3B90 GT28F160C3B90

TE28F016C3B90 GT28F016C3B90

TE28F016C3T110 GT28F016C3T110

TE28F016C3B110 GT28F016C3B110

TE28F160C3T110 GT28F160C3T110

TE28F160C3B110 GT28F160C3B110

Extended 8M

TE28F008C3T90

TE28F008C3B90

TE28F800C3T90

TE28F800C3B90

TE28F008C3T110

TE28F008C3B110

TE28F800C3T110

TE28F800C3B110

NOTE:

1.

The 48-Ball µBGA package top side mark reads FXX0C3 where XX is the device density. This mark is identical for both

x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture,

however once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side

mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for further details) enables x8

and x16 µBGA package product differentiation.

36

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

(1,2)

6.0 ADDITIONAL INFORMATION

Order Number

Document/Tool

1998 Flash Memory Databook

210830

292216

292215

AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory

AP-657 Designing with the Advanced+ Boot Block Flash Memory

Architecture

3 Volt Advanced+ Boot Block Algorithms (‘C’ and assembly)

http://developer.intel.com/design/flcomp

Contact your Intel

Representative

Flash Data Integrator (FDI) Software Developer’s Kit

297874

FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation

and tools.

37

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

APPENDIX A

WSM CURRENT/NEXT STATES

Command Input (and Next State)

Current

State

SR.7 Data

When

Read

Array

(FFH)

Program

Setup

(10/40H)

Erase

Setup

(20H)

Erase

Confirm

(D0H)

Prog/Ers

Suspend

(B0H)

Prog/Ers

Resume

(D0)

Read

Status

(70H)

Clear

Status

(50H)

Read

Read Array

“1”

“0”

“1”

Array Read Array Program Setup

Status Read Array Program Setup

Config Read Array Program Setup

Erase

Setup

Read Array

Read

Status

Read

Array

Read Status

Erase

Setup

Read

Status

Read

Array

Read

Config.

Erase

Setup

Read

Status

Read

Array

Read Query

CFI

Read Array Program Setup

Lock Command Error

Erase

Setup

Read

Status

Read

Array

Lock Setup

Status

Lock

(Done)

Lock

Cmd. Error

Lock

(Done)

Lock Cmd. Error

Lock Cmd.

Error

Status Read Array Program Setup

Erase

Setup

Read Array

Read

Status

Read

Array

Lock Oper.

(Done)

Status Read Array Program Setup

Erase

Setup

Read Array

Read

Status

Read

Array

Prot. Prog.

Setup

Status

Protection Register Program

Prot. Prog.

(Not Done)

Status

Protection Register Program (Not Done)

Prot. Prog.

(Done)

Status Read Array Program Setup

Erase

Setup

Read Array

Program

Read

Status

Read

Array

Prog. Setup

“1”

“0”

Status

Program

(Not Done)

Status

Program (Not Done)

Program Suspend

Prog. Sus.

Status

Program (Not Done)

Prog. Susp.

Status

“1”

“0”

“1”

Status Prog. Sus.

Read Array

Program

Prog. Sus.

(Not Done) Rd. Array (Not Done)

Program

Prog. Sus. Prog. Sus.

Status Rd. Array

Read Array

Prog. Susp.

Read Array

Array

Prog. Sus.

Read Array

Program Suspend

Read Array

Program Prog. Sus. Program

Prog. Sus. Prog. Sus.

Status Rd. Array

(Not Done) Rd. Array (Not Done)

Program Prog. Sus. Program

Prog. Susp.

Read Config

Config Prog. Sus.

Read Array

Program Suspend

Read Array

Prog. Sus. Prog. Sus.

Status Rd. Array

(Not Done) Rd. Array (Not Done)

Prog. Susp.

Read Query

CFI

Prog. Sus.

Read Array

Program Suspend

Read Array

Program Prog. Sus. Program

Prog. Sus. Prog. Sus.

Status

(Not Done) Rd. Array (Not Done)

Read Array

Rd. Array

Program

(Done)

Status Read Array Program Setup

Status Erase Command Error

Status Read Array Program Setup

Status

Erase

Setup

Read

Status

Read

Array

Erase Setup

Erase

Erase Command Error

(Not Done) Cmd. Error (Not Done)

Erase Cmd.

Error

Erase

Setup

Read Array

Read

Status

Read

Array

Erase

(Not Done)

Erase (Not Done)

Erase Sus.

Status

Erase (Not Done)

Ers. Susp.

Status

Status Erase Sus. Program Setup Ers. Sus.

Read Array Rd. Array

Erase

Ers. Sus.

Rd. Array

Erase

Erase Sus. Ers. Sus.

Status Rd. Array

Erase Susp.

Array

Erase Sus. Program Setup Ers. Sus.

Read Array Rd. Array

Ers. Sus.

Rd. Array

Erase Sus. Ers. Sus.

Status Rd. Array

Ers. Susp.

Read Config

Config Erase Sus. Program Setup Ers. Sus.

Read Array Rd. Array

Ers. Sus.

Rd. Array

Erase Sus. Ers. Sus.

Status Rd. Array

Ers. Susp.

Read Query

CFI

Erase Sus. Program Setup Ers. Sus.

Ers. Sus.

Rd. Array

Erase Sus. Ers. Sus.

Status

Read Array

Rd. Array

Erase

(Done)

Status Read Array Program Setup

Erase

Setup

Read Array

Read

Status

Read

Array

38

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

APPENDIX A

WSM CURRENT/NEXT STATES (Continued)

Command Input (and Next State)

Current State

Read Config

(90H)

Read Query

(98H)

Lock Setup

(60H)

Prot. Prog.

Lock Confirm

(01H)

Lock Down

Confirm

(2FH)

Unlock

Confirm

(D0H)

Setup (C0H)

Read Array

Read Status

Read Config.

Read Query

Read Config.

Read Query

Lock Setup

Prot. Prog.

Setup

Read Array

Prot. Prog.

Setup

Read Array

Prot. Prog.

Setup

Read Array

Prot. Prog.

Setup

Read Array

Lock

Setup

Locking Command Error

Lock Operation (Done)

Read Array

Lock Cmd.

Error

Read Config.

Read Query

Lock Setup

Prot. Prog.

Setup

Lock Operation

(Done)

Prot. Prog.

Setup

Read Array

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(Not Done)

Protection Register Program (Not Done)

Prot. Prog.

(Done)

Read Config.

Read Query

Lock Setup

Prot. Prog.

Setup

Read Array

Prog. Setup

Program

Program (Not Done)

(Not Done)

Prog. Susp.

Status

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program Suspend Read Array

Program

(Not Done)

Prog. Susp.

Read Array

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Prog. Susp.

Read Config.

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Prog. Susp.

Read Query.

Prog. Susp.

Read Config.

Prog. Susp.

Read Query

Program

(Not Done)

Program

(Done)

Read Config.

Read Query

Lock Setup

Prot. Prog.

Setup

Read Array

Erase

Setup

Erase Command Error

Erase

(Not Done)

Erase Cmd.

Error

Read Config.

Read Query

Prot. Prog.

Setup

Erase

Erase (Not Done)

(Not Done)

Erase Suspend Erase Suspend Erase Suspend

Status Read Config. Read Query

Lock Setup

Erase Suspend Read Array

Erase

(Not Done)

Erase Suspend Erase Suspend Erase Suspend

Array Read Config. Read Query

Erase Suspend Read Array

Erase

(Not Done)

Eras Sus. Read Erase Suspend Erase Suspend

Config Read Config. Read Query

Erase

(Not Done)

Eras Sus. Read Erase Suspend Erase Suspend

Erase

(Not Done)

Query

Read Config.

Read Query

Ers.(Done)

Read Config.

Read Query

Prot. Prog.

Setup

Read Array

39

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

APPENDIX B

PROGRAM/ERASE FLOWCHARTS

Start

Bus Operation

Write

Command

Program Setup

Program

Comments

Data = 40H

Write 40H

Data = Data to Program

Addr = Location to Program

Write

Program Address/Data

Read Status Register

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Repeat for subsequent programming operations.

No

SR.7 = 1?

Yes

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Standby

Command

Comments

Check SR.3

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4

1 = V_PPProgram Error

Standby

0

SR.4 =

0

Check SR.1

1

1 = Attempted Program to

Locked Block - Program

Aborted

Standby

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Block - Aborted

SR.1 =

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

Figure 12. Automated Word Programming Flowchart

40

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

Bus

Operation

Command

Comments

Data = B0H

Start

Program

Suspend

Write

Addr = X

Write B0H

Data=70H

Addr=X

Write

Read

Read Status

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write 70H

Read Status Register

SR.7 =

Read

Standby

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Check SR.2

1 = Program Suspended

0 = Program Completed

Standby

Write

0

Read Array

Data = FFH

Addr = X

Write

Read

1

Read array data from block

other than the one being

programmed.

SR.2 =

Program Completed

Program

Resume

Read

Write

1

Program

Resume

Data = D0H

Addr = X

Write

Write FFH

Read Array Data

No

Done

Reading

Yes

Write D0H

Write FFH

Program Resumed

Read Array Data

Figure 13. Program Suspend/Resume Flowchart

41

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

Start

Bus Operation

Command

Comments

Data = 20H

Addr = Within Block to Be

Erased

Write

Erase Setup

Write 20H

Data = D0H

Write

Read

Erase Confirm

Addr = Within Block to Be

Erased

Write D0H and

Block Address

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read Status Register

Suspend

Erase Loop

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

No

0

Yes

SR.7 =

Suspend Erase

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

1

Full Status

Check if Desired

Write FFH after the last write operation to reset device to read array mode.

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

Standby

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4,5

Standby

Both 1 = Command Sequence

Error

0

SR.4,5 =

0

1

Check SR.5

1 = Block Erase Error

Command Sequence

Error

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

SR.5 =

0

Block Erase Error

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

Attempted Erase of

Locked Block - Aborted

SR.1 =

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Block Erase

Successful

Figure 14. Automated Block Erase Flowchart

42

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

Bus

Operation

Command

Comments

Data = B0H

Start

Program

Erase Suspend

Suspend

Write

Addr = X

Write B0H

Data=70H

Addr=X

Write

Read

Read Status

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write 70H

Read Status Register

SR.7 =

Read

Standby

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Check SR.6

1 = Erase Suspended

0 = Erase Completed

Standby

Write

0

Read Array

Data = FFH

Addr = X

Write

Read

1

Read array data from block

other than the one being

erased.

SR.6 =

Erase Completed

Program

Resume

Read

Write

1

Data = D0H

Addr = X

Write

Erase Resume

Write FFH

Read Array Data

No

Done

Reading

Yes

Write D0H

Write FFH

Erase Resumed

Read Array Data

Figure 15. Erase Suspend/Resume Flowchart

43

PRODUCT PREVIEW

3 VOLT ADVANCED+ BOOT BLOCK

E

Bus

Operation

Command

Comments

Start

Program

Config. Setup

Suspend

Data = 60H

Write

Addr = X

Write 60H

(Configuration Setup)

Data= 01H (Lock Block)

D0H (Unlock Block)

2FH (Lockdown Block)

Addr=Within block to lock

Lock, Unlock,

or Lockdown

Write

01H, D0H, or 2FH

Write

Read

Data = 70H

(Optional)

Status Register Addr = X

Read

(Optional)

Status Register Data

Addr = X

Write 70H

(Read Status Register)

Check Status Register

80H = no error

Standby

(Optional)

30H = Lock Command

Sequence Error

Lock Command

Sequence Error

Read Status Register

Write

Read

Data = 90H

(Optional)

Configuration Addr = X

1,1

Read

(Optional)

Block Lock

Status

Block Lock Status Data

Addr = Second addr of block

SR.4, SR.5 =

0,0

Confirm Locking Change on

DQ₁, DQ₀. (See Block Locking

State Table for valid

Standby

(Optional)

combinations.)

Write 90H

(Read Configuration)

Read Block Lock Status

Locking

Change

Confirmed?

No

Locking Change

Complete

Figure 16. Locking Operations Flowchart

44

PRODUCT PREVIEW

E

3 VOLT ADVANCED+ BOOT BLOCK

Start

Bus Operation

Write

Command

Comments

Protection Program

Setup

Data = C0H

Write C0H

(Protection Reg.

Program Setup)

Data = Data to Program

Addr = Location to Program

Write

Protection Program

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write Protect. Register

Address/Data

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Protection Program operations can only be addressed within the protection

register address space. Addresses outside the defined space will return an

error.

No

SR.7 = 1?

Yes

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Full Status

Check if Desired

Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Standby

Command

Comments

SR.1 SR.3 SR.4

Read Status Register

Data (See Above)

0

1

V_PPLow

1, 1

0

1

Prot. Reg.

Prog. Error

Standby

SR.3, SR.4 =

SR.1, SR.4 =

V_PPRange Error

1

0

1

Register

Locked:

Aborted

0,1

1,1

Standby

Protection Register

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Register -

Aborted

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

SR.1, SR.4 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

Figure 17. Protection Register Programming Flowchart

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E

APPENDIX C

COMMON FLASH INTERFACE QUERY STRUCTURE

This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query

command. System software should parse this structure to gain critical information such as block size, density,

x8/x16, and electrical specifications. Once this information has been obtained, the software will know which

command sets to use to enable flash writes, block erases, and otherwise control the flash component. The

Query is part of an overall specification for multiple command set and control interface descriptions called

Common Flash Interface, or CFI.

C.1

QUERY STRUCTURE OUTPUT

The Query “database” allows system software to gain critical information for controlling the flash component.

This section describes the device’s CFI-compliant interface that allows the host system to access Query data.

Query data are always presented on the lowest-order data outputs (DQ_0-7) only. The numerical offset value is

the address relative to the maximum bus width supported by the device. On this family of devices, the Query

table device starting address is a 10h, which is a word address for x16 devices or a byte address for x8

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q”, ”R”, and “Y” in ASCII, appear on

the low byte at word addresses 10h, 11h, and 12h. This CFI-compliant device outputs 00H data on upper

bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ_0-7) and 00h in the high byte (DQ_8-15).

At Query addresses containing two or more bytes of information, the least significant data byte is presented

at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix

has been dropped. In addition, since the upper byte of word_-wide devices is always “00h,” the leading “00”

has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can

be assumed to have 00h on the upper byte in this mode.

Table C1. Summary of Query Structure Output As a Function of Device and Mode

Device

Location

Query Data

(Hex, ASCII)

8-Mbit x8/8-Mbit x 16, 16-Mbit x 8/16-Mbit x 16

(Word or Byte Addresses)

10

11

12

51 “Q”

52 “R”

59 “Y”

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Table C2. Example of Query Structure Output of x16 and x8 Devices

Device

Word Addressing:

Query Data

Byte

Address

Byte Addressing:

Query Data

Address

A₁₆–A₁

D₁₅–D₀

A₇–A₀

D₇–D₀

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051h “Q”

0052h “R”

0059h “Y”

P_ID_LOPrVendor ID# (Lo byte)

P_ID_HIPrVendor ID# (HI byte)

10h

11h

12h

13h

14h

15h

16h

17h

18h

...

51h

52h

59h

“Q”

“R”

“Y”

P_ID_LOPrVendor ID# (Lo)

P_ID_HIPrVendor ID# (Hi)

P_LO

P_HI

A_ID_LOAltVndr ID# (Lo)

A_ID_HIAltVndr ID# (Hi)

P_LO

P_HI

PrVendor TblAddr (Lo)

PrVendor TblAddr (Hi)

PrVndr TblAdr (Lo)

PrVndr TblAdr (Hi)

A_ID_LOAltVendor ID# (Lo)

A_ID_HIAltVendor ID# (Hi)

...

C.2

QUERY STRUCTURE OVERVIEW

The Query command causes the flash component to display the Common Flash Interface (CFI) Query

structure or “database.” The structure sub-sections and address locations are summarized in Table D3.

The following sections describe the Query structure sub-sections in detail.

Table C3. Query Structure⁽¹⁾

Offset

00h

Sub-Section Name

Description

Manufacturer Code

01h

Device Code

02-0Fh

10h

Reserved

Reserved for vendor-specific information

Command set ID and vendor data offset

Device timing & voltage information

Flash device layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

P⁽³⁾

Primary Intel-specific Extended Query

Vendor-defined additional information

table

specific to the Primary Vendor Algorithm

NOTES:

1. Refer to Section D.1 and Table D1 for the detailed definition of offset address as a function of device bus width and mode.

2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is

32 Kword).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

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C.3 BLOCK LOCK STATUS

The Block Lock Status indicates the locking settings of a block.

E

Table C4. Block Lock Status Register

Description

Offset

Length

(bytes)

C3

x16 Device/Mode

(BA+2)h⁽¹⁾

01h

Block Lock Status

BA+2:

(see Section 3.3)

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)

C.4

CFI QUERY IDENTIFICATION STRING

The Identification String provides verification that the component supports the Common Flash Interface

specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s)

is (are) supported.

Table C5. CFI Identification

Offset

Length

(Bytes)

Description

8-Mbit, 16-Mbit, 32-Mbit

10h

03h

02h

Query-Unique ASCII string “QRY“

10: 51

11: 52

12: 59

13h

15h

17h

Primary Vendor Command Set and Control Interface

ID Code

16-bit ID Code for Vendor-Specified Algorithms

13: 03

14: 00

Address for Primary Algorithm Extended Query

Table

Offset value = P = 35h

15: 35

16: 00

Alternate Vendor Command Set and Control

Interface ID Code

17: 00

18: 00

Second Vendor-Specified Algorithm Supported

Note: 0000h means none exists

19h

02h

Address for Secondary Algorithm Extended Query

Table

19: 00

1A: 00

Note: 0000h means none exists

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C.5

SYSTEM INTERFACE INFORMATION

The following device information can be useful in optimizing system interface software

Table C6. System Interface Information

Offset

Length

(bytes)

Description

8-Mbit, 16-Mbit, 32-Mbit

1Bh

01h

V_CCLogic Supply Minimum Program/Erase Voltage

bits 7–4 BCD volts

1B:27

bits 3–0 BCD 100 mv

1Ch

1Dh

V_CCLogic Supply Maximum Program/Erase Voltage

bits 7–4 BCD volts

1C:36

1D:B4

bits 3–0 BCD 100 mv

V_PP[Programming] Supply Minimum Program/Erase

Voltage

bits 7–4 HEX volts

bits 3–0 BCD 100 mv

1Eh

01h

V_PP[Programming] Supply Maximum

Program/Erase Voltage

bits 7–4 HEX volts

1E:C6

bits 3–0 BCD 100 mv

1Fh

01h

Typical Time-Out per Single Byte/Word Program,

2^Nµ-sec

1F:05

20h

21h

01h

Typical Time-Out for Max. Buffer Write, 2^Nµ-sec

20:00

21:0A

Typical Time-Out per Individual Block Erase,

2^Nm-sec

22h

23h

01h

Typical Time-Out for Full Chip Erase, 2^Nm-sec

22:00

23:04

Maximum Time-Out for Byte/Word Program,

2^NTimes Typical

24h

25h

26h

01h

Maximum Time-Out for Buffer Write, 2^NTimes

Typical

24:00

25:03

26:00

Maximum Time-Out per Individual Block Erase,

2^NTimes Typical

Maximum Time-Out for Chip Erase, 2^NTimes

Typical

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C.6 DEVICE GEOMETRY DEFINITION

This field provides critical details of the flash device geometry.

E

Table C7. Device Geometry Definition

Length (bytes) Description

Offset

27h

01h

02h

Device Size = 2^Nin Number of Bytes

Flash Device Interface Description

28h

value

meaning

28:00, 29:00

28:01,29:00

x8 asynch

x16 asynch

2Ah

2Ch

02h

01h

Maximum Number of Bytes in Write Buffer = 2^N

Number of Erase Block Regions within Device:

bits 7–0 = x = # of Erase Block Regions

Erase Block Region Information

2Dh

04h

bits 15–0 = y, Where y+1 = Number of Erase Blocks of Identical

Size within Region

bits 31–16 = z, Where the Erase Block(s) within This Region are

(z) × 256 Bytes

Device Geometry Definition

Offset

8 Mbit

16 Mbit

32 Mbit

-T