HCGD16588EF [INTEL]
Receiver, 1-Func, Bipolar, CBGA132, 13 X 13 MM, CERAMIC, BGA-132;
| 型号： | HCGD16588EF |
| 厂家： | 
INTEL |
| 描述： | Receiver, 1-Func, Bipolar, CBGA132, 13 X 13 MM, CERAMIC, BGA-132 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总15页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 Gbit/s
Receiver, CDR and
DeMUX
GD16584/GD16588
(FEC)
an Intel company
Preliminary
General Description
Features
l
GD16584 and GD16588 are Receiver
chips for use in STM-64/192 and Optical
Transport Networking (OTN) systems.
500 ppm from the reference clock, it
automatically switches the phase and fre-
quency detector into the PLL loop. In the
auto lock mode the locking range is
selectable between 500 or 2000 ppm.
Complete Clock and Data Recovery
IC with auto acquisition.
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1:16 DeMUX with differential
622 Mbit/s data outputs
The component is available in two ver-
sions:
l
u
GD16584 for 9.5328 Gbit/s.
GD16588 for 10.66 Gbit/s for OTN or
When the VCO frequency is within the
lock range, the Bang-Bang Phase Detec-
tor takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A ±40 mV
Decision Threshold Control (DTC) is pro-
vided at the 10 Gbit/s input.
622 MHz Clock output.
u
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Forward Error Correction (FEC).
Except the different operating bit rates
the two versions are functional identical.
LVDS compatible clock and data
outputs.
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OIF99.102.5 compliant timing.
The receiver is a Clock and Data Reco-
very IC with:
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155 or 622 MHz Reference Clock.
u
a low noise VCO
a Bang-Bang Phase Detector
l
u
The 10 Gbit/s input data is sampled and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock. The clock
and data outputs are LVDS compatible.
Input Decision Threshold Control
(DTC): ±40 mV.
u
a 1:16 De-multiplexer
a Lock Detect
a Phase and Frequency Detector.
u
l
u
Low noise VCO with 5 % tuning
range.
Clock and data are regenerated by using
a Phase Locked Loop (PLL) with an ex-
ternal passive loop filter.
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The device operates from a dual -5.2 V
and +3.3 V power supply. The power dis-
sipation is 3.3 W, typical.
Dual supply operation: -5.2 V and
+3.3 V.
The VCO frequency is controlled by one
of the two Phase Detectors in order to
ensure capture and lock to the line data
rate. The Lock Detector circuit monitors
the VCO frequency and determines when
the VCO is within the lock range. When
the frequency deviates more than
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Power dissipation: 3.3 W (typ).
The device is manufactured in a Silicon
Bipolar process and packaged in an 132
ball 13 × 13 mm Ceramic/Plastic Ball
Grid Array (BGA).
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Silicon Bipolar technology.
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Available in three package versions:
–
–
–
EB: 132 ball (16 mill) Ceramic
BGA 13 × 13 mm
EF: 132 ball (20 mill) Ceramic
BGA 13 × 13 mm
FB: 132 ball (20 mill) Plastic
BGA 13 × 13 mm
VCO
CKOUT
CKOUTN
Timing Control
VCTL
DO0
DON0
l
Available in two versions:
Parallel
Output
Data
1:16
–
–
GD16584 for 10 Gbit/s
GD16588 for 10.66 Gbit/s
DI
DIN
Bang
Bang
Demultiplexer
Phase
Detector
DO15
DON15
Decision
Threshold
Control
DTC
DTCN
Applications
U
D
PCTL
Phase
Frequency
Detector
l
Telecommunication systems:
–
–
–
SDH STM-64
(PHIGH)
(PLOW)
REFCK
REFCKN
SONET OC-192.
Optical Transport Networking
(OTN)
1/4
Lock
–
FEC applications
Detect
LOCK
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Fibre optic test equipment.
Submarine systems.
RESET TCK
SEL3
SEL1
SEL2
VCC
VDD
VDDA VDDO
VEE
VEEA
Data Sheet Rev.: 12
Functional Details
The application of GD16584 is as re-
ceiver in SDH STM-64 and SONET
OC-192 optical communication systems.
Loop Filter
and DIN) whereby the DC bias voltage at
the input is adjustable by ±40 mV. Opti-
mizing the input decision threshold im-
proves the system input sensitivity by
1-2 dB typical.
A passive loop filter is used for the CMU
consisting of a resistor and a capacitor
driven from the PCTL pin. The PCTL pin
outputs the phase information from the
Bang-Bang Phase Detector. The phase
information is very high frequency pulses
(200 ps pulse width) either charging or
discharging the external capacitor.
It integrates:
u
a Voltage Controlled Oscillator (VCO)
a Bang Bang Phase Detector
u
The input impedance into DTC and
DTCN is 1.5 kW and when not used they
should be de-coupled to 0 V by 100 nF.
u
a Lock Detect Circuit
a 1:16 DeMUX
u
u
a Phase and Frequency Detector
(PFD).
The select inputs (SEL1-3, RESET and
TCK) are low speed inputs that can be
connected directly to the supply rails (0 /
-5.2 V).
The values of the external components
determines the characterisctics of the
PLL, e.g. bandwidth and transfer func-
tions. For recommended loop filter val-
ues, please refer to Figure 1.
VCO
The VCO is an LC-type differential oscil-
lator, voltage controlled by pin VCTL and
with a tuning range of approximately
5 %.
The 10 Gbit/s inputs (DI and DIN) are
not ESD protected and extra precau-
tions are needed when handling these in-
puts. (Internal 50 W resistors provide
some ESD hardness making the input
low impendance.)
The PCB lay-out of the external loop filter
and the connecting lines between PCTL
and VCTL are critical for jitter perfor-
mance of the device. The external com-
ponents and the artwork should be
placed very close to the pins of the
device.
For GD16584, with the VCTL voltage at
approximately -3.5 V, the VCO fre-
quency is fixed at 9.953 GHz and by
changing the voltage from 0 to -5.2 V the
frequency is controlled from 8.9 GHz to
10.2 GHz. The modulation bandwidth of
VCTL is 90 MHz.
Bit Order
If the PHIGH and PLOW outputs are not
used they must be shorted VDD (0 V),
please refer to Figure 1.
The serial data stream is demultiplexed
with the first received bit on DO0, the
second on DO1 and with last received bit
in a 16 bit frame on DO15. The naming is
opposite to the OIF99.102.5 recommen-
dation.
PFD
The PFD ensures predictable locking
conditions for the device. It is used dur-
ing acquisition and pulls the VCO into the
locking range where the Bang-Bang
Phase Detector acquires lock to the in-
coming bit-stream. The PFD is made with
digital set/reset cells giving it a true
phase and frequency characteristic. The
reference clock input (REFCK/REFCKN)
to the PFD is differential and selectable
between 155 MHz or 622 MHz by SEL3.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the VCO clock. If they differ by
more than 500 ppm (or 2000 ppm), it
switches the PFD into the PLL, to pull it
back into the locking range. The status of
the lock circuit is given by output pin
(LOCK). Manual or automatic lock is se-
lected by SEL1. In auto lock mode, the
lock range 500 or 2000 ppm is se-
lected by SEL2. The LOCK output is an
open collector output, and should be ter-
minated with an external resistor. The
maximum termination voltage is +3.5 V.
For OIF interfaces the data pins should
be connected as shown in the following
table.
Note:
The clock output is inverted in
order to refer the data cross-
ing to the rising edge of
CKOUTN
Output Pin:
OIF:
The reference clock is a CML input with
50 W internal termination resistors to 0 V.
The reference clock is typically an X-tal
oscillator type as shown in Figure 1. The
reference clock input should be used dif-
ferential for best performance. If the ref-
erence clock is DC coupled the input
voltage swing is 0 V (high) and -0.4 V
(low).
DO0/DON0
RXDATA15_P/N
(MSB)
DO1/DON1
DO2/DON2
DO3/DON3
DO4/DON4
DO5/DON5
DO6/DON6
DO7/DON7
DO8/DON8
DO9/DON9
DO10/DON10
DO11/DON11
DO12/DON12
DO13/DON13
DO14/DON14
RXDATA14_P/N
RXDATA13_P/N
RXDATA12_P/N
RXDATA11_P/N
RXDATA10_P/N
RXDATA9_P/N
RXDATA8_P/N
RXDATA7_P/N
RXDATA6_P/N
RXDATA5_P/N
RXDATA4_P/N
RXDATA3_P/N
RXDATA2_P/N
RXDATA1_P/N
The Inputs
The input amplifier pin (DI/DIN) is de-
signed as a gain buffer stage with high
sensitivity and internal 50 W resistors ter-
minated to 0 V. After retiming, the data is
de-multiplexed down to 16 bit/s by
demultiplexer.
Bang-Bang Phase Detector
The Bang-Bang phase detector is de-
signed as a true digital type producing a
binary output. It samples the incoming
data prior to, in the vicinity of and after
any potential bit transition.
It is recommended to use the 10 Gbit/s
inputs differentially for best input
sensitivity.
When a transition has occurred, these
three samples tell whether the VCO clock
leads or lags the data. The binary output
is filtered through the (low pass) loop fil-
ter, performing an integration of all poten-
tial bit transitions. Hence the PLL is
The input voltage decision threshold is
adjustable by pin DTC and DTCN when
connected to a potentiometer. Adjusting
the resistor value of the meter controls
the current into DTC and DTCN. This DC
current is mirrored to the input pin (DI
controlled by the bit transition point.
Data Sheet Rev.: 12
GD16584/GD16588
Page 2 of 15
Output Pin:
OIF:
Thermal Condition
DO15/DON15
RXDATA0_P/N
(LSB)
The device dissipates 3.3 W from a dual
voltage supply (–5.2 V and +3.3 V). The
power consumption from the -5.2 V sup-
ply is approximately 2.9 W and 0.4 W
from the +3.3 V supply.
CKOUT
RXCLK_N
RXCLK_P
CKOUTN
The die is mounted on a metal pad di-
rectly connected to the center balls
(E4-9, F4-9, G4-9, and H4-9).
The Outputs
The data and clock outputs are LVDS
compatible outputs with internal bias re-
sistors (500 W) to VCC (+3.3 V)
It is important to have a good thermal
connection from the center balls of the
package via the PCB to the ambient en-
vironment to ensure the best thermal
conditions.
Refer to item “LVDS Compatible Inter-
face” on page 6.
Note:
To obtain TCASE < 70°C,
the PGBA requires (compared
to the CBGA) additional cool-
ing on the case.
Timing to System ASIC
The timing between GD16584 and the
system ASIC at 622 Mbit/s is controlled
by the 622 MHz output clock synchro-
nized with the output data. The clock is
used as the input clock to the ASIC,
clocking the input data into 16 parallel
registers. The timing relation between the
clock and data is given by the AC
Characteristics.
For details, please refer to
Application Note “ PBGA -
Thermal data....”.
10.66 Gbit/s Application
A version of the transmitter with a bit rate
of 10.66 Gbit/s for forward error correc-
tion application is available. The part
number is GD16588.
For a OIF99.102.5 complaint timing the
output clock should be inverted by using:
u
CKOUTN as the positive output clock
(RXCLK_P), and
u
CKOUT as the negative output clock
(RXCLK_N)
The functionality and the pin-out are
identically to GD16584.
The center frequency of the VCO
(10.66 GHz) is the only difference to
GD16584.
External Circuit
The external circuits needed to make the
device work as a complete clock and
data recovery with automatic acquisition
are:
u
A passive loop filter
An X-tal oscillator or reference clock
u
(155 MHz or 622 MHz)
De-coupling capacitors
u
Package
The device is packaged in an 132 ball
Ceramic/Plastic BGA (13 × 13 mm). For
the package outline, please refer to
the Figures on page 13 and 14.
In ceramic package the following pin
pairs are individually shorted inside the
package and mainly used as power pins:
C3/D3, C4/D4, C5/D5, C8/D8, C9/D9,
C10/D10, J3/K3, J4/K4, J5/K5, J8/K8,
J9/K9, and J10/K10.
Data Sheet Rev.: 12
GD16584/GD16588
Page 3 of 15
Applications
1
+3.3V
0V
VDD/VDDA/VDDO
VCC
TCK
0V
-5.2V
RESET
Framer
0V
1
0
16
16
SEL1
SEL2
SEL3
DO0..DO15
-5.2V
0V
DON0..DON15
1
0
-5.2V
CKOUT
50W MSL
DI
10Gbit/s
CML Driver
VDD
CKOUTN
DIN
50W MSL
0V
LOCK
+
-
VDD
220
DTC
10k
330W
0V
-5.2V
DTCN
14
8
VREF
330
43
100nF
7
REFCK
VDD
500W
XO-PECL
155/622 MHz
KVG
-5.2V
PLOW
PHIGH
VCTL
-5.2V
REFCKN
150W 33nF
100nF
500W
VDDA
-5.2V
-5.2V
PCTL
VEE/VEEA
-5.2V
Figure 1. Application Information.
VDD pins refer to Pin List
Pin A1 Pin A4
VDD
Pin K4 Pin M12
C
C
C
C
C
C
C
C
C
C
C
C
10mF
VEE
Pin C2 Pin B2
Pin D11 Pin K12
VDDO
VEEA
VDDA
10mF
VCC
VDD
C
C
C
C
10mF
C is 1000nF parallel with 100pF.
VEE pins refer to the Pin List; VEEA pins C3 and D3
Figure 2. De-coupling of the Power Supply.
Data Sheet Rev.: 12
GD16584/GD16588
Page 4 of 15
Applications Continued
10 Gbit/s Input Interface
Postamplifier
GD16584/GD16588
0V
0V
50W
50W
50W
DI
DIN
0/-0.4V
0/-0.4V
50W MSL
-5.2V
>16mA
Figure 3. 10 Gbit/s Input (DI/DIN), DC Coupled
GD16584/GD16588
0V
50W
50W
-5.2V
Post-
amplifier
220W
DI
DIN
50W MSL 100nF
220W
-5.2V
-5.2V
Figure 4. 10 Gbit/s Input (DI/DIN), AC Coupled
Data Sheet Rev.: 12
GD16584/GD16588
Page 5 of 15
LVDS Compatible Interface
GD16584 or
+3.3V
GD16585
VCC
+3.3V
500W
500W
LVDS Input
50W MSL
100W
0V
8mA
-5.2V
Figure 5. LVDS Compatible Output.
Reference Clock Input
GD16584
0V
0V
50W
-5.2V
500W
REFCK
100nF
REFCKN
500W
-5.2V
-5.2V
Figure 6. Reference Clock Input (REFCK/REFCKN), Differential AC Coupled.
Data Sheet Rev.: 12
GD16584/GD16588
Page 6 of 15
Pin List
Mnemonic:
Pin No.:
Pin Type:
Description:
DO0, DON0
DO1, DON1
DO2, DON2
DO3, DON3
DO4, DON4
DO5, DON5
DO6, DON6
DO7, DON7
DO8, DON8
DO9, DON9
DO10, DON10
DO11, DON11
DO12, DON12
DO13, DON13
DO14, DON14
DO15, DON15
A8, B8
A9, B9
LVDS Out
Data output, differential 622 Mbit/s. Demultiplexed to output with
DO0, DO1...DO15 as first received bits.
A10, B10
A11, A12
C11, C12
D12, E12
G11, H12
J12, J11
M11, L10
M10, L9
M9, L8
Note:
The bit naming convention is opposite to OIF99.102.5:
DO0 is MSB. Please refer to item “Bit Order” on page 2.
L6, K6
M5, L5
L4, M3
M2, M1
K3, L2
REFCK, REFCKN
SEL1, SEL2
A5, A6
C5, B5
CML In
ECL In
Reference clock input, differential 155 MHz or 622 MHz.
Clock and Data recovery setup.
SEL1 SEL2
0
0
1
1
0
1
0
1
Auto Lock, 500 ppm.
Auto Lock, 2000 ppm.
Manual Phase Freq. Detector (PFD).
Manual Bang-Bang Phase Detector.
When left open, the inputs are pulled to VDD.
SEL3
K11
ECL In
SEL3
0
1
155 MHz Reference Clock.
622 MHz Reference Clock.
When left open, the input is pulled to VDD.
DI, DIN
H1, E1
CML In
Data input, differential 10 Gbit/s. No ESD input protection.
CKOUT, CKOUTN
L12, L11
LVDS Out
Clock output, differential 622 MHz.
Note: The clock polarity is opposite to OIF99.102.5. Please refer
to item “Bit Order” on page 2 and Figure 1.
LOCK
C6
Open Collector
Lock detect output. When low, the divided VCO frequency
deviates more than 500/2000 ppm from REFCK/REFCKN, should
always be terminated with a resistor to VDD.
PCTL
B3
B1
Analogue Out
Analogue In
Analogue In
Open Collector
ECL In
Charge pump output. Connected to an external passive loop filter.
VCO voltage control input.
VCTL
DTC, DTCN
(PHIGH, PLOW)
TCK
M6, K5
A3, B4
C1
Decision threshold control.
Not used. Always terminate to VDD.
Connect to VDD. Used for test purpose. When left open, the input
is pulled to VDD.
RESET
VDD
L1
ECL In
PWR
Connect to VEE. Not needed on power up, used for test purpose.
Digital Ground 0 V.
A1, A4, B6, C10,
D1-2, D6, D10,
E4-9, F1-2, F4-9,
F11, G1-2, G4-9,
H4-9, J1-2, J4, J7,
K4, M12
VDDA
VDDO
VCC
B2
C2
PWR
PWR
PWR
PLL Ground 0 V.
VCO Ground 0 V. For test purpose, connect to VEE.
+3.3 V Digital supply voltage.
D11, K12
Data Sheet Rev.: 12
GD16584/GD16588
Page 7 of 15
Mnemonic:
Pin No.:
Pin Type:
Description:
VEE
C4, C8, D4, D7-8,
J8-9, K1, K8-9
PWR
-5.2 V Digital supply voltage.
VEEA
NC
C3, D3
PWR
-5.2 V PLL supply voltage.
A2, A7, B7,
Not Connected. Reserved for future use.
B11-12, C7, C9,
D9, F12, G12, J6,
J10, K2, K7, K10,
L3, L7, M4, M7-8,
NC
D5, J3, J5
DO NOT CONNECT
Package Pinout
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
M
1
2
3
4
5
6
7
8
9
10
11
12
(empty) = VDD
= Internally shorted in the package
Figure 7. Packages EB and EF Pinout. Top View - Seen Through the Package
Data Sheet Rev.: 12
GD16584/GD16588
Page 8 of 15
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
M
1
2
3
4
5
6
7
8
9
10
11
12
(empty) = VDD
= Internally shorted in the package
Figure 8. Package FB Pinout. Top View - Seen Through the Package
Data Sheet Rev.: 12
GD16584/GD16588
Page 9 of 15
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in table are referred to VDD.
All currents are defined positive out of the pin.
VDD is 0 V or GND.
Symbol:
VEE
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
0
UNIT:
V
Negative Supply
-6
VCC
Positive Supply
+4
V
VO LVDS
IO LVDS
VI CML, ECL
II CML
LVDS Output Voltage
LVDS Output Current
CML and ECL Input Voltage
CML Input Current
0
-24
VCC +0.5
24
V
Note 1
Note 1
mA
V
VEE +2
-24
0.5
24
mA
V
VO OC
IO OC
Open Collector Output Voltage
Open Collector Output Current
Static Discharge Voltage
VEE -0.5
-12
0
Note 1
0
mA
V
V ESD
HBM, Note 3
CDM, Note 4
Note 2
500
50
V
TJ
Junction Temperature
Storage Temperature
-55
-65
+125
+125
°C
°C
TS
Note 1: Nominal supply voltages.
Note 2: The maximum junction temperature equals a maximum case temperature of 95 °C (top side) with the device mounted on
the GD90584/585 Evaluation Board.
Note 3: Human Body Model: MIL 883D 3015.7 standard.
Note 4: Charge Device Model.: JESD2-C101 standard.
Data Sheet Rev.: 12
GD16584/GD16588
Page 10 of 15
DC Characteristics
TCASE* = 0 °C to 70 °C. VEE = -5.2 V, VCC = +3.3 V. VDD is 0 V or GND.
All voltages in table are referred to VDD.
All currents are defined positive out of pin.
Symbol:
VEE
Characteristic:
Conditions:
MIN.:
-5.46
455
TYP.:
-5.2
550
3.3
-140
1.4
1.1
400
0
MAX.:
-4.94
660
UNIT:
V
Negative Supply Voltage
Negative Supply Current
Positive Supply Voltage
IEE
mA
V
VCC
3.135
-180
3.465
ICC
Positive Supply Current
mA
V
VOH LVDS
VOL LVDS
VOD LVDS
VIH CML
VIL CML
IIH CML
IIL CML
RIN CML
IOH OC
IOL OC
VIH ECL
VIL ECL
IIH ECL
IIL ECL
VADS
LVDS Output Voltage High
LVDS Output Voltage Low
LVDS Output Differential Voltage
CML Input Voltage High
Note 7, VCC = 3.3 V
Note 7, VCC = 3.3 V
Note 7, VCC = 3.3 V
1.5
0.9
250
-0.1
-1
V
600
+0.1
-0.25
mV
V
CML Input Voltage Low
-0.4
0
V
CML Input Current High
VIH CML, 50 W input
VIL CML, 50 W input
DC
mA
mA
W
CML Input Current Low
8
CML Input Resistor Termination
Open Collector Output Current High
Open Collector Output Current Low
ECL Input Voltage High
40
-0.1
-10
-1.1
VEE
50
60
+0.1
-7
Note 1, 3
0
mA
mA
V
Note 1, 3
-8
Note 2, 5
0
ECL Input Voltage Low
Note 2, 5
-1.5
30
V
ECL Input Current High
V = -1.1 V
V = -1.5 V
Note 4, 6
mA
mA
mV
ECL Input Current Low
30
Offset Adjustment by DTC/DTCN, Differential
±90
Note 1: Output externally terminated by 50 W to 0 V.
Note 2: All ECL inputs can be connected directly to VDD/VEE.
Note 3: All open collector outputs should always be terminated with a resistor.
Note 4: With DTC and DTCN connected to a 10k potentiometer with the mid pin grounded (0 V).
Note 5: -5.0 V.
Note 6: With open data inputs.
Note 7: With 100 W termination resistor.
*:
TCASE measured at the center of the top.
Data Sheet Rev.: 12
GD16584/GD16588
Page 11 of 15
AC Characteristics
TCASE* = 0 °C to 70 °C. VEE = -5.2 V, VCC = +3.3 V.
CKOUT
CKOUTN
DO0-15
tD
Figure 9. OIF99.102.5 complaint timing relation between the negative output clock (CKOUTN) and output data (DO0-15).
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT:
JTol
Jitter tolerance
f < 400 kHz
4 MHz < f
Note 4
1.5
0.15
UI
tD
Delay between DO0-15 and
CKOUT/CKOUTN
0
120
200
ps
V DI/DIN
Data input sensitivity, differential
DI/DIN input reflection coefficient
Note 2
Note 3
100
-10
mVPP
dB
G DI/DIN
DCYCLE CKOUT/N CKOUT/CKOUTN duty cycle
45
55
%
F REFCK/N
REFCK/REFCKN frequency
Note 1
155/622
MHz
ppm
DC
REFCK frequency deviation from nominal
line frequency
-100
40
100
60
DCYCLE REFCK/N REFCK duty cycle
%
Note 1: Selectable by SEL3.
Note 2: BER = 10-9
Note 3: From DC to 6 GHz. Depends on lead length, board, soldering etc. of the component.
Note 4: Measured with the recommended loop filter, see Figure 1.
*:
TCASE measured at the center of the top.
Data Sheet Rev.: 12
GD16584/GD16588
Page 12 of 15
Package Outline
EF - Package
Figure 10. Package 132 ball ceramic BGA (EB and EF package). All dimensions are in mm.
Data Sheet Rev.: 12
GD16584/GD16588
Page 13 of 15
Figure 11. Package 132 ball plastic BGA (FB package). All dimensions are in mm.
Data Sheet Rev.: 12
GD16584/GD16588
Page 14 of 15
Device Marking
GD16584-<XX>
<Wafer #>-<Lot #>
<Intel FPO #>
<Die ID>
GD16588-<XX>
<Wafer #>-<Lot #>
<Intel FPO #>
<Die ID>
Figure 12. Device marking. Top view. The black square marks location of ball A1.
Ordering Information
To order, please specify as shown below:
Product Name:
GD16584-EB
GD16584-EF
GD16584-FB
GD16588-EB
GD16588-EF
GD16588-FB
Version:
Package Type:
Intel Order Number: Case Temperature
Range:
10 Gbit/s
132 ball (16 mill) Ceramic BGA HCGD16584EB
MM# 835478
0..70 °C
0..70 °C
0..70 °C
0..70 °C
0..70 °C
0..70 °C
10 Gbit/s
132 ball (20 mill) Ceramic BGA HCGD16584EF
MM# 837347
10 Gbit/s
132 ball (20 mill) Plastic BGA RCGD16584FB
MM# 836957
10.66 Gbit/s
10.66 Gbit/s
10.66 Gbit/s
132 ball (16 mill) Ceramic BGA HCGD16588EB
MM# 835480
132 ball (20 mill) Ceramic BGA HCGD16588EF
MM# 837349
132 ball (20 mill) Plastic BGA RCGD16588FB
MM# 836962
GD16584/GD16588, Data Sheet Rev.: 12 - Date: 2 November 2001
an Intel company
Mileparken 22, DK-2740 Skovlunde
Denmark
Phone : +45 7010 1062
Distributor:
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
Please check our Internet web site
for latest version of this data sheet.
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