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IMC002FLSA [INTEL]

SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA; 系列2闪存卡iMC002FLSA ， iMC004FLSA ， iMC010FLSA ， iMC020FLSA
IMC002FLSA
型号： IMC002FLSA
厂家： INTEL    INTEL
描述：

SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA
系列2闪存卡iMC002FLSA ， iMC004FLSA ， iMC010FLSA ， iMC020FLSA

闪存 存储 内存集成电路
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SERIES 2 FLASH MEMORY CARDS  
iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA  
Extended Temperature Specifications Included  
Y
Y
Y
2, 4, 10 and 20 Megabyte Capacities  
High-Performance Read Access  
Ð 150 ns Maximum  
PCMCIA 2.1/JEIDA 4.1 68-Pin Standard  
Ð Hardwired Card Information  
Structure  
Y
Y
Y
Y
High-Performance Random Writes  
Ð 6 ms Typical Word Write  
Ð Byte- or Word-Wide Selectable  
Erase Suspend to Read Command  
Ð Keeps Erase as Background Task  
Y
Component Management Registers for  
Card Status/Control and Flexible  
System Interface  
Nonvolatility (Zero Retention Power)  
Ð No Batteries Required for Back-up  
Y
Y
Automatic Erase/Write  
Ð Monitored with Ready/Busy Output  
ETOXTM V 0.4m Flash Memory  
Technology  
Ð 5V Read, 12V Erase/Write  
Ð High-Volume Manufacturing  
Experience  
Card Power-Down Modes  
Ð Deep-Sleep for Low Power  
Applications  
Y
Y
Y
Y
Mechanical Write Protect Switch  
Solid-State Reliability  
Extended Temperature Version  
b
a
40 C to 85 C  
Ð
§
§
Intel FlashFileTM Architecture  
Intel’s Series 2 Flash Memory Card facilitates high-performance disk emulation in mobile PCs and dedicated  
equipment. Manufactured with Intel’s ETOXTM III 0.8m, FlashFile Memory devices, the Series 2 Card allows  
code and data retention while erasing and/or writing other blocks. Additionally, the Series 2 Flash Memory  
Card features low power modes, flexible system interfacing and a 150 ns read access time. When coupled with  
Intel’s low-power microprocessors, these cards enable high-performance implementations of mobile comput-  
ers and systems.  
Series 2 Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.1)/Jap-  
anese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and  
physical compatibility.  
Data file management software, Flash Translation Layer (FTL), provides data file storage and memory man-  
agement, much like a disk operating system. Intel’s Series 2 Flash Memory Cards, coupled with flash file  
management software, effectively provide a removable, all-silicon mass storage solution with higher perform-  
ance and reliability than disk-based memory architectures.  
Designing with Intel’s FlashFile Architecture enables OEM system manufacturers to design and manufacture a  
new generation of mobile PCs and dedicated equipment where high performance, ruggedness, long battery  
life and lighter weight are a requirement. For large user groups in workstation environments, the Series 2  
Cards provide a means to securely store user data and backup system configuration/status information.  
December 1996  
Order Number: 290434-006  
SERIES 2 FLASH MEMORY CARDS  
Table 1. Series 2 Flash Memory Card Pinout  
Pin  
1
Signal  
GND  
I/O  
Function  
Ground  
Active  
Pin Signal I/O  
GND  
Function  
Ground  
Card Detect 1  
Active  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
Ý
1
2
DQ  
DQ  
DQ  
DQ  
DQ  
I/O Data Bit 3  
I/O Data Bit 4  
I/O Data Bit 5  
I/O Data Bit 6  
I/O Data Bit 7  
CD  
O
LO  
3
4
5
6
7
3
DQ  
DQ  
DQ  
DQ  
DQ  
I/O Data Bit 11  
I/O Data Bit 12  
I/O Data Bit 13  
I/O Data Bit 14  
I/O Data Bit 15  
11  
12  
13  
14  
15  
4
5
6
Ý
7
CE  
I
I
I
I
I
I
I
I
I
Card Enable 1  
LO  
LO  
1
Ý
2
8
A
Address Bit 10  
Output Enable  
Address Bit 11  
Address Bit 9  
Address Bit 8  
Address Bit 13  
Address Bit 14  
Write Enable  
Ready-Busy  
CE  
I
Card Enable 2  
Voltage Sense 1  
Reserved  
LO  
10  
Ý
9
OE  
VS  
O
N.C.  
1
10  
11  
12  
13  
14  
A
A
A
A
A
RFU  
RFU  
11  
Reserved  
9
A
A
A
A
A
V
V
A
A
A
A
I
I
I
I
I
Address Bit 17  
Address Bit 18  
Address Bit 19  
Address Bit 20  
Address Bit 21  
Supply Voltage  
Supply Voltage  
Address Bit 22  
Address Bit 23  
Address Bit 24  
No Connect  
8
17  
18  
19  
20  
21  
CC  
PP2  
22  
23  
24  
25  
13  
14  
Ý
15 WE  
16 RDY/BSY  
LO  
Ý
HI/LO  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
V
V
A
A
A
A
A
A
A
A
A
A
A
Supply Voltage  
Supply Voltage  
Address Bit 16  
Address Bit 15  
Address Bit 12  
Address Bit 7  
Address Bit 6  
Address Bit 5  
Address Bit 4  
Address Bit 3  
Address Bit 2  
Address Bit 1  
Address Bit 0  
CC  
PP1  
16  
15  
12  
7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
VS  
O
I
Voltage Sense 2  
Reset  
N.C.  
HI  
2
6
RST  
WAIT  
RFU  
5
Ý
O
Extend Bus Cycle  
Reserved  
LO  
4
3
Ý
REG  
BVD  
I
Register Select  
Batt. Volt Det 2  
Batt. Volt Det 1  
LO  
2
O
O
2
1
BVD  
1
0
DQ  
8
I/O Data Bit 8  
I/O Data Bit 9  
I/O Data Bit 10  
30 DQ  
31 DQ  
32 DQ  
I/O Data Bit 0  
I/O Data Bit 1  
I/O Data Bit 2  
0
1
2
DQ  
9
DQ  
10  
Ý
CD  
O
Card Detect 2  
Ground  
LO  
33 WP  
O
Write Protect  
Ground  
HI  
2
GND  
34 GND  
2
SERIES 2 FLASH MEMORY CARDS  
Table 2. Series 2 Flash Memory Card Pin Descriptions  
Name and Function  
ADDRESS INPUTS: A through A are address bus lines which enable direct  
Symbol  
A –A  
Type  
I
0
25  
0
25  
addressing of 64 megabytes of memory on a card. A is not used in word  
0
access mode. A is the most significant address bit. Note: A is a no-connect  
24  
but should be provided on host side.  
25  
DQ –DQ  
0
I/O  
I
DATA INPUT/OUTPUT: DQ through DQ constitute the bidirectional data  
0 15  
bus. DQ is the most significant bit.  
15  
15  
Ý
CE , CE  
Ý
Ý
Ý
enables even bytes, CE enables odd bytes.  
2
CARD ENABLE 1, 2: CE  
1
2
1
Ý
through DQ7. (See Table 3 for a more detailed description.)  
Ý
allows 8-bit hosts to access all data on DQ  
Multiplexing A , CE  
0
and CE  
1
2
0
Ý
OE  
I
I
OUTPUT ENABLE: Active low signal gating read data from the memory card.  
WRITE ENABLE: Active low signal gating write data to the memory card.  
Ý
WE  
Ý
RDY/BSY  
O
READY/BUSY OUTPUT: Indicates status of internally timed erase or write  
activities. A high output indicates the memory card is ready to accept  
accesses. A low output indicates that a device(s) in the memory card is(are)  
busy with internally timed activities. See text for an alternate function (READY-  
BUSY MODE REGISTER).  
Ý
Ý
2
CD  
& CD  
O
O
CARD DETECT 1, 2: These signals provide for correct card insertion detection.  
They are positioned at opposite ends of the card to detect proper alignment.  
The signals are connected to ground internally on the memory card and will be  
forced low whenever a card is placed in the socket. The host socket interface  
circuitry shall supply 10K or larger pull-up resistors on these signal pins.  
1
WP  
WRITE PROTECT: Write Protect reflects the status of the Write-Protect switch  
e
hardware write lockout to the flash array.  
on the memory card. WP set high  
write protected, providing internal  
V
V
, V  
PP1 PP2  
WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array  
blocks or writing data in the array. They must be 12V to perform an erase/write  
operation.  
CARD POWER SUPPLY (5V nominal) for all internal circuitry.  
GROUND for all internal circuitry.  
CC  
GND  
I
I
Ý
REG  
REGISTER SELECT provides access to Series 2 Flash Memory Card registers  
and Card Information Structure in the Attribute Memory Plane.  
RST  
I
RESET from system, active high. Places card in Power-On Default State.  
t
RESET pulse width must be 200 ns.  
Ý
WAIT  
O
O
WAIT (Extend Bus Cycle) is used by Intel’s I/O cards and is driven high.  
BVD , BVD  
1
BATTERY VOLTAGE DETECT: Upon completion of the power on reset cycle,  
these signals are driven high to maintain SRAM-card compatibility.  
2
RFU  
NC  
RESERVED FOR FUTURE USE  
NO INTERNAL CONNECTION. Pin may be driven or left floating.  
VS , VS  
1
VOLTAGE SENSE: Notifies the host Socket of the card’s V requirements.  
CC  
VS and VS are both open, indicating a 5V V card.  
2
1
2
CC  
3
SERIES 2 FLASH MEMORY CARDS  
290434–3  
Figure 1. Detailed Block Diagram. The Card Control Logic Provides  
Decoding Buffering and Control Signals.  
4
SERIES 2 FLASH MEMORY CARDS  
For systems currently using a static RAM/battery  
configuration for data acquisition, the Series 2 Flash  
Memory Card’s nonvolatility eliminates the need for  
battery backup. The concern for battery failure no  
longer exists, an important consideration for porta-  
ble computers and medical instruments, both requir-  
ing continuous operation. Series 2 Cards consume  
no power when the system is off, and only 60 mA in  
Deep-Sleep mode (2 Megabyte card). Furthermore,  
Flash Memory Cards offer a considerable cost and  
density advantage over memory cards based on  
static RAM with battery backup.  
APPLICATIONS  
Intel’s second generation Series 2 Flash Memory  
Cards facilitate high performance disk emulation for  
the storage of data files and application programs on  
a purely solid-state removable medium. File man-  
agement software, Flash Translation Layer (FTL), in  
conjunction with the Series 2 Flash Memory Cards,  
enable the design of high-performance light-weight  
notebook, palmtop, and pen-based PCs that have  
the processing power of today’s desktop computers.  
Application software stored on the flash memory  
card substantially reduces the slow disk-to-DRAM  
download process. Replacing the mechanical disk  
results in a dramatic enhancement of read perform-  
ance and substantial reduction of power consump-  
tion, size and weightÐconsiderations particularly  
important in portable PCs and equipment. The Se-  
ries 2 Card’s high performance read access time al-  
lows the use of Series 2 Cards in an ‘‘execute-in-  
place’’ (XIP) architecture. XIP eliminates redundancy  
associated with DRAM/Disk memory system archi-  
tectures. Operating systems stored in Flash Memory  
decreases system boot or program load times, en-  
abling the design of PCs that boot, operate, store  
data files and execute application programs from/to  
nonvolatile memory without losing the ability to per-  
form an update.  
Besides disk emulation, the Series 2 Card’s electri-  
cal block-erasure, data writability, and inherent non-  
volatility fit well with data accumulation and record-  
ing needs. Electrical block-erasure provides design  
flexibility to selectively rewrite blocks of data, while  
saving other blocks for infrequently updated param-  
eters and lookup tables. For example, networks and  
systems that utilize large banks of battery-backed  
DRAM to store configuration and status benefit from  
the Series 2 Flash Card’s nonvolatility and reliability.  
SERIES 2 ARCHITECTURE  
OVERVIEW  
The Series 2 Flash Memory Card contains a 2 to 20  
Megabyte Flash Memory array consisting of 2 to 20  
28F008SA FlashFile Memory devices. Each  
28F008SA contains sixteen individually-erasable, 64  
Kbyte blocks; therefore, the Flash Memory Card  
contains from 32 to 320 device blocks. It also con-  
tains two Card Control Logic devices that manage  
the external interface, address decoding, and com-  
ponent management logic. (Refer to Figure 1 for a  
block diagram.)  
File management systems modify and store data  
files by allocating flash memory space intelligently.  
Wear leveling algorithms, employed to equally dis-  
tribute the number of rewrite cycles, ensure that no  
particular block is cycled excessively relative to oth-  
er blocks. This provides hundreds of thousands of  
hours of power on usage.  
This file management software enables the user to  
interact with the flash memory card in precisely the  
same way as a magnetic disk.  
To support PCMCIA-compatible word-wide access,  
devices are paired so that each accessible memory  
block is 64 KWords (see Figure 2). Card logic allows  
the system to write or read one word at a time, or  
one byte at a time by referencing the high or low  
byte. Erasure can be performed on the entire block  
pair (high and low device blocks simultaneously), or  
on the high or low byte portion separately.  
Series 2 Flash Memory Cards provide durable non-  
volatile memory storage for mobile PCs on the road,  
facilitating simple transfer back into the desktop en-  
vironment.  
Also in accordance with PCMCIA specifications this  
product supports byte-wide operation, in which the  
flash array is divided into 128K x 8 bit device blocks.  
In this configuration, odd bytes are multiplexed onto  
the low byte data bus.  
5
SERIES 2 FLASH MEMORY CARDS  
290434–1  
Figure 2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks.  
Series 2 Flash Memory Cards offer additional fea-  
tures over the Bulk Erase Flash Card product family  
Write/erase automation simplifies the system soft-  
ware interface to the card. A two-step command se-  
quence initiates write or erase operations and pro-  
vides additional data security. Internal device circuits  
automatically execute the algorithms and timings  
necessary for data-write or block-erase operations,  
including verifications for long-term data integrity.  
While performing either data-write or block-erase,  
the memory card interface reflects this by bringing  
(refer  
to  
iMC001FLKA,  
iMC002FLKA  
and  
iMC004FLKA data sheets). Some of the more nota-  
ble enhancements include: high density capability,  
erase blocking, internal write/erase automation,  
erase suspension to read, Component Management  
Registers that provide software control of device-  
level functions and a deep-sleep mode.  
Ý
its RDY/BSY (Ready/Busy) pin low. This output  
Erase blocking facilitates solid-state storage applica-  
tions by allowing selective memory reclamation. Mul-  
tiple 64 Kbyte blocks may be simultaneously erased  
within the memory card as long as not more than  
one block per device is erasing. This shortens the  
total time required for erasure, but requires addition-  
al supply current. A block typically requires 1.6 sec-  
onds to erase. Each memory block can be erased  
and completely written 100,000 times.  
goes high when the operation completes. This fea-  
ture reduces CPU overhead and allows software  
polling or hardware interrupt mechanisms. Writing  
memory data is achieved in single byte or word in-  
crements, typically in 6 ms.  
Read access time is 150 ns or less over the entire  
operating temperature range.  
The Reset-PowerDown mode reduces power con-  
sumption to less than 60 mA to help extend battery  
life of portable host systems. Activated through soft-  
ware control, this mode optionally affects the entire  
flash array (Global Reset-PowerDown Register) or  
specific device pairs (Sleep Control Register).  
Erase suspend allows the system to temporarily in-  
terrupt a block erase operation. This mode permits  
reads from alternate device blocks while that same  
device contains an erasing block. Upon completion  
of the read operation, erasure of the suspended  
block must be resumed.  
6
SERIES 2 FLASH MEMORY CARDS  
PCMCIA/JEIDA INTERFACE  
BATTERY VOLTAGE DETECT  
The Series 2 Flash Memory Card interface supports  
the PCMCIA 2.1 and JEIDA 4.1 68-pin card format  
(see Tables 1 and 2). Detailed specifications are de-  
scribed in the PC Card Standard, Release 2.1, July,  
1993, published by PCMCIA. The Series 2 Card con-  
forms to the requirements of both Release 1 and  
Release 2 of the PC Card Standard.  
PCMCIA requires two signals, BVD and BVD , be  
1 2  
supplied at the interface to reflect card battery con-  
dition. Flash Memory Cards do not require batteries.  
When the power on reset cycle is complete, BVD  
1
and BVD are driven high to maintain compatibility.  
2
CARD DETECT  
Series 2 Card pin definitions are equivalent to the  
Bulk-Erase Flash Card except that certain No Con-  
nects are now used. A through A , RST (Reset),  
Ý
Ý
and CD , allow the host to de-  
2
Two signals, CD  
1
termine proper socket seating. They reside at oppo-  
site ends of the connector and are tied to ground  
within the memory card.  
22  
24  
Ý
ments as set by the PCMCIA standard.  
and RDY/BSY  
(Ready/Busy) have pin assign-  
NOTE: The READY/BUSY signal is abbreviated as  
Ý
RY/BY by JEDEC (component level).  
RDY/BSY  
Ý
by PCMCIA (card level) and as  
DESIGN CONSIDERATIONS  
The Series 2 Card consists of two separate memory  
planes: the Common Memory Plane (or Main Memo-  
ry) and the Attribute Memory Plane. The Common  
Memory Plane resides in the banks of device pairs  
and represents the user-alterable memory space.  
The outer shell of the Series 2 card meets all  
PCMCIA/JEIDA Type 1 mechanical specifications.  
See Figure 19 for mechanical dimensions.  
The Component Management Registers (CMR) and  
the hardwired Card Information Structure (CIS) re-  
side in the Attribute Memory Plane within the Card  
Control Logic, as shown in Figure 3. The Card Con-  
trol Logic interfaces the PCMCIA connector and the  
internal flash memory array and performs address  
decoding and data control.  
WRITE PROTECT SWITCH  
A
mechanical write protect switch provides the  
card’s memory array with internal write lockout. The  
Write-Protect (WP) output pin reflects the status of  
this mechanical switch. It outputs a high signal (V  
when writes are disabled. This switch does not lock  
out writes to the Component Management Regis-  
ters.  
)
OH  
IL  
290434–2  
e
e
INTEL  
PCMCIA  
Performance Enhancement Register  
Defined in PCMCIA Release 2.0  
Figure 3. Component Management Registers Allow S/W Control of Components within Card  
7
SERIES 2 FLASH MEMORY CARDS  
ADDRESS DECODE  
The 512 memory-mapped even-byte CMRs are lin-  
early mapped beginning at address 4000H in the At-  
tribute Memory Plane.  
Address decoding provides the decoding logic for  
the 2 to 20 Device Chip Enables and the elements of  
Ý
the Attribute Memory Plane. REG selects between  
e
Ý
e
the Common Memory Plane (REG  
Ý
V
) and the  
DATA CONTROL  
IH  
Attribute Memory Plane (REG  
V ).  
IL  
Data Control Logic selects the path and direction for  
accessing the Common or Attribute Memory Plane.  
It controls any of the PCMCIA-defined Word-Wide,  
Byte-Wide or Odd-Byte modes for either reads or  
writes to these areas. As shown in Table 3, input  
NOTE:  
The Series 2 Card has active address inputs A to  
0
implying that reading and writing to addresses  
A
24  
beyond 32 Megabytes causes wraparound. Further-  
more, reads to illegal addresses (for example, be-  
tween 20 and 32 Meg on a 20 Megabyte card) re-  
turns Default data (00FFH or FFFFH).  
Ý
Ý
pins which determine these selections are REG  
,
.
Ý Ý  
through A , WE , OE , CE , and CE  
24 2  
Ý
A
0
1
PCMCIA specifications allow only even-byte access  
to the Attribute Memory Plane.  
The 28F008SA devices, storing data, applications or  
firmware, form the Common Memory Plane ac-  
cessed individually or as device pairs. Memory is lin-  
early mapped in the Common Memory Plane. Three  
memory access modes are available when access-  
ing the Common Memory Plane: Byte-Wide, Word  
Wide, and Odd-Byte modes.  
In Byte-Wide mode, bytes contiguous in software ac-  
tually alternate between two device blocks of a de-  
vice pair. Therefore, erasure of one device block  
erases every other contiguous byte. In accordance  
with the PCMCIA standard for memory configuration,  
the Series 2 Card does not support confining contig-  
uous bytes within one flash device when in by-8  
mode.  
Additional decoding selects the hardwired PCMCIA  
CIS and Component Management Registers  
mapped in the Attribute Memory Plane beginning at  
address 000000H.  
8
SERIES 2 FLASH MEMORY CARDS  
Table 3. Data Access Mode Truth Table  
Ý
Function Mode REG CE  
Ý
Ý
Ý
OE WE  
Ý
CE  
A
V
PP2  
V
PP1  
D
–D  
D –D  
7 0  
2
1
0
15  
8
COMMON MEMORY PLANE  
(1)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
STANDBY  
X
H
H
H
H
H
H
H
H
H
H
X
X
L
X
H
H
H
H
L
V
V
HIGH-Z  
HIGH-Z  
HIGH-Z  
ODD-BYTE  
ODD-BYTE  
X
HIGH-Z  
EVEN-BYTE  
ODD-BYTE  
EVEN-BYTE  
HIGH-Z  
PPL  
PPL  
PPL  
PPL  
PPL  
PPL  
PPL  
PPL  
PPL  
PPL  
BYTE READ  
H
H
L
L
L
L
H
L
L
L
H
L
H
X
X
L
V
V
V
V
V
V
V
V
L
WORD READ  
L
ODD-BYTE READ  
BYTE WRITE  
L
L
H
H
L
H
H
H
H
V
V
EVEN-BYTE  
ODD-BYTE  
EVEN-BYTE  
X
PPH  
PPH  
H
X
X
L
V
V
V
V
X
PPH  
PPH  
PPH  
PPH  
PPH  
WORD WRITE  
L
V
ODD-BYTE  
ODD-BYTE  
(2)  
ODD-BYTE WRITE  
L
L
V
PPL  
ATTRIBUTE MEMORY PLANE  
(2)  
(2)  
(2)  
(2)  
BYTE READ  
L
L
L
H
H
L
L
L
L
L
H
X
L
L
L
H
H
H
X
X
HIGH-Z  
HIGH-Z  
INVALID  
EVEN-BYTE  
INVALID  
(2)  
X
X
X
(2)  
X
WORD READ  
EVEN-BYTE  
(3)  
DATA  
(2)  
(2)  
ODD-BYTE READ  
BYTE WRITE  
L
L
H
X
L
H
X
X
INVALID  
(3)  
DATA  
HIGH-Z  
(2)  
(2)  
(2)  
(2)  
L
L
H
H
L
L
L
H
H
L
L
X
X
X
X
X
EVEN-BYTE  
INVALID  
(3)  
OPERATION  
H
X
(2)  
(2)  
(2)  
(2)  
WORD WRITE  
L
L
L
L
L
X
X
H
H
L
L
X
X
X
INVALID  
OPERATION  
EVEN-BYTE  
(3)  
ODD-BYTE WRITE  
H
X
INVALID  
OPERATION  
X
(3)  
NOTES:  
1. Standby mode is valid in Common Memory or Attribute Memory access.  
e
2. To meet the low power specifications, V  
V
; however V  
presents no reliability problems.  
PPH  
PP  
3. Odd-Byte data are not valid during access to the Attribute Memory Plane.  
PPL  
e
e
e
V , X Don’t Care.  
IL  
4. H  
V , L  
IH  
9
SERIES 2 FLASH MEMORY CARDS  
PRINCIPLES OF OPERATION  
HARDWIRED CIS  
Intel’s Series 2 Flash Memory Card provides electri-  
cally-alterable, non-volatile, random-access storage.  
Individual 28F008SA devices utilize a Command  
User Interface (CUI) and Write State Machine  
(WSM) to simplify block-erasure and data write oper-  
ations.  
The card’s structure description resides in the even-  
byte locations starting at 0000H and going to the  
CIS ending tuple (FNULL) within the Attribute Memo-  
ry Plane. Data included in the hardwired CIS con-  
sists of tuples. Tuples are a variable-length list of  
data blocks describing details such as manufactur-  
er’s name, the size of each memory device and the  
number of flash devices within the card.  
COMMON MEMORY ARRAY  
Figure 4 shows the Common Memory Plane’s orga-  
nization. The first block pair (64 KWords) of Com-  
mon Memory, referred to as the Common Memory  
Card Information Structure Block, optionally extends  
the hardwired CIS in the Attribute Memory Plane for  
additional card information. This may be written dur-  
ing initial card formatting for OEM customization.  
Since this CIS Block is part of Common Memory, its  
data can be altered. Write access to the Common  
Memory CIS Block is controlled by the Write Protect  
Control Register which may be activated by system  
software after power-up. Additionally, the entire  
Common Memory plane (minus the Common Memo-  
ry CIS Block) may be software write protected. Note  
that the Common Memory CIS Block is not part of  
COMPONENT MANAGEMENT  
REGISTERS (CMRs)  
The CMRs in the Attribute Memory Plane provide  
special, software-controlled functionality. Card Con-  
trol Logic includes circuitry to access the CMRs.  
REG (PCMCIA, pin 61) selects the Attribute Memory  
Plane (and therefore the CMRs) when equal to V  
.
IL  
CMRs are classified into two categories: those de-  
fined by PCMCIA R2.1 and those included by Intel  
(referred to as Performance Enhancement Regis-  
ters) to enhance the interface between the host sys-  
tem and the card’s flash memory array. CMRs (See  
Figure 3) provide seven control functionsÐReady-  
Busy Interrupt Mode, Device Ready-Busy Status,  
Device Ready-Busy Mask, Reset-PowerDown Con-  
trol, Software-controlled Write Protection, Card  
Status and Soft Reset.  
Ý
the Attribute Memory Plane. Do not assert REG to  
access the Common Memory CIS Block.  
13FFFFFH  
Device Pair 9  
1200000H  
Device Pair 8  
1000000H  
SOFT RESET REGISTER (PCMCIA)  
(CONFIGURATION OPTION)  
Device Pair 7  
0E00000H  
Device Pair 6  
0C00000H  
The SOFT RESET REGISTER (Attribute Memory  
Plane Address 4000H, Figure 5) is defined in the  
PCMCIA Release 2.0 specification as the Configura-  
tion Option Register.  
Device Pair 5  
0A00000H  
Device Pair 4  
0800000H  
Device Pair 3  
0600000H  
Bit 7 is the soft reset bit (SRESET). Writing a 1 to  
this bit initiates card reset to the power-on default  
state (see Side Bar page 11). This bit must be  
cleared to use the CMRs or to access the devices.  
Device Pair 2  
0400000H  
Device Pair 1  
0200000H  
Device Pair 0  
0020000H  
SRESET implements in software what the reset pin  
implements in hardware. On power-up, the card au-  
tomatically assumes default conditions. Similar to  
the reset pin (pin 58), this bit clears at the end of a  
power-on reset cycle or a system reset cycle.  
Optional CIS  
0000000H  
Figure 4. Common Memory Plane. Use  
the Optional Common Memory Plane  
CIS for Custom Card Format Information.  
Bits 0 through 6 are not used by this memory card,  
but power up as zeroes for PCMCIA compatibility.  
10  
SERIES 2 FLASH MEMORY CARDS  
SOFT RESET REGISTER  
(CONFIGURATION OPTION REGISTER)  
(Read/Write Register)  
ADDRESS  
4000H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 4  
BIT 2  
BIT 1  
BIT 0  
PCMCIA CONFIGURATION INDEX  
RESETS TO ZERO ON POWER UP  
SRESET  
e
1
RESET, CLEAR TO ACCESS CARD  
Figure 5. SOFT RESET REGISTER (PCMCIA). Sets the Memory Card in the Power-On Default State.  
Global PowerDown Register (PCMCIA)  
(Configuration and Status)  
POWER-ON DEFAULT CONDITIONS  
The Global Reset-PowerDown Register (Attribute  
Memory Plane Address 4002H, Figure 6) is referred  
to as the Configuration and Status Register in the  
PCMCIA Release 2.0 specification.  
All Devices Powered Up In Standby Mode  
#
#
#
Common Memory Available For Writes  
All Device Ready/Busy Outputs Unmasked  
PCMCIA Ready/Busy Mode Enabled  
#
#
Bit 2 (RP) controls global card power-down. Writing  
Ready/Busy Output Goes To Ready  
a 1 to this bit places each device within the card into  
‘‘Deep-Sleep’’ mode. Devices in Deep-Sleep are not  
accessible. Recovery from power-down requires  
500 ns for reads and 1 ms for writes.  
The RP bit defaults to 0 on card power-up or reset.  
Setting or clearing this bit has no affect on the bit  
settings of the Sleep Control Register.  
The remaining Global Reset-PwrDwn Register bits  
are defined for Intel’s family of I/O cards and are  
driven low for compatibility.  
GLOBAL RESET-POWER-DOWN REGISTER  
(CONFIGURATION AND STATUS REGISTER)  
(Read/Write Register)  
e
1
POWER DOWN  
BIT 2  
ADDRESS  
4002H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 1  
BIT 0  
ZEROES  
RP  
ZEROES  
Figure 6. GLOBAL RESET-PWRDWN REGISTER (PCMCIA). The RP  
Bit Enables Reset PowerDown of All Flash Memory Devices.  
11  
SERIES 2 FLASH MEMORY CARDS  
CARD STATUS REGISTER  
(Read Only Register)  
ADDRESS  
4100H  
BIT 7  
ADM  
BIT 6  
ADS  
BIT 5  
BIT 4  
BIT 3  
RP  
BIT 2  
BIT 1  
WP  
BIT 0  
Ý
SRESET  
CMWP  
CISWP  
RDY/BSY  
Figure 7. CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card’s Status  
Reset with 1 indicating reset. When this bit is zero,  
the flash memory array and CMRs may be ac-  
CARD STATUS REGISTER (INTEL)  
cessed, otherwise clear it via the SRESET REGIS-  
TER.  
The Read-Only, CARD STATUS REGISTER (Attri-  
bute Memory Plane Address 4100H, Figure 7) re-  
turns generalized status of the Series 2 Card and its  
CMRs.  
Bit 6 (ADS, ANY DEVICE SLEEP) is the ‘‘ORed’’  
value of the SLEEP CONTROL REGISTER. Power-  
ing down any device pair sets this bit.  
Ý
Ý
Bit 0 (RDY/BSY ) reflects the card’s RDY/BSY  
(Ready-Busy) output. Software polling of this bit pro-  
vides data-write or block-erase operation status. A  
zero indicates a busy device(s) in the card.  
Bit 7 (ADM, ANY DEVICE MASKED) is the ‘‘ORed’’  
value of the READY/BUSY MASK REGISTER.  
Masking any device sets this bit.  
Bit 1 (WP) reports the position of the card’s Write  
Protection switch with 1 indicating write protected. It  
reports the status of the WP pin.  
WRITE PROTECTION REGISTER  
(INTEL)  
Bit 2 (CISWP) reflects whether the Common Memo-  
ry CIS is write protected using the WRITE PROTECT  
REGISTER, with 1 indicating write protected.  
The WRITE PROTECTION REGISTER (Attribute  
Memory Plane Address 4104H, Figure 8) selects  
whether the optional Common Memory CIS and the  
remaining Common Memory blocks are write pro-  
tected (see Figure 4).  
Bit 3 (RP) reports whether the entire flash memory  
array is in ‘‘Deep-Sleep’’ (Reset-PwrDwn) mode,  
with 1 indicating ‘‘Deep-Sleep’’. This bit reflects the  
RP bit of the GLOBAL RESET-POWERDOWN REG-  
ISTER. Powering down all device pairs individually  
(using the Sleep Control Register), also sets this bit.  
Enable Common Memory CIS write protection by  
writing a 1 to the CISWP Bit (bit 0).  
Enable write protection of the remaining Common  
Memory blocks by writing a 1 to the CMWP Bit (bit  
1).  
Bit 4 (CMWP) reports whether the Common Memory  
Plane (minus Common Memory CIS) is write protect-  
ed via the WRITE PROTECT REGISTER with 1 indi-  
cating write protected.  
In the power-on default state, both bits are 0, and  
therefore not write protected.  
Bit 5 (SRESET) reflects the SRESET bit of the SOFT  
RESET REGISTER. It reports that the card is in Soft  
Reserved bits (2–7) have undefined values and  
should be written as zeroes for future compatibility.  
12  
SERIES 2 FLASH MEMORY CARDS  
WRITE PROTECTION REGISTER  
(Read/Write Register)  
ADDRESS  
4104H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
CISWP  
RESERVED FOR FUTURE USE  
CMWP  
e
1
WRITE PROTECT  
Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption  
Sleep Control Register will remain unchanged after  
returning from a global reset and power down (writ-  
SLEEP CONTROL REGISTER (INTEL)  
ing a zero to the RP bit of the Global Reset-Power-  
Down Register).  
Unlike the GLOBAL RESET-POWERDOWN REGIS-  
TER, which simultaneously resets and places all  
flash memory devices into a Deep-Sleep mode, the  
SLEEP CONTROL REGISTER (Attribute Memory  
Plane Address 4118H–411AH, Figure 9) allows se-  
lective power-down control of individual device pairs.  
READY-BUSY STATUS  
REGISTER (INTEL)  
The bits in the Read-only, READY-BUSY Status  
Register (Attribute Memory Plane Address 4130H-  
Writing a 1 to a specific bit of the SLEEP CONTROL  
REGISTER places the corresponding device pair  
into the ‘‘Deep-Sleep’’ mode.Devices in Deep-Sleep  
are not accessible. On cards with fewer than  
20 Megabytes (10 device pairs), writing a one to an  
absent device pair has no affect and reads back as  
zero.  
e
4134H, Figure 10) reflect the status (READY 1,  
e
Ý
BUSY 0) of each device’s RY/BY output. A busy  
condition indicates that a device is currently pro-  
cessing a data-write or block-erase operation.  
These bits are logically ‘‘AND-ed’’ to form the  
Ý
Ready/Busy output (RDY/BSY , pin 16) of the  
PCMCIA interface. On memory cards with fewer  
Ý
than 20 devices, unused Device RY/BY Status  
Register bits appear as ready.  
This register contains all zeroes (i.e., not in Deep-  
Sleep mode) when the card powers up or after a  
hard or soft reset. Furthermore, the Global Reset-  
PowerDown Register has no affect on the contents  
of this register. Therefore, any bit settings of the  
SLEEP CONTROL REGISTER  
(Read/Write Register)  
ADDRESS  
411AH  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
DEVICES  
18/19  
DEVICES  
16/17  
RESERVED  
DEVICES DEVICES DEVICES  
14/15 12/13 10/11  
DEVICES  
8/9  
DEVICES  
6/7  
DEVICES  
4/5  
DEVICES  
2/3  
DEVICES  
0/1  
4118H  
e
1
SELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET  
Figure 9. SLEEP CONTROL REGISTER (Intel) Allows Specific  
Devices to be Reset and Put into Power-Down Mode  
13  
SERIES 2 FLASH MEMORY CARDS  
READY-BUSY STATUS REGISTER  
(Read/Write Register)  
ADDRESS  
4134H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
DEVICE  
19  
DEVICE  
18  
DEVICE  
17  
DEVICE  
16  
RESERVED  
DEVICE  
15  
DEVICE  
14  
DEVICE  
13  
DEVICE  
12  
DEVICE  
11  
DEVICE  
10  
DEVICE  
9
DEVICE  
8
4132H  
4130H  
DEVICE  
7
DEVICE  
6
DEVICE  
5
DEVICE  
4
DEVICE  
3
DEVICE  
2
DEVICE  
1
DEVICE  
0
e
e
DEVICE BUSY  
1
DEVICE READY, 0  
Figure 10. READY-BUSY STATUS REGISTER (Intel) Provides  
Operation Status of All Flash Memory Devices  
e
0), any device RY/BY output going low pulls the  
In an unmasked condition (MASK REGISTER bits  
Ý
card’s RDY/BSY output to V (BUSY). In this  
READY-BUSY MASK REGISTER  
(INTEL)  
Ý
case, all devices must be READY to allow the card’s  
IL  
The bits of the Read/Write READY-BUSY MASK  
REGISTER (Attribute Memory Plane Address  
4120H–4124H, Figure 11) mask out the correspond-  
ing ‘‘AND-ed’’ READY-BUSY STATUS REGISTER  
Ý
bits from the PCMCIA data bus (RDY/BSY , pin 16)  
and the CARD STATUS REGISTER RDY/BSY Bit  
Ý
RDY/BSY output to be ready (V ).This is referred  
IH  
to as the PCMCIA READY-BUSY MODE. An alter-  
nate type of READY-BUSY function is described in  
the next section, READY-BUSY MODE REGISTER.  
Ý
(bit 0).  
READY-BUSY MASK  
(Read/Write Register)  
ADDRESS  
4124H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
DEVICE  
19  
DEVICE  
18  
DEVICE  
17  
DEVICE  
16  
RESERVED  
DEVICE  
15  
DEVICE  
14  
DEVICE  
13  
DEVICE  
12  
DEVICE  
11  
DEVICE  
10  
DEVICE  
9
DEVICE  
8
4122H  
4120H  
DEVICE  
7
DEVICE  
6
DEVICE  
5
DEVICE  
4
DEVICE  
3
DEVICE  
2
DEVICE  
1
DEVICE  
0
e
1
MASK ENABLED  
Figure 11. READY-BUSY MASK REGISTER (Intel) Essential for Write Optimization  
14  
SERIES 2 FLASH MEMORY CARDS  
If the READY-BUSY MASK REGISTER bits are set  
system with immediate notification that a specific  
device’s operation has completed and that de-  
vice may now be used. This is particularly useful  
in a file management application where a block  
pair, containing only deleted files, is being erased  
to free up space so new file data may be written.  
Ý
to ones (masked condition), the RDY/BSY output  
and the CARD STATUS REGISTER RDY/BSY bit  
Ý
will reflect a READY condition regardless of the  
state of the corresponding devices. The READY-  
BUSY MASK REGISTER does not affect the  
READY-BUSY STATUS REGISTER allowing soft-  
ware polling to determine operation status.  
Enabling the HIGH-PERFORMANCE READY-BUSY  
MODE requires a three step sequence:  
Unmasked is the default condition for the bits in this  
register. On memory cards with fewer than 20 devic-  
es, unused device mask bits appear as masked.  
1. Set all bits in the READY/BUSY MASK REGIS-  
TER. This prevents ready devices from triggering  
an unwanted interrupt when step 3 is performed.  
2. Write 01H to the READY-BUSY MODE REGIS-  
TER. This sets the MODE bit.  
READY-BUSY MODE REGISTER  
(INTEL)  
3. Write 01H to the READY-BUSY MODE REGIS-  
TER. This clears the RACK bit.  
The READY-BUSY MODE REGISTER (Attribute  
Memory Plane Address 4140H, Figure 12) provides  
the selection of two types of system interfacing for  
the busy-to-ready transition of the card’s  
The MODE and RACK bits must be written in the  
prescribed sequence, not simultaneously. The  
card’s circuitry is designed purposely in this manner  
to prevent an initial, unwanted busy-to-ready tran-  
sition. Note that in Step 2, writing to the RACK bit is  
a Don’t Care.  
Ý
RDY/BSY pin:  
1. The standard PCMCIA READY-BUSY MODE, in  
Ý
which the card’s RDY/BSY signal generates a  
low-to-high transition (from busy to ready) only  
after all busy devices (not including masked  
devices) have completed their data-write or block-  
erase operations. This may result in a long inter-  
rupt latency.  
When the High-Performance Mode is enabled, spe-  
cific READY-BUSY MASK bits must be cleared after  
an operation is initiated on the respective devices.  
Ý
After each device becomes ready, the RDY/BSY  
pin makes a low-to-high transition. To catch the next  
device’s completion of an operation, the RACK bit  
must be cleared by writing ‘‘01H’’ to the Ready/Busy  
Mode Register.  
2. A High-Performance mode that generates a low-  
to-high (from busy-to-ready) transition after each  
device becomes ready. This provides the host  
READY-BUSY MODE REGISTER  
(Read/Write Register)  
ADDRESS  
4140H  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
RESERVED FOR FUTURE USE  
RACK  
MODE  
e
PCMCIA MODE  
HIGH PERFORMANCE  
MODE  
READY-BUSY MODE  
e
e
0
1
e
RACK  
READY ACKNOWLEDGE CLEAR TO  
Ý
SET UP RDY/BSY PIN, THEN CLEAR AFTER  
EACH DEVICE BECOMES READY TO ACKNOWL-  
EDGE TRANSITION.  
Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)  
Used to Trigger a Ready Interrupt for Each Device  
15  
SERIES 2 FLASH MEMORY CARDS  
The CUI initiates flash memory writing and erasing  
operations only when V is at 12V. Depending on  
PRINCIPLES OF DEVICE OPERATION  
PP  
the application, the system designer may choose to  
Individual 28F008SA devices include a Command  
User Interface (CUI) and a Write State Machine  
(WSM) to manage write and erase functions in each  
device block.  
make the V  
power supply switchable (available  
when writes and erases are required) or hardwired to  
PP  
e
V
. When V  
V , power savings are in-  
PPL  
PPH  
PP  
curred and memory contents cannot be altered. The  
CUI architecture provides protection from unwanted  
write and erase operations even when high voltage  
is applied to V . Additionally, all functions are dis-  
PP  
abled whenever V is below the write lockout volt-  
CC  
The CUI serves as the device’s interface to the Card  
Control Logic by directing commands to the appro-  
priate device circuitry (Table 4). It allows for fixed  
power supplies during block erasure and data writes.  
age V , or when the card’s Deep-Sleep modes  
LKO  
Ý
The CUI handles the WE interface into the device  
are enabled. The WSM automates the writing and  
erasure of blocks within a device. This on-chip state  
machine controls block erase and data-write, freeing  
the host processor for other tasks. After receiving  
the Erase Setup and Erase Confirm commands from  
the CUI, the WSM controls block-erase. Progress is  
monitored via the device’s status register, the card’s  
data and address latches, as well as system soft-  
ware requests for status while the WSM is operating.  
The CUI itself does not occupy an addressable  
memory location. The CUI provides a latch used to  
store the command and address and data informa-  
tion needed to execute the command. Erase Setup  
and Erase Confirm commands require both appropri-  
ate command data and an address within the block  
to be erased. The Data Write Setup command re-  
quires both appropriate command data and the ad-  
dress of the location to be written, while the Data  
Write command consists of the data to be written  
and the address of the location to be written.  
Ý
control logic, and the RDY/BSY  
pin of the  
PCMCIA interface. Data-write is similarly controlled,  
after destination address and expected data are  
supplied.  
Table 4. Device Command Set  
First Bus Ccyle  
Second Bus Cycle  
Data  
x8 Mode x16 Mode  
Bus  
(1)  
28F008SA Command  
Cycles  
Req’d  
Data  
(2)  
Operation Addr  
(2)  
Operation Addr  
x8 Mode x16 Mode  
Read Array/Reset  
Intelligent Identifer  
1
3
2
1
2
2
Write  
Write  
Write  
Write  
Write  
Write  
DA  
DA  
DA  
DA  
BA  
DA  
FFH  
90H  
70H  
50H  
20H  
B0H  
FFFFH  
9090H  
7070H  
5050H  
2020H  
B0B0H  
(3)  
IID  
(3)  
IID  
Read  
Read  
IA  
(4)  
SRD  
(4)  
SRD  
Read Device Status Register  
Clear Device Status Register  
Erase Setup/Erase Confirm  
DA  
Write  
Write  
BA  
DA  
D0H  
D0H  
D0D0H  
D0D0H  
Erase Suspend/  
Erase Resume  
(5)  
(5)  
Write Setup/Write  
2
2
Write  
Write  
WA  
WA  
40H  
10H  
4040H  
1010H  
Write  
Write  
WA  
WA  
WD  
WD  
(6)  
(5)  
WD  
(5)  
WD  
Alternate Write Setup/Write  
NOTES:  
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be  
used.  
e
e
2. DA  
BA  
A device-level (or device pair) address within the card.  
Address within the block of a specific device (device pair) being erased.  
e
WA Address of memory location to be written.  
e
3. Following the intelligent identifier command, two read operations access manufacturer (89H) and device codes (A2H).  
IA  
A device-level address; 00H for manufacturer code, 01 for device code.  
e
4. SRD  
Data read from Device Status Register.  
e
Ý
5. WD Data to be written at location WA. Data is latched on the rising edge of WE .  
6. Either 40H or 10H are recognized by the WSM as the Write Setup command.  
16  
SERIES 2 FLASH MEMORY CARDS  
matically return status register data. Upon comple-  
tion of that operation, the device remains in the  
Status Register read mode until the CUI receives  
another command.  
COMMAND DEFINITIONS  
Read Array (FFH) Ð  
Upon initial card power-up, after exit from the Deep-  
Sleep modes, and whenever illegal commands are  
given, individual devices default to the Read Array  
mode. This mode is also entered by writing FFH into  
the CUI. In this mode, microprocessor read cycles  
retrieve array data. Devices remain enabled for  
reads until the CUI receives an alternate command.  
Once the internal WSM has started a block-erase or  
data-write operation within a device, that device will  
not recognize the Read Array command until the  
WSM has completed its operation (or the Erase Sus-  
pend command is issued during erase).  
The read Status Register command functions when  
e
V
V
PPL  
or V  
.
PPH  
PP  
Clear Status Register (50H)  
The Erase Status and Write Status bits may be set  
to ‘‘1’’s by the WSM and can only be reset by the  
Clear Status Register Command. These bits indicate  
various failure conditions. By allowing system soft-  
ware to control the resetting of these bits, several  
operations may be performed (such as cumulatively  
writing several bytes or erasing multiple blocks in  
sequence). The device’s Status Register may then  
be polled to determine if an error occurred during  
that sequence. This adds flexibility to the way the  
device may be used.  
Intelligent Identifier (90H) Ð  
After executing this command, the intelligent identifi-  
er values can be read. Only address A of each de-  
0
vice is used in this mode, all other address inputs  
Additionally, the V Status bit (SR.3) MUST be re-  
PP  
[
are reserved and should be cleared to 0. (Manufac-  
turer code  
set by system software (Clear Status Register com-  
mand) before further block-erases are attempted  
(after an error).  
e
e
e
1) . The device will remain in this mode  
89H for A  
0), (Device code  
A2H  
0
e
until the CUI receives another command.  
]
for A  
0
The Clear Status Register command functions when  
e
in the Read Array mode.  
This information is useful by system software in de-  
termining what type of flash memory device is con-  
tained within the card and allows the correct match-  
ing of device to write and erase algorithms. System  
software that fully utilizes the PCMCIA specification  
will not use the intelligent identifier mode, as this  
data is available within the Card Information Struc-  
ture (refer to section on PCMCIA Card Information  
Structure).  
V
PP  
V
PPL  
or V  
. This command puts the device  
PPH  
Write Setup/Write  
A two-command sequence executes a data-write  
,
operation. After the system switches V to V  
PP  
PPH  
the write setup command (40H) is written to the CUI  
of the appropriate device, followed by a second  
write specifying the address and write data (latched  
Ý
on the rising edge of WE ). The device’s WSM con-  
Read Status Register (70H)  
trols the data-write and write verify algorithms inter-  
nally. After receiving the two-command write se-  
quence, the device automatically outputs Status  
Register data when read (see Figure 13). The CPU  
detects the completion of the write operation by an-  
alyzing card-level or device-level indicators. Card-  
After writing this command, a device read outputs  
the contents of its Status Register, regardless of the  
address presented to that device. The contents of  
Ý
this register are latched on the falling edge of OE  
,
Ý
Ý
(and/or CE ), whichever occurs last in the  
2
CE  
1
Ý
read cycle. This prevents possible bus errors which  
might occur if the contents of the Status Register  
level indicators include the RDY/BSY pin and the  
READY-BUSY STATUS REGISTER; while device-  
level indicators include the specific device’s Status  
Register. Only the Read Status Register command  
is valid while the write operation is active. Upon  
completion of the data-write sequence (see section  
on Status Register) the device’s Status Register re-  
flects the result of the write operation. The device  
remains in the Read Status Register mode until the  
CUI receives an alternate command.  
Ý
for odd-byte or word access) or OE must be  
changed while reading its contents. CE  
Ý
(and  
1
Ý
CE  
2
toggled with each subsequent status read, or the  
completion of a write or erase operation will not be  
evident. This command is executable while the  
WSM is operating, however, during a block-erase or  
data-write operation, reads from the device will auto-  
17  
SERIES 2 FLASH MEMORY CARDS  
Erase Setup/Erase Confirm  
Commands (20H)  
Erase Suspend (B0H)/Erase Resume  
(D0H)  
Within a device, a two-command sequence initiates  
an erase operation on one device block at a time.  
Erase Suspend allows block erase interruption to  
read data from another block of the device or to  
temporarily conserve power for another system op-  
eration. Once the erase process starts, writing the  
Erase Suspend command to the CUI (see Figure 15)  
requests the WSM to suspend the erase sequence  
at a predetermined point in the erase algorithm. In  
the erase suspend state, the device continues to  
output Status Register data when read.  
After the system switches V  
to V , an Erase  
PPH  
PP  
Setup command (20H) prepares the CUI for the  
Erase Confirm command (D0H). The device’s WSM  
controls the erase algorithms internally. After receiv-  
ing the two-command erase sequence, the device  
automatically outputs Status Register data when  
read (see Figure 14). If the command after erase  
setup is not an Erase Confirm command, the CR  
sets the Write Failure and Erase Failure bits of the  
Status Register, places the device into the Read  
Status Register mode, and waits for another com-  
mand. The Erase Confirm command enables the  
WSM for erase (simultaneously closing the address  
Ý
Polling the device’s RY/BY and Erase Suspend  
Status bits (Status Register) will determine when the  
erase suspend mode is valid. It is important to note  
Ý
that the card’s RDY/BSY pin will also transition to  
and will generate an interrupt if this pin is con-  
V
OH  
latches for that device’s block (A –A ). The CPU  
19  
nected to a system-level interrupt. At this point, a  
Read Array command can be written to the device’s  
CUI to read data from blocks other than those  
which are suspended. The only other valid com-  
mands at this time are Read Status Register (70H)  
16  
detects the completion of the erase operation by an-  
alyzing card-level or device-level indicators. Card-  
level indicators include the RDY/BSY pin and the  
READY-BUSY STATUS REGISTER; while device-  
level indicators include the specific device’s Status  
Register. Only the Read Status Register and Erase  
Suspend command is valid during an active erase  
operation. Upon completion of the erase sequence  
(see section on Status Register) the device’s Status  
Register reflects the result of the erase operation.  
The device remains in the Read Status Register  
mode until the CUI receives an alternate command.  
and Erase Resume (D0H). If V  
Erase Suspend, the V  
goes low during  
Status bit is set in the  
PP  
PP  
Status Register and the erase operation is aborted.  
The Erase Resume command clears the Erase Sus-  
pend state and allows the WSM to continue with the  
Ý
erase operation. The device’s RY/BY Status and  
Erase Suspend Status bits and the card’s READY-  
BUSY Status Register are automatically updated to  
reflect the erase resume condition. The card’s RDY/  
The two-step block-erase sequence ensures that  
memory contents are not accidentally erased. Erase  
Ý
BSY pin also returns to V  
.
OL  
k
k
ous results and are not recommended. Reliable  
attempts while V  
V
PP  
V
produce spuri-  
PPL  
PPH  
e
absence of this voltage, memory contents are pro-  
block erasure only occurs when V  
V
. In the  
Invalid/Reserved  
PP  
PPH  
These are unassigned commands having the same  
effect as the Read Array command. Do not issue  
any command other than the valid commands speci-  
fied above. Intel reserves the right to redefine these  
codes for future functions.  
tected against erasure. If block erase is attempted  
e
while V  
‘‘1’’.  
V
, the V Status bit will be set to  
PPL PP  
PP  
When erase completes, the Erase Status bit should  
be checked. If an erase error is detected, the de-  
vice’s Status Register should be cleared. The CUI  
remains in Read Status Register mode until receiv-  
ing an alternate command.  
18  
SERIES 2 FLASH MEMORY CARDS  
DEVICE STATUS REGISTER  
Bit 5ÐErase Status  
Each 28F008SA device in the Series 2 Card con-  
tains a Status Register which displays the condition  
of its Write State Machine. The Status Register is  
read at any time by writing the Read Status com-  
mand to the CUI. After writing this command, all sub-  
sequent Read operations output data from the  
Status Register, until another command is written to  
the CUI.  
This bit will be cleared to 0 to indicate a successful  
block-erasure. When set to a ‘‘1’’, the WSM has  
been unsuccessful at performing an erase verifica-  
tion. The device’s CUI only resets this bit to a ‘‘0’’ in  
response to a Clear Status Register command.  
Bit 4ÐWrite Status  
This bit will be cleared to a 0 to indicate a successful  
data-write operation. When the WSM fails to write  
data after receiving a write command, the bit is set  
to a ‘‘1’’ and can only be reset by the CUI in re-  
sponse to a Clear Status Register command.  
Bit 7ÐWSM Status  
This bit reflects the Ready/Busy condition of the  
WSM. A ‘‘1’’ indicates that read, block-erase or  
data- write operations are available. A ‘‘0’’ indicates  
that write or erase operations are in progress.  
Bit 3ÐV Status  
PP  
During block-erase and data-write operations, the  
WSM monitors the output of the device’s internal  
Bit 6ÐErase Suspend Status  
If an Erase Suspend command is issued during the  
erase operation, the WSM halts execution and sets  
the WSM Status bit and the Erase Suspend Status  
bit to a ‘‘1’’. This bit remains set until the device  
receives an Erase Resume command, at which point  
the CUI resets the WSM Status bit and the Erase  
Suspend Status bit.  
V
detector. In the event of low V , the WSM sets  
PP PP  
(‘‘1’’) the V Status bit, the status bit for the opera-  
PP  
tion in progress (either write or erase). The CUI re-  
sets these bits in response to a Clear Status Regis-  
ter command. Also, the WSM RY/BY bit will be set  
to indicate a device ready condition. This bit MUST  
be reset by system software (Clear Status Register  
command) before further data writes or block erases  
are attempted.  
Ý
Device Status Register (Read Only Register)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
WSM  
Status  
Erase  
Suspend  
Status  
Erase  
Status  
Write  
Status  
V
PP  
Status  
Reserved  
19  
SERIES 2 FLASH MEMORY CARDS  
Bus  
Command  
x8 Mode  
x16 Mode  
Operation  
e
e
e
4040H  
Write  
Write  
Write Setup  
Data  
Address  
40H  
Data  
Address  
e
Byte  
Word  
Within Card to be  
Written  
Data Write Data to be Written  
Within Card to be  
Written  
Data to be Written  
e
e
Word  
Address  
Byte  
Address  
Within Card to be  
Written  
Within Card to be  
Written  
Read  
Defaults to Status Register  
Device Sta- Data. Toggle OE  
Status Register  
Ý
, Data. Toggle OE or  
Ý
Ý
Ý
Ý
Ý
and CE  
2
tus Register CE  
Read Mode  
or CE  
to  
(CE  
)
1
2
1
update Status  
Register  
to update Status  
Registers  
Standby  
Check SR Bit 7  
e
Check SR Bits  
7 and 15  
1
Ready,  
Busy  
e
e
Ready,  
0
1
e
0
Busy  
290434–17  
FULL STATUS CHECK  
PROCEDURE  
Bus  
Command  
x8 Mode  
x16 Mode  
Operation  
Standby  
Check SR Bit 3  
e
Check SR Bits  
3 and 11  
1
V
Detected  
PP  
Low  
e
1
V Detected  
PP  
Low  
Standby  
Check SR Bit 4  
Data Write Error  
Check SR Bits  
4 and 12  
e
1
e
1
Data Write Error  
290434–18  
Figure 13. Device-Level Automated Write Algorithm  
NOTES:  
1. Repeat for subsequent data writes.  
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSY pin may be used.  
Ý
3. Full device-level status check can be done after each data write or after a sequence of data writes.  
4. Write FFH (or FFFFH) after the last data write operation to reset the device(s) to Read Array Mode.  
5. If a data write operation fails due to a low V (setting SR Bit 3), the Clear Status Register command MUST be issued  
PP  
before further attempts are allowed by the Write State Machine.  
6. If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be cleared until the  
Command User Interface receives the Clear Status Register command.  
20  
SERIES 2 FLASH MEMORY CARDS  
Bus  
Command  
x8 Mode  
x16 Mode  
Operation  
e
e
e
e
Write  
Erase  
Setup  
Data  
Address  
20H Data  
Block Address  
2020H  
Block Pair  
Within Card to be  
Erased  
Within Card to be  
Erased  
e
e
e
D0D0H  
Write  
Read  
Erase  
Data  
Address  
D0H  
Data  
Address  
e
Block  
Block  
Within Card to be  
Erased  
Pair Within Card to  
be Erased  
Defaults to Status Register  
Device Sta- Data. Toggle OE  
Status Register  
Ý
Data. Toggle OE or  
Ý
,
Ý
Ý
Ý
Ý
and CE )  
2
tus Register CE  
Read Mode  
or CE  
to  
(CE  
1
2
1
update Status  
Register  
to update Status  
Register  
Standby  
Check SR Bit 7 Check SR Bits 7 and 15  
e
Ready,  
e
1
Ready,  
Busy  
1
e
e
0
0
Busy  
290434–19  
FULL STATUS CHECK PROCEDURE  
Bus  
Command  
x8 Mode  
x16 Mode  
Operation  
Standby  
Check SR Bit 3  
e
Check SR Bits  
3 and 11  
1
V
Detected  
PP  
Low  
e
Detected Low  
Either Bit 1  
V
PP  
Standby  
Check SR Bits 4 and 5 Check SR Bits 4, 5,  
12, 13  
e
Sequence Error  
Both 1  
Command  
e
All 1 Command  
Sequence Error  
Standby  
Check SR Bit 5  
e
Check SR Bits  
5 and 13  
1
Block Erase  
Error  
e
Erase Failure  
Both 1  
Block  
290434–20  
Figure 14. Device-Level Automated Erase Algorithm  
NOTES:  
1. Repeat for subsequent data writes.  
Ý
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSY pin may be used.  
3. Full device-level status check can be done after each block erase or after a sequence of block erases.  
4. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.  
5. If a block erase operation fails due to a low V (setting SR Bit 3), the Clear Status Register command MUST be issued  
PP  
before further attempts are allowed by the Write State Machine.  
6. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the  
Command User Interface receives the Clear Status Register command.  
21  
SERIES 2 FLASH MEMORY CARDS  
Bus  
Command  
x8 Mode  
x16 Mode  
Operation  
e
e
e
B0B0H,  
Write  
Suspend  
Erase  
Data  
Address  
B0H,  
Desired  
Data  
Address  
e
Desired  
Block to Erase  
Suspend  
Block Pair to Erase  
Suspend  
Read  
Status Register  
Data. Toggle OE  
Status Register  
Ý
Data. Toggle OE or  
Ý
,
Ý
Ý
Ý
Ý
and CE )  
2
CE  
or CE  
to  
(CE  
1
1
2
update Status  
Register  
to update Status  
Register  
Standby  
Check SR Bit 7  
e
Check SR Bit 7 and 15  
e
Ready,  
1
Ready,  
Busy  
1
e
e
0
0
Busy  
Standby  
Write  
Check SR Bit 6  
Check SR Bit 6 and 14  
e
e
e
e
1
0
Suspended,  
In Progress  
1
0
Suspended,  
In Progress  
e
e
FFFFH  
Rd Array  
Cmd  
Data  
FFH  
Data  
Read  
Write  
Read Data  
until finished  
Read Data  
until finished  
e
e
D0D0H,  
Erase  
Resume  
Data  
Address  
Block Address.  
D0H,  
Data  
Address  
Block Pair Address.  
e
e
Valid  
Valid  
290434–27  
Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases.  
SLEEP MODE  
POWER CONSUMPTION  
Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL  
POWERDOWN REGISTER places all FlashFile  
Memory devices into a Deep-Sleep mode. This dis-  
ables most of the 28F008SA’s circuitry and reduces  
current consumption to 0.2 mA per device. Addition-  
ally, when the host system pulls ASIC control logic  
high and latches all address and data lines (i.e., not  
toggling), the card’s total current draw is reduced to  
approximately 5 mA (CMOS input levels) for a 20  
Megabyte card. On writing a ‘‘0’’ to the PWRDWN bit  
(Global PowerDown Register) or any individual de-  
vice pair (Sleep Control Register), a Deep-Sleep  
mode recovery period must be allowed for  
28F008SA device circuitry to power back on.  
STANDBY MODE  
In most applications, software will only be accessing  
one device pair at a time. The Series 2 Card is de-  
fined to be in the standby mode when one device  
pair is in the Read Array Mode while the remaining  
devices are in the Deep-Sleep Mode. The Series 2  
Ý
Ý
input signals must also be  
at V . In standby mode, much of the card’s circuitry  
Card’s CE  
and CE  
1
2
IH  
is shut off, substantially reducing power consump-  
tion. Typical power consumption for a 20 Megabyte  
Series 2 card in standby mode is 65 mA.  
22  
SERIES 2 FLASH MEMORY CARDS  
While these precautions are sufficient for most appli-  
cations, an alternative approach would allow V to  
SYSTEM DESIGN CONSIDERATIONS  
CC  
reach its steady state value before raising V  
/
PP1  
2.0V. In addition, upon power-  
POWER SUPPLY DECOUPLING  
a
V above V  
PP2  
ing-down, V  
before lowering V  
CC  
a
2.0V,  
/V  
PP1 PP2  
should be below V  
CC  
Flash memory power-switching characteristics re-  
quire careful device decoupling. System designers  
are interested in three supply current issuesÐstand-  
by, active and transient current peaks, produced by  
.
CC  
HOT INSERTION/REMOVAL  
Ý
Ý
and CE . The  
2
rising and falling edges of CE  
1
capacitive and inductive loads on the card and inter-  
nal flash memory device pairs determine the magni-  
tudes of these peaks.  
The capability to remove or insert PC cards while the  
system is powered on (i.e., hot insertion/removal)  
requires careful design approaches on the system  
and card levels. To design for this capability consid-  
er card overvoltage stress, system power droop and  
control line stability.  
The Flash Memory Card features on-card ceramic  
decoupling capacitors connected between V and  
CC  
and GND to help  
GND, and between V /V  
PP1 PP2  
transient voltage peaks.  
A
PCMCIA/JEIDA specified socket properly se-  
quences the power supplies to the flash memory  
card via shorter and longer pins. This assures that  
hot insertion and removal will not result in card dam-  
age or data loss.  
On the host side, the card connector should also  
have a 4.7 mF electrolytic capacitor between V  
CC  
and GND.  
and GND, as well as between V /V  
PP1 PP2  
The bulk capacitors will overcome voltage slumps  
caused by printed-circuit-board trace inductance,  
and will supply charge to the smaller capacitors as  
needed.  
PCMCIA CARD INFORMATION  
STRUCTURE  
The Card Information Structure (CIS) starts at ad-  
dress zero of the card’s Attribute Memory Plane. It  
contains a variable-length chain of data blocks (tu-  
ples) that conform to a basic format as shown in  
Table 5. This section describes each tuple contained  
within the Series 2 Flash Memory Card.  
POWER UP/DOWN PROTECTION  
Each device in the Flash Memory Card is designed  
to offer protection against accidental erasure or writ-  
ing, caused by spurious system-level signals that  
may exist during power transitions. The card will  
power-up into the Read Array Mode.  
The Device Information Tuple  
A system designer must guard against active writes  
when V is active.  
(and/or CE ) must be  
for V voltages above V  
Since both WE and CE  
CC  
LKO  
Ý
PP  
e
This tuple (CISTPL DEV  
01H) contains informa-  
Ð
Ý
Ý
2
low for a command write, driving either to V will  
1
tion pertaining to the card’s speed and size. The Se-  
ries 2 Card is offered with a 150 nanosecond access  
time. Card sizes range between 2 and 20 Mega-  
bytes.  
IH  
inhibit writes. With its Command User Interface, al-  
teration of device contents only occurs after suc-  
cessful completion of the two-step command se-  
quences.  
Table 5. Tuple Format  
Data  
Bytes  
0
1
Tuple Code: CISTPL xxx. The tuple code 0FFH indicates no more tuples in the list.  
Ð
Tuple Link: TPL LlNK. Link to the next tuple in the list. This can be viewed as the number of  
Ð
additional bytes in tuple, excluding this byte. If the link field is zero, the tuple body is empty. If the  
link field contains 0FFH, this tuple is the last tuple in the list.  
b
2
n
Bytes specific to this tuple.  
23  
SERIES 2 FLASH MEMORY CARDS  
The Device Geometry Tuple  
Level 1 Version/Product  
Information Tuple  
e
ceptually similar to a DOS disk geometry tuple  
This tuple (CISTPL DEVlCEGEO  
Ð
1EH) is con-  
e
15H) contains Level-1-  
This tuple (CISTPL VERI  
Ð
(CISTPL GEOMETRY), except it is not a format-  
Ð
dependent property; this deals with the fixed archi-  
tecture of the memory device(s).  
version compliance and card-manufacturer informa-  
tion. Fields are described as follows:  
e
TPLLV1 MAJORÐMajor version number  
04H.  
Fields are defined as follows:  
e
TPLLV1 MINORÐMinor version number  
release 2.0.  
01H for  
e
DGTPL BUSÐValue  
b
(n 1)  
n, where system bus width  
2 for standard PCMClA Re-  
e
lease 1.0/2.0 cards.  
e
2
bytes. N  
TPLLV1 INFOÐ  
e
e
e
e
e
e
e
Name of manufacturer  
Name of product  
Card type  
intel;  
SERIES2-‘‘Card size’’;  
2;  
150 ns or 200 ns  
REGBASE 4000H  
DBBDRELP  
e
physical memory segments have a minimum erase  
DGTPL EBSÐValue  
n, where the memory array’s  
b
(n 1)  
block size of  
2
DGTPL BUS-wide accesses.  
address increments of  
Speed  
Register Base  
Test Codes  
Legalities  
Ð
e
ray’s physical memory segments have a minimum  
DGTPL RBSÐValue  
n, where the memory ar-  
COPYRIGHT intel  
Corporation 1991  
b
(n 1)  
read block size of 2  
DGTPL BUS-wide accesses.  
address increments of  
Ð
The Configurable Card Tuple  
e
ray’s physical memory segments have a minimum  
DGTPL WBSÐValue  
n, where the memory ar-  
e
This tuple (ClSTPL CONF  
1AH) describes the  
Ð
b
(n 1)  
write block size of 2  
DGTPL BUS-wide accesses.  
address increments of  
interface supported by the card and the locations of  
the Card Configuration Registers and the Card Con-  
figuration Table.  
Ð
e
ray’s physical memory segments can have partitions  
DGTPL PARTÐValue  
n, where the memory ar-  
Fields are described as follows:  
subdividing the arrays in minimum granularity of  
number of erase blocks.  
b
(n 1)  
e
01H.  
2
TPCC SZÐSize of fields byte  
e
FL DEVICE INTERLEAVEÐValue bn, where card  
TPCC LASTÐIndex number of the last entry in the  
e
00H.  
(n 1)  
architectures employ a multiple of 2  
times inter-  
leaving of the entire memory arrays with the above  
Card Configuration Table  
characteristics. Non-interleaved cards have values  
e
TPCC RADRÐConfiguration Registers Base Ad-  
e
4000H.  
n
1.  
dress in Reg Space  
TPCC RMSKÐConfiguration Registers Present  
e
Mask  
03H.  
Jedec Programming  
Information Tuple  
e
This tuple (CISTPL JEDEC  
Ð
18H) contains the  
The End-Of-List Tuple  
Intel manufacturing identifier (89H) and the  
28F008SA device ID (A2H).  
e
The end-of-list tuple (CISTPL END  
Ð
FFH) marks  
the end of a tuple chain. Upon encountering this tu-  
ple, continue tuple processing as if a long-link to ad-  
dress 0 of common memory space were encoun-  
tered.  
24  
SERIES 2 FLASH MEMORY CARDS  
Tuple  
Tuple  
Value  
Description  
Value  
Description  
Address  
Address  
00H  
02H  
04H  
01H  
03H  
53H  
CISTPL DEV  
Ð
32H  
34H  
36H  
38H  
3AH  
3CH  
3EH  
40H  
42H  
44H  
46H  
6CH  
00H  
53H  
45H  
52H  
49H  
45H  
53H  
32H  
2DH  
l
TPL LINK  
Ð
END TEXT  
e
DEVICE INFO  
Ð
FLASH 150 ns  
S
E
R
I
e
52H  
DEVICE INFO  
Ð
FLASH 200 ns  
CARD SIZE  
2M  
4M  
06H  
06H  
0EH  
26H  
4EH  
E
S
2
10M  
20M  
08H  
0AH  
FFH  
END OF  
DEVICE  
Ð
e
e
30H  
30H  
31H  
32H  
2M  
4M  
0
0
1EH  
CISTPL  
Ð
DEVICEGEO  
e
e
10M  
20M  
1
2
0CH  
0EH  
10H  
12H  
14H  
16H  
18H  
06H  
02H  
11H  
01H  
01H  
03H  
01H  
TPL LINK  
Ð
e
2
e
48H  
32H  
34H  
30H  
30H  
2M  
4M  
DGTPL BUS  
Ð
4
DGTPL EBS  
Ð
e
e
10M  
20M  
0
0
DGTPL RBS  
Ð
4AH  
4CH  
4EH  
50H  
20H  
00H  
32H  
SPACE  
DGPL WBS  
Ð
END TEXT  
DGTPL PART  
Ð
CARD TYPE 2  
FL DEVICE  
Ð
INTERLEAVE  
e
e
41H  
42H  
45H  
5AH  
48H  
49H  
4CH  
4FH  
A
B
2M, 150 ns  
4M, 150 ns  
10M, 150 ns  
20M, 150 ns  
2M, 200 ns  
4M, 200 ns  
10M, 200 ns  
20M, 200 ns  
1AH  
1CH  
1EH  
20H  
22H  
24H  
26H  
18H  
02H  
89H  
A2H  
15H  
50H  
04H  
CISTPL JEDEC  
Ð
e
e
E
TPL LINK  
Ð
Z
e
INTEL J-ID  
H
e
e
e
I
28F008 J-ID  
L
CISTPL VER1  
Ð
O
TPL LINK  
Ð
TPLLV1  
MAJOR  
28H  
2AH  
01H  
69H  
TPLLV1  
MINOR  
TPLLV1 INFO  
i
2CH  
2EH  
30H  
6EH  
74H  
65H  
n
t
e
25  
SERIES 2 FLASH MEMORY CARDS  
Tuple  
Tuple  
Value  
Description  
Value  
Description  
Address  
Address  
52H  
20H  
52H  
45H  
47H  
42H  
41H  
53H  
45H  
20H  
SPACE  
96H  
98H  
9AH  
9CH  
9EH  
69H  
6EH  
74H  
65H  
6CH  
20H  
i
54H  
REGBASE-R  
n
56H  
E
t
58H  
G
e
5AH  
5CH  
5EH  
60H  
B
l
A
A H  
0
SPACE  
S
E
CORPORATION  
C
A2H  
A4H  
A6H  
A8H  
AAH  
ACH  
AEH  
B0H  
B2H  
B4H  
B6H  
B8H  
BAH  
BCH  
BEH  
C0H  
C2H  
C4H  
C6H  
C8H  
CAH  
CCH  
CEH  
D0H  
D2H  
D4H  
D6H  
D8H  
43H  
4FH  
52H  
50H  
4FH  
52H  
41H  
54H  
49H  
4FH  
4EH  
20H  
31H  
39H  
39H  
31H  
00H  
FFH  
1AH  
06H  
01H  
00H  
00H  
40H  
03H  
FFH  
FFH  
00H  
O
62H  
SPACE  
R
4000h  
4
64H  
66H  
68H  
6AH  
6CH  
6EH  
70H  
72H  
74H  
76H  
78H  
7AH  
7CH  
7EH  
80H  
34H  
30H  
30H  
30H  
68H  
20H  
44H  
42H  
42H  
44H  
52H  
45H  
4CH  
50H  
00H  
P
0
O
0
R
0
A
h
T
SPACE  
I
D
O
B
N
B
SPACE  
D
1
R
9
E
9
L
P
1
END TEXT  
END OF LIST  
END TEXT  
COPYRIGHT  
C
CISTPL CONF  
Ð
82H  
84H  
86H  
88H  
8AH  
8CH  
8EH  
90H  
92H  
94H  
43H  
4FH  
50H  
59H  
52H  
49H  
47H  
48H  
54H  
20H  
TPL LINK  
Ð
O
TPCC SZ  
Ð
P
TPCC LAST  
Ð
Y
TPCC RADR  
Ð
R
TPCC RADR  
Ð
I
TPCC RMSK  
Ð
G
END OF LIST  
H
T
CISTPL END  
Ð
INVALID ECIS  
ADDRESS  
SPACE  
26  
SERIES 2 FLASH MEMORY CARDS  
OPERATING SPECIFICATlONS  
NOTICE: This data sheet contains preliminary infor-  
mation on new products in production. The specifica-  
tions are subject to change without notice. Verify with  
your local Intel Sales office that you have the latest  
data sheet before finalizing a design.  
ABSOLUTE MAXIMUM RATINGS*  
b
a
Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C  
§
§
Voltage on Any Pin with  
Respect to Ground ÀÀÀÀÀ 2.0V to V  
(1)  
a
2.0V  
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
CC  
V
/V  
PP1 PP2  
Respect to Ground ÀÀÀÀÀÀÀ 2.0V to 14.0V  
Supply Voltage with  
(1, 2)  
b
a
V
CC  
Supply Voltage with  
Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V  
b
a
NOTES:  
1. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V tor periods of less than 20 ns.  
b
b
a
a
Maximum DC voltage on output pins is V  
ns.  
0.5V. The voltage may overshoot to V  
2.0V for periods of less than 20  
CC  
CC  
a
may overshoot to 14.0V for periods of less than 20 ns.  
2. Maximum DC input voltage on V  
/V  
PP1 PP2  
COMMERCIAL TEMPERATURE OPERATING CONDITIONS  
These operating conditions apply to commercial temperature devices.  
Symbol  
Parameter  
Min  
0
Max  
70  
Unit  
T
A
Operating Temperature  
C
§
V
V
Supply Voltage (5%)  
CC  
4.75  
5.25  
V
CC  
EXTENDED TEMPERATURE OPERATING CONDITIONS  
These operating conditions apply to extended temperature devices.  
Symbol  
Parameter  
Min  
Max  
85  
Unit  
b
T
A
Operating Temperature  
40  
C
§
V
CC  
V
Supply Voltage (5%)  
CC  
4.75  
5.25  
V
CHARACTERISTICS  
All AC and DC characteristics apply to both commercial and extended temperature devices.  
COMMON DC CHARACTERISTICS, CMOS and TTL  
Symbol  
Parameter  
Notes  
Min  
Typ  
Max  
Unit  
Test Condition  
e
V
g
g
I
LI  
Input Leakage Current  
1, 3  
1
20  
mA  
V
V
V
Max  
CC  
or GND  
CC  
CC  
IN  
e
e
g
g
I
Output Leakage Current  
1
1
20  
mA  
V
V
V
Max  
CC  
LO  
CC  
OUT  
e
V
or GND  
CC  
b
V
V
Input Low Voltage  
1
1
0.5  
2.4  
0.7 V  
0.8  
V
V
IL  
a
a
Input High Voltage (TTL)  
Input High Voltage (CMOS)  
Output Low Voltage  
V
V
0.3  
0.3  
IH  
CC  
CC  
CC  
e
V
V
1
1
V
0.4  
V
V
V
V
3.2 mA  
Min  
CC  
OL  
SS  
CC  
e
I
OL  
e
Output High Voltage  
4.0  
V
CC  
V
I
V
e b  
Min  
CC  
2.0 mA  
OH  
CC  
OH  
V
PPL  
V
PPH  
V
LKO  
V
PP  
V
PP  
V
CC  
during Read Only Operations  
during Read/Write Operations  
Erase/Write Lock Voltage  
1, 2  
1
0.0  
11.4  
2.0  
6.5  
V
V
V
12.6  
1
NOTES:  
1. Values are the same for byte and word wide modes and for all card densities.  
e
Ý
2. Block Erases/Data Writes are inhibited when V  
e
V
and not guaranteed in the range between V  
s
and V  
.
PPL  
PP  
GND, the leakage on CE , CE , REG , OE , WE , will be  
PPL  
PPH  
Ý
Ý
Ý
Ý
3. Exceptions: With V  
IN  
resistors and, with V  
500 mA due to internal pullup  
1
2
s
e
V , RST leakage will be  
CC  
500 mA due to internal pulldown resistor.  
IN  
27  
SERIES 2 FLASH MEMORY CARDS  
DC CHARACTERISTICS, CMOS  
Byte Wide Mode  
Word Wide Mode  
Symbol  
Parameter  
Notes  
Unit Test Condition  
Min  
Typ  
Max  
Min  
Typ  
Max  
e
I
V
CC  
Read Current  
1, 3  
45  
85  
65  
120  
mA  
V
V
Max,  
CCR  
CC  
Control Signals  
CC  
e
GND  
e
200 ns,  
0 mA  
t
CYCLE  
e
I
OUT  
I
I
I
V
V
V
Write Current  
Erase Current  
Standby Current  
1, 3  
35  
35  
80  
80  
45  
45  
110  
110  
mA Data Write  
CCW  
CCE  
CCS  
CC  
CC  
CC  
in Progress  
1, 2, 3  
mA Block (Pair) Erase  
in Progress  
e
2 Meg  
4 Meg  
110  
160  
310  
560  
420  
620  
1220  
2200  
60  
110  
160  
310  
560  
420  
620  
1220  
2200  
60  
V
V
Max,  
CC  
Control Signals  
CC  
e
V
IH  
1, 4, 6  
mA  
mA  
10 Meg  
20 Meg  
2 Meg  
I
V Sleep Current  
CC  
CCSL  
4 Meg  
100  
260  
460  
15  
100  
260  
460  
30  
1, 4, 5  
10 Meg  
20 Meg  
I
I
I
V Write  
PP  
1, 3  
1, 3  
mA Data Write  
in Progress  
PPW  
PPE  
e
e
Current (V  
V
V
)
)
PP  
PPH  
V
Erase  
15  
30  
mA Block (Pair) Erase  
in Progress  
PP  
Current (V  
PP  
PPH  
V
PP  
Sleep Current  
2 Meg  
4 Meg  
0.2  
0.4  
1
10  
20  
0.2  
0.4  
1
10  
20  
PPSL  
1, 5  
1, 6  
1, 6  
mA  
mA  
mA  
10 Meg  
20 Meg  
2 Meg  
50  
50  
2
100  
20  
2
100  
20  
I
I
V
Standby or  
2.0  
2.2  
2.8  
3.8  
20  
2.0  
2.2  
2.8  
3.8  
20  
PPS1  
PPS2  
PP  
Read Current  
4 Meg  
30  
30  
s
(V  
V
CC  
)
PP  
10 Meg  
20 Meg  
2 Meg  
60  
60  
110  
400  
800  
2000  
4000  
110  
400  
800  
2000  
4000  
V
Standby or  
PP  
Read Current  
4 Meg  
40  
40  
l
(V  
V
CC  
)
PP  
10 Meg  
20 Meg  
100  
200  
100  
200  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at V  
e
e
PP  
) is 5 mA typical and 10 mA max with the device  
e
12.0V, T 25 C.  
5.0V, V  
§
CC  
2. The Data Sheet specification for the 28F008SA in Erase Suspend (I  
CCES  
deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of I  
3. Standby or Sleep currents are not included for non-accessed devices.  
and I  
.
CCR  
CCES  
4. Address and data inputs to card static. Control line voltages equal to V or V  
IH  
.
IL  
5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.  
6. In Byte and Word Mode, all but two devices in Deep-Sleep.  
28  
SERIES 2 FLASH MEMORY CARDS  
DC CHARACTERISTICS, TTL  
Symbol Parameter  
Byte Wide Mode  
Min Typ Max  
Word Wide Mode  
Notes  
Unit  
Test Condition  
Min  
Typ  
Max  
e
I
V
CC  
Read Current  
1, 3  
70  
135  
90  
170 mA  
V
V
Max,  
CC  
e
200 ns,  
CCR  
CC  
Control Signals  
GND  
e
0 mA  
t
CYCLE  
e
I
OUT  
I
I
I
V
V
V
Write Current  
Erase Current  
Standby Current  
1, 3  
60  
60  
130  
130  
70  
70  
160 mA Data Write  
in Progress  
CCW  
CCE  
CCS  
CC  
CC  
CC  
1, 2, 3  
160 mA Block (Pair) Erase  
in Progress  
e
2 Meg  
4 Meg  
V
V
Max,  
CC  
Control Signals  
CC  
e
100 mA  
V
IH  
1, 4, 6  
20  
20  
100  
100  
20  
20  
10 Meg  
20 Meg  
2 Meg  
I
V Sleep Current  
CC  
CCSL  
4 Meg  
1, 4, 5  
100 mA  
10 Meg  
20 Meg  
I
I
I
V
Write  
PP  
1, 3  
1, 3  
10  
10  
30  
30  
20  
20  
60  
60  
mA Data Write  
in Progress  
PPW  
PPE  
e
e
Current (V  
V
V
)
)
PP  
PPH  
V
Erase  
mA Block (Pair) Erase  
in Progress  
PP  
Current (V  
PP  
PPH  
V
PP  
Sleep Current  
2 Meg  
4 Meg  
0.2  
0.4  
1.0  
2.0  
2.0  
2.2  
2.8  
3.8  
20  
10  
20  
0.2  
0.4  
1.0  
2.0  
2.0  
2.2  
2.8  
3.8  
20  
10  
20  
PPSL  
1, 5  
1, 6  
1, 6  
mA  
mA  
mA  
10 Meg  
20 Meg  
2 Meg  
50  
50  
100  
20  
100  
20  
I
I
V
Standby or  
PPS1  
PPS2  
PP  
Read Current  
4 Meg  
30  
30  
s
(V  
PP  
V
CC  
)
10 Meg  
20 Meg  
2 Meg  
60  
60  
110  
400  
800  
110  
400  
800  
2000  
4000  
V
Standby or  
PP  
Read Current  
4 Meg  
40  
40  
l
(V  
PP  
V
CC  
)
10 Meg  
20 Meg  
100 2000  
200 4000  
100  
200  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at V  
e
e
PP  
) is 5 mA typical and 10 mA max with the device  
e
12.0V, T 25 C.  
5.0V, V  
§
CC  
2. The Data Sheet specification for the 28F008SA in Erase Suspend (I  
CCES  
deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of I  
3. Standby or Sleep currents are not included for non-accessed devices.  
and I  
.
CCR  
CCES  
4. Address and data inputs to card static. Control line voltages equal to V or V  
IH  
.
IL  
5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.  
6. In Byte and Word Mode, all but two devices in Deep-Sleep.  
7. The current consumption from the 28F008SA is insignificant in relation to the ASIC’s.  
29  
SERIES 2 FLASH MEMORY CARDS  
AC CHARACTERISTICS  
AC Timing Diagrams and characteristics are guaran-  
teed to meet or exceed PCMCIA Release 2.0 speci-  
fications. PCMCIA allows a 300 ns access time for  
Attribute Memory. Note that read and write access  
timings to the Series 2 Flash Memory Card’s Com-  
mon and Attribute Memory Planes are identical at  
150 ns. Furthermore, there is no delay in switching  
between the Common and Attribute Memory Planes.  
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Read-Only Operations  
Symbol  
Parameter  
Notes  
Min  
Max  
Unit  
JEDEC  
PCMCIA  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
AVAV  
AVQV  
ELQV  
GLQV  
EHQX  
GHQZ  
GLQX  
ELQX  
AXQX  
RHQV  
RC  
(A)  
Address Access Time  
150  
150  
75  
a
a
a
(CE)  
(OE)  
Card Enable Access Time  
Output Enable Access Time  
Output Disable Time from CE  
Output Disable Time from OE  
Ý
(CE)  
(CE)  
(CE)  
(OE)  
75  
dis  
dis  
en  
en  
Ý
75  
Ý
Output Enable Time from CE  
Output Enable Time from OE  
Data Valid from Add Change  
5
5
Ý
t (A)  
v
0
Reset-PwrDwn Recovery to Output Delay  
CE Setup Time on Power-Up  
First Access after Reset  
500  
1
t
(V  
su CC  
)
500  
290434–28  
e
Transient Input/Output Reference Waveform (V  
5.0V) for Standard Test Configuration  
CC  
290434–29  
e
Transient Input/Output Reference Waveform (V  
3.3V) for Standard Test Configuration  
CC  
30  
SERIES 2 FLASH MEMORY CARDS  
Figure 16. AC Waveform for Read Operations  
31  
SERIES 2 FLASH MEMORY CARDS  
(1)  
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Write Operations  
Symbol  
Parameter  
Notes  
Min  
Max  
Unit  
JEDEC  
PCMCIA  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
150  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
sec  
ns  
ns  
ms  
AVAV  
WC  
(WE)  
Write Pulse Width  
WLWH  
AVWL  
AVWH  
VPWH  
ELWH  
DVWH  
WHDX  
WHAX  
WHRL  
WHQV1  
WHQV2  
QVVL  
w
(A)  
Address Setup Time  
Address Setup Time for WE  
20  
su  
su  
Ý
(A-WEH)  
100  
100  
100  
50  
Ý
Setup to WE Going High  
V
vps  
PP  
Ý
Card Enable Setup Time for WE  
(CE-WEH)  
su  
su  
Ý
(D-WEH)  
Data Setup Time for WE  
Data Hold Time  
(D)  
20  
h
(WE)  
Write Recover Time  
20  
rec  
Ý
WE High to RDY/BSY  
Ý
120  
Duration of Data Write Operation  
Duration of Block Erase Operation  
6
0.3  
0
V
Hold from Operation Complete  
2
PP  
t
(OE-WE)  
h
Write Recovery before Read  
Reset-PwrDwn Recovery to WE Going Low  
10  
1
WHGL  
RHWL  
Ý
NOTES:  
1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to  
AC Characteristics for Read-Only operations.  
2. Refer to text on Data-Write and Block-Erase Operations.  
BLOCK ERASE AND DATA WRITE PERFORMANCE  
(3)  
Parameter  
Notes Min Typ  
Max Unit  
10 sec  
2.1 sec  
(1)  
Block Pair Erase Time  
Block Pair Write Time  
2, 4  
2, 4  
4
1.1  
0.5  
Byte/Word Write Time  
4.8 ms 6 ms 3 ms  
NOTES:  
1. Individual blocks can be erased 100,000 times.  
2. Excludes System-Level Overhead.  
3. 25 C, 12.0 V  
§
.
PP  
4. Monitor Ready/Busy Registers for the completion of a write/erase command.  
32  
SERIES 2 FLASH MEMORY CARDS  
Figure 17. AC Waveform for Write Operations  
33  
SERIES 2 FLASH MEMORY CARDS  
(1)  
Ý
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CE -Controlled Write Operations  
Symbol  
Parameter  
Write Cycle Time  
Notes  
Min  
Max  
Unit  
JEDEC  
PCMCIA  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
150  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
AVAV  
ELEH  
AVEL  
AVEH  
VPEH  
WLEH  
DVEH  
EHDX  
EHAX  
EHRL  
EHQV1  
WC  
(WE)  
Chip Enable Pulse Width  
Address Setup Time  
w
(A)  
20  
su  
su  
Ý
(A-WEH)  
Address Setup Time for CE  
100  
100  
100  
50  
Ý
Setup to CE Going High  
V
PP  
vps  
Ý
Write Enable Setup Time for CE  
(CE-WEH)  
su  
su  
Ý
(D-WEH)  
Data Setup Time for CE  
Data Hold Time  
(D)  
20  
h
(WE)  
Write Recover Time  
20  
rec  
Ý
CE High to RDY/BSY  
Ý
120  
Duration of  
Data Write  
Duration of Data Write Operation  
6
t
Duration of  
Erase  
Duration of Block Erase Operation  
1
0.3  
sec  
EHQV2  
t
t
t
V
Hold from Operation Complete  
1, 2  
1
0
10  
1
ns  
ns  
ms  
QVVL  
EHGL  
RHEL  
PP  
t
h
(OE-WE)  
Write Recovery before Read  
Reset-PwrDwn Recovery to CE Going Low  
Ý
NOTES:  
1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to  
AC Characteristics for Read-Only operations.  
2. Refer to text on Data-Write and Block-Erase Operations.  
34  
SERIES 2 FLASH MEMORY CARDS  
Figure 18. Alternate AC Waveform for Write Operations  
35  
SERIES 2 FLASH MEMORY CARDS  
290434–24  
Figure 19. Series 2 Flash Memory Card Package Dimensions  
36  
SERIES 2 FLASH MEMORY CARDS  
290434–25  
Figure 20. Card Connector Socket  
290434–26  
L1 MAX  
L2  
L3 REF  
0.020  
(0.5)  
Pin TypeÐSee Table 1  
g
0.024  
(0.6)  
Detect 0.059 (1.5) 0.039  
g
General 0.084 (2.1) 0.064  
g
0.098 (2.5) 0.078  
Power  
Figure 21. Pin/Socket Contact Length with Wipe  
37  
SERIES 2 FLASH MEMORY CARDS  
Label Dimensions  
290434–30  
NOTES:  
Total label dimensions are 0.003  
g
Total label thickness with adhesive is 0.002  
×
×
Card Dimensions with Label  
290434–31  
Figure 22. Label Information  
38  
SERIES 2 FLASH MEMORY CARDS  
e
e
1.0 MHz  
Table 5. Capacitance T  
25 C, f  
§
A
Commercial  
Min Max  
Symbol  
Characteristics  
Unit  
Ý
Address/Control Capacitance (A –A , CE , CE  
Ý
)
C
30  
20  
2
pF  
pF  
mF  
pF  
IN  
0
8
1
2
Address/Control Capacitance (A –A , all others)  
24  
9
V
, V  
CC PP  
C
OUT  
Output Capacitance  
20  
NOTE:  
Sampled, not 100% tested.  
ORDERING INFORMATION  
iMC020FLSA-15  
M9508014,SBXXXX  
WHERE:  
e
e
e
e
e
e
e
e
i
INTEL  
MEMORY CARD  
M
95  
08  
014  
SBXXXX  
MANILA  
1995  
WEEK 08  
MC  
020  
DENSITY IN MEGABYTES  
(002,004,010,020 AVAILABLE)  
FLASH TECHNOLOGY  
BLOCKED ARCHITECTURE  
SERIES 2  
Ý
LOT  
CUSTOMER IDENTIFIER  
e
e
e
e
e
FL  
S
A
-ET  
15  
EXTENDED TEMPERATURE  
150 ns  
ADDITIONAL INFORMATION  
28F008SA FlashFileTM Memory Data Sheet  
ORDER NUMBER  
290429  
292096  
AP-361 ‘‘Implementing the Integrated Registers of the Series 2 Flash Memory Card’’  
AP-364 ‘‘28F008SA Automation and Algorithms’’  
AP-359 ‘‘28F008SA Hardware Interfacing’’  
292099  
292094  
292095  
AP-360 ‘‘28F008SA Software Drivers’’  
AP-606 ‘‘Interchangeability of Series 1/2/2 Flash Memory Cards’’  
a
REVISION HISTORY  
Number  
Description  
02  
Added 150 ns TUPLE, Deleted 250 ns TUPLE  
Corrected Global Power Register Address to 4002H  
Corrected Write Protection Register Address to 4104H  
Corrected Ready-Busy Mode Register Address to 4140H  
I
Standby Byte Wide Mode MAX/TYP Increased  
Added Power-On Timing Spec  
CC  
Added First Access after Reset Spec  
Changed Advanced Information to Preliminary  
03  
Added 2 MByte card support  
Changed write timing waveforms to match PCMCIA  
Changed PowerDown (PWD) to Reset-PowerDown (RP)  
04  
05  
06  
Extended Operating Temperature Range  
Added Maximum Byte Write Time  
Added 150 ns Timings  
Change Cover Drawing to Accommodate Label  
Modified DC characteristics to reflect a conversion to new memory componentsÐthe 0.4m  
version of the 28F008SA. The new devices also have improved program and erase  
performance.  
39  

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