KC80524KX466128SL3KC

MOBILE INTEL^®CELERON^®PROCESSOR IN MICRO-PGA

AND BGA PACKAGES AT 466 MHZ, 433 MHZ, 400 MHZ,

366 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

+

Available at 266 MHz, 266 MHz at low

voltage, 300 MHz, 333 MHz, 366 MHz, 400

MHz, 433 MHz, and 466 MHz

+

Fully compatible with previous Intel

microprocessors

— Binary compatible with all

applications

+

Supports Intel Architecture with

Dynamic Execution

— Support for MMX™ technology

Integrated primary 16-Kbyte instruction

cache and 16-Kbyte write back data

cache

+

Power Management Features

— Quick Start and Deep Sleep modes

provide extremely low power

dissipation

+

Integrated second level cache (128-

Kbyte)

Low-Power GTL+ processor system bus

interface

Micro-PGA and BGA packaging

technology

— Supports thin form factor notebook

designs

+

Integrated math co-processor

Integrated thermal diode

— Exposed die enables more efficient

heat dissipation

The mobile IntelÒ CeleronÒ (Micro-PGA and BGA) processor provides exceptional value to both businesses

and consumers. The mobile Intel Celeron processor with multimedia enhancements and improved Internet

and communications capabilities not only provides an excellent solution for business but also a great choice

for home computing.

The mobile Intel Celeron (Micro-PGA and BGA) processor may contain design defects or errors know as

errata that may cause the product to deviate from published specifications. Current characterized errata are

available upon request.

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as

provided in Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims

any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Intel products are not intended for use in medical, life saving or life sustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.”

Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising

from future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before

placing your product order.

Mobile Intel® CeleronÒ (Micro-PGA and BGA) processors may contain design defects or errors known as errata, which may

cause the product to deviate from published specifications. Current characterized errata are available upon request.

Copies of documents that have an ordering number and are referenced in this document, or other Intel literature, may be

obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

the I²C bus/protocol and was developed by Intel. Implementations of the I²C bus/protocol or the SMBus bus/protocol may

require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

* Third party brands and names are the property of their respective owners.

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CONTENTS

PAGE

3.2.2 Voltage Planes.................................14

3.3 System Bus Clock and Processor Clocking15

3.4 Maximum Ratings ......................................16

3.5 DC Specifications......................................16

3.6 AC Specifications .....................................22

1. INTRODUCTION ................................................1

1.1 Overview ....................................................2

1.2 Terminology.................................................2

1.3 References .................................................2

3.6.1 System Bus, Clock, APIC, TAP,

CMOS, and Open-drain AC

2. MOBILE INTEL CELERON PROCESSOR

FEATURES.........................................................4

Specifications ..................................22

2.1 New Features in the Mobile Intel Celeron

Processor ...................................................4

4. SYSTEM SIGNAL SIMULATIONS ..................36

2.1.1 Integrated L2 Cache ..........................4

4.1 System Bus Clock (BCLK) Signal Quality

Specifications ...........................................36

2.1.2 Signal Differences from the Mini-

Cartridge Processors ........................4

4.2 Low Power GTL+ Signal Quality

2.2 Power Management....................................5

2.2.1 Clock Control Architecture.................5

2.2.2 Normal State ......................................5

2.2.3 Auto Halt State...................................5

2.2.4 Stop Grant State................................7

2.2.5 Quick Start State................................7

2.2.6 Halt/Grant Snoop State......................8

2.2.7 Sleep State ........................................8

2.2.8 Deep Sleep State...............................8

Specifications ...........................................37

4.3 Non-Low Power GTL+ Signal Quality

Specifications ...........................................38

4.3.1 Overshoot and Undershoot

Guidelines ........................................38

4.3.2 Ringback Specification ....................41

4.3.3 Settling Limit Guideline .....................41

5. MECHANICAL SPECIFICATIONS ..................42

5.1 Dimensions of the Micro-PGA Package ....42

5.2 Dimensions of the BGA Package.............45

5.3 Signal Listings ...........................................47

2.2.9 Operating System Implications of

Quick Start and Sleep States.............9

2.3 Low Power GTL+ .......................................9

2.3.1 GTL+ Signals .....................................9

2.4 Mobile Intel Celeron Processor CPUID.......10

6. THERMAL SPECIFICATIONS .........................60

6.1 Thermal Diode ...........................................61

6.2 Case Temperature ....................................63

3. ELECTRICAL SPECIFICATIONS ....................11

3.1 Processor System Signals........................11

3.1.1 Power Sequencing Requirements ...12

3.1.2 Test Access Port (TAP) Connection13

3.1.3 Catastrophic Thermal Protection......13

3.1.4 Unused Signals................................13

3.1.5 Signal State in Low Power States...13

3.2 Power Supply Requirements ....................14

3.2.1 Decoupling Recommendations.........14

7. PROCESSOR INITIALIZATION AND

CONFIGURATION............................................64

7.1 Description................................................64

7.1.1 Quick Start Enable ...........................64

7.1.2 System Bus Frequency...................64

7.1.3 APIC Disable ....................................64

7.2 Clock Frequencies and Ratios ..................64

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8. PROCESSOR INTERFACE...............................65

8.2 Signal Summaries......................................73

8.1 Alphabetical Signal Reference..................65

iv

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LIST OF FIGURES

PAGE

Figure 1.1 Signal Groups of a Mobile Intel Celeron

Processor-Based System......................1

Figure 2.1 Clock Control States ..............................6

Figure 3.1 Ramp Rate Requirement ......................13

Figure 3.2 PLL LC Filter.........................................14

Figure 3.3 Generic Clock Waveform.....................29

Figure 3.4 Valid Delay Timings..............................30

Figure 3.5 Setup and Hold Timings .......................30

Figure 3.6 Reset and Configuration Timings .........31

Figure 3.7 Power-on Reset Timings .....................32

Figure 3.8 Test Timings (Boundary Scan)............33

Figure 3.9 Test Reset Timings ..............................33

Figure 3.10 Quick Start/Deep Sleep Timing...........34

Figure 3.11 Stop Grant/Sleep/Deep Sleep Timing.35

Figure 4.1 BCLK Generic Clock Waveform...........37

Figure 4.2 Low to High, Low Power GTL+

Receiver Ringback Tolerance...............38

Figure 4.3 Non-GTL+ Overshoot/Undershoot and

Ringback...............................................40

Figure 5.1 Micro-PGA Package-Top and Side View 43

Figure 5.2 Micro-PGA Package-Bottom View .......44

Figure 5.3 Surface-mount BGA Package - Top and

Side View .............................................46

Figure 5.4 Surface-mount BGA Package - Bottom

View .....................................................47

Figure 5.5 Pin/Ball Map - Top View .......................48

Figure 6.1 Technique for Measuring Case

Temperature .........................................63

Figure 8.1 PWRGOOD Relationship at Power-On.71

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LIST OF TABLES

PAGE

Table 2.1 New Mobile Intel Celeron Processor

Signals ....................................................4

Table 2.2 Removed Mini-Cartridge Processor

Signals ....................................................4

Table 2.3 Clock State Characteristics.....................7

Table 2.4 Mobile Intel Celeron Processor CPUID...10

Table 2.5 Mobile Intel Celeron Processor CPUID

Cache and TLB Descriptors .................10

Table 3.1 System Signal Groups ..........................11

Table 3.2 Recommended Resistors for Open-drain

Signals ..................................................12

Table 3.3 LC Filter Specifications .........................14

Table 3.4 Core Frequency to System Bus Ratio

Configuration ........................................15

Table 3.5 Mobile Intel Celeron Processor Absolute

Maximum Ratings ..................................16

Table 3.6 Mobile Intel Celeron Processor Power

Specifications¹......................................18

Table 3.7 Mobile Intel Celeron Processor Power

Specifications¹......................................19

Table 3.8 Low Voltage Mobile Intel Celeron

Processor Power Specifications¹........20

Table 3.9 Low Power GTL+ Signal Group DC

Specifications .......................................21

Table 3.10. Low Power GTL+ Bus DC

Table 4.2 Low Power GTL+ Signal Group Ringback

Specification.........................................37

Table 4.3 Signal Ringback Specifications for Non-

GTL+ Signals ........................................41

Table 5.1 Micro-PGA Package Mechanical

Specifications .......................................42

Table 5.2 Surface-mount BGA Package

Specifications .......................................45

Table 5.3 Signal Listing in Order by Pin/Ball Number49

Table 5.4 Signal Listing in Order by Signal Name .55

Table 5.5 Voltage and No-Connect Pin/Ball

Locations ..............................................59

Table 6.1 Mobile Intel Celeron^®Processor Power

Specifications .......................................60

Table 6.2 Thermal Diode Interface........................61

Table 6.3. Thermal Diode Specifications...............61

Table 8.1 Input Signals..........................................73

Table 8.2 Output Signals.......................................74

Table 8.3 Input/Output Signals (Single Driver)......74

Table 8.4 Input/Output Signals (Multiple Driver)....75

Specifications .......................................21

Table 3.11 Clock, APIC, TAP, CMOS and Open-

Drain Signal Group DC Specifications ..22

Table 3.12 System Bus Clock AC Specifications¹23

Table 3.13 Valid Mobile Intel Celeron Processor

Frequencies..........................................24

Table 3.14 Low Power GTL+ Signal Groups AC

Specifications¹......................................24

Table 3.15 CMOS and Open-Drain Signal Groups

AC Specifications^{1, 2}.............................25

Table 3.16 Reset Configuration AC Specifications26

Table 3.17 TAP Signal AC Specifications¹............27

Table 3.18 Quick Start/Deep Sleep AC

Specifications .......................................28

Table 3.19 Stop Grant/Sleep/Deep Sleep AC

Specifications .......................................28

Table 4.1 BCLK Signal Quality Specifications.......36

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performance, it complements the system bus by

1.

INTRODUCTION

providing critical data faster and reducing total

system power consumption. The mobile Intel

Celeron processor’s 64-bit wide Low Power

Gunning Transceiver Logic (GTL+) system bus is

compatible with the 443BX/DX/440MX AGPSet and

provides a glue-less, point-to-point interface for an

I/O bridge/memory controller. Figure 1.1 shows the

various parts of a mobile Intel Celeron processor-

based system and how the mobile Intel Celeron

processor connects to them.

The mobile Intel Celeron processor is the first

mobile processor with an integrated L2 cache

among the mobile processors. The mobile Intel

Celeron processor is now offered at seven

speeds: 466 MHz, 433 MHz, 400 MHz, 366 MHz,

333 MHz, 300 MHz, and 266 MHz, with a system

bus speed of 66 MHz. It consists of a mobile Intel

Celeron processor with an integrated L2 cache and

a

64-bit high performance system bus. The

integrated L2 cache is designed to help improve

Thermal

Sensor

Mobile Celeron

Processor

ä

TAP

System

Bus

DRAM

440MX

PCIset

OR

System

V0000-04

Controller

X-bus

PCI

Figure 1.1 Signal Groups of a Mobile Intel Celeron Processor-Based System

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1.1 Overview

1.2

Terminology

•

Exceptional value and improved performance

over existing mobile processors

In this document a ‘#’ symbol following a signal

name indicates that the signal is active low. This

means that when the signal is asserted (based on

the name of the signal) it is in an electrical low

state. Otherwise, signals are driven in an electrical

high state when they are asserted. In state

machine diagrams, a signal name in a condition

indicates the condition of that signal being

asserted. If the signal name is preceded by a ‘!’

symbol, then it indicates the condition of that signal

not being asserted. For example, the condition

‘!STPCLK# and HS’ is equivalent to ‘the active low

signal STPCLK# is unasserted (i.e., it is at 2.5V)

and the HS condition is true.” The symbols ‘L’ and

‘H’ refer respectively to electrical low and electrical

high signal levels. The symbols ‘0’ and ‘1’ refer

respectively to logical low and logical high signal

levels. For example, BD[3:0] = ‘1010’ = ‘HLHL’ refers

to a hexadecimal ‘A’, and D[3:0]# = ‘1010’ = ‘LHLH’

also refers to a hexadecimal ‘A’.

•

Supports the Intel Architecture with

Dynamic Execution

Supports the Intel Architecture MMXÔ

technology

Integrated Intel Floating-Point Unit

compatible with the IEEE Std 754

•

Integrated primary (L1) instruction and data

caches

•

4-way set associative, 32-byte line size,

1 line per sector

16-Kbyte instruction cache and 16-Kbyte

writeback data cache

Cacheable range programmable by

processor programmable registers

•

Integrated second level (L2) cache

•

4-way set associative, 32-byte line size,

1 line per sector

1.3

References

•

Operates at full core speed

128-Kbyte, ECC protected cache data array

4-Gbyte cacheable range

Pentium^®II Processor at 233 MHz, 266 MHz, 300

MHz and 333 MHz (Order Number 243335)

Low Power GTL+ system bus interface

Pentium^®II Processor Developer’s Manual

(Order Number 243502)

•

64-bit data bus, 66-MHz operation

Uniprocessor, two loads only (processor

and I/O bridge/memory controller)

CKDM66-M Clock Driver Specification

•

Short trace length and low capacitance

allows for single ended termination

(Contact your Intel Field Sales Representative)

Intel Architecture Software Developer’s Manual

(Order Number 243193)

•

Voltage reduction technology

Advanced processor clock control

Volume I: Basic Architecture

(Order Number 243190)

Volume II: Instruction Set Reference

(Order Number 243191)

Volume III: System Programming Guide

(Order Number 243192)

•

Quick Start for low power, low exit latency

clock “throttling”

•

Deep Sleep mode for extremely low power

dissipation

•

Thermal diode for measuring processor

temperature

Mobile Intel^®Celeron^®Processor I/O Buffer

Models, IBIS Format (Available in electronic

format; contact your Intel Field Sales

Representative)

2

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Mobile Pentium^®II Processor System Bus Layout

Guideline (Order Number 243672-001)

Mobile Pentium^®II Processor Mechanical and

Thermal User’s Guide

(Order Number 243671-001)

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2.

MOBILE INTEL CELERON

PROCESSOR FEATURES

2.1.1

Integrated L2 Cache

The mobile Intel Celeron processor has a 128-Kbyte

L2 cache integrated onto the processor die. The L2

cache is four-way set associative and runs at the

speed of the processor core. The L2 cache can

cache up to 4 Gbytes of memory.

2.1 New Features in the Mobile Intel

Celeron Processor

New features include an integrated L2 cache and

various signal differences from the mini-cartridge

processors.

2.1.2

Signal Differences from the

Mini-Cartridge Processors

Table 2.1 New Mobile Intel Celeron Processor Signals

Purpose

Signals

EDGCTRLN

NC

GTL+ output buffer edge rate control signals

No Connect (same as RSVD signals on mini-cartridge)

Bus speed select

BSEL

TESTHI, TESTHI3

TESTHI2

Testability signals. Pull-up to V_CC

.

Testability signals. Pull-up to V_CCP

.

TESTLO

Testability signals. Connect to V_SS

Thermal diode

.

THERMDA, THERMDC

PLL1, PLL2

V_REF

PLL analog power supply

GTL+ reference voltage

Table 2.2 Removed Mini-Cartridge Processor Signals

Purpose

Signals

SMBALERT#, SMBCLK, SMBDATA

SMBus interface for the thermal sensor

Voltage sense signals

V_{CC_S}, V_{CCP_S}, V_{SS_S}

V_CC3

3.3V supply for external L2 cache components

Voltage identification

VID[3:0]

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2.2 Power Management

2.2.2

Normal State

The Normal state of the processor is the normal

operating mode where the processor’s internal

clock is running and the processor is actively

executing instructions.

2.2.1

Clock Control Architecture

The mobile Intel Celeron processor clock control

architecture (Figure 2.1) has been optimized for

leading edge deep green desktop and mobile

computer designs. The clock control architecture

consists of seven different clock states: Normal,

Stop Grant, Auto Halt, Quick Start, HALT/Grant

Snoop, Sleep, and Deep Sleep states. The Auto

Halt state provides a low -power clock state that

can be controlled through the software execution

of the HLT instruction. The Quick Start state

provides a very low power, low exit latency clock

state that can be used for hardware controlled

“idle” computer states. The Deep Sleep state

provides an extremely low -power state that can be

used for “Power-On Suspend” computer states,

which is an alternative to shutting off the

processor’s power. Compared to the Pentium

processor exit latency of 1 msec, the exit latency

of the Deep Sleep state has been reduced to 30

msec in the mobile Intel Celeron processor. The

Stop Grant and Sleep states shown are intended

for use in “Deep Green” desktop and server

systems — not in mobile systems. Performing state

transitions not shown in Figure 2.1 is neither

recommended nor supported.

2.2.3

Auto Halt State

low -power mode entered by the

This is

a

processor through the execution of the HLT

instruction. The power level of this mode is similar

to the Stop Grant state. A transition to the Normal

state is made by a halt break event (one of the

following signals going active: NMI, INTR, BINIT#,

INIT#, RESET#, FLUSH#, or SMI#).

Asserting the STPCLK# signal while in the Auto Halt

state will cause the processor to transition to the

Stop Grant or Quick Start state, where a Stop

Grant Acknowledge bus cycle will be issued.

Deasserting STPCLK# will cause the processor to

return to the Auto Halt state without issuing a new

Halt bus cycle.

The SMI# interrupt is recognized in the Auto Halt

state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal

state or the Auto Halt state. See the Intel

Architecture Software Developer’s Manual, Volume

III: System Programmer’s Guide for more

information. No Halt bus cycle is issued when

returning to the Auto Halt state from System

Management Mode (SMM).

The Stop Grant and Quick Start clock states are

mutually exclusive, for example a strapping option

on signal A15# chooses which state is entered

when the STPCLK# signal is asserted. Strapping

the A15# signal to ground at Reset enables the

Quick Start state; otherwise, asserting the

STPCLK# signal puts the processor into the Stop

Grant state. The Stop Grant state has a higher

power level than the Quick Start state and is

designed for SMP platforms. The Quick Start state

has a much lower power level, but it can only be

used in uniprocessor platforms.

The FLUSH# signal is serviced in the Auto Halt

state. After the on-chip and off-chip caches have

been flushed, the processor will return to the Auto

Halt state without issuing

a Halt bus cycle.

Transitions in the A20M# and PREQ# signals are

recognized while in the Auto Halt state.

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STPCLK# and

QSE and SGA

Normal

HS=false

Quick

Start

(!STPCLK# and !HS)

or RESET#

HLT and

halt bus cycle

STPCLK# and

QSE and SGA

BCLK

stopped

halt

break

!STPCLK#

and HS

BCLK on

and QSE

STPCLK# and

!QSE and SGA

Auto

Halt

HS=true

Snoop

serviced occurs

Snoop

Deep

Sleep

(!STPCLK#

and !HS) or

stop break

!STPCLK#

and HS

Snoop

occurs

STPCLK# and

!QSE and SGA

Snoop

serviced

occurs

Stop

Grant

HALT/Grant

Snoop

serviced

SLP#

BCLK on

and !QSE

BCLK

stopped

!SLP# or

RESET#

Sleep

V0001-00

NOTES: Halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#

HLT - HLT instruction executed

HS - Processor Halt State

QSE - Quick Start State Enabled

SGA - Stop Grant Acknowledge bus cycle issued

Stop break - BINIT#, RESET#

Figure 2.1 Clock Control States

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Table 2.3 Clock State Characteristics

Clock State

Normal

Exit Latency

Snooping?

Yes

System Uses

N/A

Normal program execution

S/W controlled entry idle mode

Auto Halt

Approximately 10 bus clocks

Yes

Stop Grant

Yes

H/W controlled entry/exit mobile

throttling

Quick Start

Through snoop, to HALT/Grant Snoop

state: immediate

H/W controlled entry/exit mobile

throttling

Yes

Through STPCLK#, to Normal state: 8

bus clocks

HALT/Grant

Snoop

A few bus clocks after the end of

snoop activity.

Yes

No

Supports snooping in the low

power states

Sleep

To Stop Grant state,

10 bus clocks

H/W controlled entry/exit desktop

idle mode support

Deep Sleep

30 µsec

No

H/W controlled entry/exit mobile

powered-on suspend support

assertion will cause the processor to immediately

initialize itself, but the processor will stay in the

Stop Grant state after initialization until STPCLK# is

deasserted. A transition to the Sleep state can be

made by the assertion of the SLP# signal.

2.2.4

Stop Grant State

The processor enters this mode with the assertion

of the STPCLK# signal when it is configured for

Stop Grant state (via the A15# strapping option).

The processor is still able to respond to snoop

requests and it can latch interrupts. Latched

interrupts will be serviced when the processor

returns to the Normal state. Only one occurrence of

each interrupt event will be latched. A transition

back to the Normal state can be made by the

deassertion of the STPCLK# signal or the

occurrence of a stop break event (a BINIT# or

RESET# assertion).

While in the Stop Grant state, assertions of

FLUSH#, SMI#, INIT#, INTR, and NMI will be latched

by the processor. These latched events will not be

serviced until the processor returns to the Normal

state. Only one of each event will be recognized

upon return to the Normal state.

2.2.5

Quick Start State

This is a mode entered by the processor with the

assertion of the STPCLK# signal when it is

configured for the Quick Start state (via the A15#

strapping option). In the Quick Start state the

The processor will return to the Stop Grant state

after the completion of a BINIT# bus initialization

unless STPCLK# has been deasserted. RESET#

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processor is only capable of acting on snoop

transactions generated by the system bus priority

device. Because of its snooping behavior, Quick

Start can only be used in a Uniprocessor (UP)

configuration.

2.2.7

Sleep State

The Sleep state is a very low -power state in which

the processor maintains its context and the phase-

locked loop (PLL) maintains phase lock. The Sleep

state can only be entered from the Stop Grant

state. After entering the Stop Grant state, the SLP#

signal can be asserted, causing the processor to

enter the Sleep state. The SLP# signal is not

recognized in the Normal or Auto Halt states.

A transition to the Deep Sleep state can be made

by stopping the clock input to the processor. A

transition back to the Normal state (from the Quick

Start state) is made only if the STPCLK# signal is

deasserted.

The processor can be reset by the RESET# signal

while in the Sleep state. If RESET# is driven active

while the processor is in the Sleep state then SLP#

and STPCLK# must immediately be driven inactive

to ensure that the processor correctly initializes

itself.

While in this state the processor is limited in its

ability to respond to input. It is incapable of latching

any interrupts, servicing snoop transactions from

symmetric bus masters or responding to FLUSH# or

BINIT# assertions. While the processor is in the

Quick Start state, it will not respond properly to any

input signal other than STPCLK#, RESET#, or BPRI#.

If any other input signal changes, then the behavior

of the processor will be unpredictable. No serial

interrupt messages may begin or be in progress

while the processor is in the Quick Start state.

Input signals (other than RESET#) may not change

while the processor is in the Sleep state or

transitioning into or out of the Sleep state. Input

signal changes at these times will cause

unpredictable behavior. Thus, the processor is

incapable of snooping or latching any events in the

Sleep state.

RESET# assertion will cause the processor to

immediately initialize itself, but the processor will

stay in the Quick Start state after initialization until

STPCLK# is deasserted.

While in the Sleep state, the processor can enter its

lowest power state, the Deep Sleep state.

Removing the processor’s input clock puts the

processor in the Deep Sleep state. PICCLK may be

removed in the Sleep state.

2.2.6

Halt/Grant Snoop State

The processor will respond to snoop transactions

on the system bus while in the Auto Halt, Stop

2.2.8

Deep Sleep State

Grant or Quick Start state. When

a snoop

transaction is presented on the system bus the

processor will enter the HALT/Grant Snoop state.

The processor will remain in this state until the

snoop has been serviced and the system bus is

quiet. After the snoop has been serviced, the

processor will return to its previous state. If the

HALT/Grant Snoop state is entered from the Quick

Start state, then the input signal restrictions of the

Quick Start state still apply in the HALT/Grant

Snoop state, except for those signal transitions that

are required to perform the snoop.

The Deep Sleep state is the lowest power mode

the processor can enter while maintaining its

context. The Deep Sleep state is entered by

stopping the BCLK input to the processor while it is

in the Sleep or Quick Start state. For proper

operation, the BCLK input should be stopped in the

low state.

The processor will return to the Sleep or Quick

Start state from the Deep Sleep state when the

BCLK input is restarted. Due to the PLL lock

latency, there is a 30-msec delay after the clocks

have started before this state transition happens.

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PICCLK may be removed in the Deep Sleep state.

derating. Analog signal simulation of the system

bus including trace lengths is highly recommended

to ensure that there are no significant transmission

line affects. Contact your field sales representative

to receive the IBIS models for the mobile Intel

Celeron processor.

PICCLK should be designed to turn on when BCLK

turns on when transitioning out of the Deep Sleep

state.

The input signal restrictions for the Deep Sleep

state are the same as for the Sleep state, except

that RESET# assertion will result in unpredictable

behavior.

The GTL+ system bus of the Pentium II processor

was designed to support high-speed data

transfers with multiple loads on a ol ng bus that

behaves like a transmission line. However, in a

mobile system, the system bus only has two loads

(the processor and the chipset) and the bus traces

are short enough that transmission line effects are

not significant. It is possible to change the layout

and termination of the system bus to take

advantage of the mobile environment using the

same GTL+ I/O buffers. The benefit is that it

reduces the number of terminating resistors in half

and substantially reduces the AC and DC power

dissipation of the system bus. Low Power GTL+

uses GTL+ I/O buffers but only two loads are

allowed. The trace length is limited and the bus is

terminated at one end only. Since the system bus is

small and lightly loaded, it behaves like a capacitor,

and the GTL+ I/O buffers behave like high-speed

open-drain buffers. With a 66-MHz bus frequency,

the pull-up would be 120W. V_TThas been

increased from 1.5V to processor V_CCto eliminate

2.2.9

Operating System Implications of

Quick Start and Sleep States

There are a number of architectural features of the

Mobile Intel Celeron processor that are not available

when the Quick Start state is enabled or do not

function in the Quick Start or Sleep state as they do

in the Stop Grant state. These features are part of

the APIC, time-stamp counter and performance

monitor counters. The time-stamp counter and the

performance monitor counters are not guaranteed

to count in the Quick Start or Sleep states.

2.3

Low Power GTL+

The mobile Intel Celeron processor system bus

signals use a variation of the low voltage swing

GTL signaling technology. The mobile Intel Celeron

processor system bus specification is similar to the

PentiumÒ II processor system bus specification,

which is itself a version of GTL with enhanced

noise margins and less ringing. The mobile Intel

Celeron processor system bus specification

reduces system cost and power consumption by

raising the termination voltage and termination

resistance and changing the termination from dual

ended to single ended. Because the specification is

different from the standard GTL specification and

from the Pentium II processor GTL+ specification, it

is referred to as Low Power GTL+.

the need for

a 1.5V power plane. If 100W

termination resistors are used rather than 120W,

then 20% more power will be dissipated in the

termination resistors. Intel recommends 120-W

termination to conserve power.

Refer to the Mobile Pentium^®II Processor System

Bus Layout Guideline (Order Number 243672-001)

for details on laying out the Low Power GTL+

system bus.

2.3.1

GTL+ Signals

The Pentium II processor GTL+ system bus

depends on incident wave switching and uses

flight time for timing calculations of the GTL+

signals. The Low Power GTL+ system bus is short

and lightly loaded. With Low Power GTL+ signals,

timing calculations are based on capacitive

Two signals of the system bus potentially may not

meet the Low Power GTL+ layout requirements:

PRDY# and RESET#. These two signals connect to

the debug port and might not meet the maximum

length requirements. If PRDY# or RESET# do not

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meet the layout requirements for Low Power GTL+,

then they must be terminated using dual-ended

termination at 120W. Higher resistor values can be

used if simulations show that the signal quality

specifications in Section 4 are met.

cache descriptor information. A mobile Intel Celeron

processor has a stepping number in the range of

0AH to 0CH and an L2 cache descriptor of 041H

(128-Kbyte L2 cache). If the L2 cache descriptor is

042H, then the processor is a Pentium II processor.

The L2 cache must be properly initialized for the L2

cache descriptor information to be correct. After a

power-on RESET or when the CPUID version

information is loaded, the EAX register contains the

values shown in Table 2.4. After the L2 cache is

initialized, the CPUID cache/TLB descriptors will be

the values shown in Table 2.5.

2.4

Mobile Intel Celeron Processor

CPUID

The mobile Intel Celeron processor has the same

CPUID family and model number as some Pentium II

processors. The mobile Intel Celeron processor can

be distinguished from these Pentium II processors

by looking at the stepping number and the CPUID

Table 2.4 Mobile Intel Celeron Processor CPUID

Reserved [31:14]

Type [13:12]

Family [11:8]

Model [7:4]

Stepping [3:0]

X

0

6

A - C

Table 2.5 Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors

Cache and TLB Descriptors 01H, 02H, 03H, 04H, 08H, 0CH, 41H

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All Low Power GTL+ signals are synchronous with

the BCLK signal. All TAP signals are synchronous

3.

ELECTRICAL SPECIFICATIONS

with the TCK signal except TRST#. All CMOS input

signals can be applied asynchronously.

3.1

Processor System Signals

Table 3.1 lists the processor system signals by

type.

Table 3.1 System Signal Groups

Group Name

Low Power GTL+ Input

Low Power GTL+ Output

Low Power GTL+ I/O

Signals

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#

PRDY#

A[35:3]#, ADS#, AERR#¹, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,

BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,

LOCK#, REQ[4:0]#, RP#

CMOS Input ^{2, 3}

A20M#, BSEL, FLUSH#, IGNNE#, INIT#, INTR, NMI, PREQ#, PWRGOOD, SLP#,

SMI#, STPCLK#

Open Drain Output ³

Clock ³

FERR#, IERR#

BCLK

APIC Clock ³

APIC I/O ³

PICCLK

PICD[1:0]

Thermal Diode

TAP Input ³

THERMDA, THERMDC

TCK, TDI, TMS, TRST#

TDO

TAP Output ³

Power/Other ⁴

EDGECTRLN, NC, PLL1, PLL2, TESTHI, TESTHI2, TESTHI3, TESTLO,

V_CC, V_CCP, V_REF, V_SS

NOTES:

1. The AERR# processor bus pin is removed as a processor feature for mobile Intel Celeron processor at

400MHz and above. The pin must still be terminated to Vcc through a 120W pull-up resistor. But the

processor must not be configured to drive or observe the pin.

2. See Section 8.1 for information on the PWRGOOD signal.

3. These signals are tolerant to 2.5V only. See Table 3.2 for the recommended pull-up resistor.

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4. V_CCis the power supply for the core logic; PLL1 and PLL2 are the power supply for the PLL analog

section; V_CCPis the power supply for the CMOS voltage references; V_REFis the voltage reference for

the Low Power GTL+ input buffers; V_SSis system ground.

Table 3.2 Recommended Resistors for Open-drain Signals

Recommended

Open-drain Signal ¹

Resistor Value (W )

150 pull-up

680 pull-up

TDI, TDO

STPCLK#

1K pull-up

INIT#, TCK, TESTHI, TESTHI2, TESTHI3, TMS

TRST#

680 - 1K pull-down

4.7K pull-up

A20M#, FERR#, FLUSH#, IERR#, IGNNE#, INTR, NMI, PREQ#, PWRGOOD,

SLP#, SMI#

NOTE:

1. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used.

The CMOS, Clock, APIC, and TAP inputs can be

driven from ground to 2.5V. The TAP outputs are

open drain and should be pulled up to 2.5V using

resistors with the values shown in Table 3.2. If

open-drain drivers are used for input signals, then

they should also be pulled up to 2.5V using

resistors with the values shown in Table 3.2.

3.1.1

Power Sequencing Requirements

The mobile Intel Celeron processor has no power

sequencing requirements. Intel recommends that all

of the processor power planes rise to their

specified values within one second of each other.

The V power plane must not rise too fast. At

CC

least 200 msec (T_R) must pass from the time that

V_CCis at 10% of its nominal value until the time that

V_CCis at 90% of its nominal value (see Figure 3.2).

V_cc

90% V_cc(nominal)

Volts

10% V_cc(nominal)

T_R

Time

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Figure 3.1 Ramp Rate Requirement

The TESTHI3 signals can share a single 1kW pull-

3.1.2

Test Access Port (TAP) Connection

up.

The TAP interface is an implementation of the

IEEE 1149.1 (“JTAG”) standard. Due to the voltage

levels supported by the TAP interface, Intel

recommends that the mobile Intel Celeron processor

and the other 2.5V JTAG specification compliant

devices be last in the JTAG chain after any devices

with 3.3V or 5.0V JTAG interfaces within the

system. A translation buffer should be used to

reduce the TDO output voltage of the last 3.3/5.0V

device down to the 2.5V range that the mobile Intel

Celeron processor can tolerate. Multiple copies of

TCK, TMS, and TRST# must be provided¾ one for

each voltage level.

Unused Low Power GTL+ inputs, outputs, and bi-

directional signals should be individually connected

to V_CCwith 120W pull-up resistors. Unused CMOS

active low inputs should be connected to 2.5V and

unused active high inputs should be connected to

V_SS

.

Unused open-drain outputs should be

unconnected. If the processor is configured to

enter the Quick Start state rather than the Stop

Grant state, then the SLP# signal should be

connected to 2.5V. When tying any signal to power

or ground,

a resistor will allow for system

testability. For unused signals, Intel suggests that

10-kW resistors be used for pull-ups and 1-kW

resistors be used for pull-downs.

A Debug Port and connector may be placed at the

start and end of the JTAG chain containing the

processor, with TDI to the first component coming

from the Debug Port and TDO from the last

component going to the Debug Port. There are no

requirements for placement of the mobile Intel

Celeron processor in the JTAG chain, except for

those that are dictated by voltage requirements of

the TAP signals.

PICCLK and PICD[1:0] must be tied to V_SSwith a 1-

kW resistor. BSEL must be connected to V_SS.

3.1.5

Signal State in Low Power States

3.1.5.1 System Bus Signals

All of the system bus signals have Low Power

GTL+ input, output, or input/output drivers. Except

when servicing snoops, the system bus signals

are tri-stated and pulled up by the termination

resistors. Snoops are not permitted in the Sleep

and Deep Sleep states.

3.1.3

Catastrophic Thermal Protection

The mobile Intel Celeron processor does not

support catastrophic thermal protection or the

THERMTRIP# signal. An external thermal sensor

should use the thermal diode to protect the

processor and the system against excessive

temperatures.

3.1.5.2 CMOS and Open-drain Signals

The CMOS input signals are allowed to be in either

the logic high or low state when the processor is in

a low power state. In the Auto Halt and Stop Grant

states these signals are allowed to toggle. These

input buffers have no internal pull-up or pull-down

resistors and system logic can use CMOS or open-

drain drivers to drive them.

3.1.4

Unused Signals

All signals named NC must be unconnected. All

signals named TESTLO must be pulled down to V_SS

or tied directly to V_SS. All signals named TESTHI or

TESTHI3 must be pulled up to V_CCwith a resistor.

All signals named TESTHI2 must be pulled up to

V_CCPwith a resistor. Each TESTHI and TESTHI2

signal must have an individual, 1kW pull-up resistor.

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The open-drain output signals have open-drain

drivers and external pull-up resistors are required.

One of the two output signals (IERR#) is a

catastrophic error indicator and is tri-stated (and

pulled-up) when the processor is functioning

normally. The FERR# output can be either tri-stated

or driven to V_SSwhen the processor is in a low

power state depending on the condition of the

floating point unit. Since this signal is a DC current

path when it is driven to V_SS, Intel recommends that

the software clear or mask any floating point error

condition before putting the processor into the

Deep Sleep state.

tools to help determine how much decoupling is

required. The processor core power plane (V_CC

)

should have at least twenty-six 0.1 mF high

frequency decoupling capacitors. The CMOS

voltage reference power plane (V_CCP) requires

50 mF to 100 mF of bulk decoupling and at least

eight 0.1 mF high frequency decoupling capacitors.

For the Low Power GTL+ pull-up resistors, one

0.1 mF high frequency decoupling capacitor is

recommended per resistor pack. There should be

no more than eight pull-up resistors per resistor

pack. The Low Power GTL+ voltage reference

power plane (V_REF) should have at least three

0.1 mF high frequency decoupling capacitors.

3.1.5.3 Other Signals

3.2.2

Voltage Planes

The system bus clock (BCLK) must be driven in all

of the low -power states except the Deep Sleep

state.

All V_CCand V balls must be connected to the

SS

appropriate voltage plane. All V_CCPand V_REFballs

must be connected to the appropriate traces on the

system electronics.

3.2

Power Supply Requirements

3.2.1

Decoupling Recommendations

In addition to the main V_CC, V_CCP, and V_SSpower

supply signals, PLL1 and PLL2 provide isolated

power to the PLL section. PLL1 and PLL2 should be

connected according to Figure 3.2. Do not connect

The amount of bulk decoupling required to meet the

processor voltage tolerance requirements is a

strong function of the power supply design.

Contact your Intel Field Sales Representative for

PLL2 directly to V_SS

.

Table 3.3 contains the

requirements for C1 and L1.

L1

PLL1

VCCP

C1

V0027-00

PLL2

Figure 3.2 PLL LC Filter

Table 3.3 LC Filter Specifications

Symbol

Parameter

Min

Max

Unit

Notes

C1

LC Filter Capacitance

47

mF

£30% tolerance, 1W max series

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Table 3.3 LC Filter Specifications

Symbol

Parameter

Min

Max

Unit

Notes

resistance, ~2 nH series inductance

L1

LC Filter Inductance

20

47

mH

low -Q type choke, £30% tolerance, 1.5W

max series resistance, ³ 50 mA current,

self-resonant frequency >10 MHz

frequency only. In this case, the bus ratio

configuration signals are not effective.

3.3

System Bus Clock and

Processor Clocking

Processors with marked core frequency at 366

MHz and below are implemented with Bus Fraction

Limiting scheme. The processor core frequency

must be configured during Reset by using the

A20M#, IGNNE#, NMI, and INTR pins (see Table

3.4). The value on these pins during Reset

The 2.5-V BCLK clock input directly controls the

operating speed of the system bus interface. All

system bus timing parameters are specified with

respect to the rising edge of the BCLK input. The

mobile Intel Celeron processor core frequency is a

multiple of the BCLK frequency.

determines the multiplier that the PLL will use for

the internal core clock. See the Pentium^®II

Processor Developer's Manual (Order Number

243502) for the definition of these pins during

Reset and the operation of the pins after Reset.

Processors at marked core frequency of 400 MHz

and above are implemented with Bus Fraction

Locking scheme. The Bus Fraction Locking scheme

allows the processors to operate at the marked

Table 3.4 Core Frequency to System Bus Ratio Configuration

Processor Core Frequency to

System Bus Frequency Ratio

NMI

INTR

IGNNE# A20M# Power-Up Configuration

[25:22]

4 (266 MHz)

9/2 (300 MHz)

5 (333 MHz)

L

H

L

H

L

0010

0110

0000

0100

1011

1111

1001

L

H

L

11/2 (366 MHz)

6 (400 MHz)

13/2 (433 MHz)

7 (466 MHz)

L

H

L

H

L

H

L

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In this case, a multiplexer is required between the

system electronics and the processor to drive the

bus ratio configuration signals during Reset. Figure

3.6 and Table 3.16 describe the timing requirements

for this operation. The 443BX CRESET# signal has

suitable timing to control the multiplexer. After

RESET# and PWRGOOD are asserted, the

multiplexer logic must guarantee that the bus ratio

configuration signals encode one of the bus ratios

in Table 3.4 and that the bus ratio corresponds to a

core frequency at or below the marked core

frequency for the processor. The selected bus

ratio is visible to software in the Power-On

Configuration register, see Section 7.2 for details.

The 440MX PCISet contains a multiplexer that meets

the requirements described above.

some amount of time to acquire the phase of BCLK.

This time is called the PLL lock latency, which is

specified in Section 3.6. The system bus frequency

ratio can be changed when RESET# is active,

assuming that all Reset specifications are met. The

BCLK frequency should not be changed during

Deep Sleep state (see Section 2.2.8).

3.4

Maximum Ratings

Table 3.5 contains the mobile Intel Celeron

processor stress ratings. Functional operation at

the absolute maximum and minimum is neither

implied nor guaranteed. The processor should not

receive a clock while subjected to these conditions.

Functional operating conditions are provided in the

AC and DC tables. Extended exposure to the

maximum ratings may affect device reliability.

Furthermore, although the processor contains

protective circuitry to resist damage from static

electric discharge, one should always take

precautions to avoid high static voltages or electric

fields.

Multiplying the bus clock frequency is necessary to

increase performance while allowing for easier

distribution of signals within the system. Clock

multiplication within the processor is provided by

the internal Phase Lock Loop (PLL), which requires

a constant frequency BCLK input. During Reset or

on exit from the Deep Sleep state, the PLL requires

Table 3.5 Mobile Intel Celeron Processor Absolute Maximum Ratings

Parameter Min Max Unit

Storage Temperature –40 85

Symbol

T_Storage

Notes

°C

V

Note 1

V_CC(Abs)

V_CCP

Supply Voltage with respect to V_SS

–0.5

–0.3

3.0

CMOS Reference Voltage with respect to V_SS

GTL+ Buffer DC Input Voltage with respect to V_SS

2.5V Buffer DC Input Voltage with respect to V_SS

V

V_IN

–0.3 V_CC+ 0.7

–0.3 3.3

V

Note 2

Note 3

V_IN25

V

NOTES:

1. The shipping container is only rated for 65°C.

2. Parameter applies to the Low Power GTL+ signal groups only.

3. Parameter applies to CMOS, Open-Drain, APIC, and TAP bus signal groups only.

3.5

DC Specifications

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Specifications are valid only while meeting

Table 3.6 through Table 3.11 list the DC

specifications for the mobile Intel Celeron

processor.

specifications for case temperature, clock

frequency, and input voltages. Care should be

taken to read all notes associated with each

parameter.

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Table 3.6 Mobile Intel Celeron Processor Power Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ±135 mV; V_CCP= 1.8V ±90 mV

Symbol

V_CC

Parameter

Vcc of core logic

Min

Typ

Max

Unit

V

Notes

±135 mV

1.765

1.710

1.900

1.800

2.035

2.105

1.890

V_CC,LP

V_CCP

I_CC

V_CCwhen I_CC< 300 mA

V

+205/-135 mV ²

1.8V ±90 mV

Note 5

V_CCfor CMOS voltage references

V

I_CCfor V_CC

at 466 MHz

at 433 MHz

12.30

11.50

A

at core frequency

I_CCP

Current for V_CCP

75

mA

A

Notes 3, 4, 5

Note 5

I_CC,SG

Processor Stop Grant and

Auto Halt current

1.70

I_CC,QS

Processor Quick Start and

Sleep current

1.30

0.65

20

A

Note 5

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 5

dI_CC/dt

V_CCpower supply current slew rate

A/ms

Notes 6, 7

NOTES:

1. Specifications in this table apply to the listed frequencies.

2. A higher V_CC,MAXis allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator.

3. I_CCPis the current supply for the CMOS voltage references.

4. Not 100% tested. Specified by design/characterization.

5. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,max, and 100°C and under maximum signal loading

conditions. I_CCx,maxspecifications are not specified at V_CC,LP,maxif that voltage specification is used then

slightly higher currents can be expected.

6. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

7. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

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Table 3.7 Mobile Intel Celeron Processor Power Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.6V ±135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

Min

Typ

Max

Unit

Notes

±135 mV

V_CC

V_CCof core logic for regular voltage

processors

1.465

1.600

1.735

V

V_CC,LP

V_CCP

I_CC

V_CCwhen I_CC< 300 mA

1.465

1.710

1.600

1.800

1.805

1.890

V

+205/-135 mV ²

1.8V ±90 mV

Note 5

V_CCfor CMOS voltage references

I_CCfor V_CC

at 400 MHz

at 366 MHz

at 333 MHz

at 300 MHz

at 266 MHz

9.70

8.80

7.95

7.49

6.63

A

at core frequency

I_CCP

Current for V_CCP

75

mA

Notes 3, 4, 5

Note 5

I_CC,SG

Processor Stop Grant and

Auto Halt current

1190

I_CC,QS

Processor Quick Start and

Sleep current

880

650

20

mA

Note 5

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 5

dI_CC/dt

V_CCpower supply current slew rate

A/ms

Notes 6, 7

NOTES:

1. Specifications in this table apply to the listed frequencies.

2. A higher V_CC,MAXis allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator.

3. I_CCPis the current supply for the CMOS voltage references.

4. Not 100% tested. Specified by design/characterization.

5. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,max, and 100°C and under maximum signal loading

conditions. I_CCx,maxspecifications are not specified at V_CC,LP,maxif that voltage specification is used then

slightly higher currents can be expected.

6. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

7. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

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Table 3.8 Low Voltage Mobile Intel Celeron Processor Power Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.5V ±135 mV; V_CCP= 1.8V ±90 mV

Symbo Parameter

l

Min

Typ

Max

Unit

Notes

V_CC

Vcc of core logic for 266PE MHz at

1.365

1.500

1.635

V

±135 mV

low voltage

V_CC,LP

V_CCP

I_CC

V_CCwhen I_CC< 300 mA

V_CCfor CMOS voltage references

1.365

1.710

1.500

1.800

1.705

1.890

5.90

V

A

+205/-135 mV ²

1.8V ±90 mV

Note 5

I_CCfor V_CC

at 266 MHz

at core frequency

I_CCP

Current for V_CCP

75

mA

Notes 3, 4, 5

Note 5

I_CC,SG

Processor Stop Grant and

Auto Halt current

940

I_CC,QS

Processor Quick Start and

Sleep current

630

400

20

mA

Note 5

I_CC,DSLPProcessor Deep Sleep leakage

current

Note 5

dI_CC/dt

V_CCpower supply current slew rate

A/ms

Notes 6, 7

NOTES:

1. Specifications in this table apply to the listed frequency.

2. A higher V_CC,MAXis allowed when the processor is in a low -power state to enable high efficiency, low -

current modes in the power regulator.

3. I_CCPis the current supply for the CMOS voltage references.

4. Not 100% tested. Specified by design/characterization.

5. I_CCx,maxspecifications are specified at V_CC,max, V_CCP,max, and 100°C and under maximum signal loading

conditions. I_CCx,maxspecifications are not specified at V_CC,LP,maxif that voltage specification is used then

slightly higher currents can be expected.

6. Based on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

7. Maximum values specified by design/characterization at nominal V_CCand V_CCP

.

The signals on the mobile Intel Celeron processor

system bus are included in the Low Power GTL+

signal group. These signals are specified to be

terminated to V_CC. The DC specifications for these

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signals are listed in Table 3.9; the termination and

reference voltage specifications for these signals

are listed in Table 3.10. The mobile Intel Celeron

Bus Layout Guideline (Order Number 243672-001)

for full details of system V_TTand V_REF

requirements.

processor requires external termination and a V_REF

.

Refer to Mobile Pentium^®II Processor System

Table 3.9 Low Power GTL+ Signal Group DC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

V_IL

Parameter

Input Low Voltage

Input High Voltage

Output High Voltage

Min

–0.3

Max

⁵/₉V_TT– 0.2

V_CC

Unit

V

Notes

See Table 3.10 ¹

Note 1

V_IH

⁵/₉V_TT+ 0.2

—

V

V_OH

—

V

See V_TTmax in Table

3.10.

R_ON

I_L

Output Low Drive Strength

Leakage Current

35

ohms

mA

±100

±30

Note 2

Note 3

I_LO

Output Leakage Current

mA

NOTES:

1. V_REFworst case, not nominal. Noise on V_REFshould be accounted for.

2. (0 £ V_IN£ V_CC).

3. (0 £ V_OUT£ V_CC).

Table 3.10. Low Power GTL+ Bus DC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

V_TT

Parameter

Min

Typ

V_CC

Max

Unit

V

Notes

Bus Termination Voltage

Input Reference Voltage

V_CC,MIN

V_CC,MAX

Note 1

±2% ²

V_REF

⁵/₉V_TT– 2%

⁵/₉V_TT

⁵/₉V_TT+ 2%

V

NOTES:

1. The intent is to use the same power supply for V_CCand V_TT

.

2. V_REFfor the system logic should be created from V_TTby a voltage divider.

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Table 3.11 Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

Input Low Voltage

Min

–0.3

1.7

Max

0.7

Unit

V

Notes

V_IL

V_IL,BCLKInput Low Voltage, BCLK

V_IHInput High Voltage

V_IH,BCLKInput High Voltage, BCLK

0.7

V

2.625

0.4

V

1.8

V

V_OL

V_OH

I_OL

Output Low Voltage

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

V

Note 1

N/A

2.625

14

V

All outputs are open-drain

mA

I_LI

±100

±30

Note 2

I_LO

NOTES:

1. Parameter measured at 14 mA.

2. (0 £ V_IN£ 2.625V).

contains the system bus clock specifications; Table

3.13 contains the processor core frequencies;

Table 3.14 contains the Low Power GTL+

specifications; Table 3.15 contains the CMOS and

Open-Drain signal groups specifications; Table 3.16

contains timings for the reset conditions; Table 3.17

contains the TAP specifications; and Table 3.18

and Table 3.19 contain the power management

timing specifications.

The Clock, CMOS, Open-drain, and TAP signals are

designed to interface at 2.5V CMOS levels to allow

connection to other devices. The DC specifications

for these 2.5V tolerant signals are listed in Table

3.11.

3.6

AC Specifications

3.6.1

System Bus, Clock, APIC, TAP,

CMOS, and Open-drain AC

Specifications

All system bus AC specifications for the Low

Power GTL+ signal group are relative to the rising

edge of the BCLK input at 1.25V. All Low Power

GTL+ timings are referenced to V_REFfor both ‘0’

and ‘1’ logic levels unless otherwise specified.

Table 3.12 through Table 3.19 provide AC

specifications associated with the mobile Intel

Celeron processor. The AC specifications are

divided into the following categories: Table 3.12

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Table 3.12 System Bus Clock AC Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

System Bus Frequency

BCLK Period

Min

Typ

66.67

15

Max

Unit

MHz

ns

Figure

Notes

T1

T2

T3

T4

T5

T6

3.3

Note 2

BCLK Period Stability

BCLK High Time

±250

ps

Notes 3, 4

5.0

ns

3.3

At >1.8V

BCLK Low Time

BCLK Rise Time

ns

At <0.7V

0.125

0.875

ns

(0.9V – 1.6V) ⁴

(1.6V – 0.9V) ⁴

BCLK Fall Time

ns

NOTES:

1. All AC timings for Low Power GTL+ and CMOS signals are referenced to the BCLK rising edge at

1.25V. All CMOS signals are referenced at 1.25V.

2. The BCLK period allows a +0.5-ns tolerance for clock driver variation.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a

component of BCLK skew between devices.

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Table 3.13 Valid Mobile Intel Celeron Processor Frequencies

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

BCLK Frequency (MHz)

Frequency Multiplier

Core Frequency (MHz)

266.67

66.67

4

9/2

5

300.00

333.00

11/2

6

366.67

400.00

13/2

7

433.00

466.00

NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other

than those listed in Table 3.13 will not be validated by Intel and are not guaranteed. The frequency

multiplier is programmed into the processor when it is manufactured and it cannot be changed.

Table 3.14 Low Power GTL+ Signal Groups AC Specifications¹

R_TT= 120W terminated to V_CC; V_REF= 5/9 V_CC; load = 0pF

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

Min

0.00

2.98

0.90

1

Max

Unit

ns

Figure

3.4

Notes

T7

T8

T9

Low Power GTL+ Output Valid Delay

Low Power GTL+ Input Setup Time

Low Power GTL+ Input Hold Time

RESET# Pulse Width

7.78

ns

3.5

Notes 2, 3

Note 4

ns

3.5

T10

ms

3.6, 3.7

Note 5

NOTES:

1. All AC timings for Low Power GTL+ signals are referenced to the BCLK rising edge at 1.25V. All Low

Power GTL+ signals are referenced at V_REF

.

2. RESET# can be asserted (active) asynchronously but must be deasserted synchronously.

3. Specification is for a minimum 0.40V swing.

4. Specification is for a maximum 1.0V swing.

5. After V_CC, V_CCP, and BCLK become stable and PWRGOOD is asserted.

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Table 3.15 CMOS and Open-Drain Signal Groups AC Specifications^{1, 2}

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

Min

Max

Unit

Figure

Notes

T14

2.5V Input Pulse Width, except PWRGOOD

2

BCLKs

3.4

Active and

Inactive

states

T15

PWRGOOD Inactive Pulse Width

10

BCLKs

3.7

Notes 3, 4

NOTES:

1. All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25V. All

CMOS and Open-drain signals are referenced at 1.25V.

2. Minimum output pulse width on CMOS outputs is 2 BCLKs.

3. When driven inactive, or after V_CC, V_CCP,and BCLK become stable. PWRGOOD must remain below

V_IL,maxfrom Table 3.11 until all the voltage planes meet the voltage tolerance specifications in Table 3.7,

and BCLK has met the BCLK AC specifications in Table 3.12 for at least 10 clock cycles. PWRGOOD

must rise error-free and monotonically to 2.5V.

4. If the BCLK signal meets its AC specification within 150 ns of turning on then the PWRGOOD Inactive

Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD

must still remain below V_IL,maxuntil all the voltage planes meet the voltage tolerance specifications.

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Table 3.16 Reset Configuration AC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

Parameter

Min

Max

Unit

Figure

Notes

Before

T16

Reset Configuration Signals

(A[15:5]#, BR0#, FLUSH#, INIT#,

PICD0) Setup Time

4

BCLKs

3.5, 3.6

deassertion of

RESET#

T17

T18

Reset Configuration Signals

(A[15:5]#, BR0#, FLUSH#, INIT#,

PICD0) Hold Time

2

1

20

BCLKs

ms

3.5, 3.6

After clock that

deasserts

RESET#

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Setup Time

3.7

Before

deassertion of

RESET#, Note 1

T19

T20

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Delay Time

5

BCLKs

3.7

After assertion of

RESET#, Note

Reset Configuration Signals (A20M#,

IGNNE#, INTR, NMI) Hold Time

2

20

3.5, 3.7

After clock that

deasserts

RESET#

NOTES:

1. At least 1 ms must pass after PWRGOOD rises above V_IH,minfrom Table 3.11 and BCLK meets its AC

timing specification, until RESET# may be deasserted.

2. For a Reset, the clock ratio defined by these signals must be a safe value (their final value or a lower

multiplier) within this delay after RESET# is asserted unless PWRGOOD is inactive (below V_IL,max).

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Table 3.17 TAP Signal AC Specifications¹

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

T30

Parameter

TCK Frequency

Min

—

Max

16.67

—

Unit

MHz

ns

Figure

Notes

T31

TCK Period

60

3.3

T32

T33

T34

T35

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

25.0

ns

³ 1.7V ²

£ 0.7V ²

5.0

(0.7V-1.7V) ^2,3

(1.7V-0.7V) ^2,3

3.3

3.9

3.8

T36

T37

T38

T39

T40

T41

T42

T43

TRST# Pulse Width

40.0

5.0

ns

Asynchronous ²

Note 4

TDI, TMS Setup Time

TDI, TMS Hold Time

14.0

1.0

Note 4

TDO Valid Delay

10.0

25.0

Notes 5, 6

TDO Float Delay

Notes 2, 5, 6

Notes 5, 7, 8

Notes 2, 5, 7, 8

Notes 4, 7, 8

All Non-Test Outputs Valid Delay

All Non-Test Outputs Float Delay

All Non-Test Inputs Setup Time

All Non-Test Inputs Hold Time

2.0

5.0

T44

13.0

NOTES:

1. All AC timings for TAP signals are referenced to the TCK rising edge at 1.25V. All CMOS signals are

referenced at 1.25V.

2. Not 100% tested. Specified by design/characterization.

3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.

4. Referenced to TCK rising edge.

5. Referenced to TCK falling edge.

6. Valid delay timing for this signal is specified into 150W terminated to 2.5V and 0 pF of external load. For

real system timings these specifications must be derated for external capacitance at 105 ps/pF.

7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to boundary scan operations.

8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.

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Table 3.18 Quick Start/De ep Sleep AC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

T45

Parameter

Min

Max

Unit

BCLKs

ns

Figure

3.10

Stop Grant Cycle Completion to Clock Stop

Stop Grant Cycle Completion to Input Signals Stable

Deep Sleep PLL Lock Latency

100

T46

0

T47

30

ms

T48

STPCLK# Hold Time from PLL Lock

0

8

ns

T49

Input Signal Hold Time from STPCLK# Deassertion

BCLKs

NOTE:

1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.

Table 3.19 Stop Grant/Sleep/Deep Sleep AC Specifications

T_CASE= 0 to T_CASE,max; V_CC= 1.9V ± 135 mV, 1.6V ± 135 mV, or 1.5V ± 135 mV; V_CCP= 1.8V ±90 mV

Symbol

T50

Parameter

Min

Max

Unit

BCLKs

ns

Figure

3.11

SLP# Signal Hold Time from Stop Grant Cycle Completion

SLP# Assertion to Input Signals Stable

SLP# Assertion to Clock Stop

100

T51

0

T52

10

0

BCLKs

ns

T54

SLP# Hold Time from PLL Lock

T55

STPCLK# Hold Time from SLP# Deassertion

Input Signal Hold Time from SLP# Deassertion

10

BCLKs

T56

NOTE:

1. Input signals other than RESET# must be held constant in the Sleep state.

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Figure 3.3 through Figure 3.11 are to be used in conjunction with Table 3.12 through Table 3.19.

T

r2

T

h

T

r1

V_IH

1.6V

0.9V

CLK

V_TRIP

V_IL

T

f1

T

f2

T

l

T

p

D0003-02

NOTES:

T_r1

T_f1

T_h

T_l

=

T5, T_r2= T34 (Rise Time)

T6, T_f2= T35 (Fall Time)

T3, T32 (High Time)

T4, T33 (Low Time)

T1, T31 (Period)

T_p

Figure 3.3 Generic Clock Waveform

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CLK

T

x

T

x

Signal

V

Valid

T

pw

D0004-00

NOTES:

T_x

T_pw

V

=

T7, T11 (Valid Delay)

T14 (Pulse Width)

V_REFfor Low Power GTL+ signal group; 1.25V for CMOS, Open-Drain,

and TAP signal groups

Figure 3.4 Valid Delay Timings

CLK

T

s

T

h

Signal

V Valid

D0005-00

NOTES:

T_s

T_h

V

=

T8, T12 (Setup Time)

T9, T13 (Hold Time)

V_REFfor Low Power GTL+ signals; 1.25V for CMOS and TAP signals

Figure 3.5 Setup and Hold Timings

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BCLK

T

u

T

t

RESET#

T

v

T

z

T

x

y

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Safe

Valid

T

w

Configuration

(A[15:5], BREQ0#,

FLUSH#, INIT#,

PICD0)

D0006-01

NOTES:

T_t

=

T9 (Low Power GTL+ Input Hold Time)

T8 (Low Power GTL+ Input Setup Time)

T10 (RESET# Pulse Width)

T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Setup Time)

T_u

T_v

T_w

T_x

=

T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Hold Time)

T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

T19 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Delay Time)

T18 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Setup Time)

T_y

T_z

=

Figure 3.6 Reset and Configuration Timings

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BCLK

V

,

CCP,

V

,

CC

REF

V

V_IH,min

T

PWRGOOD

RESET#

V_IL,max

T

a

b

T

c

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid Ratio

D0007-01

NOTES:

T_a

T_b

T_c

=

T15 (PWRGOOD Inactive Pulse Width)

T10 (RESET# Pulse Width)

T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

Figure 3.7 Power-on Reset Timings

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TCK

T

v

T

w

TDI, TMS

1.25V

T

s

r

Input

Signals

T

x

T

u

TDO

T

y

T

z

Output

Signals

D0008-00

NOTES:

T_r

=

T43 (All Non-Test Inputs Setup Time)

T44 (All Non-Test Inputs Hold Time)

T40 (TDO Float Delay)

T37 (TDI, TMS Setup Time)

T38 (TDI, TMS Hold Time)

T39 (TDO Valid Delay)

T41 (All Non-Test Outputs Valid Delay)

T42 (All Non-Test Outputs Float Delay)

T_s

T_u

T_v

T_w

T_x

T_y

T_z

Figure 3.8 Test Timings (Boundary Scan)

1.25V

TRST#

T

q

D0009-00

NOTE:

T_q

=

T36 (TRST# Pulse Width)

Figure 3.9 Test Reset Timings

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Normal

Quick Start

Running

Deep Sleep

Normal

Quick Start

Running

BCLK

T

v

STPCLK#

T

T_y

x

CPU bus

SLP#

stpgnt

T

T_w

Changing

z

Compatibility

Signals

Frozen

V0010-00

NOTES:

T_v

T_w

T_x

T_y

T_z

=

T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)

T46 (Setup Time to Input Signal Hold Requirement)

T47 (Deep Sleep PLL Lock Latency)

T48 (PLL lock to STPCLK# Hold Time)

T49 (Input Signal Hold Time)

Figure 3.10 Quick Start/Deep Sleep Timing

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Stop

Grant

Stop

Grant

Normal

Running

Sleep

Deep Sleep

Sleep

Normal

BCLK

Running

T

v

STPCLK#

T

y

CPU bus

SLP#

stpgnt

T

T_w

T_x

t

T_u

T

z

Compatibility

Signals

Changing

Frozen

V0011-00

NOTES:

T_t

=

T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)

T51 (Setup Time to Input Signal Hold Requirement)

T52 (SLP# assertion to clock shut off delay)

T47 (Deep Sleep PLL lock latency)

T54 (SLP# Hold Time)

T55 (STPCLK# Hold Time)

T_u

T_v

T_w

T_x

T_y

T_z

T56 (Input Signal Hold Time)

Figure 3.11 Stop Grant/Sleep/Deep Sleep Timing

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to determine if they are compliant with this

specification.

4.

SYSTEM SIGNAL

SIMULATIONS

Many scenarios have been simulated to generate

a set of Low Power GTL+ processor system

bus layout guidelines which are available in the

Mobile Pentium^®II Processor System Bus

Layout Guideline (Order Number 243672-001).

Systems must be simulated using the IBIS model

4.1

System Bus Clock (BCLK)

Signal Quality Specifications

Table 4.1 and Figure 4.1 show the signal quality

for the system bus clock (BCLK) signal at the

processor. The timings illustrated in Figure 4.1

are taken from Table 3.12. BCLK is a 2.5-V clock.

Table 4.1 BCLK Signal Quality Specifications

Symbol

V1

Parameter

Min

Max

Unit

V

Figure

4.1

Notes

V_IL,BCLK

V_IH,BCLK

0.7

Note 1

V2

1.8

V

4.1

V3

V_INAbsolute Voltage Range

–0.7

3.5

0.7

V

4.1

Undershoot,

Overshoot

V4

Rising Edge Ringback

Falling Edge Ringback

1.8

V

4.1

Absolute Value ²

V5

NOTES:

1. BCLK must rise/fall monotonically between V_IL,BCLKand V_IH,BCLK

.

2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling)

absolute voltage the BCLK signal can dip back to after passing the V_IH,BCLK(rising) or V_IL,BCLK(falling)

voltage limits.

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T3

V3

V4

V2

V1

V5

T6

V3

T5

T4

V0012-00

Figure 4.1 BCLK Generic Clock Waveform

GTL+ signal quality specifications for the mobile

Intel Celeron processor. Refer to the Pentium^®II

Processor Developer’s Manual for the GTL+ buffer

specification.

4.2

Low Power GTL+ Signal

Quality Specifications

Table 4.2 and Figure 4.2 illustrate the Low Power

Table 4.2 Low Power GTL+ Signal Group Ringback Specification

Parameter Min Unit Figure

100 mV 4.2

Symbol

Notes

Notes 1, 2

Overshoot

a

t

Minimum Time at High

1

ns

mV

ns

4.2

Notes 1, 2

Notes 1, 2, 3

Notes 1, 2

Amplitude of Ringback

Final Settling Voltage

-100

100

N/A

r

f

Duration of Sequential Ringback

d

NOTES:

1. Specified for the edge rate of 0.3 – 0.8 V/ns. See Figure 4.2 for the generic waveform.

2. All values determined by design/characterization.

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3. Ringback below V_REF+100 mV is not authorized during low to high transitions. Ringback above V_REF

100mV is not authorized during high to low transitions.

-

t

V

IH,BCLK

a

V

+0.2V

REF

f

V

REF

r

V

-0.2V

d

REF

V_IL,BCLK

V

start

Clock

V0014-00

Time

NOTE: High-to-low case is analogous.

Figure 4.2 Low to High, Low Power GTL+ Receiver Ringback Tolerance

ringback and settling limit. All three signal quality

parameters are shown in Figure 4.3 for non-GTL+

signal groups.

4.3

Non-Low Power GTL+ Signal

Quality Specifications

4.3.1

Overshoot and Undershoot

Guidelines

Signals driven to the mobile Intel Celeron processor

should meet signal quality specifications to ensure

that the processor reads data properly and that

incoming signals do not affect the long-term

reliability of the processor. There are three signal

quality parameters defined: overshoot/undershoot,

Overshoot (or undershoot) is the absolute value of

the maximum voltage above the nominal high

voltage or below V . The overshoot/undershoot

SS

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guideline limits transitions beyond V_CCor V_SSdue to

However, excessive ringback is the dominant

detrimental system timing effect resulting from

overshoot/undershoot (for example, violating the

overshoot/undershoot guideline will make it difficult

to satisfy the ringback specification). The

overshoot/undershoot guideline is 0.8V and

assumes the absence of diodes on the input.

These guidelines should be verified in simulations

without the on-chip ESD protection diodes present

because the diodes will begin clamping the 2.5-V

tolerant signals beginning at approximately 1.25V

above V_CCand 0.5V below V_SS. If the signals do

not reach the clamping voltage, then this will not be

an issue. A system should not rely on the diodes

for overshoot/undershoot protection as this will

negatively affect the life of the components and

make meeting the ringback specification very

difficult.

the fast signal edge rates. The processor can be

damaged by repeated overshoot events on 2.5V

tolerant buffers if the charge is large enough (i.e., if

the overshoot is great enough).

Settling Limit

Overshoot

V_HI=2.5V

Rising-Edge

Ringback

Falling-Edge

Ringback

Settling Limit

V

LO

SS

Undershoot

Time

V0015-00

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Figure 4.3 Non-GTL+ Overshoot/Undershoot and Ringback

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4.3.2

Ringback Specification

4.3.3

Settling Limit Guideline

Ringback refers to the amount of reflection seen

after signal has switched. The ringback

Settling limit defines the maximum amount of ringing

at the receiving signal that a signal may reach

before its next transition. The amount allowed is

10% of the total signal swing (V_HI– V_LO) above and

below its final value. A signal should be within the

settling limits of its final value, when either in its

high state or low state, before its next transition.

a

specification is the voltage that the signal rings

back to after achieving its maximum absolute value.

Excessive ringback can cause false signal

detection or extend the propagation delay. The

ringback specification applies to the input signal of

each receiving agent. Violations of the signal

ringback specification are not allowed under any

circumstances for the non-GTL+ signals.

Signals that are not within their settling limit before

transitioning are at risk of unwanted oscillations

that could jeopardize signal integrity. Simulations to

verify settling limit may be done either with or

without the input protection diodes present.

Violation of the settling limit guideline is acceptable

if simulations of five to ten successive transitions

do not show the amplitude of the ringing increasing

in the subsequent transitions.

Ringback can be simulated with or without the input

protection diodes that can be added to the input

buffer model. However, signals that reach the

clamping voltage should be evaluated further. See

Table 4.3 for the signal ringback specifications for

non-GTL+ signals.

Table 4.3 Signal Ringback Specifications for Non-GTL+ Signals

Input Signal Group Transition Maximum Ringback

Figure

(with Input Diodes Present)

Non-GTL+ Signals

0 ® 1

1 ® 0

1.7 V

0.7 V

4.3

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5.

MECHANICAL SPECIFICATIONS

5.1

Dimensions of the Micro-PGA

Package

The mobile Intel Celeron processor is packaged in

an PPGA-B615 package (also known as Micro-

PGA) or an PBGA-B615 package (also known as

BGA), with the back of the processor die exposed

on top. This section contains information describing

the packages and the signal pin assignments.

The mechanical specifications for the Micro-PGA

package are provided in Table 5.1 and shown in

Figure 5.1 and Figure 5.2.

Table 5.1 Micro-PGA Package Mechanical Specifications

Parameter Min

Overall height, top of die to seating plane of the interposer 3.23

Symbol

A

Max

Unit

mm

each

mm

kPa

gram

3.83

A₁

A₂

B

Pin length

1.25 REF

Die Height

0.854 REF

0.30 REF

Pin Diameter

D

Die Substrate Width

Die Width

30.85

31.15

D₁

D₂

E

10.36 REF

32.60 REF

Package Width

Die Substrate Length

Die Length

34.85

35.15

E₁

E₂

e

17.36 REF

36.80 REF

1.27 REF

<= 0.127

615

Package Length

Pin pitch

—

N

Pin Tip Radial True Position

Pin Count

S₁

S₂

P_DIE

W

Pin row A to short edge of interposer

Pin column 1 to long edge of interposer

Allowable Pressure on the Die for Thermal Solution

Package Weight

2.220 REF

1.415 REF

—

689

7.5 REF

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NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.1 Micro-PGA Package-Top and Side View

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NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 5.2 Micro-PGA Package-Bottom View

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surface-mount package, and Figure 5.4 shows the

Dimensions of the BGA

5.2

bottom view of the surface-mount package. For

Package

component handling, the substrate may only be

contacted within the shaded region between the

keep-out outline and the edge of the substrate.

The mechanical specifications for the surface-

mount BGA package are provided in Table 5.2.

Figure 5.3 shows the top and side views of the

Table 5.2 Surface-mount BGA Package Specifications

Parameter Min

2.29

1.50 REF

Symbol

Max

Unit

mm

each

mm

kPa

grams

A

Overall Height, as delivered

2.79

A₁

A₂

B

Substrate Height, as delivered

Die Height

0.854 REF

0.78 REF

Ball Diameter

D

Package Width

30.85

10.36 REF

34.85 35.15

31.15

D₁

E

Die Width

Package Length

e

Ball Pitch

1.27

E

1

Die Length

17.36 REF

615

N

Ball Count

S₁

S₂

P_DIE

W

Outer Ball Center to Short Edge of Substrate

Outer Ball Center to Long Edge of Substrate

Allowable Pressure on the Die for Thermal Solution

Package Weight

1.625 REF

0.895 REF

—

689

3.71

4.52

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A₁

die

(7.0 TYP)

(Ø 0.65)

(5.0 TYP)

D

A₂

ink swatch

E

E₁

(2x 1.50)

(2x 2.032)

(2x 0.57)

(Ø 1.15)

D₁

A

0.20 REF

substrate

keepout

outline

(2x 1.800)

V0026-00

NOTE: Dimensions are for reference only. All dimensions are in millimeters.

Figure 5.3 Surface-mount BGA Package - Top and Side View

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e

Øb

S

S₁

2

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

e

K

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

V0025-01

Figure 5.4 Surface-mount BGA Package - Bottom View

voltage balls called out. Table 5.3 lists the signals

in pin/ball number order. Table 5.4 and Table 5.5

list the signals in signal name order.

5.3

Signal Listings

Figure 5.5 is a topside view of the pin/ball map of

the mobile Intel Celeron processor with the

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1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

19 20 21 22 23 24

A

B

VSS

A29#

VSS

A26# A34#

VSS

NC

VSS

NC

VSS

NC

D0#

D6#

VSS

D5#

D2#

D3#

D7#

VSS

D13#

D18# D16#

D26# D31#

VSS

NC

EDG

CTRLN

VSS

A35# A19#

A22# A30#

A17# A31#

A24# TESTHI NC

D15# D17#

VSS

C

VSS

NC

A25#

A33# RESET# BERR# NC

NC

D4#

D1#

D9#

D10#

VSS

D14# D19#

D20# D22#

D21#

VSS

D24# D27#

D32# D28#

D29# D35#

D

A28#

VSS TESTLO TESTLO VSS

A23#

A20#

VSS

A27# VREF

VSS

VREF

VSS

D33#

E

A16# A12#

A13# TESTLO VSS

NC

A21# VREF A18#

A32#

NC

D8#

NC

D12#

NC

D11# D30#

D23# D25#

VSS

D37

VREF D34#

D36# D43#

D39#

NC

F

A11#

A3#

A15#

A5#

A10#

NC

VCCP

G

A8#

A7#

A6#

A4#

VSS

A9#

A14#

AP0#

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

D38

VSS

D44#

NC

H

D45#

D42# D51#

D47# D41#

D49#

J

TESTHI3 BNR# RSP# AP1# VREF

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

D48#

D52# D40#

K

VSS TESTHI3 VSS

VSS TESTHI3 NC

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

D59#

D54#

VSS

D57#

VSS

L

REQ1# BPRI# REQ4# REQ0# TESTHI NC

DEFER# REQ2# TESTHI3 LOCK# TRDY# NC

VREF D55#

D56# D50#

D46# D53#

D58# D60#

M

N

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

D61#

VSS REQ3# HITM# VSS

VREF

NC

DEP7# VSS

D63#

D62#

VSS

P

VSS DBSY# RP# DRDY# HIT#

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

DEP0# DEP3# DEP5# DEP6# VSS

BPM1# VREF DEP1# DEP2# DEP4#

R

BREQ0# RS0# RS2# RS1# PWRGOOD NC

T

VSS ADS# THERMDA VSS

AERR# VCCP THERMDC NC

SLP#

TDI

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

BP3#

VSS PRDY# BINIT# VSS

U

PICD1 PICCLKTESTHI3 BP2# BPM0#

V

BSEL

NC

TMS

VSS

VCCP

NC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

INTR PREQ# TESTHI

W

Y

TRST# VSS

VSS

VSS PICD0

VSS

TCK

SMI# FERR# TESTLO NC

NC

VCC

NC

VSS

NC

VCC

NC

VSS

NC

VCC

NC

VSS

NC

VCC

NC

VSS

NC

VCCP VCCP VSS

AA

AB

AC

AD

AE

AF

STPCLK# A20M# INIT# IERR#

NC

NMI

TDO IGNNE# NC

FLUSH# TESTHI2 NC

VCCP

NC

VSS TESTLO NC

VSS

VCCP VCC TESTHI2 NC

NC

VSS

NC

VSS

NC

VSS BCLK

PLL2

PLL1

V0024-01

VCC

VCCP VSS

Other

Analog

Decoupling

Figure 5.5 Pin/Ball Map - Top View

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

A2

VSS

A29#

VSS

A26#

A34#

VSS

NC

B8

TESTHI

NC

C14

NC

D20

VSS

D32#

D28#

VSS

D33#

A16#

A12#

A13#

TESTLO

VSS

NC

A3

B9

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

D1

D4#

D21

D22

D23

D24

E1

A4

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

C1

NC

D1#

A5

NC

D10#

D14#

D19#

D21#

D24#

D27#

D29#

D35#

A28#

VSS

TESTLO

VSS

A23#

A20#

VSS

A27#

VREF

VSS

NC

A6

NC

A7

NC

A8

NC

E2

A9

D6#

D15#

D17#

D2#

D7#

D13#

D26#

D31#

VSS

NC

E3

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B1

E4

VSS

NC

E5

E6

NC

E7

A21#

VREF

A18#

A32#

NC

VSS

D0#

D2

E8

D3

E9

VSS

D5#

D4

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

F1

D5

D6

NC

D3#

D7

NC

VSS

D18#

D16#

VSS

NC

C2

D8

D8#

C3

NC

D9

D12#

D11#

D30#

D23#

D25#

VSS

VREF

D34#

D39#

NC

C4

A25#

A17#

A31#

A33#

RESET#

BERR#

NC

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

C5

C6

VSS

EDGCTRLN

A35#

A19#

A22#

A30#

A24#

C7

NC

B2

C8

VSS

VREF

D9#

B3

C9

B4

C10

C11

C12

C13

B5

NC

VSS

D20#

D22#

B6

NC

B7

NC

A11#

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

F2

A3#

A15#

A5#

A10#

NC

G8

NC

H15

VCC

VSS

NC

J21

D47#

D41#

D52#

D40#

VSS

TESTHI3

VSS

TESTHI3

NC

F3

G9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

H16

H17

H18

H19

H20

H21

H22

H23

J1

J22

J23

J24

K1

F4

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

H2

F5

NC

F6

NC

F7

NC

D45#

D42#

D51#

D49#

TESTHI3

BNR#

RSP#

AP1#

VREF

NC

K2

F8

NC

K3

F9

NC

K4

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

G2

NC

K5

NC

K6

NC

J2

K7

NC

J3

K8

NC

D38#

VSS

D44#

NC

J4

K9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

J5

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

NC

J6

NC

J7

NC

A7#

A4#

A9#

AP0#

NC

J8

NC

H3

J9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

D37#

D36#

D43#

NC

H4

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

H5

H6

H7

NC

VCCP

A8#

A6#

VSS

A14#

NC

H8

NC

H9

VCC

VSS

VCC

VSS

VCC

D59#

VSS

D57#

VSS

G3

H10

H11

H12

H13

G4

G5

NC

G6

NC

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

G7

NC

H14

VSS

NC

J20

D48#

VCC

VSS

VCC

NC

L1

REQ1#

DEP0#

DEP3#

DEP5#

DEP6#

VSS

L2

BPRI#

REQ4#

REQ0#

TESTHI

NC

M8

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

P1

P20

P21

P22

P23

P24

R1

L3

M9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

L4

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

N1

L5

L6

NC

L7

NC

BREQ0#

RS0#

RS2#

RS1#

PWRGOOD

NC

L8

NC

DEP7#

VSS

D63#

D62#

VSS

DBSY#

RP#

R2

L9

VSS

R3

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

M1

VCC

R4

VSS

R5

VCC

NC

R6

VSS

NC

R7

NC

VCC

D61#

D56#

D50#

D58#

D60#

VSS

REQ3#

HITM#

VSS

VREF

NC

P2

R8

NC

VSS

P3

R9

VSS

VCC

P4

DRDY#

HIT#

NC

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

VCC

NC

P5

VSS

NC

P6

VCC

NC

P7

NC

VSS

D54#

VREF

D55#

D46#

D53#

DEFER#

REQ2#

TESTHI3

LOCK#

TRDY#

N2

P8

NC

VCC

N3

P9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

VSS

N4

P10

P11

P12

P13

P14

P15

P16

P17

VCC

N5

NC

N6

NC

N7

NC

M2

N8

NC

BPM1#

VREF

DEP1#

DEP2#

M3

N9

VSS

VCC

VSS

M4

N10

N11

M5

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

M6

NC

N12

VCC

VSS

NC

P18

NC

R24

DEP4#

VSS

PICD0

VSS

TCK

M7

NC

N13

U8

P19

V15

V16

V17

V18

V19

V20

V21

V22

V23

W2

NC

T1

T2

ADS#

THERMDA

VSS

SLP#

NC

VCC

VSS

NC

W23

Y1

T3

U9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

T4

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

V2

Y2

T5

NC

Y3

SMI#

FERR#

TESTLO

NC

T6

NC

Y4

T7

NC

Y5

T8

NC

INTR

PREQ#

TESTHI

TRST#

VSS

VCCP

NC

Y6

T9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

Y7

NC

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

U1

Y8

NC

Y9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

W3

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

AA1

AA2

NC

W4

PICD1

PICCLK

TESTHI3

BP2#

BPM0#

BSEL

NC

W5

W6

W7

NC

W8

NC

W9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

BP3#

VSS

PRDY#

BINIT#

VSS

AERR#

VCCP

THERMDC

NC

V3

NC

V4

TMS

VCCP

NC

V5

NC

V6

NC

V7

NC

VCCP

VSS

STPCLK#

A20M#

V8

NC

U2

V9

VCC

VSS

VCC

U3

V10

V11

NC

U4

NC

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

U5

TDI

NC

V12

VSS

VCC

VSS

NC

W20

NC

AA3

INIT#

IERR#

NC

U6

V13

W21

VSS

NC

AA4

AA5

AD24

AE1

U7

NC

V14

W22

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AB1

NC

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AC1

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AD1

NC

VSS

NC

AE2

NC

AE3

NC

AE4

NC

VSS

VCCP

VCC

TESTHI2

NC

AE5

NC

AE6

NC

AE7

NC

AD2

AE8

NC

AD3

AE9

NC

AD4

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AF1

NC

AD5

NC

AD6

NC

FLUSH#

TESTHI2

NC

AD7

NC

AC2

AD8

NC

AC3

AD9

NC

AC4

VSS

TESTLO

NC

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

NC

AC5

NC

NMI

TDO

IGNNE#

NC

AC6

NC

AC7

NC

AB2

AC8

NC

AB3

AC9

NC

AB4

VCCP

NC

AC10

AC11

AC12

AC13

NC

AB5

NC

AB6

NC

AB7

NC

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Table 5.3 Signal Listing in Order by Pin/Ball Number

Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name Pin/Ball Signal Name

No.

AB8

NC

AC14

AC15

AC16

AC17

AF11

AF12

AF13

AF14

AF15

NC

AD20

AD21

AD22

AD23

AF16

AF17

AF18

AF19

AF20

NC

AF2

VSS

BCLK

VSS

PLL2

NC

AB9

AB10

AB11

AF6

NC

AF3

NC

AF4

NC

AF5

PLL1

VSS

NC

AF21

AF22

AF23

AF24

AF7

NC

AF8

NC

AF9

NC

AF10

NC

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Table 5.4 Signal Listing in Order by Signal Name

Pin/Ball

No.

Signal

Name

Signal Buffer Type

Pin/Ball

No.

Signal

Name

Signal Buffer Type

F2

A3#

Low Power GTL+ I/O

C7

A33#

Low Power GTL+ I/O

2.5V CMOS Input

H3

F4

A4#

A7

A34#

A35#

A20M#

ADS#

AERR#

AP0#

AP1#

BCLK

BERR#

BINIT#

BNR#

BP2#

BP3#

BPM0#

BPM1#

BPRI#

BREQ0#

BSEL

D0#

A5#

B3

G3

H2

G2

H4

F5

A6#

AA2

T2

A7#

Low Power GTL+ I/O

Processor Clock Input

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

2.5V CMOS Input

A8#

U1

A9#

H5

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

J4

F1

AF3

C9

E2

E3

G5

F3

T23

J2

U23

T20

U24

R20

L2

E1

C5

E9

B4

D7

E7

B5

D6

B7

C4

A6

D9

D1

A4

B6

C6

E10

R1

V2

A15

C16

B18

A19

C15

A18

B15

B19

E14

D16

C17

Low Power GTL+ I/O

D1#

D2#

D3#

D4#

D5#

D6#

D7#

D8#

D9#

D10#

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Table 5.4 Signal Listing in Order by Signal Name

Pin/Ball

No.

Signal

Name

Signal Buffer Type

Pin/Ball

No.

Signal

Name

Signal Buffer Type

E16

E15

B20

C18

B16

A22

B17

A21

C19

D18

C20

D19

E18

C21

E19

B21

C22

D22

C23

E17

B22

D21

D24

E22

C24

F21

F20

G20

E23

J24

D11#

Low Power GTL+ I/O

J22

H21

F22

G22

H20

L23

J21

J20

H23

M22

H22

J23

L24

L20

L22

M21

K23

M23

K20

M24

M20

N23

N22

P2

D41#

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

Low Power GTL+ Input

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

DEP5#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBSY#

DEFER#

DEP0#

DEP1#

DEP2#

DEP3#

DEP4#

RS0#

M1

P20

R22

R23

P21

R24

R2

P22

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Table 5.4 Signal Listing in Order by Signal Name

Pin/Ball

No.

Signal

Name

Signal Buffer Type

Pin/Ball

No.

Signal

Name

Signal Buffer Type

P23

N20

P4

DEP6#

Low Power GTL+ I/O

Low Power GTL+ Control

2.5V Open Drain Output

2.5V CMOS Input

R4

RS1#

Low Power GTL+ Input

2.5V CMOS Input

JTAG Clock Input

JTAG Input

DEP7#

DRDY#

EDGCTRLN

FERR#

FLUSH#

HIT#

R3

RS2#

J3

RSP#

B2

T5

SLP#

Y4

Y3

AA1

Y2

U5

SMI#

AC1

P5

STPCLK#

TCK

Low Power GTL+ I/O

2.5V Open Drain Output

2.5V CMOS Input

N3

HITM#

IERR#

TDI

AA4

AB2

AA3

V21

M4

AB1

B8

TDO

JTAG Output

IGNNE#

INIT#

TESTHI

TESTHI2

TESTHI3

GTL+ Test Input

CMOS Test Input

GTL+ Test Input

2.5V CMOS Input

L5

INTR

2.5V CMOS Input

V23

AC2

AD4

J1

LOCK#

NMI

Low Power GTL+ I/O

2.5V CMOS Input

AA24

U21

W23

U20

AF6

AF5

T22

V22

R5

PICCLK

PICD0

APIC Clock Input

2.5V Open Drain I/O

PLL Analog Voltage

Low Power GTL+ Output

2.5V CMOS Input

K2

PICD1

K5

PLL1

M3

U22

PLL2

PRDY#

PREQ#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

RESET#

RP#

D3

D4

E4

TESTLO

THERMDA

THERMDC

TMS

Test Input

2.5V CMOS Input

Test Input

L4

Low Power GTL+ I/O

Low Power GTL+ Input

Low Power GTL+ I/O

GTL+ Reference Voltage

Y5

AC5

T3

Test Input

L1

Test Input

M2

Thermal Diode Anode

Thermal Diode Cathode

JTAG Input

N2

U3

V4

M5

W2

J5

L3

C8

TRDY#

TRST#

Low Power GTL+ Input

JTAG Input

P3

D10

VREF

GTL+ Reference Voltage

D15

VREF

GTL+ Reference Voltage

L21

VREF

GTL+ Reference Voltage

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Table 5.4 Signal Listing in Order by Signal Name

Pin/Ball

No.

Signal

Name

Signal Buffer Type

Pin/Ball

No.

Signal

Name

Signal Buffer Type

E8

VREF

GTL+ Reference Voltage

N5

VREF

GTL+ Reference Voltage

E21

R21

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Table 5.5 Voltage and No-Connect Pin/Ball Locations

Ball Numbers

Signal

Name

NC

A10, A12, A13, A24, B9, B10, B11, B12, B13, B14, C2, C3, C10, C11, C12, C13, C14, D12, D13,

E6, E11, E12, E13, E24, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F23, G6,

G7, G8, G17, G18, G19, G23, H6, H7, H8, H17, H18, H19, J6, J7, J8, J17, J18, J19, K6, K7, K8,

K17, K18, K19, L6, L7, L8, L17, L18, L19, M6, M7, M8, M17, M18, M19, N6, N7, N8, N17, N18, N19,

P6, P7, P8, P17, P18, P19, R6, R7, R8, R17, R18, R19, T6, T7, T8, T17, T18, T19, U4, U6, U7, U8,

U17, U18, U19, V3, V6, V7, V8, V17, V18, V19, V20, W6, W7, W8, W17, W18, W19, W20, Y6,

Y7, Y8, Y17, Y18, Y19, Y20, Y21, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13,

AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AA23, AB3, AB5, AB6, AB7,

AB8, AB9, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21,

AB22, AB23, AB24, AC3, AC6, AC7, AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16,

AC17, AC18, AC19, AC20, AC21, AC22, AD5, AD6, AD7, AD8, AD9, AD10, AD11, AD12, AD13,

AD14, AD15, AD16, AD17, AD18, AD19, AD20, AD21, AD22, AD23, AD24, AE8, AE9, AE10,

AE11, AE12, AE13, AE14, AE15, AE16, AE17, AE18, AE19, AE20, AE21, AE22, AE23, AE24, AF1,

AF8, AF9, AF10, AF11, AF12, AF13, AF14, AF15, AF16, AF17, AF18, AF19, AF20, AF21, AF22,

AF23, AF24

VCC

G10, G12, G14, G16, H9, H11, H13, H15, J10, J12, J14, J16, K9, K11, K13, K15, L10, L12, L14,

L16, M9, M11, M13, M15, N10, N12, N14, N16, P9, P11, P13, P15, R10, R12, R14, R16, T9, T11,

T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, W10, W12, W14, W16, Y9, Y11, Y13, Y15,

AD3

VCCP

VSS

F24, U2, V5, W5, Y22, Y23, AB4, AD2

A2, A3, A5, A8, A9, A11, A14, A16, A17, A20, A23, B1, B23, B24, C1, D2, D5, D8, D11, D14,

D17, D20, D23, E5, E20, G4, G9, G11, G13, G15, G21, H10, H12, H14, H16, J9, J11, J13, J15, K1,

K3, K4, K10, K12, K14, K16, K21, K22, K24, L9, L11, L13, L15, M10, M12, M14, M16, N1, N4, N9,

N11, N13, N15, N21, N24, P1, P10, P12, P14, P16, P24, R9, R11, R13, R15, T1, T4, T10, T12, T14,

T16, T21, T24, U9, U11, U13, U15, V10, V12, V14, V16, W3, W4, W9, W11, W13, W15, W21,

W22, Y1, Y10, Y12, Y14, Y16, Y24, AC4, AC23, AC24, AD1, AE1, AE2, AE3, AE4, AE5, AE6,

AE7, AF2, AF4, AF7

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6.

THERMAL SPECIFICATIONS

The processor die must be clean before the thermal

solution is attached or the processor may be

damaged.

In order to achieve proper cooling of the processor,

a thermal solution (for example a heat spreader,

heat pipe, or other heat transfer system) must

make firm contact to the exposed processor die.

Table 6.1 Mobile Intel Celeron^®Processor Power Specifications

Symbol

Parameter

Thermal Design Power

Min

Typ¹

Max

20.7

Unit

Notes

TDP

at 466 MHz

at 433 MHz

at 400 MHz

at 366 MHz

at 333 MHz

at 300 MHz

at 266 MHz

—

W

At 100°C ^2,3

—

19.4

13.8

13.1

11.8

11.1

9.8

W

at 266 MHz at Low Voltage

7.9

P_SGNT

Stop Grant and Auto Halt power

at 400 MHz and Below

at 433 and 466 MHz

At 50°C ³

1.25

2.00

W

P_QS

Quick Start and Sleep power

at 400 MHz and Below

at 433 and 466 MHz

0.50

0.80

W

P_DSLP

Deep Sleep power

Case Temperature

at 400 MHz and Below

at 433 and 466 MHz

0.15

0.25

W

0

100

°C

T_CASE

NOTES:

1. TDP_TYPis a recommendation based on the power dissipation of the processor while executing publicly

available software under normal operating conditions at nominal voltages. Contact your Intel Field Sales

Representative for further information.

2. TDP_MAXis a specification of the total power dissipation of the processor while executing a worst-case

instruction mix under normal operating conditions at nominal voltages. It includes the power dissipated

by all of the components within the processor. Specified by design/characterization.

3. Not 100% tested or guaranteed. The power specifications are composed of the current of the

processor on the various voltage planes. These currents are measured and specified at high

temperature in Section 3.5. The 50°C power specifications are determined by characterization of the

processor currents at higher temperatures.

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During all operating environments, the processor

ensuring the thermal diode and A/D converter

accurately tracks the processor temperature.

The designer should verify this by correlating

“sensor” output temperature with a thermocouple

placed directly on the die surface. Refer to

section 6.2 for more details.

case temperature, T_CASE, must be within the

specified range of 0°C to 100°C. An A/D

converter attached to the thermal diode can be

used to measure the processor core

temperature to ensure compliance with this

specification. The designer is responsible for

system electronics may use the diode to monitor

the die temperature of the mobile Intel Celeron

processor for thermal management purposes.

Table 6.2 and Table 6.3 provide the diode interface

and specifications.

6.1

Thermal Diode

The mobile Intel Celeron processor has an on-die

diode that can be used to monitor the die

temperature. A thermal sensor located on the

Table 6.2 Thermal Diode Interface

Ball Number

Signal Name

Signal Description

Thermal diode anode

Thermal diode cathode

THERMDA

THERMDC

T3

U3

Table 6.3. Thermal Diode Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Note 1

Notes 2, 3, 4

I_FW

Forward Bias Current

Diode Ideality Factor

5

500

mA

n

1.0000 1.0065 1.0173

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not

support or recommend operation of the thermal diode when the processor power supplies are not

within their specified tolerance range.

2. At 35°C with a forward bias of 630mV.

3. Not 100% tested. Specified by design/characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode I/V

equation:

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æ qV_D

I = I _O× ç

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nkT

e

è

ø

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·

Attach the thermocouple bead or junction to

the center of the die on the top package

surface using highly thermally conductive

cements. Intel’s laboratory testing was done

using Omega Bond (part number: OB100).

6.2

Case Temperature

To verify that the proper T

(case temperature)

CASE

is maintained for the mobile Intel Celeron processor,

it should be measured at the center of the die on

the package top surface. To minimize any

measurement errors, the following techniques are

recommended:

Thermal

grease

provides

equivalent

temperature measurement results when used

correctly but is not as mechanically resilient as

cement.

·

Use 36 gauge or finer diameter K, T, or J type

thermocouples. Intel’s laboratory testing was

done using a thermocouple made by Omega

(part number: 5TC-TTK-36-36).

·

The thermocouple should be attached at a 90°

angle as shown in Figure 6.1. A horizontal

thermocouple mount is acceptable.

V0028-00

Figure 6.1 Technique for Measuring Case Temperature

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7.

PROCESSOR INITIALIZATION

AND CONFIGURATION

7.1.2

System Bus Frequency

The current generation mobile Intel Celeron

processor will only function with a system bus

frequency of 66 MHz, but future generations

may operate at 100 MHz. Bit position 19 of the

Power-On Configuration register indicates at

which speed a processor will run. A ‘0’ in bit 19

indicates a 66-MHz bus frequency and a ‘1’

indicates a 100-MHz bus frequency.

7.1

Description

The mobile Intel Celeron processor has some

configuration options that are determined by

hardware and some that are determined by

software. The processor samples its hardware

configuration at reset, on the active-to-inactive

transition of RESET#. Most of the configuration

options for the mobile Intel Celeron processor are

identical to those of the Pentium II processor.

The Pentium^®II Processor Developer’s Manual

(order number 243502) describes these

configuration options. New configuration options

for the mobile Intel Celeron processor are

described in the remainder of this section.

7.1.3

APIC Disable

The APIC has been removed as a feature of the

mobile Intel Celeron processor. The PICCLK and

PICD[1:0] signals must be tied to V_SSwith a 1KW

resistor to disable the APIC. Driving PICD0 low at

reset has the effect of clearing the APIC Global

Enable bit in the APIC Base MSR. This bit is

normally set when the processor is reset, but

when it is cleared the APIC is completely

disabled until the next reset.

7.1.1

Quick Start Enable

The processor normally enters the Stop Grant

state when the STPCLK# signal is asserted, but

it will enter the Quick Start state instead if A15#

is sampled active on the RESET# signal’s active-

to-inactive transition. The Quick Start state

supports snoops from the bus priority device like

the Stop Grant state, but it does not support

symmetric master snoops, nor is the latching of

interrupts supported. A ‘1’ in bit position 5 of the

Power-On Configuration register indicates that

the Quick Start state has been enabled.

7.2

Clock Frequencies and Ratios

The mobile Intel Celeron processor uses a clock

design in which the bus clock is multiplied by a

ratio to produce the processor’s internal (or

“core”) clock. The ratio used is programmed into

the processor during Reset.

Section 3.3

describes how this is done. The bus ratio

programmed into the processor is visible in bit

positions 22 to 25 of the Power-On Configuration

register. Table 3.4 shows the 4-bit codes in the

Power-On Configuration register and their

corresponding bus ratios.

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8.

PROCESSOR INTERFACE

ADS# (I/O - Low Power GTL+)

The ADS# (Address Strobe) signal is asserted to

indicate the validity of a transaction address on the

A[35:3]# signals. Both bus agents observe the

ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop, or

deferred reply ID match operations associated with

the new transaction. This signal must be connected

to the appropriate balls on both agents on the

system bus.

8.1

Alphabetical Signal Reference

A[35:3]# (I/O - Low Power GTL+)

36

The A[35:3]# (Address) signals define a 2 -byte

physical memory address space. When ADS# is

active, these signals transmit the address of a

transaction; when ADS# is inactive, these signals

transmit transaction information. These signals

must be connected to the appropriate balls of both

agents on the system bus. The A[35:24]# signals

are protected with the AP1# parity signal, and the

A[23:3]# signals are protected with the AP0# parity

signal.

AERR# (I/O - Low Power GTL+)

The AERR# (Address Parity Error) signal is

observed and driven by both system bus agents

and if used, must be connected to the appropriate

balls of both agents on the system bus. AERR#

observation is optionally enabled during power-on

On the active-to-inactive transition of RESET#, each

processor bus agent samples A[35:3]# signals to

determine its power-on configuration. See Section

7 of this document and the Pentium^®II Processor

Developer’s Manual for details.

configuration; if enabled,

a valid assertion of

AERR# aborts the current transaction.

If AERR# observation is disabled during power-on

configuration, a central agent may handle an

assertion of AERR# as appropriate to the error

handling architecture of the system.

A20M# (I - 2.5V tolerant)

If the A20M# (Address-20 Mask) input signal is

asserted, the processor masks physical address

bit 20 (A20#) before looking up a line in any internal

cache and before driving a read/write transaction

on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-Mbyte

boundary. Assertion of A20M# is only supported in

real mode.

The AERR# processor bus pin is removed as a

processor feature for mobile Intel Celeron

processor at 400 MHz and above. The pin must still

be terminated to Vcc through a 120W pull-up

resistor. But the processor must not be configured

to drive or observe the pin.

AP[1:0]# (I/O - Low Power GTL+)

During active RESET#, the processor begins

sampling the A20M#, IGNNE#, INTR, and NMI values

to determine the ratio of core-clock frequency to

bus-clock frequency (see Table 3.4). On the

active-to-inactive transition of RESET#, the

processor latches these signals and freezes the

frequency ratio internally. System logic must then

release these signals for normal operation.

The AP[1:0]# (Address Parity) signals are driven by

the request initiator along with ADS#, A[35:3]#,

REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0#

covers A[23:3]#. A correct parity signal is high if an

even number of covered signals are low and low if

an odd number of covered signals are low. This

allows parity to be high when all the covered

signals are high. AP[1:0]# should be connected to

the appropriate balls on both agents on the system

bus.

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count information is lost. The L1 and L2 caches are

BCLK (I - 2.5V tolerant)

not affected.

The BCLK (Bus Clock) signal determines the

system bus frequency. Both system bus agents

must receive this signal to drive their outputs and

latch their inputs on the BCLK rising edge. All

external timing parameters are specified with

respect to the BCLK signal.

If BINIT# is disabled during power-on configuration,

a central agent may handle an assertion of BINIT#

as appropriate to the Machine Check Architecture

(MCA) of the system.

BNR# (I/O - Low Power GTL+)

BERR# (I/O - Low Power GTL+)

The BNR# (Block Next Request) signal is used to

assert a bus stall by any bus agent that is unable to

accept new bus transactions. During a bus stall,

the current bus owner cannot issue any new

transactions.

The BERR# (Bus Error) signal is asserted to

indicate an unrecoverable error without a bus

protocol violation. It may be driven by either system

bus agent and must be connected to the

appropriate balls of both agents, if used. However,

mobile Intel Celeron processors do not observe

assertions of the BERR# signal.

Since multiple agents may need to request a bus

stall simultaneously, BNR# is a wired-OR signal

which must be connected to the appropriate balls

of both agents on the system bus. In order to avoid

wire-OR errors associated with simultaneous edge

transitions driven by multiple drivers, BNR# is

activated on specific clock edges and sampled on

specific clock edges.

BERR# assertion conditions are defined by the

system configuration. Configuration options enable

the BERR# driver as follows:

·

Enabled or disabled

Asserted optionally for internal errors along

with IERR#

BP[3:2]# (I/O - Low Power GTL+)

·

Asserted optionally by the request initiator of a

bus transaction after it observes an error

The BP[3:2]# (Breakpoint) signals are the System

Support group Breakpoint signals. They are outputs

from the processor that indicate the status of

breakpoints.

Asserted by any bus agent when it observes

an error in a bus transaction

BINIT# (I/O - Low Power GTL+)

BPM[1:0]# (I/O - Low Power GTL+)

The BINIT# (Bus Initialization) signal may be

observed and driven by both system bus agents

and must be connected to the appropriate balls of

both agents, if used. If the BINIT# driver is enabled

during the power-on configuration, BINIT# is

asserted to signal any bus condition that prevents

reliable future information.

The BPM[1:0]# (Breakpoint Monitor) signals are

breakpoint and performance monitor signals. They

are outputs from the processor that indicate the

status of breakpoints and programmable counters

used for monitoring processor performance.

BPRI# (I - Low Power GTL+)

If BINIT# is enabled during power-on configuration

and BINIT# is sampled asserted, all bus state

machines are reset and any data which was in

transit is lost. All agents reset their rotating ID for

bus arbitration to the state after reset, and internal

The BPRI# (Bus Priority Request) signal is used to

arbitrate for ownership of the system bus. It must

be connected to the appropriate balls on both

agents on the system bus. Observing BPRI# active

(as asserted by the priority agent) causes the

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processor to stop issuing new requests, unless

DEFER# (I - Low Power GTL+)

such requests are part of an ongoing locked

operation. The priority agent keeps BPRI# asserted

until all of its requests are completed and then

releases the bus by deasserting BPRI#.

The DEFER# (Defer) signal is asserted by an agent

to indicate that the transaction cannot be

guaranteed in-order completion. Assertion of

DEFER# is normally the responsibility of the

addressed memory agent or I/O agent. This signal

must be connected to the appropriate balls on both

agents on the system bus.

BREQ0# (I/O - Low Power GTL+)

The BREQ0# (Bus Request) signal is a processor

Arbitration Bus signal. The processor indicates that

it wants ownership of the system bus by asserting

the BREQ0# signal.

DEP[7:0]# (I/O - Low Power GTL+)

The DEP[7:0]# (Data Bus ECC Protection) signals

provide optional ECC protection for the data bus.

They are driven by the agent responsible for

driving D[63:0]# and must be connected to the

appropriate balls on both agents on the system bus

if they are used. During power-on configuration,

DEP[7:0]# signals can be enabled for ECC checking

or disabled for no checking.

During power-up configuration, the central agent

must assert the BREQ0# bus signal. The processor

samples BREQ0# on the active-to-inactive transition

of RESET#.

BSEL (I - 2.5V Tolerant)

The BSEL (System Bus Speed Select) signal is

used to configure the processor for the system

bus frequency. A ‘1’ on this signal configures the

DRDY# (I/O - Low Power GTL+)

processor for 100-MHz operation and

configures it for 66-MHz operation. This signal must

be connected to V_SS

a ‘0’

The DRDY# (Data Ready) signal is asserted by the

data driver on each data transfer, indicating valid

data on the data bus. In a multi-cycle data transfer,

DRDY# can be deasserted to insert idle clocks.

This signal must be connected to the appropriate

balls on both agents on the system bus.

.

D[63:0]# (I/O - Low Power GTL+)

The D[63:0]# (Data) signals are the data signals.

These signals provide a 64-bit data path between

both system bus agents, and must be connected to

the appropriate balls on both agents. The data

driver asserts DRDY# to indicate a valid data

transfer.

EDGCTRLN (Analog)

This signal is used to configure the edge rate of the

Low Power GTL+ output buffers. Connect the

EDGCTRLN (Edge Rate Control N-FET) signal to V_CC

with a 51-W, 1-% resistor.

DBSY# (I/O - Low Power GTL+)

FERR# (O - 2.5V Tolerant Open-drain)

The DBSY# (Data Bus Busy) signal is asserted by

the agent responsible for driving data on the

system bus to indicate that the data bus is in use.

The data bus is released after DBSY# is

deasserted. This signal must be connected to the

appropriate balls on both agents on the system

bus.

The FERR# (Floating-point Error) signal is asserted

when the processor detects an unmasked floating-

point error. FERR# is similar to the ERROR# signal

on the Intel387 coprocessor and is included for

compatibility with systems using DOS-type floating-

point error reporting.

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error. IGNNE# has no affect when the NE bit in

FLUSH# (I - 2.5V Tolerant)

control register 0 (CR0) is set.

When the FLUSH# (Flush) input signal is asserted,

the processor writes back all internal cache lines in

the Modified state and invalidates all internal cache

lines. At the completion of a flush operation, the

During active RESET#, the processor begins

sampling the A20M#, IGNNE#, INTR, and NMI values

to determine the ratio of core-clock frequency to

bus-clock frequency (see Table 3.4). On the

active-to-inactive transition of RESET#, the

processor latches these signals and freezes the

frequency ratio internally. System logic must then

release these signals for normal operation.

processor

issues

a

Flush

Acknowledge

transaction. The processor stops caching any new

data while the FLUSH# signal remains asserted.

On the active-to-inactive transition of RESET#, each

processor bus agent samples FLUSH# to determine

its power- on configuration.

INIT# (I - 2.5V Tolerant)

The INIT# (Initialization) signal is asserted to reset

integer registers inside the processor without

affecting the internal (L1 or L2) caches or the

floating-point registers. The processor begins

execution at the power-on reset vector configured

during power-on configuration. The processor

continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous input.

HIT# (I/O - Low Power GTL+), HITM#

(I/O - Low Power GTL+)

The HIT# (Snoop Hit) and HITM# (Hit Modified)

signals convey transaction snoop operation

results, and must be connected to the appropriate

balls on both agents on the system bus. Either bus

agent can assert both HIT# and HITM# together to

indicate that it requires a snoop stall, which can be

continued by reasserting HIT# and HITM# together.

If INIT# is sampled active on RESET#'s active-to-

inactive transition, then the processor executes its

built-in self test (BIST).

IERR# (O - 2.5V Tolerant Open-drain)

INTR (I - 2.5V Tolerant)

The IERR# (Internal Error) signal is asserted by the

processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the system bus. This

transaction may optionally be converted to an

external error signal (e.g., NMI) by system logic.

The processor will keep IERR# asserted until it is

handled in software or with the assertion of

RESET#, BINIT, or INIT#.

The INTR (Interrupt) signal indicates that an external

interrupt has been generated. The interrupt is

maskable using the IF bit in the EFLAGS register. If

the IF bit is set, the processor vectors to the

interrupt handler after completing the current

instruction execution. Upon recognizing the

interrupt request, the processor issues a single

Interrupt Acknowledge (INTA) bus transaction.

INTR must remain active until the INTA bus

transaction to guarantee its recognition. INTR must

be deasserted for a minimum of two clocks to

guarantee its inactive recognition.

IGNNE# (I - 2.5V Tolerant)

The IGNNE# (Ignore Numeric Error) signal is

asserted to force the processor to ignore a

numeric error and continue to execute non-control

floating-point instructions. If IGNNE# is deasserted,

the processor freezes on a non-control floating-

point instruction if a previous instruction caused an

During active RESET#, the processor begins

sampling the A20M#, IGNNE#, INTR, and NMI values

to determine the ratio of core-clock frequency to

bus-clock frequency (see Table 3.4). On the

active-to-inactive transition of RESET#, the

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processor latches these signals and freezes the

PICCLK (I - 2.5V Tolerant)

frequency ratio internally. System logic must then

release these signals for normal operation.

The PICCLK (APIC Clock) signal is an input clock to

the processor and system logic or I/O APIC that is

required for operation of the processor, system

logic and I/O APIC components on the APIC bus.

LOCK# (I/O - Low Power GTL+)

The LOCK# (Lock) signal indicates to the system

that

a sequence of transactions must occur

PICD[1:0] (I/O - 2.5V Tolerant Open-drain)

atomically. This signal must be connected to the

appropriate balls on both agents on the system

The PICD[1:0] (APIC Data) signals are used for bi-

directional serial message passing on the APIC bus.

They must be connected to the appropriate balls of

all APIC bus agents, including the processor and

the system logic or I/O APIC components. If the

PICD0 signal is sampled low on the active-to-

inactive transition of the RESET# signal, then the

APIC is hardware disabled.

bus. For

a locked sequence of transactions,

LOCK# is asserted from the beginning of the first

transaction through the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate

for bus ownership, it waits until it observes LOCK#

deasserted. This enables the processor to retain

bus ownership throughout the bus locked operation

and guarantee the atomicity of lock.

PRDY# (O - Low Power GTL+)

The PRDY# (Probe Ready) signal is a processor

output used by debug tools to determine processor

debug readiness.

NMI (I - 2.5V Tolerant)

The NMI (Non-Maskable Interrupt) indicates that an

external interrupt has been generated. Asserting

NMI causes an interrupt with an internally supplied

vector value of 2. An external interrupt-

acknowledge transaction is not generated. If NMI is

asserted during the execution of an NMI service

routine, it remains pending and is recognized after

the IRET is executed by the NMI service routine. At

most, one assertion of NMI is held pending.

PREQ# (I - 2.5V Tolerant)

The PREQ# (Probe Request) signal is used by

debug tools to request debug operation of the

processor.

PWRGOOD (I - 2.5V Tolerant)

PWRGOOD (Power Good) is a 2.5V tolerant input.

The processor requires this signal to be a clean

NMI is rising-edge sensitive. Active and inactive

pulse widths must be a minimum of two clocks.

indication that clocks and the power supplies (V_CC

,

V_CCPetc.) are stable and within their

,

During active RESET#, the processor begins

sampling the A20M#, IGNNE#, INTR, and NMI values

to determine the ratio of core-clock frequency to

bus-clock frequency (see Table 3.4). On the

active-to-inactive transition of RESET#, the

processor latches these signals and freezes the

frequency ratio internally. System logic must then

release these signals for normal operation.

specifications. Clean implies that the signal will

remain low, (capable of sinking leakage current)

and without glitches, from the time that the power

supplies are turned on, until they come within

specification. The signal will then transition

monotonically to a high (2.5V) state. Figure 8.1

illustrates the relationship of PWRGOOD to other

system signals. PWRGOOD can be driven inactive

at any time, but clocks and power must again be

stable before the rising edge of PWRGOOD. It must

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also meet the minimum pulse width specified in

Table 3.14 (Section 3.5), and be followed by a 1 ms

RESET# pulse.

The PWRGOOD signal, which must be supplied to

the processor, is used to protect internal circuits

against voltage sequencing issues. The PWRGOOD

signal should be driven high throughout boundary

scan operation.

REQ[4:0]# (I/O - Low Power GTL+)

The REQ[4:0]# (Request Command) signals must be

connected to the appropriate balls on both agents

on the system bus. They are asserted by the

current bus owner when it drives A[35:3]# to

define the currently active transaction type.

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For a power-on type reset, RESET# must stay

active for at least 1 msec after V_CCand BCLK have

reached their proper DC and AC specifications and

after PWRGOOD has been asserted. When

observing active RESET#, all bus agents will

deassert their outputs within two clocks.

RESET# (I - Low Power GTL+)

Asserting the RESET# signal resets the processor

to a known state and invalidates the L1 and L2

caches without writing back Modified (M state)

lines.

BCLK

V_CC

,

V_CCP

,

V_REF

V_IH,min

PWRGOOD

1 msec

RESET#

D0026-00

Figure 8.1 PWRGOOD Relationship at Power-On

A number of bus signals are sampled at the active-

to-inactive transition of RESET# for the power-on

configuration. The configuration options are

described in Section 7 and in the Pentium^®II

Processor Developer’s Manual.

RP# (I/O - Low Power GTL+)

The RP# (Request Parity) signal is driven by the

request initiator and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to

the appropriate balls on both agents on the system

bus.

Unless its outputs are tri-stated during power-on

configuration, after an active-to-inactive transition

of RESET#, the processor optionally executes its

built-in self-test (BIST) and begins program

A correct parity signal is high if an even number of

covered signals are low and low if an odd number

of covered signals are low. This definition allows

parity to be high when all covered signals are high.

execution

at

reset-vector

000FFFF0H

or

FFFFFFF0H. RESET# must be connected to the

appropriate balls on both agents on the system

bus.

RS[2:0]# (I - Low Power GTL+)

The RS[2:0]# (Response Status) signals are driven

by the response agent (the agent responsible for

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completion of the current transaction) and must be

connected to the appropriate balls on both agents

on the system bus.

processor begins program execution from the SMM

handler.

STPCLK# (I - 2.5V Tolerant)

RSP# (I - Low Power GTL+)

The STPCLK# (Stop Clock) signal, when asserted,

causes the processor to enter a low -power Stop

Grant state. The processor issues a Stop Grant

Acknowledge special transaction, and stops

providing internal clock signals to all units except

the bus and APIC units. The processor continues to

snoop bus transactions and service interrupts

while in the Stop Grant state. When STPCLK# is

deasserted, the processor restarts its internal

clock to all units and resumes execution. The

assertion of STPCLK# has no effect on the bus

clock.

The RSP# (Response Parity) signal is driven by the

response agent (the agent responsible for

completion of the current transaction) during

assertion of RS[2:0]#. RSP# provides parity

protection for RS[2:0]#. RSP# should be connected

to the appropriate balls on both agents on the

system bus.

A correct parity signal is high if an even number of

covered signals are low and low if an odd number

of covered signals are low. During Idle state of

RS[2:0]# (RS[2:0]#=000), RSP# is also high since it

is not driven by any agent guaranteeing correct

parity.

TCK (I - 2.5V Tolerant)

The TCK (Test Clock) signal provides the clock

input for the test bus (also known as the test

access port).

SLP# (I - 2.5V Tolerant)

The SLP# (Sleep) signal, when asserted in the Stop

Grant state, causes the processor to enter the

Sleep state. During the Sleep state, the processor

stops providing internal clock signals to all units,

leaving only the Phase-Locked Loop (PLL) still

running. The processor will not recognize snoop

and interrupts in the Sleep state. The processor will

only recognize changes in the SLP#, STPCLK#, and

RESET# signals while in the Sleep state.

TDI (I - 2.5V Tolerant)

The TDI (Test Data In) signal transfers serial test

data to the processor. TDI provides the serial input

needed for JTAG support.

TDO (O - 2.5V Tolerant Open-drain)

The TDO (Test Data Out) signal transfers serial test

data from the processor. TDO provides the serial

output needed for JTAG support.

If SLP# is deasserted, the processor exits Sleep

state and returns to the Stop Grant state in which it

restarts its internal clock to the bus and APIC

processor units.

THERMDA, THERMDC (Analog)

SMI# (I - 2.5V Tolerant)

The THERMDA (Thermal Diode Anode) and

THERMDC (Thermal Diode Cathode) signals connect

to the anode and cathode of the on-die thermal

diode.

The SMI# (System Management Interrupt) is

asserted asynchronously by system logic. On

accepting a System Management interrupt, the

processor saves the current state and enters

System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the

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TMS (I - 2.5V Tolerant)

TRST# (I - 2.5V Tolerant)

The TMS (Test Mode Select) signal is a JTAG

support signal used by debug tools.

The TRST# (Test Reset) signal resets the Test

Access Port (TAP) logic. Mobile Intel Celeron

processors do not self- reset during power on;

therefore, it is necessary to drive this signal low

during power-on reset.

TRDY# (I - Low Power GTL+)

The TRDY# (Target Ready) signal is asserted by

the target to indicate that the target is ready to

receive write or implicit writeback data transfer.

TRDY# must be connected to the appropriate balls

on both agents on the system bus.

8.2

Signal Summaries

Table 8.1 through Table 8.4 list the attributes of the

processor input, output, and I/O signals.

Table 8.1 Input Signals

Clock Signal Group

Name

A20M#

Active Level

Low

Qualified

Always

Asynch

—

CMOS

BCLK

High

Low

System Bus

CMOS

Always

BPRI#

BCLK

Always

DEFER#

FLUSH#

IGNNE#

INIT#

Low

BCLK

Always

Low

Asynch

—

Always

Low

CMOS

Always

Low

System Bus

CMOS

Always

INTR

High

Low

APIC disabled mode

Always

NMI

CMOS

PICCLK

PREQ#

PWRGOOD

RESET#

RS[2:0]#

RSP#

APIC

Asynch

BCLK

Implementation

System Bus

Implementation

Always

High

Low

Always

Low

BCLK

Always

Low

BCLK

Always

BSEL

High

Low

Asynch

Always

SLP#

Stop Grant state

INTEL CORPORATION

73

MOBILE INTEL ^®CELERON^®PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT

466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

Table 8.1 Input Signals

Name

Active Level

Low

Clock

Asynch

—

Signal Group

CMOS

Qualified

Always

SMI#

STPCLK#

TCK

Low

Implementation

JTAG

Always

High

TDI

TCK

JTAG

TMS

TCK

JTAG

TRDY#

TRST#

Low

BCLK

Asynch

System Bus

JTAG

Response phase

Table 8.2 Output Signals

Name

Active Level

Clock

Asynch

BCLK

Signal Group

Open-Drain

FERR#

IERR#

PRDY#

TDO

Low

High

Open-Drain

Implementation

JTAG

TCK

Table 8.3 Input/Output Signals (Single Driver)

Name

Active Level

Low

Clock

BCLK

Signal Group

System Bus

Qualified

ADS#, ADS#+1

Always

A[35:3]#

ADS#

Low

AP[1:0]#

BREQ0#

BP[3:2]#

Low

ADS#, ADS#+1

Always

Low

Always

BPM[1:0]#

D[63:0]#

Low

Always

Low

DRDY#

74

INTEL CORPORATION

MOBILE INTEL ^®CELERON^®PROCESSOR IN MICRO-PGA AND BGA PACKAGES AT

466 MHZ, 433 MHZ, 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET

Table 8.3 Input/Output Signals (Single Driver)

Name

DBSY#

Active Level

Low

Clock

BCLK

Signal Group

System Bus

Qualified

Always

DEP[7:0]#

DRDY#

LOCK#

REQ[4:0]#

RP#

Low

DRDY#

Low

Always

Low

Always

Low

ADS#, ADS#+1

Low

Table 8.4 Input/Output Signals (Multiple Driver)

Name

Active Level

Low

Clock

BCLK

PICCLK

Signal Group

System Bus

APIC

Qualified

AERR#

BERR#

BINIT#

BNR#

ADS#+3

Low

Always

Low

HIT#

Low

HITM#

PICD[1:0]

Low

High

INTEL CORPORATION

75


型号：	KC80524KX466128SL3KC
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 466MHz, PBGA615
文件：	总81页 (文件大小：461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KC80524KX466128SL3KC [INTEL]

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