KC80526GY650256 [INTEL]

Microprocessor, 64-Bit, 650MHz, CMOS, PBGA495, PLASTIC, BGA-495;


型号：	KC80526GY650256
厂家：	INTEL
描述：	Microprocessor, 64-Bit, 650MHz, CMOS, PBGA495, PLASTIC, BGA-495 时钟外围集成电路
文件：	总84页 (文件大小：450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Mobile Pentium III Processor in

BGA2 and Micro-PGA2 Packages

Datasheet

Featuring Intel® SpeedStep™ Technology: 600/500 MHz, and 650/500 MHz

Featuring Fixed Frequency: 400 MHz, 450 MHz, and 500 MHz

Product Features

Processor core/bus speeds:

BGA2 and Micro-PGA2 packaging

technologies

Single frequency at 1.60V: 450/100 MHz

and 500/100 MHz

—

Supports thin form factor notebook

designs

Single frequency at 1.35V: 400/100 MHz

and 500/100 MHz

Featuring Intel^®SpeedStep^TM

technology: 600/100 MHz and 650/100

MHz ( Maximum Performance Mode at

1.60V) and 500/100 MHz (Battery

Optimized Performance Mode at 1.35V)

—

Exposed die enables more efficient

heat dissipation

Fully compatible with previous Intel

microprocessors

—

Binary compatible with all

applications

Supports the Intel Architecture with Dynamic

Execution

—

Support for MMX™ technology

Support for Streaming SIMD

Extensions

On-die primary 16-Kbyte instruction cache

and 16-Kbyte write-back data cache

Power Management Features

On-die second level cache (256-Kbyte)

Integrated GTL+ termination

—

Quick Start and Deep Sleep modes

provide low power dissipation

Integrated math co-processor

Intel Processor Serial Number

On-die thermal diode

Order Number: XXXXX

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."

Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from

future changes to them.

The Intel mobile Pentium III processor may contain design defects or errors known as errata that may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be

obtained by calling1-800-548-4725 or by visiting Intel’s web site at http://www.intel.com

*Other brands and names are the property of their respective owners.

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

CONTENTS

1.0

Introduction ..................................................................................................1

1.1

1.2

1.3

Overview............................................................................................4

Terminology .......................................................................................4

References.........................................................................................5

2.0

Mobile Pentium III Processor Features.........................................................6

2.1

New Features in the Mobile Pentium III Processor................................6

2.1.1 On-die GTL+ Termination........................................................6

2.1.2 Streaming SIMD Extensions ....................................................6

2.1.3 Intel SpeedStep Technology....................................................6

2.1.4 Signal Differences Between the Mobile Pentium II Processor

and the Mobile Pentium III Processor........................................6

2.2

Power Management............................................................................7

2.2.1 Clock Control Architecture.......................................................7

2.2.2 Normal State..........................................................................7

2.2.3 Auto Halt State.......................................................................7

2.2.4 Stop Grant State.....................................................................8

2.2.5 Quick Start State ....................................................................9

2.2.6 HALT/Grant Snoop State.........................................................9

2.2.7 Sleep State.............................................................................9

2.2.8 Deep Sleep State.................................................................. 10

2.2.9 Operating System Implications of Low-power States ............... 10

2.2.10 Intel SpeedStep Technology.................................................. 10

GTL+ Signals ................................................................................... 11

Mobile Pentium III Processor CPUID.................................................. 11

2.3

2.4

3.0

Electrical Specifications.............................................................................. 12

3.1

Processor System Signals................................................................. 12

3.1.1 Power Sequencing Requirements.......................................... 13

3.1.2 Test Access Port (TAP) Connection....................................... 13

3.1.3 Catastrophic Thermal Protection............................................ 14

3.1.4 Unused Signals .................................................................... 14

3.1.5 Signal State in Low-power States........................................... 14

3.1.5.1

3.1.5.2

3.1.5.3

System Bus Signals ............................................. 14

CMOS and Open-drain Signals ............................. 14

Other Signals....................................................... 15

3.2

Power Supply Requirements ............................................................. 15

3.2.1 Decoupling Recommendations .............................................. 15

3.2.2 Voltage Planes ..................................................................... 15

System Bus Clock and Processor Clocking......................................... 16

Intel SpeedStep Technology.............................................................. 16

Maximum Ratings ............................................................................. 16

DC Specifications ............................................................................. 17

AC Specifications.............................................................................. 21

3.3

3.4

3.5

3.6

3.7

3.7.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC

Specifications ....................................................................... 21

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

4.0

System Signal Simulations......................................................................... 34

4.1

System Bus Clock (BCLK) and PICCLK AC Signal Quality

Specifications ................................................................................... 34

GTL+ AC Signal Quality Specifications............................................... 35

Non-GTL+ Signal Quality Specifications ............................................. 38

4.3.1 PWRGOOD Signal Quality Specifications............................... 39

4.2

4.3

5.0

Mechanical Specifications.......................................................................... 40

5.1

5.2

5.3

Surface-mount BGA2 Package Dimensions........................................ 40

Socketable Micro-PGA2 Package Dimensions.................................... 43

Signal Listings .................................................................................. 46

6.0

7.0

Thermal Specifications ............................................................................... 55

6.1 Thermal Diode.................................................................................. 56

Processor Initialization and Configuration.................................................. 58

7.1

Description....................................................................................... 58

7.1.1 Quick Start Enable................................................................ 58

7.1.2 System Bus Frequency......................................................... 58

7.1.3 APIC Enable......................................................................... 58

Clock Frequencies and Ratios ........................................................... 58

7.2

8.0

Processor Interface..................................................................................... 59

8.1

8.2

Alphabetical Signal Reference........................................................... 59

Signal Summaries............................................................................. 71

Appendix A: PLL RLC Filter Specification.............................................................. 73

A.1

A.2

A.3

A.4

Introduction...................................................................................... 73

Filter Specification............................................................................ 73

Recommendation for Mobile Systems............................................... 74

Comments....................................................................................... 75

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Figures

Figure 1. Signal Groups of a Mobile Pentium III Processor/440BX or 440ZX-M

AGPset - Based System...............................................................................2

Figure 2. Signal Groups of a Mobile Pentium III Processor/440MX Chipset - Based

System .......................................................................................................3

Figure 3. Clock Control States .....................................................................................8

Figure 4. Vcc Ramp Rate Requirement ...................................................................... 13

Figure 5. PLL RLC Filter............................................................................................ 15

Figure 6. PICCLK/TCK Clock Timing Waveform.......................................................... 27

Figure 7. BCLK Timing Waveform.............................................................................. 27

Figure 8. Valid Delay Timings .................................................................................... 28

Figure 9. Setup and Hold Timings .............................................................................. 28

Figure 10. Cold/Warm Reset and Configuration Timings.............................................. 29

Figure 11. Power-on Reset Timings ........................................................................... 29

Figure 12. Test Timings (Boundary Scan)................................................................... 30

Figure 13. Test Reset Timings ................................................................................... 30

Figure 14. Quick Start/Deep Sleep Timing.................................................................. 31

Figure 15. Stop Grant/Sleep/Deep Sleep Timing......................................................... 32

Figure 16. Intel SpeedStep Technology/Deep Sleep Timing......................................... 33

Figure 17. BCLK/PICCLK Generic Clock Waveform .................................................... 35

Figure 18. Low to High, GTL+ Receiver Ringback Tolerance....................................... 36

Figure 19. High to Low, GTL+ Receiver Ringback Tolerance....................................... 37

Figure 20. Maximum Acceptable Overshoot/Undershoot Waveform ............................. 38

Figure 21. Surface-mount BGA2 Package - Top and Side View................................... 41

Figure 22. Surface-mount BGA2 Package - Bottom View............................................. 42

Figure 23. Socketable Micro-PGA2 Package - Top and Side View............................... 45

Figure 24. Socketable Micro-PGA2 Package - Bottom View......................................... 46

Figure 25. Pin/Ball Map - Top View............................................................................ 47

Figure 26. PWRGOOD Relationship at Power On....................................................... 66

Figure 27. PLL Filter Specifications ............................................................................ 74

Intel Corporation

iii

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Tables

Table 1. New Mobile Pentium III Processor Signals.......................................................6

Table 2. Removed Mobile Pentium II Processor Signals................................................6

Table 3. Clock State Characteristics........................................................................... 10

Table 4. Mobile Pentium III Processor CPUID............................................................. 11

Table 5. Mobile Pentium III Processor CPUID Cache and TLB Descriptors................... 11

Table 6. System Signal Groups.................................................................................. 12

Table 7. Recommended Resistors for Open-drain Signals........................................... 13

Table 8. Mobile Pentium III Processor Absolute Maximum Ratings............................... 17

Table 9. Power Specifications for Mobile Pentium III Processor with Intel SpeedStep

Technology................................................................................................ 18

Table 10. Power Specifications for Fixed Frequency Mobile Pentium III Processor........ 19

Table 11. GTL+ Signal Group DC Specifications......................................................... 20

Table 12. GTL+ Bus DC Specifications....................................................................... 20

Table 13. Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications .. 21

Table 14. System Bus Clock AC Specifications........................................................... 22

Table 15. Valid Mobile Pentium III Processor Frequencies ........................................... 22

Table 16. GTL+ Signal Groups AC Specifications ....................................................... 23

Table 17. CMOS and Open-drain Signal Groups AC Specifications.............................. 23

Table 18. Reset Configuration AC Specifications ........................................................ 24

Table 19. APIC Bus Signal AC Specifications ............................................................. 24

Table 20. TAP Signal AC Specifications ..................................................................... 25

Table 21. Quick Start/Deep Sleep AC Specifications ................................................... 26

Table 22. Stop Grant/Sleep/Deep Sleep AC Specifications.......................................... 26

Table 23. Intel SpeedStep Technology AC Specifications............................................ 26

Table 24. BCLK Signal Quality Specifications ............................................................. 34

Table 25. PICCLK Signal Quality Specifications.......................................................... 34

Table 26. GTL+ Signal Group Ringback Specification.................................................. 36

Table 27. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core. 37

Table 28. Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor

Core.......................................................................................................... 39

Table 29. Surface-mount BGA2 Package Specifications.............................................. 40

Table 30. Socketable Micro-PGA2 Package Specification............................................ 44

Table 31. Signal Listing in Order by Pin/Ball Number................................................... 48

Table 32. Signal Listing in Order by Signal Name........................................................ 52

Table 33. Voltage and No-Connect Pin/Ball Locations ................................................. 54

Table 34. Power Specifications for Mobile Pentium III Processor with Intel SpeedStep

Technology................................................................................................ 55

Table 35. Power Specifications for Fixed Frequency Mobile Pentium III Processor........ 56

Table 36. Thermal Diode Interface............................................................................. 57

Table 37. Thermal Diode Specifications...................................................................... 57

Table 38. BSEL[1:0] Encoding................................................................................... 62

Table 39. Voltage Identification Encoding................................................................... 70

Table 40. Input Signals.............................................................................................. 71

Table 41. Output Signals........................................................................................... 72

Table 42. Input/Output Signals (Single Driver)............................................................. 72

Table 43. Input/Output Signals (Multiple Driver) .......................................................... 72

Table 44. PLL Filter Inductor Recommendations......................................................... 74

Table 45. PLL Filter Capacitor Recommendations....................................................... 75

Table 46. PLL Filter Resistor Recommendations......................................................... 75

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Revision History

Date

Revision Number

Updates

1.0

Initial release

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

1.0

Introduction

Using Intel’s advanced 0.18 micron process technology, the Intel^®mobile Pentium III processor

is offered at speeds of 400 MHz, 450 MHz, and 500 MHz while still offering lower power for long

battery life. Other performance advancements include the addition of new Internet Streaming

SIMD instructions, an advanced transfer cache architecture, and a processor system bus speed of

100 MHz. These features are offered in BGA2 and micro-PGA2 packages that are up to 20%

smaller than those offered for the mobile Intel Pentium® II processor. All of these technologies

make it possible to offer this outstanding performance in mobile PCs offered in a variety of shapes

and sizes.

Intel mobile Pentium III processor featuring Intel^®SpeedStep^™technology is the next dramatic

step towards achieving near desktop performance. This exciting new processor has two

performance modes and allows real-time dynamic switching of the voltage and frequency between

the modes. This occurs by switching the bus ratios, core operating voltage, and core processor

speeds without resetting the system.

There are two performance modes offered, Maximum Performance and Battery Optimized

Performance. Maximum Performance mode provides near desktop performance and runs at 600

or 650 MHz. Battery Optimized Performance mode provides the best balance between

performance and battery life and operates at a lower frequency of 500MHz.

The integrated L2 cache is designed to help improve performance, and it complements the system

bus by providing critical data faster and reducing total system power consumption. The mobile

PentiumIII processor’s 64-bit wide Gunning Transceiver Logic (GTL+) system bus provides a

glue-less, point-to-point interface for an I/O bridge/memory controller, and is compatible with the

440BX AGPset, 440ZX-M AGPset, and the 440MX Chipset. Figure 1 shows the various parts of a

mobile PentiumIII processor/440BX or 440ZX-M AGPset -based system and how the mobile

Pentium III processor connects to them. Figure 2 shows an alternative mobile Pentium III

processor/440MX Chipset - based system.

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Figure 1. Signal Groups of a Mobile Pentium III Processor/440BX or 440ZX-M AGPset - Based

System

Thermal

Sensor

Mobile

APIC

Pentium III

TAP

Bus

Processor

System

Bus

443BX or

443ZX-M

DRAM

North Bridge

PCI

PIIX4E

South Bridge

System

Controller

IOAPIC

(optional)

V0000-03

ISA/EIO

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Figure 2. Signal Groups of a Mobile Pentium III Processor/440MX Chipset - Based System

Thermal

Sensor

Mobile

TAP

Pentium^®III

Processor

System

Bus

DRAM

440MX

PCIset

System

Controller

V0000-04

X-bus

PCI

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

1.1

Overview

Performance improved over existing mobile processors

— Supports the Intel Architecture with Dynamic Execution

— Supports the Intel Architecture MMX™ technology

— Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance

— Supports Intel SpeedStep Technology

— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard

On-die primary (L1) instruction and data caches

— 4-way set associative, 32-byte line size, 1 line per sector

— 16-Kbyte instruction cache and 16-Kbyte write-back data cache

— Cacheable range controlled by processor programmable registers

On-die second level (L2) cache

— 8-way set associative, 32-byte line size, 1 line per sector

— Operates at full core speed

— 256-Kbyte, ECC protected cache data array

GTL+ system bus interface

— 64-bit data bus, 100-MHz operation

— Uniprocessor, two loads only (processor and I/O bridge/memory controller)

— Integrated termination

Pentium II processor clock control

— Quick Start for low power, low exit latency clock “throttling”

— Deep Sleep mode for lower power dissipation

Thermal diode for measuring processor temperature

1.2

Terminology

In this document a “#” symbol following a signal name indicates that the signal is active low. This

means that when the signal is asserted (based on the name of the signal) it is in an electrical low

state. Otherwise, signals are driven in an electrical high state when they are asserted. In state

machine diagrams, a signal name in a condition indicates the condition of that signal being

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

asserted. If the signal name is preceded by a “!” symbol, then it indicates the condition of that

signal not being asserted. For example, the condition “!STPCLK# and HS” is equivalent to “the

active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.” The

symbols “L” and “H” refer respectively to electrical low and electrical high signal levels. The

symbols “0” and “1” refer respectively to logical low and logical high signal levels. For example,

BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = “LHLH” also

refers to a hexadecimal “A.” The symbol “X” refers to a “Don’t Care” condition, where a “0” or a

“1” results in the same behavior.

1.3

References

Pentium^®II Processor at 233 MHz, 266 MHz, 300 MHz, and 333 MHz (Order Number 243335)

Pentium^®II Processor 350 MHz and 400 MHz (Order Number 243657)

Pentium^®II Processor Developer’s Manual (Order Number 243502)

CK97 Clock Driver Specification (Contact your Intel Field Sales Representative)

Intel^®Architecture Software Developer’s Manual (Order Number 243193)

Volume I: Basic Architecture (Order Number 243190)

Volume II: Instruction Set Reference (Order Number 243191)

Volume III: System Programming Guide (Order Number 243192)

Mobile Pentium® III Processor I/O Buffer Models, IBIS Format (Available in electronic form;

Contact your Intel Field Sales Representative)

Mobile Pentium® III Processor GTL+ System Bus Layout Guideline (Contact your Intel Field

Sales Representative)

Intel® Mobile Pentium® III Processor Thermal Specification Guideline (Contact your Intel Field

Sales Representative)

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

2.0

Mobile Pentium III Processor Features

2.1

New Features in the Mobile Pentium III Processor

2.1.1

On-die GTL+ Termination

The termination resistors for the GTL+ system bus are integrated onto the processor die. The

RESET# signal does not have on-die termination and requires an external 56.2W ±1% terminating

resistor.

2.1.2

2.1.3

2.1.4

Streaming SIMD Extensions

The mobile Pentium III processor is the first mobile processor to implement Streaming SIMD

(single instruction, multiple data) extensions. Streaming SIMD extensions can enhance floating

point, video, sound, and 3-D application performance.

Intel SpeedStep Technology

Intel SpeedStep technology is a new mobile feature developed by Intel. The mobile Pentium III

processors that are enabled with Intel SpeedStep technology have the ability to switch between

two bus ratios and core speeds without having to reset the processor.

Signal Differences Between the Mobile Pentium II Processor and the

Mobile Pentium III Processor

With the exception of BCLK, PICCLK, and PWRGOOD, the CMOS inputs and Open-drain

outputs have changed from 2.5V tolerant, as on the mobile Pentium II processor to 1.5V tolerant.

Table 1. New Mobile Pentium III Processor Signals

Signals

Function

CLKREF

CMOSREF

EDGECTRLP

GHI#

System bus clock trip point control

1.5V CMOS input buffer trip point control

GTL+ output buffer control

Intel SpeedStep technology operating mode selection

Processor system bus speed selection

Reserved, may be defined in the future

On-die GTL+ termination control

BSEL[1:0]

RSVD

RTTIMPEDP

VCCT

On-die GTL+ termination current supply

Voltage Identification

VID[4:0]

Table 2. Removed Mobile Pentium II Processor Signals

Signals

Purpose

EDGECTRLN

BSEL

GTL+ output buffer control

100/66 MHz processor system bus speed selection

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

2.2

Power Management

2.2.1

Clock Control Architecture

The mobile Pentium III processor clock control architecture (Figure 3) has been optimized for

leading edge deep green desktop and mobile computer designs. The clock control architecture

consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant

Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock state that

can be controlled through the software execution of the HLT instruction. The Quick Start state

provides a very low power and low exit latency clock state that can be used for hardware

controlled “idle” computer states. The Deep Sleep state provides an extremely low-power state

that can be used for “Power-On-Suspend” computer states, which is an alternative to shutting off

the processor’s power. Compared to the Pentium processor exit latency of 1 msec, the exit latency

of the Deep Sleep state has been reduced to 30 msec in the mobile PentiumIII processor. The Stop

Grant and Sleep states shown in Figure 3 are intended for use in “Deep Green” desktop and server

systems — not in mobile systems. Performing state transitions not shown in Figure 3 is neither

recommended nor supported.

The Stop Grant and Quick Start clock states are mutually exclusive, i.e., a strapping option on

signal A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start

state is enabled by strapping the A15# signal to ground at Reset; otherwise, asserting the

STPCLK# signal puts the processor into the Stop Grant state. The Stop Grant state has a higher

power level than the Quick Start state and is designed for Symmetric Multi-Processing (SMP)

platforms. The Quick Start state has a much lower power level, but it can only be used in

uniprocessor platforms. Table 3 provides clock state characteristics, which are described in detail

in the following sections.

2.2.2

2.2.3

Normal State

The Normal state of the processor is the normal operating mode where the processor’s core clock

is running and the processor is actively executing instructions.

Auto Halt State

This is a low-power mode entered by the processor through the execution of the HLT instruction.

The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is

made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#,

INIT#, RESET#, FLUSH#, or SMI#).

Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition

to the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued.

Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a

new Halt bus cycle.

The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel®

Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more

information. No Halt bus cycle is issued when returning to the Auto Halt state from the System

Management Mode (SMM).

The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have

been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.

Figure 3. Clock Control States

STPCLK# and

QSE and SGA

Normal

HS=false

Quick

Start

(!STPCLK# and !HS)

or RESET#

HLT and

halt bus cycle

STPCLK# and

QSE and SGA

BCLK

stopped

halt

break

!STPCLK#

and HS

BCLK on

and QSE

STPCLK# and

!QSE and SGA

Auto

Halt

HS=true

Snoop

serviced occurs

Snoop

Deep

Sleep

(!STPCLK#

and !HS) or

stop break

!STPCLK#

and HS

Snoop

occurs

Snoop

serviced

STPCLK# and

!QSE and SGA

Snoop

occurs

Stop

Grant

HALT/Grant

Snoop

serviced

SLP#

BCLK on

and !QSE

BCLK

stopped

!SLP# or

RESET#

Sleep

V0001-00

NOTES: halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#

HLT – HLT instruction executed

HS – Processor Halt State

QSE – Quick Start State Enabled

SGA – Stop Grant Acknowledge bus cycle issued

stop break – BINIT#, RESET#

2.2.4

Stop Grant State

The processor enters this mode with the assertion of the STPCLK# signal when it is configured for

Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop

requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the

Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the

Normal state can be made by the deassertion of the STPCLK# signal or the occurrence of a stop

break event (a BINIT# or RESET# assertion).

The processor will return to the Stop Grant state after the completion of a BINIT# bus

initialization unless STPCLK# has been de-asserted. RESET# assertion will cause the processor to

immediately initialize itself, but the processor will stay in the Stop Grant state after initialization

until STPCLK# is deasserted. A transition to the Sleep state can be made by the assertion of the

SLP# signal.

Intel Corporation

Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

While in the Stop Grant state, assertions of FLUSH#, SMI#, INIT#, INTR, and NMI (or

LINT[1:0]) will be latched by the processor. These latched events will not be serviced until the

processor returns to the Normal state. Only one of each event will be recognized upon return to the

Normal state.

2.2.5

Quick Start State

This is a mode entered by the processor with the assertion of the STPCLK# signal when it is

configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the

processor is only capable of acting on snoop transactions generated by the system bus priority

device. Because of its snooping behavior, Quick Start can only be used in a uniprocessor (UP)

configuration.

A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A

transition back to the Normal state (from the Quick Start state) is made only if the STPCLK#

signal is deasserted.

While in this state the processor is limited in its ability to respond to input. It is incapable of

latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to

FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond

properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal

changes, then the behavior of the processor will be unpredictable. No serial interrupt messages

may begin or be in progress while the processor is in the Quick Start state.

RESET# assertion will cause the processor to immediately initialize itself, but the processor will

stay in the Quick Start state after initialization until STPCLK# is deasserted.

2.2.6

2.2.7

HALT/Grant Snoop State

The processor will respond to snoop transactions on the system bus while in the Auto Halt, Stop

Grant, or Quick Start state. When a snoop transaction is presented on the system bus the processor

will enter the HALT/Grant Snoop state. The processor will remain in this state until the snoop has

been serviced and the system bus is quiet. After the snoop has been serviced, the processor will

return to its previous state. If the HALT/Grant Snoop state is entered from the Quick Start state,

then the input signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop

state, except for those signal transitions that are required to perform the snoop.

Sleep State

The Sleep state is a very low-power state in which the processor maintains its context and the

phase-locked loop (PLL) maintains phase lock. The Sleep state can only be entered from the Stop

Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the

processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt

states.

The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven

active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be

driven inactive to ensure that the processor correctly initializes itself.

Input signals (other than RESET#) may not change while the processor is in the Sleep state or

transitioning into or out of the Sleep state. Input signal changes at these times will cause

unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the

Sleep state.

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While in the Sleep state, the processor can enter its lowest power state, the Deep Sleep state.

Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be

removed in the Sleep state.

2.2.8

Deep Sleep State

The Deep Sleep state is the lowest power mode the processor can enter while maintaining its

context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is

in the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the

Low state.

The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the

BCLK input is restarted. Due to the PLL lock latency, there is a delay of up to 30 msec after the

clocks have started before this state transition happens. PICCLK may be removed in the Deep

Sleep state. PICCLK should be designed to turn on when BCLK turns on when transitioning out of

the Deep Sleep state.

The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except

that RESET# assertion will result in unpredictable behavior.

Table 3. Clock State Characteristics

Clock State Exit Latency

Snooping?

Yes

System Uses

Normal

N/A

Normal program execution

S/W controlled entry idle mode

H/W controlled entry/exit mobile throttling

Auto Halt

Stop Grant

Quick Start

Approximately 10 bus clocks

10 bus clocks

Yes

Through snoop, to HALT/Grant

Snoop state: immediate

Yes

H/W controlled entry/exit mobile throttling

Through STPCLK#, to Normal

state: 8 bus clocks

Yes

Supports snooping in the low power states

HALT/Grant A few bus clocks after the end

Snoop

of snoop activity

Sleep

To Stop Grant state 10 bus

clocks

H/W controlled entry/exit desktop idle mode

support

Deep Sleep

H/W controlled entry/exit mobile powered-on

suspend support

30 msec

NOTE:

See Table 35 for power dissipation in the low-power states.

2.2.9

2.2.10

Operating System Implications of Low-power States

There are a number of architectural features of the mobile Pentium III processor that do not

function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp

counter and the performance monitor counters are not guaranteed to count in the Quick Start or

Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled

before entering the Deep Sleep state or the resulting behavior will be unpredictable.

Intel SpeedStep Technology

Some mobile Pentium III processors will be offered with Intel SpeedStep technology. The Intel

SpeedStep technology lets the processor switch between two core frequencies without having to

reset the processor or change the system bus frequency. The processor has two bus ratios

programmed into it instead of one and the GHI# signal controls which one is used. After reset, the

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processor will start in the lower of its two core frequencies, the “Battery Optimized” mode. An

operating mode transition to the high core frequency can be made by putting the processor into the

Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the Normal state.

This puts the processor into the “Maximum performance” mode. Transitioning back to the low-

core frequency can be made by reversing these steps. Contact your Intel Field Sales

Representative for more information on Intel SpeedStep technology.

2.3

GTL+ Signals

The mobile Pentium III processor system bus signals use a variation of the low-voltage swing GTL

signaling technology. The mobile Pentium III processor system bus specification is similar to the

Pentium II processor system bus specification, which is a version of GTL with enhanced noise

margins and less ringing.

The GTL+ system bus depends on incident wave switching and uses flight time for timing

calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of

the system bus including trace lengths is highly recommended. Contact your field sales

representative to receive the IBIS models for the mobile Pentium III processor.

The GTL+ system bus of the Pentium II processor was designed to support high-speed data

transfers with multiple loads on a long bus that behaves like a transmission line. However, in

mobile systems the system bus only has two loads (the processor and the chipset) and the bus

traces are short. It is possible to change the layout and termination of the system bus to take

advantage of the mobile environment using the same GTL+ I/O buffers. In mobile systems the

GTL+ system bus is terminated at one end only. This termination is provided on the processor

core (except for the RESET# signal). Refer to the Mobile Coppermine Processor GTL+ System

Bus Layout Guideline for details on laying out the GTL+ system bus.

2.4

Mobile Pentium III Processor CPUID

The CPUID instruction does not distinguish between the Pentium III processor and the mobile

Pentium III processor. After a power-on RESET or when the CPUID version information is

loaded, the EAX register contains the values shown in Table 4. After the L2 cache is initialized,

the CPUID cache/TLB descriptors will be the values shown in Table 5.

Table 4. Mobile Pentium III Processor CPUID

EAX[31:0]

Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] Brand ID

EBX[7:0]

Table 5. Mobile Pentium III Processor CPUID Cache and TLB Descriptors

Cache and TLB Descriptors

01H, 02H, 03H, 04H, 08H, 0CH, 82H

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3.0

Electrical Specifications

3.1

Processor System Signals

Table 6 lists the processor system signals by type. All GTL+ signals are synchronous with the

BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS

input signals can be applied asynchronously.

Table 6. System Signal Groups

Group Name

GTL+ Input

GTL+ Output

GTL+ I/O

Signals

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#

PRDY#

A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,

BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,

LOCK#, REQ[4:0]#, RP#

1.5V CMOS Input ²

2.5V CMOS Input ^{1, 3}

A20M#, BSEL[1:0], FLUSH#, GHI#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,

PREQ#, SLP#, SMI#, STPCLK#

PWRGOOD

1.5V Open Drain Output ²FERR#, IERR#

Clock ³

BCLK

APIC Clock ³

APIC I/O ²

PICCLK

PICD[1:0]

Thermal Diode

TAP Input ²

TAP Output ²

Power/Other ⁴

THERMDA, THERMDC

TCK, TDI, TMS, TRST#

TDO

CLKREF, CMOSREF, EDGECTRLP, NC, PLL1, PLL2, RSVD, RTTIMPEDP,

TESTHI, TESTLO[2:1], V_CC, V_CCT, VID[4:0], V_REF, V_SS

NOTES:

See Section 8.1 for information on the PWRGOOD signal.

These signals are tolerant to 1.5V only. See Table 7 for the recommended pull-up resistor.

These signals are tolerant to 2.5V only. See Table 7 for the recommended pull-up resistor.

V_CCis the power supply for the core logic.

PLL1 and PLL2 are the power supply for the PLL analog section.

V_CCTis the power supply for the system bus buffers.

V_REFis the voltage reference for the GTL+ input buffers.

V_SSis system ground.

The CMOS, APIC, and TAP inputs can be driven from ground to 1.5V. BCLK, PICCLK, and

PWRGOOD can be driven from ground to 2.5V. The APIC data and TAP outputs are Open-drain

and should be pulled up to 1.5V using resistors with the values shown in Table 7. If Open-drain

drivers are used for input signals, then they should also be pulled up to the appropriate voltage

using resistors with the values shown in Table 7.

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Table 7. Recommended Resistors for Open-drain Signals

Open Drain Signal ^{1, 2}

Recommended

Resistor Value (W )

No pull-up

GHI# ³

150 pull-up

270 pull-up

680 pull-up

1K pull-up

PICD[1:0], TDI, TDO

SMI#

STPCLK#

INIT#, TCK, TMS

TRST#

1K pull-down

1.5K pull-up

A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR,

LINT1/NMI, PREQ#, PWRGOOD, SLP#

NOTES:

The recommendations above are only for signals that are being used. These recommendations are maximum values only;

stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should not violate the chipset specification.

Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used.

Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if there is too

much undershoot.

GHI# has an on-die pull-up to V_CCT

3.1.1

Power Sequencing Requirements

The mobile Pentium III processor has no power sequencing requirements. Intel recommends that

all of the processor power planes rise to their specified values within one second of each other.

The V_CCpower plane must not rise too fast. At least 200 msec (T_R) must pass from the time that

V_CCis at 10% of its nominal value until the time that V_CCis at 90% of its nominal value (see

Figure 4).

Figure 4. Vcc Ramp Rate Requirement

Vcc

90% Vcc (nominal)

Volts

10% Vcc (nominal)

T_R

Time

3.1.2

Test Access Port (TAP) Connection

The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the

voltage levels supported by the TAP interface, Intel recommends that the mobile Pentium III

processor and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain

after any devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer

should be used to reduce the TDO output voltage of the last 3.3/5.0V device down to the 1.5V

range that the mobile Pentium III processor can tolerate. Multiple copies of TMS and TRST# must

be provided, one for each voltage level.

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A Debug Port and connector may be placed at the start and end of the JTAG chain containing the

processor, with TDI to the first component coming from the Debug Port and TDO from the last

component going to the Debug Port. There are no requirements for placing the mobile Pentium III

processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP

signals.

3.1.3

3.1.4

Catastrophic Thermal Protection

The mobile Pentium III processor does not support catastrophic thermal protection or the

THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the

system against excessive temperatures.

Unused Signals

All signals named NC and RSVD must be unconnected. The TESTHI signal should be pulled up

to V_CCT. The TESTLO1 and TESTLO2 signal should be pulled down to V . Unused GTL+

inputs, outputs and bi-directional signals should be unconnected. Unused CMOS active low inputs

should be connected to V_CCTand unused active high inputs should be connected to V_SS. Unused

Open-drain outputs should be unconnected. If the processor is configured to enter the Quick Start

state rather than the Stop Grant state, then the SLP# signal should be connected to V_CCT. When

tying any signal to power or ground, a resistor will allow for system testability. For unused

signals, Intel suggests that 1.5-kW resistors are used for pull-ups and 1-kW resistors are used for

pull-downs.

If the local APIC is hardware disabled, then PICCLK and PICD[1:0] should be tied to V_SSwith a

1-kW resistor, one resistor can be used for the three signals. Otherwise PICCLK must be driven

with a clock that meets specification (see Table 19) and the PICD[1:0] signals must be pulled up

to V_CCTwith 150-W resistors, even if the local APIC is not used.

BSEL1 must be connected to V_SSand BSEL0 must be pulled up to V_CCT. VID[4:0] should be

connected to V_SSif they are not used.

If the TAP signals are not used then the inputs should be pulled to ground with 1-kW resistors and

TDO should be left unconnected.

3.1.5

Signal State in Low-power States

3.1.5.1

System Bus Signals

All of the system bus signals have GTL+ input, output, or input/output drivers. Except when

servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors.

Snoops are not permitted in the Sleep and Deep Sleep states.

3.1.5.2

CMOS and Open-drain Signals

The CMOS input signals are allowed to be in either the logic high or low state when the processor

is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle.

These input buffers have no internal pull-up or pull-down resistors and system logic can use

CMOS or Open-drain drivers to drive them.

The Open-drain output signals have open drain drivers and external pull-up resistors are required.

One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and

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pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated

or driven to V_SSwhen the processor is in a low-power state depending on the condition of the

floating point unit. Since this signal is a DC current path when it is driven to V , Intel

recommends that the software clears or masks any floating-point error condition before putting the

processor into the Deep Sleep state.

3.1.5.3

Other Signals

The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep

state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is

hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off

PICCLK by holding it at V_SS. The system bus clock should be held at V_SSwhen it is stopped in the

Deep Sleep state.

In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to

APIC bus messages. These signals are required to be tri-stated and pulled-up when the processor

is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.

3.2

Power Supply Requirements

3.2.1

Decoupling Recommendations

The amount of bulk decoupling required on the V_CCand V_CCTplanes to meet the voltage tolerance

requirements for the mobile Pentium III processor are a strong function of the power supply

design. Contact your Intel Field Sales Representative for tools to help determine how much bulk

decoupling is required. The processor core power plan (V_CC) should have eight 0.1-mF high

frequency decoupling capacitors placed underneath the die and twenty 0.1-mF mid frequency

decoupling capacitors placed around the die as close to the die as flex solution allows. The system

bus buffer power plane (V_CCT) should have twenty 0.1-mF high frequency decoupling capacitors

around the die.

3.2.2

Voltage Planes

All V_CCand V pins/balls must be connected to the appropriate voltage plane. All V

and V_REF

CCT

pins/balls must be connected to the appropriate traces on the system electronics. In addition to the

main V_CC, V_CCT, and V_SSpower supply signals, PLL1 and PLL2 provide analog decoupling to the

PLL section. PLL1 and PLL2 should be connected according to Figure 5. Do not connect PLL2

directly to V . Appendix A contains the RLC filter specification.

Figure 5. PLL RLC Filter

L 1

R 1

P L L 1

P L L 2

CCT

C 1

V0027-01

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3.3

System Bus Clock and Processor Clocking

The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All

system bus timing parameters are specified with respect to the rising edge of the BCLK input. The

mobile Pentium III processor core frequency is a multiple of the BCLK frequency. The processor

core frequency is configured during manufacturing. The configured bus ratio is visible to software

in the Power-on configuration register, see Section 7.2 for details.

Multiplying the bus clock frequency is necessary to increase performance while allowing for

easier distribution of signals within the system. Clock multiplication within the processor is

provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK

input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to

acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in

Section 3.7, AC timing parameters T18 and T47.

3.4

Intel SpeedStep Technology

The mobile Pentium III processor featuring Intel SpeedStep technology is specified to operate in

either of two modes, the “Maximum Performance Mode” or the “Battery Optimized Mode”. Each

frequency and voltage pair identifies the operating mode. The voltage provided to the processor

must meet the core voltage specification for the current operating mode. If an operating mode

transition is made, then the system logic must direct the voltage regulator to regulate to the voltage

specification of the other mode. After reset, the processor will start in the lower of its two core

frequencies, so the core voltage must meet the lower voltage specification. Any RESET# assertion

will force the processor to the lower frequency, and the core voltage must behave appropriately.

INIT# assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of

the processor. Some electrical and thermal specifications are for a specific voltage and frequency.

The mobile Pentium III processor featuring Intel SpeedStep technology will meet the electrical and

thermal specifications specific to the current operating mode and is not guaranteed to meet the

electrical and thermal specifications specific to the opposite operating mode. The timing

specifications in Table 23 must be met when performing an operating mode transition.

3.5

Maximum Ratings

Table 8 contains the mobile Pentium III processor stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor guaranteed. The processor should not

receive a clock while subjected to these conditions. Functional operating conditions are provided

in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.

Furthermore, although the processor contains protective circuitry to resist damage from static

electric discharge, one should always take precautions to avoid high static voltages or electric

fields.

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Table 8. Mobile Pentium III Processor Absolute Maximum Ratings

Symbol

T_Storage

V_CC(Abs)

V_CCT

Parameter

Min

–40

Max

Unit

Notes

Storage Temperature

°C Note 1

Supply Voltage with respect to V_SS

–0.5 2.1

–0.3 2.1

System Bus Buffer Voltage with respect to V _SS

V_{IN GTL}

V_IN15

System Bus Buffer DC Input Voltage with respect to V _SS–0.3 2.1

Notes 2, 3

System Bus Buffer DC Input Voltage with respect to V _CCT

1.5V Buffer DC Input Voltage with respect to V _SS

2.5V Buffer DC Input Voltage with respect to V _SS

VID ball/pin DC Input Voltage with respect to V_SS

VID Current

—

V_CCT+ 0.7V V

Notes 2, 4

Note 5

–0.3 2.1

–0.3 3.3

V_IN25

Note 6

V_INVID

—

5.5

I_VID

mA Note 7

NOTES:

The shipping container is only rated for 65°C.

Parameter applies to the GTL+ signal groups only. Compliance with both V

specifications is required.

IN GTL

The voltage on the GTL+ signals must never be below –0.3 or above 2.1V with respect to ground.

The voltage on the GTL+ signals must never be above V + 0.7V even if it is less than V + 2.1V, or a short to ground

CCT SS

may occur.

Parameter applies to CMOS, Open-drain, APIC, and TAP bus signal groups only.

Parameter applies to BCLK, CLKREF, PICCLK and PWRGOOD signals.

Parameter applies to each VID pin/ball individually.

3.6

DC Specifications

Table 9 through Table 13 lists the DC specifications for the mobile Pentium III processor.

Specifications are valid only while meeting specifications for the junction temperature, clock

frequency, and input voltages. Care should be taken to read all notes associated with each

parameter.

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Table 9. Power Specificationsfor Mobile Pentium III Processor with Intel SpeedStep Technology¹

T_J= 0°C to 100°C; V_CC= 1.35V ±100 mV or 1.60V ±115 mV; V _CCT= 1.50V ±115 mV

Symbol Parameter

Min

Typ Max

Unit Notes

V_CC

Transient V_CCfor core logic

1.25

1.35 1.45

±100 mV

±115 mV, Note 7

1.485 1.60 1.715

V_CC,DC

Static V_CCfor core logic

1.25 1.35 1.45

±100 mV

-115/+40 mV,

Note 2

1.485 1.60 1.640

V_CCfor System Bus Buffers, Transient tolerance 1.385 1.50 1.615

V_CCT

±115 mV, Note 7

±3%, Note 2

Notes 4

V_CCT,DCV_CCfor System Bus Buffers, Static tolerance

1.455 1.50 1.545

I_CC

Current for V _CCat core frequency

at 500 MHz & 1.35V

9.5

12.6

13.6

at 600 MHz & 1.60V

at 650 MHz & 1.60V

I_CCT

Current for V _CCT

2.5

Notes 3, 4

Notes 4

I_CC,SG

Processor Stop Grant and Auto Halt current

at 1.35V

at 1.60V

1.7

2.2

I_CC,QS

Processor Quick Start and Sleep current

Note 4

at 1.35V

at 1.60V

1.5

1.9

I_CC,DSLPProcessor Deep Sleep Leakage current

Notes 4

at 1.35V

at 1.60V

1.2

1.6

dI_CC/dt

V_CCpower supply current slew rate

1400

TBD

Notes 5, 6

A/ms

dI_CCT/dt V_CCTpower supply current slew rate

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor frequencies. Processors with Intel SpeedStep

technology will comply with the I_{CCx max}specification for the current mode of operation.

Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, output load ranges

specified in Table 9 above, temperature, and warm up.

I_CCTis the current supply for the system bus buffers, including the on-die termination.

I_CCx,_maxspecifications are specified at V_CC,_{DC max}, V_CCT,_max, and 100°C and under maximum signal loading conditions.

Based on simulations and averaged over the duration of any change in current. Use to compute the maximum inductance

and reaction time of the voltage regulator. This parameter is not tested.

Maximum values specified by design/characterization at nominal V_CCand V_CCT

V_CCxmust be within this range under all operating conditions, including maximum current transients. V_CCxmust return to

within the static voltage specification, V_{CCx DC}, within 100 ms after a transient event. The average of V_CCxover time must

not exceed 1.65V, as an arbitrarily large time span may be used for this average.

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Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet

Table 10. Power Specifications for Fixed Frequency Mobile Pentium III Processor

T_J= 0°C to 100°C; V_CC= 1.35V ±100 mV or 1.60V ±115 mV; V _CCT= 1.50V ±115 mV

Symbol Parameter

Min

Typ Max

Unit Notes

V_CC

Transient V_CCfor core logic

1.25

1.35 1.45

±100 mV

±115 mV, Note 7

1.485 1.60 1.715

V_CC,DC

Static V_CCfor core logic

1.25 1.35 1.45

±100 mV

-115/+40 mV,

Note 2

1.485 1.60 1.640

V_CCfor System Bus Buffers, Transient tolerance 1.385 1.50 1.615

V_CCT

±115 mV, Note 7

±3%, Note 2

Note 4

V_CCT,DCV_CCfor System Bus Buffers, Static tolerance

1.455 1.50 1.545

I_CC

Current for V _CCat core frequency

at 400 MHz & 1.35V

at 500 MHz & 1.35V

at 450 MHz & 1.60V

at 500 MHz & 1.60V

7.8

9.5

9.6

10.6

I_CCT

Current for V _CCT

2.5

Notes 3, 4

Notes 1,4

I_CC,SG

Processor Stop Grant and

Auto Halt current

1.29

I_CC,QS

Processor Quick Start and

Sleep current

994

700

Notes 1,4

I_CC,DSLPProcessor Deep Sleep

leakage current

dI_CC/dt

V_CCpower supply current slew rate

1400

TBD

Notes 5, 6

A/ms

dI_CCT/dt V_CCTpower supply current slew rate

NOTES:

For I_CC,SG, I_CC,QS, and I_CC,DSLPspecifications in the case of 500MHz & 1.35V fixed frequency processor, refer to these

values listed in Table 9 at 1.35V.

Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, output load ranges

specified in Table 10 above, temperature, and warm up.