KC80526GY850256 [INTEL]
Microprocessor, 32-Bit, 850MHz, CMOS, PBGA495, BGA2-495;
| 型号： | KC80526GY850256 |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, 32-Bit, 850MHz, CMOS, PBGA495, BGA2-495 |
| 文件： | 总68页 (文件大小：1464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Pentium® III Processor – Low
Power
700 MHz, 500 MHz and 400 MHz Processors in a BGA2 Package
Datasheet
Product Features
I Processor core/bus speeds:
—700/100 MHz
I Power Management Features
—Quick Start and Deep Sleep modes
provide low power dissipation
—500/100 MHz
I On-die thermal diode
—400/100 MHz
I Fully compatible with previous Intel
I Supports the Intel Architecture with
microprocessors
Dynamic Execution
—Binary compatible with all applications
—Support for Intel® MMX™ technology
—Support for Streaming SIMD Extensions
I BGA2 packaging technology
I On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
I On-die second level cache (256-Kbyte)
I Integrated GTL+ termination
I Integrated math coprocessor
—Supports thin form factor designs
I Intel Processor Serial Number
—Exposed die enables more efficient heat
dissipation
Order Number: 273500-003
April 2002
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® III Processor – Low Power may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled
platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................9
1.1
1.2
1.3
Overview.............................................................................................................................10
Terminology........................................................................................................................11
References .........................................................................................................................11
2.0 Pentium® III Processor – Low Power Features.........................................................................12
2.1
2.2
Features in the Pentium® III Processor – Low Power.........................................................12
2.1.1 On-die GTL+ Termination......................................................................................12
2.1.2 Streaming SIMD Extensions..................................................................................12
Power Management............................................................................................................12
2.2.1 Clock Control Architecture .....................................................................................12
2.2.2 Normal State..........................................................................................................12
2.2.3 Auto Halt State.......................................................................................................13
2.2.4 Stop Grant State ....................................................................................................14
2.2.5 Quick Start State....................................................................................................14
2.2.6 HALT/Grant Snoop State.......................................................................................14
2.2.7 Sleep State ............................................................................................................15
2.2.8 Deep Sleep State...................................................................................................15
2.2.9 Operating System Implications of Low-power States ............................................16
2.2.10 GTL+ Signals.........................................................................................................16
2.2.11 Pentium® III Processor – Low Power CPUID.........................................................17
3.0 Electrical Specifications .............................................................................................................17
3.1
Processor System Signals..................................................................................................17
3.1.1 Power Sequencing Requirements .........................................................................19
3.1.2 Test Access Port (TAP) Connection ......................................................................19
3.1.3 Catastrophic Thermal Protection ...........................................................................19
3.1.4 Unused Signals......................................................................................................19
3.1.5 Signal State in Low-power States..........................................................................20
3.1.5.1 System Bus Signals...............................................................................20
3.1.5.2 CMOS and Open-drain Signals .............................................................20
3.1.5.3 Other Signals .........................................................................................20
Power Supply Requirements ..............................................................................................21
3.2.1 Decoupling Recommendations..............................................................................21
3.2.2 Voltage Planes.......................................................................................................21
System Bus Clock and Processor Clocking........................................................................22
Maximum Ratings...............................................................................................................22
DC Specifications ...............................................................................................................23
AC Specifications................................................................................................................26
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........26
3.2
3.3
3.4
3.5
3.6
4.0 System Signal Simulations.........................................................................................................35
4.1
4.2
4.3
System Bus Clock (BCLK) and PICCLK AC Signal Quality Specifications ........................35
GTL+ AC Signal Quality Specifications ..............................................................................36
Non-GTL+ Signal Quality Specifications.............................................................................39
4.3.1 PWRGOOD Signal Quality Specifications .............................................................39
Datasheet
3
Contents
5.0 Mechanical Specifications..........................................................................................................40
5.1
5.2
Surface-mount BGA2 Package Dimensions.......................................................................40
Signal Listings.....................................................................................................................42
6.0 Thermal Specifications ...............................................................................................................50
6.1 Thermal Diode ....................................................................................................................51
7.0 Processor Initialization and Configuration ...............................................................................52
7.1
Description..........................................................................................................................52
7.1.1 Quick Start Enable.................................................................................................52
7.1.2 System Bus Frequency..........................................................................................52
7.1.3 APIC Enable ..........................................................................................................52
Clock Frequencies and Ratios............................................................................................52
7.2
8.0 Processor Interface.....................................................................................................................53
8.1
Alphabetical Signal Reference............................................................................................53
8.1.1 A[35:3]# (I/O - GTL+).............................................................................................53
8.1.2 A20M# (I - 1.5 V Tolerant) .....................................................................................53
8.1.3 ADS# (I/O - GTL+).................................................................................................53
8.1.4 AERR# (I/O - GTL+) ..............................................................................................53
8.1.5 AP[1:0]# (I/O - GTL+) ............................................................................................53
8.1.6 BCLK (I - 2.5 V Tolerant) .......................................................................................54
8.1.7 BERR# (I/O - GTL+) ..............................................................................................54
8.1.8 BINIT# (I/O - GTL+)...............................................................................................54
8.1.9 BNR# (I/O - GTL+).................................................................................................54
8.1.10 BP[3:2]# (I/O - GTL+) ............................................................................................55
8.1.11 BPM[1:0]# (I/O - GTL+) .........................................................................................55
8.1.12 BPRI# (I - GTL+)....................................................................................................55
8.1.13 BREQ0# (I/O - GTL+) ............................................................................................55
8.1.14 BSEL[1:0] (I – 3.3 V Tolerant)................................................................................55
8.1.15 CLKREF (Analog)..................................................................................................55
8.1.16 CMOSREF (Analog) ..............................................................................................56
8.1.17 D[63:0]# (I/O - GTL+).............................................................................................56
8.1.18 DBSY# (I/O - GTL+) ..............................................................................................56
8.1.19 DEFER# (I - GTL+)................................................................................................56
8.1.20 DEP[7:0]# (I/O - GTL+)..........................................................................................56
8.1.21 DRDY# (I/O - GTL+)..............................................................................................56
8.1.22 EDGCTRLP (Analog).............................................................................................56
8.1.23 FERR# (O - 1.5 V Tolerant Open-drain)................................................................57
8.1.24 FLUSH# (I - 1.5 V Tolerant)...................................................................................57
8.1.25 GHI# (I - 1.5 V Tolerant) ........................................................................................57
8.1.26 HIT# (I/O - GTL+), HITM# (I/O - GTL+) .................................................................57
8.1.27 IERR# (O - 1.5 V Tolerant Open-drain) .................................................................57
8.1.28 IGNNE# (I - 1.5 V Tolerant) ...................................................................................57
8.1.29 INIT# (I - 1.5 V Tolerant)........................................................................................58
8.1.30 INTR (I - 1.5 V Tolerant) ........................................................................................58
8.1.31 LINT[1:0] (I - 1.5 V Tolerant)..................................................................................58
8.1.32 LOCK# (I/O - GTL+) ..............................................................................................58
8.1.33 NMI (I - 1.5 V Tolerant)..........................................................................................58
8.1.34 PICCLK (I - 2.5 V Tolerant)....................................................................................59
4
Datasheet
Contents
8.1.35 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) ..........................................................59
8.1.36 PLL1, PLL2 (Analog) .............................................................................................59
8.1.37 PRDY# (O - GTL+) ................................................................................................59
8.1.38 PREQ# (I - 1.5 V Tolerant) ....................................................................................59
8.1.39 PWRGOOD (I - 2.5 V Tolerant) .............................................................................59
8.1.40 REQ[4:0]# (I/O - GTL+)..........................................................................................60
8.1.41 RESET# (I - GTL+) ................................................................................................60
8.1.42 RP# (I/O - GTL+) ...................................................................................................60
8.1.43 RS[2:0]# (I - GTL+) ................................................................................................61
8.1.44 RSP# (I - GTL+).....................................................................................................61
8.1.45 RSVD (TBD) ..........................................................................................................61
8.1.46 RTTIMPEDP (Analog) ...........................................................................................61
8.1.47 SLP# (I - 1.5 V Tolerant)........................................................................................61
8.1.48 SMI# (I - 1.5 V Tolerant) ........................................................................................61
8.1.49 STPCLK# (I - 1.5 V Tolerant).................................................................................61
8.1.50 TCK (I - 1.5 V Tolerant) .........................................................................................62
8.1.51 TDI (I - 1.5 V Tolerant)...........................................................................................62
8.1.52 TDO (O - 1.5 V Tolerant Open-drain) ....................................................................62
8.1.53 TESTHI (I - 1.5 V Tolerant)....................................................................................62
8.1.54 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................62
8.1.55 THERMDA, THERMDC (Analog)...........................................................................62
8.1.56 TMS (I - 1.5 V Tolerant) .........................................................................................62
8.1.57 TRDY# (I - GTL+) ..................................................................................................62
8.1.58 TRST# (I - 1.5 V Tolerant) .....................................................................................63
8.1.59 VID[4:0] (O – Open-drain)......................................................................................63
8.1.60 VREF (Analog).......................................................................................................63
Signal Summaries...............................................................................................................63
8.2
9.0 PLL RLC Filter Specification ......................................................................................................66
9.1
9.2
9.3
9.4
Introduction.........................................................................................................................66
Filter Specification ..............................................................................................................66
Recommendation for Low Power Systems.........................................................................67
Comments ..........................................................................................................................68
Datasheet
5
Contents
Figures
1
2
3
4
5
6
7
8
9
Signal Groups of a Pentium® III Processor/440BX AGPset - Based System...............................9
Signal Groups of a Pentium® III Processor/440MX Chipset - Based System ............................10
Clock Control States...................................................................................................................13
Vcc Ramp Rate Requirement.....................................................................................................19
PLL RLC Filter............................................................................................................................21
PICCLK/TCK Clock Timing Waveform .......................................................................................30
BCLK Timing Waveform.............................................................................................................31
Valid Delay Timings....................................................................................................................31
Setup and Hold Timings .............................................................................................................31
10 Cold/Warm Reset and Configuration Timings ............................................................................32
11 Power-on Reset Timings ............................................................................................................32
12 Test Timings (Boundary Scan)...................................................................................................33
13 Test Reset Timings.....................................................................................................................33
14 Quick Start/Deep Sleep Timing ..................................................................................................34
15 Stop Grant/Sleep/Deep Sleep Timing ........................................................................................34
16 BCLK/PICCLK Generic Clock Waveform ...................................................................................36
17 Low to High, GTL+ Receiver Ringback Tolerance .....................................................................37
18 High to Low, GTL+ Receiver Ringback Tolerance .....................................................................37
19 Maximum Acceptable Overshoot/Undershoot Waveform...........................................................38
20 Surface-mount BGA2 Package - Top and Side View.................................................................41
21 Surface-mount BGA2 Package - Bottom View...........................................................................42
22 Pin/Ball Map - Top View .............................................................................................................43
23 PWRGOOD Relationship at Power On ......................................................................................60
24 PLL Filter Specifications.............................................................................................................67
6
Datasheet
Contents
Tables
1
2
3
4
5
6
7
8
9
Clock State Characteristics.........................................................................................................16
Pentium® III Processor – Low Power CPUID .............................................................................17
Pentium® III Processor – Low Power CPUID Cache and TLB Descriptors ................................17
System Signal Groups................................................................................................................17
Recommended Resistors for Pentium III Processor – Low Power Signals ................................18
Pentium® III Processor – Low Power Absolute Maximum Ratings.............................................22
Power Specifications ..................................................................................................................23
GTL+ Signal Group DC Specifications .......................................................................................24
GTL+ Bus DC Specifications......................................................................................................24
10 Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications ............................25
11 System Bus Clock AC Specifications .........................................................................................26
12 Supported Processor Frequencies .............................................................................................26
13 GTL+ Signal Groups AC Specifications......................................................................................27
14 CMOS and Open-drain Signal Groups AC Specifications..........................................................27
15 Reset Configuration AC Specifications.......................................................................................28
16 APIC Bus Signal AC Specifications............................................................................................28
17 TAP Signal AC Specifications.....................................................................................................29
18 Quick Start/Deep Sleep AC Specifications.................................................................................30
19 Stop Grant/Sleep/Deep Sleep AC Specifications .......................................................................30
20 BCLK Signal Quality Specification..............................................................................................35
21 PICCLK Signal Quality Specifications ........................................................................................35
22 GTL+ Signal Group Ringback Specification ...............................................................................36
23 GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core ..........................38
24 Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core...................39
25 Surface-mount BGA2 Package Specifications ...........................................................................40
26 Signal Listing in Order by Pin/Ball Number.................................................................................44
27 Signal Listing in Order by Signal Name......................................................................................47
28 Voltage and No-Connect Pin/Ball Locations...............................................................................49
29 Power Specifications for the Pentium III Processor – Low Power..............................................50
30 Thermal Diode Interface .............................................................................................................51
31 Thermal Diode Specifications.....................................................................................................51
32 BSEL[1:0] Encoding....................................................................................................................55
33 Voltage Identification Encoding ..................................................................................................63
34 Input Signals...............................................................................................................................64
35 Output Signals ............................................................................................................................65
36 Input/Output Signals (Single Driver) ...........................................................................................65
37 Input/Output Signals (Multiple Driver).........................................................................................65
38 PLL Filter Inductor Recommendations .......................................................................................67
39 PLL Filter Capacitor Recommendations.....................................................................................68
40 PLL Filter Resistor Recommendations .......................................................................................68
Datasheet
7
Contents
Revision History
Date
Revision
Description
April, 2002
June, 2001
March, 2001
003
002
001
Updated introduction
Pins AD20, AA17, H4 and G4 changed to be NC.
First release of this document.
8
Datasheet
Intel® Pentium® III Processor – Low Power
1.0
Introduction
The Intel® Pentium® III Processor – Low Power offers high performance and low power
consumption. Key performance advancements include Internet Streaming SIMD instructions, an
advanced transfer cache architecture, and a processor system bus speed of 100 MHz. These
features are offered in a BGA2 package.
The integrated L2 cache improves performance, and complements the system bus by providing
critical data faster and reducing total system power consumption. The processor’s 64-bit wide
Gunning Transceiver Logic (GTL+) system bus provides a glueless, point-to-point interface for an
I/O bridge/memory controller, and is compatible with the 440BX and 440ZX-M AGPset Chipsets,
and the 440MX Chipset.
This document provides the electrical, mechanical and thermal specifications for the 700 MHz, 500
MHz and 400 MHz Pentium III Processor – Low Power. Please note that the 700 MHz Intel®
Pentium® III processor – Low Power (product number KC80526GY850256) is the same silicon as
the Mobile Intel® Pentium® III processor at 850/700 MHz with Intel® SpeedStep™ technology and
is labeled as such. When Intel SpeedStep technology is not implemented, the processor defaults to
700 MHz operation at 1.35 V. EID does not support Intel SpeedStep.
Figure 1 shows the components of a Pentium III processor/440BX or 440ZX-M AGPset -based
system and how the Pentium III Processor – Low Power connects to them. Figure 2 shows an
alternative Pentium III Processor – Low Power/440MX Chipset - based system.
Figure 1. Signal Groups of a Pentium® III Processor/440BX AGPset - Based System
Thermal
Sensor
APIC
Bus
Pentium® III
Processor –
Low Power
TAP
System
Bus
443BX
OR
440ZX-M
North Bridge
DRAM
PCI
OR
PIIX4E
South Bridge
System
Controller
IOAPIC
(optional)
V0000-03
ISA/EIO
Datasheet
9
Intel® Pentium® III Processor – Low Power
Figure 2. Signal Groups of a Pentium® III Processor/440MX Chipset - Based System
Thermal
Sensor
Pentium® III
TAP
Processor –
Low Power
System
Bus
DRAM
440MX
PCIset
OR
System
V0000-04
Controller
X-bus
PCI
1.1
Overview
• Performance features
— Supports the Intel Architecture with Dynamic Execution
— Supports Intel MMX™ technology
— Supports streaming SIMD extensions for enhanced video, sound, and 3D performance
— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
• On-die primary (L1) instruction and data caches
— 4-way set associative, 32-byte line size, 1 line per sector
— 16-Kbyte instruction cache and 16-Kbyte write-back data cache
— Cacheable range controlled by processor programmable registers
10
Datasheet
Intel® Pentium® III Processor – Low Power
• On-die second level (L2) cache
— 8-way set associative, 32-byte line size, 1 line per sector
— Operates at full core speed
— 256-Kbyte, ECC protected cache data array
• GTL+ system bus interface
— 64-bit data bus, 100-MHz operation
— Uniprocessor, two loads only (processor and I/O bridge/memory controller)
— Integrated termination
• Processor clock control
— Quick Start for low power, low exit latency clock “throttling”
— Deep Sleep mode for lower power dissipation
• Thermal diode for measuring processor temperature
1.2
Terminology
In this document a “#” symbol following a signal name indicates that the signal is active low. This
means that when the signal is asserted (based on the name of the signal) it is in an electrical low
state. Otherwise, signals are driven in an electrical high state when they are asserted. In state
machine diagrams, a signal name in a condition indicates the condition of that signal being
asserted. If the signal name is preceded by a “!” symbol, then it indicates the condition of that
signal not being asserted. For example, the condition “!STPCLK# and HS” is equivalent to “the
active low signal STPCLK# is unasserted (i.e., it is at 1.5 V) and the HS condition is true.” The
symbols “L” and “H” refer respectively to electrical low and electrical high signal levels. The
symbols “0” and “1” refer respectively to logical low and logical high signal levels. For example,
BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = “LHLH” also
refers to a hexadecimal “A.” The symbol “X” refers to a “Don’t Care” condition, where a “0” or a
“1” results in the same behavior.
1.3
References
CK97 Clock Driver Specification (Contact your Intel Field Sales Representative)
Intel® Architecture Software Developer’s Manual (Order Number 243193)
Volume I: Basic Architecture (Order Number 243190)
Volume II: Instruction Set Reference (Order Number 243191)
Volume III: System Programming Guide (Order Number 243192)
Mobile Pentium® III Processor I/O Buffer Models, IBIS Format (Available in electronic form;
Contact your Intel Field Sales Representative)
Mobile Pentium® III Processor GTL+ System Bus Layout Guideline (Contact your Intel Field Sales
Representative)
Datasheet
11
Intel® Pentium® III Processor – Low Power
2.0
Pentium® III Processor – Low Power Features
2.1
Features in the Pentium® III Processor – Low Power
2.1.1
On-die GTL+ Termination
The termination resistors for the GTL+ system bus are integrated onto the processor die. The
RESET# signal does not have on-die termination and requires an external 56.2 Ω ±1% terminating
resistor.
2.1.2
Streaming SIMD Extensions
The Pentium III Processor – Low Power implements Streaming SIMD (single instruction, multiple
data) extensions. Streaming SIMD extensions can enhance floating point, video, sound, and 3-D
application performance.
2.2
Power Management
2.2.1
Clock Control Architecture
The Pentium III Processor – Low Power clock control architecture (Figure 3) has been optimized
for leading edge low power designs. The clock control architecture consists of seven different
clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, and Deep
Sleep states. The Auto Halt state provides a low-power clock state that can be controlled through
the software execution of the HLT instruction. The Quick Start state provides a very low power and
low exit latency clock state that can be used for hardware controlled “idle” computer states. The
Deep Sleep state provides an extremely low-power state that can be used for “Power-On-Suspend”
computer states, which is an alternative to shutting off the processor’s power. Compared to the
Pentium processor exit latency of 1 ms, the exit latency of the Deep Sleep state has been reduced to
30 µs in the Pentium III Processor – Low Power. Performing state transitions not shown in Figure 3
is neither recommended nor supported.
The Stop Grant and Quick Start clock states are mutually exclusive, i.e., a strapping option on
signal A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start
state is enabled by strapping the A15# signal to ground at Reset; otherwise, asserting the STPCLK#
signal puts the processor into the Stop Grant state. The Stop Grant state has a higher power level
than the Quick Start state and is designed for Symmetric Multi-Processing (SMP) platforms. The
Quick Start state has a much lower power level, but it can only be used in uniprocessor platforms.
Table 1 provides clock state characteristics, which are described in detail in the following sections.
2.2.2
Normal State
The Normal state of the processor is the normal operating mode where the processor’s core clock is
running and the processor is actively executing instructions.
12
Datasheet
Intel® Pentium® III Processor – Low Power
2.2.3
Auto Halt State
This is a low-power mode entered by the processor through the execution of the HLT instruction.
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#, INIT#,
RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to
the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued.
Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a
new Halt bus cycle.
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel®
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.
Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.
Figure 3. Clock Control States
STPCLK# and
QSE and SGA
Normal
HS=false
Quick
Start
(!STPCLK# and !HS)
or RESET#
HLT and
halt bus cycle
STPCLK# and
QSE and SGA
BCLK
stopped
halt
break
!STPCLK#
and HS
BCLK on
and QSE
STPCLK# and
!QSE and SGA
Auto
Halt
HS=true
Snoop
serviced
Snoop
occurs
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
!STPCLK#
and HS
Snoop
occurs
Snoop
serviced
STPCLK# and
!QSE and SGA
Snoop
occurs
Stop
Grant
HALT/Grant
Snoop
Snoop
serviced
SLP#
BCLK on
and !QSE
BCLK
stopped
!SLP# or
RESET#
Sleep
V0001-00
NOTES:
halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT – HLT instruction executed
HS – Processor Halt State
QSE – Quick Start State Enabled
SGA – Stop Grant Acknowledge bus cycle issued
stop break – BINIT#, RESET#
Datasheet
13
Intel® Pentium® III Processor – Low Power
2.2.4
Stop Grant State
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop
requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the
Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the
Normal state can be made by the deassertion of the STPCLK# signal or the occurrence of a stop
break event (a BINIT# or RESET# assertion).
The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization
unless STPCLK# has been de-asserted. RESET# assertion will cause the processor to immediately
initialize itself, but the processor will stay in the Stop Grant state after initialization until STPCLK#
is deasserted. A transition to the Sleep state can be made by the assertion of the SLP# signal.
While in the Stop Grant state, assertions of FLUSH#, SMI#, INIT#, INTR, and NMI (or
LINT[1:0]) will be latched by the processor. These latched events will not be serviced until the
processor returns to the Normal state. Only one of each event will be recognized upon return to the
Normal state.
2.2.5
Quick Start State
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the system bus priority
device. Because of its snooping behavior, Quick Start can only be used in a uniprocessor (UP)
configuration.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal
is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
2.2.6
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt, Stop
Grant, or Quick Start state. When a snoop transaction is presented on the system bus the processor
will enter the HALT/Grant Snoop state. The processor will remain in this state until the snoop has
been serviced and the system bus is quiet. After the snoop has been serviced, the processor will
return to its previous state. If the HALT/Grant Snoop state is entered from the Quick Start state,
then the input signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop state,
except for those signal transitions that are required to perform the snoop.
14
Datasheet
Intel® Pentium® III Processor – Low Power
2.2.7
Sleep State
The Sleep state is a very low-power state in which the processor maintains its context and the
phase-locked loop (PLL) maintains phase lock. The Sleep state can only be entered from the Stop
Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt
states.
The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven
active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be
driven inactive to ensure that the processor correctly initializes itself.
Input signals (other than RESET#) may not change while the processor is in the Sleep state or
transitioning into or out of the Sleep state. Input signal changes at these times will cause
unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the
Sleep state.
While in the Sleep state, the processor can enter its lowest power state, the Deep Sleep state.
Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be
removed in the Sleep state.
2.2.8
Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is in
the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the Low
state.
The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the
BCLK input is restarted. Due to the PLL lock latency, there is a delay of up to 30 µs after the clocks
have started before this state transition happens. PICCLK may be removed in the Deep Sleep state.
PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep
Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that
RESET# assertion will result in unpredictable behavior.
Datasheet
15
Intel® Pentium® III Processor – Low Power
Table 1. Clock State Characteristics
Clock State
Exit Latency
Snooping?
System Uses
Normal
N/A
Yes
Yes
Yes
Normal program execution
Auto Halt
Stop Grant
Approximately 10 bus clocks
10 bus clocks
S/W controlled entry idle mode
H/W controlled entry/exit throttling
Through snoop, to HALT/Grant
Snoop state: immediate
Quick Start
Yes
H/W controlled entry/exit throttling
Through STPCLK#, to Normal
state: 8 bus clocks
HALT/Grant
Snoop
A few bus clocks after the end
of snoop activity
Yes
No
No
Supports snooping in the low power states
To Stop Grant state 10 bus
clocks
H/W controlled entry/exit desktop idle mode
support
Sleep
H/W controlled entry/exit powered-on
suspend support
Deep Sleep
30 µs
NOTE: See Table 29 for power dissipation in the low-power states.
2.2.9
Operating System Implications of Low-power States
There are a number of architectural features of the Pentium III Processor – Low Power that do not
function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp counter
and the performance monitor counters are not guaranteed to count in the Quick Start or Sleep
states. The local APIC timer and performance monitor counter interrupts should be disabled before
entering the Deep Sleep state or the resulting behavior will be unpredictable.
2.2.10
GTL+ Signals
The Pentium III Processor – Low Power system bus signals use a variation of the low-voltage
swing GTL signaling technology. The Pentium III Processor – Low Power system bus specification
is similar to the Pentium II processor system bus specification, which is a version of GTL with
enhanced noise margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the Pentium III Processor – Low Power.
The GTL+ system bus of the Pentium II processor was designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. However, in most
embedded systems the system bus only has two loads (the processor and the chipset) and the bus
traces are short. It is possible to change the layout and termination of the system bus to take
advantage of the embedded environment using the same GTL+ I/O buffers. In embedded systems
the GTL+ system bus is terminated at one end only. This termination is provided on the processor
core (except for the RESET# signal). Refer to the Mobile Pentium® III Processor GTL+ System Bus
Layout Guideline for details on laying out the GTL+ system bus.
16
Datasheet
Intel® Pentium® III Processor – Low Power
2.2.11
Pentium® III Processor – Low Power CPUID
The CPUID instruction does not distinguish between the Pentium III processor and the Pentium III
Processor – Low Power. After a power-on RESET or when the CPUID version information is
loaded, the EAX register contains the values shown in
Table 2. After the L2 cache is initialized, the CPUID cache/TLB descriptors will be the values
shown in Table 3.
Table 2. Pentium® III Processor – Low Power CPUID
EAX[31:0]
EBX[7:0]
Brand ID
02
Reserved [31:14] Type [13:12]
Family [11:8]
6
Model [7:4]
8
Stepping [3:0]
X
X
0
Table 3. Pentium® III Processor – Low Power CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 82H
3.0
Electrical Specifications
3.1
Processor System Signals
Table 4 lists the processor system signals by type. All GTL+ signals are synchronous with the
BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS
input signals can be applied asynchronously.
Table 4. System Signal Groups (Sheet 1 of 2)
Group Name
Signals
GTL+ Input
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
PRDY#
GTL+ Output
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#
GTL+ I/O
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#,
SMI#, STPCLK#
1.5 V CMOS Input 2
2.5 V CMOS Input 1, 3
1.5 V Open Drain Output 2
3.3 V CMOS Input4
NOTES:
PWRGOOD
FERR#, IERR#
BSEL[1:0]
1. See Section 8.1.39 for information on the PWRGOOD signal.
2. These signals are tolerant to 1.5 V only. See Table 5 for the recommended pull-up resistor.
3. These signals are tolerant to 2.5 V only. See Table 5 for the recommended pull-up resistor.
4. These signals are tolerant to 3.3 V only. See Table 5 for the recommended pull-up resistor.
5. V is the power supply for the core logic. PLL1 and PLL2 are the power supply for the PLL analog
CC
section. V
is the power supply for the system bus buffers. V
is the voltage reference for the GTL+
CCT
REF
input buffers. V is system ground.
SS
Datasheet
17
Intel® Pentium® III Processor – Low Power
Table 4. System Signal Groups (Sheet 2 of 2)
Group Name
Signals
Clock 3
BCLK
APIC Clock 3
APIC I/O 2
PICCLK
PICD[1:0]
Thermal Diode
TAP Input 2
TAP Output 2
THERMDA, THERMDC
TCK, TDI, TMS, TRST#
TDO
CLKREF, CMOSREF, EDGECTRLP, NC, PLL1, PLL2, RSVD, RTTIMPEDP,
TESTHI, TESTLO[2:1], V , V , VID[4:0], V , V
Power/Other 5
CC
CCT
REF SS
NOTES:
1. See Section 8.1.39 for information on the PWRGOOD signal.
2. These signals are tolerant to 1.5 V only. See Table 5 for the recommended pull-up resistor.
3. These signals are tolerant to 2.5 V only. See Table 5 for the recommended pull-up resistor.
4. These signals are tolerant to 3.3 V only. See Table 5 for the recommended pull-up resistor.
5. V is the power supply for the core logic. PLL1 and PLL2 are the power supply for the PLL analog
CC
section. V
is the power supply for the system bus buffers. V
is the voltage reference for the GTL+
CCT
REF
input buffers. V is system ground.
SS
The CMOS, APIC, and TAP inputs can be driven from ground to 1.5 V. BCLK, PICCLK, and
PWRGOOD can be driven from ground to 2.5 V. The APIC data and TAP outputs are Open-drain
and should be pulled up to 1.5 V using resistors with the values shown in Table 5. If Open-drain
drivers are used for input signals, then they should also be pulled up to the appropriate voltage
using resistors with the values shown in Table 5.
Table 5. Recommended Resistors for Pentium III Processor – Low Power Signals
Recommended
Resistor Value (Ω)
Pentium III Processor – Low Power Signal1, 2
10 pull-down
56.2 pull-up
150 pull-up
270 pull-up
680 pull-up
1K pull-up
BREQ0#3
RESET#4
PICD[1:0], TDI, TDO
SMI#
STPCLK#
INIT#, TCK, TMS
TRST#
1K pull-down
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR, LINT1/
NMI, PREQ#, PWRGOOD, SLP#
1.5K pull-up
NOTES:
1. The recommendations above are only for signals that are being used. These recommendations are
maximum values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should
not violate the chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors
for signals that are not being used.
2. Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if
there is too much undershoot.
3. A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
4. A 56.2Ω 1% terminating resistor connected to V
is required.
CCT
18
Datasheet
Intel® Pentium® III Processor – Low Power
3.1.1
Power Sequencing Requirements
The Pentium III Processor – Low Power has no power sequencing requirements. Intel recommends
that all of the processor power planes rise to their specified values within one second of each other.
The VCC power plane must not rise too fast. At least 200 µs (TR) must pass from the time that VCC
is at 10% of its nominal value until the time that VCC is at 90% of its nominal value (see Figure 4).
Figure 4. Vcc Ramp Rate Requirement
Vcc
90% Vcc (nominal)
10% Vcc (nominal)
Volts
TR
Time
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, Intel recommends that the Pentium III Processor – Low
Power and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain after
any devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer should be
used to reduce the TDO output voltage of the last 3.3/5.0 V device down to the 1.5 V range that the
Pentium III Processor – Low Power can tolerate. Multiple copies of TMS and TRST# must be
provided, one for each voltage level.
A Debug Port and connector may be placed at the start and end of the JTAG chain containing the
processor, with TDI to the first component coming from the Debug Port and TDO from the last
component going to the Debug Port. There are no requirements for placing the Pentium III
Processor – Low Power in the JTAG chain, except for those that are dictated by voltage
requirements of the TAP signals.
3.1.3
3.1.4
Catastrophic Thermal Protection
The Pentium III Processor – Low Power does not support catastrophic thermal protection or the
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the
system against excessive temperatures.
Unused Signals
All signals named NC and RSVD must be unconnected. The TESTHI signal should be pulled up to
VCCT. The TESTLO1 and TESTLO2 signal should be pulled down to VSS. Unused GTL+ inputs,
outputs and bidirectional signals should be unconnected. Unused CMOS active low inputs should
be connected to VCCT and unused active high inputs should be connected to VSS. Unused Open-
drain outputs should be unconnected. If the processor is configured to enter the Quick Start state
Datasheet
19
Intel® Pentium® III Processor – Low Power
rather than the Stop Grant state, then the SLP# signal should be connected to VCCT. When tying
any signal to power or ground, a resistor will allow for system testability. For unused signals, Intel
suggests that 1.5-kΩ resistors are used for pull-ups and 1-kΩ resistors are used for pull-downs.
If the local APIC is hardware disabled, then PICCLK and PICD[1:0] should be tied to VSS with a
1-kΩ resistor, one resistor can be used for the three signals. Otherwise PICCLK must be driven
with a clock that meets specification (see Table 16) and the PICD[1:0] signals must be pulled up to
V
CCT with 150-Ω resistors, even if the local APIC is not used.
BSEL1 must be connected to VSS and BSEL0 must be pulled up to VCCT. VID[4:0] should be
connected to VSS if they are not used.
If the TAP signals are not used then the inputs should be pulled to ground with 1-kΩ resistors and
TDO should be left unconnected.
3.1.5
Signal State in Low-power States
System Bus Signals
3.1.5.1
All of the system bus signals have GTL+ input, output, or input/output drivers. Except when
servicing snoops, the system bus signals are three-stated and pulled up by the termination resistors.
Snoops are not permitted in the Sleep and Deep Sleep states.
3.1.5.2
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle.
These input buffers have no internal pull-up or pull-down resistors and system logic can use CMOS
or Open-drain drivers to drive them.
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is three-stated (and
pulled-up) when the processor is functioning normally. The FERR# output can be either three-
stated or driven to VSS when the processor is in a low-power state depending on the condition of
the floating point unit. Since this signal is a DC current path when it is driven to VSS, Intel
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep
state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is
hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off
PICCLK by holding it at VSS. The system bus clock should be held at VSS when it is stopped in the
Deep Sleep state.
In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to
APIC bus messages. These signals are required to be three-stated and pulled-up when the processor
is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.
20
Datasheet
Intel® Pentium® III Processor – Low Power
3.2
Power Supply Requirements
3.2.1
Decoupling Recommendations
The amount of bulk decoupling required on the VCC and VCCT planes to meet the voltage tolerance
requirements for the Pentium III Processor – Low Power are a strong function of the power supply
design. Contact your Intel Field Sales Representative for tools to help determine how much bulk
decoupling is required.
For 700 MHz processors, the following decoupling is recommended. The processor core power
plane (VCC) should have fifteen 0.68 µF 0603 ceramic capacitors (using X7R dielectric for thermal
reasons) placed directly under the package using two vias for power and two vias for ground to
reduce the trace inductance. Also to minimize inductance, traces to those vias should be 22 mils (in
width) from the capacitor pads to match the via-pad size (assuming 22-mil pad size). Twenty-four
2.2 µF 0805, X5R mid frequency decoupling capacitors should be placed around the die as close to
the die as flex solution allows. The system bus buffer power plane (VCCT) should have twenty 0.1-
µF high frequency decoupling capacitors around the die.
For 500 and 400 MHz processors, the processor core power plan (VCC) should have eight 0.1-µF
high frequency decoupling capacitors placed underneath the die and twenty 0.1-µF mid frequency
decoupling capacitors placed around the die as close to the die as flex solution allows. The system
bus buffer power plane (VCCT) should have twenty 0.1-µF high frequency decoupling capacitors
around the die.
3.2.2
Voltage Planes
All VCC and VSS pins/balls must be connected to the appropriate voltage plane. All VCCT and
V
REF pins/balls must be connected to the appropriate traces on the system electronics. In addition
to the main VCC, VCCT, and VSS power supply signals, PLL1 and PLL2 provide analog decoupling
to the PLL section. PLL1 and PLL2 should be connected according to Figure 5. Do not connect
PLL2 directly to VSS. Section 9.0 contains the RLC filter specification.
Figure 5. PLL RLC Filter
L1
R1
PLL1
PLL2
VCCT
C1
V0027-01
Datasheet
21
Intel® Pentium® III Processor – Low Power
3.3
System Bus Clock and Processor Clocking
The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
Pentium III Processor – Low Power core frequency is a multiple of the BCLK frequency. The
processor core frequency is configured during manufacturing. The configured bus ratio is visible to
software in the Power-on configuration register, see Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for easier
distribution of signals within the system. Clock multiplication within the processor is provided by
the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK input. During
Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the
phase of BCLK. This time is called the PLL lock latency, which is specified in Section 3.6, AC
timing parameters T18 and T47.
3.4
Maximum Ratings
Table 6 contains the Pentium III Processor – Low Power stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are provided in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 6. Pentium® III Processor – Low Power Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
T
Storage Temperature
(Abs) Supply Voltage with respect to V
–40
–0.5
–0.3
–0.3
85
2.1
2.1
2.1
°C
V
Note 1
Storage
V
CC
SS
V
System Bus Buffer Voltage with respect to V
V
CCT
SS
V
System Bus Buffer DC Input Voltage with respect to V
System Bus Buffer DC Input Voltage with respect to V
V
Notes 2, 3
Notes 2, 4
IN GTL
SS
V
+
CCT
V
—
V
IN GTL
CCT
0.7 V
2.1
3.3
3.5
5.5
5
V
1.5 V Buffer DC Input Voltage with respect to V
2.5 V Buffer DC Input Voltage with respect to V
3.3 V Buffer DC Input Voltage with respect to V
–0.3
–0.3
–0.3
—
V
V
Note 5
Note 6
Note 7
IN15
IN25
IN33
SS
SS
SS
SS
V
V
V
V
VID ball/pin DC Input Voltage with respect to V
VID Current
V
INVID
I
mA
Note 8
VID
NOTES:
1. The shipping container is only rated for 65°C.
2. Parameter applies to the GTL+ signal groups only. Compliance with both V
specifications is required.
IN GTL
3. The voltage on the GTL+ signals must never be below –0.3 or above 2.1 V with respect to ground.
4. The voltage on the GTL+ signals must never be above V
short to ground may occur.
+ 0.7 V even if it is less than V + 2.1 V, or a
CCT
SS
5. Parameter applies to CMOS, Open-drain, APIC, and TAP bus signal groups only.
6. Parameter applies to BCLK, CLKREF, PICCLK and PWRGOOD signals.
7. Parameter applies to BSEL[1:0] signals.
8. Parameter applies to each VID pin/ball individually.
22
Datasheet
Intel® Pentium® III Processor – Low Power
3.5
DC Specifications
Table 7 through Table 10 lists the DC specifications for the Pentium III Processor – Low Power.
Specifications are valid only while meeting specifications for the junction temperature, clock
frequency, and input voltages. Care should be taken to read all notes associated with each
parameter.
Table 7. Power Specifications
T = 0°C to 100°C; 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CCT
1
Symbol
Parameter
Min
Typ
Max
Unit
Notes
±100 mV
Notes 7, 8
V
Transient V for core logic
1.25
1.35
1.45
V
CC
CC
±100 mV
Note 2, 8
V
Static V for core logic
1.25
1.35
1.45
V
V
V
CC,DC
CC
V
for System Bus Buffers, Transient
±115 mV,
Note 7, 8
CC
V
1.385 1.50 1.615
1.455 1.50 1.545
CCT
tolerance
V
for System Bus Buffers, Static
CC
V
±3%, Notes 2, 8
CCT,DC
tolerance
Current for V at core frequency
CC
12.8
9.5
7.8
A
A
A
at 700 MHz & 1.35 V
at 500 MHz & 1.35 V
at 400 MHz & 1.35 V
I
Note 4
CC
I
Current for V
2.5
2.7
A
A
Notes 3, 4
Note 4
CCT
CCT
Processor Stop Grant and Auto Halt
current
I
I
CC,SG
at 1.35 V (for 700 MHz)
Processor Quick Start and Sleep current
at 1.35 V (for 700 MHz)
2.4
A
Note 4
CC,QS
Processor Deep Sleep Leakage current
at 1.35 V (for 700 MHz)
I
2.1
A
Note 4
CC,DSLP
dI /dt
V
power supply current slew rate
CC
1400
A/µs
Notes 5, 6
CC
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, output
load ranges specified in this table, temperature, and warm up.
3. I
4. I
is the current supply for the system bus buffers, including the on-die termination.
CCT
specifications are specified at V , and 100°C and under maximum signal
, V
CCx,max
CC, DC max CCT,max
loading conditions.
5. Based on simulations and averaged over the duration of any change in current. Use to compute the
maximum inductance and reaction time of the voltage regulator. This parameter is not tested.
6. Maximum values specified by design/characterization at nominal V
and V .
CC
must be within this range under all operating conditions, including maximum current transients.
CCT
7. V
V
CCx
CCx
must return to within the static voltage specification, V
, within 100 µs after a transient event.
CCx,DC
8. Voltages are measured at the package ball.
The signals on the Pentium III Processor – Low Power system bus are included in the GTL+ signal
group. These signals are specified to be terminated to V . The DC specifications for these signals
CC
are listed in Table 8 and the termination and reference voltage specifications for these signals are
listed in Table 9. The Pentium III Processor – Low Power requires external termination and a
V
. Refer to the Mobile Pentium III Processor GTL+ System Bus Layout Guideline for full
REF
details of system V
and V
requirements. The CMOS, Open-drain, and TAP signals are
REF
CCT
designed to interface at 1.5 V levels to allow connection to other devices. BCLK and PICCLK are
designed to receive a 2.5-V clock signal. The DC specifications for these signals are listed in Table
10.
Datasheet
23
Intel® Pentium® III Processor – Low Power
Table 8. GTL+ Signal Group DC Specifications
T = 0°C to 100°C; V = 1.35 V ±100 mV; V = 1.50 V ±115 mV
CCT
J
CC
Symbol
Parameter
Min
Max
Unit
Notes
in Table 9
V
R
Output High Voltage
—
—
V
Ω
See V
CCT,max
OH
Output Low Drive Strength
16.67
±100
ON
I
Leakage Current for Inputs, Outputs and I/Os
µA
(0 ≤ V
≤ V )
CCT
L
IN/OUT
Table 9. GTL+ Bus DC Specifications
T = 0°C to 100°C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
Symbol
Parameter
Min
Typ
Max
1.615
Unit
Notes
V
V
Bus Termination Voltage
Input Reference Voltage
1.385
1.5
V
V
Note 1
CCT
2/ V
– 2% 2/ V
2/ V
+ 2%
±2%, Note 2
REF
3
CCT
3
CCT
3
CCT
On-die R
Note 3
,
TT
R
Bus Termination Strength
50
56
65
Ω
TT
NOTES:
1. For simulation use 1.50 V ±10%. For typical simulation conditions use V
(1.5 V –10%).
CCTmin
2. V
should be created from V
by a voltage divider.
REF
3. The RESET# signal does not have an on-die R . It requires an off-die 56.2 Ω ±1% terminating resistor
CCT
TT
connected to V
.
CCT
24
Datasheet
Intel® Pentium® III Processor – Low Power
Table 10. Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V = 1.50 V ±115 mV
CCT
J
CC
Symbol
Parameter
Min
Max
Unit
Notes
V
V
CMOSREFmin
– 200 mV
V
V
V
Input Low Voltage, 1.5 V CMOS
Input Low Voltage, 2.5 V CMOS
Input Low Voltage, 3.3 V CMOS
Input Low Voltage, BCLK
–0.15
–0.3
–0.3
–0.3
V
V
V
V
V
V
V
IL15
IL25
IL33
0.7
Notes 1, 2
Note 7
CMOSREFmin
– 200 mV
V
0.5
Note 2
IL,BCLK
V
V
CMOSREFmax
+ 200 mV
V
V
V
Input High Voltage, 1.5 V CMOS
Input High Voltage, 2.5 V CMOS
Input High Voltage, 3.3 V CMOS
V
CCT
IH15
IH25
IH33
2.0
2.625
3.465
Notes 1, 2
Note 7
CMOSREFmax
+ 200 mV
V
Input High Voltage, BCLK
Output Low Voltage
2.0
2.625
0.4
V
V
Note 2
Note 3
IH,BCLK
V
OL
All outputs are
Open-drain
V
Output High Voltage, 1.5 V CMOS
Output High Voltage, 2.5 V CMOS
N/A
N/A
1.615
2.625
V
V
OH15
OH25
All outputs are
Open-drain
V
V
Output High Voltage, VID ball/pins
CMOSREF Voltage
N/A
0.90
1.175
10
5.50
1.10
V
V
5V + 10%
Note 4
OH,VID
V
CMOSREF
V
CLKREF Voltage
1.325
V
1.25V ±6%, Note 4
Note 6
CLKREF
I
Output Low Current
mA
OL
Leakage Current for Inputs,
Outputs and I/Os
I
±100
µA
Notes 5, 8
L
NOTES:
1. Parameter applies to the PICCLK and PWRGOOD signals only.
2. V and V only apply when BCLK and PICCLK are stopped. BCLK and PICCLK should be
ILx,min
IHx,max
stopped in the low state. See Table 20 for the BCLK voltage range specifications for when BCLK is running.
See Table 21 for the PICCLK voltage range specifications for when PICCLK is running.
3. Parameter measured at 10 mA.
4. V
and V
should be created from a stable voltage supply using a voltage divider.
CMOSREF
CLKREF
5. (0 ≤
≤ V
).
VIN/OUT
IHx,max
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, V
cannot be guaranteed if this specification is exceeded.
OL,max
7. Parameter applies to BSEL[1:0] signals only.
8. For BSEL[1:0] signals, I
(with 1 KΩ pull-up to 3.3 V)
can be up to 100 µA (with 1 KΩ pull-up to 1.5 V), and can be up to 500 µA
L, Max
Datasheet
25
Intel® Pentium® III Processor – Low Power
3.6
AC Specifications
3.6.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications
Table 11 through Table 19 provide AC specifications associated with the Pentium III Processor –
Low Power. The AC specifications are divided into the following categories: Table 11 contains the
system bus clock specifications; Table 12 contains the processor core frequencies; Table 13
contains the GTL+ specifications; Table 14 contains the CMOS and Open-drain signal groups
specifications; Table 15 contains timings for the reset conditions; Table 16 contains the APIC
specifications; Table 17 contains the TAP specifications; and Table 18 and Table 19 contain the
power management timing specifications.
All system bus AC specifications for the GTL+ signal group are relative to the rising edge of the
BCLK input at 1.25 V. All GTL+ timings are referenced to VREF for both “0” and “1” logic levels
unless otherwise specified. All APIC, TAP, CMOS, and Open-drain signals except PWRGOOD are
referenced to 0.75 V.
Table 11. System Bus Clock AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes1
System Bus Frequency
BCLK Period
100
10
MHz
ns
T1
T2
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Note 2
Notes 3, 4
BCLK Period Stability
BCLK High Time
BCLK Low Time
BCLK Rise Time
BCLK Fall Time
±250
ps
T3
2.70
2.45
ns
at >2.0 V
T4
ns
at <0.5 V
T5
0.175
0.175
0.875
0.875
ns
(0.9 V – 1.6 V)
(1.6 V – 0.9 V)
T6
ns
NOTES:
1. All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25 V. All CMOS
signals are referenced at 0.75 V.
2. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3. Not 100% tested. Specified by design/characterization.
4. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a
component of BCLK skew between devices.
Table 12. Supported Processor Frequencies
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
BCLK Frequency
(MHz)
Core Frequency
Power-on Configuration
bits [27, 25:22]
Frequency Multiplier
(MHz)
100
100
100
4
5
7
400
500
700
0, 0010
0, 0000
0, 1001
NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other
than those listed above will not be validated by Intel and are not guaranteed. The frequency
multiplier is programmed into the processor when it is manufactured and it cannot be changed.
26
Datasheet
Intel® Pentium® III Processor – Low Power
Table 13. GTL+ Signal Groups AC Specifications
R
= 56 Ω internally terminated to V
; V
= 2/ V
; load = 0 pF;
TT
CCT REF
3
CCT
T = 0° C to 100° C; V = 1.35 V ±100 mV; V = 1.50 V ±115 mV
J
CC
CCT
Symbol
Parameter1
Min
Max Unit
Figure
Notes
T7
T8
T9
GTL+ Output Valid Delay
GTL+ Input Setup Time
GTL+ Input Hold Time
0.2
1.2
2.7
ns
ns
ns
Figure 8
Figure 9
Figure 9
Notes 2, 3
Notes 4
0.80
Figure 10
Figure 11
T10
RESET# Pulse Width
1
ms
Note 5
NOTES:
1. All AC timings for GTL+ signals are referenced to the BCLK rising edge at 1.25 V. All GTL+ signals are
referenced at V
.
REF
2. RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously.
3. Specification is for a minimum 0.40 V swing.
4. Specification is for a maximum 1.0 V swing.
5. After V , V
, and BCLK become stable and PWRGOOD is asserted.
CC CCT
Table 14. CMOS and Open-drain Signal Groups AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
1, 2
Parameter
Symbol
Min Max
Unit
Figure
Notes
1.5 V Input Pulse Width, except
PWRGOOD and LINT[1:0]
Active and
Inactive states
T14
2
BCLKs
BCLKs
Figure 8
Figure 8
T14B
T15
LINT[1:0] Input Pulse Width
6
Note 3
PWRGOOD Inactive Pulse Width
10
BCLKs Figure 11
Notes 4, 5
NOTES:
1. All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25 V. All
CMOS and Open-drain signals are referenced at 0.75 V.
2. Minimum output pulse width on CMOS outputs is 2 BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after V , V
and BCLK become stable. PWRGOOD must remain below
CC
CCT
V
from Table 10 until all the voltage planes meet the voltage tolerance specifications in Table 7 and
IL25,max
BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles. PWRGOOD must rise
glitch-free and monotonically to 2.5 V.
5. If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below V
specifications.
until all the voltage planes meet the voltage tolerance
IL25,max
Datasheet
27
Intel® Pentium® III Processor – Low Power
Table 15. Reset Configuration AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
Symbol
Parameter
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Setup
Time
Min Max
Unit
Figure
Notes
Before
deassertion of
RESET#
Figure 8
Figure 9
T16
T17
4
2
1
BCLKs
After clock
that deasserts
RESET#
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Hold Time
Figure 8
Figure 9
20
BCLKs
ms
Before
T18
RESET#/PWRGOOD Setup Time
Figure 11 deassertion of
RESET#1
NOTE:
1. At least 1 ms must pass after PWRGOOD rises above V
timing specification until RESET# may be deasserted.
from Table 10 and BCLK meets its AC
IH25,min
Table 16. APIC Bus Signal AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T21
T22
T23
T24
T25
T26
T27
T28
PICCLK Frequency
PICCLK Period
2
33.3
500
MHz
ns
Note 2
30
Figure 6
Figure 6
Figure 6
Figure 6
Figure 6
Figure 9
Figure 9
PICCLK High Time
PICCLK Low Time
PICCLK Rise Time
PICCLK Fall Time
PICD[1:0] Setup Time
PICD[1:0] Hold Time
10.5
10.5
0.25
0.25
5.0
ns
at >1. 7 V
at <0.7 V
ns
3.0
3.0
ns
(0.7 V – 1.7 V)
(1.7 V – 0.7 V)
Note 3
ns
ns
2.5
ns
Note 3
PICD[1:0] Valid Delay (Rising Edge)
PICD[1:0] Valid Delay (Falling Edge)
1.5
1.5
8.7
12.0
ns
ns
T29
Figure 8
Notes 3, 4, 5
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.25 V. All CMOS signals are
referenced at 0.75 V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5 V at reset. If PICD0 is strapped to V at reset then
SS
the minimum frequency is 0 MHz.
3. Referenced to PICCLK Rising Edge.
4. For Open-drain signals, Valid Delay is synonymous with Float Delay.
5. Valid delay timings for these signals are specified into 150Ω to 1.5 V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.
28
Datasheet
Intel® Pentium® III Processor – Low Power
Table 17. TAP Signal AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V = 1.50 V ±115 mV
CCT
J
CC
Symbol
Parameter1
Min
Max
Unit
Figure
Notes
T30
T31
T32
T33
TCK Frequency
TCK Period
—
60
16.67
MHz
ns
—
Figure 6
Figure 6
Figure 6
TCK High Time
TCK Low Time
25.0
25.0
ns
≥ 1.2 V, Note 2
≤ 0.6 V, Note 2
ns
(0.6 V – 1.2 V),
Notes 2, 3
T34
T35
T36
TCK Rise Time
TCK Fall Time
5.0
5.0
ns
ns
ns
Figure 6
Figure 6
Figure 13
(1.2 V – 1.6 V),
Notes 2, 3
Asynchronous,
Note 2
TRST# Pulse Width
40.0
T37
T38
TDI, TMS Setup Time
5.0
14.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Note 4
Note 4
TDI, TMS Hold Time
T39
TDO Valid Delay
10.0
25.0
25.0
25.0
Notes 5, 6
T40
TDO Float Delay
Notes 2, 5, 6
Notes 5, 7, 8
Notes 2, 5, 7, 8
Notes 4, 7, 8
Notes 4, 7, 8
T41
All Non-Test Outputs Valid Delay
All Non-Test Outputs Float Delay
All Non-Test Inputs Setup Time
All Non-Test Inputs Hold Time
2.0
T42
T43
5.0
T44
13.0
NOTES:
1. All AC timings for TAP signals are referenced to the TCK rising edge at 0.75 V. All TAP and CMOS signals
are referenced at 0.75 V.
2. Not 100% tested. Specified by design/characterization.
3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. Valid delay timing for this signal is specified into 150Ω terminated to 1.5 V and 0 pF of external load. For
real system timings these specifications must be derated for external capacitance at 105 ps/pF.
7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.
Datasheet
29
Intel® Pentium® III Processor – Low Power
Table 18. Quick Start/Deep Sleep AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V
= 1.50 V ±115 mV
J
CC
CCT
Symbol
Parameter1
Min Max
Unit
Figure
Notes
T45
T46
Stop Grant Cycle Completion to Clock Stop
100
BCLKs
µs
Figure 14
Figure 14
Stop Grant Cycle Completion to Input Signals Stable
0
30
Figure 14
Figure 15
T47
Deep Sleep PLL Lock Latency
0
µs
Note 2
T48
T49
STPCLK# Hold Time from PLL Lock
0
8
ns
Figure 14
Figure 14
Input Signal Hold Time from STPCLK# Deassertion
BCLKs
NOTES:
1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2. The BCLK Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Table 19. Stop Grant/Sleep/Deep Sleep AC Specifications
T = 0° C to 100° C; V = 1.35 V ±100 mV; V = 1.50 V ±115 mV
CCT
J
CC
Symbol
Parameter
Min
Max
Unit
Figure
T50
T51
T52
T54
T55
T56
SLP# Signal Hold Time from Stop Grant Cycle Completion 100
SLP# Assertion to Input Signals Stable
BCLKs
ns
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
0
SLP# Assertion to Clock Stop
10
0
BCLKs
ns
SLP# Hold Time from PLL Lock
STPCLK# Hold Time from SLP# Deassertion
Input Signal Hold Time from SLP# Deassertion
10
10
BCLKs
BCLKs
NOTE: Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time
specification (T60) applies to Deep Sleep state exit under all conditions.
Figure 6 through Figure 16 are to be used in conjunction with Table 11 through Table 19.
Figure 6. PICCLK/TCK Clock Timing Waveform
T
h
T
r
VH
VTRIP
CLK
VL
T
f
T
l
NOTES:
T
p
D0003-01
Tr=T34, T25 (Rise Time)
Tf=T35, T26 (Fall Time)
Th=T32, T23 (High Time)
Tl=T33, T24 (Low Time)
Tp=T31, T22 (Period)
VTRIP=1.25 V for PICCLK; 0.75 V for TCK
VL=0.7 V for PICCLK; 0.6 V for TCK
VH=2.0 V for PICCLK; 1.2 V for TCK
30
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 7. BCLK Timing Waveform
T
h
T
r
VH
1.6V
0.9V
CLK
VTRIP
VL
T
f
T
l
NOTES:
Tr=T5 (Rise Time)
Tf=T6 (Fall Time)
T
p
D0003-02
Th=T3 (High Time)
Tl=T4 (Low Time)
Tp=T1 (Period)
VTRIP=1.25 V for BCLK
VL=0.5 V for BCLK
VH=2.0 V for BCLK
Figure 8. Valid Delay Timings
CLK
TX
T
x
V
Valid
Valid
Signal
TPW
NOTES:
T =T7, T11, T29 (Valid Delay)
D0004-00
x
T
=T14, T14B (Pulse Width)
pw
V=V
for GTL+ signal group; 0.75 V for CMOS,
REF
Open-drain, APIC, and TAP signal groups
Figure 9. Setup and Hold Timings
CLK
Ts
Th
V
Valid
ignal
D0005-00
NOTES:
T =T8, T12, T27 (Setup Time)
s
T =T9, T13, T28 (Hold Time)
h
V=V
for GTL+ signals; 0.75 V for CMOS, APIC, and TAP signals
REF
Datasheet
31
Intel® Pentium® III Processor – Low Power
Figure 10. Cold/Warm Reset and Configuration Timings
BCLK
T
u
T
t
RESET#
T
v
T
T
x
w
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
Valid
D0006-01
NOTES:
Tt=T9 (GTL+ Input Hold Time)
Tu=T8 (GTL+ Input Setup Time)
Tv=T10 (RESET# Pulse Width)
T18 (RESET#/PWRGOOD Setup Time)
Tw=T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)
Tx=T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)
Figure 11. Power-on Reset Timings
BCLK
V
CCT
V
CC
REF
V
VIH25,min
WRGOOD
VIL25,max
T
T
b
a
RESET#
D0007-01
NOTES:
Ta=T15 (PWRGOOD Inactive Pulse Width)
Tb=T10 (RESET# Pulse Width)
32
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 12. Test Timings (Boundary Scan)
TCK
T
T
w
v
0.75V
TDI, TMS
T
T
s
r
Input
Signals
T
T
u
x
TDO
T
T
z
y
Output
Signals
D0008-01
NOTES:
Tr=T43 (All Non-Test Inputs Setup Time)
Ts=T44 (All Non-Test Inputs Hold Time)
Tu=T40 (TDO Float Delay)
Tv=T37 (TDI, TMS Setup Time)
Tw=T38 (TDI, TMS Hold Time)
Tx=T39 (TDO Valid Delay)
Ty=T41 (All Non-Test Outputs Valid Delay)
Tz=T42 (All Non-Test Outputs Float Delay)
Figure 13. Test Reset Timings
0.75V
TRST#
T
q
D0009-01
NOTE:
Tq=T36 (TRST# Pulse Width)
Datasheet
33
Intel® Pentium® III Processor – Low Power
Figure 14. Quick Start/Deep Sleep Timing
Normal
Quick Start
Deep Sleep
Normal
Quick Start
Running
BCLK
Running
Tv
STPCLK#
Ty
Tx
CPU bus
SLP#
stpgnt
Tz
Tw
Changing
Compatibility
Signals
Frozen
V0010-00
NOTES:
Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)
Tw=T46 (Setup Time to Input Signal Hold Requirement)
Tx=T47 (Deep Sleep PLL Lock Latency)
Ty=T48 (PLL lock to STPCLK# Hold Time)
Tz=T49 (Input Signal Hold Time)
Figure 15. Stop Grant/Sleep/Deep Sleep Timing
Stop
Grant
Stop
Grant
Normal
Running
Sleep
Tv
Deep Sleep
Sleep
Normal
BCLK
Running
STPCLK#
Ty
CPU bus
SLP#
stpgnt
Tw
Tx
Tt
Tu
Tz
Compatibility
Signals
Changing
Changing
Frozen
V0011-00
NOTES:
Tt=T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
Tu=T51 (Setup Time to Input Signal Hold Requirement)
Tv=T52 (SLP# assertion to clock shut off delay)
Tw=T47 (Deep Sleep PLL lock latency)
Tx=T54 (SLP# Hold Time)
Ty=T55 (STPCLK# Hold Time)
Tz=T56 (Input Signal Hold Time)
34
Datasheet
Intel® Pentium® III Processor – Low Power
4.0
System Signal Simulations
Many scenarios have been simulated to generate a set of GTL+ processor system bus layout
guidelines, which are available in the Mobile Pentium III Processor GTL+ System Bus Layout
Guideline. Systems must be simulated using the IBIS model to determine if they are compliant
with this specification.
4.1
System Bus Clock (BCLK) and PICCLK AC Signal Quality
Specifications
Table 20 and Figure 17 show the signal quality for the system bus clock (BCLK) signal, and Table
21 and Figure 17 show the signal quality for the APIC bus clock (PICCLK) signal at the processor.
BCLK and PICCLK are 2.5 V clocks.
Table 20. BCLK Signal Quality Specification
Symbo
Parameter
l
Min
Max Unit
Figure
Notes
V1
V2
V
V
0.5
V
V
Figure 17
Figure 17
Note 1
Note 1
IL,BCLK
2.0
-0.7
2.0
IH,BCLK
Undershoot/Overshoot,
Note 2
V3
V
Absolute Voltage Range
3.5
V
Figure 17
IN
V4
V5
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
V
V
Figure 17
Figure 17
Absolute Value, Note 3
Absolute Value, Note 3
0.5
NOTES:
1. The clock must rise/fall monotonically between V
and V
.
IH,BCLK
IL,BCLK
2. These specifications apply only when BCLK is running, see Table 10 for the DC specifications for when
BCLK is stopped. BCLK may not be above V
clock cycle.
or below V
for more than 50% of the
IH,BCLK,max
BCLK,min
IL,
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can go to after passing the V
(rising) or V
(falling) voltage limits.
IH,BCLK
IL,BCLK
Table 21. PICCLK Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
V1
V2
V
V
0.7
3.5
0.7
V
V
Figure 17
Figure 17
Note 1
Note 1
IL25
IH25
2.0
–0.7
2.0
Undershoot, Overshoot,
Note 2
V3
V
Absolute Voltage Range
V
Figure 17
IN
V4
V5
PICCLK Rising Edge Ringback
PICCLK Falling Edge Ringback
V
V
Figure 17
Figure 17
Absolute Value, Note 3
Absolute Value, Note 3
NOTES:
1. The clock must rise/fall monotonically between V
and V
.
IL25
IH25
2. These specifications apply only when PICCLK is running, see Table 10 for the DC specifications for when
PICCLK is stopped. PICCLK may not be above V
clock cycle.
or below V
for more than 50% of the
IH25,max
IL25,min
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can go to after passing the V (rising) or V (falling) voltage limits.
IH25
IL25
Datasheet
35
Intel® Pentium® III Processor – Low Power
Figure 16. BCLK/PICCLK Generic Clock Waveform
V3max
V4
V2
V1
V5
V3min
V0012-01
4.2
GTL+ AC Signal Quality Specifications
Table 22, Figure 18, and Figure 19 illustrate the GTL+ signal quality specifications for the Pentium
III Processor – Low Power. Refer to the Pentium® II Processor Developer’s Manual for the GTL+
buffer specification. The Pentium III Processor – Low Power maximum overshoot and undershoot
specifications for a given duration of time are specified in Table 23. Contact your Intel Field Sales
representative for a copy of the OVERSHOOT_CHECKER tool. The OVERSHOOT_CHECKER
determines if a specific waveform meets the overshoot/undershoot specification. Figure 20 shows
the overshoot/undershoot waveform. The tolerances listed in Table 23 are conservative. Signals
that exceed these tolerances may still meet the processor overshoot/undershoot tolerance if the
OVERSHOOT_CHECKER tool says that they pass.
Table 22. GTL+ Signal Group Ringback Specification
Symbol
Parameter
Min
Unit
Figure
Notes
Figure 18
Figure 19
α
Overshoot
100
mV
Notes 1, 2
Figure 18
Figure 19
τ
ρ
φ
Minimum Time at High
Amplitude of Ringback
Final Settling Voltage
0.5
-200
200
N/A
ns
mV
mV
ns
Notes 1, 2
Notes 1, 2, 3
Notes 1, 2
Notes 1, 2
Figure 18
Figure 19
Figure 18
Figure 19
Figure 18
Figure 19
δ
Duration of Sequential Ringback
NOTES:
1. Specified for the edge rate of 0.3 – 0.8 V/ns. See Figure 18 for the generic waveform.
2. All values determined by design/characterization.
3. Ringback below V
,max + 200 mV is not authorized during low to high transitions. Ringback above
REF
V
– 200 mV is not authorized during high to low transitions.
REF,min
36
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 17. Low to High, GTL+ Receiver Ringback Tolerance
τ
VIH,BCLK
α
VREF,max+0.2V
φ
VREF,max
ρ
VREF,min-0.2V
δ
VIL,BCLK
Vstart
Clock
V0014-01
Time
Figure 18. High to Low, GTL+ Receiver Ringback Tolerance
VIH,BCLK
Vstart
VREF,max+0.2V
δ
ρ
VREF,min
φ
V
REF,min-0.2V
VIL,BCLK
α
τ
Clock
V0014-02
Time
Datasheet
37
Intel® Pentium® III Processor – Low Power
Table 23. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
Overshoot Amplitude
Undershoot Amplitude
Allowed Pulse Duration
2.0 V
1.9 V
1.8 V
-0.35 V
-0.25 V
-0.15 V
0.35 ns
1.2 ns
4.3 ns
NOTES:
1. Under no circumstances should the GTL+ signal voltage ever exceed 2.0 V maximum with respect to
ground or -2.0 V minimum with respect to V (i.e., V - 2.0 V) under operating conditions.
CCT
CCT
2. Ringbacks below V
longer or larger overshoot.
cannot be subtracted from overshoots. Lesser undershoot does not allocate
CCT
3. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
longer or larger undershoot.
4. System designers are encouraged to follow Intel provided GTL+ layout guidelines.
5. All values are specified by design characterization and are not tested.
Figure 19. Maximum Acceptable Overshoot/Undershoot Waveform
Time dependent Overshoot
2.0V Max
1.9V
VCCT
1.8V
χ
α
β
α β
χ
Vss
-.15V
-.25V
-.35V Min
Time dependent Undershoot
NOTE:
The total overshoot/undershoot budget for one clock cycle is fully consumed by the α, β, or χ waveforms.
38
Datasheet
Intel® Pentium® III Processor – Low Power
4.3
Non-GTL+ Signal Quality Specifications
Signals driven to the Pentium III Processor – Low Power should meet signal quality specifications
to ensure that the processor reads data properly and that incoming signals do not affect the long-
term reliability of the processor. The Pentium III Processor – Low Power uses GTL+ buffers for
non-GTL+ signals. The input and output paths of the buffers have been slowed down to match the
requirements for the non-GTL+ signals. The signal quality specifications for the non-GTL+ signals
are identical to the GTL+ signal quality specifications except that they are relative to VCMOSREF
rather than VREF transitions OVERSHOOT_CHECKER can be used to verify non-GTL+ signal
compliance with the signal overshoot and undershoot tolerance. The tolerances listed in Table 24
are conservative. Signals that exceed these tolerances may still meet the processor overshoot and
undershoot tolerance if the OVERSHOOT_CHECKER tool says that they pass.
Table 24. Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
Overshoot Amplitude
Undershoot Amplitude
Allowed Pulse Duration
2.1 V
2.0 V
1.9 V
1.8 V
-0.45 V
-0.35 V
-0.25 V
-0.15 V
0.45 ns
1.5 ns
5.0 ns
17 ns
NOTES:
1. Under no circumstances should the non-GTL+ signal voltage ever exceed 2.1 V maximum with respect to
ground or -2.1 V minimum with respect to V (i.e., V - 2.1 V) under operating conditions.
CCT
CCT
2. Ring-backs below V
longer or larger overshoot.
cannot be subtracted from overshoots. Lesser undershoot does not allocate
CCT
3. Ring-backs above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
longer or larger undershoot.
4. System designers are encouraged to follow Intel provided non-GTL+ layout guidelines.
5. All values are specified by design characterization, and are not tested.
4.3.1
PWRGOOD Signal Quality Specifications
The processor requires PWRGOOD to be a clean indication that clocks and the power supplies
(VCC, VCCT, etc.) are stable and within their specifications. Clean implies that the signal will
remain below V
and without errors from the time that the power supplies are turned on, until
IL25
they come within specification. The signal will then transition monotonically to a high (2.5 V)
state. PWRGOOD may not ringback below 2.0 V after rising above V
.
IH25
Datasheet
39
Intel® Pentium® III Processor – Low Power
5.0
Mechanical Specifications
5.1
Surface-mount BGA2 Package Dimensions
The Pentium III Processor – Low Power is packaged in a PBGA-B495 package (also known as
BGA2) with the back of the processor die exposed on top. Unlike previous processors with
exposed die, the back of the Pentium III Processor – Low Power die may be polished and very
smooth. The mechanical specifications for the surface-mount package are provided in Table 25.
Figure 21 shows the top and side views of the surface-mount package, and Figure 22 shows the
bottom view of the surface-mount package. The substrate may only be contacted within the shaded
region between the keep-out outline and the edge of the substrate. The Pentium III Processor – Low
Power will have one or two label marks. These label marks will be located along the long edge of
the substrate outside of the keep-out region and they will not encroach upon the 7-mm by 7-mm
squares at the substrate corners. Please note that in order to implement VID on the BGA2 package,
some VID[4:0] balls may be depopulated.
Table 25. Surface-mount BGA2 Package Specifications
Symbol
Parameter
Min
Max
Unit
A
Overall Height, as delivered
Substrate Height, as delivered
Die Height
2.29
2.79
mm
mm
mm
mm
mm
A
1.50 REF
0.854 REF
0.78 REF
1
2
A
b
Ball Diameter
D
Package Width
27.05
27.35
D0 Step 8.82 REF (CPUID = 068Ah)
C0 Step 8.82 REF (CPUID = 0686h)
B0 Step 9.28 REF (CPUID = 0683h)
A2 Step 9.37 REF (CPUID = 0681h)
D
Die Width
mm
1
E
e
Package Length
Ball Pitch
30.85
31.15
mm
mm
1.27
D0 Step 11.00 REF (CPUID = 068Ah)
C0 Step 10.79 REF (CPUID = 0686h)
B0 Step 11.23 REF (CPUID = 0683h)
A2 Step 11.27 REF (CPUID = 0681h)
E
Die Length
mm
1
N
Ball Count
4951
each
mm
S
Outer Ball Center to Short Edge of Substrate
Outer Ball Center to Long Edge of Substrate
0.895 REF
0.900 REF
1
2
S
mm
Allowable Pressure on the Die for Thermal
Solution
P
—
689
kPa
DIE
W
Package Weight
4.5 REF
grams
Note: 1. Exact ball count will vary depending on VID[4:0] encoding. See VID[4:0] signal description.
40
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 20. Surface-mount BGA2 Package - Top and Side View
D1
E1
NOTE: All dimensions are in millimeters. Dimensions in figure are for reference only, see Table 25 for
specifications.
Datasheet
41
Intel® Pentium® III Processor – Low Power
Figure 21. Surface-mount BGA2 Package - Bottom View
NOTE: All dimensions are in millimeters. Dimensions in figure are for reference only, see Table 25 for
specifications
5.2
Signal Listings
Figure 22 is a top-side view of the ball or pin map of the Pentium III Processor – Low Power with
the voltage balls/pins called out. Table 26 lists the signals in ball/pin number order. Table 27 lists
the signals in signal name order.
42
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 22. Pin/Ball Map - Top View
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18 19 20 21
A
B
C
D
E
F
VSS
A30#
A31#
VSS
A23#
A18#
NC
A29#
A28#
A26#
A21#
VSS
VSS
VSS
NC
A32#
A34#
A20#
A25#
A33# RESET# VSS
VSS
VSS
D3#
NC
D5#
D4#
VSS
VSS
VSS
VSS
NC
VSS
D7#
VSS
D1#
VSS
VSS
VSS
D11#
D8#
D14#
D9#
D10#
D18#
NC
NC
VSS
VSS
D16#
NC
NC
D13#
VSS
NC
NC
D23#
VSS
D21#
D27#
VSS
D30#
D29#
D35#
D37#
D43#
VSS
VSS
D31#
D33#
D38#
D45#
D42#
D51#
D47#
D59#
D53#
D55#
D56#
VSS
VSS
A27#
A22#
A19#
A16#
A13#
A14#
A10#
A9#
VSS
VSS
VSS
VSS
D6#
D0#
VSS
VSS
D22#
D24#
D25#
A35# BREQ0# D2#
D20#
D15#
VSS
VSS
D26#
D28#
A24#
VSS
VSS
D17#
D12#
VSS
NC
D32#
VSS
A15# VREF BERR# VSS
VSS
VSS
D19#
VSS
VREF VREF D34#
A17# VREF
VSS
VSS
VSS
VSS
VREF D40#
D36#
VSS
G
H
J
NC
NC
NC
A8#
VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT
NC
D49#
VSS
NC
NC
VSS
A5#
VCCT
VCCT
VCCT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC VCCT D39#
VSS VCCT D41#
VCC VCCT D52#
VSS VCCT D48#
VCC VCCT D54#
D44#
VSS
A11#
A4#
VSS
A12#
A6#
NC
D46#
VSS
K
L
VSS
PLL1
D57#
VSS
A7#
A3#
VSS VCCT
D60#
VSS
M
N
P
R
T
DEFER# PLL2 BCLK
NC
VCCT
D61#
VSS
VSS
VSS
VSS
VSS TESTLO2 VCCT
VSS VCCT
VSS
VSS
VCC CLKREF NC
NC
VSS
VSS
VSS
VCCT
VCCT
VCCT
VCC VCCT D50#
VSS VCCT D63#
VSS DEP6# DEP5#
LOCK# GHI#
VSS
VSS
D56#
VSS
VSS DEP3#
D58# DEP1#
DRDY# REQ0# VSS
BNR#
VCC VCCT
VSS
U
V
W
Y
A
B
C
D
RS0# TRDY# DEFER# BPRI# VREF VCCT
VSS VCCT D62# DEP7# VSS DEP2#
HIT# REQ2# VSS REQ1# PWRGOOD VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT DEP4# VSS DEP0# BINIT#
RS2#
RP# REQ3# VSS REQ4# VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT
VSS BPM1# PRDY# BPM0#
RSP# AP1#
VSS HITM#TESTLO1 VCCT VCCT VCCT
VSS
VSS
INIT#
SMI#
VSS
VSS
VSS
VSS
VSS
VSS
VREF VREF
VSS
PICD1 BP3#
CMOS
REF
THERM EDGE
DA
NC
VSS
NC
AERR# RS1# DBSY# VSS
NC
VCCT VCCT VCCT
VCCT VCCT VCCT
TCK BSEL0 VSS TRST#
PICCLK NC
VSS
BP2#
CTRLP
THERM
DC
AP0# ADS#
VSS
NC
VID4
VID3
VSS
VSS
VSS
VSS
VSS
SLP#
VSS
VSS BSEL1
INTR RSVD PREQ# PICD0
VSS
VSS
VSS
VCCT VCCT VCCT FLUSH# VSS STPCLK# FERR# IGNNE# VSS
TDO
NC
VSS
VSS
NMI
NC
NC
VSS
VSS
CMOS RTT
VSS TESTHI
REF IMPEDP
VID0
VID1 VID2
VCCT VCCT VCCT IERR# A20M# NC
NC
TDI
TMS
V0024-03
VCC
VCCT VSS
Other
Analog
Decoupling
NOTES:
1. In order to implement VID on the BGA2 package, some VID[4:0] balls may be depopulated.
2. Ball P1 must be connected to Vcc
Datasheet
43
Intel® Pentium® III Processor – Low Power
Table 26. Signal Listing in Order by Pin/Ball Number (Sheet 1 of 3)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
A2
A3
VSS
A29#
A32#
A33#
RESET#
VSS
VSS
D5#
C3
C4
A26#
A20#
A35#
BREQ0#
D2#
E2
E3
A23#
VSS
G1
G2
A13#
NC
A4
C5
E4
A15#
VREF
BERR#
VSS
G3
VSS
A5
C6
E5
G4
NC
A6
C7
E6
G5
NC
A7
C8
D3#
E7
G6
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
NC
A8
C9
VSS
D6#
E8
VSS
G7
A9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
D1
E9
VSS
G8
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
B1
VSS
D14#
D10#
NC
VSS
D8#
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
F1
VSS
G9
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
H1
D20#
NC
D12#
VSS
NC
VSS
VSS
D24#
D26#
VSS
D35#
D33#
A22#
VSS
A21#
A25#
A24#
VSS
VSS
NC
D19#
NC
NC
D23#
D21#
D30#
VSS
VSS
A30#
A28#
A34#
VSS
VSS
VSS
VSS
D4#
VREF
VREF
D34#
VSS
D43#
D45#
A16#
A18#
VSS
VSS
B2
D49#
D51#
A14#
VSS
B3
D2
B4
D3
F2
B5
D4
F3
H2
B6
D5
F4
A17#
VREF
VSS
H3
NC
B7
D6
F5
H4
NC
B8
D7
F6
H5
NC
B9
D8
F7
VSS
H6
VCCT
VSS
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
C1
VSS
D7#
D9
VSS
D0#
F8
VSS
H7
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
E1
F9
VSS
H8
VCC
VSS
D11#
D9#
D1#
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
VSS
H9
D17#
D15#
NC
VSS
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
VCC
VSS
D18#
VSS
D13#
D22#
VSS
D27#
D29#
D31#
A27#
A31#
VSS
VSS
VCC
VSS
D16#
NC
VSS
VSS
VCC
VSS
D25#
D28#
D32#
D37#
D38#
A19#
VSS
VREF
D40#
D36#
VSS
VCC
VCCT
D39#
D44#
VSS
C2
D42#
44
Datasheet
Intel® Pentium® III Processor – Low Power
Table 26. Signal Listing in Order by Pin/Ball Number (Sheet 2 of 3)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
H21
J1
D47#
A10#
A5#
K20
K21
L1
VSS
D53#
A7#
M20
N2
VSS
VSS
R1
R2
LOCK#
NC
J2
N3
VSS
R3
VSS
J3
A11#
VSS
NC
L2
PLL1
A3#
N4
VSS
R4
VSS
J4
L3
N5
TESTLO2
VCCT
VCC
VSS
R5
VSS
J5
L4
A6#
N6
R6
VCCT
VCC
VSS
J6
VCCT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
D41#
VSS
D46#
D59#
A9#
L5
VSS
VCCT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
D48#
VSS
D60#
D55#
PLL2
BCLK
NC
N7
R7
J7
L6
N8
R8
J8
L7
N9
VCC
VSS
R9
VCC
VSS
J9
L8
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
P1
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
T1
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
K1
L9
VCC
VSS
VCC
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
M2
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
VSS
VCCT
D63#
D56#
VSS
VSS
VSS
VCC
CLKREF
NC
DEP3#
DRDY#
REQ0#
VSS
P2
P3
T2
K2
VSS
A4#
P4
NC
T3
K3
M3
P5
VSS
T4
BNR#
VSS
K4
A12#
A8#
M4
P6
VCCT
VSS
T5
K5
M5
NC
P7
T6
VCCT
VSS
K6
VCCT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCCT
D52#
D57#
M6
VCCT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCCT
D54#
D61#
P8
VCC
VSS
T7
K7
M7
P9
T8
VCC
VSS
K8
M8
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
VCC
VSS
T9
K9
M9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
VCC
VSS
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCCT
D50#
VSS
VCC
VCCT
VSS
DEP6#
DEP5#
VSS
D58#
Datasheet
45
Intel® Pentium® III Processor – Low Power
Table 26. Signal Listing in Order by Pin/Ball Number (Sheet 3 of 3)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
T21
U1
DEP1#
RS0#
TRDY#
DEFER#
BPRI#
VREF
VCCT
VCC
V20
V21
W1
DEP0#
BINIT#
RS2#
RP#
Y19
Y20
VSS
PICD1
BP3#
AB18
AB19
AB20
AB21
AC1
INTR/LINT0
RSVD
PREQ#
PICD0
VSS
U2
Y21
U3
W2
AA1
AERR#
RS1#
DBSY#
VSS
U4
W3
REQ3#
VSS
AA2
U5
W4
AA3
AC2
VSS
U6
W5
REQ4#
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VSS
AA4
AC3
NC
U7
W6
AA5
NC
AC4
VID3
U8
VSS
W7
AA6
VCCT
VCCT
VCCT
CMOSREF
INIT#
AC5
VSS
U9
VCC
W8
AA7
AC6
VCCT
VCCT
VCCT
FLUSH#
VSS
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
V1
VSS
W9
AA8
AC7
VCC
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
Y1
AA9
AC8
VSS
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AB1
AC9
VCC
TCK
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AD1
VSS
BSEL0
VSS
STPCLK#
FERR#
IGNNE#
VSS
VCC
VSS
TRST#
THERMDA
EDGECTRLP
NC
VCCT
D62#
TDO
DEP7#
VSS
VSS
BPM1#
PRDY#
BPM0#
RSP#
AP1#
VSS
PICCLK
NC
NC
DEP2#
HIT#
VSS
VSS
NMI/LINT1
NC
V2
REQ2#
VSS
BP2#
V3
Y2
AP0#
VSS
V4
REQ1#
PWRGOOD
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
DEP4#
VSS
Y3
AB2
ADS#
VSS
VSS
V5
Y4
HITM#
TESTLO1
VCCT
VCCT
VCCT
VSS
AB3
AD2
VID0
V6
Y5
AB4
VID4
AD3
VID1
V7
Y6
AB5
VSS
AD4
VID2
V8
Y7
AB6
VCCT
VCCT
VCCT
VSS
AD5
VSS
V9
Y8
AB7
AD6
VCCT
VCCT
VCCT
IERR#
A20M#
TDI
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
Y9
AB8
AD7
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
VSS
AB9
AD8
VSS
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
SMI#
AD9
VSS
VSS
AD10
AD13
AD14
AD15
AD16
AD17
AD18
VSS
SLP#
VSS
VSS
TMS
VSS
VSS
NC
VSS
BSEL1
THERMDC
VSS
VSS
VREF
VREF
TESTHI
CMOSREF
AD19
RTTIMPEDP
AD20
NC
AD21
VSS
NOTE: Ball P1 must be connected to Vcc.
46
Datasheet
Intel® Pentium® III Processor – Low Power
Table 27. Signal Listing in Order by Signal Name (Sheet 1 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
L3
K3
J2
A3#
A4#
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
1.5V CMOS Input
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
2.5V Clock Input
GTL+ I/O
GTL+ I/O
T4
AA21
Y21
W21
W19
U4
BNR#
BP2#
BP3#
BPM0#
BPM1#
BPRI#
BREQ0#
BSEL0
BSEL1
CLKREF
CMOSREF
CMOSREF
D0#
GTL+ I/O
GTL+ I/O
A5#
GTL+ I/O
L4
A6#
GTL+ I/O
L1
A7#
GTL+ I/O
K5
K1
J1
A8#
GTL+ Input
GTL+ I/O
A9#
C6
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
A20M#
ADS#
AERR#
AP0#
AP1#
BCLK
BERR#
BINIT#
AA12
AB15
P2
3.3V CMOS Input
3.3V CMOS Input
BCLK Reference Voltage
CMOS Reference Voltage
CMOS Reference Voltage
GTL+ I/O
J3
K4
G1
H1
E4
F1
AA9
AD18
D10
D11
C7
D1#
GTL+ I/O
F4
D2#
GTL+ I/O
F2
C8
D3#
GTL+ I/O
E1
C4
D3
D1
E2
D5
D4
C3
C1
B3
A3
B2
C2
A4
A5
B4
C5
AD10
AB2
AA1
AB1
Y2
M3
E6
V21
B9
D4#
GTL+ I/O
A9
D5#
GTL+ I/O
C10
B11
C12
B13
A14
B12
E12
B16
A13
D13
D15
D12
B14
E14
C13
A19
B17
A18
C17
D17
C18
B19
D18
D6#
GTL+ I/O
D7#
GTL+ I/O
D8#
GTL+ I/O
D9#
GTL+ I/O
D10#
D11#
GTL+ I/O
GTL+ I/O
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
Datasheet
47
Intel® Pentium® III Processor – Low Power
Table 27. Signal Listing in Order by Signal Name (Sheet 2 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
B20
A20
B21
D19
C21
E18
C20
F19
D20
D21
H18
F18
J18
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBSY#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ Input
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
V18
P21
P20
U19
T1
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
EDGECTRLP
FERR#
FLUSH#
HIT#
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
GTL+ I/O
AA16
AC12
AC9
V1
GTL+ Control
1.5V Open Drain Output
1.5V CMOS Input
GTL+ I/O
Y4
HITM#
GTL+ I/O
AD9
AC13
AA10
AB18
R1
IERR#
1.5V Open Drain Output
1.5V CMOS Input
1.5V CMOS Input
1.5V CMOS Input
GTL+ I/O
IGNNE#
INIT#
F21
E20
H19
E21
J20
INTR/LINT0
LOCK#
NMI/LINT1
PICCLK
PICD0
AC19
AA18
AB21
Y20
L2
1.5V CMOS Input
2.5V APIC Clock Input
1.5V Open Drain I/O
1.5V Open Drain I/O
PLL Analog Voltage
PLL Analog Voltage
GTL+ Output
H21
L18
G20
P18
G21
K18
K21
M18
L21
R19
K19
T20
J21
PICD1
PLL1
M2
PLL2
W20
AB20
V5
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RS0#
1.5V CMOS Input
2.5V CMOS Input
GTL+ I/O
T2
V4
GTL+ I/O
V2
GTL+ I/O
W3
GTL+ I/O
W5
GTL+ I/O
U1
GTL+ Input
A6
RESET#
RP#
GTL+ Input
L20
M19
U18
R18
AA3
U3
W2
GTL+ I/O
AA2
W1
RS1#
GTL+ Input
RS2#
GTL+ Input
Y1
RSP#
GTL+ Input
AB19
AD19
AB12
AB10
AC11
RSVD
Reserved
RTTIMPEDP
SLP#
GTL+ Pull-up Control
1.5V CMOS Input
1.5V CMOS Input
1.5V CMOS Input
V20
T21
U21
R21
SMI#
STPCLK#
48
Datasheet
Intel® Pentium® III Processor – Low Power
Table 27. Signal Listing in Order by Signal Name (Sheet 3 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
AA11
AD13
AC15
AD17
Y5
TCK
TDI
1.5V JTAG Clock Input AA14
TRST#
VID0
VID1
VID2
VID3
VID4
JTAG Input
JTAG Input
JTAG Output
Test Input
AD2
AD3
AD4
AC4
AB4
Voltage Identification
Voltage Identification
Voltage Identification
Voltage Identification
Voltage Identification
TDO
TESTHI
TESTLO1
TESTLO2
Test Input
N5
Test Input
Core Voltage Test
Point
AD20
H4
NC
NC
NC
E5
VREF
VREF
VREF
GTL+ Reference Voltage
GTL+ Reference Voltage
GTL+ Reference Voltage
Core Voltage Test
Point
E16
E17
Core Voltage Test
Point
AA17
Core Voltage Test
Point
G4
NC
F5
F17
U5
VREF
VREF
VREF
GTL+ Reference Voltage
GTL+ Reference Voltage
GTL+ Reference Voltage
AA15
AB16
THERMDA
THERMDC
Thermal Diode Anode
Thermal Diode
Cathode
AD14
U2
TMS
JTAG Input
GTL+ Input
Y17
Y18
VREF
VREF
GTL+ Reference Voltage
GTL+ Reference Voltage
TRDY#
Table 28. Voltage and No-Connect Pin/Ball Locations
Signal
Name
Pin/Ball Numbers
A15, A16, A17, C14, D8, D14, D16, E15, G2, G4, G5, G18, H3, H4, H5, J5, M4, M5, P3, P4, R2,
AA5, AA17, AA19, AC3, AC17, AC20, AD15, AD20
NC
H8, H10, H12, H14, H16, J7, J9, J11, J13, J15, K8, K10, K12, K14, K16, L7, L9, L11, L13, L15, M8,
M10, M12, M14, M16, N7, N9, N11, N13, N15, P1, P8, P10, P12, P14, P16, R7, R9, R11, R13,
R15, T8, T10, T12, T14, T16, U7, U9, U11, U13, U15
VCC
G6, G7, G8, G9, G10, G11, G12, G13, G14, G15, G16, G17, H6, H17, J6, J17, K6, K17, L6, L17,
M6, M17, N6, N17, P6, P17, R6, R17, T6, T17, U6, U17, V6, V7, V8, V9, V10, V11, V12, V13, V14,
V15, V16, V17, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, W16, W17, Y6, Y7, Y8, AA6,
AA7, AA8, AB6, AB7, AB8, AC6, AC7, AC8, AD6, AD7, AD8
VCCT
A2, A7, A8, A12, A21, B1, B5, B6, B7, B8, B10, B15, B18, C9, C11, C15, C16, C19, D2, D6, D7,
D9, E3, E7, E8, E9, E10, E11, E13, E19, F3, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16,
F20, G3, G19, H2, H7, H9, H11, H13, H15, H20, J4, J8, J10, J12, J14, J16, J19, K2, K7, K9, K11,
K13, K15, K20, L5, L8, L10, L12, L14, L16, L19, M7, M9, M11, M13, M15, M20, N2, N3, N4, N8,
N10, N12, N14, N16, N18, N19, N20, P5, P7, P9, P11, P13, P15, P19, R3, R4, R5, R8, R10, R12,
R14, R16, R20, T3, T5, T7, T9, T11, T13, T15, T18, T19, U8, U10, U12, U14, U16, U20, V3, V19,
W4, W18, Y3, Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16, Y19, AA4, AA13, AA20, AB3, AB5, AB9,
AB11, AB13, AB14, AB17, AC1, AC2, AC5, AC10, AC14, AC16, AC18, AC21, AD1, AD5, AD16,
AD21
VSS
NOTE: Pin/ball P1 must be connected to Vcc:
Datasheet
49
Intel® Pentium® III Processor – Low Power
6.0
Thermal Specifications
This section provides needed data for designing a thermal solution. The Pentium III Processor –
Low Power is a surface mount PBGA-B495 package with the back of the processor die exposed
and has a specified operational junction temperature (TJ) limit.
In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat
pipe, or other heat transfer system) must make firm contact to the exposed processor die. The
processor die must be clean before the thermal solution is attached or the processor may be
damaged.
Table 29 provides the maximum Thermal Design Power (TDPMAX) dissipation and the minimum
and maximum TJ temperatures for the Pentium III Processor – Low Power. A thermal solution
should be designed to ensure the junction temperature never exceeds these specifications. If no
closed loop thermal fail-safe mechanism (processor throttling) is present to maintain TJ within
specification then the thermal solution should be designed to cool the TDPMAX condition. If a
thermal fail-safe mechanism is present then thermal solution could possibly be designed to a
typical Thermal Design Power (TDPTYP). TDPTYP is a thermal design power recommendation
based on the power dissipation of the processor while executing publicly available software under
normal operating conditions at nominal voltages. TDPTYP power is lower than TDPMAX. Contact
your Intel Field Sales Representative for further information.
Table 29. Power Specifications for the Pentium III Processor – Low Power
1
Symbol
Parameter
Min
TDP
Max
Unit
Notes
TYP
Thermal Design Power
at 1.35 V (for 700 MHz)
at 1.35 V (for 500 MHz)
at 1.35 V (for 400 MHz)
10.2
7.9
6.5
16.1
12.2
10.1
at 100°C
Notes 2, 3
TDP
W
Stop Grant and Auto Halt power
at 1.35 V (for 700 MHz)
at 1.35 V (for 500 MHz)
at 1.35 V (for 400 MHz)
1.6
1.1
1.1
W
W
W
at 50°C
Note 3
P
SGNT
Quick Start and Sleep power
at 1.35 V (for 700 MHz)
at 1.35 V (for 500 MHz)
at 1.35 V (for 400 MHz)
1.2
800
650
W
mW
mW
at 50°C
Note 3
P
QS
Deep Sleep power
0.4
300
150
W
mW
mW
at 1.35 V (for 700 MHz)
at 1.35 V (for 500 MHz)
at 1.35 V (for 400 MHz)
at 35°C
Note 3
P
DSLP
T
Junction Temperature
0
100
°C
Note 4
J
NOTES:
1. TDP
is a recommendation based on the power dissipation of the processor while executing publicly
TYP
available software under normal operating conditions at nominal voltages. Contact your Intel Field Sales
Representative for further information. Not 100% tested.
2. TDP
is a specification of the total power dissipation of the processor while executing a worst-case
MAX
instruction mix under normal operating conditions at nominal voltages. It includes the power dissipated by
all of the components within the processor. Not 100% tested. Specified by design/characterization.
3. Not 100% tested or guaranteed. The power specifications are composed of the current of the processor on
the various voltage planes. These currents are measured and specified at high temperature in Table 7.
These power specifications are determined by characterization of the processor currents at higher
temperatures.
4. T is measured with the on-die thermal diode.
J
50
Datasheet
Intel® Pentium® III Processor – Low Power
6.1
Thermal Diode
The Pentium III Processor – Low Power has an on-die thermal diode that can be used to monitor the
die temperature (TJ). A thermal sensor located on the motherboard, or a stand-alone measurement
kit, may monitor the die temperature of the processor for thermal management or instrumentation
purposes. Table 30 and Table 31 provide the diode interface and specifications.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect
the temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor,
on-die temperature gradients between the location of the thermal diode and the hottest location on
the die, and time based variations in the die temperature measurement. Time based variations can
occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at
which the TJ temperature can change.
Table 30. Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
THERMDC
AA15
AB16
Thermal diode anode
Thermal diode cathode
Table 31. Thermal Diode Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
I
Forward Bias Current
Diode Ideality Factor
5
500
µA
Note 1
FW
n
1.0057
1.0080
1.0125
Notes 2, 3, 4
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not
support or recommend operation of the thermal diode when the processor power supplies are not within
their specified tolerance range.
2. Characterized at 100° C.
3. Not 100% tested. Specified by design/characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
qV
D
nkT
I
= I
e
– 1
FW
S
Where I = saturation current, q = electronic charge, V = voltage across the diode, k = Boltzmann
s
D
Constant, and T = absolute temperature (Kelvin).
Datasheet
51
Intel® Pentium® III Processor – Low Power
7.0
Processor Initialization and Configuration
7.1
Description
The Pentium III Processor – Low Power has some configuration options that are determined by
hardware and some that are determined by software. The processor samples its hardware
configuration at reset on the active-to-inactive transition of RESET#. Most of the configuration
options for the Pentium III Processor – Low Power are identical to those of the Pentium II
processor. The Pentium® II Processor Developer’s Manual describes these configuration options.
New configuration options for the Pentium III Processor – Low Power are described in the
remainder of this section.
7.1.1
Quick Start Enable
The processor normally enters the Stop Grant state when the STPCLK# signal is asserted but it will
enter the Quick Start state instead if A15# is sampled active on the RESET# signal’s active-to-
inactive transition. The Quick Start state supports snoops from the bus priority device like the Stop
Grant state but it does not support symmetric master snoops nor is the latching of interrupts
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick
Start state has been enabled.
7.1.2
7.1.3
System Bus Frequency
The current generation Pentium III Processor – Low Power will only function with a system bus
frequency of 100 MHz. Bit positions 18 to 19 of the Power-on Configuration register indicates at
which speed a processor will run. A “00” in bits [19:18] indicates a 66-MHz bus frequency, a “10”
indicates a 100-MHz bus frequency, and a “01” indicates a 133-MHz bus frequency.
APIC Enable
If the PICD0 signal is sampled low on the active-to-inactive transition of the RESET# signal then
the PICCLK signal can be tied to VSS. Otherwise the PICD[1:0] signals must be pulled up to VCCT
and PICCLK must be supplied. Driving PICD0 low at reset also has the effect of clearing the APIC
Global Enable bit in the APIC Base MSR. This bit is normally set when the processor is reset, but
when it is cleared the APIC is completely disabled until the next reset.
7.2
Clock Frequencies and Ratios
The Pentium III Processor – Low Power uses a clock design in which the bus clock is multiplied by
a ratio to produce the processor’s internal (or “core”) clock. Unlike some of the Pentium III
Processor – Low Power, the ratio used is programmed into the processor during manufacturing.
The bus ratio programmed into the processor is visible in bit positions 22 to 25 and bit 27 of the
Power-on Configuration register. Table 12 shows the 5-bit codes in the Power-on Configuration
register and their corresponding bus ratios.
52
Datasheet
Intel® Pentium® III Processor – Low Power
8.0
Processor Interface
8.1
Alphabetical Signal Reference
8.1.1
A[35:3]# (I/O - GTL+)
The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is
active, these signals transmit the address of a transaction; when ADS# is inactive, these signals
transmit transaction information. These signals must be connected to the appropriate pins/balls of
both agents on the system bus. The A[35:24]# signals are protected with the AP1# parity signal,
and the A[23:3]# signals are protected with the AP0# parity signal.
On the active-to-inactive transition of RESET#, each processor bus agent samples A[35:3]# signals
to determine its power-on configuration. See Section 4.0 of this document and the Pentium® II
Processor Developer’s Manual for details.
8.1.2
8.1.3
A20M# (I - 1.5 V Tolerant)
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction
on the bus. Asserting A20M# emulates the 8086 processor’s address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in Real mode.
ADS# (I/O - GTL+)
The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on
the A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop or deferred reply ID match operations associated
with the new transaction. This signal must be connected to the appropriate pins/balls on both agents
on the system bus.
8.1.4
AERR# (I/O - GTL+)
The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and if
used, must be connected to the appropriate pins/balls of both agents on the system bus. AERR#
observation is optionally enabled during power-on configuration; if enabled, a valid assertion of
AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an
assertion of AERR# as appropriate to the error handling architecture of the system.
8.1.5
AP[1:0]# (I/O - GTL+)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity
signal is high if an even number of covered signals are low and low if an odd number of covered
Datasheet
53
Intel® Pentium® III Processor – Low Power
signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]#
should be connected to the appropriate pins/balls on both agents on the system bus.
8.1.6
8.1.7
BCLK (I - 2.5 V Tolerant)
The BCLK (Bus Clock) signal determines the system bus frequency. Both system bus agents must
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All
external timing parameters are specified with respect to the BCLK signal.
BERR# (I/O - GTL+)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol
violation. It may be driven by either system bus agent and must be connected to the appropriate
pins/balls of both agents, if used. However, the Pentium III Processor – Low Power do not observe
assertions of the BERR# signal.
BERR# assertion conditions are defined by the system configuration. Configuration options enable
the BERR# driver as follows:
• Enabled or disabled
• Asserted optionally for internal errors along with IERR#
• Asserted optionally by the request initiator of a bus transaction after it observes an error
• Asserted by any bus agent when it observes an error in a bus transaction
8.1.8
BINIT# (I/O - GTL+)
The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and
must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches
are not affected.
If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of
BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
8.1.9
BNR# (I/O - GTL+)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
54
Datasheet
Intel® Pentium® III Processor – Low Power
8.1.10
8.1.11
BP[3:2]# (I/O - GTL+)
The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are
outputs from the processor that indicate the status of breakpoints.
BPM[1:0]# (I/O - GTL+)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
8.1.12
8.1.13
BPRI# (I - GTL+)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It
must be connected to the appropriate pins/balls on both agents on the system bus. Observing
BPRI# active (as asserted by the priority agent) causes the processor to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed and then releases the bus by deasserting BPRI#.
BREQ0# (I/O - GTL+)
The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates
that it wants ownership of the system bus by asserting the BREQ0# signal.
During power-up configuration, the central agent must assert the BREQ0# bus signal. The
processor samples BREQ0# on the active-to-inactive transition of RESET#. Optionally, this signal
may be grounded with a 10ohm resistor.
8.1.14
BSEL[1:0] (I – 3.3 V Tolerant)
The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for
the system bus frequency. Table 32 shows the encoding scheme for BSEL[1:0]. The only supported
system bus frequency for the Pentium III Processor – Low Power is 100 MHz. If another frequency
is used or if the BSEL[1:0] signals are not driven with “01” then the processor is not guaranteed to
function properly.
Table 32. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
00
01
10
11
66 MHz
100 MHz
Reserved
133 MHz
8.1.15
CLKREF (Analog)
The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip
point for the BCLK signal. This signal should be connected to a resistor divider to generate 1.25 V
from the 2.5-V supply.
Datasheet
55
Intel® Pentium® III Processor – Low Power
8.1.16
CMOSREF (Analog)
The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the
CMOS input buffers. A voltage divider should be used to divide a stable voltage plane (e.g., 2.5 V
or 3.3 V). This signal must be provided with a DC voltage that meets the VCMOSREF specification
from Table 10.
8.1.17
8.1.18
D[63:0]# (I/O - GTL+)
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between
both system bus agents, and must be connected to the appropriate pins/balls on both agents. The
data driver asserts DRDY# to indicate a valid data transfer.
DBSY# (I/O - GTL+)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must be connected to the appropriate pins/balls on both agents on the
system bus.
8.1.19
8.1.20
8.1.21
8.1.22
DEFER# (I - GTL+)
The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the
addressed memory agent or I/O agent. This signal must be connected to the appropriate pins/balls
on both agents on the system bus.
DEP[7:0]# (I/O - GTL+)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data
bus. They are driven by the agent responsible for driving D[63:0]#, and must be connected to the
appropriate pins/balls on both agents on the system bus if they are used. During power-on
configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.
DRDY# (I/O - GTL+)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle
clocks. This signal must be connected to the appropriate pins/balls on both agents on the system
bus.
EDGCTRLP (Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the GTL+ output
buffers. Connect the signal to VSS with a 110-Ω, 1% resistor.
56
Datasheet
Intel® Pentium® III Processor – Low Power
8.1.23
8.1.24
FERR# (O - 1.5 V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it is
included for compatibility with systems using DOS-type floating-point error reporting.
FLUSH# (I - 1.5 V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache
lines in the Modified state and invalidates all internal cache lines. At the completion of a flush
operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any
new data while the FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
8.1.25
GHI# (I - 1.5 V Tolerant)
Note: This is a No Connect on the Pentium III Processor – Low Power.
The GHI# signal controls which operating mode bus ratio is selected in a mobile Pentium III
Processor featuring Intel SpeedStep™ technology. On the processor featuring Intel SpeedStep
technology, this signal is latched when BCLK restarts in Deep Sleep state and determines which of
two bus ratios is selected for operation. This signal is ignored when the processor is not in the Deep
Sleep state. This signal is a “Don’t Care” (No Connect) on processors that do not feature Intel
SpeedStep technology. This signal has an on-die pull-up to VCCT and should be driven with an
open-drain driver with no external pull-up.
8.1.26
8.1.27
HIT# (I/O - GTL+), HITM# (I/O - GTL+)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation
results, and must be connected to the appropriate pins/balls on both agents on the system bus.
Either bus agent can assert both HIT# and HITM# together to indicate that it requires a snoop stall,
which can be continued by reasserting HIT# and HITM# together.
IERR# (O - 1.5 V Tolerant Open-drain)
The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This
transaction may optionally be converted to an external error signal (e.g., NMI) by system logic.
The processor will keep IERR# asserted until it is handled in software or with the assertion of
RESET#, BINIT, or INIT#.
8.1.28
IGNNE# (I - 1.5 V Tolerant)
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric
error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the
processor freezes on a non-control floating-point instruction if a previous instruction caused an
error. IGNNE# has no affect when the NE bit in control register 0 (CR0) is set.
Datasheet
57
Intel® Pentium® III Processor – Low Power
8.1.29
INIT# (I - 1.5 V Tolerant)
The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without
affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins
execution at the power-on reset vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous input.
If INIT# is sampled active on RESET#’s active-to-inactive transition, then the processor executes
its built-in self test (BIST).
8.1.30
8.1.31
INTR (I - 1.5 V Tolerant)
The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes
the LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the
EFLAGS register. If the IF bit is set, the processor vectors to the interrupt handler after completing
the current instruction execution. Upon recognizing the interrupt request, the processor issues a
single Interrupt Acknowledge (INTA) bus transaction. INTR must remain active until the INTA
bus transaction to guarantee its recognition.
LINT[1:0] (I - 1.5 V Tolerant)
The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of
all APIC bus agents, including the processor and the system logic or I/O APIC component. When
APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the
same signals for the Pentium processor. Both signals are asynchronous inputs.
Both of these signals must be software configured by programming the APIC register space to be
used either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then
LINT[1:0] is the default configuration.
8.1.32
LOCK# (I/O - GTL+)
The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur
atomically. This signal must be connected to the appropriate pins/balls on both agents on the
system bus. For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction through the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes
LOCK# deasserted. This enables the processor to retain bus ownership throughout the bus locked
operation and guarantee the atomicity of lock.
8.1.33
NMI (I - 1.5 V Tolerant)
The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of 2. An external interrupt-acknowledge transaction is not
generated. If NMI is asserted during the execution of an NMI service routine, it remains pending
and is recognized after the IRET is executed by the NMI service routine. At most, one assertion of
NMI is held pending. NMI is rising edge sensitive.
58
Datasheet
Intel® Pentium® III Processor – Low Power
8.1.34
8.1.35
PICCLK (I - 2.5 V Tolerant)
The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC
that is required for operation of the processor, system logic, and I/O APIC components on the
APIC bus.
PICD[1:0] (I/O - 1.5 V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the APIC
bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the
processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on the
active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled.
8.1.36
8.1.37
8.1.38
8.1.39
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL.
See Section 3.2.2 for a description of the analog decoupling circuit.
PRDY# (O - GTL+)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5 V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processor.
PWRGOOD (I - 2.5 V Tolerant)
PWRGOOD (Power Good) is a 2.5-V tolerant input. The processor requires this signal to be a
clean indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current)
and without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (2.5 V) state. Figure 23
illustrates the relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before the rising edge of
PWRGOOD. It must also meet the minimum pulse width specified in Table 14 on page 27 and be
followed by a 1 ms RESET# pulse.
Datasheet
59
Intel® Pentium® III Processor – Low Power
Figure 23. PWRGOOD Relationship at Power On
BCLK
VCC
VCCT
,
,
VREF
VIH25,min
PWRGOOD
1 msec
RESET#
D0026-01
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout
boundary scan operation.
8.1.40
8.1.41
REQ[4:0]# (I/O - GTL+)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on
both agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]#
to define the currently active transaction type.
RESET# (I - GTL+)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must
stay active for at least 1 ms after VCC and BCLK have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus
agents will deassert their outputs within two clocks. RESET# is the only GTL+ signal that does not
have on-die GTL+ termination. A 56.2Ω 1% terminating resistor connected to V
is required.
CCT
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-
on configuration. The configuration options are described in Section 4.0 and in the Pentium® II
Processor Developer’s Manual.
Unless its outputs are three-stated during power-on configuration, after an active-to-inactive
transition of RESET#, the processor optionally executes its built-in self-test (BIST) and begins
program execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the
appropriate pins/balls on both agents on the system bus.
8.1.42
RP# (I/O - GTL+)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the
system bus.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
60
Datasheet
Intel® Pentium® III Processor – Low Power
8.1.43
8.1.44
RS[2:0]# (I - GTL+)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - GTL+)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent guaranteeing correct parity.
8.1.45
8.1.46
8.1.47
RSVD (TBD)
The RSVD (Reserved) signal is currently unimplemented but is reserved for future use. Leave this
signal unconnected. Intel recommends that a routing channel for this signal be allocated.
RTTIMPEDP (Analog)
The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die GTL+
termination. Connect the RTTIMPEDP signal to VSS with a 56.2-Ω, 1% resistor.
SLP# (I - 1.5 V Tolerant)
The SLP# (Sleep) signal, when asserted in the Stop Grant state, causes the processor to enter the
Sleep state. During the Sleep state, the processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still running. The processor will not recognize snoop
and interrupts in the Sleep state. The processor will only recognize changes in the SLP#, STPCLK#
and RESET# signals while in the Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to the Stop Grant state in which it restarts its internal clock to the bus and APIC
processor units.
8.1.48
8.1.49
SMI# (I - 1.5 V Tolerant)
The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, the processor saves the current state and enters System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.
STPCLK# (I - 1.5 V Tolerant)
The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Stop
Grant state. The processor issues a Stop Grant Acknowledge special transaction and stops
providing internal clock signals to all units except the bus and APIC units. The processor continues
Datasheet
61
Intel® Pentium® III Processor – Low Power
to snoop bus transactions and service interrupts while in the Stop Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion
of STPCLK# has no affect on the bus clock.
8.1.50
8.1.51
8.1.52
8.1.53
8.1.54
8.1.55
TCK (I - 1.5 V Tolerant)
The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access
port).
TDI (I - 1.5 V Tolerant)
The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial
input needed for JTAG support.
TDO (O - 1.5 V Tolerant Open-drain)
The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the
serial output needed for JTAG support.
TESTHI (I - 1.5 V Tolerant)
The TESTHI (Test input High) is used during processor test and needs to be pulled high during
normal operation.
TESTLO[2:1] (I - 1.5 V Tolerant)
The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to
ground during normal operation.
THERMDA, THERMDC (Analog)
The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals
connect to the anode and cathode of the on-die thermal diode.
8.1.56
8.1.57
TMS (I - 1.5 V Tolerant)
The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.
TRDY# (I - GTL+)
The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to
receive write or implicit write-back data transfer. TRDY# must be connected to the appropriate
pins/balls on both agents on the system bus.
62
Datasheet
Intel® Pentium® III Processor – Low Power
8.1.58
8.1.59
TRST# (I - 1.5 V Tolerant)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The Pentium III Processor
– Low Power do not self-reset during power on; therefore, it is necessary to drive this signal low
during power-on reset.
VID[4:0] (O – Open-drain)
The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply
voltages. These pins/balls are not signals, they are either an open circuit or a short to VSS on the
processor substrate. The combination of opens and shorts encodes the voltage required by the
processor. External to pull-ups are required to sense the encoded VID. For processors that have
Intel SpeedStep technology enabled, VID[4:0] encode the voltage required in the battery-optimized
mode. VID[4:0] are needed to cleanly support voltage specification changes on Pentium III
Processor – Low Power. The voltage encoded by VID[4:0] is defined in Table 33. A “1” in this
table refers to an open pin/ball and a “0” refers to a short to VSS. The power supply must provide
the requested voltage or disable itself.
Please note that in order to implement VID on the BGA2 package, some VID[4:0] balls may be
depopulated. For the BGA2 package, a “1” in Table 33 implies that the corresponding VID ball is
depopulated, while a “0” implies that the corresponding VID ball is not depopulated.
Table 33. Voltage Identification Encoding
VID[4:0]
V
VID[4:0]
V
VID[4:0]
V
VID[4:0]
V
CC
CC
CC
CC
00000
00001
00010
00011
00100
00101
00110
00111
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
01000
01001
01010
01011
01100
01101
01110
01111
1.60
1.55
10000
10001
10010
10011
10100
10101
10110
10111
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
11000
11001
11010
11011
11100
11101
11110
11111
1.075
1.050
1.025
1.000
0.975
0.950
0.925
No CPU
1.50
1.45
1.40
1.35
1.30
No CPU
8.1.60
VREF (Analog)
The VREF (GTL+ Reference Voltage) signal provides a DC level reference voltage for the GTL+
input buffers. A voltage divider should be used to divide VCCT by 2/3. Resistor values of 1.00 KΩ
and 2.00 KΩ are recommended. Decouple the VREF signal with three 0.1-µF high frequency
capacitors close to the processor.
8.2
Signal Summaries
Table 34 through Table 37 list the attributes of the processor input, output, and I/O signals.
Datasheet
63
Intel® Pentium® III Processor – Low Power
Table 34. Input Signals
Name
Active Level
Clock
Signal Group
Qualified
A20M#
BCLK
Low
High
Low
High
Low
Low
Low
Low
Asynch
—
CMOS
System Bus
System Bus
Implementation
System Bus
CMOS
Always
Always
Always
Always
Always
Always
Always
Always
BPRI#
BCLK
Asynch
BCLK
Asynch
Asynch
Asynch
BSEL[1:0]
DEFER#
FLUSH#
IGNNE#
INIT#
CMOS
System Bus
APIC disabled
mode
INTR
LINT[1:0]
NMI
High
High
High
Asynch
Asynch
Asynch
CMOS
APIC
APIC enabled
mode
APIC disabled
mode
CMOS
PICCLK
PREQ#
PWRGOOD
RESET#
RS[2:0]#
RSP#
High
Low
High
Low
Low
Low
Low
Low
Low
High
—
APIC
Implementation
Implementation
System Bus
System Bus
System Bus
Implementation
CMOS
Always
Always
Asynch
Asynch
BCLK
BCLK
BCLK
Asynch
Asynch
Asynch
—
Always
Always
Always
Always
SLP#
Stop Grant state
Always
SMI#
STPCLK#
TCK
Implementation
JTAG
Always
TDI
TCK
JTAG
TMS
TCK
JTAG
TRDY#
TRST#
Low
Low
BCLK
Asynch
System Bus
JTAG
Response phase
64
Datasheet
Intel® Pentium® III Processor – Low Power
Table 35. Output Signals
Name
Active Level
Clock
Signal Group
FERR#
IERR#
PRDY#
TDO
Low
Low
Low
High
High
Asynch
Asynch
BCLK
Open-drain
Open-drain
Implementation
JTAG
TCK
VID[4:0]
Asynch
Implementation
Table 36. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
ADS#
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
ADS#, ADS#+1
Always
AP[1:0]#
BREQ0#
BP[3:2]#
BPM[1:0]#
D[63:0]#
DBSY#
ADS#, ADS#+1
Always
Always
Always
DRDY#
Always
DEP[7:0]#
DRDY#
LOCK#
DRDY#
Always
Always
REQ[4:0]#
RP#
ADS#, ADS#+1
ADS#, ADS#+1
Table 37. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
AERR#
BERR#
BINIT#
BNR#
Low
Low
Low
Low
Low
Low
High
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
PICCLK
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
APIC
ADS#+3
Always
Always
Always
Always
Always
Always
HIT#
HITM#
PICD[1:0]
Datasheet
65
Intel® Pentium® III Processor – Low Power
9.0
PLL RLC Filter Specification
9.1
Introduction
The Pentium III Processor – Low Power processor has an internal PLL clock generator, which are
analog in nature and require quiet power supplies for minimum jitter. Jitter is detrimental to a
system; it degrades external I/O timings as well as internal core timings (i.e., maximum frequency).
In mobile Pentium II processors, the power supply filter was specified as an external LC network.
This remains largely the same for the Pentium III Processor – Low Power. However, due to
increased current flow, the value of the inductor has to be reduced, thereby requiring new
components. The general desired topology is shown in Figure 5. Excluded from the external
circuitry are parasitics associated with each component.
9.2
Filter Specification
The function of the filter is two fold. It protects the PLL from external noise through low-pass
attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the
low-pass description forms an adequate description for the filter.
The AC low-pass specification, with input at V
follows:
and output measured across the capacitor, is as
CCT
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
• 34 dB attenuation from 1 MHz to 66 MHz
• 28 dB attenuation from 66 MHz to core frequency
• The filter specification (AC) is graphically shown in Figure 24.
• Other requirements:
• Use a shielded type inductor to minimize magnetic pickup
• The filter should support a DC current of at least 30 mA
• The DC voltage drop from V
CCT
to PLL1 should be less than 60 mV, which in practice
implies series resistance of less than 2Ω. This also means that the pass band (from DC to 1Hz)
attenuation below 0.5 dB is for V = 1.1 V and below 0.35 dB for V = 1.5 V.
CCT
CCT
66
Datasheet
Intel® Pentium® III Processor – Low Power
Figure 24. PLL Filter Specifications
0.2 dB
0 dB
x dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
x = 20.log[(Vcct-60 mV)/
1 Hz
fpeak
1 MHz 66 MHz
fcore
high frequency
band
Vcct]
NOTES:
Diagram is not to scale
No specification for frequencies beyond f
core
F
, if existent, should be less than 0.05 MHz
peak
9.3
Recommendation for Low Power Systems
The following LC components are recommended. The tables will be updated as other suitable
components and specifications are identified.
Table 38. PLL Filter Inductor Recommendations
Rated
I
Min Damping
R needed
Inductor
Part Number
Value
Tol
SRF
DCR
L1
L2
TDK MLF2012A4R7KT
Murata LQG21N4R7K10
4.7 µH 10% 35 MHz 30 mA 0.56Ω (1Ω max)
0Ω
0Ω
4.7 µH 10% 47 MHz 30 mA
0.7Ω (+/-50%)
0.3Ω max
0.2Ω
(assumed)
L3
Murata LQG21C4R7N00
4.7 µH 30% 35 MHz 30 mA
NOTE: Minimum damping resistance is calculated from 0.35Ω – DCR . From vendor provided data, L1 and
min
L2 DCR
is 0.4 Ω and 0.5 Ω respectively, qualifying them for zero required trace resistance. DCR
min
min
for L3 is not known and is assumed to be 0.15 Ω. There may be other vendors who might provide
parts of equivalent characteristics and the OEMs should consider doing their own testing for selecting
their own vendors.
Datasheet
67
Intel® Pentium® III Processor – Low Power
Table 39. PLL Filter Capacitor Recommendations
Capacitor
Part Number
Value
Tolerance
ESL
ESR
C1
C2
Kemet T495D336M016AS
AVX TPSD336M020S0200
33 µF
33 µF
20%
20%
2.5 nH
0.225Ω
0.2Ω
unknown
NOTE: There may be other vendors who might provide parts of equivalent characteristics and the OEMs
should consider doing their own testing for selecting their own vendors.
Table 40. PLL Filter Resistor Recommendations
Resistor
Part Number
Value
Tolerance
Power
R1
various
1Ω
10%
1/16W
To satisfy damping requirements, total series resistance in the filter (from V
CCT
to the top plate of
the capacitor) must be at least 0.35Ω. This resistor can be in the form of a discrete component, or
routing, or both. For example, if the picked inductor has minimum DCR of 0.25Ω, then a routing
resistance of at least 0.10Ω is required. Be careful not to exceed the maximum resistance rule (2Ω).
For example, if using discrete R1, the maximum DCR of the L should be less than 2.0 - 1.1 = 0.9Ω,
which precludes using L2 and possibly L1.
Other routing requirements:
• The capacitor should be close to the PLL1 and PLL2 pins, with less than 0.1Ω per route (These
routes do not count towards the minimum damping resistance requirement).
• The PLL2 route should be parallel and next to the PLL1 route (minimize loop area).
• The inductor should be close to the capacitor; any routing resistance should be inserted
between VCCT and the inductor.
• Any discrete resistor should be inserted between VCCT and the inductor.
9.4
Comments
• A magnetically shielded inductor protects the circuit from picking up external flux noise. This
should provide better timing margins than with an unshielded inductor.
• A discrete or routed resistor is required because the LC filter by nature has an under-damped
response, which can cause resonance at the LC pole. Noise amplification at this band, although
not in the PLL-sensitive spectrum, could cause a fatal headroom reduction for analog circuitry.
The resistor serves to dampen the response. Systems with tight space constraints should
consider a discrete resistor to provide the required damping resistance. Too large of a damping
resistance can cause a large IR drop, which means less analog headroom and lower frequency.
• Ceramic capacitors have very high self-resonance frequencies, but they are not available in
large capacitance values. A high self-resonant frequency coupled with low ESL/ESR is crucial
for sufficient rejection in the PLL and high frequency band. The recommended tantalum
capacitors have acceptably low ESR and ESL.
• The capacitor must be close to the PLL1 and PLL2 pins, otherwise the value of the low ESR
tantalum capacitor is wasted. Note the distance constraint should be translated from the 0.1-Ω
requirement.
The mobile Pentium II processor LC filter cannot be used with the Pentium III Processor – Low
Power. The larger inductor of the old LC filter imposes a lower current rating. Due to increased
current requirements for the Pentium III Processor – Low Power, a lower value inductor is required.
68
Datasheet
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明