LP80C31BH-2 [INTEL]
Microcontroller, 8-Bit, 8051 CPU, 12MHz, CMOS, PDIP40, PLASTIC, DIP-40;
| 型号： | LP80C31BH-2 |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 8-Bit, 8051 CPU, 12MHz, CMOS, PDIP40, PLASTIC, DIP-40 时钟 微控制器 光电二极管 外围集成电路 装置 |
| 文件： | 总21页 (文件大小：2211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
87C51/80C51BH/80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C51/80C51BH/80C51BHP/80C31BH
*See Table 1 for Proliferation Options
■
■
■
■
High Performance CHMOS EPROM
24 MHz Operation
5 Interrupt Sources
■
■
Programmable Serial Port
Improved Quick-Pulse Programming
Algorithm
TTL- and CMOS-Compatible Logic
Levels
■
■
■
■
■
■
■
■
■
■
3-Level Program Memory Lock
Boolean Processor
64K External Program Memory Space
64K External Data Memory Space
ONCE Mode Facilitates System Testing
128-Byte Data RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Extended Temperature Range
Power Control Modes
• Idle
• Power Down
(-40 C to +85 C)
°
°
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel's reliable CHMOS III-E technology. Being
a member of the MCS® 51 controller family, the
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-
pin compatible with the existing MCS 51 controller family of products.
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,
unless information applies to a specific device.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION,2004
July 2004
Order Number: 272335-004
87C51/80C51BH/80C31BH
Table 1. Proliferation Options
*Standard
-1
X
-2
X
-24
X
80C31BH
80C51BH
80C51BHP
87C51
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTES:
e
g
5V 20%
*
3.5 MHz to 12 MHz; V
CC
CC
CC
CC
e
e
e
g
-1 3.5 MHz to 16 MHz; V
-2 0.5 MHz to 12 MHz; V
-24 3.5 MHz to 24 MHz; V
5V 20%
g
5V 20%
g
5V 20%
272335±1
Figure 1. 87C51/BH Block Diagram
2
87C51/80C51BH/80C31BH
PROCESS INFORMATION
PACKAGES
Part
Package Type
The 87C51-BH is manufactured on the CHMOS III-E
process. Additional process and reliability informa-
DIP (OTP)
87C51-BH
40-Pin Plastic
®
tion is available in the Intel Quality System
(EPROM)
40-Pin CERDIP
Handbook .
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
272335–3
272335–2
PLCC
DIP
272335–4
QFP
Figure 2. Pin Connections
*Do not connect reserved pins.
3
87C51/80C51BH/80C31BH
PIN DESCRIPTION
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
V
: Supply voltage during normal, Idle and Power
CC
Down operations.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
V
: Circuit ground.
SS
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped-
ance inputs.
(I , on the data sheet) because of the pullups.
IL
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emit-
ting 1's.
Pin Name
Alternate Function
P3.0 RXD Serial input line
P3.1 TXD Serial output line
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
P3.4
P3.5
P3.6
P3.7
T0
T1
WR
RD
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
Port
3 also receives some control signals for
EPROM programming and program verification.
(I , on the data sheet) because of the internal pull-
IL
ups.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
tion when a minimum V
voltage is applied wheth-
IH1
er the oscillator is running or not. An internal pull-
down resistor permits a power-on reset with only a
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
capacitor connected to V
.
CC
ALE/PROG : Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming for
the 87C51.
(I , on the data sheet) because of the internal pull-
IL
ups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1's.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no effect if
the microcontroller is in external execution mode.
During accesses to external Data Memory that use
8-bit addresses (MOVX @Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
4
87C51/80C51BH/80C31BH
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3.
PSEN: Program Store Enable is the Read strobe to
External Program Memory. When the 87C51/BH is
executing from Internal Program Memory, PSEN is
inactive (high). When the device is executing code
from External Program Memory, PSEN is activated
twice each machine cycle, except that two PSEN
activations are skipped during each access to Exter-
nal Data Memory.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require-
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the data
sheet must be observed.
EA/V
: External Access enable. EA must be
PP
strapped to V in order to enable the 87C51/BH to
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
SS
fetch code from External Program Memory locations
starting at 0000H up to FFFFH. Note, however, that
if either of the Lock Bits is programmed, the logic
level at EA is internally latched during reset.
capacitance. Once the external signal meets the V
IL
and V specifications the capacitance will not ex-
IH
ceed 20 pF.
EA must be strapped to V
execution.
for internal program
CC
This pin also receives the programming supply volt-
age (V ) during EPROM programming.
PP
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifi-
er.
272335±6
Figure 4. External Clock Drive
272335±5
Figure 3. Using the On-Chip Oscillator
5
87C51/80C51BH/80C31BH
IDLE MODE
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset.
To properly terminate Power Down, the reset or ex-
ternal interrupt should not be executed before V is
CC
restored to its normal operating level, and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RET1 will be the one following the instruction that
put the device into Power Down.
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes pro-
gram execution, from where it left off, up to two ma-
chine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminat-
ed by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.
DESIGN CONSIDERATIONS
Exposure to light when the device is in operation
may cause logic errors. For this reason, it is sug-
gested that an opaque label be placed over the
window when the die is exposed to ambient light.
#
POWER DOWN MODE
The 87C51/BH now have some additional fea-
tures. The features are: asynchronous port reset,
4 interrupt priority levels, power off flag, ALE dis-
able, serial port automatic address recognition,
serial port framing error detection, 64-byte en-
cryption array, and 3 program lock bits. These
features cannot be used with the older versions
of 80C51BH/80C31BH. The newer version of
80C51BH/80C31BH will have change identifier
"A'' appended to the lot number.
#
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is transmitted.
On the 87C51/BH either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down.
Reset redefines all the SFR's but does not change
Table 2. Status of the External Pins during Idle and Power Down
Program
Mode
Idle
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Idle
Power Down
Power Down
Data
6
87C51/80C51BH/80C31BH
ONCE MODE
The ONCE (``On-CircuitEmulation'') mode facilitates
testing and debugging of systems using the
87C51/BH without the 87C51/BH having to be re-
moved from the circuit. The ONCE mode is invoked
by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains ac-
tive. While the 87C51/BH is in this mode, an emula-
tor or test CPU can be used to drive the circuit. Nor-
mal operation is restored when a normal reset is ap-
plied.
87C51/BH EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS-51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
temperature.
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of 0°C to 70°C. With the extend-
ed temperature range option, operational character-
istics are guaranteed over the range of -40°C to
+85 C.
°
The optional burn-in is dynamic for a minimum time
±
of 160 hours at 125°C with V
= 6.9V 0.25V,
CC
following guidelines in MIL-STD-883, Method 1015.
7
87C51/80C51BH/80C31BH
ABSOLUTE MAXIMUM RATINGS:
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias.... -40 C to +85 C
°
°
°
Storage Temperature..................... - 65 C to +150 C
°
Voltage on EA/V
Pin to V
SS..............
0V to +13.0V
0.5V to + 6.5V
PP
*WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability.
-
Voltage on Any Other Pin to V
SS........
Maximum I per I/O Pin...................................15mA
OL
Power Dissipation................................................1.5W
(Based on package heat transfer limitations, not de-
vice power consumption.)
OPERATING CONDITIONS
Symbol
Description
Min
Max
Unit
T
A
Ambient Temperature Under Bias
Commercial
Express-40
+
+
0
70
85
°C
°C
V
CC
Supply Voltage
4.5
5.5
V
f
Oscillator Frequency
87C51/BH
87C51-1/BH-1
87C51-2/BH-2
87C51-24/BH-24
MHz
OSC
3.5
3.5
0.5
3.5
12
16
12
24
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol Parameter
Min
Typ(1)
Max
Unit Test Conditions
V
V
V
Input Low Voltage
Commercial
Express
IL
-
-
-
0.1
0.5
0.5
0.2 V
0.2 V
V
V
CC
CC
-
0.15
Input Low Voltage EA
Commercial
Express
IL1
IH
0
0.5
0.2 V
-0.3
-0.35
V
V
CC
-
0.2 V
CC
Input High Voltage
(Except XTAL1, RST)
Commercial
0.2 V
0.9
V
CC
+0.5
+0.5
V
V
+
CC
0.2 V
Express
1
V
CC
+
CC
V
V
Input High Voltage
(XTAL1, RST)
Commercial
Express
IH1
0.7 V
V
+0.5
V +0.5
CC
V
V
CC
CC
0.7 V
+ 0.1
CC
(6)
(2)
=
=
=
Output Low Voltage
(Ports 1, 2, 3)
0.3
V
V
V
I
I
I
100 mA
OL
OL
OL
OL
(2)
0.45
1.0
1.6 mA
3.5 mA
(2)
8
87C51/80C51BH/80C31BH
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
Symbol Parameter
Min
Typ(1)
Max
Unit Test Conditions
(6)
(2)
e
e
e
V
V
V
Output Low Voltage
0.3
V
V
V
V
V
V
V
V
V
I
I
I
I
I
I
I
I
I
200 mA
OL1
OL
OL
OL
OH
OH
OH
OH
OH
OH
(Port 0, ALE, PSEN)
(2)
0.45
1.0
3.2 mA
(2)
7.0 mA
(3)
b
b
b
b
b
b
e b
e b
e b
e b
e b
e b
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
0.3
0.7
1.5
0.3
0.7
1.5
10 mA
30 mA
60 mA
OH
(3)
(3)
(3)
Output High Voltage
(Port 0 in External Bus Mode)
200 mA
OH1
(3)
3.2 mA
7.0 mA
(3)
e
0.45V
I
IL
Logical 0 Input Current
(Ports 1, 2, 3)
Commercial
V
IN
b
b
50
75
mA
mA
Express
k
k
V
g
I
I
Input Leakage Current
(Port 0)
10
mA
0.45
V
LI
IN
CC
e
2V
Logical 1-to-0 Transition Current
(Ports 1, 2, 3)
V
IN
TL
b
b
Commercial
Express
650
750
mA
mA
RRST
RST Pulldown Resistor
Pin Capacitance
40
225
kX
@
C
IO
10
pF
1 MHz, 25 C
§
I
Power Supply Current
Active Mode
(Note 4)
CC
@
12 MHz (Figure 5)
16 MHz
11.5
20
26
38
mA
mA
mA
@
@
24 MHz
Idle Mode
@
12 MHz (Figure 5)
16 MHz
24 MHz
3.5
5
7.5
9.5
13.5
mA
mA
mA
@
@
Power Down Mode
50
mA
9
87C51/80C51BH/80C31BH
NOTES:
1. ``Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and
OL
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the V
cation when the address bits are stabilizing.
on ALE and PSEN to momentarily fall below the 0.9V specifi-
OH
CC
4. See Figures 6 through 8 for I
test conditions. Minimum V for Power Down is 2V.
CC
CC
5. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
OL
10 mA
Maximum I per 8-bit port-
OL
Port 0: 26 mA
Ports 1, 2, and 3: 15 mA
Maximum total I for all output pins: 71 mA
OL
If I exceeds the test condition, V may exceed the related specification.
OL OL
Pins are not guaranteed to sink greater than the listed test conditions.
272335±26
Figure 5. 87C51/BH I vs Frequency
CC
10
87C51/80C51BH/80C31BH
272335±10
Figure 6. I Test Condition, Active Mode. All other pins are disconnected.
CC
272335±9
272335±8
Figure 9. I Test Condition, Power Down
CC
Mode. All other pins are disconnected.
Figure 7. I Test Condition, Idle Mode.
CC
All other pins are disconnected.
e
V
2V to 5.5V.
CC
272335±11
Figure 8. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
e
e
TCLCH
TCHCL
5 ns
11
87C51/80C51BH/80C31BH
L:Logic level LOW, or ALE.
P:PSEN.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a `T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
Q:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
A:Address.
C:Clock.
D:Input data.
For example,
H:Logic level HIGH.
I:Instruction (program memory contents).
e
e
TAVLL
TLLPL
Time from Address Valid to ALE Low.
Time from ALE Low to PSEN Low.
AC CHARACTERISTICS: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and
e
e
80 pF)
PSEN
100 pF; Load Capacitance for All Other Outputs
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2.
Oscillator
Symbol
Parameter
12 MHz
24 MHz
Variable
Units
Min Max Min Max
Min
Max
1/TCLCL Oscillator Frequency
87C51/BH
3.5
3.5
0.5
3.5
12
16
12
24
MHz
MHz
MHz
MHz
87C51-1/BH-1
87C51-2/BH-2
87C51-24/BH-24
b
TLHLL
TAVLL
ALE Pulse Width
127
43
43
2TCLCL 40
ns
Address Valid to ALE Low
87C51/BH
87C51-24/BH-24
b
TCLCL 40
ns
ns
b
12
12
TCLCL 30
b
TLLAX
TLLIV
Address Hold After ALE Low 53
TCLCL 30
ns
ALE Low to Valid Instr In
87C51/BH
87C51-24/BH-24
b
234
145
4TCLCL 100
ns
ns
b
91
35
4TCLCL 75
b
TLLPL
TPLPH
TPLIV
ALE Low to PSEN Low
PSEN Pulse Width
53
12
80
TCLCL 30
ns
ns
b
3TCLCL 45
205
PSEN Low to Valid Instr In
87C51/BH
87C51-24/BH-24
b
3TCLCL 105
ns
ns
b
3TCLCL 90
12
87C51/80C51BH/80C31BH
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued)
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
Variable
Min Max Min Max
Min
Max
TPXIX
TPXIZ
Input Instr Hold After PSEN
0
0
0
ns
Input Instr Float After PSEN
87C51/BH
87C51-24/BH-24
b
59
TCLCL 25
ns
ns
b
21
103
10
TCLCL 20
b
TAVIV
TPLAZ
TRLRH
Address to Valid Instr In
PSEN Low to Address Float
RD Pulse Width
312
10
5TCLCL 105
ns
ns
ns
ns
10
b
6TCLCL 100
400
400
150
150
b
TWLWH WR Pulse Width
TRLDV RD Low to Valid Data In
6TCLCL 100
b
87C51/BH
87C51-24/BH-24
252
5TCLCL 165
ns
ns
b
113
23
5TCLCL 95
TRHDX Data Hold After RD
0
0
0
ns
ns
b
2TCLCL 60
TRHDZ
TLLDV
Data Float After RD
107
517
ALE Low to Valid Data In
87C51/BH
87C51-24/BH-24
b
8TCLCL 150
ns
ns
b
243
8TCLCL 90
TAVDV
Address to Valid Data In
87C51/BH
b
585
9TCLCL 165
ns
ns
b
87C51-24/BH-24
285
175
9TCLCL 90
b
a
TLLWL
ALE Low to RD or WR Low
200 300
203
75
77
12
3TCLCL 50
3TCLCL 50
ns
TAVWL Address to RD or WR Low
87C51/BH
b
4TCLCL 130
ns
ns
b
87C51-24/BH-24
4TCLCL 90
TQVWX Data Valid to WR Transition
87C51/BH
b
33
TCLCL 50
ns
ns
b
80C51-24/BH-24
TCLCL 30
13
87C51/80C51BH/80C31BH
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to
87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued)
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
Variable
Min Max Min Max
Min
Max
TWHQX Data Hold After WR
87C51/BH
b
33
TCLCL 50
ns
ns
b
87C51-24/BH-24
7
TCLCL 35
TQVWH Data Valid to WR High
87C51/BH
b
433
222
7TCLCL 150
ns
ns
b
87C51-24/BH-24
7TCLCL 70
TRLAZ
RD Low to Address Float
0
0
0
ns
TWHLH RD or WR High to ALE High
87C51/BH
b
a
43
123
TCLCL 40
TCLCL 40
ns
ns
b
a
87C51-24/BH-24
12
71
TCLCL 30
TCLCL 30
EXTERNAL PROGRAM MEMORY READ CYCLE
272335±12
EXTERNAL DATA MEMORY READ CYCLE
272335±13
14
87C51/80C51BH/80C31BH
EXTERNAL DATA MEMORY WRITE CYCLE
272335-14
EXTERNAL CLOCK DRIVE
All parameter values apply to all devices unless otherwise indicated. In this
table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2.
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
87C51/BH
3.5
3.5
0.5
3.5
12
16
12
24
MHz
MHz
MHz
MHz
87C51-1/BH-1
87C51-2/BH-2
87C51-24/BH-24
TCHCX
TCLCX
TCLCH
TCHCL
High Time
87C51/BH
8751-24/BH-24
20
ns
ns
0.35TCLCL
0.65TCLCL
0.65TCLCL
Low Time
87C51/BH
87C51-24/BH-24
20
ns
ns
0.35TCLCL
Rise Time
87C51/BH
87C51-24/BH-24
20
10
ns
ns
Fall Time
87C51/BH
87C51-24/BH-24
20
10
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272335±15
15
87C51/80C51BH/80C31BH
SERIAL PORT TIMING-SHIFT REGISTER MODE
12 MHz
Oscillator
24 MHz
Oscillator
Variable Oscillator
Symbol
Parameter
Units
Min
Max
Min
Max
Min
Max
TXLXL
Serial Port Clock
Cycle Time
1.0
0.500
12TCLCL
ms
ns
ns
b
10TCLCL 133
TQVXH Output Data Setup
to Clock Rising Edge
700
284
TXHQX Output Data Hold
After Clock
Rising Edge
87C51/BH
87C51-24/BH-24
b
2TCLCL 117
50
0
b
34
0
2TCLCL 34
TXHDX Input Data Hold
After Clock
0
ns
ns
Rising Edge
b
10TCLCL 133
TXHDV Clock Rising Edge
to Input Data Valid
700
283
SHIFT REGISTER MODE TIMING WAVEFORMS
272335±18
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272335±19
272335±20
port pin is no longer floating when
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded V /V level occurs.
For timing purposes
a
a
b
AC inputs during testing are driven at V
CC
0.5 for a Logic ``1''
and 0.45V for a Logic ``0.'' Timing measurements are made at V
IH
OH OL
e
g
min for a Logic ``1'' and V max for a Logic ``0''.
IL
I
/I
20 mA.
OL OH
16
87C51/80C51BH/80C31BH
PROGRAMMING THE 87C51
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines. Control and program signals must
be held at the levels indicated in Table 4. Normally
ADDRESS LINES: P1.0±P1.7, P2.0±P2.5, P3.4 re-
spectively for A0±A14.
DATA LINES: P0.0±P0.7 for D0±D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
EA/V
is held at logic high until just before
P3.6, P3.7.
PP
ALE/PROG is to be pulsed. The EA/V
is raised to
PP
V , ALE/PROG is pulsed low and then EA/V
PP
is
PROGRAM SIGNALS: ALE/PROG , EA/V
.
PP
PP
returned to a high (also refer to timing diagrams).
NOTE:
Exceeding the V maximum for any amount of
time could damage the device permanently. The
#
PP
V
PP
source must be well regulated and free of
glitches.
Table 4. EPROM Programming Modes
ALE/
PROG
EA/
V
PP
Mode
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
Verify Code Data
H
H
H
L
L
L
ß
H
12.75V
H
L
L
L
H
L
H
L
H
H
L
H
H
H
Program Encryption
Array Address 0±3F
ß
12.75V
H
H
Program Lock Bits
Bit 1
Bit 2
Bit 3
H
H
H
H
L
L
L
L
ß
ß
ß
H
12.75V
12.75V
12.75V
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
H
L
Read Signature Byte
L
272335±21
*See Table 4 for proper input on these pins
Figure 10. Programming the EPROM
17
87C51/80C51BH/80C31BH
272335±22
*For compatibility, 25 pulses may be used.
Figure 11. Programming Waveforms
The 80C51BH has a one level program lock system
and a 64-byte encryption table. If program protection
is desired, the user submits the encryption table with
their code and both the lock bit and encryption array
are programmed by the factory. The encryption array
is not available without the lock bit. For the lock bit
to be programmed, the user must submit an encryp-
tion table. The 87C51 has a 3-level program lock
system and a 64-byte encryption array. Since this is
an EPROM device, all locations are user-program-
mable. See Table 5.
PROGRAMMING ALGORITHM
Refer to Table 4 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control sig-
nals.
g
from V to 12.75V 0.25V.
CC
4. Raise EA/V
PP
5. Pulse ALE/PROG 5 times* for the EPROM array,
and 25 times for the encryption table and the lock
bits.
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 ad-
dress lines are used to select a byte of the Encryp-
tion Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un-
programmed state (all 1's), will return the code in its
original, unmodified form. For programming the En-
cryption Array, refer to Table 4 (Programming the
EPROM).
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
Program Verify
Verification may be done after programming either
one byte or a block of bytes. In either case a com-
plete verify of the array will ensure reliable program-
ming of the 87C51.
When using the encryption array, one important fac-
tor needs to be considered. lf a code byte has the
value 0FFH, verifying the byte will produce the en-
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their fea-
tures are enabled.
l
cryption byte value. lf a large block ( 64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH, and not
all of them the same value. This will ensure maxi-
mum program protection.
ROM and EPROM Lock System
The program lock system, when programmed, pro-
tects the onboard program against software piracy.
18
87C51/80C51BH/80C31BH
Program Lock Bits
Erasure Characteristics
(Windowed Devices Only)
The 87C51 has 3 programmable lock bits that when
programmed according to Table 5 will provide differ-
ent levels of protection for the on-chip code and
data.
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an ex-
tended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadver-
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 87C51 and 80C51BH have 3 signature bytes in
locations 30H, 31H, and 60H. To read these bytes
follow the procedure for EPROM verify, but activate
the control lines provided in Table 4 for Read Signa-
ture Byte.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
2
ed dose of at least 15 W-sec/cm . Exposing the
2
EPROM to an ultraviolet lamp of 12,000 mW/cm
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Location
30H
Device
All
Contents
89H
Erasure leaves the array in an all 1's state.
31H
All
58H
60H
87C51
80C51BH
51H
11H
Table 5. Program Lock Bits and the Features
Protection Type
Program Lock Bits
LB1
LB2
LB3
1
2
U
U
U
No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3
4
P
P
P
P
U
P
Same as 2, also verify is disabled.
Same as 3, also external execution is disabled.
19
87C51/80C51BH/80C31BH
EPROM PROGRAMMING, EPROM AND ROM VERIFICATION
CHARACTERISTICS:
e
e
e
0V)
g
(T
A
21 C to 27 C, V
5V 10%, V
§
§
CC
SS
Symbol
Parameter
Min
Max
13.0
Units
V
V
PP
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
12.5
I
75
6
mA
PP
1/TCLCL
TAVGL
TGHAX
TDVGL
TGHDX
TEHSH
TSHGL
TGHSL
TGLGH
TAVQV
TELQV
TEHQZ
TGHGL
4
MHz
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
48TCLCL
48TCLCL
48TCLCL
48TCLCL
48TCLCL
10
P2.7 (ENABLE) High to V
PP
V
Setup to PROG Low
Hold After PROG
ms
ms
ms
PP
PP
V
10
PROG Width
90
110
Address to Data Valid
48TCLCL
48TCLCL
48TCLCL
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to PROG Low
0
10
ms
EPROM PROGRAMMING, EPROM AND ROM VERIFICATION WAVEFORMS
272335±23
*For programming conditions see Figure 10.
**5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
20
87C51/80C51BH/80C31BH
Thermal Impedance
The following differences exist between this data-
sheet (272335-003) and the previous version
(272335-002):
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operating conditions and ap-
plications. See the Intel Packaging Handbook (Order
No. 240800) for a description of Intel's thermal im-
pedance test methodology.
–
–
–
1. Removed 20 and 3 spec, replaced with 24
spec.
–
2. Added 24 spec.
3. 80C51BHP is replaced by 80C51BH with 64-byte
encryption table submitted and lock bit 1 set.
Device
θ
θ
JC
JA
4. 80C51BH/80C31BH are now having some addi-
tional features as 87C51.
87C51
BH
87C51
BH
All
All
45 C/W
16 C/W
°
°
5. Revised PRST value and I idle values.
CC
75 C/W
23 C/W
°
°
45 C/W
15 C/W
°
°
6. Added P3.3 control pin to programming and veri-
fication.
36 C/W
13 C/W
°
°
46 C/W
16 C/W
°
°
7. Added 80C51BH signature byte.
98 C/W
24 C/W
°
°
The following differences exist between the ``-002''
and the ``-001'' version of the 87C51/80C51BH/
80C31BH datasheet.
DATA SHEET REVISION HISTORY
-
=
±
1. Removed L, I
forms figure.
10 mA from Float Wave-
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices.
OL
2. Removed QP, QD and QN (commercial with ex-
tended burn-in) from Table 3. Prefix Identification.
The following differences exist between this data-
sheet (272335-004) and the previous version
(272335-003):
This data sheet (272335-001) replaces the following:
80C51BH/80C31BH Express
80C51BHP
270218-003
270603-004
270147-008
270430-002
272082-002
1. Product prefix variables are now indicated with an x.
87C51/80C51BH/80C31BH
87C51 Express
87C51-20/-3
21
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明