N80930HD [INTEL]
Microcontroller, 16-Bit, 80251 CPU, 12MHz, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | N80930HD |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 16-Bit, 80251 CPU, 12MHz, CMOS, PQCC68, PLASTIC, LCC-68 时钟 微控制器 外围集成电路 |
| 文件： | 总38页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
8x930Hx
UNIVERSAL SERIAL BUS HUB
PERIPHERAL CONTROLLER
■ USB Hub with One Upstream, One
■ Embedded Function FIFO Data Buffers
Internal Downstream, and Three
External Downstream Ports on HD/HE
Parts or Four on HF/HG Parts
— Three Pairs of 16-byte Transmit and
Receive FIFOs
— One Pair of Configurable Transmit
and Receive FIFOs (1 Kbyte total)
— Complete Universal Serial Bus Speci-
fication 1.0 Compatibility
■ Automatic Transmit/Receive FIFO
— Serves as both USB Hub and USB
Embedded Function (Internal Port)
Management
■ Three USB Interrupt Vectors
— Endpoint Transmit/Receive Done
— Start of Frame/Hub Endpoint Done
— Global Suspend/Resume
■ USB Hub
— Connectivity Management
— Downstream Device
Connect/Disconnect Detection
— Power Management, Including
Suspend and Resume
■ Low Clock Mode
■ User-selectable Configurations
— External Wait State
— External Address Range
— Page Mode
— Bus Fault Detection and Recovery
— Full and Low Speed Downstream
Device Support
■ Output Pin for Port Power Switching
■ Input Pin for Overcurrent Detection
■ USB Embedded Function
■ Real-time Wait Function
■ 256-Kbyte External Code/Data Memory
Space
— Supports Isochronous and
Non-isochronous Data
■ On-chip ROM Options
— 0, 8, or 16 Kbytes
■ On-chip USB Transceivers
■ 1024 bytes On-chip Data RAM
■ Four Input/Output Ports
■ Standard MCS® 51 UART
■ Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
■ Power-saving Idle and Powerdown
— NRZI Encoding/Decoding and
Bit-stuffing
Modes
■ Register-based MCS® 251 Architecture
■ Hub FIFO Data Buffers
■ Code-compatible with MCS 51 and
— One Pair of 16-byte Transmit and
Receive FIFOs
MCS 251 Microcontrollers
■ 12-MHz Crystal Operation
— One 1-byte Transmit Register
The 8x930Hx USB hub peripheral controller is based on the MCS 251 microcontroller. It consists of standard
8XC251Sx peripherals plus a USB module. The USB module provides both USB hub and USB embedded
function capabilities. The 8x930Hx supports USB hub functionality, embedded function, suspend/resume
modes, isochronous/non-isochronous transfers, and it is fully USB rev 1.0 specification compliant. The USB
module contains one internal and three (or four) external downstream ports and integrates the USB trans-
ceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and
transmit/receive FIFOs. The 8x930Hx uses the standard instruction set of the MCS 251 architecture, which is
binary code compatible with the MCS 51 architecture.
COPYRIGHT © INTEL CORPORATION, 1997
May 1997
Order Number: 272928-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1997
CONTENTS
1.0 About This Document.......................................................................................................... 1
1.1 Additional Information Sources ...................................................................................... 1
1.2 Electronic Information..................................................................................................... 1
1.3 Product Summary........................................................................................................... 2
2.0 Nomenclature Overview...................................................................................................... 4
3.0 Pinout.................................................................................................................................. 6
4.0 Signals .............................................................................................................................. 12
5.0 Address Map..................................................................................................................... 16
6.0 Electrical Characteristics................................................................................................... 17
6.1 Operating Frequencies................................................................................................. 17
6.2 DC Characteristics........................................................................................................ 18
6.3 Explanation of Timing Symbols.................................................................................... 20
6.4 System Bus AC Characteristics.................................................................................... 21
6.4.1 System Bus Timing Diagrams ...............................................................................23
6.4.2 Real-time Wait State Function AC Characteristics ................................................27
6.4.3 Real-time Wait State Function Timing Diagrams ..................................................28
6.5 AC Characteristics — Synchronous Mode 0................................................................ 30
6.6 External Clock Drive..................................................................................................... 30
6.7 Testing Waveforms ...................................................................................................... 31
7.0 Thermal Characteristics .................................................................................................... 32
8.0 Design Considerations...................................................................................................... 32
8.1 External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection........... 32
8.2 Low Clock Mode Frequency......................................................................................... 32
8.3 Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO ................................. 32
8.4 Series Resistor Requirement for Impedance Matching................................................ 32
8.5 Pullup Resistor Requirement for 8x930Hx Hub devices............................................... 32
8.6 Powerdown Mode Cannot Be Invoked Before USB Suspend...................................... 32
8.7 Unused Downstream Ports........................................................................................... 33
9.0 8x930Hx Errata ................................................................................................................. 33
10.0 Datasheet Revision History............................................................................................... 33
iii
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Figures
1.
2.
3.
4.
5.
6.
7.
8.
9.
8x930Hx Block Diagram.......................................................................................................2
8x930Hx USB Module Block Diagram..................................................................................3
Product Nomenclature .........................................................................................................4
8x930HD/HE and 8x930HF/HG 68-pin PLCC Package.......................................................6
8x930HD/HE and 8x930HF/HG 64-pin SDIP Package........................................................7
8x930Hx Code Fetch, Nonpage Mode...............................................................................23
8x930Hx Data Read, Nonpage Mode ................................................................................24
8x930Hx Data Write, Nonpage Mode.................................................................................24
8x930Hx Code Fetch, Page Mode.....................................................................................25
10. 8x930Hx Data Read, Page Mode ......................................................................................26
11. 8x930Hx Data Write, Page Mode.......................................................................................26
12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State) .........................28
13. External Data Write (Nonpage Mode, Real-time Wait State) .............................................28
14. External Data Read (Page Mode, Real-time Wait State) ...................................................29
15. External Data Write (Page Mode, Real-time Wait State) ...................................................29
16. Serial Port Waveform — Synchronous Mode 0..................................................................30
17. External Clock Drive Waveforms........................................................................................30
18. AC Testing Input, Output Waveforms.................................................................................31
19. Float Waveforms................................................................................................................31
Tables
1.
2.
3.
5.
4.
6.
7.
8.
9.
Related Documentation........................................................................................................1
Electronic Information ..........................................................................................................1
Description of Product Nomenclature...................................................................................4
Downstream Port Allocation.................................................................................................5
Proliferation Options.............................................................................................................5
68-pin PLCC Pin Assignment...............................................................................................8
64-pin SDIP Pin Assignment................................................................................................9
68-pin PLCC Signal Assignments Arranged by Functional Category ................................10
64-pin SDIP Signal Assignments Arranged by Functional Category..................................11
10. Signal Description ..............................................................................................................12
11. Memory Signal Selections (RD1:0) ...................................................................................15
12. 8x930Hx Address Map.......................................................................................................16
13. 8x930Hx Operating Frequency ..........................................................................................17
14. DC Characteristics at Operating Conditions.......................................................................18
15. AC Timing Symbol Definitions............................................................................................20
16. AC Characteristics at Operating Conditions.......................................................................21
17. Real-time Wait State AC Timing Specifications .................................................................27
18. Serial Port Timing — Synchronous Mode 0.......................................................................30
19. External Clock Drive...........................................................................................................31
20. Thermal Characteristics .....................................................................................................32
iv
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
1.0 ABOUT THIS DOCUMENT
1.2 Electronic Information
This data sheet contains advance information about
Intel’s 8x930Hx Universal Serial Bus hub peripheral
controller, based on the MCS® 251 peripheral
controller, which includes a functional overview,
mechanical data, targeted electrical specifications
We offer a variety of technical and product infor-
mation through the World Wide Web (see Table 2
for URL) and through FaxBack service which is an
on-demand publishing system that sends
documents to your fax machine. You can get
product announcements, change notifications,
product literature, device characteristics, design
recommendations, and quality and reliability infor-
mation 24 hours a day, 7 days a week. Just dial the
telephone number and respond to the system
prompts.
(simulated), and bus functional waveforms.
A
detailed functional description, other than
parametric performance, is published in the
8x930Ax, 8x930Hx Universal Serial Bus Micorcon-
troller User’s Manual (272949).
1.1 Additional Information Sources
Intel documentation is available from your local Intel
Sales Representative or Intel Literature Sales.
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
1-800-879-4683
Table 1. Related Documentation
Document Title
Order/Contact
8x930Ax, 8x930Hx Universal Serial Bus Micorcontroller
User’s Manual
Intel Order # 272949
Universal Serial Bus Specification
Intel Order # 272962
Table 2. Electronic Information
Document Title
Order/Contact
Intel’s World-Wide Web (WWW) Location:
Customer Support (US and Canada):
FaxBack Service:
http://www.intel.com/design/usb/
800-628-8686
US and Canada
800-628-2283
+44(0)793-496646
916-356-3105
Europe
worldwide
Application Bulletin Board Service:
up to 14.4-Kbaud line, worldwide
dedicated 2400-baud line, worldwide
Europe
916-356-3600
916-356-7209
+44(0)793-496340
ADVANCE INFORMATION
1
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
1.3 Product Summary
I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
RAM
ROM
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Bus Interface
Peripheral
Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Serial I/O
Clock
&
Reset
Data
Register
File
Memory
Interface
ALU
†
USB
DST (16)
Microcontroller Core
USB Ports
†
For details, see the USB module block diagram.
A4340-01
Figure 1. 8x930Hx Block Diagram
2
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
USB Upstream Port
Transceiver
DM1 USB
Transceiver
Downstream
Ports
DP1
DM2
DP2
Transceiver
Transceiver
Transceiver
Repeater
DM3
DP3
DM5
DP5
HF/HG only
Serial Bus Interface Engine
(SIE)
Hub
Interface
Unit
Function
Interface
Unit
(HIU)
(FIU)
Control
Transmit/Receive Bus
To
CPU
Data Bus
Control
FIFOs
A5102-02
Figure 2. 8x930Hx USB Module Block Diagram
ADVANCE INFORMATION
3
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
2.0 NOMENCLATURE OVERVIEW
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 3. Product Nomenclature
Table 3. Description of Product Nomenclature
Options Description
Parameter
Temperature and Burn-in
no mark Commercial operating temperature range (0oC to 70oC) with
Intel standard burn-in
Packaging Options
N
U
0
Plastic Leaded Chip Carrier (PLCC)
Shrink Dual In-Line Package (SDIP)
Without ROM
Program Memory Options
3
With ROM
Process and Voltage Information no mark CHMOS
Product Family
930Hx
Advanced 8-bit microcontroller architecture with on-chip
Universal Serial Bus Hub and Function capability. Indicates
ROM size, RAM size, and quantity of external downstream
ports (see Table 4).
Device Speed
no mark 12 MHz crystal
4
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 4. Proliferation Options
3 External
4 External
Downstream Ports Downstream Ports
ROM Size
RAM Size
Package
(HF/HG)
N80930HF
N83930HF
N83930HG
U80930HF
U83930HF
U83930HG
(HD/HE)
N80930HD
N83930HD
N83930HE
U80930HD
U83930HD
U83930HE
0
1024 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
68-pin PLCC
68-pin PLCC
68-pin PLCC
64-pin SDIP
64-pin SDIP
64-pin SDIP
8 Kbytes
16 Kbytes
0
8 Kbytes
16 Kbytes
Table 5. Downstream Port Allocation
8x930HD/HE
Downstream Port
8x930HF/HG
Number
1
2
3
4
5
External
External
External
External
External
External
Internal (Embedded Function) Internal (Embedded Function)
External
—
ADVANCE INFORMATION
5
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
3.0 PINOUT
Figure 4 illustrates a diagram of the 8x930HD/HE PLCC package. Table 6 and Table 8 contain indexes of the
pin arrangement. Table 10 contains the signal descriptions for all pins.
.
†
†
D
††
UPWEN# /
P5
AD7 / P0.7
AD6 / P0.6
AD5 / P0.5
AD4 / P0.4
AD3 / P0.3
AD2 / P0.2
AD1 / P0.1
AD0 / P0.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
†
D
OVRI# /
M5
D
D
P1
M1
Reserved
D
D
P0
M0
ECAP
View of component as
mounted on PC board
V
V
SSP
SSP
V
V
CCP
CCP
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
SOF#
D
D
P3
M3
Reserved
D
D
P2
P3.5 / T1
P3.6 / WR#
M2
PLLSEL0
NOTE:
Reserved pins must be left unconnected.
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
A4421-01
Figure 4. 8x930HD/HE and 8x930HF/HG 68-pin PLCC Package
6
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
V
V
SSP
CCP
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
A8 / P2.0
P3.5 / T1
P3.6 / WR#
8X930HX
P3.7 / A16 / RD#
P1.0 / T2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A9 / P2.1
P1.1 / T2EX
P1.2 / ECI
P1.3 / CEX0
P1.4 / CEX1
A10 / P2.2
A11 / P2.3
A12 / P2.4
A13 / P2.5
A14 / P2.6
A15 / P2.7
P1.5 / CEX2
View of
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
component
as mounted
on PC board
V
V
V
V
CC
SS
SS
CC
XTAL1
XTAL2
AV
EA#
ALE
PSEN#
UPWEN#
OVRI#
CC
RST
PLLSEL1
PLLSEL2
PLLSEL0
DM2
†
†
††
††
D
D
RESERVED /
RESERVED /
P5
M5
DP1
DMI
DP0
DM0
ECAP
DP2
DM3
DP3
SOF#
V
V
SSP
CCP
NOTE:
Reserved pins must be left unconnected.
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
A4422-01
Figure 5. 8x930HD/HE and 8x930HF/HG 64-pin SDIP Package
ADVANCE INFORMATION
7
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 6. 68-pin PLCC Pin Assignment
Pin
1
Name
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Name
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Name
Reserved
VSS
P3.4/T0
P3.5/T1
2
A15/P2.7
A14/P2.6
A13/P2.5
A12/P2.4
A11/P2.3
A10/P2.2
A9/P2.1
DM3
3
P3.6/WR#
P3.7/RD#/A16
P1.0/T2
DP3
4
SOF#
VCCP
5
6
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
VCC
VSSP
7
ECAP
DM0
8
9
A8/P2.0
DP0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VSSP
Reserved
DM1
DP1
††
OVRI#†/DM5
††
VSS
UPWEN#†/DP5
Reserved†/OVRI#††
Reserved†/UPWEN#††
XTAL1
XTAL2
AVCC
Reserved
Reserved
PSEN#
ALE
RST
VCCP
PLLSEL1
PLLSEL2
PLLSEL0
DM2
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
EA#
VCC
DP2
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
8
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 7. 64-pin SDIP Pin Assignment
Pin
Name
Pin
23
Name
Pin
45
Name
1
2
3
4
5
6
7
8
9
VCCP
RST
EA#
VCC
VSS
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/ INT1#
P3.4/T0
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PLLSEL1
PLLSEL2
PLLSEL0
DM2
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A15/P2.7
A14/P2.6
A13/P2.5
A12/P2.4
A11/P2.3
A10/P2.2
A9/P2.1
DP2
P3.5/T1
DM3
P3.6/WR#
P3.7/A16/RD#
P1.0/T2
DP3
SOF#
VCCP
10
11
12
13
14
15
16
17
18
19
20
21
22
P1.1/T2EX
P1.2/ECI
VSSP
A8/P2.0
ECAP
DM0
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VSSP
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
VCC
DP0
DM1
DP1
††
Reserved†/DM5
Reserved†/DP5
††
VSS
OVRI#
XTAL1
UPWEN#
PSEN#
XTAL2
AVCC
ALE
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
ADVANCE INFORMATION
9
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 8. 68-pin PLCC Signal Assignments Arranged by Functional Category
Address & Data
Name
Input/Output
Name
USB
Name
PLLSEL0
Pin
17
16
15
14
13
12
11
10
9
Pin
28
29
30
31
32
33
34
35
20
21
22
23
24
25
Pin
44
42
43
54
55
57
58
45
46
48
49
50
53
AD0/P0.0
P1.0/T2
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
P1.2/ECI
PLLSEL1
PLLSEL2
DM0
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
P3.0/RXD
DP0
DM1
DP1
DM2
DP2
A9/P2.1
8
P3.1/TXD
DM3
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
7
P3.2/INT0#
P3.3/INT1#
P3.4/T0
DP3
6
SOF#
ECAP
OVRI#
5
4
P3.5/T1
59†/
61††
A14/P2.6
3
P3.6/WR#
26
27
UPWEN#
60†/
62††
59††
60††
A15/P2.7
2
P3.7/RD#/A16
DM5
DP5
P3.7/RD#/A16
P1.7/CEX4/A17/WCLK
27
35
Processor Control
Power & Ground
Bus Control & Status
Name Pin
P3.6/WR#
Name
P3.2/INT0#
P3.3/INT1#
RST
Pin
22
23
41
38
39
Name
Pin
36, 68
19, 51
40
VCC
26
27
65
66
67
VCCP
AVCC
VSS
P3.7/RD#/A16
PSEN#
ALE
XTAL1
1, 37
18, 52
XTAL2
VSSP
EA#
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
10
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 9. 64-pin SDIP Signal Assignments Arranged by Functional Category
Address & Data
Name
Input/Output
Name
USB
Pin
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
9
Pin
10
11
12
13
14
15
16
17
2
Name
PLLSEL0
Pin
26
24
25
35
36
37
38
27
28
29
30
31
34
41
42
39
40
AD0/P0.0
P1.0/T2
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
P1.2/ECI
PLLSEL1
PLLSEL2
DM0
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
P3.0/RXD
DP0
DM1
DP1
DM2
DP2
A9/P2.1
P3.1/TXD
3
DM3
A10/P2.2
P3.2/INT0#
P3.3/INT1#
P3.4/T0
4
DP3
A11/P2.3
5
SOF#
ECAP
OVRI#
UPWEN#
A12/P2.4
6
A13/P2.5
P3.5/T1
7
A14/P2.6
P3.6/WR#
8
††
A15/P2.7
P3.7/A16/RD#
9
Reserved†/DM5
††
P3.7/A16/RD#
P1.7/CEX4/A17/WCLK
Reserved†/DP5
17
Processor Control
Power & Ground
Bus Control & Status
Name
P3.2/INT0#
P3.3/INT1#
RST
Pin
4
Name
Pin
46
32
22
47
64
Name
P3.6/WR#
P3.7/RD#/A16
PSEN#
Pin
8
VCC
5
VCCP
AVCC
VSS
9
23
20
21
43
44
45
XTAL1
ALE
XTAL2
VSSP
EA#
† Specific to the 8x930HD/HE
†† Specific to the 8x930HF/HG
ADVANCE INFORMATION
11
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
4.0 SIGNALS
Table 10. Signal Description (Sheet 1 of 4)
Alternate
Function
Signal
Type
Description
Name
A17
O
Address Line 17. Output to memory as 18th external address P1.7/CEX4/WCLK
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
A16
O
O
Address Line 16. Output to memory as 17th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
RD#
A15:8
AD7:0
ALE
Address Lines. Upper address lines for external memory.
Description is for nonpage mode configuration. For page mode
configuration, data (D7:0) is multiplexed with the upper address
byte (A15:8).
P2.7:0
I/O
O
Address/Data Lines. Multiplexed lower address lines and data P0.7:0
lines for external memory. Description is for nonpage mode
configuration. For page mode configuration, data (D7:0) is
multiplexed with the upper address byte (A15:8).
Address Latch Enable. ALE signals the start of an external
bus cycle and indicates that valid address information is
available on lines A15:8 and AD7:0. An external latch can use
ALE to demultiplex the address from the address/data bus.
—
AVCC
PWR Analog VCC. A separate VCC input for the phase-locked loop
—
circuitry.
CEX2:0
CEX3
CEX4
I/O
I/O
Programmable Counter Array (PCA) Input/Output Pins.
These are input signals for the PCA capture mode and output
signals for the PCA compare mode and PCA PWM mode.
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
D
M0, DP0
USB Port 0. DP0 and DM0 are the data plus and data minus
lines of USB port 0, the upstream differential port. These lines
do not have internal pullup resistors. Provide an external 1.5
KΩ pullup resistor at DP0 to indicate the connection of a
fullspeed device.
—
NOTE:
D
P0 low and DM0 low signals an SE0 (USB reset),
causing the 8x930Hx to stay in reset.
D
D
D
D
M1, DP1
M2, DP2
M3, DP3
M5, DP5
I/O
USB Ports 1, 2, 3, and 5. DP1, DP2, DP3, DM1, DM2, DM3, DM5,
and DP5 are the data plus and data minus lines of USB ports 1,
2, 3, and 5, the four downstream differential ports. These lines
have no internal pulldown resistors. Provide an external 15 KΩ
pulldown resistor at each of these pins. (See “Unused
Downstream Ports” on page 33.)
—
12
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 10. Signal Description (Sheet 2 of 4)
Alternate
Signal
Name
Type
Description
Function
EA#
I
External Access. Directs program memory accesses to on-
chip or off-chip code memory. When EA# is connected to
ground, all program memory accesses are off-chip. When EA#
is connected to VCC, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise, the
access is off-chip. The value of EA# is latched at reset. For
devices without on-chip ROM, EA# must be connected to
ground.
—
ECAP
I
External Capacitor. Connect a 1 µF or larger capacitor
between this pin and VSS to ensure proper operation of the
differential line drivers.
—
ECI
I
I
PCA External Clock Input. External clock input to the 16-bit
PCA timer.
P1.2
INT1:0#
External Interrupts 0 and 1. These inputs set the IE1:0
interrupt flags in the TCON register. Bits IT1:0 in TCON select
the triggering method: edge-triggered (high-to-low) or level
triggered (active low). INT1:0 also serves as external run
control for timer1:0 when selected by GATE1:0# in TCON.
P3.3:2
OVRI#
P0.7:0
I
Overcurrent Sense. Senses input to indicate an overcurrent
condition for a bus-powered USB device on an external
downstream port. Active low.
—
I/O
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
Port 1. This is an 8-bit, bidirectional I/O port with internal pull-
ups.
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O
I/O
Port 2. An 8-bit, bidirectional I/O port with internal pull-ups.
Port 3. An 8-bit, bidirectional I/O port with internal pull-ups.
A15:8
P3.0
RXD
P3.1
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
P3.7
RD#/A16
PLLSEL2:0
PSEN#
I
Phase-locked Loop Select. Three-bit code selects USB data
rate (see Table 13 on page 17).
—
O
Program Store Enable. Read signal output. Asserted for the
memory address range determined by bits RD1:0 in configu-
ration byte UCONFIG0 (see RD# and Table 11).
—
RD#
O
Read. Read signal output to external data memory. Asserted
only for RD1:0 = 11. See configuration byte UCONFIG0. (Also
see PSEN# and Table 11).
P3.7/A16
ADVANCE INFORMATION
13
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 10. Signal Description (Sheet 3 of 4)
Signal
Alternate
Function
Type
Description
Name
RST
I
Reset. Reset input to the chip. Holding this pin high for 64
oscillator periods while the oscillator is running resets the
device. The port pins are driven to their reset conditions when a
voltage greater than VIH1 is applied, whether or not the
oscillator is running. This pin has an internal pulldown resistor;
connecting a capacitor between this pin and Vcc implements
power-on reset.
—
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
RXD
I/O
O
Receive Serial Data. RXD sends and receives data in serial
I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.
P3.0
—
SOF#
Start of Frame. Start of frame pulse. Active low. Asserted for 8
states (see Table 13) when frame timer is locked to USB frame
timing and when SOF token or artificial SOF is detected.
T1:0
T2
I
Timer 1:0 External Clock Input. When timer 1:0 operates as a P3.5:4
counter, a falling edge on the T1:0 pin increments the count.
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode,
this signal is the external clock input. For the clock-out mode, it
is the timer 2 clock output.
P1.0
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge P1.1
initiates a capture of the timer 2 registers. In auto-reload mode,
a falling edge causes the timer 2 registers to be reloaded. In the
up-down counter mode, this signal determines the count
direction: 1 = up, 0 = down.
TXD
O
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O
mode 0 and transmits serial data in serial I/O modes 1, 2, and
3.
P3.1
UPWEN#
USB Power Enable. A low signal on this pin applies power to
—
all three external downstream ports.
VCC
PWR Supply Voltage. Connect this pin to the +5V supply voltage.
—
—
VCCP
PWR Supply Voltage for I/O Buffers. Connect this pin to the +5V
supply voltage.
VSS
GND Circuit Ground. Connect this pin to ground.
—
VSSP
GND Circuit Ground for I/O Buffers. Connect this pin to ground.
—
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is
enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at
S:A7H. During bus cycles, the external memory system can
signal ‘system ready’ to the microcontroller in real time by
controlling the WAIT# input signal on the port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at
port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1
(RTWCE) bit at S:A7H. When enabled, the WCLK output
produces a square wave signal with a period of TCLK.
P1.7/CEX4/A17
14
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 10. Signal Description (Sheet 4 of 4)
Alternate
Signal
Name
Type
Description
Function
WR#
O
I
Write. Write signal output to external memory (See Table 11).
P3.6
XTAL1
Oscillator Amplifier Input. When implementing the on-chip
oscillator, connect the external crystal/resonator across XTAL1
and XTAL2. If an external clock source is used, then connect it
to this pin.
—
XTAL2
O
Oscillator Amplifier Output. When implementing the on-chip
oscillator, connect the external crystal/resonator across XTAL1
and XTAL2. If an external oscillator is used, then leave XTAL2
unconnected.
—
Table 11. Memory Signal Selections (RD1:0) †
A17/P1.7/
CEX4/WCLK
RD1:0
A16/P3.7/RD#
PSEN#
WR#
Features
0
0
1
0
1
0
A17
A16
Asserted for
all addresses all memory locations
Asserted for writes to 256-Kbyte external
address space
P1.7/CEX4/WCLK A16
Asserted for Asserted for writes to 128-Kbyte external
all addresses all memory locations address space
P1.7/CEX4/WCLK P3.7 only
Asserted for Asserted for writes to 64-Kbyte external
all addresses all memory locations
address space
One additional port
pin
1
1
P1.7/CEX4/WCLK RD# asserted Asserted for
for addresses addresses
Asserted only for
writes to MCS® 51
microcontroller data
memory locations.
Compatible with MCS
51 microcontrollers.
Separate 64-Kbyte
external program
≤ 7F:FFFFH
≥ 80:0000H
and data memories.
†
RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to Figure 4-3 on page 4-5 in the 8x930Ax,
8x930Hx Universal Serial Bus Micorcontroller User’s Manual.
ADVANCE INFORMATION
15
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
5.0 ADDRESS MAP
Table 12. 8x930Hx Address Map
Internal
Description
Address)
Notes
FF:FFFFH
FF:4000H
External Memory except the top eight bytes (FF:FFF8H – FF:FFFFH) which are
reserved for the configuration array.
1, 2, 3
FF:FFFFH
FF:0000H
External memory or on-chip nonvolatile memory (8 Kbytes FF:0000H –
FF:1FFFH, 16 Kbytes FF:0000H – FF:3FFFH).
2, 4, 5
FE:FFFFH
FE:0000H
External Memory
2
FD:FFFFH
02:0000H
Reserved Addresses
External Memory
6
01:FFFFH
01:0000H
2
00:FFFFH
00:0420H
External Memory
4
00:041FH
00:0080H
On-chip RAM
4
00:007FH
00:0020H
On-chip RAM
7
00:001FH
00:0000H
Storage for R0–R7 of Register File
8, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. Data in this area is accessible by indirect addressing only.
3. Eight addresses at the top of all external memory maps are reserved for current and future device
Configuration Byte information.
4. Data is accessible by direct and indirect addressing.
5. Devices reset into internal or external starting locations depending on the state of EA# and configura-
tion byte information. See EA# signal description in Table 5. See also UCONFIG1:0 bit definitions in
the 8x930Ax, 8x930Hx Universal Serial Bus Micorcontroller User’s Manual.
6. This reserved area returns unspecified values. Software can execute a write to the reserved area, but
nothing is actually written.
7. Data is accessible by direct, indirect, and bit addressing.
8. The special function registers (SFRs) and the register file have separate internal address spaces.
9. Data is accessible by direct, indirect, and register addressing.
16
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS†
NOTICE: This document contains information on
products in the sampling and initial production
phases of development. The specifications are
subject to change without notice. Verify with your
local Intel sales office that you have the latest
datasheet before finalizing a design.
Ambient Temperature Under Bias................... –40°C to +85°C
Storage Temperature .................................. –65°C to +150°C
Voltage on Any Pins to VSS .............................–0.5 V to +6.5 V
IOL per I/O Pin................................................................. 15 mA
Power Dissipation (1) ..................................................... 1.5 W
† WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device
reliability.
OPERATING CONDITIONS†
TA (Ambient Temperature Under Bias):
Commercial........................................................ -0°C to +70°C
VCC / VCCP (Digital Supply Voltage) ................ 4.40 V to 5.25 V
VSS / VSSP............................................................................ 0 V
AVCC (Analog Supply Voltage) ...................... 4.40 V to 5.25 V
FOSC ............................................................................. 12 MHz
NOTE: Maximum power dissipation is based on
package heat-transfer limitations, not device
power consumption.
6.1 Operating Frequencies
Table 13. 8x930Hx Operating Frequency
Internal
Frequency
for CPU
and
XTAL1
Clocks
per
XTAL1
Frequency
PLLSEL2:0
USB Rate
(2)
Pin 43, 42, 44
Comments
(FOSC
)
State
(1)
Peripherals
(TOSC/state)
(3)
(5)
(1/TCLK
)
110
12 MHz
12 Mbps
12 MHz (4)
1
PLL On
(Full Speed)
NOTES:
1. Other PLLSELx combinations are not valid.
2. The sampling rate is four times the USB rate.
3. The AC timing specification (Table 16) defines the following symbol: CPU frequency
= FCLK = 1/TCLK
.
4. The 8x930Hx CPU and peripheral frequency is 3 MHz (low clock mode) until the LC
bit in PCON is cleared by user firmware.
5. When the CPU is operating in low clock mode (3 MHz), 1 state equals 4 Tosc.
ADVANCE INFORMATION
17
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.2 DC Characteristics
Table 14. DC Characteristics at Operating Conditions (Sheet 1 of 2)
(1)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VIL
Input Low Voltage
(except EA#)
–0.5
0.2 VCC – 0.1
V
VIL1
VIH
Input Low Voltage
(EA#)
0
0.2 VCC – 0.3
VCC + 0.5
V
V
V
V
Input High Voltage
(except XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Input High Voltage
(XTAL1, RST)
VCC + 0.5
Output Low Voltage
(port 1, 2, 3)
0.3
0.45
1.0
I
OL = 100 µA (2) (3)
IOL = 1.6 mA
IOL = 3.5 mA
VOL1
VOH
VOH1
IIL
Output Low Voltage
(port 0, ALE, PSEN#,
SOF#)
0.3
0.45
1.0
V
V
I
OL = 200 µA (2) (3)
IOL = 3.2 mA
OL = 7.0 mA
I
Output High Voltage
(port 1, 2, 3, ALE,
PSEN#, SOF#)
V
V
V
CC – 0.3
CC – 0.7
CC – 1.5
IOH = –10 µA (4)
IOH = –30 µA
I
OH = –60 µA
Output High Voltage
(port 0 in external
address space)
V
V
V
CC – 0.3
CC – 0.7
CC – 1.5
V
IOH = –200 µA (4)
IOH = –3.2 mA
I
OH = –7.0 mA
Logical 0 Input
Current
–150
µA
VIN = 0.45 V
(port 1,2,3)
ILI
Input Leakage Current
(port 0)
±10
µA
µA
0.45 < VIN < VCC
VIN = 2.0 V
ITL
Logical 1-to-0
Transition Current
(Port 1, 2,3)
-650
RRST
CIO
RST Pulldown
Resistor
40
225
KΩ
10
pF
FOSC = 12 MHz
TA = 25°C
IPD
Powerdown Current
µA
25
75
Normal powerdown
USB suspend
145
175
18
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 14. DC Characteristics at Operating Conditions (Sheet 2 of 2)
(1)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
IDL
Idle Mode ICC
60
mA Full speed
(in low clock mode)
PLLSEL2:0 = 110
CLK = 3 MHz
F
110
Full speed
(not in low clock
mode)
PLLSEL2:0 = 110
F
CLK = 12 MHz
mA Full speed
(in low clock mode)
PLLSEL2:0 = 110
CLK = 3 MHz
ICC
Active Current
75
F
170
Full speed
(not in low clock
mode)
PLLSEL2:0 = 110
F
CLK = 12 MHz
NOTE:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOH per port pin:10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total IOL for all output pins: 71 mA
If IOL exceeds the test conditions, then VOL may exceed the related specification. Pins are not guaran-
teed to sink current greater than the listed test conditions.
3. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive load-
ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-
ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
4. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC specifi-
cation when the address lines are stabilizing.
ADVANCE INFORMATION
19
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.3 Explanation of Timing Symbols
Table 15 defines the timing symbols used in Tables 11 through 14 and the associated timing diagrams. They
have the form TXXYY, where the character pairs represent a signal and its condition. Timing symbols represent
the time between two signal / condition points.
Table 15. AC Timing Symbol Definitions
Character
Signal(s)
A
C
D
L
Address: A17, A16, A15:8, A7:0
Wait Clock (WCLK), External Clock (XTAL1)
Data In: D7:0, RXD
ALE
Q
R
W
X
Y
Data Out: D7:0, RXD
Read: RD#/PSEN#
Write: WR#
TXD
WAIT#
Character
Condition
H
L
High
Low
V
X
Z
Valid, Setup
No Longer Valid, Hold
Floating (low impedance)
20
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4 System Bus AC Characteristics
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall times = 10 ns, FOSC = 12 MHz.
Table 16. AC Characteristics at Operating Conditions (Sheet 1 of 2)
CPU
CPU Frequency (FCLK) Variable
Frequency
Symbol
Parameter
Units
@ 12 MHz
(M, N = 0)
Min
Max
TCLK
1/(CPU Frequency)
83.33
ns
(1) (2)
(Typical)
TLHLL
TAVLL
TLLAX
ALE Pulse Width
34.66
21.66
4
(0.5+M)TCLK – 7
(0.5+M)TCLK – 20
4
ns (4)
ns (4)
ns
ns (5)
ns (5)
ns
Address Valid to ALE Low
Address Hold after ALE Low
RD# or PSEN# Pulse Width
WR# Pulse Width
(3)
TRLRH
73.33
71.33
5
(1+N)TCLK – 10
(1+N)TCLK – 12
5
TWLWH
(3)
TLLRL
ALE Low to RD# or PSEN#
Low
TLHAX
ALE High to Address Hold
40.33
50.33
(1+M)TCLK – 43
ns (4)
ns (5)
(3)
TRLDV
RD# or PSEN# Low to Valid
Data/Instruction In
(1+N)TCLK – 33
(3)
TRHDX
Data/Instruct. Hold After RD#
or PSEN# High
0
0
0
ns
ns
ns
ns
ns
(3)
TRLAZ
RD# or PSEN# Low to
Address Float
0
(3)
TRHDZ1
Instruct. Float After PSEN#
High
10
10
(3)
TRHDZ2
Data Float After RD# or
PSEN# High
83.33
10
TCLK
(3)
TRHLH1
PSEN# High to ALE High
(instruction)
10
(3)
TRHLH2
RD# or PSEN# High to ALE
High (data)
83.33
TCLK
ns
ns
TWHLH
WR# High to ALE High
88.33
98.66
TCLK + 5
TAVDV1
Address (Port 0) Valid to Valid
Data/Instruction In
(2+M+N)TCLK – 68
ns
(4) (5)
NOTES:
1. Refer to Table 13 for CPU frequencies versus XTAL1 frequencies.
2. XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
3. Specifications for PSEN# are identical to those for RD#.
4. M = 0,1 is the extended ALE state.
5. N = 0,1,2,3 is the RD#/PSEN#/WR# wait state.
ADVANCE INFORMATION
21
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 16. AC Characteristics at Operating Conditions (Sheet 2 of 2)
CPU
CPU Frequency (FCLK) Variable
Frequency
Symbol
Parameter
Units
@ 12 MHz
(M, N = 0)
Min
Max
TAVDV2
Address (Port 2) Valid to Valid
Data/Instruction In
118.66
(2+M+N)TCLK – 48
ns
(4) (5)
TAVDV3
Address (Port 2) Valid to Valid
Instruction In
23.33
37.33
37.33
66.33
(1+N)TCLK – 60
ns (5)
ns (4)
ns (4)
ns (4)
(3)
TAVRL
Address Valid to RD# or
PSEN# Low
(1+M)TCLK – 46
(1+M)TCLK – 46
(1+M)TCLK – 17
TAVWL1
TAVWL2
Address (Port 0) Valid to WR#
Low
Address (Port 2) Valid to WR#
Low
TWHQX
Data Hold after WR# High
Data Valid to WR# High
WR# High to Address Hold
28.66
68.33
70.33
0.5 TCLK – 13
(1+N)TCLK –15
TCLK – 13
ns
ns (5)
ns
TQVWH
TWHAX
NOTES:
1. Refer to Table 13 for CPU frequencies versus XTAL1 frequencies.
2. XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
3. Specifications for PSEN# are identical to those for RD#.
4. M = 0,1 is the extended ALE state.
5. N = 0,1,2,3 is the RD#/PSEN#/WR# wait state.
22
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.1 SYSTEM BUS TIMING DIAGRAMS
State 1
State 2
State 1
(next cycle)
ALE
TLHLL
TLLRL
TRHLH1
TRLRH
RD#/PSEN#
TAVLL
TRLDV
TRLAZ
TAVRL
TRHDX
TLLAX
TLHAX
TRHDZ1
P0
A7:0
Instruction In
TAVDV1
A17/A16/P2
A17/A16/A15:8
TAVDV2
A5011-01
Figure 6. 8x930Hx Code Fetch, Nonpage Mode
ADVANCE INFORMATION
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
State 1
State 2
State 3
ALE
TLHLL
TLLRL
TRHLH2
TRLRH
RD#/PSEN#
TAVLL
TAVRL
TRLAZ
TRLDV
TRHDX
TRHDZ2
TLLAX
TLHAX
P0
A7:0
D7:0
TAVDV1
A17/A16/P2
A17/A16/A15:8
TAVDV2
A5025-02
Figure 7. 8x930Hx Data Read, Nonpage Mode
State 1
State 2
State 3
ALE
TLHLL
TWHLH
TWLWH
WR#
TAVLL
TAVWL1
TAVWL2
TLLAX
TWHQX
TLHAX
A7:0
TQVWH
P0
D7:0
TWHAX
A17/A16/P2
A17/A16/A15:8
A5026-02
Figure 8. 8x930Hx Data Write, Nonpage Mode
24
ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Cycle 1, Page Miss
State 2
Cycle 2, Page Hit
State 1
State 1
ALE
TLHLL
TRHLH1
TLLRL
TRLRH
†
RD#/PSEN#
TAVLL
TRLDV
TRLAZ
TAVRL
TRHDX
TLLAX
TLHAX
TRHDZ1
P2
A15:8
Instruction 1 In
TAVDV3
Instruction 2 In
TAVDV1
A17/A16/P0
A17/A16/A7:0
TAVDV2
†
During a sequence of page hits, PSEN# remains low until the end of the last page hit cycle.
A5028-02
Figure 9. 8x930Hx Code Fetch, Page Mode
ADVANCE INFORMATION
25
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
State 1
State 2
State 3
ALE
TLHLL
TLLRL
TRHLH2
TRLRH
RD#/PSEN#
TAVLL
TAVRL
TRLAZ
TRLDV
TRHDX
TRHDZ2
TLLAX
TLHAX
P2
A15:8
D7:0
TAVDV1
A17/A16/P0
A17/A16/A7:0
TAVDV2
A5029-02
Figure 10. 8x930Hx Data Read, Page Mode
State 1
State 2
State 3
ALE
TLHLL
TWHLH
TWLWH
WR#
TAVLL
TAVWL1
TAVWL2
TLLAX
TWHQX
TLHAX
A15:8
TQVWH
P2
D7:0
TWHAX
A17/A16/P0
A17/A16/A7:0
A5030-02
Figure 11. 8x930Hx Data Write, Page Mode
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ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.2 REAL-TIME WAIT STATE FUNCTION AC CHARACTERISTICS
Table 17. Real-time Wait State AC Timing Specifications
F
CLK Variable (1) (2)
Typ
Symbol
Parameter
Units
Min
Max
TCLYV
WCLK Low to WAIT# Setup
0
0.5 TCLK – 13
(0.5+W)TCLK – 13
0.5 TCLK – 13
ns
ns
ns
ns
ns
ns
TCLYX
WAIT# Hold after WCLK Low
PSEN# or RD# Low to WAIT# Setup
WAIT# Hold after PSEN# or RD# Low
WR# Low to WAIT# Setup
(W)TCLK + 5
( 2)
TRLYV
0
TRLYX
(W)TCLK + 5
0
(0.5+W)TCLK – 13
0.5 TCLK – 13
TWLYV
TWLYX
WAIT# Hold after WR# Low
(W)TCLK + 5
(0.5+W)TCLK – 13
NOTES:
1. W is the number of real-time wait states (0, 1, 2, ... highest possible number).
2. The real-time wait function has a critical timing for instruction reads. It is not advisable to use this fea-
ture for instruction reads during page mode.
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27
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.4.3 REAL-TIME WAIT STATE FUNCTION TIMING DIAGRAMS
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN#
stretched
TRLYX max
T
RLYX min
TRLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
A7:0
P2
A15:8
A15:8
A5000-02
Figure 12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State)
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P0
D7:0
A7:0
stretched
stretched
P2
A15:8
A5002-02
Figure 13. External Data Write (Nonpage Mode, Real-time Wait State)
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ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN# stretched
TRLYX max
T
RLYX min
TRLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
A15:8
P0
A7:0
A7:0
A5001-02
Figure 14. External Data Read (Page Mode, Real-time Wait State)
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
P0
A7:0
A5003-02
Figure 15. External Data Write (Page Mode, Real-time Wait State)
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
6.5 AC Characteristics — Synchronous Mode 0
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 16. Serial Port Waveform — Synchronous Mode 0
Table 18. Serial Port Timing — Synchronous Mode 0
Symbol
TXLXL
Parameter
Min
6 TOSC
Max
Units
ns
Serial Port Clock Cycle Time
TQVXH
TXHQX
TXHDX
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
5 TOSC – 133
TOSC – 50
0
ns
ns
ns
TXHDV
5 TOSC – 133
ns
6.6 External Clock Drive
TCLCH
TCHCX
VCC – 0.5
0.7 VCC
TCLCX
0.2 VCC – 0.1
0.45 V
TCHCL
TCLCL
A4119-01
Figure 17. External Clock Drive Waveforms
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ADVANCE INFORMATION
8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
Table 19. External Clock Drive
Symbol
1/TOSC
TCHCX
TCLCX
Parameter
Oscillator Frequency (FOSC
High Time
Min
6
Max
12
Units
MHz
ns
)
0.35 TOSC
0.35 TOSC
0.65 TOSC
0.65 TOSC
10
Low Time
ns
TCLCH
Rise Time
ns
TCHCL
Fall Time
10
ns
6.7 Testing Waveforms
Outputs
Inputs
VCC – 0.5
0.45 V
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 18. AC Testing Input, Output Waveforms
VLOAD + 0.1 V
VLOAD
VOH – 0.1 V
Timing Reference
Points
VOL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 19. Float Waveforms
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
7.0 THERMAL CHARACTERISTICS
8.3 Setting RXFFRC Bit Clears Only
the Oldest Packet in the FIFO
The microcontroller operates over the commercial
temperature range from 0oC to 70oC. All thermal
impedance data (see Table 20) is approximate for
static air conditions at 1 watt of power dissipation.
Values change depending on operating conditions
and application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology. The
Components Quality and Reliability Handbook
(order number 210997) provides quality and
reliability information.
If the receive FIFO is set as a dual packet mode,
then it can receive two packets. Setting RXFFRC (in
RXCON registers) to indicate FIFO Read Complete
will not flush the entire FIFO; it will flush only the
oldest packet. The read marker will be advanced to
the location of the read pointer.
8.4 Series Resistor Requirement for
Impedance Matching
Table 20. Thermal Characteristics
Per USB rev. 1.0 specification (page 111, section
7.1.1.1), the impedance of the differential driver
must be between 29Ω and 44Ω. To match the cable
impedance, a series resistor of 27Ω to 33Ω should
be connected to each USB line; i.e., on DP0 (pin 55)
and on DM0 (pin 54). If the USB line is improperly
terminated or not matched, then signal fidelity will
suffer. This condition can be seen on the oscillo-
scopes as excessive overshoot and undershoot.
This condition can potentially introduce bit errors.
Package Type
θJA
θJC
68-pin PLCC
N/A
N/A
8.0 DESIGN CONSIDERATIONS
8.1 External Bus Timing and
Peripheral Timing Affected by
PLLSEL2:0 Selection
PLLSEL2 (pin 43), PLLSEL1 (pin 42), and PLLSEL0
(pin 44) determine the 8x930Hx internal CPU
operating frequency. See Table 13. Operate the
8x930Hx at full speed by setting PLLSEL2:0 to 110.
8.5 Pullup Resistor Requirement
for 8x930Hx Hub devices
The USB specification requires a pullup resistor to
allow the host to identify which devices are low
speed and which are full speed in order to commu-
nicate at the appropriate data rate. For 8x930Hx
hub devices (12 Mbps), use a 1.5KΩ pullup resistor
(to 3.0 V – 3.6 V) on the DP0 line.
This provides an internal clock frequency of 12 MHz
(FCLK = FOSC) and sets the microcontroller state time
equal to one oscillator period (TOSC).
The CPU operating frequency influences the timing
of all on-chip peripherals. Refer to the 8X930Ax,
8X930Hx Universal Serial Bus Microcontroller
User’s Manual for peripheral timing formulas (refer
to Table 1 on page 1 for ordering information).
8.6 Powerdown Mode Cannot Be
Invoked Before USB Suspend
If the 8x930Hx is put into powerdown mode before
receiving a USB suspend signal from the host, then
8.2 Low Clock Mode Frequency
a
USB resume will not properly wake up the
8x930Hx from powerdown model.
The internal clock FCLK distributed to the CPU and
peripherals is 3 MHz. Peripheral timing and external
bus accesses (including instruction fetch and data
read/write) are affected. Refer to Table 13 for clock
rates.
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8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
8.7 Unused Downstream Ports
10.0 DATASHEET REVISION HISTORY
If the USB downstream ports are not used, it is still
required that the two data lines be pulled low
externally (similar to a disconnect) so that the inputs
are not floating. This will eliminate the possibility of
induced system noise. When migrating from the
8x930HD/HE (3 external downstream port device)
to the 8x930HF/HG (4 external downstream port
device), and the additional USB port is not being
used in the application, DM5 and DP5 will still require
15K external pulldown resistors. Do not leave the
unused port disconnected.
Datasheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before
finalizing a design or ordering devices.
This (-003) revision of the 8x930Hx datasheet
replaces earlier product information. The following
changes were made in this revision:
1. Added
the
8x930HF/HG
4
external
downstream port device.
9.0 8x930Hx ERRATA
The 8x930Hx may contain design defects or errors
known as errata. Characterized errata that may
cause the 8x930Hx’s operational behavior to
deviate
from
published
specifications are
documented in
a
specification update (order
number 272962). Specification updates can be
obtained from your local Intel sales office or from
the World Wide Web (www.intel.com).
ADVANCE INFORMATION
33
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