N83C196KC [INTEL]
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER; 商业/ EXPRESS CHMOS单片机
| 型号： | N83C196KC |
| 厂家： | 
INTEL |
| 描述： | COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER |
| 文件： | 总25页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
87C196KCÐ16 Kbytes of On-Chip OTPROM
83C196KCÐ16 Kbytes ROM
80C196KCÐROMless
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16 and 20 MHz Available
Dynamically Configurable 8-Bit or
16-Bit Buswidth
488 Byte Register RAM
Y
Y
Y
Y
Y
Y
Y
Full Duplex Serial Port
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.4 ms 16 x 16 Multiply (20 MHz)
2.4 ms 32/16 Divide (20 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
High Speed I/O Subsystem
16-Bit Timer
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16-Bit Software Timers
8- or 10-Bit A/D Converter with
Sample/Hold
16-Bit Watchdog Timer
Y
Y
HOLD/HLDA Bus Protocol
Extended Temperature Available
OTPROM One-Time Programmable
Version
The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family.
É
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high performance processor
along with low power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem-
a
perature range of 0 C to 70 C. With the extended (Express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of 40 C to 85 C. Unless otherwise noted, the specifi-
§
§
b
a
§
§
cations are the same for both options.
See the Packaging information for extended temperature designators.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1994
Order Number: 270942-005
8XC196KC/8XC196KC20
270942–1
Figure 1. 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ/WRITE)
270942–45
NOTE:
*RSVÐReserved bits must be
e
0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
2
8XC196KC/8XC196KC20
Table 2. 8XC196KC Memory Map
PROCESS INFORMATION
Description
Address
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliabili-
ty information is available in Intel’s Components
Quality and Reliability Handbook, Order Number
210997.
External Memory or I/O
0FFFFH
06000H
Internal ROM/OTPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
ROM/OTPROM Security Key
203FH
2030H
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
270942–43
CCB
2018H
EXAMPLE: N87C196KC is 68-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Port 3 and Port 4
1FFFH
1FFEH
Figure 3. The 8XC196KC Family Nomenclature
External Memory
1FFDH
0200H
Table 1. Thermal Characteristics
Package
488 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3, 4)
01FFH
0018H
i
i
jc
ja
Type
PLCC
QFP
0017H
0000H
35 C/W
§
13 C/W
§
55 C/W
16 C/W
§
TBD
§
TBD
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
SQFP
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
3
8XC196KC/8XC196KC20
270942–2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
270942–40
Figure 5. S8XC196KC 80-Pin QFP Package
5
8XC196KC/8XC196KC20
270942–44
Figure 6. 80-Pin SQFP Package
6
8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol
Name and Function
V
V
V
Main supply voltage (5V).
Digital circuit ground (0V). There are multiple V pins, all of which must be connected.
CC
SS
SS
Reference voltage for the A/D converter (5V). V
is also the supply voltage to the analog
REF
REF
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
.
V
SS
V
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
PP
XTAL1
Input of the oscillator inverter and of the internal clock generator.
Output of the oscillator inverter.
XTAL2
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET
Reset input and open drain output.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA equal to low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
READY
HSI
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
Port 2
8-bit quasi-bidirectional I/O port.
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Pins 2.6 and 2.7 are quasi-bidirectional.
7
8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
HLDA
BREQ
Bus Hold input requesting control of the bus.
Bus Hold acknowledge output indicating release of the bus.
Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE
PACT
Determines the EPROM programming mode.
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
CPVER
PALE
Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
PROG
PVER
AINC
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly.
Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
8
8XC196KC/8XC196KC20
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 C to 125 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
§
§
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
(1)
Voltage On Any Pin to V ÀÀÀÀÀÀ 0.5V to 7.0V
b
a
SS
Voltage from EA or
a
V
to V or ANGNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13.00V
SS
(2)
PP
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
NOTE:
1. This includes V and EA on ROM or CPU only devices.
PP
2. Power dissipation is based on package heat transfer lim-
itations, not device power consumption.
OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Under Bias Commercial Temp.
Ambient Temperature Under Bias Extended Temp.
Digital Supply Voltage
Min
Max
Units
a
a
T
A
0
70
85
C
§
b
T
A
40
C
§
V
V
4.50
4.00
b
5.50
5.50
a
V
V
CC
Analog Supply Voltage
REF
(1)
V
ANGND
Analog Ground Voltage
V
0.4
V
0.4
SS
SS
F
F
Oscillator Frequency (8XC196KC)
Oscillator Frequency (8XC196KC20)
8
8
16
20
MHz
MHz
OSC
OSC
NOTE:
1. ANGND and V should be nominally at the same potential.
SS
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol
Description
Min
Typ
Max
0.8
a
Units Test Conditions
b
V
V
V
V
V
V
Input Low Voltage
0.5
V
V
V
V
IL
a
Input High Voltage (Note 1)
Input High Voltage on XTAL 1
Input High Voltage on RESET
Hysteresis on RESET
0.2 V
1.0
V
V
V
0.5
IH
CC
CC
a
a
0.7 V
0.5
0.5
IH1
IH2
HYS
OL
CC
CC
CC
2.2
e
5.0V
300
mV
V
CC
e
e
e
Output Low Voltage
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
2.8 mA
7 mA
OL
OL
OL
e a
V
V
Output Low Voltage
in RESET on P2.5 (Note 2)
I
0.4 mA
OL1
OL
0.8
V
b
b
b
e b
e b
e b
Output High Voltage
(Standard Outputs)
V
V
V
0.3
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
OH
CC
OH
OH
OH
0.7
1.5
CC
CC
9
8XC196KC/8XC196KC20
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol
Description
Min
Typ Max Units
Test Conditions
b
b
b
e b
e b
e b
V
Output High Voltage
(Quasi-bidirectional Outputs)
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
10 mA
30 mA
60 mA
OH1
OH1
IL2
CC
OH
OH
OH
CC
CC
b
e
b
1.5V
CC
I
I
Logical 1 Output Current in Reset.
on P2.0. Do not exceed this
or device may enter test modes.
0.8
mA
V
V
IH
e
Logical 0 Input Current in Reset
on P2.0. Maximum current that
must be sunk by external
TBD
mA
V
0.45V
IN
device to ensure test mode entry.
a
e
e
V 2.4V
CC
I
Logical 1 Input Current.
Maximum current that external
device must source to initiate NMI.
200 mA
V
IN
IH1
k
k
k
k
b
g
I
I
I
I
I
I
Input Leakage Current (Std. Inputs)
Input Leakage Current (Port 0)
1 to 0 Transition Current (QBD Pins)
Logical 0 Input Current (QBD Pins)
Ports 3 and 4 in Reset
10
mA
mA
0
0
V
V
V
V
V
V
V
0.3V
LI
IN
CC
g
3
LI1
TL
IL
IN
REF
b
e
e
e
650 mA
2.0V
IN
IN
IN
b
70
70
mA
mA
0.45V
0.45V
b
IL1
CC
e
Active Mode Current in Reset
(8XC196KC)
65
80
17
21
75
mA XTAL1
e
16 MHz
e
e
e
e
e
V
V
V
REF
5.5V
5.5V
5.5V
CC
PP
e
I
I
I
Active Mode Current in Reset
(8XC196KC20)
92
25
30
mA XTAL1
e
20 MHz
e
CC
V
V
V
REF
CC
PP
e
16 MHz
Idle Mode Current (8XC196KC)
mA XTAL1
e
IDLE
IDLE
e
V
V
V
CC
PP
REF
e
Idle Mode Current (8XC196KC20)
mA XTAL1
20 MHz
e
e
e
e
e
e
e
V
V
V
V
V
V
V
V
V
V
5.5V
5.5V
5.5V
CC
CC
CC
CC
PP
PP
PP
REF
e
e
I
I
Powerdown Mode Current
A/D Converter Reference Current
Reset Pullup Resistor
8
2
15
5
mA
mA
X
PD
REF
REF
REF
e
R
6K
65K
10
5.5V, V
4.0V
RST
IN
C
Pin Capacitance (Any Pin to V
)
SS
pF
S
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. Commercial specifications apply to express parts except where noted.
4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
5. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
6. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
7. Maximum current per pin must be externally limited to the following values if V is held above 0.45V or V
is held
OL OH
b
on Output pins: 10 mA
on quasi-bidirectional pins: self limiting
on Standard Output pins: 10 mA
below V
0.7V:
CC
I
I
I
OL
OH
OH
g
8. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.
9. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
I
I
I
: 29 mA
: 29 mA
: 13 mA
I
I
I
is self limiting
: 26 mA
: 11 mA
: 52 mA
: 13 mA
OL
OH
HSO, P2.0, RXD, RESET
P2.5, P2.7, WR, BHE
AD0–AD15
OL
OH
OL
OH
I
I
: 52 mA
OL
: 13 mA
I
OH
RD, ALE, INST–CLKOUT
I
OH
OL
10
8XC196KC/8XC196KC20
270942–17
e
e
c
c
a
a
I
I
I
I
Max
Typ
4.13
3.50
e
Frequency
Frequency
9 mA
9 mA
a
CC
CC
c
c
Max
Typ
1.25
0.88
Frequency 5 mA
a
Frequency 3 mA
IDLE
IDLE
e
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. I and I
CC
vs Frequency
IDLE
AC CHARACTERISTICS
For use over specified operating conditions.
e
e
e
16 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The system must meet these specifications to work with the 80C196KC:
Symbol
Description
Min
Max
Units
ns
Notes
b
OSC
T
T
T
T
T
T
T
T
T
T
T
Address Valid to READY Setup
Non READY Time
2 T
68
AVYV
YLYH
CLYX
LLYX
AVGV
CLGX
AVDV
RLDV
CLDV
RHDZ
RXDX
No upper limit
ns
b
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
0
T
30
ns
(Note 1)
(Note 1)
OSC
b
b
b
T
15
2 T
40
68
ns
OSC
OSC
OSC
2 T
ns
0
ns
b
3 T
55
ns
(Note 2)
(Note 2)
OSC
b
T
T
22
ns
OSC
OSC
b
45
ns
T
ns
OSC
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
e
2. If wait states are used, add 2 T
* N, where N
number of wait states.
OSC
11
8XC196KC/8XC196KC20
AC CHARACTERISTICS (Continued)
For user over specified operating conditions.
e
e
e
16 MHz
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The 80C196KC will meet these specifications:
Symbol
Description
Min
8
Max
Units
MHz
MHz
ns
Notes
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1 (8XC196KC)
Frequency on XTAL1 (8XC196KC20)
16
20
(Note 1)
(Note 1)
XTAL
XTAL
OSC
8
I/F
I/F
(8XC196KC)
62.5
50
125
125
XTAL
XTAL
(8XC196KC20)
ns
OSC
a
a
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
20
110
ns
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
2 T
ns
OSC
b
a
15
15
CLKOUT High Period
T
10
T
15
ns
OSC
OSC
b
a
a
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
5
ns
b
20
ns
4 T
ns
(Note 4)
OSC
b
b
b
b
4
a
ALE High Period
T
T
T
T
10
T
10
ns
OSC
OSC
OSC
OSC
OSC
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
15
35
30
AVLL
LLAX
LLRL
ns
ns
ns
ns
ns
ns
ns
ns
a
a
30
RLCL
RLRH
RHLH
RLAZ
LLWL
CLWL
QVWH
CHWH
WLWH
WHQX
WHLH
WHBX
WHAX
RHBX
RHAX
b
T
5
(Note 4)
(Note 2)
OSC
a
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
OSC
T
25
OSC
a
5
b
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
T
T
10
23
OSC
a
a
0
25
15
b
(Note 4)
(Note 4)
(Note 2)
(Note 3)
(Note 3)
OSC
b
5
ns
ns
ns
ns
ns
ns
ns
ns
b
b
b
b
b
b
b
T
T
T
T
T
T
T
20
25
10
10
30
10
25
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE, INST after WR Rising Edge
AD8–15 HOLD after WR Rising
BHE, INST after RD Rising Edge
AD8–15 HOLD after RD Rising
a
T
15
OSC
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 T
e
number of wait states.
* N, where N
OSC
12
8XC196KC/8XC196KC20
System Bus Timings
270942–18
13
8XC196KC/8XC196KC20
READY Timings (One Wait State)
270942–20
Buswidth Timings
270942–35
14
8XC196KC/8XC196KC20
HOLD/HLDA Timings
Symbol
Description
Min
Max
Units
ns
Notes
a
b
b
T
T
T
T
T
T
T
T
T
T
HOLD Setup
55
15
15
(Note 1)
HVCH
a
a
a
a
a
a
CLKOUT Low to HLDA Low
15
15
15
20
15
15
ns
CLHAL
CLBRL
HALAZ
HALBZ
CLHAH
CLBRH
HAHAX
HAHBV
CLLH
CLKOUT Low to BREQ Low
ns
HLDA Low to Address Float
ns
HLDA Low to BHE, INST, RD, WR Weakly Driven
CLKOUT Low to HLDA High
ns
b
b
b
b
15
15
15
10
ns
CLKOUT Low to BREQ High
ns
HLDA High to Address No Longer Float
HLDA High to BHE, INST, RD, WR Valid
CLKOUT Low to ALE High
ns
a
a
15
15
ns
b
5
ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Description
Min
Max
Units
e
e
e
e
Weak Pullups on ADV, RD,
WR, WRL, BHE
50K
250K
V
5.5V, V
0.45V
2.4
CC
CC
IN
Weak Pulldowns on
ALE, INST
10K
50K
V
5.5V, V
IN
15
8XC196KC/8XC196KC20
270942–36
Maximum Hold Latency
Bus Cycle Type
Internal Execution
1.5 States
2.5 States
4.5 States
16-Bit External Execution
8-Bit External Execution
EXTERNAL CLOCK DRIVE (8XC196KC)
Symbol
1/T
Parameter
Oscillator Frequency
Oscillator Period
High Time
Min
8
Max
16.0
125
Units
MHz
ns
XLXL
T
T
T
T
T
62.5
20
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
20
ns
Rise Time
10
10
ns
Fall Time
ns
16
8XC196KC/8XC196KC20
EXTERNAL CLOCK DRIVE (8XC196KC20)
Symbol
1/T
Parameter
Oscillator Frequency
Oscillator Period
High Time
Min
8
Max
20.0
125
Units
MHz
ns
XLXL
T
T
T
T
T
50
17
17
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
ns
Rise Time
8
8
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270942–21
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270942–41
270942–42
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V . When
SS
NOTE:
*Required if TTL driver used.
Not needed if CMOS driver is used.
e
&
20 pF. When using ceramic
using crystals, C1
C2
resonators, consult manufacturer for recommended cir-
cuitry.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270942–22
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
270942–23
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded V /V Level occurs;
OH OL
e
g
15 mA.
I
/I
OL OH
17
8XC196KC/8XC196KC20
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
HÐ High
Signals:
LÐ ALE/ADV
BRÐ BREQ
AÐ Address
BÐ BHE
LÐ Low
RÐ RD
VÐ Valid
CÐ CLKOUT
DÐ DATA
GÐ Buswidth
HÐ HOLD
HAÐ HLDA
WÐ WR/WRH/WRL
XÐ XTAL1
XÐ No Longer Valid
ZÐ Floating
YÐ READY
QÐ Data Out
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)
Symbol
Parameter
Min
6 T
Max
Units
ns
t
Serial Port Clock Period (BRR 8002H)
T
T
XLXL
OSC
b
a
Serial Port Clock Falling Edge
t
to Rising Edge (BRR 8002H)
4 T
50
50
4 T
2 T
50
50
ns
XLXH
OSC
OSC
e
T
T
Serial Port Clock Period (BRR
Serial Port Clock Falling Edge
8001H)
4 T
ns
ns
XLXL
OSC
b
a
2 T
XLXH
OSC
OSC
e
to Rising Edge (BRR
8001H)
b
b
T
QVXH
T
XHQX
T
XHQV
T
DVXH
T
XHDX
T
XHQZ
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
Last Clock Rising to Output Float
2 T
2 T
50
50
ns
ns
ns
ns
ns
ns
OSC
OSC
a
2 T
50
OSC
a
T
50
OSC
0
1 T
OSC
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)
270942–24
18
8XC196KC/8XC196KC20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V
.
REF
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Commercial Temp.
Ambient Temperature Extended Temp.
Digital Supply Voltage
Min
Max
Units
a
a
T
A
0
70
85
C
C
§
§
b
T
A
40
V
V
4.50
4.00
1.0
5.50
5.50
V
CC
Analog Supply Voltage
V
REF
SAM
CONV
OSC
OSC
(1)
T
T
F
F
Sample Time
ms
ms
(1)
Conversion Time
10
20
Oscillator Frequency (8XC196KC)
Oscillator Frequency (8XC196KC20)
8.0
16.0
20.0
MHz
MHz
8.0
NOTE:
ANGND and V should nominally be at the same potential, 0.00V.
SS
1. The value of AD TIME is selected to meet these specifications.
Ð
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
(1)
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
3
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
0.25 0.5
Full Scale Error
g
0.25 0.5
Zero Offset Error
g
1.0 2.0
g
a
Non-Linearity
0
3
2
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
g
0.1
0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
1, 2
1
b
b
60
60
V
Power Supply Rejection
1
CC
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
750
1.2K
4
b
a
ANGND
0.5
V
0.5
V
5, 6
REF
g
0
3.0
mA
pF
Sampling Capacitor
3
NOTES:
*An ‘‘LSB’’ as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if the pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
19
8XC196KC/8XC196KC20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Commercial Temp.
Ambient Temperature Extended Temp.
Digital Supply Voltage
Min
Max
Units
a
a
T
A
0
70
85
C
§
b
T
A
40
C
§
V
V
4.50
4.00
1.0
7
5.50
5.50
V
CC
Analog Supply Voltage
V
REF
SAM
CONV
OSC
OSC
(1)
T
T
F
F
Sample Time
ms
(1)
Conversion Time
20
ms
Oscillator Frequency (8XC196KC)
Oscillator Frequency (8XC196KC20)
8.0
8.0
16.0
20.0
MHz
MHz
NOTE:
ANGND and V should nominally be at the same potential, 0.00V.
SS
1. The value of AD TIME is selected to meet these specifications.
Ð
8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Resolution
Typical
Minimum
Maximum
Units*
Notes
256
8
256
8
Levels
Bits
g
Absolute Error
0
1
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
g
Full Scale Error
0.5
0.5
Zero Offset Error
g
a
Non-Linearity
0
1
1
1
l
b
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1
g
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.003
0.003
0.003
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
Xs
V
2, 3
2
b
b
60
60
V
Power Supply Rejection
2
CC
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
750
1.2K
4
b
a
V
0.5
V
0.5
5, 6
SS
REF
g
0
3.0
mA
pF
Sampling Capacitor
3
NOTES:
*An ‘‘LSB’’ as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
20
8XC196KC/8XC196KC20
EPROM SPECIFICATIONS
OPERATING CONDITIONS DURING PROGRAMMING
Symbol
Description
Ambient Temperature During Programming
Supply Voltage During Programming
Reference Supply Voltage During Programming
Programming Voltage
Min
20
Max
30
Units
T
C
A
(1)
V
V
V
V
V
4.5
5.5
CC
(1)
V
4.5
5.5
REF
PP
(2)
V
12.25
12.25
6.0
12.75
12.75
8.0
(2)
V
EA Pin Voltage
EA
F
F
F
Oscillator Frequency During Auto and Slave
Mode Programming
MHz
MHz
MHz
OSC
Oscillator Frequency During
Run-Time Programming (8XC196KC)
6.0
6.0
16.0
20.0
OSC
OSC
Oscillator Frequency During
Run-Time Programming (8XC196KC20)
NOTES:
1. V and V
2. V and V must never exceed the maximum specification, or the device may be damaged.
should nominally be at the same voltage during programming.
REF
CC
PP EA
3. V and ANGND should nominally be at the same potential (0V).
SS
e
4. Load capacitance during Auto and Slave Mode programming
150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Reset High to First PALE Low
PALE Pulse Width
Min
1100
50
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
SHLL
LLLH
AVLL
LLAX
PLDV
PHDX
DVPL
PLDX
Address Setup Time
0
Address Hold Time
100
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
50
50
0
Data Hold Time
400
50
(1)
PROG Pulse Width
PLPH
PHLL
LHPL
PHPL
PHIL
ILIH
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
220
220
220
0
240
50
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Valid
ILVH
ILPL
170
220
PHVL
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See
user’s manual for further information.
21
8XC196KC/8XC196KC20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
Units
I
V
Supply Current (When Programming)
PP
100
mA
PP
NOTE:
Do not apply V until V
PP
damaged.
is stable and within specifications and the oscillator/clock has stabilized or the device may be
CC
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270942–27
NOTE:
P3.0 must be high (‘‘1’’)
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
270942–28
NOTE:
P3.0 must be low (‘‘0’’)
22
8XC196KC/8XC196KC20
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
270942–29
4. ONCE Mode Entry. The ONCE mode is entered
on the 8XC196KC by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
8XC196KB TO 8XC196KC DESIGN
CONSIDERATIONS
high by a pullup that is specified by I
Pullup must not be overridden or the 8XC196KC
will enter the ONCE mode.
. This
OH1
1. Memory Map. The 8XC196KC has 512 bytes of
optional
RAM/SFRs
and
an
16K
of
ROM/OTPROM. The extra 256 bytes of RAM will
reside in locations 100H–1FFH and the extra 8K
of ROM/OTPROM will reside in locations
4000H–5FFFH. These locations are external
memory on the 8XC196KB.
5. During the bus HOLD state, the 8XC196KC
weakly holds RD, WR, ALE, BHE and INST in
their inactive states. The 8XC196KB only holds
ALE in its inactive state.
2. The CDE pin on the KB has become a V pin on
SS
the KC to support 16/20 MHz operation.
6. A RESET pulse from the 8XC196KC is 16 states
rather than 4 states as on the 8XC196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
3. EPROM programming. The 8XC196KC has a dif-
ferent programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code in the
8XC196KC User’s Guide.
8XC196KC ERRATA
1. Missed EXTINT on P0.7.
The 80C196KC20 could possibly miss an
EXTINT on P0.7. See techbit MC0893.
2. HSI MODE divide-by-eight.
Ð
Ý
See Faxback 2192.
3. IPD hump.
Ý
See Faxback 2311.
23
8XC196KC/8XC196KC20
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ‘‘H’’, ‘‘L’’ or ‘‘M’’ at the end of the topside tracking number. The
topside tracking number consists of nine characters and is the second line on the top side of the device. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following are differences between the 270942-004 and 270942-005 datasheets:
1. Removed ‘‘Word Addressable Only’’ from Port 3 and 4 in Table 2.
2. Renamed PVAL to CPVER.
3. Removed T
and T
from the waveform diagrams.
LLYV
LLGV
4. Added HSI MODE divide-by-eight and IPD hump to 8XC196KC errata.
Ð
The following are important differences between the 270942-002 and 270942-004 data sheets:
1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed
from the data sheet. The HSI errata is also removed as this is now considered normal operation.
2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete.
3. Added 80-lead SQFP package pinout.
4. Added documentation for CLKOUT disable bit.
5. i for QFP package was changed to 55 C/W from 42 C/W.
§
§
JA
6. i for QFP package was changed to 16 C/W from TBD C/W.
§
§
JC
7. T
8. T
(MIN) in 10-bit mode was changed to 1.0 ms from 3.0 ms.
SAM
SAM
(MIN) in 8-bit mode was changed to 1.0 ms from 2.0 ms.
9. I specification for port 2.0 was renamed I
IL1
.
IL2
b
10. I (MAX) is changed to TBD from
IL2
6 mA.
a a
(MAX) is changed to 200 mA from 100 mA.
11. I
IH1
IH1
e
e
5.5V.
12. I
test condition changes to V
2.4V from V
IN
IN
13. V
is changed to 300 mV from 150 mV.
HYS
14. I (TYP) at 16 MHz is changed to 65 mA from 50 mA.
CC
15. I (MAX) at 16 MHz is changed to 75 mA from 70 mA.
CC
16. I (TYP) at 20 MHz is changed to 80 mA from 60 mA.
CC
17. I (MAX) at 20 MHz is changed to 92 mA from 86 mA.
CC
18. I
19. I
20. I
21. I
(TYP) at 16 MHz is changed to 17 mA from 15 mA.
(MAX) at 16 MHz is changed to 25 mA from 30 mA.
(TYP) at 20 MHz is changed to 21 mA from 15 mA.
(MAX) at 20 MHz is changed to 30 mA from 35 mA.
IDLE
IDLE
IDLE
IDLE
22. I (TYP) at 16 MHz is changed to 8 mA from 15 mA.
PD
23. I (MAX) at 16 MHz is changed to 15 mA from TBD.
PD
24. I (TYP) at 20 MHz is changed to 8 mA from 18 mA.
PD
25. I (MAX) at 20 MHz is changed to 15 mA from TBD.
PD
b
b
50 ns.
26. T
27. T
28. T
29. T
30. T
31. T
(MAX) is changed to T
45 ns from T
OSC
CLDV
OSC
b
b
40 ns.
(MIN) is changed to T
35 ns from T
OSC
LLAX
OSC
b
b
(MIN) is changed to 5 ns from 10 ns.
CHWH
RHAX
HALAZ
HALBZ
b
b
30 ns.
(MIN) is changed to T
25 ns from T
OSC
OSC
a
a
(MAX) is changed to 15 ns from 10 ns.
a
a
(MAX) is changed to 20 ns from 15 ns.
24
8XC196KC/8XC196KC20
a
(MAX) is now specified at 15 ns, was formerly unspecified.
32. T
HAHBV
33. The T
and T
systems designs.
specifications were removed. These specifications are not required in high-speed
LLGV
LLYV
34. Added EXTINT, P0.7 errata to Errata section.
The following are the important differences between the -001 and -002 versions of data sheet 270942.
1. Express and Commercial devices are combined into one data sheet. The Express only data sheet
270794-001 is obsolete.
2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps.
3. Added programming pin function to package drawings and pin descriptions.
a
b
a
4. Changed absolute maximum temperature under bias from 0 C to 70 C to 55 C to 125 C.
§
and I specifications.
§
§
§
5. Replaced V
specification with I
OH2
OH1 IL1
6. Added I
specification for NMI pulldown resistors.
IH1
7. Added maximum hold latency table.
8. Added external oscillator and external clock circuit drawings.
9. Changed Clock Drive T
and T
Min spec to 20 ns.
XLXX
XHXX
10. Fixed Serial Port T
specification.
XLXH
11. Added 8- and 10-bit mode A/D operating conditions tables.
12. Specified operating range for sample and convert times.
13. Added specification for voltage on analog input pin.
14. Put operating conditions for EPROM programming into tabular format.
25
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