NG80L960JF-16 [INTEL]
RISC Microprocessor, 32-Bit, 16.67MHz, CMOS, PQFP132, PLASTIC, QFP-132;
| 型号： | NG80L960JF-16 |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 32-Bit, 16.67MHz, CMOS, PQFP132, PLASTIC, QFP-132 时钟 外围集成电路 装置 |
| 文件： | 总16页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80L960JA/JF Microprocessor
1.0
Electrical Specifications: 80L960JA/JF Processor
Note: This section contains preliminary information on new products in production. The specifications
are subject to change without notice.
1.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
Table 1. Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature
–65°C to +150°C
–65°C to +110°C
–0.5 V to + 4.6 V
Case Temperature Under Bias
Supply Voltage wrt. VSS
Voltage on Other Pins wrt. VSS
–0.5 V to VCC + 0.5 V
1.2
Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 2. 80L960JA/JF Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
Supply Voltage
VCC
80L960JA/JF-25
80L960JA/JF-16
3.0
3.0
3.6
3.6
V
Input Clock Frequency
80L960JA/JF-25
fCLKIN
8
8
25
16.67
MHz
°C
80L960JA/JF-16
Operating Case Temperature
A80L960JA/JF-25 (132 PGA)
A80L960JA/JF-16 (132 PGA)
0
0
100
100
TC
NG80L960JA/JF-25 (132 PQFP)
NG80L960JA/JF-16 (132 PQFP)
0
0
100
100
1.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS pins separately feed the device’s functional
units. Power and ground connections must be made to all 80960Jx processor power and ground
pins. On the circuit board, every VCC pin should connect to a power plane and every VSS pin
should connect to a ground plane. Place liberal decoupling capacitance near the processor, since
the processor can cause transient power surges.
Preliminary Online Information, August 1998
1
80L960JA/JF Microprocessor
Pay special attention to the Test Reset (TRST#) pin. It is essential that the JTAG Boundary Scan
Test Access Port (TAP) controller initializes to a known state whether it will be used or not. If the
JTAG Boundary Scan function will be used, connect a pulldown resistor between the TRST# pin
and VSS. If the JTAG Boundary Scan function will not be used (even for board-level testing),
connect the TRST# pin to VSS. Also, do not connect the TDI, TDO, and TCK pins if the TAP
Controller will not be used.
Pins identified as NC must not be connected in the system.
2
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
1.4
DC Specifications
Table 3. 80L960JA/JF DC Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
Units
Notes
Input Low Voltage
Input High Voltage
-0.3
2.0
0.8
V
V
VIH
VCC + 0.3
0.4
0.2
IOL = 3 mA
OL = 100 µA
VOL
Output Low Voltage
I
2.4
VCC - 0.2
IOH = -3 mA
OH = -100 µA
VOH
Output High Voltage
V
V
V
I
VOLP
Output Ground Bounce
< 0.8
(1,2)
Input Capacitance
PGA
CIN
12
10
pF
pF
pF
f
CLKIN = fMIN (2)
PQFP
I/O or Output
Capacitance
PGA
COUT
fCLKIN = fMIN (2)
12
10
PQFP
CLKIN Capacitance
CCLK
PGA
PQFP
12
10
fCLKIN = fMIN (2)
NOTES:
1. Typical is measured with VCC = 3.3V and temperature = 25 °C.
2. Not tested.
Preliminary Online Information, August 1998
3
80L960JA/JF Microprocessor
Table 4. 80L960JA/JF ICC Characteristics
Symbol
Parameter
Typ
Max
Units
Notes
Input Leakage Current
for each pin except TCK,
TDI, TRST# and TMS
ILI1
± 1
µA
0 ≤ VIN ≤ VCC
Input Leakage Current
for TCK, TDI, TRST# and
TMS
ILI2
ILO
-140
-250
± 1
µA
VIN = 0.45V (1)
Output Leakage Current
µA
0.4 ≤ VOUT ≤ VCC
ICC Active
(Power Supply)
80960JA/JF-25
80960JA/JF-16
284
184
(1,2)
(2,3)
mA
I
CC Active
80960JA/JF-25
80960JA/JF-16
225
165
(2,4)
(2,4)
mA
mA
mA
mA
(Thermal)
ICC Test
Reset mode
80960JA/JF-25
80960JA/JF-16
200
150
(5)
(5)
ICC Test
80960JA/JF-25
80960JA/JF-16
26
16
(5)
(5)
Halt mode
ICC Test
10
(5)
ONCE mode
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 1 “AC Test Load”.
3. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.6V. This parameter is characterized but not tested.
4. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured
with VCC = 3.3V and temperature = 25° C. This parameter is characterized but not tested.
5. ICC Test (Power modes) refers to the ICC values that are tested when the 80960JA/JF is in Reset mode,
Halt mode or ONCE mode with VCC = 3.6V.
4
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
1.5
AC Specifications
The 80960Jx AC timings are based upon device characterization.
Table 5. 80L960JA/JF AC Characteristics (25 MHz) (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
25
MHz
ns
TC
CLKIN Period
40
125
TCS
TCH
TCL
TCR
TCF
CLKIN Period Stability
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
± 250
ps
(1,2)
12
12
ns
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
ns
4
4
ns
ns
2.0 V to 0.8 V (1)
SYNCHRONOUS OUTPUT TIMINGS
Output Valid Delay, Except ALE/
ALE# Inactive
and DT/R#
TOV1
4.0
18
ns
(3)
(4)
TOV2
TOF
Output Valid Delay, DT/R#
Output Float Delay
0.5 TC + 4.0
4.0
0.5 TC +18
16
ns
ns
SYNCHRONOUS INPUT TIMINGS
Input Setup to CLKIN —
AD[31:0], NMI#, XINT[7:0]#
TIS1
TIH1
TIS2
TIH2
TIS3
TIH3
TIS4
TIH4
9
ns
ns
ns
ns
ns
ns
ns
ns
(5)
(5)
(6)
(6)
(7)
(7)
(8)
(8)
Input Hold from CLKIN —
AD[31:0], NMI#, XINT[7:0]#
1
10
1
Input Setup to CLKIN —
RDYRCV# and HOLD
Input Hold from CLKIN —
RDYRCV# and HOLD
Input Setup to CLKIN —
RESET#
8
Input Hold from CLKIN —
RESET#
1
Input Setup to RESET# —
ONCE#, STEST#
8
Input Hold from RESET# —
ONCE#, STEST#
1
NOTE: Refer to Table 6 for note definitions for this table.
Preliminary Online Information, August 1998
5
80L960JA/JF Microprocessor
Table 5. 80L960JA/JF AC Characteristics (25 MHz) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
RELATIVE OUTPUT TIMINGS
TLXL
TLXA
TDXD
ALE/ALE# Width
0.5TC - 7.5
ns
ns
ns
(9)
Address Hold from ALE/ALE#
Inactive
0.5TC - 7.5
0.5TC - 7.5
Equal Loading (9)
Equal Loading (9)
DT/R# Valid to DEN# Active
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
0.5 TF
MHz
ns
TBSCH
TBSCL
TBSCR
TBSCF
TBSIS1
15
15
5
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
ns
ns
5
ns
2.0 V to 0.8 V (1)
Input Setup to TCK — TDI, TMS
4
6
ns
Input Hold from TCK — TDI,
TMS
TBSIH1
ns
TBSOV1
TBSOF1
TDO Valid Delay
TDO Float Delay
3
3
30
36
ns
ns
(1, 10)
(1, 10)
All Outputs (Non-Test) Valid
Delay
TBSOV2
TBSOF2
TBSIS2
TBSIH2
3
3
4
6
35
36
ns
ns
ns
ns
(1, 10)
(1, 10)
All Outputs (Non-Test) Float
Delay
Input Setup to TCK — All Inputs
(Non-Test)
Input Hold from TCK — All Inputs
(Non-Test)
NOTE: Refer to Table 6 for note definitions for this table.
Table 6. Note Definitions for Table 5 “80L960JA/JF AC Characteristics (25 MHz)”
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in Table 5.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE# and STEST must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
6
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
Table 7. 80L960JA/JF AC Characteristics (16 MHz) (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
16.67
MHz
ns
TC
CLKIN Period
60
125
TCS
TCH
TCL
TCR
TCF
CLKIN Period Stability
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
± 250
ps
(1,2)
18
18
ns
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
ns
6
6
ns
ns
2.0 V to 0.8 V (1)
SYNCHRONOUS OUTPUT TIMINGS
Output Valid Delay, Except
ALE/ALE# Inactive and
DT/R#
TOV1
4.0
21
ns
(3)
(4)
TOV2
TOF
Output Valid Delay, DT/R#
Output Float Delay
0.5 TC + 4.0
4.0
0.5 TC +21
19
ns
ns
SYNCHRONOUS INPUT TIMINGS
Input Setup to CLKIN —
AD[31:0], NMI#, XINT[7:0]#
TIS1
TIH1
TIS2
TIH2
TIS3
TIH3
TIS4
TIH4
10
ns
ns
ns
ns
ns
ns
ns
ns
(5)
(5)
(6)
(6)
(7)
(7)
(8)
(8)
Input Hold from CLKIN —
AD[31:0], NMI# XINT[7:0]#
1
11
1
Input Setup to CLKIN —
RDYRCV# and HOLD
Input Hold from CLKIN —
RDYRCV# and HOLD
Input Setup to CLKIN —
RESET#
8
Input Hold from CLKIN —
RESET#
1
Input Setup to RESET# —
ONCE#, STEST
8
Input Hold from RESET# —
ONCE#, STEST
1
RELATIVE OUTPUT TIMINGS
TLXL
TLXA
TDXD
ALE/ALE# Width
0.5TC - 8
ns
ns
ns
(9)
Address Hold from ALE/ALE#
Inactive
0.5TC - 8
0.5TC - 8
Equal Loading (9)
Equal Loading (9)
DT/R# Valid to DEN# Active
NOTE: Refer to Table 8 for note definitions for this table.
Preliminary Online Information, August 1998
7
80L960JA/JF Microprocessor
Table 7. 80L960JA/JF AC Characteristics (16 MHz) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
0.5 TF
MHz
ns
TBSCH
TBSCL
TBSCR
TBSCF
15
15
5
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
ns
ns
5
ns
2.0 V to 0.8 V (1)
Input Setup to TCK — TDI,
TMS
TBSIS1
4
6
ns
ns
Input Hold from TCK — TDI,
TMS
TBSIH1
TBSOV1
TBSOF1
TDO Valid Delay
TDO Float Delay
3
3
30
36
ns
ns
(1, 10)
(1, 10)
All Outputs (Non-Test) Valid
Delay
TBSOV2
TBSOF2
TBSIS2
TBSIH2
3
3
4
6
35
36
ns
ns
ns
ns
(1, 10)
(1, 10)
All Outputs (Non-Test) Float
Delay
Input Setup to TCK — All Inputs
(Non-Test)
Input Hold from TCK — All
Inputs (Non-Test)
NOTE: Refer to Table 8 for note definitions for this table.
Table 8. Note Definitions for Table 7 “80L960JA/JF AC Characteristics (16 MHz)”
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, see Relative Output Timings in Table 7.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE# and STEST must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
1.5.1
AC Test Conditions and Derating Curves
The AC Specifications in Section 1.5, “AC Specifications are tested with the 50 pF load indicated
in Figure 1. Figure 2 shows how timings vary with load capacitance; Figure 3 shows how output
rise and fall times vary with load capacitance.
8
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
Figure 1. AC Test Load
Output Pin
C
= 50 pF for all signals
L
C
L
Figure 2. Output Delay or Hold vs. Load Capacitance
AC Derating Curves
nom +6
nom +4
nom +2
nom
High-to-Low Transitions
Low-to-High Transitions
nom -2
50
100
150
C
(pF)
L
Preliminary Online Information, August 1998
9
80L960JA/JF Microprocessor
Figure 3. Rise and Fall Time Derating
10
8
2.0V to 0.8V Transitions
0.8V to 2.0V Transitions
6
4
2
50
100
150
C
(pF)
L
1.5.2
AC Timing Waveforms
Figure 4. CLKIN Waveform
T
T
CR
CF
2.0V
1.5V
0.8V
T
CH
T
CL
T
C
10
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
Figure 5. Output Delay Waveform for TOV1
1.5V
OV1
1.5V
CLKIN
T
AD[31:0],
ALE (active),
ALE# (active),
ADS#, A[3:2],
1.5V
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DEN#,
BLAST#, LOCK#,
HOLDA, BSTAT, FAIL#
Figure 6. Output Float Waveform for TOF
1.5V
1.5V
CLKIN
T
OF
AD[31:0],
ALE, ALE#
ADS#, A[3:2],
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DT/R#,
DEN#, BLAST#, LOCK#
Figure 7. Input Setup and Hold Waveform for TIS1 and TIH1
1.5V
1.5V
IH1
1.5V
CLKIN
T
T
IS1
AD[31:0]
NMI#
Valid
1.5V
XINT[7:0]#
Preliminary Online Information, August 1998
11
80L960JA/JF Microprocessor
Figure 8. Input Setup and Hold Waveform for TIS2 and TIH2
1.5V
1.5V
1.5V
CLKIN
T
IH2
T
IS2
HOLD,
1.5V
Valid
1.5V
RDYRCV#
Figure 9. Input Setup and Hold Waveform for TIS3 and TIH3
1.5V
1.5V
CLKIN
T
T
IS3
IH3
RESET#
12
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
Figure 10. Input Setup and Hold Waveform for TIS4 and TIH4
RESET#
T
IH4
T
IS4
ONCE#,
STEST#
Valid
Figure 11. Relative Timings Waveform for TLXL and TLXA
T
T /T
w
a
d
1.5V
1.5V
1.5V
CLKIN
T
LXL
ALE
1.5V
Valid
1.5V
1.5V
ALE#
T
LXA
1.5V
AD[31:0]
Valid
Preliminary Online Information, August 1998
13
80L960JA/JF Microprocessor
Figure 12. DT/R# and DEN# Timings Waveform
T
T /T
w d
a
CLKIN
1.5V
1.5V
1.5V
T
OV2
Valid
DT/R#
DEN#
T
DXD
T
OV1
Figure 13. TCK Waveform
T
T
BSCR
BSCF
2.0V
1.5V
0.8V
T
BSCH
T
BSCL
14
Preliminary Online Information, August 1998
80L960JA/JF Microprocessor
Figure 14. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1
1.5V
1.5V
1.5V
TCK
T
T
BSIH1
BSIS1
TMS
TDI
1.5V
Valid
1.5V
Figure 15. Output Delay and Output Float Waveform for TBSOV1 AND TBSOF1
TCK
1.5V
1.5V
1.5V
T
T
BSOV1
BSOF1
Valid
1.5V
TDO
Figure 16. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2
TCK
1.5V
1.5V
1.5V
T
T
BSOF2
BSOV2
Non-Test
Outputs
Valid
1.5V
Preliminary Online Information, August 1998
15
80L960JA/JF Microprocessor
Figure 17. Input Setup and Hold Waveform for TBSIS2 and TBSIH2
TCK
1.5V
1.5V
1.5V
T
T
BSIH2
BSIS2
Non-Test
Inputs
1.5V
Valid
1.5V
16
Preliminary Online Information, August 1998
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