NLXT907PC.E2 [INTEL]
Ethernet Transceiver, 1-Trnsvr, PQCC44,;
| 型号： | NLXT907PC.E2 |
| 厂家： | 
INTEL |
| 描述： | Ethernet Transceiver, 1-Trnsvr, PQCC44, 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总46页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LXT901/907
Universal 10BASE-T and AUI Transceivers
Datasheet
The LXT901 and LXT907 Universal 10BASE-T and AUI Transceivers are designed for IEEE
802.3 physical layer applications. They provide all the active circuitry to interface most standard
IEEE 802.3 controllers to either the 10BASE-T media or Attachment Unit Interface (AUI). In
addition to standard 10 Mbps Ethernet, they also support full-duplex operation at 20 Mbps.
The LXT901 and LXT907 are identical except for the function of one pin. The LXT901 offers
selectable termination impedance to allow the use of either shielded or unshielded twisted-pair
cable. The LXT907 offers a signal quality error (SQE) disable function.
Common LXT901 and LXT907 functions include Manchester encoding/decoding, receiver
squelch and transmit pulse shaping, jabber, link testing, and reversed polity detection/correction.
Integrated filters simplify the design work required for FCC-compliance EMI performance.
Applications
■ Access devices (DSL, Cable Modems, and ■ Telecom Backplane
Set-Top Boxes).
■ Routers/Bridges/Switches/Hubs
■ USB to Ethernet Converters
Product Features
Functional Features
■ Integrated Manchester Encoder/Decoder
■ 10BASE-T Transceiver
Convenience Features
■ Automatic/Manual AUI/RJ-45 Selection
■ Automatic Polarity Correction
■ AUI Transceiver
■ SQE Disable function (LXT907 only)
■ Full-Duplex Capable (20 Mbps)
■ Programmable Impedance Driver (LXT901
only)
Diagnostic Features
■ Four LED Drivers
■ AUI/RJ-45 Loopback
■ Power-Down Mode and four loopback
modes
■ LXT901 available in 64-pin LQFP and 44-
pin PLCC
■ Remote Signaling of Link-Down and
■ LXT907 available in 44-pin PLCC
Jabber conditions
For technical assistance on this product, please call 1-800-628-8686,
or send an e-mail to support@mailbox.intel.com.
Order Number: 249097-002
June 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT901/907 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Contents
Contents
1.0
2.0
Pin Assignments and Signal Descriptions ....................................................................8
Functional Description ..................................................................................................11
2.1
2.2
Controller Compatibility Modes ...........................................................................12
Transmit Function................................................................................................12
2.2.1 Jabber Control Function.........................................................................13
2.2.2 SQE Function.........................................................................................13
2.2.2.1 SQE Disable Function (LXT907 only) .......................................14
2.3
2.4
Receive Function.................................................................................................14
2.3.1 Polarity Reverse Function ......................................................................15
2.3.2 Collision Detection Function...................................................................15
Loopback Functions ............................................................................................16
2.4.1 Standard Twisted-Pair Loopback ...........................................................16
2.4.2 External Loopback..................................................................................16
2.4.3 Forced Twisted-Pair Loopback...............................................................17
2.4.4 AUI Loopback.........................................................................................17
Link Integrity Test Function .................................................................................17
2.5.1 Remote Signaling...................................................................................19
2.5
3.0
Application Information.................................................................................................19
3.1
3.2
3.3
3.4
Twisted-Pair Impedance Matching......................................................................19
Crystal Information ..............................................................................................20
Magnetics Information.........................................................................................21
Typical Applications.............................................................................................21
3.4.1 Auto Port Select with External Loopback Control...................................21
3.4.2 Full-Duplex Support................................................................................24
3.4.3 Dual Network Support - 10Base-T and Token Ring...............................25
3.4.4 Manual Port Select with Link Test Function ...........................................26
3.4.5 Three Media Application.........................................................................28
3.4.6 AUI Encoder/Decoder ONLY..................................................................29
3.4.7 150Ω Shielded Twisted-Pair Only (LXT901 only)...................................30
4.0
Test Specifications.........................................................................................................31
4.1
4.2
4.3
4.4
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figures 17 - 22 ....................................................................................................35
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figures 23 - 28 ....................................................................................................37
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36 ....................................................................................................39
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figures 37 - 42 ....................................................................................................42
5.0
A
Mechanical Specifications.............................................................................................44
Ordering Information .....................................................................................................45
Datasheet
3
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Contents
Figures
1
2
3
4
5
6
7
8
LXT901/907 Block Diagram ..................................................................................7
LXT901/907 Pin Assignments...............................................................................8
LXT901/907 TPO Output Waveform ..................................................................12
Jabber Control Function .....................................................................................13
SQE Function .....................................................................................................14
Collision Detection Function ...............................................................................16
Link Integrity Test Function ................................................................................18
Remote Signaling Link Integrity Pulse Timing ....................................................19
LAN Adapter Board - Auto Port Select with External LPBK Control ..................23
Full-Duplex Operation ........................................................................................24
380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ......25
LAN Adapter Board - Manual Port Select with Link Test Function .....................26
Manual Port Select with Seeq 8005 Controller ..................................................27
Three Media Application ....................................................................................28
AUI Encoder/Decoder Only Application .............................................................29
150 Ω Shielded Twisted-Pair Only Application (LXT901) ...................................30
Mode 1 RCLK/Start-of-Frame Timing ................................................................35
Mode 1 RCLK/End-of-Frame Timing ..................................................................35
Mode 1 Transmit Timing ....................................................................................36
Mode 1 Collision Detect Timing .........................................................................36
Mode 1 COL/CI Output Timing ...........................................................................36
Mode 1 Loopback Timing ...................................................................................36
Mode 2 RCLK/Start-of-Frame Timing ................................................................37
Mode 2 RCLK/End-of-Frame Timing ..................................................................37
Mode 2 Transmit Timing ....................................................................................38
Mode 2 Collision Detect Timing .........................................................................38
Mode 2 COL/CI Output Timing ...........................................................................38
Mode 2 Loopback Timing ...................................................................................38
Mode 3 RCLK/Start-of-Frame Timing (LXT901 only) .........................................39
Mode 3 RCLK/End-of-Frame Timing (LXT901 only) ..........................................39
Mode 3 RCLK/Start-of-Frame Timing (LXT907 only) .........................................40
Mode 3 RCLK/End-of-Frame Timing (LXT907 only) ..........................................40
Mode 3 Transmit Timing ....................................................................................41
Mode 3 Collision Detect Timing .........................................................................41
Mode 3 COL/CI Output Timing ...........................................................................41
Mode 3 Loopback Timing ...................................................................................41
Mode 4 RCLK/Start-of-Frame Timing ................................................................42
Mode 4 RCLK/End-of-Frame Timing ..................................................................42
Mode 4 Transmit Timing ....................................................................................43
Mode 4 Collision Detect Timing .........................................................................43
Mode 4 COL/CI Output Timing ...........................................................................43
Mode 4 Loopback Timing ...................................................................................43
LXT901/907 Package Specifications ..................................................................44
Ordering Information - Sample............................................................................45
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
4
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Contents
Tables
1
2
3
4
5
6
7
8
LXT901/907 Signal Descriptions...........................................................................9
Controller Compatibility Modes ...........................................................................12
Crystal Specifications..........................................................................................20
Suitable Crystals .................................................................................................20
Suitable Magnetics..............................................................................................21
Absolute Maximum Ratings.................................................................................31
Recommended Operating Conditions .................................................................31
I/O Electrical Characteristics ...............................................................................31
AUI Electrical Characteristics..............................................................................32
Twisted-Pair Electrical Characteristics................................................................32
Switching Characteristics ....................................................................................33
RCLK/Start-of-Frame Timing...............................................................................33
RCLK/End-of-Frame Timing................................................................................34
Transmit Timing...................................................................................................34
Collision, COL/CI Output and Loopback Timing..................................................34
Product Information.............................................................................................45
9
10
11
12
13
14
15
16
Datasheet
5
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Contents
Revision History
Date
Revision
Page #
Description
20
23
Table 3: Changed Nom frequency from “25.0” to “20.0.”
Added 0.1 µF label to capacitor at bottom of Figure 9 graphic.
Added 0.1 µF label to capacitor at bottom of Figure 10
graphic.
24
25
26
27
Added 0.1 µF label to capacitor at bottom of Figure 11 graphic
Added 0.1 µF label to capacitor at bottom of Figure 12 graphic
Added 0.1 µF label to capacitor at bottom of Figure 13 graphic
June 2001
002
Added 2nd para under “Test Specifications”: Quality &
Reliability issues.
31
Removed “Ambient operating temperature” from Absolute
Maximum Ratings table.
31
45
Added Appendix: Product Ordering Information
6
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 1. LXT901/907 Block Diagram
MD0
MD1
AUTOSEL
PAUI
MODE SELECT LOGIC
Controller Compatibility
Port Select
TWISTED PAIR
INTERFACE
Select:
PLS Only
or
*STP
*(LXT901 only)
LBK
RC
RC
Loopback
Link test
LI
TPOPB
TPOPA
TPONA
TPONB
PLS / MAU
CMOS
TX
AMP
PULSE SHAPER
AND FILTER
TCLK
CLKI
DO
WATCHDOG
TIMER
COLLISION/
POLARITY
DETECT
XTAL
OSC
TPIP
TPIN
RX
SLICER
CLKO
TEN
MANCHESTER
ENCODER
CORRECT
TXD
DROP CABLE
INTERFACE
RLD
+
REMOTE SIGNALING
ECL
TX
AMP
DOP
DON
RJAB
RCMPT
CD
-
SQUELCH / LINK
DETECT
LEDL
LPBK
RXD
DI
CI
MANCHESTER
DECODER
RX
SLICER
DIP
DIN
RCLK
CIP
CIN
COLLISION
RECEIVER
COLLISION LOGIC
COL
LEDR LEDT/PDN
*DSQE
LEDC/FDE
*(LXT907 only)
NTH JAB
PLR
Datasheet
7
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
1.0
Pin Assignments and Signal Descriptions
Figure 2. LXT901/907 Pin Assignments
TPIN
RLD
LI
39
38
37
36
35
34
33
32
31
30
29
7
TPIP
8
DSQE (907) or STP (901)
JAB
9
TPONB
TPONA
VCC2
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
10
11
12
13
14
15
16
17
Rev #
GND2
TPOPA
TPOPB
PLR
Part #
LOT #
FPO #
LXT901/907PC XX
XXXXXX
XXXXXXXX
RJAB
AUTOSEL
48 n/c
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
1
2
3
4
5
6
7
8
RCLK
47
46 CD
RXD
45
44 RCMPT
n/c
42 RBIAS
43
Rev #
n/c
GNDA
41
40
Part #
LOT #
FPO #
LXT901LC XX
XXXXXX
XXXXXXXX
9
39 GND1
10
11
12
13
14
15
16
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
38
37
36
35
34
33
CIN
NTH
MD0
MD1
n/c
8
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 1. LXT901/907 Signal Descriptions
PLCC
LQFP
Symbol
I/O
Description
1
34
-
10
56
9
VCC1
VCC2
VCCA
I
I
I
Power Inputs. Power supply inputs of +5 volts.
(LQFP Only)
2
3
11
12
CIP
CIN
I
I
AUI Collision Pair. Differential input to the AUI transceiver CI circuit. The input is
collision signaling or SQE.
Normal Threshold. Selects normal or reduced threshold.
4
13
NTH
I
When NTH is High, the normal twisted-pair squelch threshold is in effect.
When NTH is Low, the normal twisted-pair squelch threshold is reduced by 4.5 dB.
5
6
14
15
MD0
MD1
I
I
Mode Select 0 (MD0), Mode Select 1 (MD1). Mode select pins determine the
controller compatibility mode in accordance with Table 2.
Remote Link Down. Output goes high to signal to the controller that the remote
port is in link down condition.
7
8
18
19
RLD
LI
O
1
Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
9
21
22
JAB
O
I
Jabber Indicator. Output goes High to indicate Jabber state.
10
TEST
Test. For Intel internal use only. It is recommended to tie this pin High externally.
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
11
12
13
23
24
25
TCLK
TXD
TEN
O
I
Transmit Data. Input signal containing NRZ data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
Transmit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
I
14
15
26
27
CLKO
CLKI
O
I
Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
16
28
COL
O
Collision Detect. Output which drives the collision detect input of the controller.
Automatic Port Select.
When High, automatic port selection is enabled (the 901/907 defaults to the AUI
port only if twisted-pair link integrity = Fail).
17
29
AUTOSEL
I
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
18
19
34
35
LEDR
OD
Transmit LED (LEDT)/Power-Down (PDN). Open drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
LEDT/
PDN
OD
I
If externally pulled Low, the LXT901/907 goes to power-down state.
Link LED. Open drain driver for link integrity indicator. Output is pulled Low during
OD link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and the 901/
907 will transmit link test pulses continuously.
20
36
LEDL
I
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Datasheet
9
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 1. LXT901/907 Signal Descriptions (Continued)
PLCC
LQFP
Symbol
I/O
Description
Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain driver for the
collision indicator pulls Low during collision. LED “On”(i.e., Low output) time is
extended by approximately 100 ms.
LEDC/
FDE
OD
I
21
37
If externally tied Low, the LXT901/907 enables full duplex operation by disabling
the internal twisted-pair loopback and collision detection circuits in anticipation of
external twisted-pair loopback or full duplex operation.
If this pin is not used, tie high or directly to VCC.
Loopback. Enables internal loopback mode.
22
38
LBK
I
Refer to Functional Descriptions for details.
23
33
–
39
55
40
GND1
GND2
GNDA
–
–
–
Ground Returns. Grounds
(LQFP Only)
Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating
circuit bias.
24
25
42
44
RBIAS
I
Remote Compatibility. Output goes High to signal the controller that the remote
port is compatible with the LXT901/LXT907 remote signaling features.
RCMPT
O
26
27
45
46
RXD
CD
O
O
Receive Data. Connect RXD directly to the receive data input of the controller.
Carrier Detect. An output to notify the controller of activity on the network.
Receive Clock. A recovered 10 MHz clock which is synchronous to the received
data. Connect to the controller receive clock input.
28
29
30
47
51
52
RCLK
RJAB
PLR
O
O
O
Remote Jabber. Output goes High to indicate the remote port is in Jabber
condition.
Polarity Reverse. Output goes High to indicate reversed polarity at the twisted-
pair input.
Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B)
to the twisted-pair cable. The outputs are pre-equalized. Each pair must be
shorted together and tied to the transformer with a 24.9Ω 1% series resistor to
match impedance of 100Ω.
31
36
32
35
53
58
54
57
TPOPB
TPONB
TPOPA
TPONA
O
O
O
O
Refer to Figure 16 in the Applications Section for information on 150Ω
configurations.
STP Select (LXT901 only).
STP
When STP is Low, 150Ω termination for shielded twisted-pair is selected.
When STP is High, 100Ω termination for unshielded twisted-pair is selected.
LXT907 is designed for 100Ω UTP termination (not selectable).
37
59
I
I
(LXT901)
Disable SQE (LXT907 only).
When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled.
SQE must be disabled for normal operation in Hub/Switch applications.
LXT901operates with SQE enabled (not selectable).
DSQE
(LXT907)
38
39
61
62
TPIP
TPIN
I
I
Twisted-Pair Receive Pair. A differential input pair from the twisted-pair cable.
Receive filter is integrated on-chip. No external filters are required.
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the
active port.
When PAUI is High, the AUI port is selected.
40
3
PAUI
I
When PAUI is Low, the twisted-pair port is selected.
In Auto Port Select mode, PAUI must be tied to ground.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
10
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 1. LXT901/907 Signal Descriptions (Continued)
PLCC
LQFP
Symbol
I/O
Description
41
42
4
5
DIP
DIN
I
I
AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The
input is Manchester encoded.
43
44
7
8
DOP
DON
O
O
AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable.
The output is Manchester encoded.
1, 2, 6,
16, 17,
20, 30,
31, 32,
33, 41,
43, 48,
49, 50,
60, 63,
64
–
N/C
–
No Connect (Internally tied to ground).
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
2.0
Functional Description
The LXT901/907 Universal 10BASE-T and AUI Transceivers perform the physical layer signaling
(PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification.
They function as PLS-only devices (for use with 10BASE-2 or 10BASE-5 coaxial cable networks),
or as Integrated PLS/MAU devices (for use with 10BASE-T twisted-pair networks). In addition to
standard 10 Mbps operation, they also support full-duplex 20 Mbps operation. Unless otherwise
noted, all the information in this data sheet applies to both the LXT901 and LXT907.
The LXT901/907 interfaces a back-end controller to either an AUI drop cable or a twisted-pair
cable. The controller interface includes transmit and receive clocks and NRZ data channels, as well
as mode control logic and signaling. The AUI interface comprises three circuits: Data Output
(DO), Data Input (DI), and Collision (CI). The twisted-pair interface comprises two circuits:
Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces,
the LXT901/907 contains an internal crystal oscillator and four LED drivers for visual status
reporting.
Functions are defined from the back-end controller side of the interface. The Transmit function
refers to data transmitted by the back-end to the AUI cable (PLS-only mode), or to the twisted-pair
network (Integrated PLS/MAU mode). The Receive function refers to data received by the back-
end from the AUI cable (PLS-only), or from the twisted-pair network (Integrated PLS/MAU
mode). In the integrated PLS/MAU mode, the LXT901/907 performs all required MAU functions
defined by the IEEE 802.3 10BASE–T specification, such as collision detection, link integrity
testing, signal quality error messaging, jabber control, and loopback. In the PLS-only mode, the
LXT901/907 receives incoming signals from the AUI DI circuit with ± 18 ns of jitter and drives the
AUI DO circuit.
Datasheet
11
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.1
Controller Compatibility Modes
The LXT901/907 ia compatible with most industry standard controllers, including devices
produced by Motorola, AMD, Intel, Fujitsu, National Semiconductor, Seeq, and Texas Instruments.
Four different control signal timing and polarity schemes (Modes 1 through 4) are required to
achieve this compatibility. Mode select pins (MD0 and MD1) determine controller compatibility
modes as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for
each mode.
Table 2. Controller Compatibility Modes
Setting
Controller Mode
MD1
MD0
Mode 1
For Motorola 68EN360, MPC860, Advanced Micro Devices AM7990, or compatible
controllers
L o w
L o w
Mode 2
Low
High
H i g h
High
Low
H i g h
For Intel 82596 or compatible controllers1
Mode 3
2
For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)
Mode 4
For National Semiconductor 8390 or compatible controllers (TI TMS380C26)
1. Refer to Intel Application Note 51 when designing with Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
2.2
Transmit Function
The LXT901/907 receives NRZ data from the controller at the TXD input, as shown in Figure 1,
“LXT901/907 Block Diagram” on page 7, and passes it through a Manchester encoder. The
encoded data is then transferred to either the AUI cable (DO circuit) or the twisted-pair network
(TPO circuit). The advanced integrated pulse shaping and filtering network produces the output
signal on TPON and TPOP, as shown in Figure 3. The TPO output is pre-distorted and pre-filtered
to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to
remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters
simplify the design work required for FCC compliant EMI performance. During idle periods, the
LXT901/907 transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated,
PLS/ MAU mode is selected). External resistors control the termination impedance for the
LXT907. External resistors and the STP pin control termination impedance on the LXT901.
Figure 3. LXT901/907 TPO Output Waveform
12
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.2.1
Jabber Control Function
Figure 4 is a state diagram of the LXT901/907 Jabber control function. The on-chip watchdog
timer prevents the DTE from locking into a continuous transmit mode. When a transmission
exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and
activates the JAB pin. Once the LXT901/907 is in the jabber state, the TXD circuit must remain
idle for a period of 250 to 750 ms before it will exit the jabber state.
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle
DO=Active*
XMIT_Max_Timer_Done
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
DO=Active*
Unjab_Timer_Not_Done
2.2.2
SQE Function
In the integrated PLS/MAU mode, the LXT901/907 supports the signal quality error (SQE)
function, as shown in Figure 5 on page 14. After every successful transmission on the 10BASE-T
network when SQE is enabled, the LXT901/907 transmits the SQE signal for 10BT ± 5BT over the
internal CI circuit which is indicated on the COL pin of the device. When using the 10BASE-2 port
of the LXT901/907, the SQE function is determined by the external MAU attached.
Datasheet
13
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.2.2.1
SQE Disable Function (LXT907 only)
SQE must be disabled for normal operation in hub and switch applications. The LXT907 offers an
SQE disable function. The SQE function is disabled when DSQE is set High, and enabled when
DSQE is Low.
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DO=Idle
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done
XMIT=Enable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.3
Receive Function
The LXT901/907 receive function acquires timing and data from the twisted-pair network (the TPI
circuit) or from the AUI (the DI circuit). Valid received signals are passed through the on-chip
filters and Manchester decoder, then output as decoded NRZ data and receive timing on the RXD
and RCLK pins, respectively.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs
falls below 75 percent of the threshold level (unsquelched) for 8 bit times (typical), the LXT901/
907 receive function enters the Idle state. If the polarity of the TPI circuit is reversed, LXT901/
907 detects the polarity reverse and reports it via the PLR output. The LXT901/907 automatically
corrects reversed polarity.
14
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.3.1
Polarity Reverse Function
The LXT901/907 polarity reverse function uses both link pulses and End-of-Frame data to
determine the polarity of the received signal. If Link Integrity Testing is disabled, polarity detection
is based only on received data. A reversed polarity condition is detected when eight opposite
receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed
polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a
correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the
LXT901/907 enters the link fail state and no valid data or link pulses are received within 96 to 128
ms, the polarity is reset to the default non-flipped condition. Polarity correction is always enabled.
2.3.2
Collision Detection Function
The collision detection function operates on the twisted pair side of the interface. For standard
(half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid
signals on both the TPI circuit and the TPO circuit. The LXT901/907 reports collisions to the back-
end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit,
the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 6 is
a state diagram of the LXT901/907 collision detection function. Refer to Test Specifications for
collision detection and COL/CI output timing.
Note: For full-duplex operation on twisted-pair and AUI ports, the collision detection circuitry must be
disabled.)
Datasheet
15
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 6. Collision Detection Function
A
Power On
DO=Active
TPI=Idle
Idle
TPI=Active
XMIT=Enable
Output
Input
DI=TPI
TPO=DO
DI=DO
DO=Active
TPI=Active
DO=Active
TPI=Active
XMIT=Enable
XMIT=Enable
Collision
TPO=DO
DI=TPI
CI=SQE
A
A
DO=Idle+
XMIT=Disable
TPI=Idle
DO=Active
TPI=Idle
DO=Idle
2.4
Loopback Functions
2.4.1
Standard Twisted-Pair Loopback
The LXT901/907 provides the standard loopback function defined by the 10BASE-T specification
for the twisted-pair port. The loopback function operates in conjunction with the transmit function.
Data transmitted by the back-end is internally looped back within the LXT901/907 from the TXD
pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This
standard loopback function is disabled when a data collision occurs, clearing the RXD circuit for
the TPI data. Standard loopback is also disabled during link fail and jabber states. The
LXT901/907 also provides three additional loopback functions.
2.4.2
External Loopback
An external loopback mode, useful for system-level testing, is controlled by the LEDC pin. When
LEDC is tied Low, the LXT901/907 disables the collision detection and internal loopback circuits
to allow external loopback. External loopback mode can be set on either twisted-pair or AUI ports.
16
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.4.3
2.4.4
Forced Twisted-Pair Loopback
“Forced” twisted-pair loopback is controlled by the LBK pin. When the twisted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
2.5
Link Integrity Test Function
Figure 7 on page 18 is a state diagram of the LXT901/907 Link Integrity test function. The link
integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity
testing is enabled when the LI pin is tied High. When enabled, the receiver recognizes link integrity
pulses which are transmitted in the absence of receive traffic. If no serial data stream or link
integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the
transmit and normal loopback functions. The LXT901/907 ignores any link integrity pulse with
interval less than 2 - 7 ms. The LXT901/907 will remain in the link fail state until it detects either a
serial data packet or two or more link integrity pulses.
Datasheet
17
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 7. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
TPI=Active+
(Link_Test_Rcvd=True
Link_Test_Min_Timer_Done)
Link_Loss_Timer_Done
TPI=Idle
Link_Test_Rcvd=False
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
TPI=Active
Link_Test_Rcvd=False
TPI=Idle
TPI=Active
Link_Test_Rcvd=Idle
TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
Link_Test_Rcvd=True)
TPI=Idle
DO=Idle
18
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.5.1
Remote Signaling
The LXT901/907 transmits standard link pulses which meet the IEEE 802.3 10BASE-T
specification. However, the LXT901/907 encodes additional status information into the link pulse
by varying the link pulse timing. This is referred to as remote signaling. Using alternate pulse
intervals, the LXT901/907 can signal three local conditions: link down, jabber, and remote
signaling compatibility. Figure 8 shows the interval variations used to signal local status to the
other end of the line. The LXT901/907 also recognizes these alternate pulse intervals when
received from a remote unit. Remote status conditions are reported to the controller over the RLD,
RJAB and RCMPT output pins.
Figure 8. Remote Signaling Link Integrity Pulse Timing
10
ms
10
ms
10 ms
20 ms
15 ms
15 ms
20 ms
15 ms
20 ms
LI-RLD
(note 1)
10
ms
10
ms
10
ms
20 ms
15 ms
20 ms
15 ms
15 ms
20 ms
LI-RJAB
(note 2)
20
ms
10
ms
10
ms
10
ms
10
ms
10 ms
20 ms
20 ms
20 ms
LI-RCMPT
(note 3)
907F07.VSD
NOTES:
1. For Remote Link-Down (RLD) signaling, the interval between LI pulses increments from 10 ms to 15 ms, and then the cycle
starts over.
2. For Remote Jabber (RJAB) signaling, the interval between LI pulses decrements from 20 ms to 15 ms to 10 ms, and then the
cycle starts over.
3. For Remote Compatibility (RCMPT) signaling, the interval between LI pulses continually switches between 10 ms and 20 ms.
3.0
Application Information
3.1
Twisted-Pair Impedance Matching
Resistors must be installed on each input and output pair to match impedance of the network media
being used. The LXT907 is configured with 100Ω termination for Unshielded Twisted-Pair (UTP).
In this case, the positive and negative sides of both output pairs are shorted together (TPOPA/
TPOPB and TPONA/TPONB) and tied to the transformer through a 24.9Ω 1% series resistor.
Datasheet
19
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
The LXT901 is designed with an STP Select pin that allows the device to match both 100Ω and
150Ω media. A dual resistor combination can be configured to accommodate either line
termination, as shown in Figure 16 on page 30. When 100Ω termination is selected, both A and B
pairs are driven in parallel. When 150Ω termination is selected, the B pair is tri-stated and only the
A pair is driven.
3.2
Crystal Information
Designers should test and validate crystals to system requirements before committing to a specific
component. Crystal specifications for the LXT901/907 are shown in Table 3. Based on limited
evaluation, Table 4 lists some suitable crystals.
Table 3. Crystal Specifications
Parameter
Min
Nom
Max
Units
Frequency
Frequency1 Stability
1. Test condition = -40 - 85oC
–
20.0
–
MHz
ppm
–
–
+/-80
Table 4. Suitable Crystals
Manufacturer
Part Number
MP-1
MP-2
MTRON
20
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.3
Magnetics Information
The LXT901 and LXT907 require a 1:1 ratio for the receive transformer and a 1:√2 ratio for the
transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for both
the transmit and receive transformers. Designers should test and validate magnetics for system
requirements before committing to a specific component. Table 5 lists some suitable magnetics.
Table 5. Suitable Magnetics
Manufacturer
Part Number
23Z128
23Z128SM
PT4069
Fil-Mag
Valor
ST7011
Twisted-Pair
A553-0716
S553-0716
TD42-2006Q
TG42-1406N1
23Z90
Belfuse
HALO
Fil-Mag
Valor
23Z90SM
LT6032
AUI
ST7032
TD01-0756K
TG01-0756N
HALO
3.4
Typical Applications
Figure 9 on page 23 through Figure 16 on page 30 show typical LXT901/907 applications.
3.4.1
Auto Port Select with External Loopback Control
Figure 9 on page 23 is a typical LXT901/907 application. The diagram is arranged to group similar
pins together; it does not represent the actual LXT901/907 pinout. The controller interface pins
(transmit data, clock and enable; receive data and clock; and the collision detect, carrier detect and
loopback control pins) are shown at the top left.
Datasheet
21
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option
pins are tied High. This set-up selects the following options:
• Automatic Port Selection
(PAUI Low and AUTOSEL High)
• Normal Receive Threshold (NTH High)
• Mode 4, compatible with National NS8390 controllers (MD0 High, MD1 High)
• SQE Disabled (DSQE High on LXT907 only)
• 100Ω termination UTP cable (STP High on LXT901 only)
• Link Testing Enabled (LI High)
Status outputs are grouped at lower left. Local status outputs drive LED indicators and remote
status indicators are available as required.
Power and ground pins are shown at the bottom of the diagram. A single power supply is used for
both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses.
The twisted-pair and AUI interfaces are shown at upper and lower right, respectively. Impedance
matching resistors for 100Ω UTP are installed in each I/O pair but no external filters are required.
22
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 9. LAN Adapter Board - Auto Port Select with External LPBK Control
20 pF
20 pF
0.1 µF
20 MHz
CLKI
TXD
2
CLKO
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
RJ45
6
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
NS8390 BACK-END
CONTROLLER
INTERFACE
5
4
3
2
1
3
14
COL
LBK
LOOPBACK
ENABLE
TPONB
TPONA
1 : 2
24.9 Ω 1%
24.9 Ω 1%
11
6
8
PAUI
AUTOSEL
NTH
9
PROGRAMMING
OPTIONS
MD0
TPOPB
TPOPA
MD1
DSQE (907)
STP (901)
LI
RJAB
RLD
RCMPT
REMOTE
STATUS
1
78 Ω
1
16
JAB
9
CIN
LINE STATUS
PLR
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330 330 330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
1 : 1
78 Ω
78 Ω
Green
Red Red Red
DON
5
12
10
DOP
DIN
1 : 1
7
Fuse
8
9
TEST
DIP
12.4 kΩ 1%
+5 V
VCC1
VCC2
RBIAS
+ 12 V
1
GND1 GND2
Chassis
Gnd
0.1 µF
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
23
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.2
Full-Duplex Support
Figure 10 shows the LXT907 with a Texas Instruments 380C24 CommProcessor. The 380C24 is
compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C24 or other full-
duplex-capable controllers, the LXT907 supports full-duplex Ethernet, effectively doubling the
available bandwidth of the network. In this application, the SQE function is enabled (DSQE is tied
Low) and the AUI port is not used.
Figure 10. Full-Duplex Operation
20 pF
20 pF
CLKO
0.1 µF
TMS380C24
20 MHz
4
CLKI
TXD
3
RJ45
6
TXD
1
1 : 1 16
TPIN
TPIP
TXEN
TXC
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
RXC
RXD
CSN
COLL
5
4
3
2
1
3
14
COL
LBK
LPBK
*TEST0
TPONB
TPONA
1N914
1
1 : 2
24.9 Ω 1%
24.9 Ω 1%
11
6
8
LEDC/FDE
OUTSEL0
10 KΩ
9
TPOPB
AUTOSEL
*Open Collector
Driver
TPOPA
NTH
MD0
MD1
4.7 KΩ
PROGRAMMING
OPTIONS
LI
DSQE (907)
CIN
CIP
Half/Full Duplex Selection controlled by TMS380C24 Pins
Test0 and OUTSEL0.
REMOTE
STATUS
RJAB
RLD
1
2
RCMPT
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
JAB
PLR
LINE STATUS
DON
DOP
The TMS380C26 may be substituted for dual network
support of 10BASE-T and Token Ring.
3
330 330
330
PAUI
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
4
LEDR
LEDT/PDN
Red Red
Green
LEDL
DIN
DIP
TEST
12.4 kΩ 1 %
+5 V
VCC1
VCC2
RBIAS
GND2
GND1
2
0.1 µF
24
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.4.3
Dual Network Support - 10Base-T and Token Ring
Figure 11 shows the LXT901/907 with a Texas Instruments 380C26 CommProcessor. The 380C26
is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C26, both the
LXT901/907 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual
network support from a single connector. The LXT901/907 AUI port is not used. The LXT901
STP is High and the LXT907 DSQE is Low.
Figure 11. 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring
From TI TMS38054 Token
Ring Transceiver
To TI TMS38054 Token Ring
Transceiver
20 pF
20 pF
CLKO
0.1 µF
20 MHz
3
CLKI
TXD
380C26
TXD
RJ45
2
1
1 : 1 16
TPIN
TPIP
6
TXE
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
TXC
RXC
5
3
14
RXD
CRS
4
COL
COL
LBK
LBK
3
TPONB
TPONA
1 : 2
11
24.9 Ω 1%
24.9 Ω 1%
6
8
AUTOSEL
NTH
2
9
PROGRAMMING
OPTIONS
MD0
1
TPOPA
TPOPB
MD1
STP (LXT901)
DSQE (LXT907)
LI
RJAB
RLD
RCMPT
JAB
REMOTE
STATUS
CIN
CIP
LINE STATUS
PLR
330
330 330 330
TEST
PAUI
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
LEDC/FDE
LEDR
LEDT/PDN
LEDL
1
Red Red Red
Green
DON
DOP
Additional magnetics and switching logic (not shown)
are required to implement the dual network solution.
2
3
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
DIN
DIP
12.4 kΩ 1%
+5 V
VCC1
VCC2
RBIAS
GND2
1
GND1
0.1 µF
Datasheet
25
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.4
Manual Port Select with Link Test Function
With MD0 tied Low and MD1 tied High, the LXT901/907 logic and framing are set to Mode 3
(compatible with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers). Figure 12 shows
the setup for Fujitsu controllers. Figure 13 on page 27 shows the four inverters required to interface
with the Seeq 8005 controller. As in Figure 9 on page 23, both these Mode 3 applications show the
LI pin tied High, enabling Link Testing; and the STP (LXT901 only) and NTH pins are both tied
High, selecting the standard receiver threshold and 100Ω termination for unshielded twisted-pair
cable. However, in these applications, AUTOSEL is tied Low, allowing external port selection
through the PAUI pin. The remote status outputs are inverted to drive LED indicators.
Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function
20 pF
20 pF
0.1 µF
20 MHz
2
CLKI
TXD
CLKO
RJ45
6
TXD
TEN
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
TCKN
RCKN
RXD
50 Ω
50 Ω
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
5
4
3
2
1
3
14
XCD
XCOL
LBC
COL
LBK
TPONB
TPONA
24.9 Ω 1%
24.9 Ω 1%
11
9
1 :
2
6
8
Port Selection
PAUI
AUTOSEL
NTH
PROGRAMMING
OPTIONS
MD0
TPOPA
TPOPB
MD1
DSQE (907)
STP (901)
330
330
330
LI
RJAB
RLD
RCMPT
JAB
Amber
Amber
Amber
1
78 Ω
16
1
REMOTE & LINE
STATUS
9
CIN
PLR
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
78 Ω
1 : 1
Green
Red
Red
Red
DON
5
12
10
DOP
DIN
78 Ω
1 : 1
7
Fuse
8
9
TEST
DIP
12.4 kΩ
+5 V
VCC1
VCC2
RBIAS
+ 12 V
1 %
1
Chassis
Gnd
GND1 GND2
0.1 µF
1
2
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
26
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 13. Manual Port Select with Seeq 8005 Controller
External
20 MHz
Source
Left Open
CLKO
0.1 µF
2
CLKI
LPBK
CSN
RxD
CLKI
LBK
RJ45
6
1
1 : 1 16
TPIN
TPIP
CD
50 Ω
50 Ω
RXD
RCLK
COL
TEN
TCLK
TXD
8005
RxC
5
4
3
2
1
3
14
COLL
TxEN
TxC
TxD
TPONB
TPONA
1 :
2
24.9 Ω 1%
24.9 Ω 1%
11
9
6
8
PAUI
AUTOSEL
Port Selection
NTH
MD0
MD1
TPOPA
TPOPB
DSQE (907)
STP (901)
LI
330
330
330
RJAB
RLD
Amber
Amber
Amber
1
RCMPT
78 Ω
16
1
REMOTE & LINE
STATUS
JAB
PLR
CIN
9
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
Red
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
78 Ω
1 : 1
Green
Red
Red
DON
5
12
10
TEST
DOP
DIN
78
1 : 1
7
Fuse
8
9
DIP
+5 V
12.4 kΩ 1 %
VCC1
VCC2
RBIAS
+ 12 V
1
Chassis
Gnd
GND1 GND2
0.1 µF
1
2
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
27
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.5
Three Media Application
Figure 14 shows the LXT907 in Mode 2 (compatible with Intel 82596 controllers) with additional
media options for the AUI port. Two transformers are used to couple the AUI port to either a D-
connector or a BNC connector. (A DP8392 coax transceiver with PM6044 power supply is
required to drive the thin coax network through the BNC.)
Figure 14. Three Media Application
L X T 9 0 7
28
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.4.6
AUI Encoder/Decoder ONLY
In Figure 15, the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low
and PAUI is tied High, manually selecting the AUI port. The twisted-pair port is not used. With
MD1 and MD0 both tied Low, the logic and framing are set to Mode 1 (compatible with AMD
AM7990 controllers). The LI pin is tied Low, disabling the link test function. The DSQE pin is also
tied Low, enabling the SQE function on the LXT907. The LBK input controls loop back. A
20 MHz system clock is supplied at CLK1, with CLK0 left open.
Figure 15. AUI Encoder/Decoder Only Application
SYSTEM
CLOCK
Left Open
CLKO
20 MHz
CLKI
TX
TENA
TXD
TEN
TCLK
RCLK
RXD
CD
TCLK
RCLK
AM7990 BACK-END/
CONTROLLER
INTERFACE
RX
RENA
CLSN
LBK
COL
LBK
LOOPBACK
CONTROL
AUTOSEL
1
2
3
4
5
6
7
8
78 Ω
1
16
PAUI
NTH
9
CIN
PROGRAMMING
OPTIONS
MD0
MD1
10
11
12
13
14
15
2
4
15
13
CIP
DSQE (907)
78 Ω
1:1
1:1
DON
LI
RJAB
RLD
RCMPT
JAB
REMOTE
STATUS
5
12
10
DOP
DIN
78 Ω
LINE STATUS
7
PLR
330
330 330 330
Fuse
8
9
LEDC/FDE
LEDR
DIP
GREEN
Red Red Red
LEDT/PDN
LEDL
+ 12 V
Chassis
Gnd
TEST
+5 V
12.4 Ω 1%
VCC1
VCC2
RBIAS
1
GND1 GND2
Bias resistor RBIAS should be located close to the pin and isolated from the other signals.
1
Datasheet
29
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.7
150Ω Shielded Twisted-Pair Only (LXT901 only)
Figure 16 shows the LXT901 in a typical twisted-pair only application. The DTE is connected to a
10BASE-T network through the twisted-pair RJ-45 connector. (The AUI port is not used). With
MD0 tied High and MD1 tied Low, the LXT901 logic and framing are set to Mode 2 (compatible
with Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left
open). The L1 pin externally controls the link test function. The UTP/STP and NTH pins are both
tied Low, selecting the reduced receiver threshold and 150Ω termination for shielded twisted-pair
cable. The switch at LEDT/PDN manually controls the power-down mode.
Figure 16. 150 Ω Shielded Twisted-Pair Only Application (LXT901)
0.1 µF
20 MHz
SYSTEM
CLOCK
Left Open
2
CLK0
CLK1
TXD
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
RJ45
1
1 : 1 16
TPIN
TPIP
6
TEN
75 Ω
75 Ω
TCLK
RCLK
RXD
82596
5
4
3
2
1
BACK-END/
CONTROLLER
INTERFACE
3
14
RCLK
CD
COL
LBK
75 Ω 1%
TPONB
TPONA
1 :
2
11
9
6
AUTOSEL
PAUI
NTH
37.5 Ω 1%
37.5 Ω 1%
MD0
8
PROGRAMMING
OPTIONS
TPOPA
TPOPB
MD1
STP
75 Ω 1%
LI
Link Test Enable
RJAB
RLD
RCMPT
REMOTE
STATUS
JAB
PLR
LINE STATUS
10K
10K
TEST
LEDC/
FDE
LEDR
LEDL
12.4 kΩ
RBIAS
LEDT/PDN
VCC1
+5 V
1
GND1 GND2
VCC2
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
30
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.0
Test Specifications
Note: Table 6 through Table 15 and Figure 17 through Figure 42 represent the performance specifications
of the LXT901/907. These specifications are guaranteed by test except where noted “by design.”
Minimum and maximum values listed in Table 8 through Table 15 apply over the recommended
operating conditions specified in Table 7.
For all Quality and Reliability issues (for example, parts packaging and thermal specifications),
please send your questions to Intel at the following e-mail address: qr.requests@intel.com.
Table 6. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Supply voltage
VCC
-0.3
-65
6
V
Storage temperature
TSTG
+150
ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Table 7. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage1
VCC
TOP
4.75
0
5.0
5.25
70
V
Recommended operating temperature
–
ºC
1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress
high frequency transients, consistent with good PCB design.
Table 8. I/O Electrical Characteristics
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Input low
voltage2
VIL
–
–
0.8
V
–
Input high
voltage2
VIH
2.0
–
–
V
–
VOL
VOL
–
–
–
–
0.4
10
V
IOL = 1.6 mA
Output low voltage
µ
IOL < 10 A
%VCC
Output low
voltage
(Open drain LED
VOLL
–
–
0.7
%VCC
IOLL = 10 mA
driver)
µ
µ
VOH
VOH
2.4
90
–
–
–
–
V
IOH = 40
IOH < 10
A
A
Output high voltage
%VCC
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Datasheet
31
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 8. I/O Electrical Characteristics (Continued)
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
CMOS
TTL
–
–
–
–
–
–
–
–
–
3
2
3
2
–
12
8
ns
ns
ns
ns
ns
%
CLOAD = 20 pF
Output rise time
TCLK & RCLK
–
CMOS
TTL
–
12
CLOAD= 20 pF
Output fall time
TCLK & RCLK
–
8
–
CLKI rise time (externally driven)
CLKI duty cycle (externally driven)
–
10
–
–
–
50/50
65
40/60
85
ICC
mA
Idle Mode
Transmitting on
twisted-pair
ICC
ICC
ICC
–
–
–
90
70
110
90
2
mA
mA
mA
Normal Mode
Supply current
Transmitting on
AUI
Power-Down
Mode
0.75
–
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Table 9. AUI Electrical Characteristics
1
Parameter
Input Low current
Symbol
Min
Typ
Max
Units
Test Conditions
µ
µ
IIL
IIH
–
–
–
–
–
-700
500
A
A
–
–
–
Input High current
Differential output voltage
VOD
±550
±1200
mV
mV
5 MHz square wave
input
Differential squelch threshold
VDS
150
250
350
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 10. Twisted-Pair Electrical Characteristics
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmit output impedance
ZOUT
–
5
–
Ω
–
0 line length for internal
MAU
Transmit timing jitter addition
–
–
±3.3
±10
ns
After line model
specified by IEEE 802.3
for 10BASE-T internal
MAU
Transmit timing jitter added by
the MAU and PLS sections
–
–
±3.3
±5.5
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
32
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 10. Twisted-Pair Electrical Characteristics (Continued)
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Between TPIP/TPIN,
CIP/CIN & DIP/DIN
Receive input impedance
Normal
ZIN
–
20
–
kΩ
Threshold;
NTH =
High
5 MHz square wave
input
VDS
VDS
300
180
400
250
585
345
mV
mV
Differential
Squelch
Threshold
Reduced
Threshold;
NTH =
5 MHz square wave
input
Low
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 11. Switching Characteristics
1
Parameter
Maximum transmit time
Symbol
Minimum
Typical
Maximum
Units
–
–
–
–
–
–
20
250
50
2
–
–
150
750
150
7
ms
ms
ms
ms
ms
ms
Jabber Timing
Unjab time
Time link loss receive
Link min receive
Link max receive
Link transmit period
–
–
Link Integrity
Timing
50
8
–
150
24
10
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 12. RCLK/Start-of-Frame Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
AUI
tDATA
tDATA
tCD
–
–
900
1200
25
1100
1500
200
550
–
ns
ns
ns
ns
ns
ns
ns
ns
Decoder acquisition time
CD turn-on delay
Twisted-Pair
AUI
–
Twisted-Pair
Mode 1
tCD
–
425
70
tRDS
tRDS
tRDH
tRDH
60
30
10
30
Receive data setup from
RCLK
Modes 2, 3 and 4
Mode 1
45
–
20
–
Receive data hold from
RCLK
Modes 2, 3 and 4
45
–
RCLK shut off delay from CD assert
(LXT907 only; Mode 3)
tsws
–
±90
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Datasheet
33
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 13. RCLK/End-of-Frame Timing
Parameter
RCLK after CD off
Type
Sym
Mode 1
Mode 2
Mode 3
Mode 4
Units
Min
Max
Max
Typ1
tRC
tRD
5
1
27
375
475
–
5
bt
ns
ns
bt
Rcv data throughput delay
400
500
5
375
475
50
375
475
–
2
CD turn off delay
tCDOFF
tIFG
Receive block out after TEN off
RCLK switching delay after CD
off (LXT907 only; Mode 3)
Typ1
tSWE
–
–
120(±80)
–
ns
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last
bit.
Table 14. Transmit Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
TEN setup from TCLK
TXD setup from TCLK
TEN hold after TCLK
TXD hold after TCLK
Transmit start-up delay - AUI
tEHCH
tDSCH
tCHEL
tCHDU
tSTUD
22
22
5
–
–
–
–
ns
ns
ns
ns
ns
–
–
5
–
–
–
220
450
Transmit start-up delay -
Twisted-Pair
tSTUD
tTPD
–
–
–
430
–
450
300
350
ns
ns
ns
Transmit through-put delay -
AUI
Transmit through-put delay -
Twisted-Pair
tTPD
300
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 15. Collision, COL/CI Output and Loopback Timing
1
Parameter
COL turn-on delay
Symbol
Minimum
Typical
Maximum
Units
tCOLD
tCOLOFF
tSQED
tSQEP
tKHEH
tKHEL
–
–
40
420
1.2
1000
25
500
500
1.6
1500
–
ns
ns
COL turn-off delay
µ
s
COL (SQE) Delay after TEN off
COL (SQE) Pulse Duration
LBK setup from TEN
0.65
500
10
ns
ns
ns
LBK hold after TEN
10
0
–
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
34
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.1
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figures 17 - 22
Figure 17. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Figure 18. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
t
RC
RCLK
RXD
1
0
1
0
1
0
1
0
0
Datasheet
35
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 19. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 20. Mode 1 Collision Detect Timing
CI
t
COLOFF
t
COLD
COL
Figure 21. Mode 1 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 22. Mode 1 Loopback Timing
LBK
tKHEH
tKHEL
TEN
36
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.2
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figures 23 - 28
Figure 23. Mode 2 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
CD
tCD
RCLK
tRDS
tRDH
1
tDATA
RXD
1
0
1
0
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 24. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
CD
tCDOFF
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
37
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 25. Mode 2 Transmit Timing
TEN
tEHCH
TCLK
tCHEL
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 26. Mode 2 Collision Detect Timing
CI
tCOLD
tCOLOFF
COL
Figure 27. Mode 2 COL/CI Output Timing
tIFG
TEN
tSQED
COL
tSQEP
Figure 28. Mode 2 Loopback Timing
LBK
tKHEH
tKHEL
TEN
38
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36
Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901 only)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
1
tRDH
1
tDATA
RXD
0
1
0
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 30. Mode 3 RCLK/End-of-Frame Timing (LXT901 only)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
27 bits
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
39
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT907 only)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
Generated from TCLK
tDATA
tRDH
1
RXD
1
0
1
0
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907 only)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
40
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 33. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tCHDU
tDSCH
TXD
TPO
tSTUD
tTPD
Figure 34. Mode 3 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 35. Mode 3 COL/CI Output Timing
TEN
tSQED
tSQEP
COL
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 36. Mode 3 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
41
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
4.4
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figures 37 - 42
Figure 37. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 38. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
t
CDOFF
CD
t
RD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
42
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 39. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
TXD
tDSCH
tCHDU
tTPD
tSTUD
TPO
Figure 40. Mode 4 Collision Detect Timing
CI
t
COLOFF
t
COLD
COL
Figure 41. Mode 4 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 42. Mode 4 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
43
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
LXT901/907 — Universal 10BASE-T and AUI Transceivers
5.0
Mechanical Specifications
Figure 43. LXT901/907 Package Specifications
44-Pin PLCC
64-Pin LQFP
• Part Number LXT901PC and LXT907PC
• Commercial Temp Range (0oC to 70oC)
• Part Number LXT901LC
• Commercial Temp Range (0oC to 70oC)
C
L
D
D1
C
B
E1
E
e
for sides with
even
/
2
e
number of pins
for sides with odd
number of pins
D1
D
θ3
L1
A2
A
D
θ
A2
A1
B
θ3
A
L
A1
F
Inches
Millimeters
Dim
Inches
Millimeters
Min
Max
Min
Max
Dim
Min
Max
Min
Max
A
A1
A2
B
–
0.063
0.006
0.057
.011
–
1.60
0.15
1.45
0.27
A
A1
A2
B
0.165
0.090
0.062
0.050
0.026
0.685
0.650
0.013
0.180
0.120
0.083
–
4.191
2.286
1.575
1.270
0.660
17.399
16.510
0.330
4.572
3.048
2.108
–
0.002
0.053
0.007
0.05
1.35
0.17
D
0.472 BSC
12.00 BSC
C
0.032
0.695
0.656
0.021
0.813
17.653
16.662
0.533
D1
E
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
D
D1
F
E1
e
L
0.018
0.030
0.45
0.75
L1
θ3
θ
0.039 REF
1.00 REF
11o
0o
13o
7o
11o
0o
13o
7o
44
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Universal 10BASE-T and AUI Transceivers — LXT901/907
Appendix A Ordering Information
Table 16. Product Information
Number
Revision
Qualification
Tray MM
Tape & Reel MM
DJLXT901LC.E2
NLXT901PC.E2
NLXT907PC.E2
E2
E2
E2
S
S
S
831686
831657
831666
831803
831813
831822
Figure 44. Ordering Information - Sample
901
L
C
E2
S
E001
DJ
LXT
Build Format
= Tray
= Tape and reel
E000
E001
Qualification
= Pre-production material
= Production material
Q
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
A
C
E
Internal Package Designator
= LQFP
L
= PLCC
= DIP
= PQFP
= QFP with heat spreader
P
N
Q
H
T
= TQFP
= BGA
= TBGA
= HSBGA (BGA with heat slug)
B
E
K
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
= Switching engine
= Formatting device (MAC)
= Network processor
LXT
IXE
IXF
IXP
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HG
S
= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= SOIC
= QFP
GC
N
= TBGA
= PLCC
Datasheet
45
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
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