PA28F004SC-120 [INTEL]
BYTE-WIDE SmartVoltage FlashFile⑩ MEMORY FAMILY 4, 8, AND 16 MBIT; 字节宽SmartVoltage FlashFile⑩ Memory系列4 ，8和16 MBIT
| 型号： | PA28F004SC-120 |
| 厂家： | 
INTEL |
| 描述： | BYTE-WIDE SmartVoltage FlashFile⑩ MEMORY FAMILY 4, 8, AND 16 MBIT |
| 文件： | 总42页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
E
BYTE-WIDE
SmartVoltage FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
SmartVoltage Technology
High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
2.7 V (Read-Only), 3.3 V or 5 V VCC
and 3.3 V, 5 V, or 12 V VPP
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
High-Performance
4, 8 Mbit 85 ns Read Access Time
16 Mbit 95 ns Read Access Time
Extended Cycling Capability
100,000 Block Erase Cycles
Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Low Power Management
Deep Power-Down Mode
Block Write Lockout during Power
Transitions
Automatic Power Savings Mode
Decreases ICC in Static Mode
Enhanced Automated Suspend Options
Program Suspend to Read
Automated Program and Block Erase
Command User Interface
Status Register
Block Erase Suspend to Program
Block Erase Suspend to Read
SRAM-Compatible Write Interface
Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290600-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004SC, 28F008SC, 28F016SC may contain design defects or errors known as errata. Current characterized errata are
available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997
CG-041493
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description...........................6
6.0 ELECTRICAL SPECIFICATIONS..................30
6.1 Absolute Maximum Ratings........................30
6.2 Commercial Temperature Operating
Conditions .................................................30
6.3 Capacitance ...............................................30
2.0 PRINCIPLES OF OPERATION .....................12
6.4 DC Characteristics—Commercial
2.1 Data Protection ..........................................13
Temperature..............................................31
6.5 AC Characteristics—Read-Only
3.0 BUS OPERATION.........................................13
3.1 Read ..........................................................13
3.2 Output Disable ...........................................13
3.3 Standby......................................................13
3.4 Deep Power-Down.....................................13
3.5 Read Identifier Codes Operation................14
3.6 Write ..........................................................14
Operations—Commercial Temperature .....35
6.6 AC Characteristics—Write Operations—
Commercial Temperature..........................37
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance—Commercial
Temperature..............................................39
6.8 Extended Temperature Operating
Conditions .................................................40
6.9 DC Characteristics—Extended
4.0 COMMAND DEFINITIONS ............................14
4.1 Read Array Command................................17
4.2 Read Identifier Codes Command ...............17
4.3 Read Status Register Command................17
4.4 Clear Status Register Command................17
4.5 Block Erase Command ..............................17
4.6 Program Command....................................18
4.7 Block Erase Suspend Command................18
4.8 Program Suspend Command.....................19
4.9 Set Block and Master Lock-Bit Commands 19
4.10 Clear Block Lock-Bits Command..............20
Temperature..............................................40
6.10 AC Characteristics—Read-Only Operations
— Extended Temperature .........................40
7.0 ORDERING INFORMATION..........................41
8.0 ADDITIONAL INFORMATION.......................42
5.0 DESIGN CONSIDERATIONS........................28
5.1 Three-Line Output Control..........................28
5.2 RY/BY# Hardware Detection......................28
5.3 Power Supply Decoupling ..........................28
5.4 VPP Trace on Printed Circuit Boards...........28
5.5 VCC, VPP, RP# Transitions .........................28
5.6 Power-Up/Down Protection........................28
5.7 VPP Program and Erase Voltages on Sub-
0.4µ SC Memory Family............................29
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REVISION HISTORY
Number
-001
Description
Original version
-002
Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP.
Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under ILO Test Conditions, previously read VIN = VCC
or GND, corrected to VOUT = VCC or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
-003
Added µBGA* CSP pinout and corrected error in PSOP pinout.
Added Design Consideration for VPP Program and Erase Voltages on future sub-0.4µ
devices.
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
1.2 Product Overview
1.0 INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit
SmartVoltage FlashFile memory specifications.
Section 1.0 provides a flash memory overview.
Sections 2.0, through 5.0 describe the memory
organization and functionality. Section 6.0 covers
electrical specifications for commercial and
extended temperature product offerings. Section
7.0 contains ordering information. Finally, the byte-
wide SmartVoltage FlashFile memory family
documentation also includes application notes and
design tools which are referenced in Section 8.0.
The byte-wide SmartVoltage FlashFile memory
family provides density upgrades with pinout
compatibility for the 4-, 8-, and 16-Mbit densities.
The 28F004SC, 28F008SC, and 28F016SC are
high-performance
memories
arranged
as
512 Kbyte, 1 Mbyte, and 2 Mbyte of 8 bits. This
data is grouped in eight, sixteen, and thirty-two
64-Kbyte blocks which are individually erasable,
lockable, and unlockable in-system. Figure
illustrates the memory organization.
4
SmartVoltage technology enables fast factory
programming and low-power designs. These
components support read operations at 2.7 V (read-
only), 3.3 V, and 5 V VCC and block erase and
1.1
New Features
program operations at 3.3 V, 5 V, and 12 V VPP
.
The byte-wide SmartVoltage FlashFile memory
family maintains backwards-compatibility with
The 12 V VPP option renders the fastest program
and erase performance which will increase your
factory throughput. With the 3.3 V and 5 V VPP
option, VCC and VPP can be tied together for a
simple and voltage flexible design. This voltage
flexibility is key for removable media that need to
operate in a 3 V to 5 V system. In addition, the
dedicated VPP pin gives complete data protection
Intel’s
28F008SA
and
28F008SA-L.
Key
enhancements include:
•
•
•
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
when VPP ≤ VPPLK
.
They share a compatible status register, software
commands, and pinouts. These similarities enable
Table 1. SmartVoltage Flash
CC and VPP Voltage Combinations
V
a
clean upgrade from the 28F008SA and
28F008SA-L to byte-wide SmartVoltage FlashFile
products. When upgrading, it is important to note
the following differences:
VCC Voltage
VPP Voltage
2.7 V(1)
3.3 V
5 V
3.3 V, 5 V, 12 V
5 V, 12 V
•
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
NOTE:
1. Block erase, program, and lock-bit configuration
•
VPPLK has been lowered from 6.5 V to 1.5 V to
support low VPP voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch VPP off during read
operations should transition VPP to GND.
operation with V , 3.0 V are not supported.
CC
Internal VCC and VPP detection circuitry
automatically configures the device for optimum
performance.
•
To take advantage of SmartVoltage tech-
nology, allow VPP connection to 3.3 V or 5 V.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
For more details see application note AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180).
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
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A block erase operation erases one of the device’s
64-Kbyte blocks typically within second
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
1
(5 V VCC, 12 V VPP), independent of other blocks.
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data from or write data
to any other block.
indicates that the WSM is ready for a new
command, block erase is suspended (and program
is inactive), program is suspended, or the device is
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
Data is programmed in byte increments typically
within 6 µs (5 V VCC, 12 V VPP). A program
suspend operation permits system software to read
data or execute code from any other flash memory
array location.
5 V VCC
.
When CE# and RP# pins are at VCC
,
the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
To protect programmed data, each block can be
locked. This block locking mechanism uses
a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
valid. Likewise, the device has a wake time (tPHEL
)
from RP#-high until writes to the CUI are
recognized.
1.3
Pinout and Pin Description
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package) and
40-bump µBGA* CSP (28F008SC and 28F016SC
only). Pinouts are shown in Figures 2, 3 and 4.
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
DQ - DQ
0
7
Input
Buffer
Output
Buffer
Identifier
Register
I/O Logic
V
CC
CE#
WE#
OE#
RP#
Status
Register
Command
Register
Data
Comparator
4-Mbit:
8-Mbit:
16-Mbit: A - A
A
A
- A
- A
,
,
0
0
0
18
19
20
Y
Input
Buffer
RY/BY#
Y Gating
Write State
Machine
Decoder
Program/Erase
Voltage Switch
V
PP
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
V
GND
Address
Latch
X
CC
Decoder
Address
Counter
Figure 1. Block Diagram
Table 2. Pin Descriptions
Sym
Type
Name and Function
A0–A20
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit → A0–A18
8 Mbit → A0–A19
16 Mbit → A0–A20
DQ0–DQ7 INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CE#
INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP#
INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at VHH enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce
spurious results and should not be attempted.
OE#
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
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PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
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Table 3. Pin Descriptions (Continued)
Sym
WE#
Type
Name and Function
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
RY/BY#
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
VPP
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, programming data, or configuring lock-bits.
SmartVoltage Flash → 3.3 V, 5 V, and 12 V VPP
With VPP ≤ VPPLK, memory contents cannot be altered. Block erase, program, and
lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious
results and should not be attempted.
VCC
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
for optimized read performance. Do not float any power pins.
SmartVoltage Flash → 2.7 V (Read-Only), 3.3 V, and 5 V VCC
With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. Device
operations at invalid VCC voltages (see DC Characteristics) produce spurious
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with VCC < 3.0 V are not supported.
GND
NC
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
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PRELIMINARY
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
28F016SC
28F008SC
28F004SC
A
NC
WE#
OE#
A
A
A
A
A
A
A
A
A
A
A
NC
NC
WE#
OE#
NC
NC
WE#
OE#
20
NC
18
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
19
18
17
16
19
18
17
1
2
3
4
5
6
7
8
A
A
17
A
A
A
A
A
A
16
16
RY/BY#
RY/BY# RY/BY#
DQ
A
15
14
13
12
15
14
13
12
15
A
DQ
7
DQ
14
7
7
A
DQ
DQ
DQ
13
6
6
5
4
6
40-LEAD TSOP
STANDARD PINOUT
10 mm x 20 mm
TOP VIEW
A
DQ
5
12
DQ
DQ
5
4
CE#
CE#
CE#
DQ
DQ
DQ
4
9
V
V
V
V
V
V
V
V
V
CC
CC
PP
CC
CC
CC
PP
CC
PP
10
11
12
13
14
15
16
17
18
19
20
GND
GND
GND
GND
GND
GND
DQ
RP#
A
A
A
A
8
A
A
6
A
5
RP#
A
A
A
A
8
A
A
6
A
5
RP#
A
11
10
9
11
10
9
DQ
DQ
11
3
3
3
A
A
10
9
DQ
2
DQ
2
DQ
2
DQ
DQ
DQ
1
1
1
A
8
DQ
0
DQ
0
DQ
0
A
7
7
7
A
A
A
A
1
A
A
3
0
0
0
A
6
A
5
A
4
A
1
A
1
A
A
2
2
2
A
4
A
4
A
3
A
3
Figure 2. TSOP 40-Lead Pinout
9
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Figure 3. PSOP 44-Lead Pinout
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
8
7
6
5
4
3
2
1
A
B
C
A7
A9
RP#
VPP
VCC
A12
A15
A17
A6
A4
A10
A11
A3
CE#
A8
A13
NC
A14
A16
A18
A20
A5
A19
RY/BY#
D
E
A2
A0
D0
D1
D2
D3
GND
VCC
D4
D5
D6
D7
WE#
OE#
A1
GND
Bottom View - Bump Side Up
Pin #1
Indicator
1
2
3
4
5
6
7
8
A
B
C
A17
A15
A12
VCC
VPP
RP#
A9
A7
A18
A16
RY/BY#
D6
A14
A19
D4
A13
CE#
A8
A11
A3
A10
A5
A6
A4
A2
NC
NC
D
E
WE#
GND
D3
D1
A0
OE#
D7
D5
VCC
GND
D2
D0
A1
Top View - Bump Side Down
This is the view of the package as surface mounted on the board.
Note that the signals are mirror images of bottom view.
NOTES:
1. Figures are not drawn to scale.
2. Address A20 is not included in the 28F008SC.
3. More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4. µBGA* CSP 40-Ball Pinout (28F008SC and 28F016SC)
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2.0 PRINCIPLES OF OPERATION
1FFFFF
The byte-wide SmartVoltage FlashFile memories
1F0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
include an on-chip WSM to manage block erase,
1EFFFF
1E0000
program, and lock-bit configuration functions. It
1DFFFF
allows for: 100% TTL-level control inputs, fixed
1D0000
power supplies during block erasure, program, and
lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
190000
18FFFF
180000
17FFFF
standby, and output disable operations.
170000
16FFFF
160000
Status register and identifier codes can be
15FFFF
accessed through the CUI independent of the VPP
150000
14FFFF
voltage. High voltage on VPP enables successful
140000
block erasure, program, and lock-bit configuration.
13FFFF
All functions associated with altering memory
130000
12FFFF
contents—block
erase,
program,
lock-bit
120000
11FFFF
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
110000
10FFFF
100000
0FFFFF
16-Mbit
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
8-Mbit
8
080000
07FFFF
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or write
data from any other block. Program suspend allows
system software to suspend a program to read data
from any other flash memory array location.
7
070000
06FFFF
6
060000
05FFFF
5
050000
04FFFF
4
040000
03FFFF
4-Mbit
3
030000
02FFFF
2
020000
01FFFF
1
010000
00FFFF
0
000000
Figure 5. Memory Map
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3.2 Output Disable
2.1
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, programs, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ7 are
placed in a high-impedance state.
3.3
Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0–DQ7 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, program, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
When VPP ≤ VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provides pro-
tection from unwanted operations. All write
functions are disabled when VCC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability provides
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode.
3.0 BUS OPERATION
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be held
low for time tPLPH. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
80H.
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1
Read
Block information, identifier codes, or status register
can be read independent of the VPP voltage. RP#
During block erase, program, or lock-bit
configuration, RP#-low will abort the operation.
RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially erased or
written. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be
written.
can be at either VIH or VHH
.
The first task is to write the appropriate read-mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
in and out of the component: CE#, OE#, WE#, and
RP#. CE# and OE# must be driven active to obtain
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ0–DQ7)
control and when active drives the selected
memory data onto the I/O bus. WE# must be at VIH
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
and RP# must be at VIH or VHH. Figure 18
illustrates a read cycle.
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3.5
Read Identifier Codes
Operation
1FFFFF
Block 31
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and master lock
configuration code (see Figure 6). Using the
manufacturer and device codes, the system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
Reserved for
Future Implementation
1F0002
1F0000
Block 31 Lock Configuration
Reserved for
Future Implementation
(Blocks 16 through 30)
0FFFFF
Block 15
Reserved for
Future Implementation
3.6
Write
0F0002
0F0000
Block 15 Lock Configuration
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = VIH. The address and data needed to
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 18 illustrates a write operation.
Reserved for
Future Implementation
(Blocks 8 through 14)
07FFFF
16-Mbit
Block 7
Reserved for
Future Implementation
070002
070000
Block 7 Lock Configuration
4.0 COMMAND DEFINITIONS
Reserved for
Future Implementation
When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, program, and lock-bit
configuration operations.
8-Mbit
(Blocks 2 through 14)
01FFFF
Block 1
Reserved for
Future Implementation
4-Mbit
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
010002
Block 1 Lock Configuration
Reserved for
010000
00FFFF
Future Implementation
Block 0
Reserved For
Future Implementation
000003
000002
000001
000000
Master Lock Configuration
Block 0 Lock Configuration
Device Code
Manufacturer Code
Figure 6. Device Identifier Code Memory Map
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Table 3. Bus Operations
Mode
Notes
RP#
CE#
OE#
WE# Address VPP
DQ0–7 RY/BY#
Read
1,2,3
VIH or
VHH
VIL
VIL
VIH
VIH
X
X
X
X
X
X
X
X
DOUT
High Z
High Z
X
X
X
Output Disable
3
3
4
VIH or
VHH
VIL
VIH
VIH
X
Standby
VIH or
VHH
Deep Power-Down
VIL
X
X
X
X
X
High Z
Note 5
VOH
VOH
Read Identifier Codes
VIH or
VHH
VIL
VIL
VIH
See
Figure 5
Write
3,6,7
VIH or
VHH
VIL
VIH
VIL
X
X
DIN
X
NOTES:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for VPPLK and
PPH1/2/3 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is V
V
OH
when the WSM is not busy, in block erase suspend mode (with program inactive), program suspend mode, or deep power-
down mode.
4. RP# at GND ± 0.2 V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and
V
CC = VCC2/3 (see Section 6.2 for operating conditions).
7. Refer to Table 4 for valid DIN during a write operation.
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Table 4. Command Definitions(9)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Read Array/Reset
Req’d.
Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
1
≥ 2
2
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
4
Read
Read
IA
ID
X
X
SRD
1
X
2
5
BA
PA
Write
Write
BA
PA
D0H
PD
Program
2
5,6
40H
or
10H
Block Erase and Program
Suspend
1
1
5
5
Write
Write
X
X
B0H
Block Erase and Program
Resume
D0H
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
NOTES:
2
2
2
7
7
8
Write
Write
Write
BA
X
60H
60H
60H
Write
Write
Write
BA
X
01H
F1H
D0H
X
X
1. Bus operations are defined in Table 3.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 7 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is V .
IH
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V .
IH
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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4.1
Read Array Command
4.3
Read Status Register
Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or
Program Suspend command. The Read Array
command functions independently of the VPP
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs first. OE# or CE# must
toggle to VIH to update the status register latch. The
Read Status Register command functions
independently of the VPP voltage. RP# can be VIH
voltage and RP# can be VIH or VHH
.
or VHH
.
4.2
Read Identifier Codes
Command
4.4
Clear Status Register
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 5 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 5 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the subsequent information can be read.
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 7). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
Table 5. Identifier Codes
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or program suspend modes.
Code
Address
Data
Manufacturer Code
000000
000001
000001
89
A7
A6
AA
4 Mbit
8 Mbit
Device Code
16 Mbit 000001
4.5
Block Erase Command
Block Lock Configuration
• Block Is Unlocked
• Block Is Locked
XX0002(1)
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command sequence requires appropriate se-
quencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 67). The CPU can
detect block erase completion by analyzing the
RY/BY# pin or status register bit SR.7.
DQ0 = 0
DQ0 = 1
DQ1–7
• Reserved for Future Use
Master Lock Configuration
• Device Is Unlocked
• Device Is Locked
000003
DQ0 = 0
DQ0 = 1
DQ1–7
• Reserved for Future Use
NOTE:
1. X selects the specific block lock configuration code to
be read. See Figure 6 for the Device Identifier Code
Memory Map.
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When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
Successful program also requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = VHH. If program is attempted when the
corresponding block lock-bit is set and RP# = VIH,
program will fail, and SR.1 and SR.4 will be set to
“1.” Program operations with VIH < RP# < VHH
produce spurious results and should not be
attempted.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
4.7
Block Erase Suspend
Command
V
CC = VCC2/3 and VPP = VPPH1/2/3. In the absence of
The Block Erase Suspend command allows
block-erase interruption to read or write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to
this high voltage, block contents are protected
against erasure. If block erase is attempted while
VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.”
Successful block erase requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = VHH. If block erase is attempted when
the corresponding block lock-bit is set and
RP# = VIH, the block erase will fail, and SR.1 and
SR.5 will be set to “1.” Block erase operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
“1”). RY/BY# will also transition to VOH
.
Specification tWHRH2 defines the block erase
suspend latency.
4.6
Program Command
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to VOL. However, SR.6 will remain “1” to
indicate block erase suspend status.
Program is executed by a two-cycle command
sequence. Program setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and write verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
The only other valid commands while block erase is
suspended are Read Status Register and Block
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully write to “0”s. The CUI remains in read
status register mode until it receives another
command.
Erase Resume. After
a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Figure 9). VPP must remain at VPPH1/2/3
(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
VIH or VHH (the same RP# level used for block
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
Reliable programs only occurs when VCC = VCC2/3
and VPP = VPPH1/2/3. In the absence of this high
voltage, memory contents are protected against
programs. If program is attempted while
VPP ≤ VPPLK, the operation will fail, and status
register bits SR.3 and SR.5 will be set to “1.”
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master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit
4.8
Program Suspend Command
command and VHH on the RP# pin. See Table 6 for
summary of hardware and software write
protection options.
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
a
Set block lock-bit and master lock-bit are initiated
using two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address within
the block to be locked) or the set master lock-bit
confirm (and any device address). The WSM then
controls the set lock-bit algorithm. After the
sequence is written, the device automatically
outputs status register data when read (see
Figure 11). The CPU can detect the completion of
the set lock-bit event by analyzing the RY/BY# pin
output or status register bit SR.7.
WSM suspend the program sequence at
a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the program operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to VOH. Specification tWHRH1 defines the
program suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
program is suspended are Read Status Register
and Program Resume. After Program Resume
command is written to the flash memory, the WSM
will continue the program process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Figure 10). VPP must remain at VPPH1/2/3
(the same VPP level used for program) while in
program suspend mode. RP# must also remain at
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations
V
IH or VHH (the same RP# level used for program).
occur only when VCC = VCC2/3 and VPP = VPPH1/2/3
.
In the absence of this high voltage, lock-bit contents
are protected against alteration.
4.9
Set Block and Master Lock-Bit
Commands
A successful set block lock-bit operation requires
that the master lock-bit be cleared or, if the master
lock-bit is set, that RP# = VHH. If it is attempted with
the master lock-bit set and RP# = VIH, the operation
will fail, and SR.1 and SR.4 will be set to “1.” A
successful set master lock-bit operation requires
that RP# = VHH. If it is attempted with RP# = VIH,
the operation will fail, and SR.1 and SR.4 will be set
to “1.” Set block and master lock-bit operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with
RP# = VHH, sets the master lock-bit. After the
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This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when VCC = VCC2/3 and VPP = VPPH1/2/3. If a
clear block lock-bits operation is attempted while
4.10 Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and VHH on the RP# pin. See Table 6 for a
summary of hardware and software write protection
options.
V
PP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” In the
absence of this high voltage, the block lock-bits
content are protected against alteration. A suc-
cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
bit is set, that RP# = VHH. If it is attempted with the
master lock-bit set and RP# = VIH, SR.1 and SR.5
will be set to “1” and the operation will fail. A clear
block lock-bits operation with VIH < RP# < VHH
produce spurious results and should not be
attempted.
Clear block lock-bits operation is initiated using a
two-cycle command sequence.
A clear block
lock-bits setup is written first. Then, the device
automatically outputs status register data when
read (see Figure 12). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
Table 6. Write Protection Alternatives
Block
Master
Operation
Block Erase or
Program
Lock-Bit Lock-Bit
RP#
Effect
0
VIH or VHH Block Erase and Program Enabled
X
1
VIH
Block is Locked. Block Erase and Program Disabled
VHH
Block Lock-Bit Override. Block Erase and Program
Enabled
Set Block
Lock-Bit
0
1
X
X
VIH or VHH Set Block Lock-Bit Enabled
VIH
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH
Master Lock-Bit Override. Set Block Lock-Bit
Enabled
Set Master
Lock-Bit
X
X
VIH
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
VHH
Clear Block
Lock-Bits
0
1
X
X
VIH or VHH Clear Block Lock-Bits Enabled
VIH
Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
VHH
Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
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Table 7. Status Register Definition
WSMS
7
ESS
6
ECLBS
5
PSLBS
4
VPPS
3
PSS
2
DPS
1
R
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
Check RY/BY# or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–0 are invalid while SR.7 = “0.”
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS
STATUS
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in Program or Set Master/Block
Lock-Bit
0 = Successful Program or Set Master/Block
Lock-Bit
SR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.3 does not provide a continuous indication of
V
V
PP level. The WSM interrogates and indicates the
PP level only after a block erase, program, or lock-
bit configuration operation. SR.3 is not guaranteed
to reports accurate feedback only when VPP
VPPH1/2/3
≠
.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or
RP# Lock Detected, Operation Abort
0 = Unlock
SR.1 does not provide a continuous indication of
master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit, and
RP# only after a block erase, program, or lock-bit
configuration operation. It informs the system,
depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or
RP# ≠ VHH
.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.0 is reserved for future use and should be
masked out when polling the status register.
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Start
Bus
Operation
Command
Comments
Write
Erase Setup
Data = 20H
Addr = Within Block to Be Erased
Write 20H,
Block Address
Write
Erase
Data = D0H
Confirm
Addr = Within Block to Be Erased
Write D0H,
Block Address
Read
Status Register Data
Read Status
Register
Suspend Block
Erase Loop
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
0
Suspend
SR.7 =
1
Block Erase
Yes
Repeat for subsequent block erasures.
Full status check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Standby
Check SR.3
1 = V Error Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.1
Standby
1 = Device Protect Detect
RP# = VIH , Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
1
1
SR.1 =
0
Device Protect Error
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
Block Erase
Error
SR.5 =
0
Block Erase
Successful
Figure 7. Automated Block Erase Flowchart
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Start
Bus
Operation
Command
Comments
Setup
Program
Write
Data = 40H
Addr = Location to Be Programmed
Write 40H,
Address
Write
Program
Data = Data to Be Programmed
Addr = Location to Be Programmed
Write Byte
Data and Address
Read
Status Register Data
Read
Status Register
Suspend
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Program Loop
No
0
Suspend
Program
SR.7 =
Yes
Repeat for subsequent byte writes.
SR full status check can be done after each program, or after a
sequence of program operations.
1
Write FFH after the last program operation to reset device to
read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Standby
Check SR.3
1 = V Error Detect
1
PP
V
Range Error
SR.3 =
0
PP
Check SR.1
1 = Device Protect Detect
Standby
Standby
RP# = V , Block Lock-Bit Is Set
IH
Only required for systems
implementing lock-bit configuration
1
Device Protect Error
Program Error
SR.1 =
0
Check SR.4
1 = Program Error
1
SR.4 =
0
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Program Successful
Figure 8. Automated Program Flowchart
23
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Start
Bus
Command
Comments
Operation
Write
Erase
Suspend
Data = B0H
Addr = X
Write B0H
Read
Status Register Data
Addr = X
Read
Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
0
SR.7 =
1
Standby
Write
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Erase
Resume
Data = D0H
Addr = X
SR.6 =
1
Block Erase Completed
Read
Program
Read or
Program
?
Program
Loop
Read Array
Data
No
Done?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
24
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Start
Bus
Operation
Command
Comments
Write
Program
Suspend
Data = B0H
Addr = X
Write B0H
Read
Status Register Data
Addr = X
Read
Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
0
Standby
Check SR.2
1 =Program Suspended
0 = Program Completed
SR.7 =
1
Write
Read
Write
Read Array
Data = FFH
Addr = X
Program Completed
SR.2 =
Read array locations other
than that being data written.
1
Program
Resume
Data = D0H
Addr = X
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
Figure 10. Program Suspend/Resume Flowchart
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E
Start
Bus
Command
Comments
Operation
Set
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Write
Write
Write 60H,
Block/Device Address
Block/Master
Lock-Bit Setup
Set
Data = 01H (Block),
F1H (Master)
Write 01H/F1H,
Block/Device Address
Block or Master
Lock-Bit Confirm Addr = Block Address (Block),
Device Address (Master)
Read
Status Register Data
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
1
Write FFH after the last lock-bit set operation to place device in
read array mode.
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Check SR.3
Standby
1 = V Error Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.1
1 = Device Protect Detect
Standby
RP# = V
,
IH
(Set Master Lock-Bit Operation)
RP# = V , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
HH
1
1
Device Protect Error
SR.1 =
0
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Lock-Bit Reset Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
1
Set Lock-Bit Error
SR.4 =
0
Set Lock-Bit Successful
Figure 11. Set Block and Master Lock-Bit Flowchart
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Start
Bus
Operation
Command
Comments
Data = 60H
Addr = X
Clear Block
Lock-Bits Setup
Write
Write 60H
Data = D0H
Addr = X
Clear Block
Lock-Bits Confirm
Write
Read
Write D0H
Status Register Data
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
1
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Check SR.3
Standby
1 = V Error Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.1
1 = Device Protect Detect
Standby
RP# = V , Master Lock-Bit Is Set
IH
1
1
Check SR.4,5
Both 1 = Command Sequence Error
Device Protect Error
SR.1=
0
Standby
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
Clear Block Lock-Bits
Error
SR.5 =
0
Clear Block Lock-Bits
Successful
Figure 12. Clear Block Lock-Bits Flowchart
27
PRELIMINARY
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5.0 DESIGN CONSIDERATIONS 5.4
5.1 Three-Line Output Control
E
V
Trace on Printed Circuit
PP
Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
Intel provides three control inputs to accommodate
multiple memory connections: CE#, OE#, and RP#.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.5
V
, V , RP# Transitions
CC PP
Block erase, program and lock-bit configuration are
not guaranteed if VPP or VCC fall outside of a valid
voltage range (VCC2/3 and VPPH1/2/3) or RP# ≠ VIH or
V
HH. If VPP error is detected, status register bit
SR.3 is set to “1” along with SR.4 or SR.5,
depending on the attempted operation. If RP#
transitions to VIL during block erase, program, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-
down. The aborted operation may leave data
partially altered. Therefore, the command sequence
must be repeated after normal operation is
restored.
5.2
RY/BY# Hardware Detection
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, program
and lock-bit configuration completion. This output
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to VOH when it is finished
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at
5.6
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
VOH
.
5.3
Power Supply Decoupling
supply (VPP or VCC
) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues: standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Two-line control and proper
decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between VCC and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either input signal to VIH will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. The device is
disabled while RP# = VIL regardless of its control
inputs state.
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5.7
V
Program and Erase
PP
Voltages on Sub-0.4µ SC
Memory Family
Intel's SmartVoltage FlashFile™ memory family
provides in-system program/erase at 3.3 V VPP and
5V VPP as well as faster factory program/erase at
12 V VPP
.
Future sub-0.4µ lithography SmartVoltage FlashFile
memory products will also include a backward-
compatible 12 V programming feature. This mode,
however, is not intended for extended use. A 12 V
program/erase VPP can be applied for 1000 cycles
maximum per block or 80 hours maximum per
device. To ensure compatibility with future sub-0.4µ
SmartVoltage FlashFile memory products, present
designs should not permanently connect VPP to
12 V. This will avoid device over-stressing that may
cause permanent damage.
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E
6.0 ELECTRICAL SPECIFICATIONS
NOTICE: This datasheet contains information on new
products in production. Do not finalize a design with this
information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
6.1
Absolute Maximum Ratings*
Temperature under Bias ................ –10°C to +80°C
Storage Temperature....................–65°C to +125°C
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device
reliability.
Voltage on Any Pin
(except VPP, and RP#)......... –2.0 V to +7.0 V(1)
VPP Voltage ........................... –2.0 V to +14.0 V(1,2)
RP# Voltage ........................–2.0 V to +14.0 V(1,2,4)
Output Short Circuit Current ....................100 mA(3)
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is–0.5 V on input/output pins and –0.2 V on VCC, RP#,
and VPP pins. During transitions, this level may undershoot to–2.0 V for periods <20 ns. Maximum DC voltage on
input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.
2. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods <20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
6.2
Commercial Temperature Operating Conditions
Commercial Temperature and VCC Operating Conditions
Symbol
Parameter
Notes
Min
0
Max
+70
3.6
Unit
°C
V
Test Condition
TA
Operating Temperature
Ambient Temperature
VCC1
VCC2
VCC3
VCC Supply Voltage (2.7 V–3.6 V)
VCC Supply Voltage (3.3 V ± 0.3 V)
VCC Supply Voltage (5 V ± 5%)
VCC Supply Voltage (5 V ± 10%)
1
2.7
3.0
4.75
4.5
3.6
V
5.25
5.5
V
VCC4
V
NOTE:
1. Block erase, program, and lock-bit configuration withV
< 3.0 V should not be attempted.
CC
(1)
6.3
Capacitance
TA = +25°C, f = 1 MHz
Symbol
Parameter
Typ
6
Max
8
Unit
Condition
VIN = 0.0 V
CIN
Input Capacitance
Output Capacitance
pF
pF
COUT
8
12
VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
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6.4
DC Characteristics—Commercial Temperature
2.7V V
3.3V V
CC
5V V
Test
CC
CC
Parameter
Sym
Notes Typ Max Typ Max Typ Max Unit
Conditions
I
I
I
Input Load Current
1
1
±0.5
±0.5
±0.5
±0.5
±1 µA
±10 µA
V
V
= V
= V
Max, V = V
or GND
LI
CC
CC
CC
CC
IN
CC
Output Leakage Current
Max, V
OUT
= V
or GND
CC
LO
V
Standby Current
1,3,6 20 100 20 100 25 100 µA CMOS Inputs
= V Max
CCS
CC
V
CC
CC
CE# = RP# = V
± 0.2 V
CC
0.1
2
0.2
2
0.4
2
mA TTL Inputs
= V
V
Max, CE# = RP# = V
CC IH
CC
10 µA RP# = GND ± 0.2 V
(RY/BY#) = 0 mA
I
V
Deep Power-
1
10
10
CCD
CCR
CC
I
OUT
CMOS Inputs
12 17 35 mA
Down Current
V Read Current
I
1,5,6
6
7
12
18
7
8
CC
V
= V
Max, CE# = GND
CC
f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V)
= 0 mA
CC
I
OUT
TTL Inputs
18 20 50 mA
V
= V
Max, CE# = GND
CC
CC
f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V)
= 0 mA
I
OUT
I
I
V
Program or
1,7
1,7
1,2
17
17
12
17
17
12
6
mA V = 3.3 V ± 0.3 V
PP
35 mA V = 5 V ± 10%
CCW
CC
Set Lock-Bit Current
PP
30 mA V = 12 V ± 5%
PP
V
Block Erase or
mA V = 3.3 V ± 0.3 V
PP
CCE
CC
Clear Block
30 mA V = 5 V ± 10%
PP
Lock-Bits Current
25 mA V = 12 V ± 5%
PP
I
I
V
Program or Block
1
1
10 mA CE# = V
CCWS CC
IH
Erase Suspend Current
CCES
PPS
I
I
I
V
V
V
Standby Current
Read Current
1
1
1
±2 ±15 ±2 ±15 ± 2 ±15 µA
10 200 10 200 10 200 µA
V
V
≤ V
PP
PP
PP
PP
PP
CC
CC
> V
PPR
PPD
Deep Power-Down
0.1
5
0.1
5
0.1
5
µA RP# = GND ± 0.2 V
Current
I
V
Program/ Set
1,7
1,7
1
40
40
15
20
20
15
mA V = 3.3 V ± 0.3 V
PP
PPW
PP
Lock-Bit Current
40 mA V = 5 V ± 10%
PP
15 mA V = 12 V ± 5%
PP
I
V
Block Erase/Clear
mA V = 3.3 V ± 0.3 V
PP
PPE
PP
Block Lock-Bits
Current
20 mA V = 5 V ± 10%
PP
15 mA V = 12 V ± 5%
PP
I
I
V
Program/ Block Erase
10 200 10 200 µA
V
= V
PP PPH1/2/3
PPWS PP
Suspend Current
PPES
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6.4 DC Characteristics—Commercial Temperature(Continued)
E
2.7 V V
3.3 V V
CC
5 V V
Test
Conditions
CC
CC
Sym
Parameter
Input Low Voltage
Input High Voltage
Notes Min Max Min Max Min Max Unit
V
7
–0.5 0.8 –0.5 0.8 –0.5 0.8
V
V
IL
V
7
2.0
2.4
V
2.0
V
2.0 V
CC
IH
CC
CC
+ 0.5
0.4
+ 0.5
0.4
+ 0.5
0.45
V
Output Low Voltage
3,7
3,7
V
V
I
= V
Min
CC
OL
CC
= 2 mA (2.7V, 3.3V)
5.8 mA (5V)
OL
V
V
Output High Voltage (TTL)
2.4
2.4
V
V
V
V
I
= V
Min
CC
OH1
OH2
CC
= –2.5 mA
OH
Output High Voltage
(CMOS)
3,7 0.85
0.85
0.85
V
I
= V
Min
CC
CC
= –2.5 mA
V
V
V
CC
CC
CC
OH
V
V
V
V
I
= V
Min
CC
CC
CC
CC
CC
= –100 µA
–0.4
–0.4
–0.4
OH
V
V
V
V
V
Lockout Voltage
Voltage
4,7
8,9
1.5
1.5
1.5
V
V
PPLK PP
V
3.0 3.6
PPH1 PP
V
Voltage
4.5 5.5 4.5 5.5
11.4 12.6 11.4 12.6
PPH2 PP
V
Voltage
V
PPH3 PP
V
V
V
Lockout Voltage
CC
2.0
2.0
2.0
V
V
LKO
HH
RP# Unlock Voltage
11.4 12.6 11.4 12.6
Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominalVCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2.
I
CCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of ICCWS or ICCES and ICCR or ICCW
3. Includes RY/BY#.
.
4. Block erases, programs, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), between VPPH2 (max) and VPPH3 (min), and
above VPPH3 (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH
7. Sampled, not 100% tested.
.
8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with VIH < RP# < VHH
.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
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2.7
0.0
OUTPUT
INPUT
1.35
TEST POINTS
1.35
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35
V. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V
3.0
OUTPUT
INPUT
1.5
TEST POINTS
1.5
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V and VCC = 5.0 V ± 5%
(High Speed Testing Configuration)
2.4
2.0
0.8
2.0
0.8
INPUT
OUTPUT
TEST POINTS
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and V (0.45 VTTL) for a Logic "0." Input timing begins at V
IH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. OInLput rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for VCC = 5.0 V ± 10%
(Standard Testing Configuration)
Test Configuration Capacitance Loading Value
1.3V
Test Configuration
VCC = 3.3 V ± 0.3 V, 2.7 V−3.6 V
VCC = 5 V ± 5%
CL (pF)
50
1N914
30
RL
= 3.3 K
DEVICE
UNDER
TEST
VCC = 5 V ± 10%
100
OUT
CL
NOTE:
CL includes Jig Capacitance
Figure 16. Transient Equivalent Testing
Load Circuit
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PRELIMINARY
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E
V
IH
RY/BY# (R)
VIL
P2
VIH
RP# (P)
VIL
P1
Figure 17. AC Waveform for Reset Operation
Table 8. Reset Specifications
2.7 V VCC 3.3 V VCC
5 V VCC
#
Sym
Parameter
Notes Min Max Min Max Min Max Unit
tPLPH RP# Pulse Low Time (If RP# is tied to VCC
,
100
100
100
P1
ns
this specification is not applicable)
tPLRH RP# Low to Reset during Block Erase,
Program, or Lock-Bit Configuration
20
12
P2
2,3
µs
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted when the WSM is not busy (RY/BY# = “1”), the reset will complete within 100 ns.
3. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid.
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
(1)
6.5
AC Characteristics—Read-Only Operations —Commercial Temperature
TA = 0°C to +70°C
5 V ± 5% VCC
5 V ± 10% VCC
3.3 V ± 0.3 V VCC
2.7 V−3.6 V VCC
-85/-95(5)
Versions(4)
-90/-100(6)
-120
-120
Unit
-150
-150
-170
#
Sym
Parameter
Notes Min Max Min Max Min Max Min Max Min Max
85
95
90
120
120
R1 tAVAV Read Cycle
Time
4, 8 Mbit
16 Mbit
150
150
170
170
ns
ns
100
85
95
90
100
90
120
120
120
120
50
R2 tAVQV Address to
4, 8 Mbit
150
150
150
150
55
170 ns
170 ns
170 ns
170 ns
55 ns
600 ns
Output Delay 16 Mbit
85
R3 tELQV CE# to Output 4, 8 Mbit
2
2
2
95
100
45
Delay
16 Mbit
40
R4 tGLQV OE# to Output Delay
400
400
400/
R5 tPHQV RP# High to Output
Delay
600
(7)
600
0
0
0
0
0
0
R6 tELQX CE# to Output in Low Z
R7 tGLQX OE# to Output in Low Z
3
3
3
0
0
0
0
ns
ns
55
10
55
10
55
15
R8 tEHQZ CE# High to Output in
High Z
55
20
55 ns
R9 tGHQZ OE# High to Output in
High Z
3
3
25 ns
ns
0
0
0
R10 tOH
Output Hold from
Address, CE# or OE#
Change, Whichever
Occurs First
0
0
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characteristics.
7. Valid for 3.3 V V
read operations.
CC
35
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Device
Data
Valid
Standby
Address Selection
V
IH
ADDRESSES (A)
Address Stable
VIL
R1
V
IH
CE# (E)
VIL
R8
R9
R2
R3
V
IH
OE# (G)
WE# (W)
VIL
V
IH
R4
VIL
R5
R10
V
OH
R6
DATA (D/Q)
(DQ0-DQ7)
High Z
High Z
Valid Output
VOL
R7
VCC
V
IH
RP# (P)
VIL
Figure 18. AC Waveform for Read Operations
36
PRELIMINARY
E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
(1,2)
6.6
AC Characteristics—Write Operations
—Commercial Temperature
TA = 0°C to +70°C
5 V ± 5%,
5 V ± 10% VCC
Valid for All
Speeds
3.3 V ± 0.3 V,
2.7 V−3.6 V VCC
Valid for All
Speeds
Versions
Unit
#
Sym
Parameter
Notes Min Max Min Max
W1 tPHWL (tPHEL
)
RP# High Recovery to WE# (CE#) Going
Low
3
1
1
µs
ns
W2 tELWL (tWLEL
)
CE# (WE#) Setup to WE# (CE#) Going
Low
7
0
0
W3 tWP
W4 tDVWH (tDVEH
W5 tAVWH (tAVEH
W6 tWHEH (tEHWH
W7 tWHDX (tEHDX
Write Pulse Width
7
4
4
50
40
40
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
)
)
)
5
5
W8 tWHAX (tEHAX
)
5
5
W9 tWPH
9
25
100
100
0
25
100
100
0
W10 tPHHWH (tPHHEH
W11 tVPWH (tVPEH
W12 tWHGL (tEHGL
) RP# VHH Setup to WE# (CE#) Going High 3,8
)
VPP Setup to WE# (CE#) Going High
Write Recovery before Read
3,8
)
W13 tWHRL (tEHRL
)
WE# (CE#) High to RY/BY# Going Low
8
90
90
W14 tQVPH
RP# VHH Hold from Valid SRD, RY/BY#
High
3,5,8
0
0
0
0
W15 tQVVL
VPP Hold from Valid SRD, RY/BY# High
3,5,8
ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration.
5.
V
PP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, program,
or lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Ordering Information for device speeds (valid operational combinations).
7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to tWP – 10 ns for 5 V VCC and tWP – 20 ns for 2.7 V and 3.3 V VCC writes.
8. Block erase, program, and lock-bit configuration withV
< 3.0 V should not be attempted.
CC
9. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
37
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
A
B
C
D
E
F
V
IH
ADDRESSES [A]
A
A
IN
IN
V
IL
W5
W8
V
IH
CE# (WE#) [E(W)]
OE# [G]
VIL
W6
W12
W16
W1
V
IH
V
IL
W9
W2
V
IH
WE# (CE#) [W(E)]
VIL
W3
W4
W7
V
IH
High Z
DATA [D/Q]
RY/BY# [R]
Valid
SRD
D
D
D
IN
IN
IN
V
IL
W13
V
IH
VIL
W14
W15
W10
VHH
V
IH
RP# [P]
V
IL
W11
V PPH2,1
V
[V]
PP
VPPLK
V
IL
NOTES:
A.
B. Write block erase or program setup.
V
power-up and standby.
CC
C. Write block erase confirm or valid address and data..
D. Automated erase or program delay.
E. Read status register data.
F. Write Read Array command.
Figure 19. AC Waveform for Write Operations
38
PRELIMINARY
E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
(3, 4, 5)
—
6.7
Block Erase, Program, and Lock-Bit Configuration Performance
Commercial Temperature
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
3.3 V VPP
5 V VPP
12 V VPP
(1)
(1)
(1)
#
Sym
Parameter
Notes Typ
Max
Typ
Max
Typ
Max Unit
W16 tWHRH1
,
Program Time
2
19
300
10
150
7
125
µs
tEHRH1
Block Write Time
Block Erase Time
2
2
1.2
0.8
4
6
0.7
0.4
2
5
0.5
0.3
1.5
4
sec
sec
W16 tWHRH2
,
,
,
tEHRH2
W16 tWHRH3
tEHRH3
Set Lock-Bit Time
Clear Block Lock-
2
2
21
1.8
7.1
TBD
TBD
10
13.3
1.2
TBD
TBD
9.3
11.6
1.1
TBD
TBD
10.4
µs
sec
µs
W16 tWHRH4
tEHRH4 Bits Time
W16 tWHRH5
,
Program Suspend
6.6
7.4
tEHRH5 Latency Time to
Read
W16 tWHRH6
,
Erase Suspend
15.2
21.1
12.3
17.2
12.3
17.2
µs
tEHRH6 Latency Time to
Read
V
CC = 5 V ± 5%, 5 V ± 10%, TA = 0°C to +70°C
5 V VPP
12 V VPP
(1)
(1)
#
Sym
Parameter
Program Time
Notes
Typ Max
Typ Max Unit
W16 tWHRH1
,
2
8
150
6
100 µs
tEHRH1
Block Write Time
Block Erase Time
2
2
0.5
0.4
1.5
5
0.4
0.3
1
4
sec
sec
W16 tWHRH2
,
,
,
,
,
tEHRH2
W16 tWHRH3
tEHRH3
Set Lock-Bit Time
2
2
12 TBD
1.1 TBD
10 TBD µs
1.0 TBD sec
5.2 7.5 µs
9.8 12.6 µs
W16 tWHRH4
tEHRH4
Clear Block Lock-Bits Time
W16 tWHRH5
tEHRH5
Program Suspend Latency Time to
Read
5.6
7
W16 tWHRH6
tEHRH6
Erase Suspend Latency Time to
Read
9.4 13.1
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested.
5. Reference the AC Waveform for Write Operations, Figure 19.
39
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
6.8 Extended Temperature Operating Conditions
E
Except for the specifications given in this section, all DC and AC characteristics are identical to those give in
commercial temperature specifications. See the Section 6.2 for commercial temperature specifications.
Extended Temperature and VCC Operating Conditions
Symbol
Parameter
Notes
Min
Max
Unit
Test Condition
TA
Operating Temperature
–40
+85
°C
Ambient Temperature
6.9
DC Characteristics—Extended Temperature
2.7V VCC 3.3V VCC 5V VCC
Test
Parameter
Sym
Notes Typ Max Typ Max Typ Max Unit
Conditions
ICCD VCC Deep Power-Down
1
20
20
20 µA RP# = GND ± 0.2 V
IOUT (RY/BY#) = 0 mA
Current
NOTE:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.
(1)
6.10 AC Characteristics—Read-Only Operations — Extended Temperature
TA = –40°C to +85°C
5 V ± 10% VCC
3.3 V ± 0.3 V VCC
2.7 V−3.6 V VCC
-100/-110
Versions(3)
-150
Unit
-170
Max
#
Sym
Parameter
Notes Min
100
110
Max
Min
Max
Min
R1 tAVAV Read Cycle Time
4, 8 Mbit
16 Mbit
4, 8 Mbit
16 Mbit
150
150
170
170
ns
ns
R2 tAVQV Address to Output
Delay
100
110
100
110
150
150
150
150
170 ns
170 ns
170 ns
170 ns
R3 tELQV CE# to Output Delay 4, 8 Mbit
16 Mbit
2
2
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV
3. See Ordering Information for device speeds (valid operational combinations).
.
40
PRELIMINARY
E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
7.0 ORDERING INFORMATION
Product line designator for all Intel Flash products
E 2 8 F 0 0 4 S C - 0 8 5
Operating Temperature/Package
Access Speed (ns)
85 ns (5 V, 30 pF), 90 ns (5 V)
120 ns (3.3 V), 150 ns (2.7 V)
E = Comm. Temp. 40-Lead TSOP
TE = Extended Temp. 40-Lead TSOP
PA = Comm. Temp 44-Lead PSOP
TB = Ext. Temp 44-Lead PSOP
G = Comm. Temp. 40-Ball µBGA* CSP
Voltage Options (VCC/VPP
C = SmartVoltage Flash
(2.7 V, 3.3 V and
)
5 V/3.3 V, 5 V and 12 V)
Device Density
004 = 4 Mbit
008 = 8 Mbit
016 = 16 Mbit
Product Family
S = FlashFile™ Memory
Valid Operational Combinations
5V VCC
Order Code by Density
8-Mbit
2.7V VCC
,
3.3V VCC
,
10% VCC
,
5% VCC,
4-Mbit
16-Mbit
Commercial Temperature
50pF load 50pF load 100pF load 30pF load
E28F004SC-85
E28F008SC-85
E28F016SC-95
-150
-170
-150
-170
-170
-120
-150
-120
-150
-90/-100(1) -85/95(1)
E28F004SC-120 E28F008SC-120 E28F016SC-120
PA28F004SC-85 PA28F008SC-85 PA28F016SC-95
PA28F004SC-120 PA28F008SC-120 PA28F016SC-120
-120
-90/-100(1) -85/95(1)
-120
G28F008SC-120 G28F016SC-120
–150
–150
–120
–120
-170
G28F008SC-150 G28F016SC-150
Extended Temperature
TE28F004SC-100 TE28F008SC-100 TE28F016SC-110
TB28F004SC-100 TB28F008SC-100 TB28F016SC-110
-170
-170
-150
-150
-100/-110(1)
-100/-110(1)
NOTE:
1. Valid access time for 16-Mbit byte-wide FlashFile memory.
41
PRELIMINARY
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
8.0 ADDITIONAL INFORMATION
Order Number
290598
Document/Tool
Byte-Wide Smart3 FlashFile Memory Family Datasheet
Byte-Wide Smart5 FlashFile Memory Family Datasheet
290597
292183
AB-64 4-, 8-, 16-Mbit Byte-Wide FlashFile™ Memory Family Overview
AP-359 28F008SA Hardware Interfacing
292094
292099
AP-364 28F008SA Automation and Algorithms
292123
AP-374 Flash Memory Write Protection Techniques
AP-625 28F008SC Compatibility with 28F008SA
292180
292182
AP-627 Byte-Wide FlashFile™ Memory Family Software Drivers
Byte-Wide SmartVoltage FlashFile™ Memory Family Specification Update
297729
Contact Intel/Distribution 4-, 8-, and 16-Mbit Schematic Symbols
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit TimingDesigner* Files
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit VHDL and Verilog Models
Sales Office
Contact Intel/Distribution 4-, 8-, and 16-Mbit iBIS Models
Sales Office
NOTE:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
42
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