PBA31308V2.02SLJYU [INTEL]
Telecom Circuit, 1-Func, CMOS, PBGA54, LGA-54;
| 型号： | PBA31308V2.02SLJYU |
| 厂家： | 
INTEL |
| 描述： | Telecom Circuit, 1-Func, CMOS, PBGA54, LGA-54 电信 电信集成电路 |
| 文件： | 总44页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Overview
T3130-8XV10PO5-7600
Jan 2007
PBA 31308
Bluetooth QD ID: B012097/B012098
UniStone
BlueMoon Universal Platform
N e v e r s t o p t h i n k i n g .
Edition 2007-01-31
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
For questions on technology, delivery and prices, please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S,
ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2,
IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A,
OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of
Infineon Technologies AG.
ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of
ARM Limited. The ARM logo, AMBA, ARMulator, EmbeddedICE, ModulGen, Multi-ICE,
PrimeCell, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, TDMI and STRONG are
trademarks of ARM Limited.
The Bluetooth® word mark is owned by the Bluetooth SIG, Inc. and any use of this mark
by Infineon Technologies AG is under license.
The BlueMoon® trade mark is owned by Infineon Technologies AG.
UniStone
PBA 31308
Revision History:
2007-01-31
T3130-8XV10PO5-7600
Previous Version:
Subjects (major changes since last revision)
Section
Product Overview
4
T3130-8XV10PO5-7600, 2007-01-31
UniStone
1
General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FW version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1
1.2
1.3
1.4
1.5
1.6
2
Basic Operating Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
2.2
3
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HCI / UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Supported Transport Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
WLAN Coexistence Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.1.1
3.1.2
3.1.2.1
3.2
3.2.1
3.3
4
General Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
HCI+ and Bluetooth Device Data (BD_DATA) . . . . . . . . . . . . . . . . . . . . . . 20
Manufacturer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Firmware ROM Patching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Patch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
4.2
4.3
4.3.1
5
Bluetooth Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UniStone Specifics and Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
During Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Scatternet and Piconet Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Role Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dynamic Polling Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Adaptive Frequency Hopping (AFH) . . . . . . . . . . . . . . . . . . . . . . . . . 23
Channel Quality Driven Data Rate Change (CQDDR) . . . . . . . . . . . 23
Synchronous Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voice Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RSSI and Output Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Received Signal Strength Indication (RSSI) . . . . . . . . . . . . . . . . . . . 24
Output Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ultra Low Transmit Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.1.5
5.2.2
5.2.2.1
5.2.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Product Overview
5
T3130-8XV10PO5-7600, 2007-01-31
UniStone
6.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pad Driver and Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pull-ups and Pull-downs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Characteristics of 32.768 kHz Clock Signal . . . . . . . . . . . . . . . . . . . . . . 33
RF Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Characteristics RF Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bluetooth Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2
6.3
6.3.1
6.3.2
6.3.3
6.4
6.4.1
6.5
6.5.1
6.5.1.1
7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Production Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.2.1
8
Acronyms & Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Product Overview
6
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
1
General Device Overview
1.1
Features
General
•
•
•
•
•
•
•
•
•
Complete Bluetooth 2.0 + EDR solution
Ultra low power design in 0.13 µm CMOS
Temperature range from -40°C to 85°C
Integrates ARM7TDMI, RAM and patchable ROM
On-module voltage regulators. External supply 2.9-4.1V
On-module EEPROM with configureable data
Reference clock included
Low power clock from internal oscillator or external low power clock (e.g. 32.768 kHz)
Dynamic low power mode switching
Interfaces
•
•
•
•
3.25 MBaud UART with transport layer detection (HCI UART, HCI Three-Wire UART)
PCM/I2S interface for digital audio
WLAN coexistence interface
General purpose I/Os with interrupt capabilities. JTAG for boundary scan and debug
RF
•
•
•
•
•
•
•
Transmit power programmable from -45 dBm to 4.5 dBm
Transmit power typ. 2.5 dBm (default settings)
Receiver sensitivity typ. -86 dBm
Integrated antenna switch, balun and antenna filter
Integrated LNA with excellent blocking and intermodulation performance
No external components except antenna
Digital demodulation for optimum sensitivity and co-/adjacent channel performance
Bluetooth
•
•
•
•
•
•
Piconet with seven slaves. Scatternet with two slave roles while still being visible
SCO and eSCO with hardware accelerated audio signal processing
Power control and RSSI. Hold, Park and Sniff.
Adaptive Frequency Hopping, Quality of Service, Channel Quality Driven Data Rate
Bluetooth security features: Authentication, Pairing and Encryption
Bluetooth test mode and Infineon’s active Bluetooth tester mode
Product Overview
7
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
1.2
Block Diagram
UniStone
EEPROM
I2C
VDD_PCM
VDD_UART
UART - HCI
PCM1
PMB8753
BlueMoon
UniCellular
Balun
Filter
Vsupply
Voltage
Regulator
Crystal
26 MHz
Low Power Clock
(Optional)
32.768 kHz
Figure 1-1
Simplified block diagram of UniStone.
Product Overview
8
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
1.3
Pin Configuration LGA
11,6
0,6
1,0
1,2
1,0
1,35
F1
F2
F3
F4
F5
F6
F7
F8
F9
E1
E2
E3
E4
E5
E6
E7
E8
E9
D1
C1
D2
C2
D3
C3
D4
C4
D5
C5
D6
C6
D7
C7
D8
C8
D9
C9
1,2
8,7
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
1,35
0,6
Figure 1-2
1.4
Pin Configuration for UniStone in Top View (footprint)
Pin Description
The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells
indicate that the pin might be removed/changed in future variants. All pins not listed
below shall be not connected.
Product Overview
9
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
.
Pin No.
Symbol
Input/
Supply
voltage
During
Reset
After
Reset
Function
Output
A2
A3
A8
P1.6
I/O/OD Internal1
AI Internal1
Z
Z
Port 1.6
RESET#
Input
Input
Input
Input
Hardware Reset
P1.5/
I/O/OD Internal1
Port 1.5 or
CLK32
LPM clock input (e.g.
32.768kHz)
B1
B2
B3
B4
P1.7/
I/O/OD Internal1
I/O/OD Internal1
I/O/OD Internal2
I/O/OD Internal2
I
PD/
PD/
Port 1.7 or
WAKEUP_BT
Input
Input
Bluetooth wake-up signal
P1.8/
PD
PD
Port 1.8 or
WAKEUP_HOST
Host wake-up signal
1)
1)
P1.0/
TMS
PU
PU
Port 1.0 or
JTAG interface
P1.4/
Z
-
Z
Port 1.4 or
RTCK
JTAG interface
B5
B9
C2
C3
ONOFF
SLEEPX
P0.9
-
Turns off module completely
Sleep indication signal
Port 0.9
I/O
VDDUART PD
H
Z
I/O/OD Internal2
Z
JTAG#
I
Internal2
PU
PU
Mode selection Port 1:
0: JTAG
1: Port
C4
D1
D2
D3
TRST#
P0.10
P0.8
I
Internal2
PD
Z
PD
Z
JTAG interface
Port 0.10
I/O/OD Internal2
I/O/OD Internal2
I/O/OD Internal2
PD
PD
Port 0.8
1)
1)
P1.1/
TCK
PU
PU
Port 1.1 or
JTAG interface
D4
D5
P0.3/
I/O/OD VDDPCM
I/O/OD VDDPCM
Conf.
Conf.
Port 0.3 or
PCMOUT
PD def. PD def. PCM data out
P0.2/
Z
Z
Port 0.2 or
PCMIN
PCM data in
D9
E1
ANTENNA
AI/AO
inactive inactive RF input/output single ended
P0.12/
SDA0
I/O/OD Internal2
PU
PU
Z
PU
PU
Z
Port 0.12 or
I2C data signal
E2
E3
P0.13/
SCL0
I/O/OD Internal2
I/O/OD Internal2
Port 0.13 or
I2C clock signal
P1.3/
Port 1.3 or
TDO/
JTAG interface or
WLAN coexistence interface
SLOT_STATE
E4
E5
P0.0/
I/O/OD VDDPCM
I/O/OD VDDPCM
PD
PD
PD
PD
Port 0.0 or
PCMFR1
PCM frame signal 1
P0.1/
Port 0.1 or
PCM clock
PCMCLK
Product Overview
10
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
Pin No.
Symbol
Input/
Supply
voltage
During
Reset
After
Reset
Function
Output
E6
F2
P0.5/
I/O/OD VDDUART
Z
Z
Port 0.5 or
UARTRXD
UART receive data
1)
1)
P1.2/
I/O/OD Internal2
PU
PU
Port 1.2 or
TDI/
JTAG interface or
WLAN coexistence interface
RF_ACTIVE
F3
F4
F5
F7
F8
P0.11/
I/O/OD Internal2
Z
Z
Z
Z
Port 0.11or
TX_CONF
WLAN coexistence interface
P0.14/
I/O
VDDUART
Z
Port 0.14 or
TX_CONF
WLAN coexistence interface
P0.7/
I/O/OD VDDUART
Z
Port 0.7 or
UARTCTS
UART CTS flow control
P0.4/
I/O/OD VDDUART PU
I/O/OD VDDUART PU
PU
PU
Port 0.4 or
UARTTXD
UART transmit data
P0.6/
Port 0.6 or
UARTRTS
UART RTS flow control
A4, A5, A6
VSUPPLY
VREG
SI
-
-
-
-
-
-
-
-
-
-
Power supply
C1
F6
C5
SO
SI
Regulated Power supply
UART interface Power supply
PCM interface Power supply
Ground
VDDUART
VDDPCM
SI
A1, A7, A9, C8, VSS
C9, D7, D8, E8,
E9, F1, F9
1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset.
If JTAG interface is not selected the port is tristate.
Descriptions of acronyms used in the pin list:
Acronym
Description
I
Input
O
Output
OD
Z
Output with open drain capability
Tristate
PU
PD
A
Pull-up
Pull-down
Analog (e.g. AI means analog input)
Supply (e.g. SO means supply output)
S
Product Overview
11
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
1.5
System Integration
UniStone is optimized for a low bill of material (BOM) and a small PCB size. Figure 1-3
shows a typical application example.
UARTRTS
ANTENNA
UARTTXD
UARTRXD
UARTCTS
PCMCLK
PCMFR1
PCMIN
PCMOUT
HOST
UniStone
TX_CONF
RF_ACTIVE
SLOT_STATE
WAKEUP_HOST
WAKEUP_BT
RESET#
WLAN
Subsystem
CLK32
Power
Supply
Optional
Figure 1-3
Example Bluetooth System
The UART interface is used for Bluetooth HCI communication between the host and
UniStone. When the HCI UART transport layer is used, four interface lines are needed:
two for data (UARTTXD and UARTRXD) and two for hardware flow control (UARTRTS
and UARTCTS). When the HCI Three-Wire UART transport layer is used the hardware
flow control lines are optional. In addition to the standard Bluetooth HCI commands,
UniStone supports a set of Infineon specific commands called HCI+.
Digital audio can either be sent over the HCI interface or over the dedicated PCM/I2S
interface. The PCM/I2S interface is highly configurable.
Low power mode control of UniStone and the host can be implemented in different ways,
either using the dedicated WAKEUP_HOST and WAKEUP_BT signals or using
signaling over the HCI interface. The host can reset UniStone via the RESET# signal.
A low power clock can be connected to CLK32 or generated internally by a low power
oscillator. Power is supplied to a single VSUPPLY input from which internal regulators
can generate all required voltages. The UART and the PCM interfaces have separate
supply voltages so that they can comply with host signaling.
Product Overview
12
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Overview
If a WLAN subsystem is collocated with UniStone the WLAN coexistence interface
should be used to enhance Bluetooth and WLAN performance. To coexist with external
WLAN devices UniStone supports adaptive frequency hopping.
1.6
FW version
UniStone is available in different versions. Please check corresponding release
documents for latest information.
Product Overview
13
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Basic Operating Information
2
Basic Operating Information
2.1
Power Supply
BlueMoon UniCellular is supplied from a single supply voltage VSUPPLY. This supply
voltage must always be present. The Bluemoon UniCellular chip is supplied from an
internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG
pin. This voltage may not be used for supplying other components in the host system but
can be used for referencing the host interfaces.
The PCM interface and the UART interface are supplied with dedicated, independent,
reference levels via the VDDPCM and VDDUART pins. All other digital I/O pins are
supplied internally by either 2.5 V (Internal2) or 1.5 V(Internal1). Section 1.4 provides a
mapping between pins and supply voltages.
The I/O power domains (VDDPCM and VDDUART) are completely separated from the
other power domains and can stay present also in low power modes.
2.2
Clocking
BlueMoon UniCellular has one clock input CLK32 that is optional. If used this 32.768 kHz
clock must always be present to assist BlueMoon UniCellular to keep the time in low
power modes.
The low power clock can be generated internally by the crystal oscillator and/or the low
power oscillator or provided externally.
Product Overview
14
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Interfaces
3
Interfaces
3.1
HCI / UART Interface
The HCI/UART interface is the main communication interface between the host and
UniStone. The standard HCI commands are supported together with an Infineon specific
set of commands called HCI+.
The interface consists of four UART signals and two wake-up signals as shown in
Figure 3-1. Depending on which HCI transport layer that is used, some or all of the
signals are needed.
Host
UniStone
UARTTXD
UARTRXD
UARTRTS
UARTCTS
UARTTXD
UARTRXD
UARTRTS
UARTCTS
WAKEUP_BT
WAKEUP_HOST
WAKEUP_BT
WAKEUP_HOST
Figure 3-1
3.1.1
HCI/UART Interface
Supported Transport Layers
UniStone supports the HCI Three-Wire UART transport layer and two derivatives of the
HCI UART transport layer (HCI UART-4W and HCI-UART-6W) where the only difference
is how low power modes are handled. UniStone automatically detects which transport
layer that is used by the host.
3.1.2
UART
The on-chip UART (Universal Asynchronous Receiver and Transmitter) is compatible
with standard UARTs and is optimized for Bluetooth communication. Hardware support
for SLIP1) framing and 16-bit CRC calculation enhances performance with the HCI
Three-Wire UART transport layer. A separate supply voltage, VDDUART, makes it easy
to connect the UART interface to any system.
1)
See http://www.ietf.org/rfc/rfc1055.txt for information about SLIP.
Product Overview
15
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Interfaces
3.1.2.1 Baud Rates
The supported baud rates are listed in Table 3-1 together with the small deviation error
that results from the internal clock generation. The default baud rate is 115200 Baud.
Table 3-1
UART Baud Rates
Wanted Baud Rate
Real Baud Rate
9615
Deviation Error (%)
9600
19200
38400
0.16
0.16
0.16
-0.14
-0.14
-0.14
0.76
0.76
0.76
0
19230
38461
57522
115044
230088
464285
928571
1857142
3250000
57600
115200
230400
460800
921600
1843200
3250000
Product Overview
16
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Interfaces
3.2
PCM Interface
The PCM interface is used to exchange synchronous data (usually audio) between
UniStone and the host as well as to connect e.g. an external audio codec or an external
DSP to UniStone. It can be configured as an industry standard PCM interface supporting
long and short frame synchronization, as an I2S interface1) or as an IOM-2 interface in
terminal mode with reduced capabilities.
The main features of the PCM interface are:
• Two bidirectional PCM channels
• Separate supply voltage (VDDPCM) for easy interfacing to other systems
• Support for all sample types defined in the Bluetooth specification
(Up to 16-bit linear samples and 8-bit A-law/µ-law compressed samples)2)
• 8x32-bit FIFOs for each channel
• Programmable frame length
• Programmable frame signal length
• Programmable channel start positions
• Programmable idle level on PCMOUT
• Programmable low-power/inactive levels on all PCM pins
• Data word LSB justified or MSB justified with respect to frame signal
• Clock master/slave mode
• Frame master/slave mode
• Fractional divider for PCM clock generation
1)
2)
Does not support variable word length. Hardware supports 16 or 24 bits. Current firmware supports 16 bits.
The hardware supports data word lengths of up to 24 bits.
Product Overview
17
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Interfaces
3.2.1
Overview
The PCM interface consists of four signals as shown in Figure 3-2 below
PCMCLK
M
S
B
L
S
B
M
S
B
L
S
B
M
1
4
1
3
1
2
1
1
1
0
1
4
1
3
1
2
1
1
1
0
1
4
1
3
1
2
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
S
B
IDLE
IDLE
PCMOUT
PCMIN
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
1
4
1
3
1
2
1
1
1
0
1
4
1
3
1
2
1
1
1
0
1
4
1
3
1
2
Don’t Care
Don’t Care
PCMFR1
Frame Signal Length
Channel
2
Start Position
Data Word Length
Frame Length
Figure 3-2
PCM Signals Overview
The clock signal PCMCLK is the timing base for the other signals in the PCM interface.
In clock master mode, UniStone generates PCMCLK from the internal system clock
using a fractional divider. In clock slave mode PCMCLK is an input to UniStone and has
to be supplied by an external source. The maximum PCMCLK frequency (in both modes)
is 1/8 of the internal system clock frequency.
The PCM interface supports up to two bidirectional channels. Data is transmitted on
PCMOUT and received on PCMIN, always with the most significant bit first. The
hardware supports a Data Word Length of 16 or 24 bits. The firmware always uses 16
bits since that is the maximum audio sample size (linear samples can be up to 16 bits,
A-law or µ-law compressed samples are always 8 bits).
The samples are organized in frames such that each frame contains one sample in each
direction of each active channel. The frame rate (i.e. sample rate) is controlled by the
PCMCLK frequency and the programmable Frame Length. In the firmware the sample
rate has been fixed to 8 kHz. This means that the PCMCLK frequency can be calculated
from Frame Length and does not have to be specified.
Channel 1 has a frame signal (PCMFR1) that indicates where in the frame the channel
starts. The Frame Signal Length is programmable.
In frame master mode, UniStone generates PCMFR1. In frame slave mode the signal
PCMFR1 is an input to UniStone and has to be supplied externally.
Product Overview
18
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Interfaces
3.3
WLAN Coexistence Interface
UniStone has a WLAN coexistence interface that is based on the IEEE 802.15.2 Packet
Traffic Arbitration (PTA) scheme1). The interface prevents interference between
collocated WLAN and Bluetooth devices by not letting the two devices transmit and/or
receive at the same time. WLAN packets and Bluetooth packets are assigned priorities,
and a control unit decides on a per-packet basis which of the devices that should be
allowed to operate.
The interface uses three wires as shown in Figure 3-3.
Host
UniStone
TX_CONF
SLOT_STATE
RF_ACTIVE
Host
Figure 3-3
WLAN Coexistence Interface
1)
“802.15.2: Coexistence of Wireless Personal Area Networks with other Wireless Devices Operating in
Unlicensed Frequency Bands”, IEEE, 28 August 2003
Product Overview
19
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Capabilities
4
General Device Capabilities
4.1
HCI+ and Bluetooth Device Data (BD_DATA)
In addition to the standard Bluetooth HCI commands and events, UniStone supports a
set of Infineon specific commands and events called HCI+. All Infineon specific features
are accessed using HCI+.
All configuration information that is critical for correct operation of UniStone is called
Bluetooth Device Data (BD_DATA). This data is stored in the module’s EEPROM and is
initialized during module manufacturing. BD_DATA can be read and written with the
HCI+ commands Infineon_Read_BD_Data and Infineon_Write_BD_Data.
Important Note: Each UniStone module is delivered with BD_DATA containing a unique
Bluetooth device address aswell as configuration parameters for the device. This
information should not be changed unless expressly allowed to do so. Please consult
manufacturer in uncertain cases.
4.2
Manufacturer Mode
HCI+ commands that modify critical information are not available during normal
operation. To access these commands the host must first tell UniStone to enter
manufacturer mode with the Infineon_Manufacturer_Mode command.
Operations that are only allowed in manufacturer mode are for example:
• Changing the Baud rate with Infineon_Set_UART_Baudrate.
• Switching to the built-in boot loader with Infineon_Switch_To_Loader. The loader is
primarily used for firmware evaluation and is not described in this document.
• Accessing Bluetooth Device Data (BD_DATA) with any of the following commands:
Infineon_Write_BD_Data, Infineon_Read_BD_Data,
Infineon_Write_Ext_EEPROM_Data, Infineon_Read_Ext_EEPROM_Data.
• Accessing internal memory and registers with
Infineon_Memory_Write and Infineon_Memory_Read.
It is necessary to leave manufacturer mode before start of normal operation. Leaving
manufacturer mode is done with the Infineon_Manufacturer_Mode command.
4.3
Firmware ROM Patching
Patch Support
4.3.1
UniStone contains dedicated hardware that makes it possible to apply patches to any
code and data in the firmware ROM. The hardware is capable of replacing up to 32
blocks of 16 bytes each with new content. In addition to this, a 12 kByte area of the
firmware RAM has been reserved for patches. This area can be filled with any
Product Overview
20
T3130-8XV10PO5-7600, 2007-01-31
UniStone
General Device Capabilities
combination of code and data. Please consult manufacturer for latest information of
available patches.
Product Overview
21
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Bluetooth Capabilities
5
Bluetooth Capabilities
5.1
Supported Features
UniStone supports all features in the Bluetooth 2.0 + EDR specification, including:
• Enhanced Data Rate up to 3 Mbit/s
• Adaptive Frequency Hopping (AFH)
• All packet types
• All LMP features
• Authentication, Pairing and Encryption
• Quality of Service
• Channel Quality Driven Data Rate change
• Sniff, Hold and Park
• Role Switch
• RSSI and Power Control
• Power class 1, 2 and 3
• 7 point-to-multipoint connections
• Scatternet with two slave roles while still being visible
• 2 synchronous links (SCO/eSCO)
• A-law, µ-law, CVSD and transparent synchronous data
• Dual SCO/eSCO channels in scatternet
5.2
UniStone Specifics and Extensions
During Connection
5.2.1
5.2.1.1 Scatternet and Piconet Capabilities
UniStone supports point-to-multipoint and scatternet scenarios:
• Up to 7 links
• Up to 2 simultaneous slave roles
• Always capable of responding to inquiry and remote name request
• Always capable of Inquiry
5.2.1.2 Role Switch
Only one role switch can be performed at a time. If a role switch request is pending, other
role switch requests on the same or other links are rejected. If a role switch fails,
UniStone will automatically try again a maximum of three times. Encryption (if present)
is stopped in the old piconet before a role switch is performed and re-enabled when the
role switch has succeeded or failed. If the physical link is in Sniff Mode, Hold Mode or
Product Overview
22
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Bluetooth Capabilities
Park State, or has any synchronous logical transports, a role switch will not be
performed.
5.2.1.3 Dynamic Polling Strategy
In addition to the regular polling scheme, UniStone dynamically assigns unused slots to
links where data is exchanged. This adapts very well to bursty traffic and improves
throughput and latency on the links.
5.2.1.4 Adaptive Frequency Hopping (AFH)
UniStone supports adaptive frequency hopping according to the Bluetooth 2.0 + EDR
specification. AFH switch and channel classification are supported both as master and
slave. Channel classification from the host is also supported.
A number of HCI+ commands and events are available to provide information about AFH
operation. The commands Infineon_Enable_AFH_Info_Sending and Infineon_Disable_
AFH_Info_Sending turn on and off the Infineon AFH Info events that provide detailed
information about channel classification, channel maps, interferers, etc.
If enabled by the Infineon_Enable_Infineon_Events command, the Infineon AFH
Extraordinary RSSI event informs the host whenever extraordinary RSSI measurements
in unused slots have been started. This is done when the number of known good
channels has decreased below a critical limit and periodically after a defined time.
The Infineon_Set_AFH_Measurement_Period command can be used to configure the
duration of the AFH measurement period.
5.2.1.5 Channel Quality Driven Data Rate Change (CQDDR)
UniStone supports channel quality driven data rate change according to the Bluetooth
2.0 + EDR specification. A device that receives an LMP_preferred_rate message is not
required to follow all recommendations. UniStone normally at least follows the
recommendation whether to use forward error correction (FEC) or not. If possible,
recommendations about packet size and modulation scheme will be taken into account.
When UniStone sends an LMP_preferred_rate to another device the proposal always
includes preferences for all parameters.
The HCI+ commands Infineon_Enable_CQDDR_Info_Sending and Infineon_Disable_
CQDDR_Info_Sending turn on and off sending of the Infineon CQDDR Info event. This
event provides information to the host every time a new CQDDR proposal is sent to a
remote device.
5.2.2
Synchronous Links
UniStone supports up to two simultaneous synchronous links (SCO/eSCO).
Product Overview
23
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Bluetooth Capabilities
5.2.2.1 Interface
The interface for synchronous data is either the HCI transport layer or the dedicated
PCM/I2S interface. The choice of interface for a synchronous connection is done with
the HCI+ command Infineon_Config_Synchronous_Interface and must be done before
the connection is established. The default interface is configurable via the bit Default_
SCO_interface in the BD_DATA parameter BB_Conf.
All details about the PCM/I2S interface are described in Section 3.2.
5.2.2.2 Voice Coding
Table 5-1 shows the supported values of the Bluetooth parameter Voice_Settings.
Table 5-1
Parameter
Supported Voice Settings
Supported Values
Input Coding
Linear (PCM/I2S only), µ-law, A-law
2’s complement
16-bit (only relevant for linear input coding)
CVSD, µ-law, A-law, Transparent Data
Input Data Format
Input Sample Size
Air Coding Format
UniStone supports transcoding between any combination of linear, µ-law and A-law. If
the air coding format is “Transparent Data” and the synchronous interface is the
transport layer, the input coding is ignored. If transparent data is sent through the PCM/
I2S interface, the input coding determines if 8-bit or 16-bit samples are used.
Transparent Data is the only setting for which data rates other than 64 kbit/s can be used.
5.2.3
RSSI and Output Power Control
5.2.3.1 Received Signal Strength Indication (RSSI)
UniStone supports received signal strength measurements and uses LMP signaling to
keep the output power of a remote device within the golden receive power range. The
range is set with the BD_DATA parameters RSSI_Min and RSSI_Max.
5.2.3.2 Output Power Control
UniStone supports power control according to the Bluetooth 2.0 + EDR specification.
• The output power can be controlled in 4 steps when an external power amplifier is
present.
• The output power can be controlled in 3 or 4 steps (configurable) with internal power
settings. In this case no power amplifier is present; therefore UniStone can work as a
class 1, 2 or 3 device depending on the settings.
Product Overview
24
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Bluetooth Capabilities
• Fine tuning can be used on the power steps.
The following BD_DATA parameters are used for configuration:
RF_Psel_D, RF_Psel_Conf, RF_Conf, TX_Power_Ref#.
5.2.3.3 Ultra Low Transmit Power
For high security devices the output power can be reduced to a value that reduces the
communication range to a few inches. This mode is enabled with the HCI+ command
Infineon_TX_Power_Config.
Product Overview
25
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
6
Electrical Characteristics
6.1
Absolute Maximum Ratings
Table 6-1
Parameter
Absolute Maximum Ratings
Limit Values
Unit Notes
Min
-40
Max
125
6.0
4.0
4.0
4.0
VSUPPLY
VSUPPLY+0.3
4.0
4.0
1.0
Storage temperature
VSUPPLY supply voltage
VDDUART supply voltage
VDDPCM supply voltage
VREG
VREG
ONOFF
Input voltage range
Output voltage range
ESD
oC
V
V
V
V
V
V
V
V
-
-
-
-
-0.3
-0.9
-0.9
-0.3
-0.3
-0.3
-0.9
-0.9
VSUPPLY > 4 V
VSUPPLY < 4 V
-
-
-
kV
According to MIL-
STD883D method 3015.7
Note: Stresses above those listed here are likely to cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.
Maximum ratings are not operating conditions.
Product Overview
26
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
6.2
Operating Conditions
Operating Conditions
Table 6-2
Parameter
Limit Values
Unit Notes
Min
-40
Max
85
4.1
3.6
3.6
Operating temperature
oC
V
V
-
Main supply voltage (Vsupply) 2.9
VDDUART
VDDPCM
1.35
1.35
V
Product Overview
27
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
6.3
DC Characteristics
6.3.1
Pad Driver and Input Stages
Table 6-3
Internal1 (1.5 V) supplied Pins (see Chapter 1.4)
Parameter
Condition
Limit Values
Unit
Min
-0.3
1.15
Typ Max
0.27
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Continuous Load1)
Pin Capacitance
-
-
V
V
V
V
mA
pF
µA
3.6
0.25
I
I
OL=1mA
OH=-1mA,
1.1
1
10
Magnitude Pin
Leakage
input and output
drivers disabled
0.01
1
1)
The totaled continuous load for all Internal1 supplied pins shall not exceed 2mA at the same time
Table 6-4
Internal2 (2.5 V) supplied Pins (see Chapter 1.4)
Parameter
Condition
Limit Values
Unit
Min
-0.3
1.93
1.93
Typ Max
0.45
Input low voltage
Input high voltage
-
V
V
V
-P0.10
-Other pins
2.8
3.6
Output low voltage
Output low voltage
Output high voltage
Output high voltage
Continuous Load1)
Pin Capacitance
I
I
I
I
OL=5mA
OL=2mA
OH=-5mA,
OH=-2mA,
0.25
0.15
V
V
V
V
mA
pF
µA
2.0
2.1
5
10
1
Magnitude Pin
Leakage
input and output
drivers disabled
0.01
1)
The totaled continuous load for all Internal2 supplied pins shall not exceed 35mA at the same time
Product Overview
28
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-5
VDDUART supplied Pins (see Chapter 1.4)
Parameter
Condition
Limit Values
Min
-0.3
0.7*VDDUART
0.7*VDDUART
Unit
Typ Max
0.2*VDDUART
Input low voltage
Input high voltage
V
V
V
V
P0.5/UARTRXD
-Other pins
VDDUART+0.3
3.6
0.25
Output low voltage
Output low voltage
Output high voltage
Output high voltage
I
OL=5mA
VDDUART=2.5V
IOL=2mA
VDDUART=2.5V
0.15
V
V
V
I
OH=-5mA,
VDDUART-0.25
VDDUART-0.15
VDDUART=2.5V
I
OH=-2mA,
VDDUART=2.5V
Continuous Load1)
Pin Capacitance
Magnitude Pin
Leakage
5
10
1
mA
pF
µA
input and output
drivers disabled
0.01
1)
The totaled continuous load for all VDDUART supplied pins shall not exceed 35mA at the same time
Product Overview
29
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-6
VDDPCM supplied Pins (see Chapter 1.4)
Parameter
Condition
Limit Values
Min
-0.3
Unit
Typ Max
0.2*VDDPCM
Input low voltage
Input high voltage
Output low voltage
V
V
V
0.7*VDDPCM
3.6
0.25
I
OL=5mA
VDDPCM=2.5V
Output low voltage
Output high voltage
Output high voltage
I
OL=2mA
0.15
V
V
V
VDDPCM=2.5V
I
OH=-5mA,
VDDPCM-0.25
VDDPCM-0.15
VDDPCM=2.5V
I
OH=-2mA,
VDDPCM=2.5V
Continuous Load1)
Pin Capacitance
Magnitude Pin
Leakage
5
10
1
mA
pF
µA
input and output
drivers disabled
0.01
1)
The totaled continuous load for all VDDPCM supplied pins shall not exceed 35mA at the same time
Table 6-7
ONOFF PIN (see Chapter 1.4)
Parameter
Condition
Limit Values
Unit
Min
Typ Max
Input low voltage
Input high voltage
Input current
0.7
VSUPPLY
1
V
V
µA
1.7
-1
ONOFF=0V
0.01
Product Overview
30
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
6.3.2
Pull-ups and Pull-downs
Table 6-8
Pin
Pull-up and pull-down currents
Pull Up Current Pull Down Current Unit Conditions
Min Typ Max Min Typ Max
260 740 1300 N/A N/A
P0.12/SDA0,
P0.13/SCL0
N/A µA Pull-up current
measured with
pin voltage = 0V
TRST#, JTAG#,
P0.0/PCMFR1,
P0.1/PCMCLK,
P0.2/PCMIN,
22 130 350 23
150
380 µA
Pull-down current
measured with
pin voltage =
P0.3/PCMOUT
supply voltage
P0.4/UARTTXD,
P0.5/UARTRXD,
P0.6/UARTRTS,
P0.7/UARTCTS,
P0.10/PSEL1,
P0.8/PAON,
4.2 24
68
3.0 20
55
14
µA
Min measured at
125°C with
supply = 1.35V
Typ measured at
27°C with
supply = 2.5V
P0.9/PSEL0,
P0.11/RXON,
P0.14/TX_CONF,
P0.15/SLEEPX
Max measured at
-40°C with
supply = 3.63V
P1.0/TMS,
1.1 6.0 17
0.75 5.0
µA
P1.1/TCK,
P1.2/TDI,
P1.3/TDO,
P1.4/RTCK,
P1.5/CLK32,
P1.6,
P1.7/WAKEUP_BT,
P1.8/WAKEUP_HOST,
6.3.3
Protection Circuits
All pins have an inverse protection diode against VSS.
P0.10 has an inverse diode against Internal2.
P0.5/UARTRXD has an inverse diode against VDDUART.
All other pins have no diode against their supply.
Product Overview
31
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
System Power Consumption
Table 6-9 Current Consumption In Different Operating Modes
This table shows the Vsupply current consumption. All I/O current is neglected since they
depend mainly on the external load.
T=25°C, Output Power=0dBm,
Parameters
Min Typ
Max Unit Comment
Ultra Low Power Mode
Page & Inquiry Scan (1.28s)
Sniff (1.28s)
ACL (Transmit DH1)
ACL (Receive DH1)
ACL (Transmit 2-DH1)
170
1.1
0.35
38
35
40
µA
mA
mA
mA Basic Rate, 179.2 kb/s1)
mA Basic Rate, 179.2 kb/s
mA Enhanced Data Rate, 358.4 kb/
s1)
ACL (Receive 2-DH1)
ACL (Transmit 3-DH1)
ACL (Receive 3-DH1)
37
40
37
mA Enhanced Data Rate, 358.4 kb/
s1)
mA Enhanced Data Rate, 544.0 kb/
s1)
mA Enhanced Data Rate, 544.0 kb/
s1)
SCO (HV3)
19
20
13
11
14
10
8.7
mA
mA
eSCO (Symmetric 64 kb/s, EV3)
eSCO (Symmetric 64 kb/s, 2-EV3)
eSCO (Symmetric 64 kb/s, 3-EV3)
eSCO (Symmetric 64 kb/s, EV5)
eSCO (Symmetric 64 kb/s, 2-EV5)
eSCO (Symmetric 64 kb/s, 3-EV5)
mA Enhanced Data Rate
mA Enhanced Data Rate
mA
mA Enhanced Data Rate
mA Enhanced Data Rate
1)
Figure indicates maximum possible data rate with this packet type
Table 6-10 Max. Load at the Different Supply Voltages
I/O currents are not included since they depend mainly on external loads.
Parameters
Vsupply
Min
Typ
Max
100
Unit Comment
mA peak current
Product Overview
32
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
6.4
AC Characteristics
6.4.1
Characteristics of 32.768 kHz Clock Signal
The 32.768 kHz clock signal applied to CLK32 must be a rectangular waveform with a
duty cycle of between 10-90%. The frequency accuracy must be better than 250 ppm.
The rise and fall time of the signal must be less than 10 µs.
6.5
RF Part
6.5.1
Characteristics RF Part
The characteristics involve the spread of values to be within the specific temperature
range. Typical characteristics are the median of the production.
All values refers to Infineon reference design. All values will be updated after verification/
Characterisation.
6.5.1.1 Bluetooth Related Specifications
Table 6-11 BDR - Transmitter Part
Parameters
Min
0.5
Typ
2.5
4.5
Max
4.5
Unit
dBm
dBm
dB
Conditions
Default settings
Maximum settings
Output power (high gain)
Output power (highest gain)
Power control step size
Frequency range fL
4
2400
6
8
2401.3
MHz
Frequency range fH
2480.7 2483.5 MHz
20dB bandwidth
0.930
-40
-60
1
MHz
dBm
dBm
dBm
2nd adjacent channel power
3rd adjacent channel power
>3rd adjacent channel power
-20
-40
-40
-64
max. 2 of 3 exceptions
@ 52 MHz offset
might be used
Average modulation deviation
for 00001111 sequence
Minimum modulation deviation
for 01010101 sequence
Ratio Deviation 01010101 /
Deviation 00001111
140
115
0.8
156
145
1
175
kHz
kHz
Product Overview
33
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-11 BDR - Transmitter Part
Parameters
Min
Typ
Max
Unit
Conditions
Initialcarrierfrequencytolerance
75
kHz
kHz
kHz
kHz
|foffset|
Carrier frequency drift (one slot)
|fdrift|
Carrier frequency drift (three
slots) |fdrift|
Carrier frequency drift (five slots)
|fdrift|
Carrier frequency driftrate (one
slot) |fdriftrate|
Carrier frequency driftrate (three
slots) |fdriftrate|
Carrier frequency driftrate (five
slots) |fdriftrate|
10
10
10
5
25
40
40
20
20
20
kHz/
50µs
kHz/
50µs
kHz/
50µs
5
5
Table 6-12 BDR - Receiver Part
Parameters
Sensitivity
C/I-performance:
-4th adjacent channel
Min
Typ
-86
-51
Max
-81
-40
Unit
dBm
dB
Conditions
ideal wanted signal
C/I-performance:
-3rd adjacent channel (1st adj. of
image)
-46
-20
dB
C/I-performance:
-35
-4
-9
0
dB
dB
-2nd adjacent channel (image)
C/I-performance:
-1st adjacent channel
C/I-performance: co. channel
C/I-performance:
+1st adjacent channel
9
-4
11
0
dB
dB
C/I-performance:
-40
-50
-30
-40
dB
dB
+2nd adjacent channel
C/I-performance:
+3rd adjacent channel
Product Overview
34
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-12 BDR - Receiver Part
Parameters
Min
Typ
Max
Unit
Conditions
Blocking performance
30MHz-2GHz
10
dBm
some spurious
responses, but
according to
BT-specification
Blocking performance
2GHz-2.4GHz
Blocking performance
2.5GHz-3GHz
Blocking performance
3GHz-12.75GHz
-27
-27
10
dBm
dBm
dBm
some spurious
responses, but
according to
BT-specification
Intermodulation performance
Maximum input level
-39
-20
-34
dBm
dBm
valid for all
intermodulation tests
Table 6-13 EDR - Transmitter Part
Parameters
Output power (high gain)
Relative transmit power: PxPSK -4
- PGFSK
Min
-2.5
Typ
0
-0.6
Max
2
1
Unit
dBm
dB
Conditions
Carrier frequency stability |ωi|
Carrier frequency stability
|ωi+ω0|
75
75
kHz
kHz
Carrier frequency stability |ω0|
DPSK - RMS DEVM
8DPSK - RMS DEVM
DPSK - Peak DEVM
8DPSK - Peak DEVM
DPSK - 99% DEVM
2
10
20
13
35
25
30
20
kHz
%
%
%
%
10
10
20
20
%
%
8DPSK - 99% DEVM
Differential phase encoding
1st adjacent channel power
99
100
-40
%
dBc
-26
Product Overview
35
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-13 EDR - Transmitter Part
Parameters
Min
Typ
Max
Unit
Conditions
2nd adjacent channel power
-20
dBm
Carrier power
measured at basic
rate.
≥3rd adjacent channel power
-40
dBm
Carrier power
measured at basic
rate.
Table 6-14 EDR - Receiver Part
Parameters
DQPSK-Sensitivity
8DPSK-Sensitivity
DQPSK - BER Floor Sensitivity
8DPSK - BER Floor Sensitivity
Min
Typ
-88
-83
-84
-79
-53
Max
-83
-77
-60
-60
-40
Unit
dBm
dBm
dBm
dBm
dB
Conditions
ideal wanted signal
ideal wanted signal
DQPSK - C/I-performance:
-4th adjacent channel
DQPSK - C/I-performance:
-3rd adjacent channel (1st adj.
of image)
-47
-20
dB
DQPSK - C/I-performance:
-31
-7
-7
dB
dB
dB
dB
dB
dB
dB
dB
-2nd adjacent channel (image)
DQPSK - C/I-performance:
-1st adjacent channel
DQPSK - C/I-performance:
co. channel
DQPSK - C/I-performance:
+1st adjacent channel
DQPSK - C/I-performance:
+2nd adjacent channel
DQPSK - C/I-performance:
+3rd adjacent channel
8DPSK - C/I-performance:
-4th adjacent channel
8DPSK - C/I-performance:
-3rd adjacent channel (1st adj.
of image)
0
11
13
0
-9
-44
-50
-48
-44
-30
-40
-33
-13
Product Overview
36
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Electrical Characteristics
Table 6-14 EDR - Receiver Part
Parameters
Min
Typ
Max
Unit
Conditions
8DPSK - C/I-performance:
-25
0
dB
dB
dB
dB
dB
dB
dBm
-2nd adjacent channel (image)
8DPSK - C/I-performance:
-1st adjacent channel
8DPSK - C/I-performance:
co. channel
8DPSK - C/I-performance:
+1st adjacent channel
8DPSK - C/I-performance:
+2nd adjacent channel
-5
5
17
-5
21
5
-36
-46
-25
-33
8DPSK - C/I-performance:
+3rd adjacent channel
Maximum input level
-20
Product Overview
37
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Package Information
7
Package Information
7.1
Package marking
PBA 31308 V1.01
Version
Date code
FCC ID
G0644 5N605001
FCC ID: Q2331308
Machine readable
2D date code
7.2
Production Package
All dimensions are in mm.
Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm.
Product Overview
38
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Package Information
7.2.1
Pin mark
Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module
according to Figure 7-1. Diameter of pin 1 mark on the shield is 0.40 mm.
Figure 7-1
Topview and bottom view
PBA 31308 V1.01
G0644 5N605001
FCC ID: Q2331308
0,92
D=0,4
0,92
Pin1 marking bottom side
Product Overview
39
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Acronyms & Abbreviations
8
Acronyms & Abbreviations
Acronym or
abbreviation
Writing out in full
ACK
Acknowledgement
ACL
Asynchronous Connection-oriented (logical transport)
Adaptive Frequency Hopping
Adaptive Hop Sequence
AFH
AHS
ARQ
b
Automatic Repeat reQuest
bit/bits (e.g. kb/s)
B
Byte/Bytes (e.g. kB/s)
BALUN
BD_ADDR
BER
BALanced UNbalanced
Bluetooth Device Address
Bit Error Rate
BMU
BOM
BT
BlueMoon Universal
Bill Of Material
Bluetooth
BW
Bandwidth
CMOS
COD
CODEC
CPU
CQDDR
CRC
CTS
Complementary Metal Oxide Semiconductor
Class Of Device
COder/DECoder
Central Processing Unit
Channel Quality Driven Data Rate
Cyclic Redundancy Check
Clear To Send (UART flow control signal)
Continuous Variable Slope Delta (modulation)
Direct Current
CVSD
DC
DDC
DM
Device Data Control
Data Medium-Rate (packet type)
Direct Memory Access
DMA
DH
Data High-Rate (packet type)
Differential Phase Shift Keying (modulation)
Differential Quaternary Phase Shift Keying (modulation)
DPSK
DQPSK
Product Overview
40
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Acronyms & Abbreviations
Acronym or
abbreviation
Writing out in full
DSP
DUT
CDCT
CQDDR
EDR
EEPROM
eSCO
EV
Digital Signal Processor
Device Under Test
Clock Drift Compensation Task
Channel Quality Driven Data Rate
Enhanced Data Rate
Electrically Erasable Programmable Read Only Memory
Extended Synchronous Connection-Oriented (logical transport)
Extended Voice (packet type)
Forward Error Correction
FEC
FHS
FIFO
FM
Frequency Hop Synchronization (packet)
First In First Out (buffer)
Frequency Modulation
FW
Firmware
GFSK
GPIO
GSM
HCI
Gaussian Frequency Shift Keying (modulation)
General Purpose Input/Output
Global System for Mobile communication
Host Controller Interface
HCI+
HEC
HV
Infineon Specific HCI command set
Header Error Check
High quality Voice (packet type)
Hardware
HW
I2C
Inter-IC Control (bus)
I2S
Inter-IC Sound (bus)
IAC
Inquiry Access Code
ID
IDentifier
IEEE
IF
Institute of Electrical and Electronics Engineers
Intermediate Frequency
ISM
Industrial Scientific & Medical (frequency band)
Joint Test Action Group
JTAG
LAN
LAP
Local Area Network
Lower Address Part
Product Overview
41
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Acronyms & Abbreviations
Acronym or
abbreviation
Writing out in full
LM
Link Manager
LMP
LNA
LO
Link Manager Protocol
Low Noise Amplifier
Local Oscillator
LPM
LSB
LT_ADDR
MSB
MSRS
NC
Low Power Mode(s)
Least Significant Bit/Byte
Logical Transport Address
Most Significant Bit/Byte
Master-Slave Role Switch
No Connection
NOP
NVM
OCF
OGF
PA
No OPeration
Non-Volatile Memory
Opcode Command Field
Opcode Group Field
Power Amplifier
PCB
PCM
PDU
PER
PIN
Printed Circuit Board
Pulse Coded Modulation
Protocol Data Unit
Packet Error Rate
Personal Identification Number
Packet Loss Concealment
Phase Locked Loop
Power Management Unit
Power-On Reset
PLC
PLL
PMU
POR
PTA
PTT
QoS
RAM
RF
Packet Traffic Arbitration
Packet Type Table
Quality Of Service
Random Access Memory
Radio Frequency
ROM
RSSI
Read Only Memory
Received Signal Strength Indication
Product Overview
42
T3130-8XV10PO5-7600, 2007-01-31
UniStone
Acronyms & Abbreviations
Acronym or
abbreviation
Writing out in full
RTS
Request To Send (UART flow control signal)
Receive
RX
RXD
SCO
SIG
Receive Data (UART signal)
Synchronous Connection-Oriented (logical transport)
Special Interest Group (Bluetooth SIG)
Software
SW
SYRI
TBD
TCK
TDI
Synthesizer Reference Input
To Be Determined
Test Clock (JTAG signal)
Test Data In (JTAG signal)
Test Data Out (JTAG signal)
Transport Layer
TDO
TL
TMS
TX
Test Mode Select (JTAG signal)
Transmit
TXD
UART
ULPM
VCO
WLAN
Transmit Data (UART signal)
Universal Asynchronous Receiver & Transmitter
Ultra Low Power Mode
Voltage Controlled Oscillator
Wireless LAN (Local Area Network)
Product Overview
43
T3130-8XV10PO5-7600, 2007-01-31
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
©2020 ICPDF网 联系我们和版权申明