PRIXP420BB [INTEL]
RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA492, LEAD FREE, PLASTIC, BGA-492;
| 型号： | PRIXP420BB |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA492, LEAD FREE, PLASTIC, BGA-492 时钟 外围集成电路 |
| 文件： | 总112页 (文件大小：1252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane
Processor
Datasheet
Product Features
For a complete list of product features, see “Product Features” on page 9.
■ Intel XScale® Core
■ Three Network Processor Engines
■ PCI Interface
■ Encryption/Authentication
■ High-Speed UART
■ Console UART
■ Two MII Interfaces
■ UTOPIA-2 Interface
■ Internal Bus Performance Monitoring Unit
■ 16 GPIOs
■ USB v 1.1 Device Controller
■ Two High-Speed, Serial Interfaces
■ SDRAM Interface
■ Four Internal Timers
■ Packaging
—492-pin PBGA
—Commercial/Extended Temperature
Typical Applications
■ High-Performance DSL Modem
■ High-Performance Cable Modem
■ Residential Gateway
■ Control Plane
■ Integrated Access Device (IAD)
■ Set-Top Box
■ SME Router
■ Network Printers
■ Access Points (802.11a/b/g)
■ Industrial Controllers
Document Number: 252479-004
June 2004
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS
AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
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Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling
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Inside, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2004
2
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
Contents
1.0 Product Features ...........................................................................................................................9
1.1
1.2
1.3
Product Line Features ..........................................................................................................9
Processor Features ............................................................................................................12
About this Document ..........................................................................................................12
2.0 Functional Overview ...................................................................................................................14
2.1
Functional Units..................................................................................................................17
2.1.1 Network Processor Engines (NPEs)......................................................................17
2.1.2 Internal Bus............................................................................................................18
2.1.2.1 North AHB..............................................................................................18
2.1.2.2 South AHB .............................................................................................19
2.1.2.3 APB Bus.................................................................................................19
2.1.3 MII Interfaces.........................................................................................................19
2.1.4 UTOPIA 2 ..............................................................................................................20
2.1.5 USB Interface ........................................................................................................20
2.1.6 PCI Controller ........................................................................................................20
2.1.7 SDRAM Controller .................................................................................................20
2.1.8 Expansion Bus.......................................................................................................21
2.1.9 High-Speed, Serial Interfaces................................................................................21
2.1.10 High-Speed and Console UARTs ..........................................................................22
2.1.11 GPIO......................................................................................................................22
2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..............................................22
2.1.13 Interrupt Controller.................................................................................................22
2.1.14 Timers....................................................................................................................23
2.1.15 AHB Queue Manager ............................................................................................23
Intel XScale® Core..............................................................................................................23
2.2.1 Super Pipeline .......................................................................................................24
2.2.2 Branch Target Buffer (BTB)...................................................................................25
2.2.3 Instruction Memory Management Unit (IMMU)......................................................26
2.2.4 Data Memory Management Unit (DMMU) .............................................................26
2.2.5 Instruction Cache (I-Cache)...................................................................................26
2.2.6 Data Cache (D-Cache) ..........................................................................................27
2.2.7 Mini-Data Cache ....................................................................................................27
2.2.8 Fill Buffer (FB) and Pend Buffer (PB).....................................................................28
2.2.9 Write Buffer (WB)...................................................................................................28
2.2.10 Multiply-Accumulate Coprocessor (CP0)...............................................................28
2.2.11 Performance Monitoring Unit (PMU)......................................................................29
2.2.12 Debug Unit.............................................................................................................29
2.2
3.0 Functional Signal Descriptions..................................................................................................30
4.0 Package and Pinout Information................................................................................................42
4.1
4.2
4.3
Package Description...........................................................................................................42
Signal-Pin Descriptions.......................................................................................................45
Package Thermal Specifications ........................................................................................73
4.3.1 Commercial Temperature ......................................................................................73
4.3.2 Extended Temperature ..........................................................................................73
Datasheet
3
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
5.0 Electrical Specifications .............................................................................................................74
5.1
5.2
Absolute Maximum Ratings................................................................................................74
CCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements..................................................74
V
5.2.1
5.2.2
5.2.3
5.2.4
V
V
V
V
CCPLL1 Requirement............................................................................................74
CCPLL2 Requirement............................................................................................75
CCOSCP Requirement ..........................................................................................75
CCOSC Requirement ............................................................................................76
5.3
5.4
RCOMP Pin Requirements.................................................................................................77
DC Specifications ...............................................................................................................77
5.4.1 Operating Conditions.............................................................................................77
5.4.2 PCI DC Parameters...............................................................................................78
5.4.3 USB DC Parameters..............................................................................................78
5.4.4 UTOPIA-2 DC Parameters ....................................................................................79
5.4.5 MII DC Parameters................................................................................................79
5.4.6 MDIO DC Parameters............................................................................................80
5.4.7 SDRAM Bus DC Parameters.................................................................................80
5.4.8 Expansion Bus DC Parameters.............................................................................81
5.4.9 High-Speed, Serial Interface 0 DC Parameters.....................................................81
5.4.10 High-Speed, Serial Interface 1 DC Parameters.....................................................81
5.4.11 High-Speed and Console UART DC Parameters..................................................82
5.4.12 GPIO DC Parameters............................................................................................83
5.4.13 JTAG DC Parameters............................................................................................83
5.4.14 Reset DC Parameters............................................................................................83
AC Specifications................................................................................................................84
5.5.1 Clock Signal Timings .............................................................................................84
5.5.1.1 Processor Clock Timings .......................................................................84
5.5.1.2 PCI Clock Timings .................................................................................86
5.5.1.3 MII Clock Timings ..................................................................................86
5.5.1.4 UTOPIA-2 Clock Timings.......................................................................86
5.5.1.5 Expansion Bus Clock Timings ...............................................................86
5.5.2 Bus Signal Timings................................................................................................87
5.5.2.1 PCI.........................................................................................................87
5.5.2.2 USB Interface.........................................................................................88
5.5.2.3 UTOPIA-2 ..............................................................................................89
5.5.2.4 MII..........................................................................................................90
5.5.2.5 MDIO......................................................................................................91
5.5.2.6 SDRAM Bus...........................................................................................92
5.5.2.7 Expansion Bus.......................................................................................93
5.5.2.8 High-Speed, Serial Interfaces..............................................................107
5.5.2.9 JTAG....................................................................................................109
5.5.3 Reset Timings......................................................................................................110
Power Sequence ..............................................................................................................111
5.5
5.6
5.7
5.8
ICC and Total Average Power ...........................................................................................112
Ordering Information.........................................................................................................112
4
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
Figures
1
2
3
4
5
6
7
Intel® IXP425 Network Processor Block Diagram ......................................................................14
Intel® IXP422 Network Processor Block Diagram ......................................................................15
Intel® IXP421 Network Processor Block Diagram ......................................................................15
Intel® IXP420 Network Processor Block Diagram ......................................................................16
Intel XScale® Core Block Diagram .............................................................................................24
492-Pin Lead PBGA Package ....................................................................................................42
Package Markings ......................................................................................................................43
8
9
10
11
VCCPLL1 Power Filtering Diagram...............................................................................................75
VCCPLL2 Power Filtering Diagram...............................................................................................75
VCCOSCP Power Filtering Diagram .............................................................................................76
VCCOSC Power Filtering Diagram ...............................................................................................76
12 RCOMP Pin External Resistor Requirements ............................................................................77
13 Typical Connection to a Crystal..................................................................................................85
14 Typical Connection to an Oscillator ............................................................................................85
15 PCI Output Timing ......................................................................................................................87
16 PCI Input Timing.........................................................................................................................87
17 UTOPIA-2 Input Timings.............................................................................................................89
18 UTOPIA-2 Output Timings..........................................................................................................89
19 MII Output Timings .....................................................................................................................90
20 MII Input Timings ........................................................................................................................90
21 MDIO Output Timings.................................................................................................................91
22 MDIO Input Timings....................................................................................................................91
23 SDRAM Input Timings ................................................................................................................92
24 SDRAM Output Timings .............................................................................................................93
25 Intel Multiplexed Mode................................................................................................................93
26 Intel Simplex Mode .....................................................................................................................94
27 Motorola* Multiplexed Mode .......................................................................................................95
28 Motorola* Simplex Mode.............................................................................................................97
29 HPI – 8 Mode Write Accesses....................................................................................................99
30 HPI-16 Multiplex Write Mode....................................................................................................101
31 HPI-16 Multiplex Read Mode....................................................................................................103
32 HPI-16 Non-Multiplex Read Mode............................................................................................104
33 HPI-16 Non-Multiplex Write Mode ............................................................................................106
34 High-Speed, Serial Timings......................................................................................................107
35 Boundary-Scan General Timings..............................................................................................109
36 Boundary-Scan Reset Timings.................................................................................................109
37 Reset Timings...........................................................................................................................110
38 Power-up Sequence Timing .....................................................................................................112
Datasheet
5
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
Tables
1
2
3
4
5
6
7
8
9
Processor Features ....................................................................................................................12
Related Documents....................................................................................................................13
Processor Functions...................................................................................................................17
Signal Type Definitions...............................................................................................................30
SDRAM Interface........................................................................................................................31
PCI Controller.............................................................................................................................33
High-Speed, Serial Interface 0 ...................................................................................................34
High-Speed, Serial Interface 1 ...................................................................................................35
MII Interfaces..............................................................................................................................35
10 UTOPIA-2 Interface....................................................................................................................37
11 Expansion Bus Interface.............................................................................................................38
12 UART Interfaces.........................................................................................................................39
13 USB Interface .............................................................................................................................39
14 Oscillator Interface......................................................................................................................40
15 GPIO Interface............................................................................................................................40
16 JTAG Interface ...........................................................................................................................40
17 System Interface.........................................................................................................................41
18 Power Interface ..........................................................................................................................41
19 Part Numbers .............................................................................................................................43
20 Ball Map Assignment for the Intel® IXP425 Network Processor.................................................45
21 Ball Map Assignment for the Intel® IXP422 Network Processor.................................................52
22 Ball Map Assignment for the Intel® IXP421 Network Processor.................................................59
23 Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor.............................................................................66
24 Operating Conditions..................................................................................................................77
25 PCI DC Parameters....................................................................................................................78
26 USB v1.1 DC Parameters...........................................................................................................78
27 UTOPIA-2 DC Parameters .........................................................................................................79
28 MII DC Parameters.....................................................................................................................79
29 MDIO DC Parameters ................................................................................................................80
30 SDRAM Bus DC Parameters......................................................................................................80
31 Expansion Bus DC Parameters..................................................................................................81
32 High-Speed, Serial Interface 0 DC Parameters..........................................................................81
33 High-Speed, Serial Interface 1 DC Parameters..........................................................................81
34 UART DC Parameters................................................................................................................82
35 GPIO DC Parameters.................................................................................................................83
36 JTAG DC Parameters.................................................................................................................83
37 PWRON_Reset _N DC Parameters...........................................................................................83
38 Device Clock Timings (Oscillator Reference).............................................................................84
39 Device Clock Timings (Crystal Reference).................................................................................84
40 PCI Clock Timings......................................................................................................................86
41 MII Clock Timings.......................................................................................................................86
42 UTOPIA-2 Clock Timings ...........................................................................................................86
43 Expansion Bus Clock Timings....................................................................................................86
44 PCI Bus Signal Timings..............................................................................................................88
45 UTOPIA-2 Input Timings Values ................................................................................................89
46 UTOPIA-2 Output Timings Values..............................................................................................89
47 MII Output Timings Values .........................................................................................................90
6
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
48 MII Input Timings Values ............................................................................................................90
49 MDIO Timings Values.................................................................................................................92
50 SDRAM Input Timings Values ....................................................................................................92
51 SDRAM Output Timings Values .................................................................................................93
52 Intel Multiplexed Mode Values....................................................................................................94
53 Intel Simplex Mode Values .........................................................................................................95
54 Motorola* Multiplexed Mode Values ...........................................................................................96
55 Motorola* Simplex Mode Values.................................................................................................98
56 HPI Timing Symbol Description..................................................................................................99
57 HPI – 8 Mode Write Accesses Values........................................................................................99
58 Setup/Hold Timing Values ........................................................................................................100
59 HPI-16 Multiplexed Write Accesses Values..............................................................................101
60 HPI-16 Multiplex Read Accesses Values .................................................................................102
61 HPI-16 Non-Multiplex Read Accesses Values..........................................................................104
62 HPI-16 Non-Multiplexed Write Accesses Values......................................................................105
63 High-Speed, Serial Timing Values............................................................................................108
64 Boundary-Scan Interface Timings Values ................................................................................109
65 Reset Timings Table Parameters .............................................................................................111
66
ICC and Total Average Power...................................................................................................112
Datasheet
7
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Contents
Revision History
Date
Revision
Description
Updated Intel® product branding. Change bars are retained
from the previous release of this document (003).
June 2004
004
Incorporated specification changes, specification clarifications
and document changes from the Intel® IXP4XX Product Line of
Network Processors and IXC1100 Control Plane Processor
Specification Update (252702-003).
April 2004
003
Incorporated specification changes, specification clarifications
and document changes from the Intel® IXP4XX Product Line of
Network Processors Specification Update (252702-001).
Incorporated information for the Intel® IXC1100 Control Plane
Processor.
May 2003
002
001
Initial release of this document. Document reissued, without
“Confidential” marking.
February 2003
8
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Product Features
1.0
Product Features
1.1
Product Line Features
Table 1 on page 12 describes which features apply to the Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane Processor.
• Intel XScale® Core (compliant with ARM* architecture)
— High-performance processor based on Intel XScale® Microarchitecture
— Seven/eight-stage Intel® Super-Pipelined RISC Technology
— Management unit
• 32-entry, data memory management unit
• 32-entry, instruction memory management unit
• 32-Kbyte, 32-way, set associative instruction cache
• 32-Kbyte, 32-way, set associative data cache
• 2-Kbyte, two-way, set associative mini-data cache
• 128-entry, branch target buffer
• Eight-entry write buffer
• Four-entry fill and pend buffers
— Clock speeds:
• 266 MHz
• 400 MHz
• 533 MHz
— ARM* Version V5TE Compliant
— Intel® Media Processing Technology
Multiply-accumulate coprocessor
— Debug unit
Accessible through JTAG port
• Three network processor engines (NPEs)
Used to offload typical Layer-2 networking functions such as:
— Ethernet filtering
— ATM SARing
— HDLC
• PCI interface
— 32-bit interface
— Selectable clock
• 33-MHz clock output
• 0- to 66-MHz clock input
— PCI Local Bus Specification, Rev. 2.2 compatible
Datasheet
9
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Product Features
— PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs)
— Host/option capable
— Master/target capable
— Two DMA channels
• Two MII interfaces
— 802.3 MII interfaces
— Single MDIO interface to control both MII interfaces
• UTOPIA-2 Interface
— Eight-bit interface
— Up to 33 MHz clock speed
— Five transmit and five receive address lines
• USB v 1.1 device controller
— Full-speed capable
— Embedded transceiver
— 16 endpoints
• Two high-speed, serial interfaces
— Six-wire
— Supports speeds up to 8.192 MHz
— Supports connection to T1/E1 framers
— Supports connection to CODEC/SLICs
— Eight HDLC Channels
• SDRAM interface
— 32-bit data
— 13-bit address
— 133 MHz
— Up to eight open pages simultaneously maintained
— Programmable auto-refresh
— Programmable CAS/data delay
— Support for 8 MB, minimum, up to 256 MB maximum
• Expansion interface
— 24-bit address
— 16-bit data
— Eight programmable chip selects
— Supports Intel/Motorola* microprocessors
• Multiplexed-style bus cycles
• Simplex-style bus cycles
10
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Product Features
• Encryption/Authentication
— DES
— DES 3
— AES 128-bit and 256-bit
• DSP support for:
— Texas Instruments* DSPs supporting HPI-8 bus cycles
— Texas Instruments DSPs supporting HPI-16 bus cycles
• High-speed/Console UARTs
— 1,200 baud to 921 Kbaud
— 16550 compliant
— 64-byte Tx and Rx FIFOs
— CTS and RTS modem control signals
• Internal bus performance monitoring unit
— Seven 27-bit event counters
— Monitoring of internal bus occurrences and duration events
• 16 GPIOs
• Four internal timers
• Packaging
— 492-pin PBGA
— Commercial temperature (0° to +70° C)
— Extended temperature (-40° to +85° C)
Datasheet
11
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Product Features
1.2
Processor Features
Table 1. Processor Features
Intel® IXP425
Network
Processor
B0 Step
Intel® IXP422
Network
Processor
Intel® IXP421
Network
Processor
Intel® IXP420 Intel® IXC1100
Feature
Network
Control Plane
Processor
Processor
Processor Speed
(MHz)
266/400/533
266
266
2661/400/533
266/400/533
UTOPIA 2
GPIO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
UART 0/1
HSS 0
HSS 1
MII 0
X
X
X
X
X
X
X
X
X
X
X
X
MII 1
USB
X
X
PCI
Expansion Bus
16-bit, 66-MHz 16-bit, 66-MHz 16-bit, 66-MHz 16-bit, 66-MHz 16-bit, 66-MHz
32-bit,
133-MHz
32-bit,
133-MHz
32-bit,
133-MHz
32-bit,
133-MHz
32-bit,
133-MHz
SDRAM
AES / DES / DES3
Multi-Channel HDLC
SHA-1 / MD-5
X
8
X
8
X
X
X
Commercial
Temperature
X
X
X
X
X
X
X
Extended
Temperature
1. Only the 266-MHz version of the Intel® IXP420 Network Processor supports extended temperature.
1.3
About this Document
This datasheet contains a functional overview of the Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane Processor, as well as mechanical data (package signal
locations and simulated thermal characteristics), targeted electrical specifications, and some bus
functional wave forms for the device. Detailed functional descriptions — other than parametric
performance — are published in the Intel® IXP42X Product Line of Network Processors and
IXC1100 Control Plane Processor Developer’s Manual.
Other related documents are shown in Table 2.
12
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Product Features
Table 2.
Related Documents
Document Title
Document #
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Specification Update
252702
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual
252480
Intel® IXP400 Software Specification Update
273795
252539
252539
273473
252817
—
Intel® IXP400 Software Programmer’s Guide
Intel® IXP4XX Product Line Programmer’s Guide (Version 1.1)
Intel® XScale™ Core Developer’s Manual
Intel® IXP4XX Product Line and Intel® IXC1100 Processor Hardware Design Guideline
Intel XScale® Microarchitecture Technical Summary
PCI Local Bus Specification, Rev. 2.2
—
Universal Serial Bus Specification, Revision 1.1
PC133 SDRAM Specification
—
—
Datasheet
13
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.0
Functional Overview
The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are
compliant with the ARM* Version 5TE instruction-set architecture (ISA). The Intel® IXP42X
product line and IXC1100 control plane processors are designed with Intel state-of-the-art 0.18-µ
production semiconductor process technology. This process technology — along with the
compactness of the Intel XScale core, the ability to simultaneously process up to three integrated
network processing engines (NPEs), and numerous dedicated-function peripheral interfaces —
enables the IXP42X product line and IXC1100 control plane processors to operate over a wide
range of low-cost networking applications, with industry-leading performance.
As indicated in Figure 1 through Figure 4, the Intel® IXP42X product line and IXC1100 control
plane processors combine many features with the Intel XScale core to create a highly integrated
processor applicable to LAN/WAN-based networking applications in addition to other embedded
networking applications.
This section briefly describes the main features of the product. For detailed functional descriptions,
see the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
Figure 1.
Intel® IXP425 Network Processor Block Diagram
HSS-W
HSS-V
Utopia 2
WAN/Voice NPE
UTOPIA
(Max 24 xDSL PHYs)
AAL, HSS, HDLC
Media Independent Interface
Media Independent Interface
Ethernet
NPE A
Ethernet MAC
133 MHz Advanced
High-Performance Bus
Queue
Status
Bus
Ethernet
NPE B
Ethernet MAC
SHA-1/MD5,
DES/3DES, AES
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
UART
921Kbaud
Interrupt
Controller
Bridge
Timers
Arbiter
66 MHz Advanced Peripheral Bus
Bridge
133 MHz Advanced High-
Performance Bus
Intel XScale® Core
266/400/533 MHz
UART
921Kbaud
PMU
GPIO
USB
(AHB)
Controller Controller
PCI
Exp Bus
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Controller
Test Logic Unit
16 Pins
JTAG
32-Bit
16-Bit
B1563-02
14
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
Figure 2.
Intel® IXP422 Network Processor Block Diagram
Media Independent Interface
Media Independent Interface
Ethernet
NPE A
Ethernet MAC
133 MHz Advanced
High-Performance Bus
Queue
Status
Bus
Ethernet
NPE B
Ethernet MAC
SHA-1/MD5,
DES, 3DES, AES
Arbiter
SDRAM
Controller
8 - 256 MB
32-Bit
Queue
Manager
8 KB SRAM
UART
921Kbaud
Interrupt
Controller
Bridge
Timers
Arbiter
66 MHz Advanced Peripheral Bus
Bridge
133 MHz Advanced High-
Performance Bus
Intel XScale® Core
UART
921Kbaud
PMU
(AHB)
GPIO
USB
Controller Controller
266 MHz
PCI
Controller
Exp Bus
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Test Logic Unit
16 Pins
JTAG
32-Bit
16-Bit
B1566-02
Figure 3.
Intel® IXP421 Network Processor Block Diagram
HSS-W
HSS-V
Utopia 2
WAN/Voice NPE
UTOPIA
(Max 4 xDSL PHYs)
AAL, HSS
133 MHz Advanced
High-Performance Bus
Media Independent Interface
Queue
Status
Bus
Ethernet
NPE A
Ethernet MAC
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
UART
921Kbaud
Interrupt
Controller
Bridge
Timers
Arbiter
66 MHz Advanced Peripheral Bus
Bridge
133 MHz Advanced High-
Performance Bus
Intel XScale® Core
UART
921Kbaud
PMU
(AHB)
GPIO
USB
Controller Controller
266 MHz
PCI
Controller
Exp Bus
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Test Logic Unit
16 Pins
JTAG
32-Bit
16-Bit
B1565-02
Datasheet
15
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
Figure 4.
Intel® IXP420 Network Processor Block Diagram
Media Independent Interface
Ethernet
NPE A
Ethernet MAC
133 MHz Advanced
High-Performance Bus
Media Independent Interface
Queue
Status
Bus
Ethernet
NPE B
Ethernet MAC
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
UART
921Kbaud
Interrupt
Controller
Bridge
Timers
Arbiter
66 MHz Advanced Peripheral Bus
Bridge
133 MHz Advanced High-
Performance Bus
Intel XScale® Core
UART
921Kbaud
PMU
GPIO
USB
(AHB)
Controller Controller
266/400/533 MHz
PCI
Exp Bus
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Controller
Test Logic Unit
16 Pins
JTAG
32-Bit
16-Bit
B1564-02
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.1
Functional Units
The following sections briefly describe the functional units and their interaction in the system. For
more detailed information, refer to the Intel® IXP42X Product Line of Network Processors and
IXC1100 Control Plane Processor Developer’s Manual.
Unless otherwise specified, the functional descriptions apply to all processors in the IXP42X
product line and IXC1100 control plane processors. Refer to Table 1 on page 12 and Figure 1 on
page 14 through Figure 4 for specific information on supported interfaces
2.1.1
Network Processor Engines (NPEs)
The network processor engines (NPEs) are dedicated-function processors containing hardware
coprocessors integrated into the IXP42X product line and IXC1100 control plane processors. The
NPEs are used to off-load processing functions required by the Intel XScale core.
These NPEs are high-performance, hardware-multi-threaded processors with additional
local-hardware-assist functionality used to off-load highly processor-intensive functions such as
MII (MAC), CRC checking/generation, AAL 2, AES, DES, SHA-1, and MD5. All instruction code
for the NPEs are stored locally with a dedicated instruction memory bus and dedicated data
memory bus.
These NPEs support processing of the dedicated peripherals that can include:
• A Universal Test and Operation PHY Interface for ATM (UTOPIA) 2 interface
• Two High-Speed Serial (HSS) interfaces
• Two Media-Independent Interfaces (MII)
Table 3 specifies which devices, in the IXP42X product line and IXC1100 control plane
processors, have which of these capabilities.
Table 3. Processor Functions
AES / DES / Multi-Channel SHA-1 /
Device
UTOPIA HSS MII 0 MII 1
DES3
HDLC
MD-5
Intel® IXP425 Network
Processor, B-Step
Intel® IXP422 Network
Processor
X
X
X
X
X
X
X
X
X
X
8
X
X
X
Intel® IXP421 Network
Processor
X
X
8
Intel® IXP420 Network
Processor
X
X
Intel® IXC1100 Control
Plane Processor
The NPE core is a hardware-multi-threaded processor engine that is used to accelerate functions
that are difficult to achieve high performance in a standard RISC processor. Each NPE core is a
133-MHz processor core that has self-contained instruction memory and self-contained data
memory that operate in parallel.
Datasheet
17
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
In addition to having separate instruction/data memory and local-code store, the NPE core supports
hardware multi-threading with support for multiple contexts. The support of hardware
multi-threading creates an efficient processor engine with minimal processor stalls due to the
ability of the processor core to switch contexts in a single clock cycle, based on a
prioritized/preemptive basis. The prioritized/preemptive nature of the context switching allows
time-critical applications to be implemented in a low-latency fashion — which is required when
processing multi-media applications.
The NPE core also connects several hardware-based coprocessors that are used to implement
functions that are difficult for a processor to implement. These functions include:
• Serialization/De-serialization
• DES/3DES/AES
• MD5
• CRC checking/generation
• SHA-1
• HDLC bit stuffing/de-stuffing
These coprocessors are implemented in hardware, enabling the coprocessors and the NPE
processor core to operate in parallel.
The combined forces of the hardware multi-threading, local-code store, independent instruction
memory, independent data memory, and parallel processing allows the Intel XScale core to be
utilized for application purposes. The multi-processing capability of the peripheral interface
functions allows unparalleled performance to be achieved by the application running on the Intel
XScale core.
2.1.2
Internal Bus
The internal bus architecture of the IXP42X product line and IXC1100 control plane processors is
designed to allow parallel processing to occur and to isolate bus utilization, based on particular
traffic patterns. The bus is segmented into three major buses: the North AHB, South AHB, and
APB.
2.1.2.1
North AHB
The North AHB is a 133.32-MHz, 32-bit bus that can be mastered by the NPEs. The targets of the
North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB bridge allows the NPEs
to access the peripherals and internal targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted predominately to the
queue manager. Transfers to the AHB/AHB bridge may be “posted,” when writing, or “split,”
when reading.
When a transaction is “posted,” a master on the North AHB requests a write to a peripheral on the
South AHB. If the AHB/AHB Bridge has a free FIFO location, the write request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the write on the South AHB, when it can obtain access to the peripheral on the South AHB. The
North AHB is released to complete another transaction.
When a transaction is “split,” a master on the North AHB requests a read of a peripheral on the
South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the read on the South AHB, when it can obtain access to the peripheral on the South AHB.
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
Once the AHB/AHB bridge has obtained the read information from the peripheral on the South
AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has
the data for the master that requested the “split” transfer. The master on the North AHB — that
requested the split transfer — will arbitrate for the North AHB and transfer the read data from the
AHB/AHB bridge. The North AHB is released to complete another transaction while the North
AHB master — that requested the “split” transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to another
master on the North AHB — enabling the North AHB to achieve maximum efficiency. Transfers to
the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed
between the NPEs on the North AHB and the SDRAM.
2.1.2.2
2.1.2.3
South AHB
The South AHB is a 133.32-MHz, 32-bit bus that can be mastered by the Intel XScale® Core, PCI
controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI
interface, queue manager, expansion bus, or the APB/AHB bridge.
Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the APB.
APB Bus
The APB Bus is a 66.66-MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be mastered by
the AHB/APB bridge only. The targets of the APB bus can be:
• High-speed UART interface
• USB v 1.1 interface
• Console UART interface
• All NPEs
• Internal bus performance monitoring unit
(IBPMU)
• Interrupt controller
• GPIO
• Timers
The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code
download and configuration.
2.1.3
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated into most of
the IXP42X product line and IXC1100 control plane processors with separate media-access
controllers and independent network processing engines. (See Table 3 on page 17.)
The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces
and off-loading of processing required by the Intel XScale® Core. The IXP42X product line and
IXC1100 control plane processors are compliant with the IEEE, 802.3 specification.
In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane processors
include a single management data interface that is used to configure and control PHY devices that
are connected to the MII interface.
Datasheet
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.1.4
UTOPIA 2
The integrated, UTOPIA-2 interface works with a network processing engine, for several of the
IXP42X product line and IXC1100 control plane processors. (See Table 3 on page 17.)
The UTOPIA-2 interface supports a single- or a multiple-physical-interface configuration with
cell-level or octet-level handshaking. The network processing engine handles segmentation and
reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This
allows parallel processing of data traffic on the UTOPIA-2 interface, off-loading processor
overhead required by the Intel XScale® Core.
The IXP42X product line and IXC1100 control plane processors are compliant with the ATM
Forum, UTOPIA Level-2 Specification, Revision 1.0.
2.1.5
USB Interface
The integrated USB 1.1 interface is a device-only controller. The interface supports full-speed
operation and 16 endpoints and includes an integrated transceiver.
There are:
• Six isochronous endpoints (three input and three output)
• One control endpoints
• Three interrupt endpoints
• Six bulk endpoints (three input and three output)
2.1.6
2.1.7
PCI Controller
The IXP42X product line and IXC1100 control plane processors’ PCI controller is compatible with
the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable
of operating as either a host or an option (i.e. not the Host) For more information on PCI Controller
support and configuration see the Intel® IXP42X Product Line of Network Processors and IXC1100
Control Plane Processor Developer’s Manual
SDRAM Controller
The memory controller manages the interface to external SDRAM memory chips. The interface:
• Operates at 133.32 MHz (which is 4 * OSC_IN input pin.)
• Supports eight open pages simultaneously
• Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte
The memory controller only supports 32-bit memory. If a x16 memory chip is used, a minimum of
two memory chips would be required to facilitate the 32-bit interface required by the IXP42X
product line and IXC1100 control plane processors. A maximum of four SDRAM memory chips
may be attached to the processors. For more information on SDRAM support and configuration see
the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
The memory controller internally interfaces to the North AHB and South AHB with independent
interfaces. This architecture allows SDRAM transfers to be interleaved and pipelined to achieve
maximum possible efficiency.
The maximum burst size supported to the SDRAM interface is eight 32-bit words. This burst size
allows the best efficiency/fairness performance between accesses from the North AHB and the
South AHB.
2.1.8
Expansion Bus
The expansion interface allows easy and — in most cases — glue-less connection to peripheral
devices. It also provides input information for device configuration after reset. Some of the
peripheral device types are flash, ATM control interfaces, and DSPs used for voice applications.
(Some voice configurations can be supported by the HSS interfaces and the Intel XScale® Core,
implementing voice-compression algorithms.)
The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to
16 Mbytes, using 24 address lines for each of the eight independent chip selects.
Accesses to the expansion bus interface consists of five phases. Each of the five phases can be
lengthened or shortened by setting various configuration registers on a per-chip-select basis. This
feature allows the IXP42X product line and IXC1100 control plane processors to connect to a wide
variety of peripheral devices with varying speeds.
The expansion bus interface supports Intel or Motorola* microprocessor-style bus cycles. The bus
cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for
each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments HPI-8 or
HPI-16 style accesses for DSPs.
The expansion bus interface is an asynchronous interface to externally connected chips. However,
a clock must be supplied to the IXP42X product line and IXC1100 control plane processors’
expansion bus interface for the interface to operate. This clock can be driven from GPIO 15 or an
external source. The maximum clock rate that the expansion bus interface can accept is
66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration information
from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are
used to tie the signals to particular logic levels. (For additional details, see “Package and Pinout
Information” on page 42.)
2.1.9
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer speeds from
512 KHz to 8.192 MHz, for some models of the IXP42X product line and IXC1100 control plane
processors. (See Table 3 on page 17.)
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the
IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are
capable of supporting various protocols, based on the implementation of the code developed for the
network processor engine core. For a list of supported protocols, see the Intel® IXP400 Software
Programmer’s Guide.
Datasheet
21
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.1.10
High-Speed and Console UARTs
The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive
buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the
16550 UART specification.
The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The interface
support configurations of:
• Five, six, seven, or eight data-bit transfers
• One or two stop bits
• Even, odd, or no parity
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also are available
with the interface for hardware flow control.
2.1.11
GPIO
There are 16 GPIO pins supported by the IXP42X product line and IXC1100 control plane
processors. GPIO pins 0 through 13 can be configured to be general-purpose input or
general-purpose output. Additionally, GPIO pins 0 through 12 can be configured to be an interrupt
input.
GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-clock
configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 14
is configured as an input, upon reset.
GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-clock
configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 15
is configured as a clock output, upon reset. GPIO Pin 15 can be used to clock the expansion
interface, after reset.
2.1.12
2.1.13
Internal Bus Performance Monitoring Unit (IBPMU)
The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit counters
that may be used to capture predefined durations or occurrence events on the North AHB, South
AHB, or SDRAM controller page hits/misses.
Interrupt Controller
The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to
allow an extension of the Intel XScale® Core FIQ and IRQ interrupt sources. These sources can
originate from some external GPIO pins or internal peripheral interfaces.
The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The
interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining interrupts are prioritized
in ascending order. For example, Interrupt 8 has a higher priority than 9, 9 has a higher priority than
10, and 30 has a higher priority that 31.
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.1.14
2.1.15
Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal timers
operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task scheduling and prevent
software lock-ups. The device has four 32-bit counters:
• Watch-Dog Timer
• Timestamp Timer
• Two general-purpose timers
AHB Queue Manager
The AHB Queue Manager (AQM) provides queue functionality for various internal blocks. It
maintains the queues as circular buffers in an embedded 8KB SRAM. It also implements the status
flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and entry size.
Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs
and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to the
NPE condition select logic) and two interrupts to the Intel XScale core. The AHB interface is used
for configuration of the AQM and provides access to queues, queue status and SRAM. Individual
queue status for queues 0-31 is communicated to the NPEs via the flag bus. Combined queue status
for queues 32-63 are communicated to the NPEs via the event bus. The two interrupts, one for
queues 0-31 and one for queues 32-63, provide status interrupts to the Intel XScale core.
2.2
Intel XScale® Core
The Intel XScale® Core technology is compliant with the ARM* Version 5TE instruction-set
architecture (ISA). The Intel XScale core — shown in Figure 5 — is designed with Intel
state-of-the-art, 0.18-µ-production semiconductor process technology. This process technology
enables the Intel XScale core to operate over a wide speed and power range, producing
industry-leading mW/MIPS performance.
Intel XScale core features include:
• Seven/eight-stage super-pipeline promotes high-speed, efficient core performance
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch choices
• 32-entry instruction memory-management unit for logical-to-physical address translation,
access permissions, I-cache attributes
• 32-entry data-memory management unit for logical-to-physical address translation, access
permissions, D-cache attributes
• 32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by
multi-cycle memory accesses
• 32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses
• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing” of the
D-cache
• Four-entry fill-and-pend buffers to promote core efficiency by allowing “hit-under-miss”
operation with data caches
Datasheet
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
• Eight-entry write buffer allows the core to continue execution while data is written to memory
• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with
40-bit accumulation for efficient, high-quality media and signal processing
• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle
counter for analysis of hit rates, etc.
This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of
internal bus performance.
• JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for
flow-change messages) to debug programs
Figure 5.
Intel XScale® Core Block Diagram
Branch Target Cache
FIQ
Interrupt
Request
IRQ
M
M
Instruction Cache
Instruction
32 KB
U
South
AHB
Bus
Execution
Core
Data Cache
Data
Address
M
M
32 KB
Coprocessor Interface
U
Mini-Data Cache
2 KB
Data
Multiply
Accumulate
System
Management
Debug/
PMU
JTAG
A9568-02
2.2.1
Super Pipeline
The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes.
The integer pipe has seven stages:
• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
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Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
• Integer Writeback
The memory pipe has eight stages:
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
. . . then finish with the following memory stages:
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
The MAC pipe has six to nine stages:
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
. . . then finish with the following MAC stages:
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or
MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to successfully
predict the outcome of branch instructions. The branch target buffer provides such a means.
2.2.2
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the target address
associated with the branch instruction, and a previous history of the branch being taken or not
taken. The history is recorded as one of four states:
• Strongly taken
• Weakly taken
• Weakly not taken
• Strongly not taken
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or weakly
taken, the instruction at the branch target address is fetched. When its history is strongly or weakly
not-taken, the next sequential instruction is fetched. In either case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is taken. This
data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when
present).
Successfully predicted branches avoid any branch-latency penalties in the super pipeline.
Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super
pipeline.
Datasheet
25
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
2.2.3
Instruction Memory Management Unit (IMMU)
For instruction pre-fetches, the IMMU controls logical-to-physical address translation, memory
access permissions, memory-domain identifications, and attributes (governing operation of the
instruction cache). The IMMU contains a 32-entry, fully associative instruction-translation,
look-aside buffer (ITLB) that has a round-robin replacement policy. ITLB entries zero through 30
can be locked.
When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The
descriptor contains information for logical-to-physical address translation, memory-access
permissions, memory-domain identifications, and attributes governing operation of the I-cache.
The IMMU then continues the instruction pre-fetch by using the address translation just entered
into the ITLB. When an instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch
using the address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When an
instruction pre-fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a pre-fetch abort is sent to the core for exception processing. The IMMU and
DMMU can be enabled or disabled together.
2.2.4
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory-access
permissions, memory-domain identifications, and attributes (governing operation of the data cache
or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative
data-translation, look-aside buffer (DTLB) that has a round-robin replacement policy. DTLB
entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism
that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor
contains information for logical-to-physical address translation, memory-access permissions,
memory-domain identifications, and attributes (governing operation of the D-cache or mini-data
cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into the DTLB.
When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation
already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a data fetch
is attempted to an area of memory in violation of access permissions, the attempt is aborted and a
data abort is sent to the core for exception processing.
The IMMU and DMMU can be enabled or disabled together.
2.2.5
Instruction Cache (I-Cache)
The I-cache can contain high-use, multiple-code segments or entire programs, allowing the core
access to instructions at core frequencies. This prevents core stalls caused by multi-cycle accesses
to external memory.
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Functional Overview
The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way
contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word),
and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are
replaceable via a round-robin policy.
The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the
ITLB of the IMMU — provide some control over an enabled I-cache.
When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical
word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next
instruction to be accessed from the I-cache, but only when its data operands do not depend on the
execution results of the instruction being fetched via the queue.
2.2.6
Data Cache (D-Cache)
The D-cache can contain high-use data such as lookup tables and filter coefficients, allowing the
core access to data at core frequencies. This prevents core stalls caused by multi-cycle accesses to
external memory.
The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways and each
way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty
bits (one for each of two eight-byte groupings in a line), and one valid bit. For each of the 32 sets,
zero through 28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are
replaceable via a round-robin policy.
The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within
the descriptors, contained in the DTLB of the DMMU, provide significant control over an enabled
D-cache. These bits specify cache operating modes such as read and write allocate, write-back,
write-through, and D-cache versus mini-data cache targeting.
The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide
“hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is
encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for
data that is to be stored to memory.
2.2.7
Mini-Data Cache
The mini-data cache can contain frequently changing data streams such as MPEG video, allowing
the core access to data streams at core frequencies. This prevents core stalls caused by multi-cycle
accesses to external memory. The mini-data cache relieves the D-cache of data “thrashing” caused
by frequently changing data streams.
The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and
each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two
dirty bits (one for each of two eight-byte groupings in a line), and a valid bit. The mini-data cache
uses a round-robin replacement policy, and cannot be locked.
The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits
contained within a coprocessor register specify operating modes write and/or read allocate,
write-back, and write-through.
Datasheet
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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
The mini-data cache (and D-cache) work with the load buffer and pend buffer to provide
“hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is
encountered. The mini-data cache (and D-cache) works in conjunction with the write buffer for
data that is to be stored to memory.
2.2.8
Fill Buffer (FB) and Pend Buffer (PB)
The four-entry fill buffer (FB) works with the core to hold non-cacheable loads until the bus
controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and
mini-data cache to provide “hit-under-miss” capability, allowing the core to seek other data in the
caches while “miss” data is being fetched from memory.
The FB can contain up to four unique “miss” addresses (logical), allowing four “misses” before the
core is stalled. The PB holds up to four addresses (logical) for additional “misses” to those
addresses that are already in the FB. A coprocessor register can specify draining of the fill and pend
(write) buffers.
2.2.9
Write Buffer (WB)
The write buffer (WB) holds data for storage to memory until the bus controller can act on it. The
WB is eight entries deep, where each entry holds 16 bytes. The WB is constantly enabled and
accepts data from the core, D-cache, or mini-data cache.
Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled. When
coalescing is disabled, stores to memory occur in program order regardless of the attribute bits
within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within
the descriptors located in the DTLB are examined to determine when coalescing is enabled for the
destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, data
entering the WB can coalesce with any of the eight entries (16 bytes) and be stored to the
destination memory region, but possibly out of program order.
Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits
within the descriptors located in the DTLB causes the core to stall until the store completes. A
coprocessor register can specify draining of the write buffer.
2.2.10
Multiply-Accumulate Coprocessor (CP0)
For efficient processing of high-quality, media-and-signal-processing algorithms, CP0 provides
40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD), and 32 x 32 signed multiplies. Special MAR
and MRA instructions are implemented to move the 40-bit accumulator to two core-general
registers (MAR) and move two core-general registers to the 40-bit accumulator (MRA). The 40-bit
accumulator can be stored or loaded to or from D-cache, mini-data cache, or memory using two
STC or LDC instructions.
The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low,
high/low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core
general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and
added to the 40-bit accumulator.
Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low
16-bits of a packed 32-bit, core-general register (multiplier) and another packed 32-bit,
core-general register (multiplicand) to produce two 16-bits products that are both sign-extended to
40 bits and added to the 40-bit accumulator.
28
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Overview
The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, core-general register
(multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product
where the 40 LSBs are added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32
multiply-accumulate instructions complete in a single cycle.
2.2.11
2.2.12
Performance Monitoring Unit (PMU)
The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter.
The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit
rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.
Debug Unit
The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1 JTAG port
consists of a test access port (TAP) controller, boundary-scan register, instruction and data
registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.
The debug unit — when used with debugger application code running on a host system outside of
the Intel XScale core — allows a program, running on the Intel XScale core, to be debugged. It
allows the debugger application code or a debug exception to stop program execution and redirect
execution to a debug-handling routine.
Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug
breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the
debugger application code can examine or modify the core’s state, coprocessor state, or memory.
The debugger application code can then restart program execution.
The debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint
registers; and a hardware, data-breakpoint control register. The second data-breakpoint register can
be alternatively used as a mask register for the first data-breakpoint register.
A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A
JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the
mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction cache to hold a debug handler).
Datasheet
29
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
3.0
Functional Signal Descriptions
Listed in the signal definition tables — starting at Table 5, “SDRAM Interface” on page 31 — are
pull-up an pull-down resistor recommendations that are required when the particular enabled
interface is not being used in the application. These external resistor requirements are only needed
if the particular model of Intel® IXP42X product line and IXC1100 control plane processors has
the particular interface enabled and the interface is not required in the application.
Warning: All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V tolerant.
Disabled features, within the IXP42X product line and IXC1100 control plane processors, do not
require external resistors as the processor will have internal pull-up or pull-down resistors enabled
as part of the disabled interface.
Table 4 presents the legend for interpreting the Type field in the other tables in this section of the
document.
To determine which interfaces are not enabled within the IXP42X product line and IXC1100
control plane processors, see Table 1 on page 12.
Table 4.
Signal Type Definitions
Symbol
Description
I
O
Input pin only
Output pin only
I/O
OD
PWR
GND
1
Pin can be either an input or output
Open Drain pin
Power pin
Ground pin
Driven to Vcc
0
Driven to Vss
X
Driven to unknown state
Input is disabled
ID
H
Pulled up to Vcc
L
Pulled to Vss
PD
Z
Pull-up Disabled
Output Disabled
VO
A valid output level is driven, allowed states -- 1, 0, H, Z
Need to drive a valid input level, allowed states - 1, 0, H,
Z
VI
PE
Tri
N/C
-
Pull-up Enabled, equivalent to H
Output Only/Tristatable
No Connect
Pin must be connected as described
30
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
This section’s other tables include:
• Table 5 — SDRAM Interface signals
• Table 6 — PCI Controller signals
• Table 7 — High-Speed, Serial Interface 0 signals
• Table 8 — High-Speed, Serial Interface 1 signals
• Table 9 — MII Interfaces signals
• Table 10 — UTOPIA-2 Interface signals
• Table 11 — Expansion Bus Interface signals
• Table 12 — UART Interfaces signals
• Table 13 — USB Interface signals
• Table 14 — Oscillator Interface signals
• Table 15 — GPIO Interface signals
• Table 16 — JTAG Interface signals
• Table 17 — System Interface signals
• Table 18 — Power Interface signals
Note:
1. The Power On Reset Column of the Tables indicate the state of the signals during the Power On Reset
process
2. The Reset Column of the Tables indicate the state of the signals during the Reset.
Table 5.
SDRAM Interface (Sheet 1 of 2)
Power
Name
on
Reset† Type†
Description
Reset†
SDRAM Address: A0-A12 signals are output during the READ/WRITE
commands and ACTIVE commands to select a location in memory to act
upon.
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CLKOUT
SDM_BA[1:0]
Z
Z
0
1
0
0
1
O
I/O
O
SDRAM Data: Bidirectional data bus used to transfer data to and from the
SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the rising edge
of SDM_CLKOUT. All output signals are driven with respect to the rising
edge of SDM_CLKOUT.
Z
Z
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the
current command is attempting to access.
O
SDRAM Row Address strobe/select (active low): Along with
SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals determines the
current command to be executed.
SDM_RAS_N
Z
Z
O
SDRAM Column Address strobe/select (active low): Along with
SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals determines the
current command to be executed.
SDM_CAS_N
SDM_CS_N[1:0]
SDM_WE_N
1
1
1
O
O
O
SDRAM Chip select (active low): CS# enables the command decoder in
the external SDRAM when logic low and disables the command decoder
in the external SDRAM when logic high.
Z
Z
SDRAM Write enable (active low): Along with SDM_CAS_N,
SDM_RAS_N, and SDM_CS_N signals determines the current command
to be executed.
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
31
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 5.
SDRAM Interface (Sheet 2 of 2)
Power
Name
on
Reset† Type†
Description
Reset†
SDRAM Clock Enable: CKE is driving high to activate the clock to an
external SDRAM and driven low to de-activate the CLK to an external
SDRAM.
SDM_CKE
Z
Z
1
0
O
O
SDRAM Data bus mask: DQM is used to byte select data during
read/write access to an external SDRAM.
SDM_DQM[3:0]
†
For a legend of the Type codes, see Table 4 on page 30.
32
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 6.
PCI Controller (Sheet 1 of 2)
Power
On
Name
PCI_AD[31:0]
PCI_CBE_N[3:0]
PCI_PAR
Reset† Type†
Description
Reset†
PCI Address/Data bus used to transfer address and bidirectional data to
and from multiple PCI devices.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
Z
Z
Z
Z
I/O
I/O
I/O
system.
PCI Command/Byte Enables is used as a command word during PCI address
cycles and as byte enables for data cycles.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
Z
Z
system.
PCI Parity used to check parity across the 32 bits of PCI_AD and the
four bits of PCI_CBE_N.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final data
phase of a given transaction.
PCI_FRAME_N
Z
Z
I/O
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Target Ready informs that the target of the PCI bus is ready to
complete the current data phase of a given transaction.
PCI_TRDY_N
PCI_IRDY_N
PCI_STOP_N
Z
Z
Z
Z
Z
Z
I/O
I/O
I/O
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Initiator Ready informs the PCI bus that the initiator is ready to
complete the transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Stop indicates that the current target is requesting the current initiator
to stop the current transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Parity Error asserted when a PCI parity error is detected — between the
PCI_PAR and associated information on the PCI_AD bus and PCI_CBE_N —
during all PCI transactions, except for Special Cycles. The agent receiving
data will drive this signal.
PCI_PERR_N
PCI_SERR_N
Z
Z
Z
Z
I/O
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI System Error asserted when a parity error occurs on special cycles or
any other error that will cause the PCI bus not to function properly. This
signal can function as an input or an open drain output.
I/OD
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Device Select:
•
When used as an output, PCI_DEVSEL_N indicates that device has
decoded that address as the target of the requested transaction.
PCI_DEVSEL_N
Z
Z
I/O
•
When used as an input, PCI_DEVSEL_N indicates if any device on
the PCI bus exists with the given address.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Initialization Device Select is a chip select during configuration reads
and writes.
PCI_IDSEL
Z
Z
Z
Z
I
I
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
PCI arbitration request: Used by the internal PCI arbiter to allow an agent
to request the PCI bus.
PCI_REQ_N[3:1]
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI arbitration request:
•
When configured as an input (PCI arbiter enabled), the internal PCI
arbiter will allow an agent to request the PCI bus.
PCI_REQ_N[0]
Z
Z
Z
Z
I/O
O
•
When configured as an output (PCI arbiter disabled), the pin will be
used to request access to the PCI bus from an external arbiter.
Should be pulled high with a 10-KΩ resistor, when the PCI bus is not being
utilized in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to allow an
agent to claim control of the PCI bus.
PCI_GNT_N[3:1]
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
33
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 6.
PCI Controller (Sheet 2 of 2)
Power
Reset† Type†
Description
On
Name
Reset†
PCI arbitration grant:
•
When configured as an output (PCI arbiter enabled), the internal PCI
arbiter to allow an agent to claim control of the PCI bus.
PCI_GNT_N[0]
Z
Z
I/O
•
When configured as an input (PCI arbiter disabled), the pin will be
used to claim access of the PCI bus from an external arbiter.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI interrupt: Used to request an interrupt.
PCI_INTA_N
PCI_CLKIN
Z
Z
Z
O/D
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Clock: provides timing for all transactions on PCI. All PCI signals —
except INTA#, INTB#, INTC#, and INTD# — are sampled on the rising edge of
CLK and timing parameters are defined with respect to this edge. The PCI
clock rate can operate at up to 66 MHz.
VI
I
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
†
For a legend of the Type codes, see Table 4 on page 30.
Table 7.
High-Speed, Serial Interface 0
Power
Reset† Type†
Description
On
Name
Reset†
The High-Speed Serial (HSS) transmit frame signal can be configured as
an input or an output to allow an external source become synchronized
with the transmitted data. Often known as a Frame Sync signal.
Configured as an input upon reset.
HSS_TXFRAME0
HSS_TXDATA0
Z
Z
Z
Z
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Transmit data out. Open Drain output.
O/D
Must be pulled high with a 10-KΩ resistor to VCCP
.
The High-Speed Serial (HSS) transmit clock signal can be configured as an
input or an output. The clock can be a frequency ranging from 512 KHz to
8.192 MHz. Used to clock out the transmitted data. Configured as an input
upon reset. Frame sync and data can be selected to be generated on the
rising or falling edge of the transmit clock.
HSS_TXCLK0
Z
Z
Z
Z
I/O
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
The High-Speed Serial (HSS) receive frame signal can be configured as
an input or an output to allow an external source to become
synchronized with the received data. Often known as a Frame Sync
signal. Configured as an input upon reset.
HSS_RXFRAME0
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Receive data input. Can be sampled on the rising or falling edge of the
receive clock.
HSS_RXDATA0
HSS_RXCLK0
Z
Z
VI
Z
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
The High-Speed Serial (HSS) receive clock signal can be configured as
an input or an output. The clock can be from 512 KHz to 8.192 MHz.
Used to sample the received data. Configured as an input upon reset.
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
34
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 8.
High-Speed, Serial Interface 1
Power
On
Name
Reset† Type†
Description
Reset†
The High-Speed Serial (HSS) transmit frame signal can be configured as
an input or an output to allow an external source to be synchronized with
the transmitted data. Often known as a Frame Sync signal. Configured as
an input upon reset.
HSS_TXFRAME1
HSS_TXDATA1
Z
Z
Z
Z
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Transmit data out. Open Drain output.
O/D
Must be pulled high with a 10-KΩ resistor to VCCP
.
The High-Speed Serial (HSS) transmit clock signal can be configured as
an input or an output. The clock can be a frequency ranging from 512 KHz
to 8.192 MHz. Used to clock out the transmitted data. Configured as an
input upon reset. Frame sync and Data can be selected to be generated
on the rising or falling edge of the transmit clock.
HSS_TXCLK1
Z
Z
Z
Z
I/O
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
The High-Speed Serial (HSS) receive frame signal can be configured as
an input or an output to allow an external source to be synchronized with
the received data. Often known as a Frame Sync signal. Configured as an
input upon reset.
HSS_RXFRAME1
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Receive data input. Can be sampled on the rising or falling edge of the
receive clock.
HSS_RXDATA1
HSS_RXCLK1
Z
Z
VI
Z
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
The High-Speed Serial (HSS) receive clock signal can be configured as
an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used
to sample the received data. Configured as an input upon reset.
I/O
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
†
For a legend of the Type codes, see Table 4 on page 30.
Table 9.
MII Interfaces (Sheet 1 of 2)
Power
On
Name
Reset† Type†
Description
Reset†
Externally supplied transmit clock.
ETH_TXCLK0
•
•
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
Transmit data bus to PHY, asserted synchronously with respect to
ETH_TXCLK0.
ETH_TXDATA0[3:0]
ETH_TXEN0
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on the MII
interface. Asserted synchronously, with respect to ETH_TXCLK0, at the
first nibble of the preamble and remains asserted until all the nibbles of a
frame are presented.
Externally supplied receive clock.
ETH_RXCLK0
•
•
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
35
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 9.
MII Interfaces (Sheet 2 of 2)
Power
On
Name
Reset† Type†
Description
Reset†
Receive data bus from PHY, data sampled synchronously with respect
to ETH_RXCLK0
ETH_RXDATA0[3:0]
Z
VI
I
•
Should be pulled low through a 10-KΩ resistor when not being
utilized in the system.
Receive data valid, used to inform the MII interface that the Ethernet
PHY is sending data. Should be pulled low through a 10-KΩ resistor
when not being utilized in the system.
ETH_RXDV0
ETH_COL0
ETH_CRS0
Z
Z
VI
VI
I
I
Asserted by the PHY when a collision is detected by the PHY. Should be
pulled low through a 10-KΩ resistor when not being utilized in the
system.
Asserted by the PHY when the transmit medium or receive medium is
active. De-asserted when both the transmit and receive medium are
idle. Remains asserted throughout the duration of a collision condition.
PHY asserts CRS asynchronously and de-asserts synchronously, with
respect to ETH_RXCLK0. Should be pulled low through a 10-KΩ resistor
when not being utilized in the system.
Z
VI
I
Management data output. Provides the write data to both PHY devices
connected to each MII interface.
ETH_MDIO
ETH_MDC
Z
Z
Z
Z
I/O
O
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
Management data clock. Management data interface clock is used to
clock the MDIO signal as an output and sample the MDIO as an input.
The ETH_MDC is an input on power up and can be configured to be an
output through an Intel API as documented in the Intel® IXP400
Software Programmer’s Guide.
Externally supplied transmit clock.
ETH_TXCLK1
•
•
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
Transmit data bus to PHY, asserted synchronously with respect to
ETH_TXCLK1.
ETH_TXDATA1[3:0]
ETH_TXEN1
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on the MII
interface. Asserted synchronously, with respect to ETH_TXCLK1, at the
first nibble of the preamble, and remains asserted until all the nibbles of
a frame are presented.
Externally supplied receive clock.
ETH_RXCLK1
•
•
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
Z
Z
VI
VI
I
I
Should be pulled low through a 10-KΩ resistor when not being utilized in the
system.
Receive data bus from PHY, data sampled synchronously, with respect
to ETH_RXCLK1.
•
ETH_RXDATA1[3:0]
ETH_RXDV1
Should be pulled low through a 10-KΩ resistor when not being
utilized in the system.
Receive data valid, used to inform the MII interface that the Ethernet
PHY is sending data.
Z
Z
VI
VI
I
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
Asserted by the PHY when a collision is detected by the PHY.
ETH_COL1
ETH_CRS1
•
Should be pulled low through a 10-KΩ resistor when not being
utilized in the system.
Asserted by the PHY when the transmit medium or receive medium are
active. De-asserted when both the transmit and receive medium are
idle. Remains asserted throughout the duration of collision condition.
PHY asserts CRS asynchronously and de-asserts synchronously with
respect to ETH_RXCLK1.
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
†
For a legend of the Type codes, see Table 4 on page 30.
36
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 10.
UTOPIA-2 Interface (Sheet 1 of 2)
Power
On
Name
Reset† Type†
Description
Reset†
UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This
signal is used to synchronize all UTOPIA-transmit outputs to the rising
edge of the UTP_OP_CLK.
UTP_OP_CLK
Z
VI
I
This signal should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
UTOPIA flow control output signal. Also known as the TXENB_N
signal.
Used to inform the selected PHY that data is being transmitted to the
PHY. Placing the PHY’s address on the UTP_OP_ADDR — and
bringing UTP_OP_FCO to logic 1, during the current clock — followed
by the UTP_OP_FCO going to a logic 0, on the next clock cycle,
selects which PHY is active in MPHY mode.
In SPHY configurations, UTP_OP_FCO is used to inform the PHY that
the processor is ready to send data.
UTP_OP_FCO
UTP_OP_SOC
Z
Z
Z
Z
O
O
Start of Cell. Also known as TX_SOC.
Active high signal is asserted when UTP_OP_DATA contains the first
valid byte of a transmitted cell.
UTOPIA output data. Also known as UTP_TX_DATA. Used to send
UTP_OP_DATA[7:0]
UTP_OP_ADDR[4:0]
Z
Z
Z
O
O
data from the processor to an ATM UTOPIA-Level-2-compliant PHY.
Transmit PHY address bus. Used by the processor when operating in
MPHY mode to poll and select a single PHY at any given time.
VI
UTOPIA Output data flow control input: Also known as the
TXFULL/CLAV signal.
Used to inform the processor of the ability of each polled PHY to
receive a complete cell. For cell-level flow control in an MPHY
environment, TxClav is an active high tri-stateable signal from the
MPHY to ATM layer. The UTP_OP_FCI, which is connected to multiple
MPHY devices, will see logic high generated by the PHY, one clock
after the given PHY address is asserted — when a full cell can be
received by the PHY. The UTP_OP_FCI will see a logic low generated
by the PHY one clock cycle, after the PHY address is asserted — if a
full cell cannot be received by the PHY.
UTP_OP_FCI
Z
VI
I
This signal should be tied low through a 10-KΩ resistor if not being
used.
UTOPIA Receive clock input. Also known as UTP_RX_CLK.
This signal is used to synchronize all UTOPIA-received inputs to the
rising edge of the UTP_IP_CLK.
UTP_IP_CLK
Z
VI
I
This signal should be pulled low through a 10-KΩ resistor when not
being utilized in the system.
UTOPIA Input Data flow control input signal. Also known as
RXEMPTY/CLAV.
Used to inform the processor of the ability of each polled PHY to send a
complete cell. For cell-level flow control in an MPHY environment,
RxClav is an active high tri-stateable signal from the MPHY to ATM
layer. The UTP_IP_FCI, which is connected to multiple MPHY devices,
will see logic high generated by the PHY, one clock after the given PHY
address is asserted, when a full cell can be received by the PHY. The
UTP_IP_FCI will see a logic low generated by the PHY, one clock cycle
after the PHY address is asserted if a full cell cannot be received by the
PHY.
UTP_IP_FCI
Z
VI
I
In SPHY mode, this signal is used to indicate to the processor that the
PHY has an octet or cell available to be transferred to the processor.
Should be pulled low through a 10-KΩ resistor when not being utilized
in the system.
Start of Cell. RX_SOC
Active-high signal that is asserted when UTP_IP_DATA contains the
first valid byte of a transmitted cell.
UTP_IP_SOC
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized
in the system.
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
37
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 10.
UTOPIA-2 Interface (Sheet 2 of 2)
Power
On
Name
Reset† Type†
Description
Reset†
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM
UTOPIA-Level-2-compliant PHY.
UTP_IP_DATA[7:0]
UTP_IP_ADDR[4:0]
Z
VI
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized
in the system.
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and
select a single PHY at any one given time.
Z
Z
O
UTOPIA Input Data Flow Control Output signal: Also known as the
RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that
the processor is ready to accept data.
In MPHY configurations, UTP_IP_FCO is used to select which PHY will
drive the UTP_RX_DATA and UTP_RX_SOC signals. The PHY is
selected by placing the PHY’s address on the UTP_IP_ADDR and
bringing UTP_OP_FCO to logic 1 during the current clock, followed by
the UTP_OP_FCO going to a logic 0 on the next clock cycle.
UTP_IP_FCO
Z
O
†
For a legend of the Type codes, see Table 4 on page 30.
Table 11.
Expansion Bus Interface
Power
Name
On
Reset†
Type†
Description
Reset†
Input clock signal used to sample all expansion interface inputs and
clock all expansion interface outputs.
EX_CLK
Z
Z
Z
0
I
Address-latch enable used for multiplexed address/data bus accesses.
Used in Intel and Motorola* multiplexed modes of operation.
EX_ALE
O
Expansion-bus address used as an output for data accesses over the
expansion bus. Also, used as an input during reset to capture device
configuration. These signals have a weak pull-up resistor attached
internally. Based on the desired configuration, various address signals
must be tied low in order for the device to operate in the desired mode.
EX_ADDR[23:0]
H
H
I/O
Intel-mode write strobe / Motorola-mode data strobe
EX_WR_N
EX_RD_N
Z
Z
1
1
O
O
(EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
Intel-mode read strobe / Motorola-mode read-not-write
(EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N).
External chip selects for expansion bus.
•
Chip selects 0 through 7 can be configured to support Intel or
Motorola bus cycles.
Chip selects 4 through 7 can be configured to support TI HPI bus
cycles.
EX_CS_N[7:0]
EX_DATA[15:0]
Z
Z
1
0
O
•
I/O
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices. Expansion-bus
access is halted when an external device sets EX_IOWAIT_N to logic 0
and resume from the halted location once the external device sets
EX_IOWAIT_N to logic 1. This signal affects accesses that use
EX_CS_N[7:0] when the chip select is configured in Intel- or
Motorola-mode of operation.
EX_IOWAIT_N
EX_RDY[3:0]
H
H
H
H
I
I
Should be pulled high through a 10-KΩ resistor when not being utilized
in the system.
HPI interface ready signals. Can be configured to be active high or
active low. These signals are used to halt accesses using Chip Selects
7 through 4 when the chip selects are configured to operate in HPI
mode. There is one RDY signal per chip select. This signal only affects
accesses that use EX_CS_N[7:4].
Should be pulled low though a 10-KΩ resistor when not being utilized in
the system.
†
For a legend of the Type codes, see Table 4 on page 30.
38
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 12.
UART Interfaces
Power
Reset† Type†
Description
Name
On
Reset†
UART serial data input to High-Speed UART Pins.
RXDATA0
TXDATA0
Z
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in the
system.
UART serial data output. The TXD signal is set to the MARKING (logic 1) state
upon a reset operation. High-Speed Serial UART Pins.
VO
O
UART CLEAR-TO-SEND input to High-Speed UART Pins.
When logic 0, this pin indicates that the modem or data set connected to the
UART interface of the processor is ready to exchange data. The CTS_N signal is
a modem status input whose condition can be tested by the processor.
CTS0_N
RTS0_N
H
H
VI/PE
I
Should be pulled high through a 10-KΩ resistor when not being utilized in the
system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART
interface of the processor that the UART is ready to exchange data. A reset sets
the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1). High-Speed
UART Pins.
UART serial data input.
RXDATA1
TXDATA1
Z
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being utilized in the
system.
UART serial data output. The TXD signal is set to the MARKING (logic 1) state
upon a Reset operation. Console UART Pins.
VO
O
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set connected to the
UART interface of the processor is ready to exchange data. The CTS_N signal is
a modem status input whose condition can be tested by the processor.
CTS1_N
RTS1_N
H
H
VI/PE
I
Should be pulled high through a 10-KΩ resistor when not being utilized in the
system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART
interface of the processor that the UART is ready to exchange data. A reset sets
the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1). Console
UART Pins.
†
For a legend of the Type codes, see Table 4 on page 30.
Power
Table 13.
USB Interface
Power
On
Name
Reset† Type†
Description
Reset†
USB_DPOS
USB_DNEG
Z
Z
Z
Z
I/O
I/O
Positive signal of the differential USB receiver/driver.
Negative signal of the differential USB receiver/driver.
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
39
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 14.
Oscillator Interface
Power
Name
On
Reset† Type†
Description
Reset†
OSC_IN
OSC_OUT
I
33.33-MHz, sinusoidal crystal input signal. Can be driven by an oscillator.
33.33-MHz, sinusoidal crystal output signal. Left disconnected when being
driven by an oscillator.
O
†
For a legend of the Type codes, see Table 4 on page 30.
Table 15.
GPIO Interface
Power
Name
On
Reset† Type†
Description
Reset†
General purpose Input/Output pins. May be configured as an input or an
output. As an input, each signal may be configured a processor interrupt.
Default after reset is to be configured as inputs.
GPIO[12:0]
Z
Z
Z
Z
Z
Z
I/O
I/O
I/O
Should be pulled low using a 10-KΩ resistor when not being utilized in the
system.
General purpose input/output pins. May be configured as an input or an
output. Default after reset is to be configured as inputs.
GPIO[13]
GPIO[14]
Should be pulled low using a 10-KΩ resistor when not being utilized in the
system.
Can be configured similar to GPIO Pin 13 or as a clock output. Configuration
as an output clock can be set at various speeds of up to 33.33 MHz with
various duty cycles. Configured as an input, upon reset.
Should be pulled low though a 10-KΩ resistor when not being utilized in the
system.
Can be configured similar to GPIO Pin 13 or as a clock output. Configuration
as an output clock can be set at various speeds of up to 33.33 MHz with
various duty cycles. Configured as an output, upon reset. Can be used to
clock the expansion interface, after reset.
CLKOUT
/VO
GPIO[15]
Z
I/O
Should be pulled low though a 10-KΩ resistor when not being utilized in the
system.
†
For a legend of the Type codes, see Table 4 on page 30.
Table 16.
JTAG Interface
Power
Name
On
Reset†
Type†
Description
Reset†
JTG_TMS
JTG_TDI
JTG_TDO
H
H
Z
VI/PE
VI/PE
VO
I
I
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
O
The JTG_TRST_N signal must be asserted (driven low) during
power-up, otherwise the TAP controller may not be initialized properly,
and the processor may be locked.
JTG_TRST_N
H
VI/PE
I
When the JTAG interface is not being used, the signal must be pulled low
using a 10-KΩ resistor.
JTG_TCK
Z
VI
I
Used as the clock for the IEEE 1149.1 JTAG interface.
†
For a legend of the Type codes, see Table 4 on page 30.
40
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Functional Signal Descriptions
Table 17.
System Interface
Power
Name
On
Reset† Type†
Description
Reset†
Used for test purposes only.
Must be pulled high for normal operation.
BYPASS_CLK
Z
VI
I
I
Used for test purposes only.
Must be pulled high for normal operation.
SCANTESTMODE_N
H
VI/PE
Used as a reset input to the device after power up conditions have
been met. Power up conditions include the power supplies reaching
a safe stable condition and the PLL achieving a locked state and the
PWRON_RESET_N coming to an active state prior to the
RESET_IN_N coming to an active state.
RESET_IN_N
0
0
VI
VI
I
I
Signal used at power up to reset all internal logic to a known state
after the PLL has achieved a locked state. The PWRON_RESET_N
input is a 1.3-V tolerant only.
PWRON_RESET_N
Used for test purposes only.
Must be pulled high for normal operation.
HIGHZ_N
H
Z
VI/PE
VO
I
Signal used to inform external reset logic that the internal PLL has
achieved a locked state.
PLL_LOCK
O
Signal used to control PCI drive strength characteristics. Drive
strength is varied on PCI address, data and control signals.
RCOMP
I
Pin requires a 34-Ω +/- 1% tolerance resistor to ground. Refer to
Figure 12 on page 77
†
For a legend of the Type codes, see Table 4 on page 30.
Table 18.
Power Interface
Name
VCC
Type†
Description
I
I
1.3-V power supply input pins used for the internal logic.
VCCP
VSS
3.3-V power supply input pins used for the peripheral (I/O) logic.
Ground power supply input pins used for both the 3.3-V and the 1.3-V power supplies.
3.3-V power supply input pins used for the peripheral (I/O) logic of the analog
oscillator circuitry.
VCCOSCP
VSSOSCP
VCCOSC
VSSOSC
VCCPLL1
VCCPLL2
I
I
I
I
I
I
Require special power filtering circuitry. Refer to Figure 10 on page 76
Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry.
Used in conjunction with the VCCOSCP pins.
Requires special power filtering circuitry. Refer to Figure 10 on page 76
1.3-V power supply input pins used for the internal logic of the analog oscillator
circuitry.
Requires special power filtering circuitry. Refer to Figure 11 on page 76
Ground power supply input pins used for the internal logic of the analog oscillator
circuitry. Used in conjunction with the VCCOSC pins.
Requires special power filtering circuitry. Refer to Figure 11 on page 76
1.3-V power supply input pins used for the internal logic of the analog phase lock-loop
circuitry.
Requires special power filtering circuitry. Refer to Figure 8 on page 75
1.3-V power supply input pins used for the internal logic of the analog phase lock-loop
circuitry.
Requires special power filtering circuitry. Refer to Figure 9 on page 75
†
For a legend of the Type codes, see Table 4 on page 30.
Datasheet
41
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
4.0
Package and Pinout Information
The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
have a 492-ball, plastic ball grid array (PBGA) package for commercial-temperature applications
and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for
extended-temperature applications.
4.1
Package Description
Figure 6.
492-Pin Lead PBGA Package
-A-
0.127
A
35.00 0.20
30.00 0.25
(1)
0.90
0.60
Pin #1
Corner
ø
26 24 22
25 23 21
20 18
19
16 14 12 10
15 13
8
6
4
2
3 1
17
11
9
7
5
2
C
-B-
ø 0.30
S
A
S
S
B
A
B
C
D
E
F
G
H
J
Pin 1 ID
K
L
M
35.00 0.20
22.00 REF
N
P
R
T
U
(2)
1.27
30.00 0.25
V
W
+
+
Y
AA
AB
AC
AD
AE
AF
+
+ +
1.63 REF
ø1.0
45º Chamfer
4 Places
1.27
1.63 REF
22.00 REF
3 Places
TOP VIEW
2.38 0.21
1.17 0.05
30º
0.15
0.20
C
-C-
0.61 0.06
3
0.60 0.10
Seating Plane
SIDE VIEW
B1268-03
1. All measurements are in millimeters (mm).
2. The size of the land pad at the interposer side (1) is 0.81 mm.
3. The size of the solder resist at the interposer side (2) is 0.66 mm.
42
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Figure 7.
Package Markings
Pin #1
(Not a mark)
*
FWIXP42 XBX
<FPO>
Level 1 Name
INTEL M C 2002
i
<ATPO>
YWW KOREA
BSMC marking zone:
0.380” max.
BSMC
(ATPO#, Date
Code and COO)
NOTE: See Table 19 for specific on “Level 1 Name.”
Table 19. Part Numbers (Sheet 1 of 2)
Speed
(MHz)
Device
Stepping
Part #
Intel® IXP425
Network
Processor
B-0
533
400
266
FWIXP425BD
Intel® IXP425
Network
Processor
B-0
B-0
B-0
B-0
B-0
B-0
B-0
FWIXP425BC
FWIXP425BB
GWIXP425BDT
GWIXP425BCT
GWIXP425BBT
FWIXP422BB
FWIXP421BB
Intel® IXP425
Network
Processor
Intel® IXP425
Network
Processor
533
Extended
Temperature
Intel® IXP425
Network
Processor
400
Extended
Temperature
Intel® IXP425
Network
Processor
266
Extended
Temperature
Intel® IXP422
Network
Processor
266
266
Intel® IXP421
Network
Processor
Datasheet
43
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 19. Part Numbers (Sheet 2 of 2)
Speed
(MHz)
Device
Stepping
Part #
Intel® IXP420
Network
B-0
533
FWIXP420BD
Processor
Intel® IXP420
Network
Processor
B-0
B-0
400
FWIXP420BC
FWIXP420BB
Intel® IXP420
Network
Processor
266
266
Intel® IXP420
Network
Processor
B-0
GWIXP420BBT
Extended
Temperature
Intel® IXC1100
Control Plane
Processor
B-0
B-0
B-0
B-0
B-0
B-0
533
400
266
FWIXC1100BD
FWIXC1100BC
FWIXC1100BB
GWIXC1100BDT
GWIXC1100BCT
GWIXC1100BBT
Intel® IXC1100
Control Plane
Processor
Intel® IXC1100
Control Plane
Processor
Intel® IXC1100
Control Plane
Processor
533
Extended
Temperature
Intel® IXC1100
Control Plane
Processor
400
Extended
Temperature
Intel® IXC1100
Control Plane
Processor
266
Extended
Temperature
44
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
4.2
Signal-Pin Descriptions
In this section, separate ball-map-assignment tables are given for each model of the IXP42X
product line and IXC1100 control plane processors. These tables include:
Device
Table #
Starting Page
Intel® IXP425 Network Processor
Intel® IXP422 Network Processor
Intel® IXP421 Network Processor
20
21
22
45
52
59
Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane
Processor
23
66
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
45
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
46
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
VCC
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
47
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
48
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
PCI_AD[1]
VCCP
Y1
Y2
HSS_TXCLK0
HSS_RXCLK0
HSS_TXFRAME1
VCC
PCI_AD[0]
PCI_AD[7]
HSS_TXDATA0
VCC
PCI_AD[3]
VCC
W3 HSS_RXFRAME0 Y3
W4
W5
VSS
Y4
Y5
HSS_TXFRAME0
VSS
HSS_TXCLK1
VCCP
W6 HSS_RXFRAME1 Y6
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
VCC
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
49
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
HSS_RXDATA0
VCCP
AB1
AB2
AB3
AB4
HSS_TXDATA1
HSS_RXDATA1
ETH_TXDATA0[3]
ETH_TXDATA0[1]
VSS
AC1
VSS
AD1
ETH_TXCLK0
ETH_RXDV0
VSS
AC2 ETH_TXDATA0[0] AD2
VSS
AC3
AC4
VCCP
VCC
AD3
AD4
HSS_RXCLK1
ETH_CRS0
ETH_MDC
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
AA5 ETH_TXDATA0[2] AB5
AA6 VCC AB6
AA7 ETH_RXDATA0[1] AB7
AA8 VSS AB8
AA9 ETH_TXDATA1[1] AB9
AC5 ETH_RXDATA0[0] AD5
ETH_RXCLK0
VCCP
AC6
AC7
VSS
VCC
AD6
AD7
ETH_TXDATA1[2]
ETH_RXDATA1[1]
VCCP
AC8 ETH_RXDATA1[2] AD8
AC9
AC10
AC11
AC12
VCC
VCC
AD9
AD10
AD11
AD12
AA10
VCC
AB10
AB11
AB12
VSSOSCP
VCCP
VCCP
VCCOSCP
VCC
VSS
PLL_LOCK
AB13 UTP_OP_DATA[7] AC13
RESET_IN_N
VCC
AD13 PWRON_RESET_N
AD14 UTP_OP_DATA[4]
AB14
AB15
AB16
AB17
AB18
VCCP
UTP_OP_SOC
VSS
AC14
AC15 UTP_OP_DATA[1] AD15 UTP_OP_DATA[2]
AC16 UTP_OP_FCI AD16 VSS
AC17 UTP_OP_ADDR[1] AD17 UTP_OP_ADDR[3]
AA17
AA18
VCC
UTP_IP_DATA[6]
VCCP
UTP_IP_FCI
AC18
VCC
AD18
UTP_IP_DATA[7]
VCCP
AA19 UTP_IP_ADDR[0] AB19
UTP_IP_CLK
AC19 UTP_IP_DATA[2] AD19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VSS
VCC
AB20 UTP_IP_ADDR[1] AC20
AB21 SCANTESTMODE_N AC21
UTP_IP_SOC
VCC
AD20
AD21
AD22
AD23
AD24
AD25
AD26
UTP_IP_DATA[1]
UTP_IP_ADDR[4]
VSS
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
50
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 20.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
AE2
AE3
VCCP
ETH_COL0
ETH_TXEN1
VCCP
AF2
AF3
(Reserved)
AE4
AF4
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
OSC_IN
AE10
AE11
AE12
AE13
VCCPLL1
VSS
AF10
AF11
AF12
AF13
VSSOSCP
OSC_OUT
VCCPLL2
VCCP
VCCOSC
BYPASS_CLK
AE14 UTP_OP_DATA[5] AF14 UTP_OP_DATA[6]
AE15
AE16
AE17
VSS
UTP_OP_FCO
VCCP
AF15 UTP_OP_DATA[3]
AF16 UTP_OP_DATA[0]
AF17
UTP_OP_CLK
AE18 UTP_OP_ADDR[2] AF18 UTP_OP_ADDR[4]
AE19 VSS AF19 UTP_OP_ADDR[0]
AE20 UTP_IP_DATA[4] AF20
UTP_IP_DATA[5]
UTP_IP_DATA[3]
UTP_IP_DATA[0]
UTP_IP_ADDR[3]
UTP_IP_ADDR[2]
JTG_TMS
AE21
AE22
AE23
AE24
AE25
AE26
VCCP
UTP_IP_FCO
VCCP
AF21
AF22
AF23
AF24
AF25
AF26
JTG_TDI
VCCP
HIGHZ_N
JTG_TCK
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
51
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
52
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
53
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
VCC
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
54
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
55
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
N/C
Y1
Y2
Y3
Y4
Y5
Y6
N/C
N/C
PCI_AD[0]
PCI_AD[7]
N/C
PCI_AD[3]
VCC
N/C
VSS
VCC
N/C
N/C
VCCP
ETH_TXEN0
VCC
VSS
N/C
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
VCC
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
56
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
N/C
VCCP
VSS
N/C
AB1
AB2
AB3
AB4
N/C
AC1
VSS
AD1
ETH_TXCLK0
ETH_RXDV0
VSS
N/C
AC2 ETH_TXDATA0[0] AD2
ETH_TXDATA0[3]
AC3
AC4
VCCP
VCC
AD3
AD4
ETH_TXDATA0[1]
ETH_CRS0
ETH_MDC
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
AA5 ETH_TXDATA0[2] AB5
AA6 VCC AB6
AA7 ETH_RXDATA0[1] AB7
AA8 VSS AB8
AA9 ETH_TXDATA1[1] AB9
VSS
ETH_RXCLK0
VCCP
AC5 ETH_RXDATA0[0] AD5
AC6
AC7
VSS
VCC
AD6
AD7
ETH_TXDATA1[2]
ETH_RXDATA1[1]
VCCP
AC8 ETH_RXDATA1[2] AD8
AC9
VCC
VCC
AD9
AD10
AD11
AD12
AA10
VCC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
VSSOSCP
VCCP
VCCP
VCCOSCP
VCC
VSS
PLL_LOCK
N/C
RESET_IN_N
VCC
AD13 PWRON_RESET_N
VCCP
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
N/C
N/C
N/C
N/C
VSS
N/C
VSS
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VCC
N/C
N/C
N/C
N/C
VCCP
VCC
N/C
N/C
N/C
N/C
VCCP
N/C
VSS
N/C
N/C
VCC
AB21 SCANTESTMODE_N AC21
VCC
N/C
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
VSS
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
57
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 21.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
OSC_IN
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
N/C
AE2
AE3
VCCP
ETH_COL0
ETH_TXEN1
VCCP
AF2
AF3
AE4
AF4
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VCCPLL1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
VCCPLL2
VCCP
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VCCP
N/C
JTG_TDI
VCCP
N/C
JTG_TMS
JTG_TCK
HIGHZ_N
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
58
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
59
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
60
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
VCC
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
61
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
62
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
PCI_AD[1]
VCCP
Y1
Y2
HSS_TXCLK0
HSS_RXCLK0
HSS_TXFRAME1
VCC
PCI_AD[0]
PCI_AD[7]
HSS_TXDATA0
VCC
PCI_AD[3]
VCC
W3 HSS_RXFRAME0 Y3
W4
W5
VSS
Y4
Y5
HSS_TXFRAME0
VSS
HSS_TXCLK1
VCCP
W6 HSS_RXFRAME1 Y6
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
VCC
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
63
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
HSS_RXDATA0
VCCP
AB1
AB2
AB3
AB4
HSS_TXDATA1
HSS_RXDATA1
ETH_TXDATA0[3]
ETH_TXDATA0[1]
VSS
AC1
VSS
AD1
ETH_TXCLK0
ETH_RXDV0
VSS
AC2 ETH_TXDATA0[0] AD2
VSS
AC3
AC4
VCCP
VCC
AD3
AD4
HSS_RXCLK1
ETH_CRS0
ETH_MDC
N/C
AA5 ETH_TXDATA0[2] AB5
AA6 VCC AB6
AA7 ETH_RXDATA0[1] AB7
AC5 ETH_RXDATA0[0] AD5
ETH_RXCLK0
VCCP
AC6
AC7
VSS
VCC
AD6
AD7
N/C
AA8
AA9
VSS
N/C
AB8
AB9
N/C
AC8
N/C
AD8
N/C
N/C
AC9
VCC
AD9
VSS
AA10
VCC
AB10
AB11
AB12
VCCP
AC10
AC11
AC12
VCC
AD10
AD11
AD12
VSSOSCP
VCCP
VCCP
VCCOSCP
VCC
VSS
PLL_LOCK
AB13 UTP_OP_DATA[7] AC13
RESET_IN_N
VCC
AD13 PWRON_RESET_N
AD14 UTP_OP_DATA[4]
AB14
AB15
AB16
AB17
AB18
VCCP
UTP_OP_SOC
VSS
AC14
AC15 UTP_OP_DATA[1] AD15 UTP_OP_DATA[2]
AC16 UTP_OP_FCI AD16 VSS
AC17 UTP_OP_ADDR[1] AD17 UTP_OP_ADDR[3]
AA17
AA18
VCC
UTP_IP_DATA[6]
VCCP
UTP_IP_FCI
AC18
VCC
AD18
UTP_IP_DATA[7]
VCCP
AA19 UTP_IP_ADDR[0] AB19
UTP_IP_CLK
AC19 UTP_IP_DATA[2] AD19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VSS
VCC
AB20 UTP_IP_ADDR[1] AC20
AB21 SCANTESTMODE_N AC21
UTP_IP_SOC
VCC
AD20
AD21
AD22
AD23
AD24
AD25
AD26
UTP_IP_DATA[1]
UTP_IP_ADDR[4]
VSS
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
64
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 22.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
N/C
AE2
AE3
VCCP
ETH_COL0
N/C
AF2
AF3
AE4
AF4
AE5
VCCP
N/C
AF5
N/C
AE6
AF6
N/C
AE7
VSS
AF7
N/C
AE8
N/C
AF8
VSSOSC
OSC_IN
AE9
VCCP
VCCPLL1
VSS
AF9
AE10
AE11
AE12
AE13
AF10
AF11
AF12
AF13
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
VCCPLL2
VCCP
AE14 UTP_OP_DATA[5] AF14 UTP_OP_DATA[6]
AE15
AE16
AE17
VSS
UTP_OP_FCO
VCCP
AF15 UTP_OP_DATA[3]
AF16 UTP_OP_DATA[0]
AF17
UTP_OP_CLK
AE18 UTP_OP_ADDR[2] AF18 UTP_OP_ADDR[4]
AE19 VSS AF19 UTP_OP_ADDR[0]
AE20 UTP_IP_DATA[4] AF20
UTP_IP_DATA[5]
UTP_IP_DATA[3]
UTP_IP_DATA[0]
UTP_IP_ADDR[3]
UTP_IP_ADDR[2]
JTG_TMS
AE21
AE22
AE23
AE24
AE25
AE26
VCCP
UTP_IP_FCO
VCCP
AF21
AF22
AF23
AF24
AF25
AF26
JTG_TDI
VCCP
HIGHZ_N
JTG_TCK
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
65
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
66
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
67
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
VCC
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
68
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
69
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
N/C
Y1
Y2
Y3
Y4
Y5
Y6
N/C
N/C
PCI_AD[0]
PCI_AD[7]
N/C
PCI_AD[3]
VCC
N/C
VSS
VCC
N/C
N/C
VCCP
ETH_TXEN0
VCC
VSS
N/C
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
VCC
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
70
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
N/C
VCCP
VSS
N/C
AB1
AB2
AB3
AB4
N/C
AC1
VSS
AD1
ETH_TXCLK0
ETH_RXDV0
VSS
N/C
AC2 ETH_TXDATA0[0] AD2
ETH_TXDATA0[3]
AC3
AC4
VCCP
VCC
AD3
AD4
ETH_TXDATA0[1]
ETH_CRS0
ETH_MDC
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
AA5 ETH_TXDATA0[2] AB5
AA6 VCC AB6
AA7 ETH_RXDATA0[1] AB7
AA8 VSS AB8
AA9 ETH_TXDATA1[1] AB9
VSS
ETH_RXCLK0
VCCP
AC5 ETH_RXDATA0[0] AD5
AC6
AC7
VSS
VCC
AD6
AD7
ETH_TXDATA1[2]
ETH_RXDATA1[1]
VCCP
AC8 ETH_RXDATA1[2] AD8
AC9
VCC
VCC
AD9
AD10
AD11
AD12
AA10
VCC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
VSSOSCP
VCCP
VCCP
VCCOSCP
VCC
VSS
PLL_LOCK
N/C
RESET_IN_N
VCC
AD13 PWRON_RESET_N
VCCP
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
N/C
N/C
N/C
N/C
VSS
N/C
VSS
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VCC
N/C
N/C
N/C
N/C
VCCP
VCC
N/C
N/C
N/C
N/C
VCCP
N/C
VSS
N/C
N/C
VCC
AB21 SCANTESTMODE_N AC21
VCC
N/C
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
VSS
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
Datasheet
71
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
Table 23.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1 ETH_RXDATA0[3] AF1
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
OSC_IN
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
N/C
AE2
AE3
VCCP
ETH_COL0
ETH_TXEN1
VCCP
AF2
AF3
AE4
AF4
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VCCPLL1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
VCCPLL2
VCCP
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VCCP
N/C
JTG_TDI
VCCP
N/C
JTG_TMS
JTG_TCK
HIGHZ_N
NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 30.
72
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Package and Pinout Information
4.3
Package Thermal Specifications
The thermal characterization parameter “ΨJT” is proportional to the temperature difference
between the top, center of the package and the junction temperature.
This can be a useful value for verifying device temperatures in an actual environment. By
measuring the package of the device, the junction temperature can be estimated, if the thermal
characterization parameter has been measured under similar conditions.
The use of ΨJT should not be confused with Θjc, which is the thermal resistance from the device
junction to the external surface of the package or case nearest the die attachment — as the case is
held at a constant temperature.
Case temperature = Junction Temperature - (ΨJT * Power Dissipation)
T
JC = TJ - (ΨJT * Power Dissipation)
The case temperature can then be monitored to make sure that the maximum junction temperature
is not violated. Examples are given in the following sections.
Note: For more information on ΨJT, refer to the EIA/JEDEC Standard 51-2, Section 4.
4.3.1
Commercial Temperature
“Commercial” temperature range is defined in terms of the ambient temperature range, which is
specified as 0° C to 70° C. The maximum power (P) is 2.4 W and the maximum junction
temperature (Tj) is 115 ° C.
ΨJT for commercial temperature is 0.89° C/W.
Using the preceding junction-temperature formula, the commercial temperature for a 266-MHz
part — assuming a maximum power of 2 W — would be:
TJC = 115° C - (0.89 * 2.0)
T
JC = 113.22° C
4.3.2
Extended Temperature
“Extended” temperature range is defined in terms of the ambient temperature range, which is
specified as -40° C to 85° C. The maximum power (P) is 2.4 W and the maximum junction
temperature (Tj) is 115° C.
ΨJT for extended temperature is 0.32° C/W.
Using the preceding junction-temperature formula, the extended temperature for a 533-MHz part
— assuming a maximum power of 2.4 W — would be:
TJC = 115° C - (0.32 * 2.4)
T
JC = 114.23° C
Datasheet
73
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.0
Electrical Specifications
5.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Ambient Air Temperature (Extended)
Ambient Air Temperature (Commercial)
Supply Voltage Core
-40º C to 85º C
0º C to 70º C
-0.3 V to 2.1V
-0.3 V to 3.6V
-0.3 V to 2.1V
-0.3 V to 3.6V
-0.3 V to 2.1V
-0.3 V to 2.1V
-0.3 V to 3.6V
-55o C to 125o C
Supply Voltage I/O
Supply Voltage Oscillator (V
Supply Voltage Oscillator (V
)
CCOSC
)
CCOSCP
Supply Voltage PLL (V
Supply Voltage PLL (V
)
)
CCPLL1
CCPLL2
Voltage On Any I/O Ball
Storage Temperature
Warning: Stressing the device beyond the “absolute maximum ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “operating conditions” is not recommended and
extended exposure beyond the “operating conditions” may affect device reliability.
5.2
V
, V
, V
, V
Pin Requirements
CCPLL1
CCPLL2
CCOSCP CCOSC
To reduce voltage-supply noise on the analog sections of the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (VCCPLL1
VCCPLL2) and oscillator circuit (VCCOSCP, VCCOSC) require isolated voltage supplies.
,
The filter circuits for each supply are shown in the following sections.
5.2.1
V
Requirement
CCPLL1
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a
first-order filter with a cut-off frequency below 30 MHz — must be connected to the VCCPLL1 pin
of the Intel® IXP42X product line and IXC1100 control plane processors.
The ground of both capacitors should be connected to the nearest VSS supply pin. Both capacitors
should be located less than 0.5 inch away from the VCCPLL1 pin and the associated VSS pin. In
order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be
used as long as the capacitors are placed directly beside each other.
74
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 8.
V
CCPLL1 Power Filtering Diagram
1.3 V
VCCPLL1
100 nF
Intel® IXP4XX
Product Line /
Intel® IXC1100
Control Plane
Processor
10 nF
100 nF
VSS
VSS
B1680-02
5.2.2
V
Requirement
CCPLL2
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a
first-order filter with a cut-off frequency below 30 MHz — must be connected to the VCCPLL2 pin
of the IXP42X product line and IXC1100 control plane processors.
The ground of both capacitors should be connected to the nearest VSS supply pin. Both capacitors
should be located less than 0.5 inch away from the VCCPLL2 pin and the associated VSS pin. In
order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be
used as long as the capacitors are placed directly beside each other.
Figure 9.
VCCPLL2 Power Filtering Diagram
1.3 V
VCCPLL2
100 nF
Intel® IXP4XX
Product Line /
Intel® IXC1100
Control Plane
Processor
10 nF
100 nF
VSS
VSS
B1681-02
5.2.3
V
Requirement
CCOSCP
A single 170-nF capacitor must be connected between the VCCP_OSC pin and VSSP_OSC pin of the
IXP42X product line and IXC1100 control plane processors. This capacitor value provides both
bypass and filtering.
When 170 nF is an inconvenient size, capacitor values between 150 nF to 200 nF could be used
with little adverse effects, assuming that the effective series resistance of the 200-nF capacitor is
under 50 mΩ.
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be
used as long as the capacitors are placed directly beside each other. VSSP_OSC consists of two pins,
AD10 and AF10. Ensure that both pins are connected as shown in Figure 10.
Datasheet
75
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 10.
VCCOSCP Power Filtering Diagram
3.3 V
VCCOSCP
Intel® IXP4XX
Product Line /
Intel® IXC1100
Control Plane
Processor
170 nF
VSSOSCP
VSSOSCP
VSS
B1675-03
5.2.4
V
Requirement
CCOSC
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a
first-order filter with a cut-off frequency below 33 MHz — must be connected to both of the
V
CCOSC pins of the IXP42X product line and IXC1100 control plane processors.
The grounds of both capacitors should be connected to the VSSOSC supply pin. Both capacitors
should be located less than 0.5 inch away from the VCCOSC pin and the associated VSSOSC pin.
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be
used as long as the capacitors are placed directly beside each other.
Figure 11.
VCCOSC Power Filtering Diagram
1.3 V
Intel® IXP4XX
Product Line /
10 nF
Intel® IXC1100
Control Plane
Processor
100 nF
100 nF
VSS
B1676-02
76
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.3
RCOMP Pin Requirements
Figure 12 shows the requirements for the RCOMP pin.
Figure 12.
RCOMP Pin External Resistor Requirements
RCOMP
Intel® IXP4XX Product Line /
Intel® IXC1100 Control Plane
Processor
34 Ω,
+ 1%
VSS
VSS
B1672-01
5.4
DC Specifications
5.4.1
Operating Conditions
Table 24.
Operating Conditions
Symbol
Parameter
Voltage supplied to the I/O.
Min.
Typ.
Max.
Units
Notes
VCCP
VCC
3.135
1.235
3.3
1.3
3.465
1.365
V
V
Voltage supplied to the internal logic.
Voltage supplied to the internal oscillator
logic.
VCCOSC
1.235
3.135
1.235
1.3
3.3
1.3
1.365
3.465
1.365
V
V
V
VCCOSCP Voltage supplied to the oscillator I/O.
Voltage supplied to the analog phase-lock
VCCPLL1
loop.
Voltage supplied to the analog phase-lock
VCCPLL2
loop.
1.235
1.3
1.365
V
Datasheet
77
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.2
PCI DC Parameters
Table 25.
PCI DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
0.5 VCCP
V
V
3
0.3 VCCP
3
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -500 µA
IOUT = 1500 µA
0 < VIN < VCCP
0.9 VCCP
-10
V
3
0.1 VCCP
10
V
3
µA
pF
1, 3
2, 3
CIN
5
5
I/O or output pin
capacitance
COUT
pF
2,3
CIDSEL IDSEL-pin capacitance
5
pF
nH
2,3
2,3
LPIN
Pin inductance
20
NOTES:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
2. These values are typical values seen by the manufacturing process and are not tested.
3. For additional information, see the PCI Local Bus Specification, Rev. 2.2.
5.4.3
USB DC Parameters
Table 26.
USB v1.1 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.15
V
V
0.8
IOUT
=
VOH
Output-high voltage
Output-low voltage
2.8
-10
V
V
-6.1 * VOHmA
IOUT =
VOL
0.3
10
6.1 * VOHmA
IIL
Input-leakage current
Input-pin capacitance
0 < VIN < VCCP
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
78
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.4
UTOPIA-2 DC Parameters
Table 27.
UTOPIA-2 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
V
V
0.8
0.5
VOH
VOL
IOUT = -8 mA
IOUT = 8 mA
2.4
-8
Output current at high
voltage
IOH
IOL
VOH > 2.4 V
mA
mA
Output current at low
voltage
VOL < 0.5 V
8
IIL
Input-leakage current
Input-pin capacitance
0 < VIN < VCCP
-10
10
µA
pF
1
CIN
5
5
2
2
I/O or output pin
capacitance
COUT
pF
NOTES:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
2. These values are typical values seen by the manufacturing process and are not tested.
5.4.5
MII DC Parameters
Table 28.
MII DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
V
V
0.8
0.4
VOH
VOL
IOUT = -4 mA
IOUT = 4mA
2.4
-8
Output current at high
voltage
IOH
IOL
VOH > 2.4 V
mA
mA
Output current at low
voltage
VOL < 0.4 V
8
IIL
Input-leakage current
Input-pin capacitance
0 < VIN < VCCP
-10
10
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
Datasheet
79
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.6
MDIO DC Parameters
Table 29.
MDIO DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
0.8
VOH
VOL
IOUT = -4 mA
IOUT = 4 mA
2.4
-10
V
0.4
10
V
IIL
Input-leakage current 0 < VIN < VCCP
Input-pin capacitance
µA
pF
pF
CIN
5
5
1
1
CINMDIO
Input-pin capacitance
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
5.4.7
SDRAM Bus DC Parameters
Table 30.
SDRAM Bus DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
1
0.8
2
VOH
Output-high voltage
Output-low voltage
Input-leakage current
IOUT = -4 mA
IOUT = 4 mA
0 < VIN < VCCP
2.4
V
V
0.4
5
V
OL
IIL
-5
-5
µA
Output-leakage
current
IOL
0 < VIN < VCCP
5
µA
CINCLK
CIO
Input-pin capacitance
I/O-pin capacitance
4
5
pF
pF
3
3
NOTES:
1. VIH overshoot: VIH (MAX) = VCCP + 2 V for a pulse width < 3 ns, and the pulse width cannot be greater than
one third of the cycle rate.
2. VIL undershoot: VIL (MIN) = -2 V for a pulse width < 3 ns cannot be exceeded.
3. These values are typical values seen by the manufacturing process and are not tested.
80
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.8
Expansion Bus DC Parameters
Table 31.
Expansion Bus DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
0.8
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -4 mA
IOUT = 4mA
2.4
-10
V
1
1
0.4
10
V
0 < VIN < VCCP
µA
pF
CIN
5
2
NOTES:
1. Test conditions were a 70 pF load to ground.
2. These values are typical values seen by the manufacturing process and are not tested.
5.4.9
High-Speed, Serial Interface 0 DC Parameters
Table 32.
High-Speed, Serial Interface 0 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
0.8
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -8 mA
IOUT = 8 mA
2.4
-10
V
0.4
10
V
0 < VIN < VCCP
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
5.4.10
High-Speed, Serial Interface 1 DC Parameters
Table 33.
High-Speed, Serial Interface 1 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
0.8
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -8 mA
IOUT = 8 mA
0 < VIN < VCCP
2.4
-10
V
0.4
10
V
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
Datasheet
81
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.11
High-Speed and Console UART DC Parameters
Table 34.
UART DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
0.8
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -4 mA
IOUT = 4 mA
0 < VIN < VCCP
2.4
-10
V
0.4
10
V
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
82
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.4.12
GPIO DC Parameters
Table 35.
GPIO DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
0.8
0.4
V
V
Output-high voltage for GPIO 0 to
GPIO 13
VOH
VOL
VOH
VOL
IOUT = -16 mA
IOUT = 16 mA
IOUT = -4 mA
2.4
Output-low voltage for GPIO 0 to
GPIO 13
V
V
V
Output-high voltage for GPIO 14 and
GPIO 15
2.4
-10
Output-low voltage for GPIO 14 and
GPIO 15
IOUT = 4 mA
0.4
10
IIL
Input-leakage current
Input-pin capacitance
0 < VIN < VCCP
µA
pF
CIN
5
5.4.13
JTAG DC Parameters
Table 36.
JTAG DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
VIH
VIL
Input-high voltage
Input-low voltage
2.0
V
V
0.8
VOH
VOL
IIL
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
IOUT = -4 mA
IOUT = 4 mA
0 < VIN < VCCP
2.4
-10
V
0.4
10
V
µA
pF
CIN
5
1
NOTES:
1. These values are typical values seen by the manufacturing process and are not tested.
5.4.14
Reset DC Parameters
Table 37.
PWRON_Reset _N DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
The input voltage
must not exceed
1.3V or long-term
reliability may be
adversely affected.
VIH
Input-high voltage
1.0
1.3
V
VIL
IIL
Input-low voltage
0.3
10
1
V
0 < VIN
1.3V
<
Input leakage current
Input Capacitance
-500
µA
pF
CIN
Simulated results.
Datasheet
83
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5
AC Specifications
5.5.1
Clock Signal Timings
5.5.1.1
Processor Clock Timings
Table 38.
Device Clock Timings (Oscillator Reference)
Symbol
Parameter
Input-high voltage
Min.
Nom.
Max.
Units
Notes
VIH
VIL
2.0
V
V
Input-low voltage
0.8
Clock frequency for IXP42X product line
TFREQUENCY and IXC1100 control plane processors
crystal or oscillator.
33.33
MHz
1, 4
U
Clock tolerance over -40º C to 85º C.
-50
2
50
4
ppm
pF
FREQUENCY
Pin capacitance of IXP42X product line and
IXC1100 control plane processors’ inputs.
CIN
5
3
CSHUNT is a crystal parameter sometimes
referred to as the holder capacitance.
CSHUNT
pF
C1
C2
Load capacitance
Load capacitance
Duty cycle
pF
pF
%
2
2
3
TDC
35
50
65
NOTES:
1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator
input, tie to the crystal input pin and leave the crystal output pin disconnected.
2. Use the component values recommended by the crystal manufacturer.
3. This parameter applies when driving the clock input with an oscillator.
4. The reference-clock input slope should not exceed more than 2.5 V/nS to ensure proper PLL operation
.
Table 39.
Device Clock Timings (Crystal Reference) (Sheet 1 of 2)
Symbol
Parameter
Input-high voltage
Min.
Nom.
Max.
Units
Notes
VIH
VIL
1.9
V
V
Input-low voltage
1.6
Clock frequency for IXP42X product
TFREQUENCY line and IXC1100 control plane
33.33
MHz
1, 4
processors crystal or oscillator.
U
Clock tolerance over -40º C to 85º C.
Equivalent Series Resistance
-50
50
60
ppm
FREQUENCY
ESR
Ω
Pin capacitance of IXP42X product line
and IXC1100 control plane processors’
inputs.
CIN
5
3
pF
pF
CSHUNT is a crystal parameter
sometimes referred to as the holder
capacitance.
CSHUNT
2
4
84
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 39.
Device Clock Timings (Crystal Reference) (Sheet 2 of 2)
Symbol
Parameter
Load capacitance
Min.
Nom.
Max.
Units
Notes
C1
C2
pF
pF
%
2
2
3
Load capacitance
Duty cycle
TDC
35
50
65
1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator
input, tie to the crystal input pin and leave the crystal output pin disconnected.
2. Use the component values recommended by the crystal manufacturer.
3. This parameter applies when driving the clock input with an oscillator.
4. The reference-clock input slope should not exceed more than 2.5 V/nS to ensure proper PLL operation
Figure 13.
Typical Connection to a Crystal
Intel® IXP4XX Product Line /
Intel® IXC1100 Control Plane
Processor
OSC_IN
C1
XTAL
OSC_OUT
C2
B1677-02
Figure 14.
Typical Connection to an Oscillator
Intel® IXP4XX Product Line /
Intel® IXC1100 Control Plane
Processor
OSC_IN
Oscillator
OSC_OUT
B1678-02
Datasheet
85
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.1.2
PCI Clock Timings
PCI Clock Timings
Table 40.
33 MHZ
66 MHZ
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
TPERIODPCICLK Clock period for PCI Clock
30
11
11
15
6
ns
ns
ns
TCLKHIGH
TCLKLOW
PCI Clock high time
PCI Clock low time
6
Rise and fall time
requirements for PCI Clock
TRISE/FALL
2
2
ns
5.5.1.3
MII Clock Timings
Table 41.
MII Clock Timings
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Clock period for Tx and Rx Ethernet
clocks
Tperiod100Mbit
Tperiod10Mbit
Tduty
25
25
MHz
Clock period for Tx and Rx Ethernet
clocks
2.5
50
2.5
65
2
MHz
%
Duty cycle for Tx and Rx Ethernet
clocks
35
Rise and fall time requirements for
Tx and Rx Ethernet clocks
Trise/fall
ns
5.5.1.4
UTOPIA-2 Clock Timings
UTOPIA-2 Clock Timings
Table 42.
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Clock period for Tx and Rx UTOPIA-2
clocks
Tperiod
Tduty
33
60
2
MHz
%
1
Duty cycle for Tx and Rx UTOPIA-2 clocks
40
50
1
1
Rise and fall time requirements for Tx and
Rx UTOPIA-2 clocks
Trise/fall
ns
NOTES:
1. The Utopia interface can operate at a minimum frequency greater than 0Hz
5.5.1.5
Expansion Bus Clock Timings
Expansion Bus Clock Timings
Table 43.
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Tperiod
Tduty
Clock period for expansion-bus clock
Duty cycle for expansion-bus clock
66
60
MHz
%
40
50
Rise and fall time requirements for
expansion-bus clock
Trise/fall
2
ns
86
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2
Bus Signal Timings
The AC timing waveforms are shown in the following sections.
5.5.2.1
PCI
Figure 15.
PCI Output Timing
V
V
hi
CLK
low
T
clk2out(b)
Output
Delay
A9572-01
NOTE: VHI = 0.6 VCC and VLOW = 0.2 VCC
Figure 16.
PCI Input Timing
CLK
T
setup(b)
T
hold
Inputs
Valid
Input
A9573-01
Datasheet
87
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 44.
PCI Bus Signal Timings
33 MHz
66 MHz
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
1, 2, 5,
7, 8
Tclk2outb PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
2
2
7
11
1
1
3
6
ns
ns
ns
Clock to output for all point-to-point
signals. This is the PCI_GNT_N
and PCI_REQ_N(0) only.
1, 2, 5,
7, 8
Tclk2out
12
6
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
4, 6, 7,
8
Tsetupb
Input setup time for all
point-to-point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
Tsetup
10, 12
0
5
0
ns
4, 7, 8
4, 7, 8
Thold
Input hold time from clock.
ns
ns
5, 6, 7,
8
Trst-off
Reset active-to-output float delay
40
40
NOTES:
1. See the timing measurement conditions.
2. Parts compliant to the 3.3 V signaling environment.
3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than
do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a setup of 12 ns for
33 MHz and 5 ns for 66 MHz.
4. RST# is asserted and de-asserted asynchronously with respect to CLK.
5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. Timing was tested with a 70-pF capacitor to ground.
8. For additional information, see the PCI Local Bus Specification, Rev. 2.2.
5.5.2.2
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100
control plane processors’ USB 1.1 interface is a device or function controller only. The IXP42X
product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered.
88
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2.3
UTOPIA-2
Figure 17.
UTOPIA-2 Input Timings
Clock
Signals
Tsetup
Thold
A9578-01
Table 45.
UTOPIA-2 Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are UTP_IP_DATA[7:0],
UTP_IP_SOC, AND UTP_IP_FCI, and
UTP_OP_FCI.
Tsetup
8
ns
ns
Input hold time after the rising edge of the clock.
Inputs included in this timing are
UTP_IP_DATA[7:0], UTP_IP_SOC, and
UTP_IP_FCI, and UTP_OP_FCI.
Thold
1
Figure 18.
UTOPIA-2 Output Timings
Clock
Signals
Tclk2out
Tholdout
A9579-01
Table 46.
UTOPIA-2 Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Rising edge of clock to signal output. Outputs
included in this timing are UTP_IP_DATA[3:0],
UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Tclk2out
17
ns
1
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
UTP_IP_DATA[3:0], UTP_OP_SOC,
Tholdout
1
ns
1
UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
NOTES:
1. Timing was tested with a 70-pF capacitor to ground.
Datasheet
89
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2.4
MII
Figure 19.
MII Output Timings
T
T
2
1
eth_tx_clk
eth_tx_data[7:0]
eth_tx_en
eth_crs
A9580-01
Table 47.
MII Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Clock to output delay for ETH_TXDATA and
ETH_TXEN.
T1
0
2
17
ns
1
ETH_TXDATA and ETH_TXEN hold time after
ETH_TXCLK.
T2
ns
NOTES:
1. These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.
Figure 20.
MII Input Timings
T
T
4
3
eth_rx_clk
eth_rx_data[7:0]
eth_rx_dv
eth_crs
A9581-01
Table 48.
MII Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
ETH_RXDATA and ETH_RXDV setup time prior
to rising edge of ETH_RXCLK
T3
5.5
ns
1, 2
1, 2
ETH_RXDATA and ETH_RXDV hold time after
the rising edge of ETH_RXCLK
T4
0
ns
NOTES:
1. These values satisfy the MII specification requirement of 10-ns setup and hold time.
2. Timing tests were performed with a 70-pF capacitor to ground.
90
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2.5
MDIO
Figure 21.
MDIO Output Timings
ETH_MDC
ETH_MDIO
T
T
1
2
A9582-02
NOTE: Processor is Sourcing MDIO.
Figure 22.
MDIO Input Timings
T
5
ETH_MDC
ETH_MDIO
T
T
4
3
A9583-02
NOTE: PHY is sourcing MDIO.
Datasheet
91
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 49.
MDIO Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
ETH_MDIO, clock to output timing with respect to
rising edge of ETH_MDC clock
ETH_MDC/2
+ 10 ns
T1
T2
T3
ns
ETH_MDIO output hold timing after the rising
edge of ETH_MDC clock
10
2
ns
ns
ETH_MDIO input setup prior to rising edge of
ETH_MDC clock
ETH_MDIO hold time after the rising edge of
ETH_MDC clock
T4
T5
0
ns
ns
ETH_MDC clock period
125
500
1
NOTE:
1. This parameter is not tested and is guaranteed by design.
5.5.2.6
SDRAM Bus
Figure 23.
SDRAM Input Timings
Clock
Signals
Tsetup
Thold
Table 50.
SDRAM Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are SDM_DQ[31:0] (during
a read operation).
Tsetup
1.4
ns
Input hold time after the rising edge of the clock.
Inputs included in this timing are SDM_DQ[31:0]
(during a read operation).
Thold
1.5
ns
92
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 24.
SDRAM Output Timings
Clock
Signals
Data Valid
T
T
clk2out
holdout
A9584-01
Notes
1
Table 51.
SDRAM Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Rising edge of clock-to-signal output. Outputs
included in this timing are SDM_ADDR[12:0],
SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE,
SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N,
SDM_RAS_N, SDM_DQ[31:0] (during a write
operation).
Tclk2out
5.5
ns
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
SDM_DQ[31:0] (during a write operation).
Tholdout
1.5
ns
1
NOTES:
1. Timing test were performed with a 70-pF load to ground.
5.5.2.7
Expansion Bus
Figure 25.
Intel Multiplexed Mode
T1
T2
T3
T4
T5
2-5 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
ALE Extended
EX_CLK
T
recov
T
T
EX_CS_N
EX_ADDR
EX_ALE
alepulse
ale2valcs
Valid Address
T
dhold2afterwr
T
wrpulse
EX_WR_N
T
dval2valwrt
T
ale2addrhold
Multiplexed Address/Data
Output Data
EX_DATA
EX_RD_N
EX_DATA
Address
T
rdsetup
T
rdhold
Address
Input Data
A9585-01
Datasheet
93
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 52.
Intel Multiplexed Mode Values
Symbol
Parameter
Min. Max. Units Notes
Talepulse
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
1
1
41
1
Cycles 1, 7
Cycles 1, 2, 7
Cycles 3, 7
Cycles 4, 7
Cycles 5, 7
Cycles 7
ns
Tale2addrhold Valid address hold time after from falling edge of ALE
Tdval2valwrt
Twrpulse
Write data valid prior to WR_N falling edge
Pulse width of the WR_N
1
4
1
16
4
Tdholdafterwr Valid data after the rising edge of WR_N
1
Tale2valcs
Trdsetup
Trdhold
Valid chip select after the falling edge of ALE
Data valid required before the rising edge of RD_N
Data hold required after the rising edge of RD_N
1
4
5.3
2
14.7
ns
Time needed between successive accesses on expansion
interface.
Trecov
1
16
Cycles 6
NOTES:
1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.
The parameter Tale2addrhold is fixed at 1 cycle.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
Figure 26.
Intel Simplex Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
EX_CLK
T
recov
EX_CS_N
EX_ADDR
EX_WR_N
Valid Address
T
wrpulse
T
dval2valwrt
T
T
addr2valcs
dhold2afterwr
Output Data
EX_DATA
EX_RD_N
EX_DATA
T
rdsetup
T
rdhold
Input Data
A9586-01
94
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 53.
Intel Simplex Mode Values
Symbol
Parameter
Min. Max. Units
Notes
Taddr2valcs
Tdval2valwrt
Twrpulse
Valid address to valid chip select
1
1
1
1
4
4
Cycles 1, 2, 7
Cycles 3, 7
Cycles 4, 7
Cycles 5, 7
Write data valid prior to EXPB_IO_WRITE_N falling edge
Pulse width of the EXP_IO_WRITE_N
16
4
Tdholdafterwr Valid data after the rising edge of EXPB_IO_WRITE_N
Data valid required before the rising edge of
EXP_IO_READ_N
Trdsetup
5.3
2
14.7
ns
ns
Data hold required after the rising edge of
EXP_IO_READ_N
Trdhold
Time required between successive accesses on the
expansion interface.
Trecov
1
16
Cycles
6
NOTES:
1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external
device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
Figure 27.
Motorola* Multiplexed Mode
T1
T2
T3
T4
T5
2-5 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
ALE Extended
EX_CLK
T
recov
EX_CS_N
T
T
alepulse
ale2valcs
EX_ADDR
EX_ALE
Valid Address
T
dhold2afterds
EX_RD_N
(exp_mot_rnw)
T
dspulse
EX_WR_N
(exp_mot_ds_n)
T
dval2valds
T
ale2addrhold
Multiplexed Address/Data
Output Data
EX_DATA
Address
EX_RD_N
(exp_mot_rnw)
T
rdsetup
EX_WR_N
(exp_mot_ds_n)
T
rdhold
Address
Input Data
EX_DATA
A9587-01
Datasheet
95
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 54.
Motorola* Multiplexed Mode Values
Symbol
Talepulse
Parameter
Min. Max. Units
Notes
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
1
1
1
1
1
1
4
1
Cycles 1, 7
Tale2addrhold Valid address hold time after from falling edge of ALE
Cycles 1, 2, 7
Cycles 3, 7
Cycles 4, 7
Cycles 5, 7
Tdval2valds
Tdspulse
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
4
16
4
Tdholdafterds Valid data after the rising edge of EXP_MOT_DS_N
Tale2valcs
Trdsetup
Trdhold
Valid chip select after the falling edge of ALE
4
Cycles
ns
7
Data valid required before the rising edge of EXP_MOT_DS_N 5.3
14.7
Data hold required after the rising edge of EXP_MOT_DS_N
2
ns
Time needed between successive accesses on expansion
interface.
Trecov
1
16
Cycles
6
NOTES:
1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.
The parameter Tale2addrhold is fixed at 1 cycle
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
96
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 28.
Motorola* Simplex Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
EX_CLK
T
recov
EX_CS_N
T
ad2valcs
EX_ADDR
Valid Address
T
dhold2afterds
EX_RD_N
(exp_mot_rnw)
T
dspulse
EX_WR_N
(exp_mot_ds_n)
T
dval2valds
Output Data
EX_DATA
EX_RD_N
(exp_mot_rnw)
T
rdsetup
EX_WR_N
(exp_mot_ds_n)
T
rdhold
Input Data
EX_DATA
A9588-01
Datasheet
97
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 55.
Motorola* Simplex Mode Values
Symbol
Parameter
Min. Max. Units
Note
s
1, 2,
7
Tad2valcs
Valid address to valid chip select
1
4
Cycles
Tdval2valds
Tdspulse
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
1
1
1
4
16
4
Cycles 3, 7
Cycles 4, 7
Cycles 5, 7
Tdholdafterds
Valid data after the rising edge of EXP_MOT_DS_N
Data valid required before the rising edge of
EXP_MOT_DS_N
Trdsetup
Trdhold
Trecov
5.3
2
14.7
ns
ns
Data hold required after the rising edge of
EXP_MOT_DS_N
Time required between successive accesses on the
expansion interface.
1
16
Cycles
6
NOTES:
1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
98
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 29.
HPI – 8 Mode Write Accesses
T1
T2
T3
T4 T5 T1 T2
T3
T4
T5
EX_CLK
EX_CS_N
(hcs_n)
Trecov
Tadd_setup
Valid
EX_ADDR[2:1]
(hcntl)
Valid
EX_RD_N
(hr_w_n)
EX_ADDR[0]
(hbil)
Thds1_pulse
Tcs2hds1val
EX_WR_N
(hds1_n)
EX_RDY_N
(hrdy)
Tdata_hold
Tdata_setup
EX_DATA
(hdin)
Data
Data
Table 56.
HPI Timing Symbol Description
State
T1
Description
Min Max
Unit
Notes
Address Timing
Setup/Chip Select Timing
Strobe Timing
3
3
2
3
2
4
4
Cycles
Cycles
Cycles
Cycles
Cycles
1, 5, 6
2, 6
3, 5, 6
6
T2
T3
16
4
T4
Hold Timing
T5
Recovery Phase
17
6
Table 57.
HPI – 8 Mode Write Accesses Values
Symbol
Parameter
Min. Max. Units Notes
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
Tadd_setup
11
45
Cycles 1, 5, 6
Delay from chip select being active and the HDS1 data
strobe being active.
Tcs2hds1val
Thds1_pulse
Tdata_setup
Tdata_hold
Trecov
3
4
4
4
2
4
5
Cycles 5, 6
Cycles 2, 4, 5
Cycles 3, 5, 6
Cycles 3, 6
Cycles 4, 6
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data
strobe.
5
Data valid after the rising edge of the HDS1 data strobe.
36
17
Time required between successive accesses on the
expansion interface.
Datasheet
99
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the address phase for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the data setup phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
Table 58.
Setup/Hold Timing Values
Parameter
Min. Max. Units Notes
Output Valid.
Output Hold
Input Setup
Input Hold.
15
0
ns
ns
ns
ns
1
1
1
1
3
2
NOTES:
1. The Setup and Hold Timing Values are for all modes.
100
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 59.
HPI-16 Multiplexed Write Accesses Values
Max
.
Symbol
Parameter
Min.
Units Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Tadd_setup
Tcs2hds1val
11
3
45
4
Cycles 1, 5, 6
Cycles 5, 6
Delay from chip select being active and the HDS1 data
strobe being active.
Thds1_pulse
Tdata_setup
Tdata_hold
Pulse width of the HDS1 data strobe
4
4
4
5
5
Cycles 2, 4, 5
Cycles 3, 5, 6
Cycles 3, 6
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
36
Time required between successive accesses on the
expansion interface.
Trecov
2
17
Cycles 4, 6
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the address phase for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the data setup phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
Figure 30.
HPI-16 Multiplex Write Mode
T1
T2
T5
T1 T2
T4
T3
T3
T4
EX_CLK
EX_CS_N
(hcs_n)
Trecov
Tadd_setup
Valid
EX_ADDR[2:1]
(hcntl)
Valid
EX_RD_N
(hr_w_n)
Tcs2hds1val
Thds1_pulse
Tdata_setup
EX_WR_N
(hds1_n)
EX_RDY_N
(hrdy)
Tdata_hold
Data
EX_DATA
(hdin)
Data
Datasheet
101
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 60.
HPI-16 Multiplex Read Accesses Values
Symbol
Parameter
Min. Max. Units Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
T
11
45
Cycles 1, 5, 6
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
3
4
4
4
5
5
Cycles 5, 6
cs2hds1val
T
Pulse width of the HDS1 data strobe
Cycles 2, 4, 5
Cycles 3, 5, 6
hds1_pulse
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
T
data_setup
Time required between successive accesses on the
expansion interface.
T
2
17
cycles 4, 6
recov
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the address phase for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the data setup phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
102
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 31.
HPI-16 Multiplex Read Mode
T1
T2
T3
T4
T5 T1 T2 T3 T4 T5
EX_CLK
EX_CS_N
(hcs_n)
Trecov
Tadd_setup
Valid
EX_ADDR[2:1]
(hcntl)
Valid
EX_RD_N
(hr_w_n)
Tcs2hds1val
Thds1_pulse
EX_WR_N
(hds1_n)
EX_RDY_N
(hrdy)
Tdata_setup
Valid Data
EX_DATA
(hdout)
Data
Datasheet
103
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 61.
HPI-16 Non-Multiplex Read Accesses Values
Symbol
Parameter
Min. Max. Units
Notes
Valid time that address is asserted on the line. The address is
asserted at the same time as chip select.
T
11
45
Cycles 1, 5, 6
add_setup
Delay from chip select being active and the HDS1 data strobe
being active.
T
3
4
4
4
5
5
Cycles 5, 6
cs2hds1val
T
Pulse width of the HDS1 data strobe
Cycles 2, 4, 5
Cycles 3, 5, 6
hds1_pulse
Data is valid from the time from of the falling edge of HDS1_N
to when the data is read.
T
data_setup
Time required between successive accesses on the
expansion interface.
T
2
17
Cycles 4, 6
recov
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the address phase for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the data setup phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
Figure 32.
HPI-16 Non-Multiplex Read Mode
T1
T2
T3
T4
T5 T1
T2
T3
EX_CLK
EX_CS_N
(hcs_n)
Trecov
Tadd_setup
EX_ADDR[23:0]
(ha)
Valid
Valid
EX_RD_N
(hr_w_n)
Thds1_pulse
Tcs2hds1val
EX_WR_N
(hds1_n)
EX_RDY_N
(hrdy)
Tdata_setup
EX_DATA
(hdout)
Valid Data
Valid Data
104
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 62.
HPI-16 Non-Multiplexed Write Accesses Values
Symbol
Parameter
Min. Max. Units
Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
T
11
3
45
4
Cycles 1, 5, 6
Cycles 5, 6
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
cs2hds1val
T
Pulse width of the HDS1 data strobe
4
4
4
5
5
Cycles 2, 4, 5
Cycles 3, 5, 6
Cycles 3, 6
hds1_pulse
T
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
data_setup
T
36
data_hold
Time required between successive accesses on the
expansion interface.
T
2
17
Cycles 4, 6
recov
N1OT.EST: he address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the address phase for at least one clock pulse after the HRDY is de-active.
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
for setup phase.
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product
Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
the data setup phase for at least one clock pulse after the HRDY is de-active
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
Expansion Bus interface.
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
until HRDY is de-active
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet
105
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 33.
HPI-16 Non-Multiplex Write Mode
T1 T2
T5
T1 T2
T3
T4
T3
T4
EX_CLK
EX_CS_N
(hcs_n)
Trecov
Tadd_setup
Valid
_ADDR[23:0]
(ha)
Valid
EX_RD_N
(hr_w_n)
Thds1_pulse
Tcs2hds1val
EX_WR_N
(hds1_n)
EX_RDY_N
(hrdy)
Tdata_hold
Tdata_setup
EX_DATA
(hdin)
Data
Data
106
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2.7.1
EX_IOWAIT_N
The EX_IOWAIT_N signal is available to be shared by devices attached to Chip Selects 0 through
7 and is used as required by slow devices.
If the external device asserts EX_IOWAIT_N during the strobe phase of a read transfer, the
controller will hold in that phase until the EX_IOWAIT_N goes false. At that time, the controller
will immediately transition to the hold phase regardless of the setting of the programming
parameter (T3) for the strobe phase.
The EX_IOWAIT_N signal only affects the interface during the strobe phase of a read transfer. If
Chip Selects 4 through 7 are configured in HPI mode of operation, each chip select will have a
corresponding HRDY signal called EX_RDY. The polarity of the ready signal is programmable.
Chip Select 4 corresponds to EX_RDY signal 0 and Chip Select 7 corresponds to EX_RDY signal
3.
5.5.2.8
High-Speed, Serial Interfaces
High-Speed, Serial Timings
Figure 34.
T2
T4
T9
T1
T3
As Inputs:
hss_txclk/
hss_rxclk1
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ rxdata
(Positive edge)
Valid Data
hss_ rxdata
(Negative edge)
Valid Data
T5
T6
T7
T8
As Outputs:
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ txdata
(Positive edge)
Valid Data
hss_ txdata
(Negative edge)
Valid Data
A9594-01
Datasheet
107
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 63.
High-Speed, Serial Timing Values
Symbol
Parameter
Min.
Max.
Units Notes
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the rising edge of clock
T1
5
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 4
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the rising edge of clock
T2
T3
T4
T5
T6
T7
0
5
0
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the falling edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the falling edge of clock
Rising edge of clock to output delay for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
15
15
Falling edge of clock to output delay for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
1, 3, 4
1, 3, 4
Output Hold Delay after rising edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
0
0
Output Hold Delay after falling edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
T8
T9
ns
ns
1,3, 4
5
HSS_TXCLK period and HSS_RXCLK period
1/8.192 MHz 1/512 KHz
NOTES:
1. HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the
IXP42X product line and IXC1100 control plane processors. The signals are shown to be synchronous for
illustrative purposes and are not required to be synchronous.
2. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source
as inputs into the IXP42X product line and IXC1100 control plane processors. Always applicable to
HSS_RXDATA.
3. The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of
the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK
and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.
4. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X product
line and IXC1100 control plane processors to an external source. Always applicable to HSS_TXDATA.
5. The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X product
line and IXC1100 control plane processors. The slowest clock speed that can be accepted or driven is
512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle
accepted will be 50/50 + 20%.
6. Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor.
For more information on the HSS Jitter Specifications see the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor Developer’s Manual
108
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.2.9
JTAG
Figure 35.
Boundary-Scan General Timings
T
T
bsch
bsel
JTG_TCK
JTG_TMS, JTG_TDI
T
bsis
T
bsih
JTG_TDO
T
bsoh
T
bsod
B0416-01
Figure 36.
Boundary-Scan Reset Timings
JTG_TRST_N
T
bsr
JTG_TMS
T
T
bsrs bsrh
A9597-01
Table 64.
Boundary-Scan Interface Timings Values
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units Notes
T
JTAG_TCK low time
JTAG_TCK high time
50
50
ns
ns
2
2
bscl
T
bsch
JTAG_TDI, JTAG_TMS setup time
to rising edge of JTAG_TCK
T
T
10
10
ns
ns
ns
bsis
bsih
bsoh
bsod
JTAG_TDI, JTAG_TMS hold time
from rising edge of JTAG_TCK
JTAG_TDO hold time after falling
edge of JTAG_TCK
T
T
1.5
1
1
JTAG_TDO clock to output from
falling edge of JTAG_TCK
40
ns
ns
ns
T
JTAG_TRST_N reset period
30
10
bsr
JTAG_TMS setup time to rising
edge of JTAG_TRST_N
T
T
bsrs
JTAG_TMS hold time from rising
edge of JTAG_TRST_N
10
ns
bsrh
NOTES:
1. Tests completed with a TBD pF load to ground on JTAG_TDO.
2. JTAG_TCK may be stopped indefinitely in either the low or high phase.
Datasheet
109
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
5.5.3
Reset Timings
Figure 37.
Reset Timings
VCCP
VCC
PLL_LOCK
PWRON_RESET_N
RESET_IN_N
CFG Settings To Be Captured
CFG Settings To Be Captured
EX_ADDR[23:0]
IXP4XX/IXC1100 Drives Outputs
EX_ADDR[23:0]-Pull Up/Down
TEX_ADDR_HOLD
TRELEASE_RST_N
TPLL_LOCK
TRELEASE_PWRON_RST_N
TEX_ADDR_SETUP
B1679-02
110
Datasheet
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Table 65.
Reset Timings Table Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
Note
Minimum time required to hold the
PWRON_RST_N at logic 0 state after
stable power has been applied to the
IXP42X product line and IXC1100 control
plane processors. When using a crystal
to drive the processors’ system clock.
(OSC_IN and OSC_OUT)
T
T
500
ms
1
RELEASE_PWRON_RST_N
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
logic 1 state. The RESET_IN_N signal
must be held low when the
10
ns
RELEASE_RESET_IN_N
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
T
T
T
10
µs
ns
ns
PLL_LOCK
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
50
0
2
2
EX_ADDR_SETUP
EX_ADDR_HOLD
Minimum/maximum time for the
EX_ADDR signals to drive the inputs
prior to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
20
Minimum time required to drive
RESET_IN_N signal to logic 0 in order to
cause a reset after the IXP42X product
line and IXC1100 control plane
processors has been in normal operation.
The power must remain stable and the
PWRON_RST_N signal must remain
stable.
T
500
ns
WARM_RESET
NOTES:
1. T
is the time required for the internal oscillator to reach stability. When an external
RELEASE_PWRON_RST_N
oscillator is being used in place of a crystal, the 500-ms delay is not required.
2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a
programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be
active until PLL_LOCK is active.
3. PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after the
watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
5.6
Power Sequence
The 3.3-V I/O voltage (VCCP) must be powered up 1 µs before the core voltage (VCC). The
IXP42X product line and IXC1100 control plane processors’ core voltage (VCC) must never
become stable prior to the 3.3-V I/O voltage (VCCP). The VCCOSC, VCCPLL1, and VCCPLL2
voltages follow the VCC power-up pattern. The VCCOSCP follows the VCCP power-up pattern. The
value for TPOWER_UP must be at least 1 µs. The TPOWER_UP timing parameter is measured from
V
CCP at 3.3 V and VCC at 1.3 V. There are no power-down requirements for the IXP42X product
line and IXC1100 control plane processors.
Datasheet
111
Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Figure 38.
Power-up Sequence Timing
VCCP
VCC
TPOWER_UP
4
V
O
L
T
S
3
2
1
Time
B2263-01
5.7
I
and Total Average Power
CC
Table 66.
ICC and Total Average Power
Speed
Symbol
Description
Typ.1
Max..2
Units
Notes
I
Core supply current
I/O supply current
Total average power
Core supply current
I/O supply current
Total average power
Core supply current
I/O supply current
Total average power
0.70
0.17
1.50
0.75
0.17
1.57
0.82
0.17
1.66
0.95
0.26
2.20
1.05
0.260
2.34
1.15
0.260
2.47
A
A
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
CC
266 MHz
I
CCP
P
W
A
TOTAL
I
CC
400 MHz
I
A
CCP
P
W
A
TOTAL
I
CC
533 MHz
I
A
CCP
P
W
TOTAL
NOTES:
1. Typical current I and I
are not tested. Typical currents were measured on the Intel®
CC
CCP
IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon
samples. A SmartBits* tester was used in a router application running Linux on the
development board. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in
this router application.
2. Typical case power supply voltages V =1.327V, V
= 3.363 V.
CC
CCP
3. Maximum voltages: V = 1.365 V, V
= 3.465 V, V
= 1.365 V, V
= 1.365 V,
CCPLL1
CC
CCP
CCosc
V
= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum I and I
CCPLL2
CC CCP
specifications are tested and guaranteed.
4. The 400-MHz typical case core supply current is an approximation.
5.8
Ordering Information
For ordering information, please contact your local Intel sales representative.
112
Datasheet
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