QG41210_技术文档

Intel® 41210 Serial to Parallel PCI Bridge

Datasheet

Product Features

■ PCI Express Specification, Revision 1.0a

■ 2-level programmable round-robin internal

arbiter with Multi-Transaction Timer

(MTT)

■ Support for single x8, single x4 or single x1

PCI Express operation.

■ External PCI clock-feed support for

asynchronous primary and secondary

domain operation.

■ 64-bit addressing support

■ 32-bit CRC (cyclic redundancy checking)

covering all transmitted data packets.

■ 64-bit addressing for upstream and

■ 16-bit CRC on all link message

downstream transactions

information.

■ Downstream LOCK# support.

■ No upstream LOCK# support.

■ PCI fast Back-to-Back capable as target.

■ Raw bit-rate on the data pins of 2.5 Gbit/s,

resulting in a raw bandwidth per pin of

250 MB/s.

■ Maximum realized bandwidth on PCI

Express interface is 2 GB/s (in x8 mode) in

each direction simultaneously, for an

aggregate of 4 GB/s.

■ Up to four active and four pending

upstream memory read transactions

■ Up to two downstream delayed (memory

read, I/O read/write and configuration read/

write) transaction.

■ PCI Local Bus Specification, Revision 2.3.

■ PCI-to-PCI Bridge Specification,

■ Tunable inbound read prefetch algorithm

Revision 1.1.

for PCI MRM/MRL commands

■ PCI-X Addendum to the PCI Local Bus

Specification, Revision 1.0b

■ Device hiding support for secondary PCI

devices.

■ 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.

■ Secondary bus Private Memory support via

Opaque memory region

■ On Die Termination (ODT) with 8.3KOhm

pull-up to 3.3V for PCI signals.

■ Local initialization via SMBus

■ Six external REQ/GNT Pairs for internal

■ Secondary side initialization via Type 0

arbiter on segment A and B respectively.

configuration cycles.

■ Programmable bus parking on either the

■ Full peer-to-peer read/write capability

last agent or always on the 41210 Bridge

between the two secondary PCI segments.

Order Number: 278875-005US

May 2005

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Intel may make changes to specifications and product descriptions at any time, without notice.

The Intel® 41210 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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2

Contents

1

Introduction....................................................................................................................................7

1.1

1.2

About This Document ...........................................................................................................7

Product Overview .................................................................................................................7

2

Signal Description.........................................................................................................................8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

On Die Termination (ODT)....................................................................................................8

PCI Express Interface.........................................................................................................10

PCI Bus Interface (Two Instances).....................................................................................10

PCI Bus Interface 64-Bit Extension (Two Interfaces) .........................................................12

PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) ..............13

Interrupt Interface (Two Interfaces) ....................................................................................13

Reset Straps.......................................................................................................................13

SMBus Interface .................................................................................................................15

Miscellaneous Pins.............................................................................................................15

3

Electrical and Thermal Characteristics .....................................................................................17

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

DC Voltage and Current Specifications ..............................................................................17

AC Specifications................................................................................................................25

Voltage Filter Specifications ...............................................................................................27

VCC15 and VCC33 Voltage Requirements........................................................................27

Timing Specifications..........................................................................................................28

41210 Bridge Power Consumption.....................................................................................36

Power Delivery Guidelines..................................................................................................37

Reference and Compensation Pins....................................................................................37

Thermal Specifications .......................................................................................................38

4

Package Specification and Ballout............................................................................................40

4.1

4.2

4.3

4.4

Package Specification ........................................................................................................40

Ball Map..............................................................................................................................42

Signal List, sorted by Ball Location.....................................................................................44

Signal List, sorted by Signal Name.....................................................................................48

Figures

1

2

3

4

5

6

7

8

9

Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22

Compliance Test/Measurement Load.........................................................................................23

Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23

Voltage Requirements VCC33 versus VCC15 ...........................................................................27

PCI Output Timing ......................................................................................................................31

PCI Input Timing.........................................................................................................................31

PCI-X 3.3V Clock Waveform ......................................................................................................33

41210 Bridge Reference and Compensation Circuit Implementations.......................................38

41210 Bridge Package Dimensions (Top View) .........................................................................40

10 41210 Bridge Package Dimensions (Side View) ........................................................................41

3

Contents

Tables

1

2

3

4

5

6

7

8

9

ODT Signals .................................................................................................................................9

PCI Express Interface Pins.........................................................................................................10

PCI Interface Pins.......................................................................................................................11

PCI Interface Pins: 64-Bit Extensions.........................................................................................12

PCI Clock and Reset Pins ..........................................................................................................13

Interrupt Interface Pins ...............................................................................................................13

Reset Strap Pins.........................................................................................................................14

SMBus Interface Pins.................................................................................................................15

Miscellaneous Pins.....................................................................................................................15

10 Intel® 41210 Bridge DC Voltage Specifications .........................................................................17

11 DC Characteristics Input Signal Association ..............................................................................18

12 DC Input Characteristics.............................................................................................................18

13 DC Characteristic Output Signal Association .............................................................................18

14 DC Output Characteristic............................................................................................................19

15 Differential Transmitter (TX) DC Output Specifications..............................................................19

16 Differential Receiver (RX) DC Input Specifications ....................................................................21

17 DC Specifications for PCI and PCI-X 3.3 V Signaling ................................................................24

18 DC Specification for Input Clock Signals....................................................................................25

19 DC Specification for Output Clock Signals .................................................................................25

20 Conventional PCI 3.3V AC Characteristics ................................................................................25

21 PCI-X 3.3V AC Characteristics...................................................................................................26

22 Differential Transmitter (TX) AC Output Specifications ..............................................................28

23 Differential Receiver (RX) AC Input Specifications.....................................................................29

24 PCI Interface Timing...................................................................................................................30

25 PCI-X 3.3V Signal Timing Parameters .......................................................................................31

26 PCI and PCI-X Clock Timings ....................................................................................................33

27 41210 Bridge Clock Timings.......................................................................................................35

28 41210 Bridge Maximum Voltage Plane Currents .......................................................................37

29 41210 Bridge Thermal Voltage Plane Currents..........................................................................37

30 41210 Bridge Thermal Specifications.........................................................................................39

31 Signal List, sorted by Ball Name.................................................................................................44

32 Signal List, sorted by Signal Name.............................................................................................48

4

Contents

Revision History

Date

Revision

Description

Revised Table 1, Table 9, and Section 3.8

May 2005

April 2005

005

004

003

Revised Table 26 “PCI and PCI-X Clock Timings” on page 33 CLK Cycle Time parameters

Revised first page PCI Express operation description; updated information in Table 2.

September 2004

Added Chapter 2. Removed original Sections 3.6 and 3.7. Updated VCC information to

VCC15.

June 2004

002

001

September 2003

Initial release

5

Order Number: 278875-005US

May 2005

Datasheet — 41210 Bridge

Introduction

1

1.1

About This Document

This document provides information on the Intel^®41210 Serial to Parallel PCI Bridge, including a

functional overview, signal descriptions, mechanical data, package signal location and bus

functional waveforms.

1.2

Product Overview

The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge) integrates two PCI

Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model.

The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two

PCI bus interfaces are compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X

Addendum to the PCI Local Bus Specification, Revision 1.0b.

7

41210 Bridge — Datasheet

Signal Description

2

The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present after the signal name the signal is

asserted when at the high voltage level. The following notations are used to describe the signal

type:

I:

Input pin

O:

Output pin

OD:

I/O:

Open-drain Output pin

Bidirectional Input/Output pin

I/OD: Bidirectional Input/Open-drain Output pin

2.1

On Die Termination (ODT)

The 41210 Bridge incorporates on-die termination for most of the PCI interface signals. This

eliminates the need for the system designer to incorporate external pull-up resistors in the design.

The following signals have an on die termination of 8.33KOhm @40%:

8

Datasheet — 41210 Bridge

Table 1.

ODT Signals

A_ACK64#

A_AD[63:32]

A_CBE#[7:4]

A_DEVSEL#

A_FRAME#

A_GNT#[5:0]

A_IRDY#

A_PAR

B_ACK64#

B_AD[63:32]

B_CBE#[7:4]

B_DEVSEL#

B_FRAME#

B_GNT#[5:0]

B_IRDY#

B_PAR

A_PAR64

A_PERR#

A_LOCK#

A_REQ#[5:0]

A_REQ64#

A_SERR#

A_STOP#

A_TRDY#

A_INTA#

A_INTB#

A_INTC#

A_INTD#

TCK

B_PAR64

B_PERR#

B_LOCK#

B_REQ#[5:0]

B_REQ64#

B_SERR#

B_STOP#

B_TRDY#

B_INTA#

B_INTB#

B_INTC#

B_INTD#

TDI

TDO

TMS

9

41210 Bridge — Datasheet

2.2

PCI Express Interface

Table 2.

PCI Express Interface Pins

Signal

I/O

Description

REFCLKp/

REFCLKn

PCI Express Reference Clocks: 100 MHz differential clock pair.

I

PCI Express Serial Data Transmit: PCI Express differential data transmit

signals.

PETp[7:0]/

PETn[7:0]

X8 Mode: All PETp[7:0]/ PETn[7:0] are used

X4 Mode: Only PETp[3:0]/ PETn[3:0] are used

O

x1 Mode: Either PETp[0]/ PETn[0] is used or PETp[7]/ PETn[7] is used

PCI Express Serial Data Receive: PCI Express differential data receive

signals.

PERp[7:0]/

PERn[7:0]

X8 Mode: All PERp[7:0]/ PERn[7:0] are used

X4 Mode: Only PERp[3:0]/ PERn[3:0] are used

I

x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used

PCI Express Compensation Inputs: Analog signals. Connect to a

24.9Ω±1% pull-up resitor to 1.5V. A single resistor can be used for both

signals.

PE_RCOMP[1:0]

Total

I

36

2.3

PCI Bus Interface (Two Instances)

Each interface is marked by either the letter “A” or “B” to signify the interface. Therefore, A_AD

refers to the AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For pin names

described in the following sections, an ‘X’ in the name indicates either A or B, for the PCI bus A

and PCI bus B sides. For example, X_PAR signal would be called A_PAR on the PCI bus A and

B_PAR on the PCI bus B.

10

Datasheet — 41210 Bridge

Table 3.

PCI Interface Pins (Sheet 1 of 2)

Signal

I/O

Description

PCI Address/Data: These signals are a multiplexed address and data bus. During the address

phase or phases of a transaction, the initiator drives a physical address on X_AD[31:0]. During the

data phases of a transaction, the initiator drives write data, or the target drives read data.

A_AD[31:0]

B_AD[31:0]

I/O

No External pull-up resistors are required on the system board for these signals.

Bus Command and Byte Enables: These signals are a multiplexed command field and byte enable

field. During the address phase or phases of a transaction, the initiator drives the transaction type on

C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address

command and the second address phase carries the transaction type. For both read and write

transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases.

A_C/BE#[3:0]

B_C/BE#[3:0]

No External pull-up resistors are required on the system board for these signals.

Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits

regardless of the valid byte enables. It is generated for address and data phases. It is driven

identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during

the address phase for all 41210 Bridge initiated transactions and all data phases when the 41210

Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction.

A_PAR

B_PAR

I/O

41210 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of

PCI write transactions.

No External pull-up resistors are required on the system board for these signals.

Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41210 Bridge

asserts DEVSEL# when a PCI master peripheral attempts an access an address destined for PCI

Express. As an initiator, DEVSEL# indicates the response to a 41210 Bridge initiated transaction on the

PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by

the 41210 Bridge until driven as a target.

A_DEVSEL#

B_DEVSEL#

No External pull-up resistors are required on the system board for these signals.

Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While

FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final

data phase.

A_FRAME#

B_FRAME#

I/O

No External pull-up resistors are required on the system board for these signals.

Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the

transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted.

A_IRDY#

B_IRDY#

No External pull-up resistors are required on the system board for these signals.

Target Ready: Indicates the ability of the target to complete the current data phase of the transaction.

A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated

from the leading edge of RST#. TRDY# remains tri-stated by the 41210 Bridge until driven as a target.

A_TRDY#

B_TRDY#

I/O

No External pull-up resistors are required on the system board for these signals.

Stop: Indicates that the target is requesting an initiator to stop the current transaction.

A_STOP#

B_STOP#

No External pull-up resistors are required on the system board for these signals.

Parity Error: Driven by an external PCI device when it receives data that has a parity error. Driven by

41210 Bridge when, as a initiator it detects a parity error during a read transaction and as a target

during write transactions.

A_PERR#

B_PERR#

No External pull-up resistors are required on the system board for these signals.

System Error: The 41210 Bridge samples SERR# as an input and conditionally forwards it to the

A_SERR#

B_SERR#

PCI Express.

I

No External pull-up resistors are required on the system board for these signals.

66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high

then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be used

to generate appropriate clock (33 or 66 MHz) on the PCI Bus.

A_M66EN

B_M66EN

I/OD

Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground.

11

41210 Bridge — Datasheet

Table 3.

PCI Interface Pins (Sheet 2 of 2)

Signal

I/O

Description

A_PCIXCAP

B_PCIXCAP

PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the 41210

Bridge can switch into PCI-X mode. Use an approximately 8.2KΩ resistor to pull to VCC33.

I

PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete.

This signal is an output from the bridge when it is initiating exclusive transactions on PCI. LOCK# is

ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream.

A_LOCK#

B_LOCK#

O

No External pull-up resistors are required on the system board for these signals.

Total

118

2.4

PCI Bus Interface 64-Bit Extension (Two Interfaces)

Table 4.

PCI Interface Pins: 64-Bit Extensions

Signal

I/O

Description

PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an

additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the

upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when

REQ64# and ACK64# are both asserted.

A_AD[63:32]

B_AD[63:32]

I/O

Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and

byte enable field. For both reads and write transactions, the initiator will drive byte enables for the

AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both

A_C/BE#[7:4]

B_C/BE#[7:4]

I/O

asserted.

A_PAR64

B_PAR64

PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/

BE#[7:4] for both address and data phases.

I/O

PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is

requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41210 Bridge is

the initiator, this signal is an output. When the 41210 Bridge is the target this signal is an input.

A_REQ64#

B_REQ64#

PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is

asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same

timing as DEVSEL#.

A_ACK64#

B_ACK64#

I/O

78

Total

12

Datasheet — 41210 Bridge

2.5

PCI Bus Interface Clocks and, Reset and Power

Management (Two Interfaces)

Table 5.

PCI Clock and Reset Pins

Signal

I/O

Description

PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. X_CLK[6] must be connected to the

respective X_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be

disabled via the “Offset 43: PCLKC – PCI Clock Control” register and should be treated as no

connects on the board.

A_CLKO[6:0]

B_CLKO[6:0]

O

Note: Registers are listed in the Intel® 41210 Serial to Parallel PCI Bridge

Developer’s Manual.

A_CLKIN

B_CLKIN

PCI Clock In: This signal is PCI clock feedback input. This pin should be connected to the

corresponding X_CLKO[6] through a 22Ω±1% series resistor.

I

A_RST#

B_RST#

O

PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus.

PCI Power Management Event: PCI bus power management event signal. This is a shared open

drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive

signal that will be converted to a PME event on PCI Express.

A_PME#

B_PME#

I

This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally.

Total

20

2.6

Interrupt Interface (Two Interfaces)

This section lists the interrupt interface signals. There are two sets of interrupt signals for the

standard INTA:INTD pci signals.

Table 6.

Interrupt Interface Pins

Signal

I/O

Description

A_INTA#

A_INTB#

A_INTC#

A_INTD#

Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these

interrupt lines.

I

B_INTA#

B_INTB#

B_INTC#

B_INTD#

Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information on device

numbering.

Total

8

2.7

Reset Straps

The following signals are used for static configuration. These signals are all sampled on the rising

edge of PERST#.

13

41210 Bridge — Datasheet

Table 7.

Reset Strap Pins

Signal

I/O

Description

PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to

run at 133 MHz when X_PCIXCAP is sampled high. When low, the PCI-X

segment will only run at 100 MHz when X_PCIXCAP is sampled high.

A_133EN

B_133EN

I

Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to

ground.

Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3

must be pulled high for normal operation.

X_STRAP Logic Level

0

1

2

3

4

5

6

‘0’

‘1’

‘0’

A_STRAP[6:0

]

I

B_STRAP[6:0

]

Use approximately an 8.2KΩ resistor to pull-up to VCC33 or pull-down to

VSS

Internal Test Modes: These straps should be pulled high to VCC33.

Use approximately an 8.2KΩ resistor to pull-up to VCC33.

A_TEST[2:1]

B_TEST{2:1]

I

Configuration Retry: This pin, when sampled high sets the Configuration

Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC.

If no local initialization is needed, this pin should be pulled low to VSS.

CFGRETRY

Total

Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for

more information.

19

14

Datasheet — 41210 Bridge

2.8

SMBus Interface

Table 8.

SMBus Interface Pins

Signal

I/O

Description

SMBus Clock: This signal should be pulled to 3.3V via an 8.2KOhm

resistor.

SMBCLK

I/OD

SMBus Data: This signal should be pulled to 3.3V via an 8.2KOhm

resistor.

SMBDAT

I/OD

SMBus Addressing Straps: These straps set the SMBus Address for

41210 Bridge. The address is determined as indicated below:

Bit 7‘1’

Bit 6‘1’

Bit 5SMBUS[5]

Bit 4‘0’

SMBUS[5]

I

SMBUS[3:1]

Bit 3SMBUS[3]

Bit 2SMBUS[2]

Bit 1SMBUS[1]

These signals (bits 5, 3:1) should be pulled up to 3.3V or down to

ground. Sampled at the rising edge of PERST#.

Total

6

2.9

Miscellaneous Pins

Table 9.

Miscellaneous Pins

Signal

I/O

Description

Configuration Reset: This signal is asserted low when ever the bridge goes

through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This

signal should be used to indicate when the local initialization methods should be

executed.

CFGRST#

O

Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more

information.

PCI Express Fundamental Reset: When low, asynchronously resets the

internal logic (including sticky bits).

PERST#

RSTIN#

I

Reset In: When Asserted, this signal asynchronously resets the internal logic

and asserts X_RST# output for both PCI interfaces. This signal should be pulled

high for adapter card usage.

TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable

frequency is 0-16MHz

TCK

I

If not utilizing JTAG, this signal can be left as a no connect.

Test Data In: This is the serial data input to the JTAG BSCAN shift register

chain and to the JTAG BSCAN control logic. This is latched in on the rising edge

of TCK.

TDI

I

If not utilizing JTAG, this signal can be left as a no connect.

Test Data Output: This is the serial data output from the JTAG BSCAN logic

If not utilizing JTAG, this signal can be left as a no connect.

TDO

O

15

41210 Bridge — Datasheet

Signal

I/O

Description

Test Mode Select: This signal controls the TAP controller state machine to

move to different states and is sampled on the rising edge of TCK.

If not utilizing JTAG, this signal can be left as a no connect.

TMS

I

Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN

logic.

TRST#

I

If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down

resistor.

Reserved: (8 pins) These input pins should be pulled low

Use an approximately 8.2KΩ resistor to pull-down to ground.

RESERVED[8:1]

NC[19:18], NC[16:1]

A_NC[10:1]

O

No Connect: (39 pins) These output pins should be left floating

B_NC[10:1]

NC[17]

Total

This signal requires an external pull-up, 8.2K ohm to 3.3V

57

16

Datasheet — 41210 Bridge

Electrical and Thermal Characteristics 3

3.1

DC Voltage and Current Specifications

3.1.1

41210 Bridge DC Specifications

Table 10.

Intel^®41210 Bridge DC Voltage Specifications

Symbol

VCC15

Parameter

Min

1.425

Typ

Max

1.575

Unit

Notes

Intel^®41210 Bridge Core

PCI-X I/O Voltage

1.5

2.5

1.5

3.3

V

VCC15

1.425

1.455

2.425

1.46

1.575

1.545

2.575

1.55

VCCAPE

Analog PCI Express Voltage

1

VCCAPCI[2:0] Analog PCI Voltages

VCCBGPE

VCCPE

Analog Bandgap Voltage

PCI Express Interface Voltage

PCI Bus Interface Voltage

2

V

VCC33

3.0

3.6

P

Thermal Design Power

10.2

W

TDP

1. Transient tolerance ±5 mV above 1 MHz at package pin under DC load conditions.

2. Transient tolerance ±10 mV above 1 MHz at package pin under DC load conditions.

17

41210 Bridge — Datasheet

3.1.2

Input Characteristic Signal Association

Table 11.

DC Characteristics Input Signal Association

Symbol

Signals

Interrupt Signals: A_IRQ[15:0]#, B_IRQ[15:0]#

PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR,

A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#,

B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_SERR#, B_SERR#, A_REQ[5:0]#,

B_REQ[5:0]#, A_M66EN, B_M66EN, A_133EN, B_133EN, A_PCIXCAP, B_PCIXCAP,

A_PAR64, B_PAR64, A_REQ64#, B_REQ64#, A_ACK64#, B_ACK64#

V

/V

IH1 IL1

Clock Signals (3.3 V Only): A_CLKI, B_CLKI

Miscellaneous Signals: PERST#

V

/V

PCI Express Signals: REFCLK, REFCLK#, PETP[7:0], PETN[7:0], PE_RCOMP[1:0]

SMB Signals: SMBDAT, SMBCLK

IH2 IL2

/V

IH3 IL3

3.1.3

DC Input Characteristics

Table 12.

DC Input Characteristics

3.3 V Signal

Max

Symbol

Parameter

Unit

Min

V

Input Low Voltage

Input High Voltage

-0.5

0.35 VCC33

VCC33 +0.5

V

IL1

V

0.5 VCC33

IH1

Symbol

Parameter

Max

V

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

N/A

0.6

V

IL2

IH2

IL3

IH3

V

VCC33 + 0.5

3.1.4

DC Characteristic Output Signal Association

Table 13.

DC Characteristic Output Signal Association

Symbol

Signals

PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR,

A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#,

B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_M66EN, B_M66EN,

A_GNT[6:0]#, B_GNT[5:0]#, A_LOCK#, B_LOCK#, A_PAR64, B_PAR64, A_REQ64#,

B_REQ64#, A_ACK64#, B_ACK64#

V

/V

OH1 OL1

PCI Clock Signals (3.3 V Only): A_CLKO[6:0], B_CLKO[6:0], A_RST#, B_RST#

Miscellaneous Signals: RASERR#

V

/V

PCI Express Signals: PERP[7:0], PERN[7:0]

SMBus Signals: SMBDAT, SMBCLK

OH2 OL2

/V

OH3 OL3

18

Datasheet — 41210 Bridge

3.1.5

DC Output Characteristics

Table 14.

DC Output Characteristic

3.3 V Signal

Symbol

Parameter

Unit

Notes

Min

Max

0.1VCC33

(5 V) Iout = 6 mA

V

Output Low Voltage

V

OL1

(3.3 V) Iout = 1500 uA

(5 V) Iout = -2 mA

V

Output High Voltage

0.9VCC33

OH1

(3.3 V) Iout = -500 uA

Symbol

Parameter

Max

Unit

Notes

V

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

N/A

0.4

V

OL2

OH2

OL3

OH3

V

I

=14 mA

OL4

N/A

Open Drain

3.1.6

PCI Express Interface DC Specifications

3.1.6.1

Differential Transmitter (TX) DC Output Specifications

Table 15 defines the DC specifications of parameters for the differential output at all transmitters

(TXs). The parameters are specified at the component pins.

Table 15.

Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2)

Symbol

Parameter

Min

Nom Max Units

Comments

= 2*|V

Differential Peak to

Peak Output

Voltage

V

TX-D+- TX-D-

|

TX-DIFFp-p

V

0.80

1.2

V

TX-DIFFp-p

See Note 1.

This is the ratio of the V

second and following bits after a

transition divided by the V

of the

of

TX-DIFFp-p

De-Emphasized

Differential Output

Voltage (Ratio)

V

-3.0

-3.5

-4.0

dB

TX-DIFFp-p

TX-DE-RATIO

the first bit after a transition

See Note 1.

V

= |V

+ v

| / 2 – v

TX-

TX-CM-ACp

CM-DC

TX-D+

TX-D-

AC Peak

V

Common Mode

Output Voltage

20

mV

v

= DC

during L0

of |V

+ V

TX-D-|

TX-CM-ACp

TX-CM-DC

(avg)

TX-D+

/ 2

See Note 1.

|V

V

TX-CM-DC [during L0] – TX-CM-Idle-

Absolute Delta of

DC Common Mode

Voltage During L0

and Electrical Idle

| <= 100mv

DC[during electrical idle]

TX-CM-DC-

0

100

V

DC

of |V

+ V

|

ACTIVE-IDLE-

DELTA

TX-CM-DC =

(avg)

TX-D+

TX-D-

/ 2 [electrical idle]

See Note 1.

19

41210 Bridge — Datasheet

Table 15.

Differential Transmitter (TX) DC Output Specifications (Sheet 2 of 2)

|V

V

TX-CM-DC-D+ [during L0] – TX-CM-DC-D-

|<=25mV

[During L0.]

Absolute Delta of

DC Common Mode

Voltage between D+

and D-.

V

DC

of |V

|

TX-D+

TX-CM-DC-D+ =

(avg)

V

TX-CM-DC-

LINE-DELTA

[during L0]

0

25

mV

V

DC

|V

of |V

|

TX-D-

TX-CM-DC-D- =

(avg)

[during L0]

See Note 1.

V

Electrical Idle

Differential Peak

Output Voltage

TX-IDLE-DIFFp = TX-Idle-D+ - Tx-Idle-D-

V

TX-IDLE-

DIFFp

|<=20mV

20

mV

See Note 1.

The amount of

voltage change

allowed during

The total amount of voltage change that

a transmitter can apply to sense

whether a low impedance receiver is

present.

V

TX-RCV-

DETECT

600

Receiver Detection.

Differential Return

Loss

Measured over 50 MHz to 1.25 GHz

See Note 2.

RL

12

6

dB

W

TX-DIFF

Common Mode

Return Loss

Measured over 50 MHz to 1.25 GHz

See Note 2.

TX-CM

DC Differential TX

Impedance

TX DC Differential Mode Low

impedance

Z

80

100

120

20k

TX-DIFF-DC

Transmitter

TX-COM-

Common Mode

High Impedance

State (DC)

5 k

75

W

TX DC High Impedance.

High-

IMP-DC

All transmitters shall be AC coupled.

The AC coupling is required either

within the media or within the

AC Coupling

Capacitor

C

200

nF

TX

transmitting component itself.

1. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,

“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also

refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage

Output Compliance Specification.)

2. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a

common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This

input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements is 50W to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer

with 50W probes – see Figure 2). Note that the series capacitors CTX is optional for the return loss

measurement.

20

Datasheet — 41210 Bridge

3.1.6.2

Differential Receiver (RX) DC Input Specifications

Table 16 defines the DC specifications of parameters for all differential Receivers (RXs). The

parameters are specified at the component pins.

Table 16.

Differential Receiver (RX) DC Input Specifications

Symbol

Parameter

Min

Nom Max Units

Comments

= 2*|V

Differential Input

Peak to Peak

Voltage

V

|

0.17

5

1.20

V

RX-DIFFp-p

RX-D+ - RX-D-

V

RX-DIFFp-p

0

See Note 1.

V

=

RX-CM-AC

|V

+

|/2– V

RX-CM-DC

RX-D+ VRX-D-

V

RX-CM-DC =

AC Peak Common

Mode Input Voltage

V

150

mV

RX-CM-ACp

DC

of |V

+V

|/2 during L0

RX-D-

(avg)

RX-D+

See Note 1.

Measured over 50 MHz to 1.25 GHz

See Note 2.

Differential Return

Loss

RL

15

6

dB

W

RX-DIFF

Measured over 50 MHz to 1.25 GHz

See Note 2

Common Mode

Return Loss

RX-CM

RX DC Differential Mode impedance.

See Note 3.

DC Differential Input

Impedance

Z

80

100

50

120

60

RX-DIFF-DC

RX DC Common Mode impedance 50

?+/-20% tolerance.

DC Input Common

Mode Input

Impedance

RX-COM-

40

5

W

DC

See Notes 1 and 3.

RX DC Common Mode impedance

allowed when the receiver terminations

are first powered on.

Initial DC Input

Common Mode

Input Impedance

Z

RX-COM-

INITIAL-DC

50

60

See Note 4.

RX DC Common Mode impedance when

the receiver terminations are not

powered (i.e., no power).

Powered Down DC

Input Common

Mode Input

Z

RX-COM-

200 k

65

W

HIGH-IMP-

DC

Impedance

See Note 5.

V

=2*|V

-

|

RX-IDLE-

RX-IDLE-DET-DIFFp-p

RX-D+ VRX-D-

Electrical Idle

Detect Threshold

175

mV

Measured at the package pins of the

Receiver.

DET-DIFFp-

p

1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,

“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking

measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum

Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are

not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.

2. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a

common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This

input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements for is 50 Ω to ground for both the D+ and D- line (i.e., as measured by a Vector Network

Analyzer with 50Ω probes - see Figure 2). Note: that the series capacitors C is optional for the return loss

TX

measurement.

3. Impedance during all operating conditions.

4. The Rx DC Common Mode Impedance that must be present when the receiver terminations are first enabled

to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately

and the (Z

)RxDC Common Mode Impedance must be with in the specified range by the time

RX-COM-DC

Detect is entered.

5. The Rx DC Common Mode Impedance that exists when the receiver terminations are disabled or when no

power is present. This helps ensure that the Receiver Detect circuit will not falsely assume a receiver is

powered on when it is not.

21

41210 Bridge — Datasheet

Figure 1.

Minimum Transmitter Timing and Voltage Output Compliance Specification

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be

aligned in time using the jitter median to locate the center of the eye diagram. The different eye

diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit.

The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must

be used as the interval for measuring the eye diagram.

3.1.6.3

Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified by

the device vendor within 0.2 inches of the package pins, into a test/measurement load shown in

Figure 2.

Note:

The allowance of the measurement point to be within 0.2 inches of the package pins is meant to

acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at

the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the

measurement point is assumed to be the D+ and D-package pins.

22

Datasheet — 41210 Bridge

Figure 2.

Compliance Test/Measurement Load

The test load is shown at the transmitter package reference plane, but the same Test/Measurement

load is applicable to the receiver package reference plane. CTX is an optional portion of the

measurement test load. The measurement should be taken on the opposite side of the capacitor

from the package, and the value of the CTX must be in the range of 75 nF to 200 nF.

.

Figure 3.

Minimum Receiver Eye Timing and Voltage Compliance Specification

The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye

diagram. The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX

UI must be used as the interval for measuring the eye diagram.

23

41210 Bridge — Datasheet

3.1.6.4

PCI and PCI-X Interface DC Specifications

Table 17 summarizes the DC specifications for 3.3V signaling.

Table 17.

DC Specifications for PCI and PCI-X 3.3 V Signaling

Symbol

Parameter

Supply Voltage

Min

Max

Units

Condition

Notes

VCC33

3.0

3.6

V

Input High Voltage

0.5 VCC33 VCC33 +0.5

V

ih

il

Input Low Voltage

-0.5

0.3VCC33

V

Input Pull-up Voltage

Input Leakage Current

Output High Voltage

Output Low Voltage

Input Pin Capacitance

X_CLKIN Pin Capacitance

IDSEL Pin Capacitance

Pin Inductance

0.7VCC33

V

1

2

ipu

I

±10

µA

V

0 < V < VCC33

in

il

V

0.9VCC33

I

= -500 µA

= 1500 µA

oh

out

V

0.1VCC33

V

ol

C

10

8

pF

nH

3

in

C

5

clk

8

4

5

IDSEL

L

20

V ≤ 3.6 VCC33 off or

floating

o

I

X_PME# input leakage

-

1

µA

6

Off

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are

calculated to pull a floated network. Applications sensitive to static power utilization must assure that the

input buffer is conducting minimum current at this input voltage.

2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

3. Absolute maximum pin capacitance for a PCI/PCIX input except X_CLKIN and X_IDSEL.

4. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to

X_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before X_FRAME# asserts (see

Section 2.7.2.1, “Configuration Transaction Timing,” in the PCI-X Protocol Addendum to the PCI Local Bus

Specification Revision 2.0a).

5. For conventional PCI, this is a recommendation, not an absolute requirement. For PCI-X, this is a

requirement.

6. This input leakage is the maximum allowable leakage into the X_PME# open drain driver when power is

removed from VCC33 of the component. This assumes that no event has occurred to cause the device to

attempt to assert X_PME#.

24

Datasheet — 41210 Bridge

3.1.6.5

Input Clock DC Specifications

Table 18.

DC Specification for Input Clock Signals

Symbol

CLK100

Parameter

Input Low Voltage

Min

Max

Units

-0.5

2.0

0.8

V

CLK100

CLK133

Input High Voltage

Input Low Voltage

Input High Voltage

VCC3.3 + 0.5

0.8

-0.5

2.0

VCC3.3 + 0.5

3.1.6.6

Output Clock DC Specifications

Table 19.

DC Specification for Output Clock Signals

Symbol

CLK33

Parameter

Output Low Voltage

Min

Max

0.4

Units

Condition

V

Iol = 1 mA

Ioh= -1 mA

CLK33

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

2.4

CLK66

0.4

Iol = 1 mA

Ioh= -1 mA

Iol = 1 mA

Ioh= -1 mA

Iol = 1 mA

Ioh= -1 mA

CLK66

2.4

CLK100

CLK133

3.2

AC Specifications

3.2.1

PCI and PCI-X AC Characteristics

Table 20.

Conventional PCI 3.3V AC Characteristics (Sheet 1 of 2)

Sym

Parameter

Condition

Min

Max

Unit

mA

Note

V

= 0.7VCC33

= 0.3VCC33

= 0.18VCC33

-32VCC33

out

Switching Current

High

I

oh(AC)

-12VCC33

mA

1

38VCC33

Switching Current

Low

ol(AC)

1

V

= 0.6VCC33

16VCC33

mA

out

25 + (V

–

in

VCC33 + 4 > V

VCC33 + 1

in

I

High Clamp Current

VCC33 – 1) /

0.015

ch

25

41210 Bridge — Datasheet

Table 20.

Conventional PCI 3.3V AC Characteristics (Sheet 2 of 2)

I

Low Clamp Current

-3 < V -1

-25 + (V + 1) /

mA

cl

in

0.015

1

slew

Output Rise Slew

Rate

0.3VCC33 to

0.6VCC33

4

V/ns

2

r

f

2

Output Fall Slew

Rate

0.6VCC33 to

0.3VCC33

1

1. In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half

of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to

CLK and RSTIN# which are system outputs. “Switching Current High” specifications are not relevant to

X_SERR# which is an open drain output.

2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the

instantaneous rate at any point within the transition range. For more details on slew rate measurement

conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,

Revision 2.0a

Table 21.

PCI-X 3.3V AC Characteristics

Sym

Parameter

Condition

Min

Max

Unit

mA

Note

0 < VCC33 –

-74(VCC33 -

V

3.6V

V

)

out

0 < VCC33 –

1.2V

-32 (VCC33 –

mA

1

V

)

out

I

Switching Current High

oh(AC)

1.2V < VCC33 – -11 (VCC33 -

1.9V ) – 25.2

V

out

1.9V < VCC33 – -1.8 (VCC33 -

mA

V

3.6V

V

) – 42.7

out

0 V

3.6V

100V

out

0 < V

1.3V

48V

1

out

I

Switching Current Low

Low Clamp Current

High Clamp Current

ol(AC)

1.3V < V

3.6V

out

5.7V + 55

out

-3V < V ≤ -

0.8875V

-40 + (V + 1) /

0.005

in

mA

cl

-0.8875V < V

-0.625V

≤

-25 + (V + 1) /

0.015

in

40 + (V

VCC33 - 1) /

0.005

–

in

0.8875V < V

VCC33 ≤ -4V

–

in

mA

ch

0.625V < V

VCC33 ≤

0.8875V

–

25 + (V –

in

VCC33 - 1) /

0.015

in

0.3VCC33 to

0.6VCC33

slew

Output Rise Slew Rate

Output Fall Slew Rate

1

4

V/ns

2

r

f

0.6VCC33 to

0.3VCC33

1. In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half

of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to

CLK and RST# which are system outputs. “Switching Current High” specifications are not relevant to

X_SERR#, which is an open drain output.

26

Datasheet — 41210 Bridge

2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the

instantaneous rate at any point within the transition range. For more details on slew rate measurement

conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,

Revision 2.0a.

3.3

3.4

Voltage Filter Specifications

The 41210 Bridge requires voltage filtering to reduce noise on critical voltage planes. There are

two filter types necessary on the platform:

• Analog Voltage Filter (PCI-Express and PCI)

• Bandgap Filter

Note:

For filter specifications, refer to the 41210 Serial to Parallel PCI Bridge Design Guide.

VCC15 and VCC33 Voltage Requirements

The 41210 Bridge requires that the VCC33 voltage rail be equal to or no less than 0.5V below

VCC15 (absolute voltage value) at all times during 41210 Bridge operation, including during

system power up and power down. In other words, the following must always be true:

VCC33 ≥ (VCC15 –0.5V)

Figure 4 graphically illustrates this requirement. This can be accomplished by placing a diode (with

a voltage drop < 0.5V) between VCC15 and VCC33. Anode will be connected to VCC15 and

cathode will be connected to VCC33.

Figure 4.

Voltage Requirements VCC33 versus VCC15

27

41210 Bridge — Datasheet

3.5

Timing Specifications

3.5.1

PCI Express Interface Timing

3.5.1.1

Differential Transmitter (TX) AC Output Specifications

Table 22 defines the AC specifications of parameters for the differential output at all transmitters

(TXs). The parameters are specified at the component pins.

Table 22.

Differential Transmitter (TX) AC Output Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

Each UI is 400 ps +/-300 ppm. UI

does not account for SSC dictated

variations.

UI

Unit Interval

399.88 400

400.12 ps

See Note 1.

The maximum transmitter jitter

can be derived as T

Minimum TX Eye

Width

TX-MAX-JITTER

T

0.70

UI

TX-EYE

= 1 - T

= .3 UI

TX-EYE

See Notes 2 and 3.

Jitter is defined as the

measurement variation of the

Maximum time

between the jitter

median and

maximum deviation

for the median

TX-EYE-

crossing points (V

= 0V)

TX-DIFFp-p

0.15

UI

MEDIAN-to-

MAX-JITTER

in relation to an appropriate

average TX UI.

See Notes 2 and 3.

T

D+/D- TX Output

Rise/Fall Time

TX-RISE,

TX-FALL

0.125

50

UI

See Notes 2 and 4.

T

Minimum time spent

in Electrical Idle

Minimum time a transmitter must

be in electrical idle.

TX-IDLE-

MIN

Maximum time to

transition to a valid

Electrical Idle after

sending an Electrical

Idle ordered-set

After sending an electrical idle

ordered-set, the transmitter must

meet all electrical idle

T

TX-IDLE-

20

UI

SET-

TO-IDLE

specifications within this time.

Maximum time spent

in Electrical Idle

before initiating a

receiver detect

sequence.

T

TX-IDLE-

Maximum time spent in Electrical

Idle before initiating a receiver

detect sequence.

RCV-

100

500

ms

ps

DETECT-

MAX

Lane-to-Lane Output

Skew

Between any two Lanes within a

single Transmitter.

L

TX-SKEW

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,

“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also

refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage

Output Compliance Specification.)

3. A T

= 0.70 UI provides for a total sum of deterministic and random jitter budget of T

=

TX-EYE

TX-JITTER-MAX

0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The T

TX-EYE-MEDIAN-to-MAX-JITTER

specification ensures a jitter distribution in which the median and the maximum deviation from the median is

less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that

the median is not the same as the mean. The jitter median describes the point in time where the number of

jitter points on either side is approximately equal as opposed to the averaged time value.

28

Datasheet — 41210 Bridge

4. Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both V

TX-D+

and V

TX-D-.

3.5.1.2

Differential Receiver (RX) AC Input Specifications

Table 23 defines the AC specifications of parameters for all differential Receivers (RXs). The

parameters are specified at the component pins.

Table 23.

Differential Receiver (RX) AC Input Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

The UI is 400 ps +/-300 ppm. UI

does not account for SSC dictated

variations. See Note 1.

UI

Unit Interval

399.88 400

400.12 ps

The maximum interconnect media

and transmitter jitter that can be

tolerated by the receiver can be

Minimum

Receiver Eye

Width

T

0.4

UI

RX-EYE

derived asT

=1 -T

RX-MAX-JITTER

RX-

=0.6 UI

EYE

See Notes 2 and 3.

Jitter is defined as the

Maximum time

between the jitter

median and

maximum

deviation from

the median.

measurement variation of the

crossing points (V = 0 V)

T

RX-EYE-

RX- DIFFp-p

0.3

UI

MEDIAN-to-

in relation to an appropriate

average TX UI.

MAX-JITTER

See Notes 2 and 3.

Unexpected

Electrical Idle

Enter Detect

Threshold

An unexpected electrical idle (V

RX-

T

<V

) must

RX-IDLE-DET-

DIFFp-p

RX-IDLE-DET- DIFFp-p

10

20

ms

ns

be recognized no longer than T

DIFF-

RX-

to signal

ENTERTIME

IDLE-DET- DIFF-ENTERTIME

Integration Time

an unexpected idle condition.

Across all Lanes on a port. This

includes variation in the length of a

skip ordered-set (e.g., COM and 1

to 5 SKP symbols) at the RX as well

as any delay differences arising

from the interconnect itself.

L

Total Skew

RX-SKEW

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,

“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking

measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum

Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are

not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.

3. A T

= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the

RX-EYE

transmitter and interconnect collected any 250 consecutive UIs. The T

RX-EYE-MEDIAN-to-MAX-JITTER

specification ensures a jitter distribution in which the median and the maximum deviation from the median is

less than half of the total .6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that

the median is not the same as the mean. The jitter median describes the point in time where the number of

jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the

RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the

reference for the eye diagram.

29

41210 Bridge — Datasheet

3.5.2

PCI and PCI-X Interface Timing

Table 24.

PCI Interface Timing

Functional Operating Range (VCC33 = 3.3 V + 5%, Tcase=0°C to 105°C)

66 MHz 33 MHz

Min Max Min Max

Symbol

Parameter

Units

ns

Notes

CLK to Signal Valid Delay;

bused signals

T

2

6

2

11

12

1, 2, 3

val

CLK to Signal Valid Delay;

point-to-point signals

T

(ptp)

2

ns

1, 2, 3

T

Float to Active Delay

Active to Float Delay

ns

1, 7

on

T

14

28

off

Input Setup Time to CLK;

Bused signals

T

3

7

ns

3, 4, 8

su

Input Setup Time to CLK;

point-to-point

T

(ptp)

5

0

1

10,12

ns

ms

3, 4

4

su

T

Input Hold Time from CLK

0

1

h

Reset Active Time after power

stable

T

5

rst

Reset Active Time after CLK

stable

100

µs

5

rst-clk

T

Reset Active to output float delay

40

50

40

50

ns

5, 6

rst-off

rrsu

rrh

PxREQ64# to RSTIN# setup time 10

10

0

clocks

ns

RSTIN# to PxREQ64# hold Time

0

9

RSTIN# high to first configuration

access

T

2²⁵

clocks

rhfa

RSTIN# high to first PxFRAME#

Assertion

T

5

clocks

ms

rhff

Power Valid to RSTIN# High

100

pvrh

1. It is important that all driven signal transitions drive to their V or V level within one T .

cyc

oh

ol

2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X

Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and

load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a.

3. X_REQ_[5:0]# and X_GNT_[5:0]# are point-to-point signals and have different input setup times than do

bused signals. X_GNT_[5:0]# and X_REQ_[5:0]# have a setup of 5 ns at 66 MHz. All other signals are

bused.

4. See Section 3.5, “Timing Specifications” on page 28 and the measurement conditions in the PCI-X Electrical

and Mechanical Addendum, Revision 2.0a.

5. If X_M66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Specification

Revision 2.3. RSTIN# is asserted and deasserted asynchronously with respect to CLK.

6. When X_M66EN is asserted, the minimum specification for T (min), T (ptp)(min), and T may be reduced

val

on

to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when X_M66EN is deasserted.

7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total

current delivered through the component pin is less than or equal to the leakage current specification.

8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time. Refer to the PCI Local Bus Specification Revision 2.3 for more details.

9. Maximum value is also limited by delay to the first transaction (T ).

rhff

30

Datasheet — 41210 Bridge

Figure 5.

PCI Output Timing

Figure 6.

PCI Input Timing

Table 25.

PCI-X 3.3V Signal Timing Parameters (Sheet 1 of 2)

Sym

Parameter

PCI-X 133

Min Max

0.7 3.8

PCI-X 66

Min Max

0.7 3.8

Units

Notes

T

CLK to Signal Valid Delay

ns

1, 2, 8

val

31

41210 Bridge — Datasheet

Table 25.

PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)

T

Float to Active Delay

Active to Float Delay

Input Setup Time to CLK

0

ns

1, 6, 8

3, 7

on

T

7

off

T

1.2

1.7

su

T

Input Hold Time from CLK

0.5

1

0.5

1

ns

3

4

h

Reset Active Time after power

stable

ms

rst

T

Reset Active Time after CLK stable 100

Reset Active to output float delay

100

µs

ns

4

rst-clk

rst-off

rrsu

40

50

40

50

PxREQ64# to RSTIN# setup time

RSTIN# to PxREQ64# hold Time

10

0

10

0

7

rrh

RSTIN# high to first configuration

access

T

2²⁶

clocks

rhfa

RSTIN# high to first PxFRAME#

Assertion

T

5

clocks

ms

rhff

Power valid to RSTIN# high

100

10

100

10

pvrh

prsu

PCI-X initialization pattern to

RSTIN# setup time

clocks

RSTIN# to PCI-X initialization

pattern hold time

T

0

50

0

50

ns

7

prh

rlcx

Delay from RSTIN# low to CLK

frequency change

1. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28.

2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X

Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and

load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.

3. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28 and the PCI-X

Electrical and Mechanical Addendum, Revision 2.0a.

4. RST# is asserted and deasserted asynchronously with respect to CLK.

5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total

current delivered through the component pin is less than or equal to the leakage current specification

6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time.

7. Maximum value is also limited by delay to the first transaction (T ). The PCI-X initialization pattern control

rhfa

signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first

PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.

8. Device must meet this specification independent of how many outputs switch simultaneously.

32

Datasheet — 41210 Bridge

3.5.3

PCI and PCI-X Clock Specification

Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a

3.3V signaling environment except for voltage levels specified in Table 26, “PCI and PCI-X Clock

Timings” on page 33. The same spread-spectrum clocking techniques are allowed in PCI-X as for

66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of

spread-spectrum clocking specified in Table 26.

Figure 7. PCI-X 3.3V Clock Waveform

Table 26.

PCI and PCI-X Clock Timings

PCI-X 133

PCI-X 66

Min Max

PCI 66

PCI 33

Symbol Parameter

Min

Max

Min

Max

Min

Max

Units

Notes

Average

7.5

20

15

20

15

30

ns

1,3,4

∞

^Tcyc

CLK Cycle

Absolute

Minimum

7.375

3

14.8

29.7

ns

ps

1,3

Time

T

CLK high

time

6

11

high

T

CLK low

time

3

low

T

CLKPeriod

Jitter

125

-125

4

200

-200

200

-200

4

300

-300

4

5

2

jit

Slew Rate

1.5

—

CLK slew

rate

1.5

4

1.5

1

V/ns

Spread Spectrum Requirements

fmod

Modulation

frequency

30

33

30

33

30

33

0

kHz

%

fsprea

d

Frequency

spread

-1

0

-1

0

-1

1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and

jitter limits except while RSTIN# is asserted.

2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the

PCI-X Electrical and Mechanical Addendum, Revision 2.0a.

3. The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter).

4. Average T is measured over any 1 µs period of time and must include all sources of clock variation.

cyc

33

41210 Bridge — Datasheet

5. Period jitter is the deviation between any single period of the clock, T , and the average period of the clock,

cyc

T

.

cyc(average)

34

Datasheet — 41210 Bridge

3.5.4

41210 Bridge Clock Timings

Table 27.

41210 Bridge Clock Timings

Symbol

CLK100

Parameter

Min

Max

Units

Notes

T

Average Period

Rise time across 600 mV

Fall time across 600 mV

Rise/Fall Matching

10.0

300

10.2

600

20%

0.76

200

55

ns

ps

6

period

T

7,8

7,9

rise

T

fall

—

Cross point at 1 V

0.51

45

V

ps

%

V

T

Cycle to Cycle jitter

ccjitter

—

Duty Cycle

—

Maximum voltage allowed at input

Minimum voltage allowed at input

Rising edge ringback

Falling edge ring back

1.45

-200

mV

V

0.85

0.35

V

CLK133

T

Average Period

7.5

300

7.65

600

ns

ps

6

period

T

Rise time across 600 mV

Fall time across 600 mV

7,8

7,9

rise

T

fall

—

Rise/Fall Matching

Cross point at 1V

Cycle to Cycle jitter

20%

0.76

125

—

0.51

45

V

T

ps

10

ccjitter

—

Duty Cycle

55

%

V

—

Maximum voltage allowed at input

Minimum voltage allowed at input

Rising edge ringback

1.45

-200

—

mV

V

—

0.85

—

Falling edge ring back

0.35

V

CLK33

T

CLK period

30.0

12.0

N/A

ns

1,2

3

period

T

CLK high time

CLK low time

high

T

4

low

—

Rising edge rate

Falling edge rate

CLK rise time

1.0

0.5

4.0

2.0

V/ns

ns

5

—

T

rise

T

CLK fall time

0.5

2.0

ns

5

fall

1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.

35

41210 Bridge — Datasheet

2. The average period over any 1 us period of time must be greater than the minimum specified period.

3. T is measured at 2.4V for non-host outputs.

high

4. T is measured at 0.4V for all outputs.

low

5. For 3.3V clocks T

and T are measured as a transition through the threshold region V = 0.4V and V

=

rise

fall

ol

oh

2.4V (1 mA) JEDEC Specification.

6. Measured at crossing point.

7. Measured from V = 0.2V to V = 0.8V.

ol

oh

8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].

9. Determined as a fraction of 2*(T – T ) / (T + T ).

rise

fall

rise

fall

10.Period jitter is the deviation between any single period of the clock, T , and the average period of the clock,

cyc

T

(average).

cyc

3.5.4.1

Spread Spectrum Clocking

Spread spectrum clocking can be used on the 41210 Bridge to reduce energy. Spread Spectrum

clocking is a common technique used by system designers to meet FCC emissions, where the

frequency is deliberately shifted around to spread the energy off of the peak. The following is to be

observed when using Spread Spectrum clocking:

• All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST

meet the existing non-spread spectrum specifications

• All non-spread Host and PCI functionality must be maintained in the spread spectrum mode

(includes all power management functions.)

• The minimum clock period cannot be violated. The preferred method is to adjust the spread

technique to not allow for modulation above the nominal frequency. This technique is often

called “down-spreading”. The modulation profile in a modulation period can be expressed as:

Equations:

1



(1 − δ ) f_nom+ 2 f_m

δ

f_nom

t

when 0 < t <

;



2 f_m

f =







1

(1 + δ ) f_nom− 2 f_m

δ

t

when

< t <

,

2 f_m

f_m

where:

_nomis the nominal frequency in the non-SSC mode

f

f_mis the modulation frequency

f_mis the modulation amount

t is time.

3.6

41210 Bridge Power Consumption

Table 28 provides details on the maximum draw from the power planes by the 41210 Bridge for

use in voltage regulation.

36

Datasheet — 41210 Bridge

Table 28.

41210 Bridge Maximum Voltage Plane Currents

Power Plane

Frequency (MHz)

Number of Slots

Maximum Voltage Plane Current (Amps)

133

1

100

2

66

4

I

_VCC15(core 1.5V)

1.68

0.22

0.005

0.70

1.05

1.61

0.22

0.005

0.70

1.14

1.55

0.22

0.005

0.70

1.22

I

_VCC15(I/O 1.5V)

VCCBGPE

I

_VCCPE(PCI Express 1.5V)

I

(PCI/PCI-X Mode 1 3.3V) ¹

VCC33

1.

Per PCI-X Bus segment

Table 29 provides details on the maximum nominal draw from the power planes by the 41210

Bridge for use in thermal design.

Table 29.

41210 Bridge Thermal Voltage Plane Currents

Power Plane

Frequency (MHz)

Number of Slots

Thermal Voltage Plane Current (Amps)

133

1

100

2

66

4

I

_VCC15(core 1.5V)

I_VCC15(I/O 1.5V)

VCCBGPE

1.24

1.18

1.11

0.22

0.005

I

_VCCPE(PCI Express 1.5V)

0.69

0.99

0.69

1.04

0.69

1.10

I

(PCI/PCI-X Mode 1 3.3V) ¹

VCC33

1.

Per PCI-X Bus segment

3.7

3.8

Power Delivery Guidelines

Please refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide.

Reference and Compensation Pins

The 41210 Bridge has one reference pin and three compensation pins:

• PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI

Express interface on the 41210 Bridge. The nominal compensation voltage is 0.5V. An

external 24.9 ±1% pull-up resistor should be used to connect to VCC15. A single pull-up

resistor can be used to for both of these signals.

37

41210 Bridge — Datasheet

• RCOMP is an analog PCI interface compensation pin to the 41210 Bridge. A 100 ±1% pull-

down resistor should be used to connect the RCOMP pin to ground.

All three of these implementations are shown in Figure 8.

Figure 8.

41210 Bridge Reference and Compensation Circuit Implementations

3.9

Thermal Specifications

3.9.1

Power

For TDP specifications, see 41210 Bridge Thermal Specifications for the 41210 Bridge

component. FC-BGA packages have poor heat transfer capability into the board and have minimal

thermal capability without thermal solutions. Intel recommends that system designers plan for a

heatsink when using the 41210 Bridge component.

3.9.2

Die Temperature

To ensure proper operation and reliability of the 41210 Bridge component, the die temperatures

must be at or below the values specified in Table 30. System and/or component level thermal

solutions are required to maintain die temperatures below the maximum temperature

specifications.

38

Datasheet — 41210 Bridge

Table 30.

41210 Bridge Thermal Specifications

Parameter

Maxinum

T

105×C

8.70W

8.30W

8.10W

case

TDP

Mode#1/Mode#1

Mode#1/No Connect

TDP

DDR/No Connect

Note:

Mode 1: PCI-X 66MHz, 64-bit, 4 slots/devices

No Connect: Unused PCI segment (no slots/devices on PCI bus segment)

3.9.3

Thermal Solution Component Suppliers

3.9.3.1

Torsional Clip Heatsink Thermal Solution

Supplier

(Part Number)

Part

Intel Part Number

Contact Information

Harry Lin (USA)

714-739-5797

hlinack@aol.com

Heatsink Assembly includes:

Unidirectional Fin Heatsink

Thermal Interface Material

Torsional Clip

C76435-001

CCI/ACK

Monica Chih (Taiwan)

866-2-29952666, x131

monica_chih@ccic.com.tw

Harry Lin (USA)

714-739-5797

hlinack@aol.com

Unidirectional Fin Heatsink

(31.0 x 31.0 x 12.2mm)

C76434-001

A69230-001

CCI/ACK

Monica Chih (Taiwan)

866-2-29952666, x131

monica_chih@ccic.com.tw

Todd Sousa (USA)

360-606-8171

tsousa@parker.com

Chomerics

Thermal Interface

(Chomerics T-710)

69-12-22066-T710

Harry Lin (USA)

714-739-5797

hlinack@aol.com

Heatsink Attach Clip

C17725-001

A13494-005

CCI/ACK

Monica Chih (Taiwan)

866-2-29952666, x131

monica_chih@ccic.com.tw

Julia Jiang (USA)

408-919-6178

juliaj@foxconn.com

Foxconn

(HB96030-DW)

Solder-Down Anchor

Note:

The enabled components may not be currently available from all suppliers. Contact the supplier

directly to verify time of component availability.

39

41210 Bridge — Datasheet

Package Specification and Ballout 4

4.1

Package Specification

The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball

pitch (see Figure 9 and Figure 10).

Figure 9.

41210 Bridge Package Dimensions (Top View)

Handling

Exclusion

Area

0.550 in.

Die Area

21.00 mm

17.00 mm

0.550 in.

31.00 mm

17.00 mm

21.00 mm

31.00 mm

Pkg_567-Ball_Top

40

Datasheet — 41210 Bridge

Figure 10.

41210 Bridge Package Dimensions (Side View)

Note:

Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.

All dimensions and tolerances conform to ANSI Y14.5M-1982

41

41210 Bridge — Datasheet

4.2

Ball Map

42

Datasheet — 41210 Bridge

43

41210 Bridge — Datasheet

4.3

Signal List, sorted by Ball Location

Table 31.

Signal List, sorted by Ball Name (Sheet 1 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

A1

A2

C1

C2

B_INTD#

VSS

E1

E2

B_NC4

VSS

B_STRAP5

RESERVED5

VSS

A3

C3

B_TEST1

NC4

E3

B_NC9

B_NC2

VSS

A4

C4

E4

A5

NC2

C5

VSS

E5

A6

TDO

C6

NC18

E6

B_STRAP4

TMS

A7

VCC33

VSS

C7

SMBCLK

VSS

E7

A8

C8

E8

VSS

A9

PETN[5]

PETP[5]

C9

PERN[5]

PERN[4]

PERP[4]

VCCPE

PERN[2]

VCCBGPE

VCCPE

REFCLKP

REFCLKN

A_STRAP0

A_STRAP3

VSS

E9

TDI

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

D1

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

F1

VSS

PETP[7]

PERN[6]

VSS

VSSBGPE

VCCPE

PERN[0]

PERP[0]

PE_RCOMP[0]

A_PCIXCAP

CFGRST#

NC6

PERN[1]

PERP[1]

VSS

SMBUS[3]

B_STRAP0

VSS

A_STRAP4

NC3

RESERVED1

VCC33

A_NC10

A_NC8

VSS

A_NC2

VSS

A_INTD#

B_TEST2

B_NC3

VCC33

B_INTA#

B_INTC#

B_NC10

RESERVED8

NC7

B_NC7

B2

B_NC1

D2

F2

B3

B_STRAP1

RESERVED6

B_STRAP6

NC19

D3

B_NC6

F3

B4

D4

RESERVED7

VCC33

F4

B5

D5

F5

B6

D6

NC5

F6

B7

TCK

D7

B_PCIXCAP

SMBDAT

PETN[6]

PETP[6]

VSS

F7

NC9

B8

CFGRETRY

PERP[5]

VSS

D8

F8

NC8

B9

D9

F9

TRST#

PERP[7]

PETN[7]

VCCPE

PETN[0]

PETP[0]

VSS

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

PETN[4]

PETP[4]

VSS

PERP[6]

PERP[2]

VSS

PETN[2]

PETP[2]

VSS

PETN[1]

PETP[1]

VSS

VSSAPE

PERST#

NC1

PE_RCOMP[1]

VCC33

A_STRAP1

A_STRAP5

SMBUS[5]

RESERVED3

A_NC6

B_STRAP2

SMBUS[2]

RESERVED2

A_STRAP2

A_TEST2

A_NC1

A_STRAP6

RESERVED4

A_NC9

A_TEST1

A_NC4

A_INTB#

A_INTC#

A_NC3

44

Datasheet — 41210 Bridge

Table 31.

Signal List, sorted by Ball Name (Sheet 2 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

G1

G2

B_INTB#

VSS

J1

J2

VSS

B_AD[45]

B_AD[46]

VSS

L1

L2

B_AD[41]

B_AD[42]

VCC15

B_REQ0#

B_AD[56]

VCC33

B_AD[57]

B_GNT5#

VSS

G3

B_NC5

B_NC8

VSS

J3

L3

G4

J4

L4

G5

J5

B_GNT0#

B_AD[60]

B_AD[61]

VCCAPCI1

VSS

L5

G6

B_CBE6#

B_CBE7#

VSS

J6

L6

G7

J7

L7

G8

J8

L8

G9

B_CBE4#

PERN[7]

VSS

J9

L9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

H1

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

K1

VCCPE

VSS

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

M1

VCC15

VSS

PERN[3]

PETP[3]

VSS

VCCPE

VSS

VCC15

VSS

VCCPE

VSS

VCC15

VSS

VCCAPE

SMBUS[1]

VSS

VCC15

A_AD[63]

A_CBE5#

VSS

VCC15

A_AD[59]

VSS

NC11

NC12

A_AD[58]

A_AD[43]

VSS

A_PAR64

A_AD[47]

VSS

A_NC5

A_NC7

VSS

A_REQ4#

A_AD[42]

VSS

A_AD[46]

A_GNT1#

B_GNT1#

VSS

A_INTA#

B_AD[48]

B_AD[49]

VCC33

B_AD[47]

B_AD[62]

VSS

H2

K2

M2

B_AD[39]

B_AD[40]

VSS

H3

K3

B_AD[43]

B_AD[44]

VSS

M3

H4

K4

M4

H5

K5

M5

B_AD[54]

B_AD[55]

VSS

H6

K6

B_AD[58]

B_AD[59]

VSS

M6

H7

B_PAR64

B_AD[63]

B_CBE5#

VSS

K7

M7

H8

K8

M8

NC14

H9

K9

VCC15

VSS

M9

VCC15

VSS

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

VCCPE

PERP[3]

PETN[3]

VSS

VCC15

VSS

VCC15

VSS

VCC15

VSS

VCC15

VSS

VCCPE

RSTIN#

A_CBE4#

VCC33

A_CBE6#

A_CBE7#

VCC33

A_AD[49]

A_AD[48]

VCC33

VCC15

VSS

VCC15

VSS

A_AD[61]

A_AD[60]

A_AD[62]

VSS

A_AD[57]

A_AD[56]

VCC33

NC15

NC13

A_AD[41]

VCC15

A_AD[40]

A_AD[45]

VSS

A_AD[44]

45

41210 Bridge — Datasheet

Table 31.

Signal List, sorted by Ball Name (Sheet 3 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

N1

N2

R1

R2

VSS

B_AD[32]

B_AD[33]

VSS

U1

U2

B_M66EN

B_PERR#

VSS

B_AD[37]

B_AD[38]

VSS

N3

R3

U3

N4

R4

U4

B_FRAME#

B_IRDY#

VSS

N5

R5

B_PME#

NC16

U5

N6

B_AD[52]

B_AD[53]

B_RST#

VSS

R6

U6

N7

R7

VCC33

VCCAPCI2

VSS

U7

B_CLKO[5]

B_CLKO[6]

VCC33

N8

R8

U8

N9

R9

U9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

P1

VCC15

VSS

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

T1

VCC15

VSS

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

V1

B_CLKIN

B_STRAP3

VSS

VCC15

VSS

VCC15

VSS

A_CLKIN

A_CLKO[4]

VSS

VCC15

VSS

VCC15

VSS

VCC15

A_AD[55]

A_REQ3#

A_AD[54]

VSS

VCC15

VCCAPCI3

A_AD[51]

VSS

A_CLKO[5]

A_CLKO[3]

VSS

A_STOP#

A_DEVSEL#

VSS

A_AD[50]

A_LOCK#

VSS

A_AD[39]

A_AD[38]

VSS

A_TRDY#

A_GNT5#

VSS

A_AD[35]

A_AD[34]

B_REQ3#

VSS

B_AD[34]

B_133EN

VSS

P2

T2

V2

B_SERR#

B_STOP#

VCC33

P3

T3

B_DEVSEL#

NC10

V3

P4

B_AD[35]

B_AD[36]

VSS

T4

V4

P5

T5

VCC33

B_REQ2#

B_CLKO[3]

VSS

V5

B_REQ4#

B_CLKO[4]

VSS

P6

T6

V6

P7

B_AD[50]

B_AD[51]

VCC15

VSS

T7

V7

P8

T8

V8

B_CLKO[2]

B_CLKO[1]

VSS

P9

T9

VCC15

VSS

V9

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

VCC15

VSS

VCC15

VSS

RCOMP

VCC15

VSS

VCC15

VSS

A_CLKO[0]

A_CLKO[6]

VCC15

VSS

VCC15

VSS

A_AD[53]

VSS

VCC33

A_M66EN

A_SERR#

VCC33

A_AD[33]

A_AD[32]

VCC33

NC17

A_CLKO[2]

A_REQ2#

VSS

A_AD[52]

A_PERR#

VSS

A_133EN

A_PME#

VSS

A_AD[37]

A_AD[36]

VSS

A_FRAME#

A_IRDY#

46

Datasheet — 41210 Bridge

Table 31.

Signal List, sorted by Ball Name (Sheet 4 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

W1

W2

B_AD[16]

VCC33

AA1

AA2

VCC33

B_AD[18]

B_AD[19]

VSS

AC1

AC2

B_REQ64#

B_AD[0]

VCC15

B_AD[4]

B_AD[5]

VCC33

B_AD[9]

B_CBE0#

VSS

W3

B_LOCK#

B_TRDY#

VSS

AA3

AC3

W4

AA4

AC4

W5

AA5

B_CBE3#

B_AD[24]

VSS

AC5

W6

B_AD[23]

B_AD[25]

VSS

AA6

AC6

W7

AA7

AC7

W8

AA8

B_AD[28]

B_AD[31]

VSS

AC8

W9

B_AD[29]

B_CLKO[0]

VCC33

AA9

AC9

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

Y1

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AB1

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AD1

B_AD[14]

B_PAR

VSS

B_GNT3#

B_REQ5#

VSS

B_GNT4#

A_REQ5#

VSS

A_AD[15]

A_CBE1#

VSS

A_GNT4#

A_AD[31]

VSS

A_AD[30]

A_CLKO[1]

VSS

A_AD[11]

A_AD[9]

VSS

A_RST#

A_AD[26]

VSS

A_AD[25]

A_GNT0#

VSS

A_AD[7]

A_AD[5]

VSS

A_CBE3#

A_AD[21]

VSS

A_REQ0#

A_REQ1#

VSS

A_AD[2]

A_AD[0]

A_REQ64#

VSS

A_AD[18]

A_CBE2#

B_ACK64#

VSS

A_AD[16]

B_CBE2#

B_AD[17]

VSS

Y2

AB2

AD2

B_AD[1]

B_AD[2]

VSS

Y3

AB3

B_AD[20]

B_AD[3]

VSS

AD3

Y4

B_AD[21]

B_AD[22]

VCC15

AB4

AD4

Y5

AB5

AD5

B_AD[6]

B_AD[7]

VSS

Y6

AB6

B_REQ1#

B_AD[8]

VCC33

AD6

Y7

B_AD[26]

B_AD[27]

VCC33

AB7

AD7

Y8

AB8

AD8

B_AD[10]

B_AD[12]

VSS

Y9

AB9

B_AD[11]

B_AD[13]

VSS

AD9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

B_AD[30]

B_GNT2#

VSS

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

B_AD[15]

B_CBE1#

A_PAR

A_GNT3#

A_GNT2#

VCC33

A_AD[14]

A_AD[13]

VSS

A_AD[12]

A_AD[29]

VSS

A_AD[28]

A_AD[27]

VSS

A_AD[10]

A_CBE0#

VCC33

A_AD[6]

A_AD[4]

VSS

A_AD[8]

A_AD[24]

VCC15

A_AD[23]

A_AD[22]

VCC33

A_AD[3]

A_AD[20]

VSS

A_AD[19]

A_AD[17]

VCC33

A_AD[1]

VSS

A_ACK64#

47

41210 Bridge — Datasheet

4.4

Signal List, sorted by Signal Name

Table 32. Signal List, sorted by Signal Name (Sheet 1 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

V20

AB24

AC23

AD23

AC22

AB21

AD21

AC20

AD20

AC19

AB18

AC17

AD17

AC16

AB15

AD15

AD14

AC13

W24

Y23

A_133EN

A_ACK64#

A_AD[0]

J23

J21

A_AD[46]

A_AD[47]

A_AD[48]

A_AD[49]

A_AD[50]

A_AD[51]

A_AD[52]

A_AD[53]

A_AD[54]

A_AD[55]

A_AD[56]

A_AD[57]

A_AD[58]

A_AD[59]

A_AD[60]

A_AD[61]

A_AD[62]

A_AD[63]

A_CBE0#

A_CBE1#

A_CBE2#

A_CBE3#

A_CBE4#

A_CBE5#

A_CBE6#

A_CBE7#

A_CLKIN

A_CLKO[0]

A_CLKO[1]

A_CLKO[2]

A_CLKO[3]

A_CLKO[4]

A_CLKO[5]

A_CLKO[6]

A_DEVSEL#

A_FRAME#

A_GNT0#

A_GNT1#

A_GNT2#

A_GNT3#

A_GNT4#

A_GNT5#

A_IRDY#

A_INTA#

A23

D24

F23

G21

D22

G22

E22

F21

E21

R21

T18

AB13

J20

A_NC2

A_NC3

H23

H22

R20

R18

P19

P17

N19

N17

M18

M17

L19

A_NC4

A_AD[1]

A_NC5

A_AD[2]

A_NC6

A_AD[3]

A_NC7

A_AD[4]

A_NC8

A_AD[5]

A_NC9

A_AD[6]

A_NC10

A_AD[7]

A_LOCK#

A_M66EN

A_PAR

A_AD[8]

A_AD[9]

A_AD[10]

A_AD[11]

A_AD[12]

A_AD[13]

A_AD[14]

A_AD[15]

A_AD[16]

A_AD[17]

A_AD[18]

A_AD[19]

A_AD[20]

A_AD[21]

A_AD[22]

A_AD[23]

A_AD[24]

A_AD[25]

A_AD[26]

A_AD[27]

A_AD[28]

A_AD[29]

A_AD[30]

A_AD[31]

A_AD[32]

A_AD[33]

A_AD[34]

A_AD[35]

A_AD[36]

A_AD[37]

A_AD[38]

A_AD[39]

A_AD[40]

A_AD[41]

A_AD[42]

A_AD[43]

A_AD[44]

A_AD[45]

A_PAR64

A_PCIXCAP

A_PERR#

A_PME#

A_REQ0#

A_REQ1#

A_REQ2#

A_REQ3#

A_REQ4#

A_REQ5#

A_REQ64#

A_RST#

L17

E17

P20

V21

W21

W22

V18

N18

L22

K18

K17

K19

J17

AD18

AC14

AA24

AA20

H17

J18

AA23

Y22

W13

AC24

AA17

T19

U19

C18

D18

B22

C19

A21

D19

F19

F22

B23

U22

P2

AB22

AA21

Y20

H19

H20

U13

V14

W16

V17

U17

U14

U16

V15

U20

V23

W19

J24

A_SERR#

A_STOP#

A_STRAP0

A_STRAP1

A_STRAP2

A_STRAP3

A_STRAP4

A_STRAP5

A_STRAP6

A_TEST1

A_TEST2

A_TRDY#

B_133EN

B_ACK64#

B_AD[0]

Y19

AB19

W18

AA18

Y17

Y16

AB16

W15

AA15

T22

T21

R24

R23

AB1

AC2

AD2

AD3

AB4

AC4

AC5

AD5

AD6

AB7

AC7

P23

Y14

Y13

AA14

U23

V24

G24

F24

D23

C24

B24

P22

B_AD[1]

N22

B_AD[2]

N21

B_AD[3]

M23

B_AD[4]

M21

B_AD[5]

L23

A_INTB#

A_INTC#

A_INTD#

A_NC1

B_AD[6]

L20

B_AD[7]

K24

B_AD[8]

K22

B_AD[9]

48

Datasheet — 41210 Bridge

Table 32. Signal List, sorted by Signal Name (Sheet 2 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AD8

AB9

AD9

AB10

AC10

AD11

W1

Y2

B_AD[10]

B_AD[11]

B_AD[12]

B_AD[13]

B_AD[14]

B_AD[15]

B_AD[16]

B_AD[17]

B_AD[18]

B_AD[19]

B_AD[20]

B_AD[21]

B_AD[22]

B_AD[23]

B_AD[24]

B_AD[25]

B_AD[26]

B_AD[27]

B_AD[28]

B_AD[29]

B_AD[30]

B_AD[31]

B_AD[32]

B_AD[33]

B_AD[34]

B_AD[35]

B_AD[36]

B_AD[37]

B_AD[38]

B_AD[39]

B_AD[40]

B_AD[41]

B_AD[42]

B_AD[43]

B_AD[44]

B_AD[45]

B_AD[46]

B_AD[47]

B_AD[48]

B_AD[49]

B_AD[50]

B_AD[51]

B_AD[52]

B_AD[53]

B_AD[54]

B_AD[55]

B_AD[56]

B_AD[57]

K6

K7

B_AD[58]

B_AD[59]

B_AD[60]

B_AD[61]

B_AD[62]

B_AD[63]

B_CBE0#

B_CBE1#

B_CBE2#

B_CBE3#

B_CBE4#

B_CBE5#

B_CBE6#

B_CBE7#

B_CLKIN

B_CLKO[0]

B_CLKO[1]

B_CLKO[2]

B_CLKO[3]

B_CLKO[4]

B_CLKO[5]

B_CLKO[6]

B_DEVSEL#

B_FRAME#

B_GNT0#

B_GNT1#

B_GNT2#

B_GNT3#

B_GNT4#

B_GNT5#

B_IRDY#

B_INTA#

B_INTB#

B_INTC#

B_INTD#

B_NC1

H7

D7

B_PAR64

B_PCIXCAP

B_PERR#

B_PME#

B_REQ0#

B_REQ1#

B_REQ2#

B_REQ3#

B_REQ4#

B_REQ5#

B_REQ64#

B_RST#

B_SERR#

B_STOP#

B_STRAP0

B_STRAP1

B_STRAP2

B_STRAP3

B_STRAP4

B_STRAP5

B_STRAP6

B_TEST1

B_TEST2

B_TRDY#

CFGRETRY

CFGRST#

NC1

J6

U2

J7

R5

H5

L4

H8

AB6

T6

AC8

AB12

Y1

T1

AA2

AA3

AB3

Y4

V5

AA5

G9

H9

AA12

AC1

N8

Y5

G6

G7

U10

W10

V9

V2

W6

AA6

W7

Y7

V3

A19

B3

B19

U11

E6

Y8

V8

AA8

W9

Y10

AA9

R2

T7

V6

A2

U7

B5

U8

C3

T3

D1

R3

U4

W4

B8

P1

J5

P4

K1

E18

F18

A5

P5

Y11

AA11

W12

L8

N3

NC2

N4

A22

C4

NC3

M2

M3

L1

NC4

U5

D6

NC5

F2

E19

F6

NC6

L2

G1

F3

NC7

K3

F8

NC8

K4

C1

F7

NC9

J2

B2

T4

NC10

J3

E4

B_NC2

G18

G19

K21

M8

M20

R6

NC11

H4

D2

B_NC3

NC12

H1

E1

B_NC4

NC13

H2

G3

D3

B_NC5

NC14

P7

B_NC6

NC15

P8

B1

B_NC7

NC16

N6

G4

E3

B_NC8

T24

C6

NC17

N7

B_NC9

NC18

M5

M6

L5

F4

B_NC10

B6

NC19

W3

U1

B_LOCK#

B_M66EN

B_PAR

E16

B17

E14

PE_RCOMP[0]

PE_RCOMP[1]

PERN[0]

L7

AC11

49

41210 Bridge — Datasheet

Table 32. Signal List, sorted by Signal Name (Sheet 3 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

A15

C13

G12

C10

C9

PERN[1]

PERN[2]

PERN[3]

PERN[4]

PERN[5]

PERN[6]

PERN[7]

PERP[0]

A18

D20

B7

SMBUS[3]

SMBUS[5]

TCK

F1

H3

VCC33

VCCAPCI1

VCCAPCI2

VCCAPCI3

VCCAPE

VCCBGPE

VCCPE

VSS

H18

H21

H24

L6

E9

TDI

A6

TDO

E12

G10

E15

A16

D13

H12

C11

B9

E7

TMS

F9

TRST#

VCC15

VCC33

M19

R7

J16

K9

PERP[1]

T5

PERP[2]

K11

K13

K15

L3

T17

T20

T23

U9

PERP[3]

PERP[4]

PERP[5]

D12

F10

F17

F13

D15

B14

H13

B11

A9

PERP[6]

L10

L12

L14

L16

M9

V4

PERP[7]

W2

PERST#

W11

Y9

PETN[0]

PETN[1]

Y15

Y21

Y24

AA1

AB8

AB14

AC6

AD19

J8

PETN[2]

M11

M13

M15

M22

N10

N12

N14

N16

P9

PETN[3]

PETN[4]

PETN[5]

D9

PETN[6]

F11

F14

D16

B15

G13

B12

A10

D10

E11

V11

C17

C16

C21

B21

D21

F20

A3

PETN[7]

PETP[0]

PETP[1]

PETP[2]

R8

PETP[3]

P11

P13

P15

R10

R12

R14

R16

T9

R17

G15

C14

A14

C12

C15

F12

H11

H15

J10

J12

J14

A4

PETP[4]

PETP[5]

PETP[6]

PETP[7]

RCOMP

REFCLKN

REFCLKP

RESERVED1

RESERVED2

RESERVED3

RESERVED4

RESERVED5

RESERVED6

RESERVED7

RESERVED8

RSTIN#

T11

T13

T15

V12

V16

Y6

B4

A8

VSS

D4

AB20

AC3

A7

A17

A20

A24

B10

B13

B16

C2

VSS

F5

VSS

H16

C7

VSS

SMBCLK

SMBDAT

SMBUS[1]

SMBUS[2]

B18

C22

D5

VSS

D8

VSS

G16

B20

VSS

E24

VSS

50

Datasheet — 41210 Bridge

Table 32. Signal List, sorted by Signal Name (Sheet 4 of 4)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

C5

C8

VSS

L21

L24

M4

VSS

V10

V13

VSS

VSSAPE

VSSBGPE

C20

C23

D11

D14

D17

E2

V19

M7

V22

M10

M12

M14

M16

N2

W5

W8

W14

W17

W20

W23

Y3

E5

E8

N5

E10

E13

E20

E23

F15

G2

N9

N11

N13

N15

N20

N23

P3

Y12

Y18

AA4

AA7

AA10

AA13

AA16

AA19

AA22

AB2

AB5

AB11

AB17

AB23

AC9

AC12

AC15

AC18

AC21

AD1

AD4

AD7

AD10

AD16

AD22

AD24

F16

G5

G8

P6

G11

G14

G17

G20

G23

H6

P10

P12

P14

P16

P18

P21

P24

R1

H10

H14

J1

R4

J4

R9

J9

R11

R13

R15

R19

R22

T2

J11

J13

J15

J19

J22

K2

T8

K5

T10

T12

T14

T16

U3

K8

K10

K12

K14

K16

K20

K23

L9

A13

A1

U6

A11

U12

U15

U18

U21

U24

V1

A12

M1

M24

N1

L11

L13

L15

L18

N24

AD12

AD13

V7

51

41210 Bridge — Datasheet

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§ §

52


型号：	QG41210
厂家：	INTEL
描述：	Micro Peripheral IC, CBGA567
文件：	总52页 (文件大小：328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

QG41210 [INTEL]

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