QG80332M800_技术文档

Intel® 80332 I/O Processor

Datasheet

Product Features

■ Integrated Intel XScale^®core

—500, 667 and 800 MHz

■ Memory Controller

—PC2700 Double Data Rate (DDR333)

SDRAM

—DDRII 400 SDRAM

—Up to 2 GB of 64-bit DDR333

—Up to 1 GB of 64-bit DDRII400

—Optional Single-bit Error Correction,

Multi-bit Detection Support (ECC)

—ARM* V5TE Compliant

—32 KByte, 32-way Set Associative

Instruction Cache with cache locking

—32 KByte, 32-way Set Associative Data

Cache with cache locking. Supports

write through or write back

—Supports Unbuffered or Registered

DIMMs and Discrete SDRAM

—32-bit memory support

—2 KByte, 2-way Set Associative

Mini-Data Cache

—128-Entry Branch Target Buffer

—8-Entry Write Buffer

■ DMA Controller

—Two Independent Channels Connected

to Internal Bus

—Two 1KB Queues in Ch0 and Ch1

—CRC-32C Calculation

—4-Entry Fill and Pend Buffer

—Performance Monitor Unit

—Internal Bus 266 MHz/64-bit

■ PCI Express-to-PCI Bridges

—x8 PCI Express Upstream Link

■ Application Accelerator Unit

—Performs optional XOR on Read Data

—PCI Express Specification 1.0a

compliant

—Compute Parity Across Local Memory

Blocks

—PCI-X Bus A (IOP bus - ATU interface)

—1 KB/512-byte Store Queue

—PCI-X Bus B (Slot Expansion bus)

■ Two UART (16550) Units

supports standard PCI Hot-Plug Controller

—64-byte Receive and Transmit FIFOs

—Four output clocks per PCI-X bus

■ Address Translation Unit

—4-pin, Master/Slave Capable

■ Peripheral Bus Interface

—8-/16-bit Data Bus with Two Chip Selects

—2 KB or 4 KB Outbound Read Queue

—4 KB Outbound Write Queue

■ Interrupt Controller Unit

—Four Priority Levels

—Vector Generation

—4 KB Inbound Read and Write Queue

—Connects Internal Bus to PCI/X Bus A

—Messaging Unit and Expansion ROM

—Sixteen External Interrupt Pins with

High Priority Interrupt (HPI#)

■ Two Programmable 32-bit Timers and

■ 829-Ball, Flip Chip Ball Grid Array (FCBGA)

Watchdog Timer

—37.5 mm²and 1.27 mm ball pitch

■ Eight General Purpose I/O Pins

■ Two I²C Bus Interface Units

Warning: Intel Corporation products are not intended for use in life support appliances,

devices or systems. Use of a Intel products in such applications without written

consent is prohibited.

Document Number: 274066-004US

August 2005

Intel® 80332 I/O Processor Datasheet

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*Other names and brands may be claimed as the property of others.

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Intel® 80332 I/O Processor Datasheet

Contents

1.0

Introduction.........................................................................................................................7

1.1

About This Document............................................................................................7

1.1.1 Terminology..............................................................................................7

1.1.2 Other Relevant Documents......................................................................8

About the Intel^®80332 I/O Processor ...................................................................9

1.2

2.0

Features ...........................................................................................................................11

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Intel XScale^®Core ..............................................................................................11

PCI Express-to-PCI Bridge Units ........................................................................11

Address Translation Unit.....................................................................................12

Memory Controller...............................................................................................12

Application Accelerator Unit ................................................................................12

Peripheral Bus Interface......................................................................................12

DMA Controller....................................................................................................12

I²C Bus Interface Unit..........................................................................................13

Messaging Unit....................................................................................................13

Internal Bus .........................................................................................................13

UART Units .........................................................................................................13

Interrupt Controller Unit.......................................................................................13

GPIO ...................................................................................................................14

SMBus Unit .........................................................................................................14

2.9

2.10

2.11

2.12

2.13

2.14

3.0

4.0

Package Information ........................................................................................................15

3.1

3.2

Functional Signal Descriptions............................................................................15

Package Thermal Specifications.........................................................................56

Electrical Specifications....................................................................................................57

4.1

4.2

4.3

4.4

Absolute Maximum Ratings.................................................................................57

_CCPLLPin Requirements...................................................................................57

V

Targeted DC Specifications.................................................................................58

Targeted AC Specifications.................................................................................60

4.4.1 Clock Signal Timings..............................................................................60

4.4.2 DDR/DDR-II SDRAM Interface Signal Timings......................................62

4.4.3 Peripheral Bus Interface Signal Timings ................................................64

4.4.4 I²C/SMBus Interface Signal Timings ......................................................66

4.4.5 UART Interface Signal Timings..............................................................66

4.4.6 PCI Express Differential Transmitter (Tx) Output Specifications............67

4.4.7 PCI Express Differential Receiver (Rx) Input Specifications..................68

4.4.8 Boundary Scan Test Signal Timings ......................................................69

AC Timing Waveforms ........................................................................................70

AC Test Conditions .............................................................................................74

4.5

4.6

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Intel® 80332 I/O Processor Datasheet

Figures

1

Intel^®80332 I/O Processor Functional Block Diagram .......................................10

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

829-Ball FCBGA Package Diagram....................................................................36

Intel^®80332 I/O Processor Signal Group Locations (Bottom View) ...................37

Intel^®80332 I/O Processor Ballout - Left Side (Bottom View) ............................38

Intel^®80332 I/O Processor Ballout - Right Side (Bottom View) ..........................39

Clock Timing Measurement Waveforms .............................................................70

Output Timing Measurement Waveforms ...........................................................70

Input Timing Measurement Waveforms ..............................................................71

I²C/SMBus Interface Signal Timings...................................................................71

UART Transmitter Receiver Timing ....................................................................71

DDR SDRAM Write Timings ...............................................................................72

DDR SDRAM Read Timings ...............................................................................72

Write PreAmble/PostAmble Durations ................................................................73

AC Test Load for All Signals Except PCI and DDR SDRAM ..............................74

AC Test Load for DDR SDRAM Signals .............................................................74

PCI/PCI-X TOV(max) Rising Edge AC Test Load...............................................74

PCI/PCI-X TOV(max) Falling Edge AC Test Load..............................................75

PCI/PCI-X TOV(min) AC Test Load....................................................................75

Transmitter Test Load (100 ohm differential load) ..............................................75

Transmitter Eye Diagram ....................................................................................76

Receiver Eye Opening (Differential)....................................................................76

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Intel® 80332 I/O Processor Datasheet

Tables

1

2

4

3

5

6

7

8

Pin Description Nomenclature.............................................................................15

DDR SDRAM Signals..........................................................................................16

MISC SDRAM Signals.........................................................................................17

DDR-II SDRAM Signals.......................................................................................17

Peripheral Bus Interface Signals.........................................................................18

PCI Express Signals............................................................................................19

B PCI (Slot Expansion) Bus Signals....................................................................20

A PCI (IOP) Bus Signals .....................................................................................22

I²C/SMBus Signals..............................................................................................24

Interrupt Signals ..................................................................................................24

Hot-Plug Controller Signals for Parallel 1-slot, no-glue.......................................25

UART Signals......................................................................................................26

Test and Miscellaneous Signals..........................................................................28

Reset Strap Signals.............................................................................................29

Power and Ground Pins ......................................................................................31

Pin Mode Behavior..............................................................................................32

Pin Multiplexing for Functional Modes.................................................................35

FC-style, H-PBGA Package Dimensions ............................................................36

829-Lead Package - Alphabetical Ball Listings ...................................................40

829-Lead Package - Alphabetical Signal Listings ...............................................48

Absolute Maximum Ratings.................................................................................57

Operating Conditions...........................................................................................57

DC Characteristics ..............................................................................................58

10

9

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

I_CCCharacteristics ..............................................................................................59

PCI Clock Timings...............................................................................................60

DDR Clock Timings.............................................................................................60

PCI Express Clock Timings.................................................................................61

DDR SDRAM Signal Timings..............................................................................62

DDR-II SDRAM Signal Timings...........................................................................63

Peripheral Bus Signal Timings ............................................................................64

PCI Signal Timings..............................................................................................65

I²C/SMBus Signal Timings ..................................................................................66

UART Signal Timings..........................................................................................66

PCI Express Tx Output Specifications ................................................................67

PCI Express Rx Input Specifications...................................................................68

Boundary Scan Test Signal Timings ...................................................................69

AC Measurement Conditions ..............................................................................74

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Intel® 80332 I/O Processor Datasheet

Revision History

Date

Revision #

Description

August 2005

March 2005

004

003

Updated voltages in Section 4.3.

Revised:

Table 14, modified pin mode behavior for DQ[63:32] for 32-bit DDR.

Table 21, modified Case Temperature Under Bias to 95^oC Max

Table 22, modified Case Temperature Under Bias to 95^oC Max

Table 23, modified Vol1 and Voh1 parameters

Table 25, added note 4.

Table 26, added note 2.

Table 28, modified Tvb4 and Tva4.

Figure 12, removed Tvb6 parameter.

Added ICC data to Table 24.

October 2004

August 2004

002

001

Removed text errors in Figure 1.

Initial Release.

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Intel® 80332 I/O Processor Datasheet

Introduction

1.0

Introduction

1.1

About This Document

This is the Intel^®80332 I/O Processor Datasheet. This document contains a functional overview,

package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed

functional descriptions other than parametric performance are published in the Intel^®80332 I/O

Processor Developer’s Manual.

Intel Corporation assumes no responsibility for any errors which may appear in this document nor

does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice. In

particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment

to implement them. In fact, this specification does not imply a commitment by Intel to design,

manufacture, or sell the product described herein.

1.1.1

Terminology

To aid the discussion of the Intel^®80332 I/O processor (80332) architecture, the following

terminology is used:

Core processor

Local processor

Host processor

Local bus

Intel XScale^®core within the 80332

Processor located upstream from the 80332

80332 Internal Bus

Local memory

Memory subsystem on the Intel XScale^®core DDR SDRAM or Peripheral Bus

Interface busses.

Inbound

At or toward the Internal Bus of the 80332 from the PCI interface of the ATU.

At or toward the PCI interface of the 80332 ATU from the Internal Bus.

Outbound

Downstream

At or toward a PCI Express port directed away from the root complex (to a bus

with a higher number).

Upstream

At or toward a PCI Express port directed to the PCI Express root complex (to

a bus with a lower number).

QWORD

DWORD

word

64-bit data quantity (8 bytes).

32-bit data quantity (4 bytes).

16-bit data quantity (2 bytes).

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Intel® 80332 I/O Processor Datasheet

Introduction

1.1.2

Other Relevant Documents

1. Intel XScale^®Core Developer’s Manual (273473), Intel Corporation.

2. PCI Hot-Plug Specification, Revision 1.1 - PCI Special Interest Group.

3. PCI Express Specification, Revision 1.0a - PCI Special Interest Group.

4. Intel^®80332 I/O Processor Developer’s Manual (274065), Intel Corporation.

5. Intel^®80332 I/O Processor Design Guide (273824), Intel Corporation

6. Intel^®80332 I/O Processor Specification Update (273927), Intel Corporation

7. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group.

8. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a - PCI Special Interest

Group.

9. PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest

Group.

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Intel® 80332 I/O Processor Datasheet

Introduction

1.2

About the Intel^®80332 I/O Processor

The 80332 is a multi-function device that integrates the Intel XScale^®core (ARM* architecture

compliant) with intelligent peripherals and PCI Express-to-PCI Bridges. The 80332 consolidates,

into a single system:

• Intel XScale^®core.

• x8 PCI Express Upstream Link.

• Two PCI Express-to-PCI Bridges supporting PCI-X interface on both segments.

• PCI Standard Hot-Plug Controller (segment B).

• Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to

the segment A.

• High-Performance Memory Controller.

• Interrupt Controller with up to 16 external interrupt inputs.

• Two Direct Memory Access (DMA) Controllers.

• Application Accelerator.

• Messaging Unit.

• Peripheral Bus Interface Unit.

• Two I²C Bus Interface Units.

• Two 16550 compatible UARTs with flow control (four pins).

• Eight General Purpose Input Output (GPIO) ports.

It is an integrated processor that addresses the needs of intelligent I/O applications and helps

reduce intelligent I/O system costs.

PCI Express is an industry standard, high performance, low latency system interconnect. The

80332s PCI Express upstream link is capable of x8 lane widths at 2.5 GHz operation as defined by

the PCI Express Specification, Revision 1.0a. The addition of the Intel XScale^®core brings

intelligence to the PCI Express-to-PCI Bridges.

The 80332 integrates PCI Express-to-PCI Bridges with the ATU as an integrated secondary PCI

device. The Upstream PCI Express port implements the PCI-to-PCI Bridge programming model

according to the PCI Express Specification, Revision 1.0a. The Primary Address Translation Unit

is compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a

definitions of an ‘application bridge’.

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Intel® 80332 I/O Processor Datasheet

Introduction

Figure 1 is a functional block diagram of the 80332.

Intel^®80332 I/O Processor Functional Block Diagram

Figure 1.

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Intel® 80332 I/O Processor Datasheet

Features

2.0

Features

The 80332 combines the Intel XScale^®core with powerful new features to create an intelligent I/O

processor. This multi-device I/O Processor is fully compliant with the PCI Local Bus Specification,

Revision 2.3 and the PCI Express Specification, Revision 1.0a. The 80332-specific features

include:

• Intel XScale^®core

• Interrupt Controller Unit

• Messaging Unit

• Internal Bus

• Application Accelerator Unit

• Address Translation Unit

• Memory Controller

• Two DMA Controllers

• Two UART Units

• Eight GPIOs

• Peripheral Bus Interface

• Two I2C Bus Interface Units

• PCI Express 2.5 GHz x8 link

• Two PCI Express-to-PCI Bridges to

secondary PCI-X 133 MHz Bus interfaces

The subsections that follow briefly overview each feature. Refer to the Intel^®80332 I/O Processor

Developer’s Manual for full technical descriptions.

2.1

2.2

Intel XScale^®Core

The 80332 is based upon the Intel XScale^®core. The core processor operates at a maximum

frequency of 800 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative.

Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative, and

a mini data cache that is 2 Kbytes and is two-way set associative.

PCI Express-to-PCI Bridge Units

The 80332 provides PCI Express-to-PCI Bridge units. These bridge units share a common

upstream PCI Express interface compliant to the PCI Express Specification, Revision 1.0a. The

PCI Express interface supports a port lane width of eight, for up to 2 Gbytes/s per direction (4

Gbytes/s total) at 2.5 Gbits/s bit rate. The PCI-X secondary interfaces support 64-bit 133 MHz

compliant to the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. These two

secondary PCI bus interfaces are referred to as the ‘A’ and ‘B’ segment, where the 80332 Address

Translation Unit resides on ‘A’ segment. The ‘B’ PCI bus interface may be used for slot expansion.

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Intel® 80332 I/O Processor Datasheet

Features

2.3

2.4

2.5

Address Translation Unit

An Address Translation Unit (ATU) allows PCI transactions direct access to the 80332 local

memory. The ATU supports transactions between PCI address space and 80332 address space.

Address translation for the ATU is controlled through programmable registers accessible from both

the PCI interface and the Intel XScale^®core. The PCI interface of the ATU is connected to the

80332 “A” Secondary PCI interface of the bridge. Upstream access to the PCI Express interface is

controlled by inverse decode with the address windows of the bridge. Dual access to registers

allows flexibility in mapping the two address spaces. The ATU also supports the power

management extended capability configuration header that as defined by the PCI Bus Power

Management Interface Specification, Revision 1.1.

Memory Controller

The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features

programmable chip selects and support for error correction codes (ECC). The memory controller

may be configured for DDR SDRAM at 333 MHz (with 500 MHz and 667 MHz processors) or

DDR-II SDRAM at 400 MHz (with 500 MHz and 800 MHz processors). The memory controller

interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete

DDR SDRAM devices.

External memory may be configured as host addressable memory or private 80332 memory

utilizing the Address Translation Unit and Bridges.

Application Accelerator Unit

The Application Accelerator Unit (AA) provides low-latency, high-throughput data transfer

capability between the AA unit, the 80332 local memory and the PCI bus. It executes data transfers

from and to the 80332 local memory, from the PCI bus to the 80332 local memory, or from the

80332 local memory to the PCI bus. The AA unit performs XOR operations, computes parity,

generates and verifies an eight byte data integrity field, performs memory block fills, and provides

the necessary programming interface.

2.6

2.7

Peripheral Bus Interface

The Peripheral Bus Interface Unit is a data communication path to the flash memory components

or other peripherals of an 80332 hardware system. The PBI includes support for either 8/16 bit

devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability

which allows successive 8/16-bit data transfers.

DMA Controller

The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents

and the local memory. Two separate DMA channels accommodate data transfers to the PCI bus.

Both channels include a local memory to local memory transfer mode. The DMA Controller

supports chaining and unaligned data transfers. It is programmable through the Intel XScale^®core

only.

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Features

2.8

I²C Bus Interface Unit

The I²C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel XScale^®core to serve as a

master and slave device residing on the I²C bus. The I²C unit uses a serial bus developed by Philips

Semiconductor*, consisting of a two-pin interface. The bus allows the 80332 to interface to other

I²C peripherals and microcontrollers for system management functions. It requires a minimum of

hardware components for an economical system to relay status and reliability information on the

I/O subsystem to an external device. Also refer to I²C Peripherals for Microcontrollers (Philips

Semiconductor).

The 80332 includes two I²C bus interface units.

2.9

Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 80332. It uses

interrupts to notify each system when new data arrives. The MU has four messaging mechanisms:

• Message Registers

• Doorbell Registers

• Circular Queues

• Index Registers

Each messaging mechanism allows a host processor or external PCI device and the 80332 to

communicate through message passing and interrupt generation.

2.10

2.11

Internal Bus

The Internal Bus is a high-speed interconnect between internal units and Intel XScale^®core

processor. The Internal Bus operates at 266 MHz and is 64 bits wide.

UART Units

The 80332 includes two UART unit. The UART units allow the Intel XScale^®core to serve as a

master and slave device residing on the UART bus. The UART units use a serial bus consisting of a

four-pin interface. The bus allows the 80332 to interface to other peripherals and microcontrollers.

Also refer to 16550 Device Specification (National Semiconductor*).

2.12

Interrupt Controller Unit

The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the

80332 to the Intel XScale^®core processor. The ICU supports high performance interrupt

processing with direct interrupt service routine vector generation on a per source basis. Each source

has programmability for masking, core processor interrupt input, and priority.

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Intel® 80332 I/O Processor Datasheet

Features

2.13

2.14

GPIO

The 80332 includes eight General Purpose I/O (GPIO) pins which can also be used as external

interrupt inputs.

SMBus Unit

The SMBus (System Management Bus) Interface Unit allows the 80332 to serve as a slave device

on the SMBus. SMBus is based on the principles of the I²C bus and allows the 80332 to interface to

system SMBus for external access and control of internal registers.

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Package Information

3.0

Package Information

The 80332 is offered in a Flip Chip Ball Grid Array (FCBGA) package. This is a full grid array

package with 829 ball connections.

3.1

Functional Signal Descriptions

Table 1.

Pin Description Nomenclature

Symbol

Description

C

I

Configuration

Input pin only

O

Output pin only

I/O

Pin may be either an input or output.

Open Drain pin

OD

PWR

GND

-

Power pin

Ground pin

Pin must be connected as described.

Sync(...)

Synchronous. Signal meets timings relative to a clock.

Sync(B) Synchronous to B_CLKIN

Sync(M) Synchronous to M_CK[2:0]

Sync(A) Synchronous to A_CLKIN

Sync(T) Synchronous to TCK

Async

Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals

are level-sensitive.

Rst(R)

Rst(A)

The pin is reset with PWRGD or RSTIN#.

The pin is reset with A_RST#. Note that A_RST# is asserted when RSTIN# or PWRGD is

asserted.

Rst(B)

Rst(M)

Rst(T)

The pin is reset with B_RST#. Note that B_RST# is asserted when RSTIN# or PWRGD is

asserted.

The pin is reset with M_RST#. Note that M_RST# is asserted when RSTIN# or PWRGD is

asserted or is asserted with software.

The pin is reset with TRST#.

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 2.

DDR SDRAM Signals

Name

Count

Type

Description

M_CK[2:0]

3

O

Memory Clocks are used to provide the positive differential

clocks to the external SDRAM memory subsystem.

M_CK[2:0]#

M_RST#

3

1

O

Memory Clocks are used to provide the negative differential

clocks to the external SDRAM memory subsystem.

O

Async

Memory Reset indicates when the memory subsystem has

been reset with RSTIN# or PWRGD or a software reset.

MA[13:0]

14

O

Memory Address Bus carries the multiplexed row and

column addresses to the SDRAM memory banks.

Sync(M), Rst(M)

BA[1:0]

2

O

SDRAM Bank Address indicates which of the SDRAM

internal banks are read or written during the current

transaction.

Sync(M), Rst(M)

RAS#

CAS#

1

O

SDRAM Row Address Strobe indicates the presence of a

valid row address on the Multiplexed Address Bus MA[12:0].

Sync(M), Rst(M)

O

SDRAM Column Address Strobe indicates the presence of a

valid column address on the Multiplexed Address Bus

MA[12:0].

Sync(M), Rst(M)

WE#

1

2

O

SDRAM Write Enable indicates that the current memory

transaction is a write operation.

Sync(M), Rst(M)

CS[1:0]#

CKE[1:0]

O

SDRAM Chip Select enables the SDRAM devices for a

memory access (Physical banks 0 and 1).

Sync(M), Rst(M)

O

SDRAM Clock Enable enables the clocks for the SDRAM

memory. Deasserting will place the SDRAM in self-refresh

mode.

Sync(M), Rst(M)

DQ[63:0]

64

I/O

SDRAM Data Bus carries 64-bit data to and from memory.

During a data cycle, read or write data is present on one or

more contiguous bytes. During write operations, unused pins

are driven to determinate values.

Sync(M), Rst(M)

CB[7:0]

8

9

I/O

SDRAM ECC Check Bits carry the 8-bit ECC code to and

from memory during data cycles.

Sync(M), Rst(M)

DQS[8:0]

I/O

SDRAM Data Strobes carry the strobe signals, output in write

mode and input in read mode for source synchronous data

transfer.

Sync(M), Rst(M)

DM[8:0]

Total

9

O

SDRAM Data Mask controls which bytes on the data bus

should be written. When DM[8:0] is asserted, the SDRAM

devices do not accept valid data from the byte lanes.

Sync(M), Rst(M)

120

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 3.

DDR-II SDRAM Signals

Name

Count

Type

Description

DQS[8:0]#

9

I/O

SDRAM Data Strobes carry the differential strobe signals in

DDR-II mode, output in write mode and input in read mode for

source synchronous data transfer.

Sync(M)

Rst(M)

ODT[1:0]

2

O

On Die Termination Control, turns on SDRAM termination

during writes.

Sync(M)

Rst(M)

DDRRES[2:1]

Total

2

I/O

Compensation For DDR OCD (analog) DDR-II mode only.

13

Table 4.

MISC SDRAM Signals

Name

Count

Type

Description

DDRCRES0

1

O

Analog VSS Ref Pin (analog) both DDRSLWCRES and

DDRIMPCRES signals connect to this pin through a reference

resistor.

DDRSLWCRES

DDRIMPCRES

Total

1

3

I/O

Compensation Voltage Reference (analog) for DDR driver slew

rate control connected through a resistor to DDRCRES0.

Compensation Voltage Reference (analog) for DDR driver

impedance control connected through a resistor to DDRCRES0.

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17

Intel® 80332 I/O Processor Datasheet

Package Information

Table 5.

Peripheral Bus Interface Signals

Name

Count

Type

O

Description

A[22:16]

7

Address Bus 22:16 carries a demultiplexed version of address bits

A22:16. During address (T ), wait state (T ) and data cycles (T )

cycles, A22:16 represents the upper seven address bits for the

a

w

d

Rst(M)

current access. A22:16 allows the PBI interface to address up to

8 Mbytes per peripheral device.

See “Table 17 “Pin Multiplexing for Functional Modes” on page 37”

for strap inputs which are muxed onto A[19:16], and “Table 14

“Reset Strap Signals” on page 31” for a functional description.

AD[15:0]

16

I/O

Address/Data Bus carries 16-bit physical addresses and 8-, or

16-bit data to and from memory. During an address (T ) cycle, bits

2-31 contain a physical word address (bits 0-1 indicate SIZE; see

a

Rst(M)

below). During a data (T ) cycle, bits 0-7, or 0-15 contain read or

d

write data, depending on the corresponding bus width.

During write operations to 8-bit wide memory regions, the PBI

drives unused bus pins high or low.

SIZE, which comprises bits 0-1 of the AD lines during a T cycle,

a

specifies the number of data transfers during the bus transaction.

AD1 AD0

0

1

0

1

0

1

1 Transfer

2 Transfers

3 Transfers

4 Transfers

See “Table 17 “Pin Multiplexing for Functional Modes” on page 37”

for strap inputs which are muxed onto AD[15:0], and “Table 14

“Reset Strap Signals” on page 31” for a functional description.

A[2:0]

3

O

Address Bus 2:0 carries a demultiplexed version of bits 2:0 of the

AD[15:0] bus. During an address (T ) cycle, bits A[2:0] matches

a

Rst(M)

AD[2:0]. During a bursted read data (T ) cycle, A[2:0] will

d

represent the current byte address in the bursted transaction.

A[2:1] are used for an 16-bit wide peripheral while A[1:0] are used

for an 8-bit wide peripheral.

See “Table 17 “Pin Multiplexing for Functional Modes” on page 37”

for strap inputs which are muxed onto A[2:0], and “Table 14 “Reset

Strap Signals” on page 31” for a functional description.

ALE

1

O

Address Latch Enable indicates the transfer of a physical address.

The pin is asserted during the first address cycle and deasserted

during the second address cycle.

Rst(M)

POE#

O

Peripheral Output Enable Indicates whether the bus access is a

write or a read with respect to the I/O processor and is valid during

the entire bus access. This pin may be used to control the OE#

input on peripheral devices.

Rst(M)

0 = Read

1 = Write

PWE#

1

O

Peripheral Write Enable indicates whether the bus access is a

write or a read with respect to the I/O processor and is valid during

the entire bus access. This pin is use for flash memory accesses

and controls the WE# input on the ROM.

Rst(M)

0 = Write

1 = Read

PCE[1]#

PCE[0]#

Total

1

O

Peripheral Chip Enables specify which of the two memory address

ranges are associated with current bus access. The pin remains valid

during the entire bus access.

Rst(M)

O

Peripheral Chip Enables specify which of the two memory address

ranges are associated with current bus access. The pin remains valid

during the entire bus access.

Rst(M)

31

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 6.

PCI Express Signals

Name

Count

Type

Description

REFCLK+/

REFCLK-

2

I

PCI Express Differential Clock In: These pins receive a 100

MHz differential clock input from an external source. This clock is

used as the reference clock for the PCI Express circuitry.

PE0Tp[7:0]/

PE0Tn[7:0]

16

O

PCI Express Serial Data Transmit: These eight differential

output pairs carry data and embedded clock for the PCI Express

port 0 interface.

•

x8 Mode: All PE0Tp[7:0] and PE0Tn[7:0] signals are used.

x4 Mode: Only PE0Tp[3:0] and PE0Tn[3:0] signals are used.

PE0Rp[7:0]/

PE0Rn[7:0]

16

I

PCI Express Serial Data Receive: These eight differential input

pairs receive data and embedded clock for port 0.

•

x8 Mode: All PE0Rp[7:0] and PE0Rn[7:0] signals are used.

x4 Mode: Only PE0Rp[3:0] and PE0Rn[3:0] signals are

used.

PE_RCOMPO

PE_ICOMPI

Total

1

I

PCI EXPRESS RCOMP: Connected to external reference

resistor. Output current path, used to compensate PCI Express

driver and RX termination.

PCI EXPRESS RCOMP IN: Connected to the same external

resistor as PE_RCOMPO on the board, for input voltage sensing

comparator.

36

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 7.

B PCI (Slot Expansion) Bus Signals (Sheet 1 of 2)

Name

Count

Type

Description

B_AD[31:0]

32

I/O

B PCI Address/Data is the multiplexed PCI address and lower

32 bits of the data bus.

Sync(B)

Rst(B)

B_AD[63:32]

32

I/O

B PCI Address/Data is the upper 32 bits of the PCI data bus

driven during the data phase.

Sync(B)

Rst(B)

B_PAR

B_PAR64

1

8

I/O

B PCI Bus Parity is even parity across B_AD[31:0] and

Sync(B) B_C/BE[3:0]#.

Rst(B)

I/O

B PCI Bus Upper DWORD Parity is even parity across

Sync(B) B_AD[63:32] and B_C/BE[7:4]#.

Rst(B)

B_C/BE[7:0]#

I/O

B PCI Bus Command and Byte Enables are multiplexed on the

Sync(B) same PCI pins. During the address phase, they define the bus

Rst(B)

O

command. During the data phase, they are used as byte enables

for B_AD[63:0].

B_GNT[4]#

B_GNT[3]#

B_GNT[2]#

B_GNT[1]#

B_GNT[0]#

B_REQ64#

1

B Secondary PCI Bus Grant signals sent to device 4 on the

Sync(B) B-segment PCI bus.

Rst(B)

O

B Secondary PCI Bus Grant signals sent to device 3 on the

Sync(B) B-segment PCI bus.

Rst(B)

O

B Secondary PCI Bus Grant signal sent to device 2 on the

Sync(B) B-segment PCI bus.

Rst(B)

O

B Secondary PCI Bus Grant signal sent to device 1 on the

Sync(B) B-segment PCI bus.

Rst(B)

O

B PCI Bus Grant is the grant signal sent to device 0 on the

Sync(B) B-segment PCI bus.

Rst(B)

I/O

B PCI Bus Request 64-Bit Transfer indicates the attempt of a

Sync(B) 64-bit transaction on the PCI bus. When the target is 64-bit

Rst(B)

capable, the target acknowledges the attempt with the assertion of

B_ACK64#.

B_REQ[4]#

B_REQ[3]#

1

I

B PCI Bus Requests is the request signal for device 4 on the

Sync(B) B-segment PCI bus.

I

B PCI Bus Requests is the request signal for device 3 on the

Sync(B) B-segment PCI bus.

B_REQ[2]#/

B_HM66EN

I

B PCI Bus Requests is the request signal for device 2 on the

Sync(B) B-segment PCI bus.

PCI 66 Enable is used to determine when the slot is PCI 66 MHz

capable. This signal is only valid for Hot-Plug 1-slot mode.

B_REQ[1]#

B_REQ[0]#

B_ACK64#

1

I

B PCI Bus Requests is the request signal for device 1 on the

Sync(B) B-segment PCI bus.

I

B PCI Bus Requests are the request signals from device 0 on the

Sync(B) B segment secondary PCI bus.

I/O

B PCI Bus Acknowledge 64-Bit Transfer indicates that the

Sync(B) device has positively decoded its address as the target of the

Rst(B)

current access and the target is willing to transfer data using the

full 64-bit data bus.

B_FRAME#

1

I/O

B PCI Bus Cycle Frame is asserted to indicate the beginning and

Sync(B) duration of an access.

Rst(B)

20

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Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 7.

B PCI (Slot Expansion) Bus Signals (Sheet 2 of 2)

Name

Count

Type

Description

B_IRDY#

1

I/O

B PCI Bus Initiator Ready indicates the initiating agent’s ability to

Sync(B) complete the current data phase of the transaction. During a write,

Rst(B)

it indicates that valid data is present on the Address/Data bus.

During a read, it indicates the processor is ready to accept the

data.

B_TRDY#

B_STOP#

1

I/O

B PCI Bus Target Ready indicates the target agent’s ability to

Sync(B) complete the current data phase of the transaction. During a read,

Rst(B)

it indicates that valid data is present on the Address/Data bus.

During a write, it indicates the target is ready to accept the data.

I/O

B PCI Bus Stop indicates a request to stop the current transaction

Sync(B) on the PCI bus.

Rst(B)

B_DEVSEL#

B_LOCK#

B_SERR#

1

I/O

B PCI Bus Device Select is driven by a target agent that has

Sync(B) successfully decoded the address. As an input, it indicates

Rst(B)

whether or not an agent has been selected.

I/O

B PCI Bus Lock indicates whether or not a transaction is

Sync(B) establishing a LOCK across the bridge.

Rst(B)

I/O

B PCI Bus System Error is driven for address parity errors on the

PCI bus.

OD

Sync(B)

Rst(B)

B_PERR#

B_M66EN

B_PME#

1

I/O

B PCI Bus Parity Error is asserted when a data parity error

Sync(B) occurs during a PCI bus transaction.

Rst(B)

I/O

B PCI Bus 66 MHz Enable indicates the speed of the PCI bus.

When this signal is sampled high the PCI bus speed is 66 MHz,

when low, the bus speed is 33 MHz.

I

Power Management Event signal is used to request a change in

the device or system power state.

Sync(B)

I

B_PCIXCAP

B_CLKO[4:0]

B_CLKOUT

B_CLKIN

1

5

1

B PCI-X Capability Analog pad that selects PCI/X mode and

frequency capabilities. Non-standard, special purpose analog pin.

O

I

B PCI Bus Output Clocks are used to drive external logic on the

secondary PCI bus.

B PCI Bus Output Clock is used to drive B_CLKIN when

secondary bus clocks are enabled.

B PCI Bus Input Clock provides the timing for all PCI

transactions. Typically connected on the board to B_CLKOUT.

Provides timing clock for all B segment PCI interfaces.

B_RST#

1

O

B PCI BUS RESET is an output based on RSTIN# or PWRGD. It

brings PCI-specific registers, sequencers, and signals to a

consistent state. When RSTIN# is asserted or PWRGD is

deasserted, or the secondary bridge reset bit is asserted, it causes

B_RST# to assert and:

• PCI output signals are driven to a known consistent state.

• PCI bus interface output signals are three-stated.

• open drain signals such as B_SERR# are floated

B_RST# may be asynchronous to B_CLKIN when asserted or

deasserted. Although asynchronous, deassertion must be

guaranteed to be a clean, bounce-free edge.

B_RCOMP

Total

1

I/O

PCI Resistor Compensation Pin is an analog pad that connects

to a board resistor to control all B segment PCI output driver

strengths (analog).

106

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Intel® 80332 I/O Processor Datasheet

Package Information

22

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 8.

A PCI (IOP) Bus Signals (Sheet 1 of 2)

Name

Count

Type

Description

A_AD[31:0]

32

I/O

A PCI Address/Data is the multiplexed PCI address and lower 32

bits of the data bus.

Sync(A)

Rst(A)

A_AD[63:32]

A_PAR

32

1

I/O

Sync(A)

Rst(A)

A PCI Address/Data is the upper 32 bits of the PCI data bus.

I/O

A PCI Bus Parity is even parity across A_AD[31:0] and

A_C/BE[3:0]#.

Sync(A)

Rst(A)

A_PAR64

1

4

I/O

Sync(A)

Rst(A)

A PCI Bus Upper DWORD Parity is even parity across

A_AD[63:32] and A_C/BE[7:4]#.

A_C/BE[3:0]#

I/O

Sync(A)

Rst(A)

A PCI Bus Command and Byte Enables are multiplexed on the

same PCI pins. During the address phase, they define the bus

command. During the data phase, they are used as the byte

enables for A_AD[31:0].

A_C/BE[7:4]#

A_REQ64#

4

1

I/O

Sync(A)

Rst(A)

A PCI Byte Enables are used as byte enables for A_AD[63:32]

during secondary PCI data phases.

I/O

Sync(A)

Rst(A)

A PCI Bus Request 64-Bit Transfer indicates the attempt of a

64-bit transaction on the secondary PCI bus. When the target is

64-bit capable, the target acknowledges the attempt with the

assertion of A_ACK64#.

A_ACK64#

1

I/O

Sync(A)

Rst(A)

A PCI Bus Acknowledge 64-Bit Transfer indicates that the

device has positively decoded its address as the target of the

current access, indicates the target is willing to transfer data using

64 bits.

A_FRAME#

A_IRDY#

1

I/O

Sync(A)

Rst(A)

A PCI Bus Cycle Frame is asserted to indicate the beginning and

duration of an access.

I/O

Sync(A)

Rst(A)

A PCI Bus Initiator Ready indicates the initiating agent’s ability

to complete the current data phase of the transaction. During a

write, it indicates that valid data is present on the secondary

Address/Data bus. During a read, it indicates the processor is

ready to accept the data.

A_TRDY#

A_STOP#

1

I/O

Sync(A)

Rst(A)

A PCI Bus Target Ready indicates the target agent’s ability to

complete the current data phase of the transaction. During a read,

it indicates that valid data is present on the secondary

Address/Data bus. During a write, it indicates the target is ready

to accept the data.

I/O

A PCI Bus Stop indicates a request to stop the current

Sync(A)

transaction on the secondary PCI bus.

Rst(A)

A_DEVSEL#

A_SERR#

1

I/O

Sync(A)

Rst(A)

A PCI Bus Device Select is driven by a target agent that has

successfully decoded the address. As an input, it indicates

whether or not an agent has been selected.

I/O

A PCI Bus System Error is driven for address parity errors on

the secondary PCI bus.

OD

Sync(A)

Rst(A)

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23

Intel® 80332 I/O Processor Datasheet

Package Information

Table 8.

A PCI (IOP) Bus Signals (Sheet 2 of 2)

Name

Count

Type

Description

A_RST#

1

O

Async

A PCI Bus Reset is an output based on RSTIN# or PWRGD. It

brings PCI-specific registers, sequencers, and signals to a

consistent state. When RSTIN# is asserted or PWRGD is

deasserted, or the secondary bridge reset bit is asserted, it

causes A_RST# to assert and:

•

PCI output signals are driven to a known consistent state.

PCI bus interface output signals are three-stated.

Open drain signals such as A_SERR#are floated.

A_RST# may be asynchronous to A_CLKIN when asserted or

deasserted. Although asynchronous, deassertion must be

ensured to be a clean, bounce-free edge.

A_PERR#

A_LOCK#

1

I/O

Sync(A)

Rst(A)

A PCI Bus Parity Error is asserted when a data parity error

during a secondary PCI bus transaction.

I/O

A PCI Bus Lock indicates the need to perform an atomic

Sync(A)

Rst(A)

operation on the secondary PCI bus.

A_CLKO[3:0]

A_CLKOUT

A_CLKIN

4

1

O

I

A PCI Bus Output Clocks are used to drive external logic on the

secondary PCI bus.

A PCI Bus Output Clock is used to drive A_CLKIN when the IO

processor provides secondary bus clocks.

A PCI Bus Input Clock provides the timing for all PCI

transactions. Typically connected on the board to A_CLKOUT.

Provides the timing clock for all A segment PCI interfaces.

A_M66EN

1

I/O

A PCI Bus 66 MHz Enable indicates the speed of the secondary

PCI bus. When this signal is high, the bus speed is 66 MHz and

when it is low, the bus speed is 33 MHz.

A_PME#

1

4

I

Power Management Event signal is used to request a change in

the device or system power state.

Sync(A)

A_REQ[3:0]#

A_GNT[3:0]#

I

A PCI Bus Requests are the request signals from devices 3

through 0 on the A PCI bus.

Sync(A)

O

A PCI Bus Grant are grant signals sent to devices 3 through 0 on

the A PCI bus.

Sync(A)

Rst(A)

A_PCIXCAP

A_RCOMP

1

I

A PCI-X Capability is an analog pad that selects PCI/X mode and

frequency capabilities. Non-standard, special purpose analog pin.

I/O

PCI Resistor Compensation Pin is an analog pad that connects

to the board resistor to control all A segment PCI output driver

strengths (analog).

Total

103

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 9.

Interrupt Signals

Name

Count

Type

Description

XINT[7:0]#

8

I

Interrupt Inputs: XINT[7:0]# interrupts are directed to the input of

Async the IOAPIC, or the Interrupt Controller inputs. When directed to the

Interrupt Controller inputs, then the inputs can be steered to either

the FIQ or IRQ internal interrupt input of the core.

By default, XINT[7:4]# interrupts are directed to the input of the B

IOAPIC and XINT[3:0]# interrupts are directed to the input of the A

IOAPIC.

These interrupt pins are level sensitive.

HPI#

Total

1

9

I

High Priority Interrupt causes a high priority interrupt to the I/O

Async processor. This pin is level-detect only and is internally

synchronized.

Table 10.

I²C/SMBus Signals

Name

SCL0

Count

Type

I/O

Description

1

I²C Clock provides synchronous operation of the I²C bus zero.

I²C Data is used for data transfer and arbitration of the I²C bus zero.

SCD0

I/O

SCL1/SCLK

I/O

I²C Clock provides synchronous operation of the I²C bus zero.

SM Bus Clock provides synchronous operation of the SM bus.

SCD1/SDTA

Total

1

4

I/O

I²C Data is used for data transfer and arbitration of the I²C bus zero.

SM Bus Data is used for data transfer and arbitration of the SM bus.

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25

Intel® 80332 I/O Processor Datasheet

Package Information

Table 11.

Hot-Plug Controller Signals for Parallel 1-slot, no-glue

Name

Count

Type

Description

B_HPWRFLT#

1

I

Parallel Mode Hot-Plug Power Controller Fault indication for

over-current/under-volt status. When asserted, the device (when

enabled) may assert a slot reset and disconnects the slot from the

bus.

Sync(B)

Rst(B)

B_HMRL#

1

I

Parallel Mode Hot-Plug Status of the slot 1 MRL sensor switch,

when asserted it indicates the MRL latch is closed. When a platform

does not support MRL sensors, this must be wired to a logic low

level.

Sync(B)

Rst(B)

B_HPRSNT2#

B_HPWREN

1

I

Parallel Mode Hot-Plug PRSNT2 signal is used to indicate whether

a card is installed in the slot and its power requirements. These

signals are directly connected to the present bits on the PCI card.

Sync(B)

O

Parallel Mode Hot-Plug Power Enable signal connected to

on-board slot specific power controller to regulate current and

voltage of the slot.

Sync(B)

Rst(B)

B_HPRSNT1#

B_HATNLED#

B_HPWRLED#

B_HBUTTON#

1

I

Parallel Mode Hot-Plug PRSNT1 signal is used to indicate whether

a card is installed in the slot and its power requirements. These

signals are directly connected to the present bits on the PCI card.

Sync(B)

Rst(B)

O

Parallel Mode Hot-Plug Attention indicator LED signal that is

yellow or amber in color.

Sync(B)

Rst(B)

O

Parallel Mode Hot-Plug Power Indicator LED signal that is green

in color.

Sync(B)

Rst(B)

I

Parallel Mode Hot-Plug Attention Button input from the slot. When

low, this indicates that the operator has requested attention. When

an attention button is not implemented, this input must be wired to a

logic high level.

Sync(B)

Rst(B)

B_HRESET#

Total

1

9

O

Parallel Mode Reset Output Signal. This signal was added in C-0

stepping. Signal was previously ‘N/C1’. This output signal is always

‘on’, therefore, it does not tri-state during boundary scan.

26

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 12.

UART Signals (Sheet 1 of 2)

Name

Count

Type

Description

GPIO[0]/

U0_RXD

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Serial Input: Serial data input from device pin to receive shift register.

GPIO[1]/

U0_TXD

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Serial Output: Composite serial data output to the communications

link-peripheral, modem, or data set. The TXD signal is set to the

MARKING (logic 1) state upon a Reset operation.

GPIO[2]/

U0_CTS#

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Clear To Send: When low, this pin indicates that the receiving UART is

ready to receive data. When the receiving UART deasserts CTS# high,

the transmitting UART should stop transmission to prevent overflow of

the receiving UARTs buffer. The CTS# signal is a modem-status input

whose condition may be tested by the host processor or by the UART

when in Autoflow mode as described below:

Non-Autoflow Mode:

When not in Autoflow mode, bit 4 (CTS) of the Modem Status

register (MSR) indicates the state of CTS#. Bit 4 is the complement

of the CTS# signal. Bit 0 (DCTS) of the Modem Status register

indicates whether the CTS# input has changed state since the

previous reading of the Modem Status register. CTS# has no effect

on the transmitter. The user may program the UART to interrupt the

processor when DCTS changes state. The programmer may then

stall the outgoing data stream by starving the transmit FIFO or

disabling the UART with the IER register.

NOTE: When UART transmission is stalled by disabling the UART,

the user may not receive an MSR interrupt when CTS#

reasserts. This occurs because disabling the UART also

disables interrupts. As a workaround, the user may use Auto

CTS in Autoflow Mode, or program the CTS# pin to interrupt.

Autoflow Mode:

NOTE: In Autoflow mode, the UART Transmit circuitry will check

the state of CTS# before transmitting each byte. When

CTS# is high, no data is transmitted.

GPIO[3]/

U0_RTS#

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Request To Send: When low, this informs the remote device that

the UART is ready to receive data. A reset operation sets this signal

to its Inactive (high) state. LOOP mode operation holds this signal in

its Inactive state.

Non-Autoflow Mode:

The RTS# output signal may be asserted by setting bit 1 (RTS) of

the Modem Control register to a 1. The RTS bit is the complement of

the RTS# signal.

Autoflow Mode:

RTS# is automatically asserted by the autoflow circuitry when the

Receive buffer exceeds its programmed threshold. It is deasserted

when enough bytes are removed from the buffer to lower the data

level back to the threshold.

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27

Intel® 80332 I/O Processor Datasheet

Package Information

Table 12.

UART Signals (Sheet 2 of 2)

Name

Count

Type

Description

GPIO[4]/

U1_RXD

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Serial Input: Serial data input from device pin to receive shift register.

GPIO[5]/

U1_TXD

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Serial Output: Composite serial data output to the communications

link-peripheral, modem, or data set. The TXD signal is set to the

MARKING (logic 1) state upon a Reset operation.

GPIO[6]/

U1_CTS#

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Clear To Send: When low, this pin indicates that the receiving UART is

ready to receive data. When the receiving UART deasserts CTS# high,

the transmitting UART should stop transmission to prevent overflow of

the receiving UARTs buffer. The CTS# signal is a modem-status input

whose condition may be tested by the host processor or by the UART

when in Autoflow mode as described below:

Non-Autoflow Mode:

When not in Autoflow mode, bit 4 (CTS) of the Modem Status

register (MSR) indicates the state of CTS#. Bit 4 is the complement

of the CTS# signal. Bit 0 (DCTS) of the Modem Status register

indicates whether the CTS# input has changed state since the

previous reading of the Modem Status register. CTS# has no effect

on the transmitter. The user may program the UART to interrupt the

processor when DCTS changes state. The programmer may then

stall the outgoing data stream by starving the transmit FIFO or

disabling the UART with the IER register.

NOTE: When UART transmission is stalled by disabling the UART,

the user may not receive an MSR interrupt when CTS#

reasserts. This occurs because disabling the UART also

disables interrupts. As a workaround, the user may use Auto

CTS in Autoflow Mode, or program the CTS# pin to interrupt.

Autoflow Mode:

NOTE: In Autoflow mode, the UART Transmit circuitry will check

the state of CTS# before transmitting each byte. When

CTS# is high, no data is transmitted.

GPIO[7]/

U1_RTS#

1

I/O

General Purpose I/O: These pins may be selected on a per pin

basis as general purpose inputs or outputs. The default mode is a

general purpose input.

Request To Send: When low, this informs the remote device that

the UART is ready to receive data. A reset operation sets this signal

to its Inactive (high) state. LOOP mode operation holds this signal in

its Inactive state.

Non-Autoflow Mode:

The RTS# output signal may be asserted by setting bit 1 (RTS) of

the Modem Control register to a 1. The RTS bit is the complement of

the RTS# signal.

Autoflow Mode:

RTS# is automatically asserted by the autoflow circuitry when the

Receive buffer exceeds its programmed threshold. It is deasserted

when enough bytes are removed from the buffer to lower the data

level back to the threshold.

Total

8

28

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Intel® 80332 I/O Processor Datasheet

Package Information

Document Number: 274066-004US

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29

Intel® 80332 I/O Processor Datasheet

Package Information

Table 13.

Test and Miscellaneous Signals

Name

TCK

Count

Type

Description

1

I

Test Clock provides clock input for IEEE 1149.1 Boundary Scan

Testing (JTAG). State information and data are clocked into the

device on the rising clock edge and data is clocked out on the falling

clock edge.

TDI

1

I

Test Data Input is the JTAG serial input pin. TDI is sampled on the

rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of

the Test Access Port. This signal has a weak internal pull-up to

ensure proper operation when this pin is not being driven.

Sync(T)

TDO

O

Test Data Output is the serial output pin for the JTAG feature. TDO

is driven on the falling edge of TCK during the SHIFT-IR and

SHIFT-DR states of the Test Access Port. At other times, TDO

floats. The behavior of TDO is independent of RSTIN# or PWRGD.

Sync(T)

Rst(T)

TRST#

TMS

1

I

Test Reset asynchronously resets the Test Access Port controller

function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has

a weak internal pull-up.

Async

I

Test Mode Select is sampled on the rising edge of TCK to select

the operation of the test logic for IEEE 1149 Boundary Scan testing.

This pin has a weak internal pull-up.

Sync(T)

N/C

7

1

-

No Connect. Do not connect to any signal, power or ground.

PWRDELAY

I

Power Fail Delay is used to delay the reset of the memory

controller in a power-fail condition. This allows the self-refresh

command to be sent to the DDR SDRAM array.

Async

PWRGD

RSTIN#

1

I

Power Supply Good: Signal that specifies that the motherboard

power supply has stabilized. This signal is used to asynchronously

reset the 80332 when it is low. The low period of this signal must be

long enough for the system power supply to stabilize and for the

base PLLs to lock.

Async

Note: This is the same signal as PERST# which is described in the

PCI Express Card Electromechanical Specification, Revision 1.0a.

1

I

Reset Input brings PCI-specific registers, sequencers, and signals

to a consistent state. When RSTIN# is asserted:

Async

•

PCI output signals are driven to a known consistent state.

PCI bus interface output signals are three-stated.

Open drain signals such as B_SERR# are floated.

RSTIN# may be asynchronous to B_CLKIN when asserted or

deasserted. Although asynchronous, deassertion must be ensured

to be a clean, bounce-free edge.

Total

15

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Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 14.

Reset Strap Signals (Sheet 1 of 2)

Name

Count

Type

Description

RETRY

1

C

Configuration Retry Mode: RETRY is latched on the rising

(asserting) edge of PWRGD and determines when the PCI interface

of the ATU will disable PCI configuration cycles by signaling a retry

until the configuration cycle retry bit is cleared in the PCI configuration

and status register.

0 = Configuration Cycles enabled (Requires pull down resistor.)

1 = Configuration Retry enabled in the ATU (Default mode)

NOTE: Muxed onto signal AD[6], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

CORE_RST#

1

C

Core Reset Mode is latched on the rising (asserting) edge of PWRGD

and determines when the Intel XScale^®core is held in reset until the

processor reset bit is cleared in PCI configuration and status register.

0 = Hold in reset. (Requires pull-down resistor.)

1 = Do not hold in reset. (Default mode)

NOTE: Muxed onto signal AD[5], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

P_BOOT16#

MEM_TYPE

1

C

Bus Width is latched on the rising (asserting) edge of PWRGD, it

sets the default bus width for the PBI Memory Boot window.

0 = 16 bits wide (Requires a pull-down resistor.)

1 = 8 bits wide (Default mode)

NOTE: Muxed onto signal AD[4], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

Memory Type: MEM_TYPE is latched on the rising (asserting) edge

of PWRGD and it defines the speed of the DDR SDRAM interface.

0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.)

1 = DDR SDRAM at 333 MHz (Default mode)

NOTE: Muxed onto signal AD[2], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

A_PCIX133EN

PCI Bus Segment ‘A’ 133 MHz Enable: A_PCIX133EN is latched

on the rising (asserting) edge of PWRGD and it determines the

maximum PCI-X mode operating frequency.

0 = 100 MHz enabled (Requires pull down resistor).

1 = 133 MHz enabled (Default mode).

NOTE: Muxed onto signal AD[3], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

B_PCIX133EN

1

C

PCI Bus Segment ‘B’ 133 MHz Enable: B_PCIX133EN latched

on rising (asserting) edge of PWRGD and determines maximum

PCI-X mode operating frequency.

0 = 100 MHz enabled (Requires pull down resistor.)

1 = 133 MHz enabled (Default mode)

NOTE: Muxed onto signal AD[10], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37

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31

Intel® 80332 I/O Processor Datasheet

Package Information

Table 14.

Reset Strap Signals (Sheet 2 of 2)

Name

Count

Type

Description

B_HSLOT[3:0]

4

C

Number of Slots: B_HSLOT[3:0] latched on rising (asserting) edge

of PWRGD and indicates when the ‘B’ PCI-X bus interface Standard

Hot-Plug Controller is enabled, the total number of slots in both

Hot-Plug enabled mode and disabled mode, and the Hot-Plug mode.

B_HSLOT[3] enables Hot-Plug when high and disables Hot-Plug

when low.

Hot-Plug disabled

0000 = 1 slot

Hot-Plug enabled

1000 = reserved

1001 = reserved

1010 = reserved

1011 = reserved

1100 = reserved

1101 = reserved

1110 = reserved

1111 = Parallel 1-slot-no-glue

0001 = 2 slots

0010 = 3 slots

0011 = 4 slots

0100 = 5 slots

0101 = 6 slots

0110 = 7 slots

0111 = 8 slots

NOTE: 1111 is Default mode.

NOTE: Muxed onto signal AD[15:12], see Table 17 “Pin

Multiplexing for Functional Modes” on page 37.

SMB_MA5

SMB_MA3

SMB_MA2

SMB_MA1

4

C

Manageability Address (MA): latched on rising (asserting) edge

of PWRGD and maps to MA bit 5, 3, 2, and 1, where MA bits 7- 0

represent the address the SMBus slave port will respond to when

access is attempted.

0 = (Requires pull down resistor.)

1 = (Default mode)

NOTE: Muxed onto signal A[19:16], see Table 17 “Pin

Multiplexing for Functional Modes” on page 37.

PCIODT_EN

1

C

PCI Bus ODT Enable: PCIODT_EN is latched on the rising

(asserting) edge of PWRGD, and determines when the PCI-X

interface will have On Die Termination enabled. PCI ODT enable is

valid for both A and B segments.

The following signals are affected by PCIODT_EN:

A_ACK64#, A_AD[63:32], A_C/BE[7:4]#, A_DEVSEL#, A_FRAME#,

A_IRDY#, A_LOCK#, A_M66EN, A_PAR64, A_PERR#,

A_REQ[3:0]#, A_REQ64#, A_SERR#, A_STOP#, A_TRDY#,

B_ACK64#, B_AD[63:32], B_C/BE[7:4]#, B_DEVSEL#, B_FRAME#,

B_IRDY#, B_LOCK#, B_M66EN, B_PAR64, B_PERR#,

B_REQ[4:0]#, B_REQ64#, B_SERR#, B_STOP#, B_TRDY#,

XINT[7:0]#

0 = ODT disabled (Requires pull-down resistor).

1 = ODT enabled (Default mode).

NOTE: Muxed onto signal A[20], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

PD1

1

C

Pull-down Resistor is required for default mode.

NOTE: Muxed onto signal AD[7], see Table 17 “Pin Multiplexing

for Functional Modes” on page 37.

Total

16

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Intel® 80332 I/O Processor Datasheet

Package Information

Table 15.

Power and Ground Pins

Name

Count

Type

Description

V

5

PWR

PLL 1-5 Power is a separate V

supply ball for the phase lock

CC15

CCPLL[1-5]

loop clock generator. It is to be connected to the board V

plane.

CC15

Each V

requires a lowpass filter circuit to reduce

CCPLL

noise-induced clock jitter and its effects on timing relationships. See

the Intel^®80332 I/O Processor Design Guide for more information.

V

49

29

PWR

3.3 V Power balls to be connected to a 3.3 V power board plane.

CC33

V

2.5 V/1.8 V Power balls to be connected to a 2.5 V or 1.8 V power

CC25/18

board plane, dependent on DDR or DDRII mode.

V

56

PWR

1.5 V Power balls to be connected to a 1.5 V power board plane.

VCC15 = core

CC15

VCC15E = PCI Express

V

7

1

PWR

1.3 V Power balls to be connected to a 1.35 V power board plane.

CC13

PE_VCCBG

DDR_VREF

PCI Express Band Gap Analog Ref Power: 2.5v power for analog

reference circuit, separated from all other VCC signals. Requires a

lowpass filter.

1

PWR

SDRAM Voltage Reference is used to supply the reference voltage

to the differential inputs of the memory controller pins.

V

218

5

GND

Ground balls to be connected to a ground board plane.

SS

V

Analog Ground balls need to be connected to the appropriate

SSA[1-5]

V

filter, and not to board ground.

CCPLL

PE_VSSBG

1

GND

PCI Express Band Gap Analog Ground: Ground for analog

reference circuit, separated from all other VSS signals.

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33

Intel® 80332 I/O Processor Datasheet

Package Information

Table 16.

Pin Mode Behavior (Sheet 1 of 4)

ECC

Off

32-Bit

DDR

32-Bit

B_PCI

32-Bit

A_PCI

Reset

Norm

M_CK[2:0]

M_CK[2:0]#

M_RST#

MA[13:0]

BA[1:0]

X (1)

0

VO

VB

VO

VI

VO

VB

ID,Z

VB

ID,Z

VB

Z

VO

ID,Z

VB

ID,Z

VB

ID,Z

VB

VO

Z

-

0*

1*

0*

Z*

VI

0

RAS#

CAS#

WE#

CS[1:0]#

CKE[1:0]

DQ[63:32]

DQ[31:0]

CB[7:0]

DQS[8]

DQS[7:4]

DQS[3:0]

DQS[8]#

DQS[7:4]#

DQS[3:0]#

DM[8]

DM[7:4]

VO

VI

DM[3:0]

VO

VI

DDR_VREF

ODT[1:0] (2)

DDRRES[2:1]

DDRCRES0

DDRSLWCRES

DDRIMPCRES

A[22:16]

AD[15:0]

A[2:0]

VO

VB

VO

VB

VO

VB

VO

VI

VO

VB

VO

VB

-

VO

VB

VO

VB

-

Z*

VO

VB

H

-

H

-

ALE

0

-

POE#

1

-

PWE#

1

-

PCE[1]#

PCE[0]#

H

-

H

-

REFCLK+

REFCLK-

VI

-

PE0Tp[7:0]

PE0Tn[7:0]

Z (3)

ID(4)

VO

VI

-

PE0Rp[7:0]

PE0Rn[7:0]

PE_RCOMPO

PE_ICOMPI

VI

34

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Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 16.

Pin Mode Behavior (Sheet 2 of 4)

ECC

Off

32-Bit

DDR

32-Bit

B_PCI

32-Bit

A_PCI

Reset

Norm

B_AD[63:32]

B_AD[31:0]

B_PAR

0

VB

VO

VB

VI

-

H

-

VB

0

VB

B_PAR64

Z

H

VB

-

B_C/BE[7:4]#

B_C/BE[3:0]#

B_GNT[4:0]#

B_REQ64#

B_REQ[4:0]#

B_ACK64#

B_FRAME#

B_IRDY#

0

H

-

VO

VI

Z

-

VB

VI

-

Z

-

Z

-

B_TRDY#

B_STOP#

B_DEVSEL#

B_LOCK#

B_SERR#

B_CLKIN

VO

Z

-

Z

-

VI

VO

Z

-

PWRGD

VI

-

RSTIN#

VI

-

B_RST#

VO

VB

VI

-

B_PERR#

B_M66EN

B_PME#

-

VB

VI

VO

Z

-

B_PCIXCAP

B_CLKO[4:0]

B_CLKOUT

A_AD[63:32]

A_AD[31:0]

A_PAR

VI

-

VO

VB

VO

VB

-

H

-

0

-

A_PAR64

Z

H

-

A_C/BE[3:0]#

A_C/BE[7:4]#

A_REQ64#

A_ACK64#

A_FRAME#

A_IRDY#

0

Z

H

-

VO

Z

-

Z

-

Z

-

A_TRDY#

A_STOP#

A_DEVSEL#

A_SERR#

A_RST#

VO

Z

-

VO

Z

-

A_PERR#

-

Document Number: 274066-004US

August 2005

35

Intel® 80332 I/O Processor Datasheet

Package Information

Table 16.

Pin Mode Behavior (Sheet 3 of 4)

ECC

Off

32-Bit

DDR

32-Bit

B_PCI

32-Bit

A_PCI

Reset

Norm

A_LOCK#

A_CLKO[3:0]

A_CLKOUT

Z

VO

VI

VB

VI

H

VB

VO

VI

-

A_CLKIN

A_M66EN

VB

VI

A_PME#

A_REQ[3:0]#

A_GNT[3:0]#

A_PCIXCAP

A_RCOMP

VI

-

VO

VI

AO

VI

Z

AO

VI

B_RCOMP

XINT[7:4]#

XINT[3:0]#

VI

HPI#

VI

B_HPWRFLT# (5)

B_HMRL# (5)

B_HPRSNT2# (5)

B_HPWREN (5)

B_HPRSNT1# (5)

B_HATNLED# (5)

B_HPWRLED# (5)

B_HBUTTON# (5)

VI

VO

VI

Z

VO

VI

Z

VI

H

SCL0, SCD0, SCL1/ SCLK,

SCD1/ SDTA

VB

GPIO[3:0]/ U0_RTS#, U0_CTS#,

U0_TXD, U0_RXD,

VI

VB

-

GPIO[7:4]/ U1_RTS#, U1_CTS#,

U1_TXD, U1_RXD

TCK

TDI

VI

H

VI

H

-

TDO

VO*

H

VO

H

TRST#

TMS

H

PWRDELAY

PWRGD

NC[3:0]

NOTES:

VI

H

VI

H

L = pulled down to V

.

SS

Z = output disabled (Floats).

1 = driven to V

0 = driven to V

X = driven to unknown state.

ID = The input is disabled.

H = pulled up to V

PD = pull-up disabled.

.

CC

VB = acts like a Valid Bidirectional pin.

VO = a Valid Output level is driven.

VI = Need to drive a Valid Input level.

* = After power fail sequence completes.

SS

.

CC

** = Caused by Hi-Z from mode pins only.

AO = analog output level.

36

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 16.

Pin Mode Behavior (Sheet 4 of 4)

ECC

Off

32-Bit

DDR

32-Bit

B_PCI

32-Bit

A_PCI

Reset

Norm

1. Clocks become valid right before M_RST# deasserts.

2. ODT signal to be low during power up and initialization per DDR-II JEDEC specification.

3. High impedance common mode DC voltage driven per PCI Express Specification, Revision 1.0.

4. Input Disabled, but termination on, per PCI Express Specification, Revision 1.0.

5. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

PWRGD.)

Table 17.

Pin Multiplexing for Functional Modes

Reset Straps

A[20]

AD[15]

PCIODT_EN

B_HSLOT[3]

AD[14]

B_HSLOT[2]

AD[13]

B_HSLOT[1]

AD[12]

B_HSLOT[0]

AD[10]

B_PCIX133EN

AD[7]

PD1

AD[6]

RETRY

AD[5]

CORE_RST#

AD[4]

P_BOOT16#

AD[3]

A_PCIX133EN

AD[2]

MEM_TYPE

A[19]

SMB_MA5

A[18]

SMB_MA3

A[17]

SMB_MA2

A[16]

SMB_MA1

SCL1/SCLK

SCD1/SDTA

GPIO[0]/U0_RXD

GPIO[1]/U0_TXD

GPIO[2]/U0_CTS#

GPIO[3]/U0_RTS#

GPIO[4]/U1_RXD

GPIO[5]/U1_TXD

GPIO[6]/U1_CTS#

GPIO[7]/U1_RTS#

-

Document Number: 274066-004US

August 2005

37

Intel® 80332 I/O Processor Datasheet

Package Information

Figure 2.

829-Ball FCBGA Package Diagram

S2

S1

E

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

F1

R

P

N

M

L

D

F2

K

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Pin #1

Corner

Die

e

øb

Laser Mark

Top View

Bottom View

A

A3

A1

C

Seating Plane

Side View

B1230-02

Table 18.

FC-style, H-PBGA Package Dimensions

829-Pin BGA

Minimum

Symbol

Maximum

A

2.392

0.50

2.942

0.70

A1

A3

0.742

0.872

b

0.61 Ref.

9.88 Ref.

C

1.15

37.45

1.37

37.55

D

E

F1

F2

10.16 Ref.

1.27 Ref.

0.97 Ref.

e

S1

S2

NOTE: Measurement in millimeters.

38

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Figure 3.

Intel^®80332 I/O Processor Signal Group Locations (Bottom View)

21

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

22 23 24 25 26 27 28 29

AJ

AH

AG

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

AF

AE

AD

AC

AB

AA

Y

DDR / DDRII SDRAM

GPIO

PBI

SHPC

W

V

W

V

U

T

VCC/VSS

R

P

N

M

L

M

L

K

J

H

PCI-X Bus B

PCI-X Bus A

G

F

E

D

PCI Express

C

B

A

21

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

22 23 24 25 26 27 28 29

B1215-01

Document Number: 274066-004US

August 2005

39

Intel® 80332 I/O Processor Datasheet

Package Information

Figure 4.

Intel^®80332 I/O Processor Ballout - Left Side (Bottom View)

40

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Figure 5.

Intel^®80332 I/O Processor Ballout - Right Side (Bottom View)

16

17

18

19

20

21

22

23

24

25

26

27

28

29

M_CK0 M_CK0# DQ[36]

DM[4]

DQ[38]

DQ[35]

DQ[40]

DQS5#

DQ[46]

DQS#6

DQS6

VSS

NB

AJ

VCC25

M_CK2

DQ[37]

VSS

DQS4#

DQS[4]

VSS

DQ[39]

DQ[34]

VCC25

CS0#

DQ[44]

VSS

DQ[41]

VCC25

VSS

DQS5

DQ[42]

DQ[43]

DQ[53]

CS1#

DQ[47]

VSS

DM[6]

DQ[49]

VSS

DQ[54]

DQ[50]

VCC25

DQ[57]

DQ[63]

DQ[55]

DQ[51]

DQ[61]

DM[7]

VSS

DQ[60]

DQ[56]

VSS

NB

AH

AG

DQS[8] M_CK2#

VSS

DQS8#

VSS

VCC25

CB[7]

CB[2]

VSS

DQ[32]

DQ[33]

BA[0]

DQ[45]

DM[5]

VSS

DQ[48]

DQ[52]

VCC25

SDTA

DQS7#

DQS7

DQ[58]

AF

AE

AD

AC

AB

AA

Y

CB[6]

CB[3]

VCC25

RAS#

WE#

MA13

ODT0

DQ[62]

DQ[59]

GPIO

[5]

GPIO

[4]

DDR

CRES0

DDRSLW DDRIMP

CRES

MA10

VCC25

CAS#

VSS

CRES

GPIO

[6]

GPIO

[7]

GPIO

[0]

GPIO

[1]

DDR

RES1

DDR

RES2

VSS

VCC25

VSS

VCC25

VSS

VCC25

VSS

VCC25

VSS

ODT1

VCC25

VSS

SCD0

SCLK

VSS

PCE1#

A[0]

GPIO

[2]

GPIO

[3]

SCL0

VSS

VCC33

AD[11]

PCE0#

VCC33

VSS

ALE

A[1]

VCC15

PWE#

AD[15]

A[17]

A[21]

A[20]

VCC15

VSS

VCC15

VSS

VCC33

VSS

A[2]

A[22]

A[19]

AD[7]

AD[3]

AD[2]

VSS

AD[8]

AD[5]

AD[9]

VSS

A[16]

AD[0]

W

VCC15

POE#

VCC33

AD[13]

AD[1]

V

U

T

A_

GNT3#

A_

AD48

VCC15

VSS

VCC15

VSS

VCC15

VSS

VCC15

VSS

VCC33

VSS

A[18]

AD[14]

AD[6]

VSS

AD[12]

XINT2#

VCC33

VCC33 XINT#0 XINT1#

A_

RCOMP

AD[10]

AD[4]

VSS

AD[49]

VSS

AD50

A_

PCIXCAP

A_

PME#

A_

AD52

A_

AD53

VSSA4

VCC15

VCC33

A_RST# XINT3#

AD[51]

VCC33

R

P

N

M

L

A_

GNT2#

A_

AD32

A_

AD33

A_

AD55

A_

AD56

VSS

VCC15

VSS

VCC15

VSS

VCC15

VSS

VCC33

VSS

VCC33

VSS

AD[54]

VCC33

VSS

A_

AD35

A_

AD34

A_

REQ0#

A_

AD59

A_

AD57

A_

AD58

VCC15

VSSA1

VCC33

VCC

PLL1

A_

AD38

A_

AD37

A_

AD36

A_

AD62

A_

AD61

A_

AD60

VCC15

VCC33

VSS

VCC33

A_

AD41

A_

AD39

A_

AD40

A_

AD63

VSS

VCC15

VSS

VCC33

VSS

VCC33

VSS

A_

C/BE6# C/BE7#

A_

AD42

A_

AD43

A_

REQ3#

A_

VCC33

VSS

C/BE4# C/BE5# PAR64

K

A_

AD47

A_

AD46

A_

AD45

A_

AD44

A_

VCC15E

VSS

VCC33

VSS

VCC33

VSS

VCC33

VSS

ACK64# REQ64#

J

A_

C/BE1#

A_

AD14

A_

AD11

A_

C/BE0#

A_

AD6

A_

AD3

A_

CLKO3

A_

CLKO0

VSS

A_

VCC33

VSS

H

G

A_

AD15

A_

AD12

A_

AD7

A_

AD4

A_

CLKIN

A_

PERR#

PE0TN7

VSS

VCC33

VSS

A_

CLKO1 CLKOUT

A_

AD13

A_

AD9

A_

AD5

A_

AD1

A_

VSS

A_

PE0TP7 PE0RN7

VSS

VCC33

A_PAR

A_

VSS

A_

CLKO2

REQ1# DEVSEL#

F

A_

AD10

A_

REQ2#

A_

AD2

A_

TRDY#

A_

IRDY#

VCC15E PE0RP7 PE0RP5

VSS

A_AD0

A_AD23

VCC33

VSS

E

D

C

B

SERR# LOCK#

A_

AD8

A_

AD27

A_

AD20

A_

PE0RP4

VSS

PE0RN5 PE0TP5

VSS

VCC33

VSS

VCC33

NB

C/BE3# STOP#

A_

M66EN

A_

AD28

A_

AD25

A_

AD21

A_

AD17

A_

PE0RN4 PE0TP4 VCC15E PE0TN5

VCC33

C/BE2# FRAME#

A_

AD30

A_

AD26

A_

GNT1#

A_

AD18

A_

VSS

PE0TN4 PE0RN6

VSS

AD16

PE_

ICOMPI

A_

AD31

A_

AD29

A_

GNT0#

A_

AD24

A_

AD22

A_

AD19

VSS

PE0RP6 PE0TP6 PE0TN6

VSS

NB

A

16

17

18

19

20

21

22

23

24

25

26

27

28

29

B1240-02

Document Number: 274066-004US

August 2005

41

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 1 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

A1

A2

--

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

C1

VSS

C25

C26

C27

C28

C29

D1

A_AD21

A_AD17

A_C/BE2#

A_FRAME#

VCC33

B_AD10

B_AD11

B_AD12

VCC33

B_C/BE2#

B_AD19

VSS

A3

VSS

PE_RCOMPO

VSS

A4

B_AD16

B_AD18

B_AD21

B_C/BE3#

B_AD26

B_AD29

VSS

A5

PE0TN4

PE0RN6

VSS

A6

A7

D2

A8

VSS

D3

A9

A_AD30

VSS

D4

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

B1

D5

PE0RP2

PE0RN2

VCC15E

PE_VSSBG

PE_VCCBG

PE_ICOMPI

VSS

A_AD26

A_GNT1#

VSS

D6

D7

D8

B_AD24

B_AD27

VSS

A_AD18

A_AD16

VSS

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

E1

PE0TN2

PE0RN1

VSS

--

PE0RP6

PE0TP6

PE0TN6

A_AD31

A_AD29

A_GNT0#

A_AD24

A_AD22

A_AD19

VSS

VCC33

B_AD13

B_AD14

B_PAR

B_AD17

VCC33

B_AD22

B_AD25

VCC33

B_AD30

PE0TP2

PE0TP1

VCC15E

PE0RN3

VSS

C2

PE0RP3

PE0TN3

PE0RP4

VSS

C3

C4

C5

C6

PE0RN5

PE0TP5

VSS

C7

C8

C9

A_AD8

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

A_AD27

VSS

--

A_AD23

A_AD20

VCC33

A_C/BE3#

A_STOP#

VSS

--

B2

VSS

B3

B_AD15

B_C/BE1#

VSS

B4

PE0RN4

PE0TP4

VCC15E

PE0TN5

A_M66EN

VCC33

A_AD28

A_AD25

B5

B6

B_AD20

B_AD23

VSS

B_C/BE0#

VSS

B7

E2

B8

E3

B_M66EN

B_AD9

B9

B_AD28

B_AD31

VSS

E4

B10

B11

E5

VSS

E6

B_FRAME#

42

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 2 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

B12

E8

PE0TN1

VSS

C24

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

G1

VCC33

A_AD9

VCC33

A_AD5

A_AD1

VSS

E7

H3

B_CLKOUT

B_AD1

E9

VCC33

VSS

H4

B_AD2

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

F1

H5

VCC33

VSS

H6

B_ACK64#

B_CLKO4

B_CLKO2

B_CLKO3

B_TRDY#

B_GNT2#

B_GNT4#

B_PME#

VSS

PE0RP1

PE0TN0

VCC15E

PE0TP3

VCC15E

PE0RP7

PE0RP5

VSS

H7

A_CLKO2

A_PAR

VSS

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

J1

A_REQ1#

A_DEVSEL#

B_AD3

B_AD4

B_AD5

VSS

G2

A_AD10

A_REQ2#

VSS

G3

REFCLK+

VSS

G4

G5

B_DEVSEL#

B_STOP#

VSS

A_C/BE1#

A_AD14

A_AD11

A_C/BE0#

A_AD6

A_AD2

A_AD0

VSS

G6

G7

G8

VSS

A_SERR#

A_LOCK#

A_TRDY#

A_IRDY#

B_AD6

B_AD7

VCC33

B_AD8

B_IRDY#

VCC33

B_CLKO0

VSS

G9

B_CLKIN

VCC33

B_REQ64#

B_REQ2#

VSS

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

A_AD3

A_CLKO3

A_CLKO0

VSS

F2

PE0RP0

REFCLK-

PE0TN7

VSS

VCC33

F3

VSS

F4

VSS

F5

VSS

F6

A_AD15

A_AD12

VSS

B_AD49

B_AD48

VCC33

F7

J2

F8

J3

F9

VSS

A_AD7

A_AD4

VCC33

A_CLKO1

A_CLKOUT

VSS

J4

B_PERR#

B_SERR#

VSS

F10

F11

F12

F13

F14

F15

F16

F17

VSS

J5

B_GNT3#

VSS

J6

J7

B_LOCK#

B_CLKO1

VSS

PE0TP0

PE0RN0

VSS

J8

J9

A_CLKIN

VSS

J10

J11

J12

VCC15

PE0TP7

PE0RN7

VSS

A_PERR#

VCC15

Document Number: 274066-004US

August 2005

43

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 3 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

F18

F19

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

K1

VSS

A_AD13

VSS

H1

H2

B_AD0

VSS

J13

J14

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

N1

VSS

VCC15E

VSS

K27

K28

K29

L1

A_C/BE4#

A_C/BE5#

A_PAR64

B_AD53

VSS

VCC15E

VSS

VCCPLL2

VSSA2

VCC15

VSS

VCC33

VSS

L2

VCC33

VSS

L3

B_AD52

B_AD51

VCC33

B_AD35

B_AD34

B_AD33

VSS

VCC15

VSS

L4

A_AD47

A_AD46

VCC33

A_AD45

A_AD44

VCC33

A_ACK64#

A_REQ64#

B_AD50

B_REQ4#

B_REQ3#

VSS

L5

VCC15

VSSA1

VCCPLL1

VSS

L6

L7

L8

L9

VCC33

A_AD38

A_AD37

VSS

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

M1

M2

M3

M4

M5

M6

VCC15

VSS

VCC15

VSS

A_AD36

A_AD62

VCC33

A_AD61

A_AD60

B_AD59

B_AD58

B_AD57

VSS

K2

VSS

K3

VCCPLL3

VSS

K4

K5

B_REQ1#

N/C7

VSS

K6

VCC15

VSS

K7

VSS

N2

K8

B_AD32

VCC15

VSS

VCC33

VSS

N3

K9

N4

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

A_AD41

A_AD39

A_AD40

VCC33

A_C/BE6#

A_C/BE7#

VSS

N5

B_AD41

B_AD40

VSS

N6

N7

VCC15

VSS

N8

B_AD39

VSS

N9

VSSA3

VSS

N10

N11

N12

N13

N14

N15

N16

N17

N18

VCC15

VSS

VCC33

VSS

A_AD63

B_AD56

B_AD55

VCC33

B_AD54

B_AD38

VCC33

VCC15

VSS

VCC33

VSS

VCC15

VSS

VCC33

A_AD42

VSS

VCC15

VSS

VCC15

44

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 4 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

K24

K25

K26

N22

N23

N24

N25

N26

N27

N28

N29

P1

A_AD43

A_REQ3#

VSS

M7

M8

B_AD37

B_AD36

VCC15

B_AD45

VCC33

B_AD46

B_AD47

VSS

N19

N20

N21

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

U1

VSS

VCC33

VSS

M9

A_AD35

VCC33

A_AD34

A_REQ0#

VCC33

A_AD59

A_AD57

A_AD58

B_AD60

VSS

R5

VCC15

VSS

R6

R7

VCC15

VSS

R8

R9

AD10

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

T1

VCC15

VSS

AD6

AD4

VCC15

VSS

XINT2#

VSS

P2

VCC15

VCCPLL4

VSSA4

VSS

A_AD49

A_AD50

VSS

P3

B_AD61

B_AD62

VSS

P4

P5

A_RCOMP

B_C/BE4#

B_C/BE5#

B_C/BE7#

VSS

P6

B_AD44

B_AD43

B_AD42

VCC15

VSS

VCC15

VSS

P7

U2

P8

VCC33

A_PCIXCAP

A_RST#

XINT3#

VCC33

A_PME#

A_AD51

VCC33

A_AD52

A_AD53

N/C2

U3

P9

U4

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

U5

B_HPRSNT1#

B_HATNLED#

VCC33

B_HPWRFLT#

VSS

VCC15

VSS

U6

U7

VCCPLL5

VSSA5

VCC15

VSS

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

VCC15

VSS

VCC15

VSS

VCC13

VSS

VCC15

VSS

T2

VSS

VCC15

VSS

T3

B_C/BE6#

B_GNT1#

VSS

VCC33

A_GNT2#

A_AD32

A_AD33

VSS

T4

VCC15

VSS

T5

T6

B_GNT0#

VSS

VCC15

VSS

T7

T8

B_HMRL#

VCC15

VSS

VCC33

A18

A_AD54

A_AD55

VSS

T9

T10

T11

T12

AD14

VCC15

VSS

A_AD56

AD12

Document Number: 274066-004US

August 2005

45

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 5 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

R1

R2

B_AD63

B_PAR64

VCC33

B_REQ0#

A_AD48

B_RCOMP

XINT7#

VCC33

XINT6#

XINT5#

VSS

T13

T14

T15

T16

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

W27

W28

W29

Y1

VCC15

VSS

U25

U26

A_GNT3#

VCC33

XINT0#

XINT1#

AD11

R3

VCC15

VSS

U27

R4

U28

U29

V1

VCC13

VSS

Y24

Y25

A0

V2

VCC15

VSS

Y26

VCC33

A17

V3

Y27

V4

VCC15

VSS

Y28

A21

V5

Y29

A20

V6

VCC15

VSS

AA1

B_HBUTTON#

N/C4

V7

B_HPWRLED#

B_RST#

VCC15

VSS

AA2

V8

VCC33

A2

AA3

VSS

V9

AA4

N/C5

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

V27

V28

V29

W1

W2

W3

W4

W5

W6

A22

AA5

TRST#

VSS

VCC15

VSS

AD7

AA6

AD2

AA7

PWRGD

HPI#

VCC13

VSS

AA8

AD8

AA9

VSS

VCC15

VSS

AD9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AB1

VCC25

VSS

VCC15

VSS

A16

VCC25

VSS

VCC15

TCK

VCC15

VSS

Y2

VCC25

VSS

Y3

VSS

POE#

Y4

VSS

VCC25

VSS

A19

Y5

N/C0

TDI

AD3

Y6

VCC25

VSS

VCC33

AD13

Y7

VSS

Y8

N/C3

VCC13

VSS

VCC25

GPIO2/U0_CTS#

GPIO3/U0_RTS#

SCL0

AD5

Y9

VSS

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

AD1

VCC13

VSS

AD0

VCC33

PCE1#

PCE0#

VSS

PWRDELAY

VSS

VCC13

VSS

XINT4#

B_PCIXCAP

VCC33

B_HRESET# (C-0)

VCC15

VSS

ALE

VCC15

VSS

A1

N/C6

46

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 6 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

W7

W8

B_HPWREN

B_HPRSNT2#

VSS

Y19

Y20

VCC15

VSS

AB2

AB3

VSS

TDO

W9

Y21

PWE#

AD15

AB4

TMS

W10

W11

VCC13

VSS

Y22

AB5

VSS

Y23

VSS

AB6

RSTIN#

VSS

AB7

VCC25

VSS

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AD1

RAS#

AE2

AB8

VCC25

CAS#

AE3

DQS0#

DQS0

VSS

AB9

VCC25

VSS

AE4

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AC1

ODT0

AE5

VCC25

VSS

AE6

DQ13

DQ8

SDTA/SCD1

GPIO5/U1_TXD

GPIO4/U1_RXD

DDRCRES0

DDRSLWCRES

DDRIMPCRES

DQ5

AE7

VCC25

VSS

AE8

VSS

AE9

DQS2#

DQ23

VSS

VCC25

VSS

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AF1

VCC25

VSS

MA1

DQ26

VSS

VCC25

ODT1

AD2

DQ4

AD3

VSS

CB0

SCD0

AD4

DQ1

VSS

SCLK/SCL1

GPIO6/U1_CTS#

GPIO7/U1_RTS#

VSS

AD5

DQ0

CB7

AD6

VCC25

MA7

DQ33

VSS

AD7

AD8

DQ12

CS0#

DM5

GPIO0/U0_RXD

GPIO1/U0_TXD

DDRRES1

DDRRES2

DDR_VREF

VSS

AD9

VSS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

DQ22

VSS

DQ19

DQ53

DQ52

VSS

VCC25

BA1

AC2

DQ27

DQ57

DM7

AC3

VSS

AC4

VSS

CB6

VSS

AC5

VSS

CB2

DQS7

DQ6

AC6

VSS

BA0

AC7

VSS

VCC25

WE#

AF2

DQ7

AC8

MA11

AF3

DQ2

AC9

MA9

VSS

AF4

VCC25

MA12

DQ9

AC10

AC11

AC12

VCC25

VSS

MA13

AF5

CS1#

AF6

MA2

VCC25

AF7

VSS

Document Number: 274066-004US

August 2005

47

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 7 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

AC13

AC14

AC15

AC16

AC17

AC18

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AG1

MA0

CB5

AD25

AD26

AD27

AD28

AD29

AE1

DQ62

DQ63

VSS

AF8

AF9

DQ21

DQS2

VCC25

MA3

CB4

AF10

AF11

AF12

AF13

AJ9

CB3

DQ59

DQ58

DM0

VSS

DQ29

VCC25

DM2

MA10

DQ30

CB1

AG26

AG27

AG28

AG29

AH1

DQ50

DQ51

DQ60

VSS

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

MA8

DQS_8#

VCC25

DQ32

DQS4

VCC25

DQ45

VCC25

DQ43

DQ48

DQ49

VCC25

DQ61

DQ56

DQS7#

VSS

DQ28

DQ25

DM3

--

AH2

VSS

M_CK1

M_CK1#

M_CK0

M_CK0#

DQ36

DM4

AH3

M_RST#

CKE1

VSS

AH4

AH5

AH6

DQ14

DQ20

VSS

AH7

AH8

DQ38

DQ35

DQ40

DQS5#

DQ46

DQS6#

DQS6

VSS

AH9

MA6

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AJ1

MA5

VCC25

DQ24

DQS3#

VSS

AG2

DQ3

AG3

VSS

DM8

AG4

CKE0

DM1

VCC25

M_CK2

DQ37

VSS

--

AG5

--

AG6

VSS

AG7

DQ11

DQ16

VSS

AG8

DQ39

DQ44

VSS

AG9

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

DQ18

MA4

DQS5

DQ47

VSS

DQS3

DQ31

VSS

DQ54

DQ55

VSS

DQS8

M_CK2#

VSS

--

48

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 19.

829-Lead Package - Alphabetical Ball Listings (Sheet 8 of 8)

Ball

Signal

Ball

Signal

Ball

Signal

AG19

AG20

AG21

AG22

AG23

AG24

AG25

DQS4#

DQ34

VSS

AJ2

AJ3

AJ4

AJ5

AJ6

AJ7

AJ8

--

VCC25

DQS1#

DQS1

DQ15

DQ10

DQ17

DQ41

DQ42

VSS

DM6

Document Number: 274066-004US

August 2005

49

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 1 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

--

A1

A2

A_AD28

A_AD29

A_AD30

A_AD31

A_AD32

A_AD33

A_AD34

A_AD35

A_AD36

A_AD37

A_AD38

A_AD39

A_AD40

A_AD41

A_AD42

A_AD43

A_AD44

A_AD45

A_AD46

A_AD47

A_AD48

A_AD49

A_AD50

A_AD51

A_AD52

A_AD53

A_AD54

A_AD55

A_AD56

A_AD57

A_AD58

A_AD59

A_AD60

A_AD61

A_AD62

A_AD63

A_C/BE0#

A_C/BE1#

A_C/BE2#

A_C/BE3#

C22

A22

B21

A21

P23

P24

N24

N22

M25

M23

M22

L23

L24

L22

K22

K24

J26

A_C/BE5#

A_C/BE6#

A_C/BE7#

A_CLKIN

A_CLKO0

A_CLKO1

A_CLKO2

A_CLKO3

A_CLKOUT

A_DEVSEL#

A_FRAME#

A_GNT0#

A_GNT1#

A_GNT2#

A_GNT3#

A_IRDY#

A_LOCK#

A_M66EN

A_PAR

K28

L26

L27

G27

H24

G24

F25

H23

G25

F29

C28

A23

B24

P22

U25

E29

E27

C20

F26

K29

R21

G29

R25

T29

N25

F28

E21

K25

J29

--

A28

A29

AH1

AH29

AJ1

AJ2

AJ28

AJ29

B1

--

B29

J28

A_ACK64#

A_AD0

A_AD1

A_AD2

A_AD3

A_AD4

A_AD5

A_AD6

A_AD7

A_AD8

A_AD9

A_AD10

A_AD11

A_AD12

A_AD13

A_AD14

A_AD15

A_AD16

A_AD17

A_AD18

A_AD19

A_AD20

A_AD21

A_AD22

A_AD23

A_AD24

A_AD25

A_AD26

E24

F23

E23

H22

G22

F22

H21

G21

D21

F20

E20

H19

G19

F19

H18

G18

B27

C26

B26

A26

D25

C25

A25

D24

A24

C23

B23

J25

J23

J22

A_PAR64

A_PCIXCAP

A_PERR#

A_PME#

A_RCOMP

A_REQ0#

A_REQ1#

A_REQ2#

A_REQ3#

A_REQ64#

A_RST#

A_SERR#

A_STOP#

A_TRDY#

A0

U29

T26

T27

R26

R28

R29

P26

P27

P29

N28

N29

N27

M29

M28

M26

L29

H20

H17

C27

D27

R22

E26

D28

E28

Y25

AA29

W21

W29

Y27

U21

V22

A1

A2

A16

A17

A18

A19

50

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 2 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

A_AD27

A21

D22

Y28

W22

V29

V28

W24

V23

T23

V26

T22

W23

W26

W27

T21

Y24

U24

V25

U22

Y22

AA28

H6

A_C/BE4#

B_AD21

B_AD22

B_AD23

B_AD24

B_AD25

B_AD26

B_AD27

B_AD28

B_AD29

B_AD30

B_AD31

B_AD32

B_AD33

B_AD34

B_AD35

B_AD36

B_AD37

B_AD38

B_AD39

B_AD40

B_AD41

B_AD42

B_AD43

B_AD44

B_AD45

B_AD46

B_AD47

B_AD48

B_AD49

B_AD50

B_AD51

B_AD52

B_AD53

B_AD54

B_AD55

B_AD56

B_AD57

B_AD58

B_AD59

K27

A6

C7

B7

D8

C8

A8

D9

B9

A9

C10

B10

K8

L8

A20

Y29

P4

R1

E1

B4

D5

A7

U1

U2

T3

B_AD62

A22

B_AD63

AD0

B_C/BE0#

B_C/BE1#

B_C/BE2#

B_C/BE3#

B_C/BE4#

B_C/BE5#

B_C/BE6#

B_C/BE7#

B_CLKIN

AD1

AD2

AD3

AD4

AD5

AD6

AD7

U3

G9

F7

AD8

AD9

B_CLKO0

B_CLKO1

B_CLKO2

B_CLKO3

B_CLKO4

B_CLKOUT

B_DEVSEL#

B_FRAME#

B_GNT0#

B_GNT1#

B_GNT2#

B_GNT3#

B_GNT4#

B_HPWRFLT#

B_HPRSNT2#

B_HMRL#

B_HPWREN

B_HPWRLED#

B_HPRSNT1#

B_HATNLED#

B_HBUTTON#

B_IRDY#

AD10

J8

AD11

L7

H8

H9

H7

E7

G5

E6

T6

AD12

L6

AD13

M8

M7

M5

N8

N6

N5

P8

P7

P6

R5

R7

R8

J2

AD14

AD15

ALE

B_ACK64#

B_AD0

B_AD1

B_AD2

B_AD3

B_AD4

B_AD5

B_AD6

B_AD7

B_AD8

B_AD9

B_AD10

B_AD11

B_AD12

B_AD13

B_AD14

B_AD15

B_AD16

B_AD17

B_AD18

H1

T4

H3

H11

F11

H12

U8

W8

T8

H4

G1

G2

G3

F1

F2

W7

V7

U5

U6

AA1

F5

F4

J1

E4

K1

L4

D1

D2

L3

D3

L1

C2

M4

M2

M1

N3

N2

N1

B_LOCK#

B_M66EN

B_PAR

J7

C3

E3

C4

R2

W4

J4

B3

A4

B_PAR64

C5

B_PCIXCAP

B_PERR#

A5

Document Number: 274066-004US

August 2005

51

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 3 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

B_AD19

B_AD20

B_REQ0#

B_REQ1#

B_REQ2#

B_REQ3#

B_REQ4#

B_REQ64#

B_RST#

B_SERR#

B_STOP#

B_TRDY#

BA0

D6

B6

B_AD60

B_AD61

DQ1

P1

B_PME#

B_RCOMP

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS0

DQS0#

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS1#

DQS2#

DQS3#

DQS4#

DQS5#

DQS6#

H13

V1

P3

R4

AD4

AF3

AG23

AF23

AH21

AF21

AJ24

AH24

AF24

AF25

AG26

AG27

AE24

AE23

AH26

AH27

AF28

AE26

AD29

AD28

AG28

AF27

AD25

AD26

AE4

K5

DQ2

G12

K3

DQ3

AG2

AD2

AD1

AF1

DQ4

K2

DQ5

G11

DQ6

V8

DQ7

AF2

J5

DQ8

AE7

G6

DQ9

AF6

H10

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

AJ7

AD18

AD13

AC21

AE15

AF15

AD17

AC16

AC15

AC14

AD16

AE17

AG4

AH4

AE20

AD23

AC1

AC27

AC29

AB28

AB29

AC28

AE1

AG5

AJ9

AG7

AD8

AE6

BA1

CAS#

CB0

AH6

AJ6

CB1

CB2

AG8

AJ8

CB3

CB4

AG10

AD11

AH7

AF8

CB5

CB6

CB7

CKE0

AD10

AE10

AH12

AJ12

AE13

AD14

AJ11

AF12

AF14

AG14

AF18

AE18

AG20

AJ21

AJ18

AH18

AJ20

CKE1

CS0#

AE3

CS1#

AJ5

DDR_VREF

DDRCRES0

DDRIMPCRES

DDRRES1

DDRRES2

DDRSLWCRES

DM0

AF9

AG13

AF19

AH23

AJ26

AE29

AG16

AJ4

DM1

DM2

AE9

DM3

AJ13

AJ19

AE21

AG25

AH13

AG19

AJ23

AJ25

DM4

DM5

DM6

52

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 4 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

DM7

DM8

AE27

AH15

AD5

DQ39

DQ40

AH20

AJ22

AG22

A16

B15

A15

A14

F14

D12

A12

C14

C16

D18

B18

F17

G14

E12

A11

D14

D16

E18

A18

E17

E13

B12

D11

D15

B17

C19

A20

G16

F13

C12

C11

E15

C17

D19

A19

F16

V21

DQS7#

DQS_8#

GPIO0/U0_RXD

REFCLK-

REFCLK+

RSTIN#

SCD0

AF29

AF16

AB26

G15

H15

AB6

AB21

AC24

AA23

AB22

Y2

DQ0

DQ41

GPIO1/U0_TXD

GPIO2/U0_CTS#

GPIO3/U0_RTS#

GPIO4/U1_RXD

GPIO5/U1_TXD

GPIO6/U1_CTS#

GPIO7/U1_RTS#

HPI#

AB27

AA21

AA22

AC26

AC25

AB23

AB24

AA8

PE_ICOMPI

PE_RCOMPO

PE_VCCBG

PE_VSSBG

PE0RN0

PE0RN1

PE0RN2

PE0RN3

PE0RN4

PE0RN5

PE0RN6

PE0RN7

PE0RP0

PE0RP1

PE0RP2

PE0RP3

PE0RP4

PE0RP5

PE0RP6

PE0RP7

PE0TN0

PE0TN1

PE0TN2

PE0TN3

PE0TN4

PE0TN5

PE0TN6

PE0TN7

PE0TP0

PE0TP1

PE0TP2

PE0TP3

PE0TP4

PE0TP5

PE0TP6

PE0TP7

POE#

SCD1/SDTA

SCL0

SCL1/SCLK

TCK

M_CK0

M_CK1

M_CK2

M_CK0#

M_CK1#

M_CK2#

M_RST#

MA0

AJ16

AJ14

AH17

AJ17

AJ15

AG17

AH3

TDI

Y6

TDO

AB3

AB4

AA5

U12

V13

W10

W12

Y9

TMS

TRST#

VCC13

VCC15E

VCC15

AC13

AE12

AC12

AF11

AG11

AH10

AH9

MA1

MA2

Y11

Y13

A13

C13

C18

E14

E16

J14

MA3

MA4

MA5

MA6

MA7

AD7

MA8

AJ10

AC9

AC18

AC8

AF5

MA9

MA10

J16

MA11

J10

MA12

J12

MA13

AD22

Y5

K9

N/C0

K10

K11

K13

L10

N/C1 (A/B step only)

N/C2

W6

T1

N/C3

Y8

N/C4

AA2

L12

N/C5

AA4

L18

N/C6

AB1

M9

N/C7

K6

M13

Document Number: 274066-004US

August 2005

53

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 5 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

ODT0

ODT1

AC22

AB20

AA26

AA25

N14

N16

N18

P9

PWE#

PWRDELAY

PWRGD

RAS#

Y21

W1

VCC15

VCC33

VCCPLL1

VCCPLL2

VCCPLL3

VCCPLL4

VCCPLL5

VSS

M15

M17

N10

N12

J24

J27

K17

K19

K21

L5

PCE0#

PCE1#

VCC15

VCC25

AA7

AC19

AA20

AB11

AB13

AB15

AB17

AB19

AC10

AC20

AD6

AD12

AD19

AD24

AF4

VCC25

VCC33

P11

P15

P17

P19

R10

R12

R14

R18

T9

L20

L25

M3

M6

M21

M27

N20

N23

N26

P21

R3

T11

AF10

AF13

AF17

AF20

AF22

AF26

AH11

AH16

AJ3

T13

T15

T17

T19

U10

U14

U16

U18

V9

R6

R20

R24

R27

U7

C1

U20

U26

V24

V3

V11

V15

V17

V19

W14

W16

W18

Y1

C6

C9

C21

C24

W5

C29

W20

Y26

AA24

M19

M11

L15

R15

P13

A3

D4

D26

E9

Y15

Y17

Y19

AB7

AB9

F3

F6

F21

G10

G23

54

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 6 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

VCC25

VSS

AA10

AA12

AA14

AA16

AA18

B8

VCC33

VSS

H5

H26

J3

VSS

A10

A17

A27

B2

J18

J20

G28

H2

B5

N7

B11

B13

B14

B16

B19

B20

B22

B25

B28

C15

D7

N9

H14

H16

H25

H27

H28

H29

J6

N11

N13

N15

N17

N19

N21

P2

J9

P5

J11

J13

J15

J17

J19

J21

K4

P10

P12

P16

P18

P20

P25

P28

R9

D10

D13

D17

D20

D23

D29

E2

K7

K12

K14

K16

K18

K20

K23

K26

L2

R11

R13

R17

R19

T2

E5

E8

E10

E11

E19

E22

E25

F8

T5

T7

T10

T12

T14

T16

T18

T20

T25

T28

U4

L9

F9

L11

L13

L14

L16

L17

L19

L21

L28

F10

F12

F15

F18

F24

F27

G4

U9

Document Number: 274066-004US

August 2005

55

Intel® 80332 I/O Processor Datasheet

Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 7 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

VSS

G7

G8

VSS

M10

M14

VSS

U11

U13

U15

U17

U19

U23

AH8

AH14

AH19

AH22

AH25

AH28

AJ27

M18

M12

K15

R16

P14

AD20

U27

U28

T24

G13

G17

G20

G26

V6

M16

VSS

M20

VSS

M24

VSS

N4

VSS

AB14

AB16

AB18

AB25

AC2

VSS

V10

V12

V14

V16

V18

V20

V27

W2

VSS

AC3

VSS

AC4

VSS

AC5

VSSA1

VSSA2

VSSA3

VSSA4

VSSA5

WE#

AC6

W9

AC7

W11

W13

W15

W17

W19

W25

W28

Y3

AC11

AC17

AC23

AD3

XINT0#

XINT1#

XINT2#

XINT3#

XINT4#

XINT5#

XINT6#

XINT7#

AD9

AD15

AD21

AD27

AE2

R23

W3

Y4

V5

Y7

AE5

V4

Y10

Y12

Y14

Y16

Y18

Y20

Y23

AA3

AA6

AA9

AA11

AA13

AA15

AA17

AE8

V2

AE11

AE14

AE16

AE19

AE22

AE25

AE28

AF7

AG1

AG3

AG6

AG9

AG12

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Package Information

Table 20.

829-Lead Package - Alphabetical Signal Listings (Sheet 8 of 8)

Signal

Ball

Signal

Ball

Signal

Ball

VSS

AA19

AA27

AB2

VSS

AG15

AG18

AG21

AG24

AG29

AH2

AB5

AB8

AB10

AB12

AH5

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Intel® 80332 I/O Processor Datasheet

Package Information

3.2

Package Thermal Specifications

See Intel^®80332 I/O Processor Thermal Design Guidelines Application Note (273981).

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Electrical Specifications

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Table 21.

Absolute Maximum Ratings

NOTE: This data sheet contains information on

products in the design phase of

Parameter

Maximum Rating

Storage Temperature

–55° C to +125°C

0°C to +95°C

development. Do not finalize a design with

this information. Revised information will

be published when the product becomes

available. The specifications are subject to

change without notice. Contact your local

Intel representative before finalizing a

design.

Case Temperature Under Bias

Supply Voltage V

wrt. V

–0.5 V to +4.1 V

–0.5 V to +3.2 V

–0.5 V to +2.1 V

CC33

CC25

CC15

CC13

SS

Voltage on Any Ball wrt. V

–0.5 V to V

+ 0.5 V

CCP

SS

WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage.

These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended

exposure beyond the Operating Conditions may affect device reliability.

Table 22.

Operating Conditions

Symbol

Parameter

Minimum

Maximum

Units

Notes

V

3.3 V PCI/PCI-X Supply Voltage

2.5 V/1.8V DDR/DDR-II Supply Voltage

1.5 V IOP Core Supply Voltage

1.35 V Intel XScale^®core Supply

Voltage

3.0

3.6

V

+/- 10%

+/-8%, 5%¹

+/- 5%¹

CC33

2.3/1.7

1.425

1.282

2.7/1.9

1.575

1.418

CC25/18

CC15

+/- 5%

CC13

V

PLL Supply Voltage

V

CC15

V

CCPLL1-5

CC15

DDR_VREF Memory I/O Reference Voltage

PE_VCCBG 2.5v PCI Express VCC Band Gap

0.49V

0.51 V

CC25/18

2.375

2.625

+/- 5%

Input Clock Frequency

100 -300ppm 100 +300ppm

MHz 100 MHz

nominal

REFCLK

T

Case Temperature Under Bias

0

95

°C

C

1. +/- 3% DC; additional +/- 2% for AC transients. Under no circumstance may the supply voltage go past the AC

min/max window. The supply voltage window may go outside the DC min/max window for transient events.

4.2

V

Pin Requirements

CCPLL

The V_CCPLL[1-5]balls for the Phase Lock Loop (PLL) circuit must each have filters, and be

connected to the appropriate VSSA ball. See the Intel^®80332 I/O Processor Design Guide for

specific recommendations.

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59

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.3

Targeted DC Specifications

Table 23.

DC Characteristics

Symbol

Parameter

Minimum

Maximum

Units

Notes

V

Input Low Voltage (DDR SDRAM)

Input High Voltage (DDR SDRAM)

Input Low Voltage (DDR-II SDRAM)

Input High Voltage (DDR-II SDRAM)

Input Low Voltage (Misc.)

-0.3

DDR_VREF - 0.18

V

(1, 2)

(1, 3)

(4, 5)

IL1

V

DDR_VREF + 0.18

V

+ 0.3

IH1

CC25

V

-0.2

DDR_VREF - 0.125

V

IL2

V

DDR_VREF + 0.125

V

+ 0.2

V

IH2

CC25

CC33

V

-0.3

2.0

0.8

V

IL2

V

Input High Voltage (Misc.)

V

+ 0.3

V

IH2

V

Input Low Voltage (PCI-X)

-0.5

0.35 V

V

IL3

CC33

V

Input High Voltage (PCI-X/PCI)

Input Low Voltage (PCI)

0.5 V

V + 0.5

CC33

V

IH3

CC33

V

-0.5

0.3 V

V

IL5

CC33

V

Output Low Voltage (Misc.)

Output High Voltage (Misc.)

Output Low Voltage (DDR SDRAM)

Output High Voltage (DDR SDRAM)

Output Low Voltage (DDR-II SDRAM)

Output High Voltage (DDR-II SDRAM)

Output Low Voltage (PCI-X)

Output High Voltage (PCI-X)

Input pin Capacitance

0.4

V

I

= 6 mA

OL

OL2

OH2

V

2.4

1.95

1.314

V

I

= -2 mA

OH

V

0.35

V

I

= 12.5 mA (1, 2)

= -12.5 mA (1, 2)

OL1

OH1

OL

V

I

OH

V

0.414

V

I

= 20.7mA (3)

= -18mA (3)

OL2

OH2

OL

V

I

OH

V

0.1 V

V

I

OL

= 1500 µA

= -500 µA

(6)

OL3

OH3

CC33

V

0.9 V

V

I

OH

CC33

C

8

pF

nH

IN

C

L

PCI clock pin Capacitance

(6)

CLK

Ball Inductance

15

(1, 2, 6)

NOTES:

1. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#,M_CK[2:0], M_CK[2:0]#,

DQ[63:0], DQS[8:0] and CB[7:0].

2. For 2.5 V DDR SDRAM support.

3. For 1.8 V DDR-II SDRAM support.

4. Miscellaneous signals include all signals that are not PCI-X or SDRAM signals.

5. Includes PCI-X Express Auxiliary signals; PWRGD

6. Ensured by design.

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Electrical Specifications

Table 24.

I_CCCharacteristics

Symbol

Parameter

Typ

Max

Units

Notes

I

Input Leakage Current for each signal

except TCK, TMS, TRST#, TDI

± 2

µA

0 ≤ V ≤ V (4)

LI1

IN

CC

I

Input Leakage Current for TCK, TMS,

TRST#, TDI

-140

-250

µA

A

V

= 0.45 V (1, 4)

(1, 2)

LI2

IN

I

Active

Power Supply Current - PCI-X interfaces

CC33

(Power Supply)

Both at 66 MHz

Both at 100 MHz

Both at 133 MHz

1.33

1.20

1.04

I

Active

Power Supply Current - DDR

0.580

0.487

4.7

A

(1, 2)

CC25

(Power Supply)

I

Active

Power Supply Current - DDR-II

CC18

(Power Supply)

I

Active

Power Supply Current - IOP/Bridge core

Power Supply Current - Intel XScale^®

CC15

(Power Supply)

I

Active

CC13

(Power Supply) core

800 MHz

667 MHz

500 MHz

0.453

0.411

0.358

A

I

Active

Thermal Current - PCI-X interfaces

(1, 3)

CC33

(Thermal)

Both at 66 MHz

Both at 100 MHz

Both at 133 MHz

1.08

1.00

0.914

A

I

Active

(Thermal)

Thermal Current - DDR

0.295

0.255

3.8

(1, 3)

CC25

Active

(Thermal)

Thermal Current - DDR-II

A

CC18

Active

(Thermal)

Thermal Current - IOP/Bridge core

Thermal Current - Intel XScale^®core

CC15

Active

CC13

(Thermal)

800 MHz

667 MHz

500 MHz

0.430

0.390

0.340

A

NOTES:

1. Measured with device operating and outputs loaded to the test condition in Figure 14 “AC Test Load for All

Signals Except PCI and DDR SDRAM” on page 76.

2. I Active (Power Supply) value is provided for selecting the system power supply. This is based on the

CC

worst case data patterns and skew material at the following worst case voltages: V

= 3.63 V, V

=

CC33

CC25

2.7 V, V

= 1.9v, V

= 1.575 V, V

= 1.41 V.

cc18

CC15

CC13

3. I Active (Thermal) value is provided for selecting the system thermal design power (TDP). This is based

CC

on the following typical voltages: V

= 3.3 V, V

= 2.5 V, V

= 1.8v, V

= 1.5 V, V

= 1.35 V.

CC33

CC25

cc18

CC15

CC13

4. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

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Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.4

Targeted AC Specifications

4.4.1

Clock Signal Timings

Table 25.

PCI Clock Timings

PCI-X 133

Parameter

PCI-X 100

PCI-X 66

PCI 66

PCI 33

Symbol

Units Notes

Min. Max Min. Max Min. Max Min. Max Min. Max

T

PCI clock Frequency

PCI clock Cycle Time - Avg.

Absolute Minimum

100

7.5

133

10

66

10

100

15

50

15

14.8

6

66

20

33

15

14.8

6

66

30

16

30

29.7

11

33

60

MHz

ns

1

F1

T

C1

7.375

9.875

ns

3, 4

T

PCI clock High Time

PCI clock Low Time

PCI clock Slew Rate

3

ns

CH1

T

6

11

ns

CL1

SR1

1.5

4

1.5

4

1.5

4

1.5

4

1

4

V/ns

2

PCI Spread Spectrum Requirements

f

PCI clock modulation

frequency

30

33

30

33

30

33

30

-1

33

0

KHz

%

mod

f

PCI clock frequency spread

-1

0

-1

0

-1

0

spread

NOTES:

1. Clock frequency may not change beyond spread-spectrum limits except while RSTIN# is asserted or PWRGD deasserted.

2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.

3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.

4. Clock jitter class 2, per PCI-X Electrical and Mechanical Rev 2.0a specification

Table 26.

DDR Clock Timings

DDR-II 400

DDR333

Symbol

Parameter

Units Notes

Minimum

Maximum

Minimum

Maximum

T

DDR SDRAM clock Frequency

DDR SDRAM clock Cycle Time

DDR SDRAM clock High Time

DDR SDRAM clock LowTime

DDR SDRAM clock Period Stability

200

167

MHz

ns

F2

5.0

6.0/7.5⁽¹⁾

2.7/3.37⁽¹⁾

C2

T

2.15

ns

CH2

T

ns

CL2

CS2

350

100

350

100

ps

T

DDR SDRAM clock skew for any differential

ps

skew2

clock pair (M_CK[2:0] - M_CK[2:0]#)

T

DDR SDRAM clock skew for any clock pair and

-285

285

-285

285

ps

2

skew3

any system memory strobe (M_CK - DQS).

NOTES:

1. CL = 2.5/2.0.

2. This specification applies for writes only; that is, when the 80331 is driving the strobes as well as the clocks. Refer to the

JEDEC specification for an explanation of strobe to clock timing for DDR reads.

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Electrical Specifications

Table 27.

PCI Express Clock Timings

Symbol

Parameter

Minimum

Nominal

Maximum

Units Notes

T

PCI Express clock frequency

PCI Express clock cycle time

Cycle to Cycle Jitter

-300ppm

10

100

+300ppm

10.2

200

MHz

ns

1

2

F2

T

C2

T

ps

CCJ

Clock duty cycle

45

55

%

T

REFCLK rise time across

600mV

300

600

ps

3

rise

T

REFCLK fall time across

600mV

300

600

ps

fall

Rise-Fall matching

Cross point at 1V

20

%

V

3,4

0.51

0.85

0.76

Rising edge ringback

Falling edge ringback

0.35

NOTES:

1. Spread spectrum clocking is allowed with the following three requirements;

a.All device timings must be met including jitter, skew, min/max clock period. Output rise/fall timing MUST meet the existing

non-spread spectrum specifications.

b.All non-spread Host and PCI functionality must be maintained in the spread spectum mode (includes all power management

functions).

c.The minimum clock period cannot be violated. The preferred method is to adjust the spread technique to allow for

modulation above the nominal frequency. This technique is often called "down-spreading".

2. Measured at crossing point.

3. Measured from Vol=0.2v to Voh=0.8v.

4. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).

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Electrical Specifications

4.4.2

DDR/DDR-II SDRAM Interface Signal Timings

Table 28.

DDR SDRAM Signal Timings

Symbol

Parameter

Minimum Max. Units Notes

T

DQ, CB and DM write output valid time before DQS.

DQ, CB and DM write output valid time after DQS.

2.68

2.62

ns

(4)

VB1

VA1

VB3

Address and Command write output valid before M_CK rising

edge.

(4,9)

T

Address and Command write output valid after M_CK rising

edge.

2.62

0.35

ns

(4,9)

(6)

VA3

VB4

VA4

DQ, CB and DM read input valid time before DQS rising or

falling edges.

DQ, CB and DM read input valid time after DQS rising or

falling edges.

(6)

T

CS[1:0]# control valid before M_CK rising edge.

CS[1:0]# control valid after M_CK rising edge.

DQS write preamble duration.

2.62

ns

(4)

(7)

VB5

VA5

VB6

4.50

(nominal)

T

DQS write postamble duration.

3.00

ns

(7)

VA6

(nominal)

NOTES:

1. See Figure 7 “Output Timing Measurement Waveforms” on page 72.

2. See Figure 8 “Input Timing Measurement Waveforms” on page 73.

3. Clock to output valid times are specified with a 0 pF loading.

4. See Figure 11 “DDR SDRAM Write Timings” on page 74.

5. See Figure 13 “DQS falling edge output access time to M_CK rising edge.

6. See Figure 12 “DDR SDRAM Read Timings” on page 74. Data to strobe read setup and data from strobe

read hold minimum requirements specified are determined with the DQS delay programmed for a 90

degree phase shift.

7. See Figure 13 “Write PreAmble/PostAmble Durations” on page 75.

8. See Figure 15 “AC Test Load for DDR SDRAM Signals” on page 76.

9. Address/Command pin group; RAS#, CAS#, WE#, MA[12:0], BA[1:0].

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Electrical Specifications

Table 29.

DDR-II SDRAM Signal Timings

Symbol

Parameter

Mini

Max

Units

Notes

T

DQ, CB and DM write output valid time before DQS crossing.

DQ, CB and DM write output valid time after DQS crossing.

2.12

ns

4

VB1

T

VA1

VB3

T

Address and Command write output valid before M_CK rising

edge

T

Address and Command write output valid after M_CK rising

edge

2.12

0.35

ns

4,8

6

VA3

VB4

T

DQ, CB and DM read input valid time before DQS rising or

falling edges

T

DQ, CB and DM read input valid time after DQS rising or falling

edges

6

VA4

T

CS[1:0]# control valid before M_CK rising edge.

CS[1:0]# control valid after M_CK rising edge.

DQS write preamble duration.

2.12

ns

4

9

VB5

T

VA5

VB6

T

3.75

(nom)

T

DQS write postamble duration.

2.50

ns

9

VA6

(nom)

NOTES:

1. See Figure 7 “Output Timing Measurement Waveforms” on page 72.

2. See Figure 8 “Input Timing Measurement Waveforms” on page 73.

3. Clock to output valid times are specified with a 0 pF loading.

4. See Figure 11 “DDR SDRAM Write Timings” on page 74.

5. See Figure 13 “DQS falling edge output access time to M_CK rising edge.

6. See Figure 12 “DDR SDRAM Read Timings” on page 74. Data to strobe read setup and data from strobe

read hold minimum requirements specified are determined with the DQS delay programmed for a 90

degree phase shift.

7. See Figure 15 “AC Test Load for DDR SDRAM Signals” on page 76.

8. Address/Command pin group: RAS#, CAS#, WE#, MA[12:0], BA[1:0], ODT[1:0].

9. See Figure 13 “Write PreAmble/PostAmble Durations” on page 75.

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Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.4.3

Peripheral Bus Interface Signal Timings

Table 30.

Peripheral Bus Signal Timings

Symbol

Parameter

Min Max

Units

Notes

T

Output Valid Delay from M_CK

Output Float Delay from M_CK

Input Setup to M_CK

1

5

ns

(1, 3)

(2)

OV1

T

OF

IS1

IH1

T

4.5

2

T

Input Hold from M_CK

(2)

T

ALE High time

15

ns

AH1

T

ALE high to address Valid

ALE low to address invalid

Address valid to ALE low

ALE low to POE# low

ALE low to PWE# low

PWE# high to Data Invalid

Data valid to PWE# high

ALE low to PCE[1:0]# low

0

AV1

T

15

AH2

T

15

0

AS1

T

AO1

T

15

60

15

AW1

T

AH3

T

AS2

T

AC1

NOTES:

1. See Figure 7 “Output Timing Measurement Waveforms” on page 72.

2. See Figure 8 “Input Timing Measurement Waveforms” on page 73.

3. See Figure 14 “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 76.

4. See Table 32, AC Measurement Conditions.

5. All timing referenced to M_CK is for functional testing, for the cases where M_CK * N = IBCLK.

6. PBI Clock is internal only; 66 MHz with 266 MHz internal bus.

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Electrical Specifications

Table 31.

PCI Signal Timings

PCI-X 133

PCI-X 100

PCI-X 66

PCI 66

PCI 33

Symbol

Parameter

Units Notes

Min. Max Min. Max Min. Max Min. Max

T

Clock to Output Valid

Delay for bused

signals

0.7

3.8

7

0.7

3.8

7

1

6

2

11

12

28

ns

(1,2,3)

OV1

Clock to Output Valid

Delay for point to point

signals

0.7

2

6

2

OV2

T

Clock to Output Float

Delay

14

ns

(1,7)

(3,4,8)

(3,4)

OF

IS1

IS2

T

Input Setup to clock

for bused signals

1.2

1.7

3

5

7

T

Input Setup to clock

for point to point

signals

10,

12

Input Hold time from

clock

0.5

1

0.5

1

0

1

0

1

ns

(4)

IH1

T

Reset Active Time

ms

ns

RST

T

Reset Active to output

float delay

40

50

40

50

40

50

40

50

(5,6)

RF

IS3

IH2

IS4

T

REQ64# to Reset

setup time

10

0

10

0

10

0

10

0

clocks

ns

T

Reset to REQ64# hold

time

PCI-X initialization

pattern to Reset setup

time

10

clocks

T

Reset to PCI-X

initialization pattern

hold time

0

50

0

50

ns

IH3

NOTES:

1. See the timing measurement conditions in; Figure 7 “Output Timing Measurement Waveforms” on page 72.

2. See Figure 16 “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 76, Figure 17 “PCI/PCI-X

TOV(max) Falling Edge AC Test Load” on page 77, and Figure 18 “PCI/PCI-X TOV(min) AC Test Load” on

page 77.

3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused.

4. See the timing measurement conditions in Figure 8 “Input Timing Measurement Waveforms” on page 73.

5. RST# is asserted and deasserted asynchronously with respect to CLK.

6. All output drivers must be floated when RST# is active.

7. For purposes of Active/Float timing measurements, the HI-Z or ‘off’ state is defined to be when the total

current delivered through the component pin is less than or equal to the leakage current specification.

8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time.

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Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.4.4

I²C/SMBus Interface Signal Timings

Table 32.

I²C/SMBus Signal Timings

Std. Mode

Fast Mode

Symbol

Parameter

Units Notes

Min.

Max

Min.

Max

400

F

T

SCL Clock Frequency

0

100

0

KHz

SCL

Bus Free Time Between STOP and START

Condition

4.7

1.3

µs

(1)

BUF

T

Hold Time (repeated) START Condition

SCL Clock Low Time

4

4.7

4

0.6

1.3

0.6

0

µs

ns

µs

(1, 3)

(1, 2)

(1)

HDSTA

T

LOW

HIGH

T

SCL Clock High Time

T

Setup Time for a Repeated START Condition

Data Hold Time

4.7

0

SUSTA

HDDAT

SUDAT

T

3.45

0.9

(1)

Data Setup Time

250

100

(1)

T

SCL and SDA Rise Time

SCL and SDA Fall Time

1000 20+0.1C

300 20+0.1C

0.6

300

(1, 4)

(1)

SR

b

T

SF

T

Setup Time for STOP Condition

4

SUSTO

NOTES:

1. See Figure 9 “I2C/SMBus Interface Signal Timings” on page 73.

2. Not tested.

3. After this period, the first clock pulse is generated.

4. C = the total capacitance of one bus line, in pF.

b

5. Std Mode I²C signal timings apply for SMBus timing.

4.4.5

UART Interface Signal Timings

Table 33.

UART Signal Timings

Std. Mode

Symbol

Parameter

Units

Notes

Min.

Max

60

T

Ux_TXD output delay from M_CK rising edge

Ux_RXD data setup time (to M_CK rising edge).

Ux_RXD data hold time (to M_CK rising edge).

Ux_CTS setup time (to M_CK rising edge).

Ux_CTS hold time (to M_CK rising edge).

Ux_RTS setup time (to M_CK rising edge).

Ux_RTS hold time (to M_CK rising edge).

ns

1

XD1

T

50

60

RXS1

RXH1

T

CTS1

CTH1

T

RTS1

RTH1

NOTES:

1. See Figure 10 “UART Transmitter Receiver Timing” on page 73.

1. All timings referenced to M_CK for functional testing, is for cases where M_CK * N = IBCLK.

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Electrical Specifications

4.4.6

PCI Express Differential Transmitter (Tx) Output Specifications

Table 34.

PCI Express Tx Output Specifications

Symbol

UI

Parameter

Min. Nom. Max

Units

Notes

Unit Interval

400

ps

V

1

2

3

4

V

Differential output voltage

Driver Rise/Fall Time

.800

0.2

1.200

0.4

DIFFp-p

T

, T

UI

rise fall

TX-CM-AC

V

AC Common Mode

20

mV

Common Mode Active to Sleep mode delta

-50

+50

TX-CM-DC

delta

RL-Diff

RL-CM

Differential Return Loss

15

6

dB

Ω

5

6

7

TX

Common Mode Return Loss

DC Differential Output Impedance

D+/D- impedance matching

Z

90

-5

100

110

+5

TX-OUT-DC

Z

%

TX-Match-DC

L

Lane to Lane Skew at Tx

Total Output Jitter.

500

ps

UI

8

SKEW-TX

J

0.35

9

TOTAL

T

Minimum Transmitter eye opening.

Short Circuit Current

0.65

-100

0

UI

10

11

12

Deye

TX-SHORT

I

100

20

mA

mV

V

Sleep mode Voltage Output

0

TX-IDLE

NOTES:

1. +/- 300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated with

this value. This UI spec is a ‘before transmission’ specification and represents the nominal time of each bit

transmission or width.

2. Peak-Peak differential voltage. V

= 2 * V

Specified at the package pins into a 100 ohm test

DIFFp-p

DMAx.

load as shown in Figure 19 “Transmitter Test Load (100 ohm differential load)” on page 77. Max level set

by maximum single ended voltage after a reflection from an open. This value is for the first bit after a

transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB (+/- .5db)

less as measured differentially peak to peak than the specified value.

3. 20-80% at Transmitter. Slower rise/fall times are better.

4. Peak common mode value. |V + V |/2 - V

D+

D-

CM-DC(avg).

5. 50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than or

equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50

MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The reference

impedance for return loss measurements is 100 Ohms for differential return loss and 25 ohms for common

mode (i.e., as measured by a Vector Network Analyzer with 100 ohm differential probes). Note this is

based on a nominal PCI Express interconnect differential characteristic impedance of 100 ohms.

Applicable during active (L0) and Align states only.

6. DC Differential Mode Impedance 100 ohm +/-10% tolerance. All devices shall employ on-chip adaptive

impedance matching circuits to ensure the best possible termination/Zout for its Transmitters (as well as

Receivers).

7. DC impedance matching between two lanes of a port.

8. Between any two lanes within a single Transmitter.

9. Clock source PPM mismatch is in addition to this value. Measured over 250 UI.

10.See Figure 20 “Transmitter Eye Diagram” on page 78.

11.Between any voltage from max supply to gnd with power on or off.

12.Squelch condition. Both signals brought to V

CM-DC-|VD+ - VD-|.

Document Number: 274066-004US

August 2005

69

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.4.7

PCI Express Differential Receiver (Rx) Input Specifications

Table 35.

PCI Express Rx Input Specifications

Symbol

Parameter

Differential input voltage

Min. Nom. Max

Units

Notes

V

0.175

1.200

0.65

100

V

UI

1

2

DIFFp-p

J

Total Output Jitter.

TOTAL

CM-AC

V

AC Common Mode

mV

UI

3

T

Receiver eye opening.

Differential Return Loss

Common Mode Return Loss

DC Differential Output Impedance

D+/D- impedance matching

Squelch detect threshold

AC coupled

0.35

15

6

4

Reye

RL-Diff

RL-CM

dB

Ω

5

RX

TX

5

Z

90

-5

100

110

+5

6

RX-OUT-DC

RX-Match-DC

RX-SQUELCH

Z

%

7

V

75

400

175

mV

pF

UI

8

Cin

9

RX

SKEW-RX

L

Lane to Lane Skew at Rx

20

10

NOTES:

1. Peak-Peak differential voltage. V

= 2 * V

Measured at the package pins of the receiver. See

DIFFp-p

RMAx.

Figure 20 “Transmitter Eye Diagram” on page 78.

2. Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver device. A

receiver must therefore tolerate any additional jitter generated by the package to the die.

3. Peak common mode value. |V + V |/2 - V .

D+

D-

CM-DC(avg)

4. See Figure 21 “Receiver Eye Opening (Differential)” on page 78.

5. 50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than or

equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50

MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The reference

impedance for return loss measurements is 100 ohms for differential return loss and 25 ohms for common

mode (i.e., as measured by a Vector Network Analyzer with 100 ohm differential probes). Note this is

based on a nominal PCI Express interconnect differential characteristic impedance of 100 ohms.

Applicable during active (L0) and Align states only.

6. DC Differential Mode Impedance 100 ohm +/-10% tolerance.

7. DC impedance matching between two lanes of a port.

8. Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will indicate a

squelch condition.

9. All receivers shall be AC coupled to the media.

10.Lane skew at the Receiver that must be tolerated.

70

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.4.8

Boundary Scan Test Signal Timings

Table 36.

Boundary Scan Test Signal Timings

Symbol

Parameter

TCK Frequency

Min.

0

Max

Units

MHz

ns

Notes

T

0.5T

BSF

F

T

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

15

Measured at 1.5 V (1).

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

(4)

BSCH

T

ns

BSCL

BSCR

T

5

ns

T

ns

BSCF

BSIS1

T

Input Setup to TCK — TDI,

TMS

3

5

ns

T

Input Hold from TCK — TDI,

ns

(4)

BSIH1

TMS

T

TDO Valid Delay

TDO Float Delay

5

15

ns

Relative to falling edge of TCK (2, 3).

Relative to falling edge of TCK (2, 5).

BSOV1

T

OF1

NOTES:

1. Not tested.

2. Outputs precharged to V

.

CC5

3. See Figure 7 “Output Timing Measurement Waveforms” on page 72.

4. See Figure 8 “Input Timing Measurement Waveforms” on page 73.

5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See

Figure 7 “Output Timing Measurement Waveforms” on page 72.

Document Number: 274066-004US

August 2005

71

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.5

AC Timing Waveforms

Figure 6.

Clock Timing Measurement Waveforms

T_CR

T_CF

V_tch

V_ih(min)

V_test

V_il(max)

V_tcl

T_CH

T_CL

T_C

Figure 7.

Output Timing Measurement Waveforms

V_th

CLK

V_test

V_tl

T_OV

V_tfall

OUTPUT

DELAY FALL

T_OV

OUTPUT

DELAY RISE

V_trise

T_OF

OUTPUT

FLOAT

72

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Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

Figure 8.

Figure 9.

Figure 10.

Input Timing Measurement Waveforms

V_th

CLK

V_test

V_tl

V_th

V_tl

T_IH

T_IS

INPUT

V_test

Valid

V_test

V_max

I²C/SMBus Interface Signal Timings

SDA

T

LOW

BUF

T

SP

HDSTA

SR

SF

SCL

T

SUSTO

HDSTA

T

HDDAT

HIGH

SUDAT

SUSTA

Stop

Start

Stop

Repeated

Start

UART Transmitter Receiver Timing

M_CK

T_XD1

Ux_TXD

T

T_RXS1

RXH1

Ux_RXD

Document Number: 274066-004US

August 2005

73

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

Figure 11.

DDR SDRAM Write Timings

T

VA3

ADDR/CTRL

T

VB3

T

VA5

CS[1:0]#

T

VB5

M_CK

DQS

DQS#

T

VA1

T

VB1

DQ

Figure 12.

DDR SDRAM Read Timings

DQS

T

VB4

T

VA4

DQ

74

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

Figure 13.

Write PreAmble/PostAmble Durations

T

DQS

VB6

T

DQS

VA6

Document Number: 274066-004US

August 2005

75

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

4.6

AC Test Conditions

Table 37.

AC Measurement Conditions

Symbol

PCI-X

0.6 V

PCI

DDR / DDR-II

DDR-II

PBI

Units

V

0.6 V

2.0 / 1.15

0.5 / 0.2

1.25 / 0.90

1.5 / 0.97

1.0

1.15

0.2

2.0

0.8

1.5

1.2

1.0

V

th

CC33

V

0.25 V

0.2 V

0.4 V

tl

CC33

V

0.4 V

0.90

0.97

1.0

V

test

V

0.285 V

0.615 V

0.285 V

0.615 V

V

trise

CC33

V

tfall

V

0.4 V

CC33

V

max

CC33

Slew Rate

(1)

1.5

V/nS

1. Input signal slew rate is measured between V and V .

il

ih

Figure 14.

AC Test Load for All Signals Except PCI and DDR SDRAM

Test

Point

Output

50pF

Figure 15.

AC Test Load for DDR SDRAM Signals

1.25V

25Ω

Test

Point

25Ω

Output

30pF

Figure 16.

PCI/PCI-X T_OV(max)Rising Edge AC Test Load

Test

Point

Output

25Ω

10pF

76

August 2005

Document Number: 274066-004US

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

Figure 17.

PCI/PCI-X T_OV(max)Falling Edge AC Test Load

V

CC33

Test

Point

25Ω

Output

10pF

Figure 18.

PCI/PCI-X T_OV(min)AC Test Load

V

CC33

Test

Point

1KΩ

Output

1KΩ

10pF

Figure 19.

Transmitter Test Load (100 ohm differential load)

D+

D-

50

Ohm

+

V

cm-dc

-

Document Number: 274066-004US

August 2005

77

Intel® 80332 I/O Processor Datasheet

Electrical Specifications

Figure 20.

Transmitter Eye Diagram

UI

T_Deye

V

Dmax

Dmin

Note: Transmitter V_diffp-p= 2 * V_Dmax

Figure 21.

Receiver Eye Opening (Differential)

UI

T

V_Rmin

V_Rmax

Reye

Note: Transmitter V_diffp-p= 2 * V_Rmax

78

August 2005

Document Number: 274066-004US


型号：	QG80332M800
厂家：	INTEL
描述：	Microprocessor, 800MHz, CMOS, PBGA829, 37.50 X 37.50 MM, 1.27 MM PITCH, LEAD FREE, FCBGA-829 时钟外围集成电路
文件：	总78页 (文件大小：1276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

QG80332M800 [INTEL]

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