RB80526PY733256 [INTEL]
Microprocessor, 32-Bit, 733MHz, CMOS, CPGA370, FCPGA-370;
| 型号： | RB80526PY733256 |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, 32-Bit, 733MHz, CMOS, CPGA370, FCPGA-370 |
| 文件： | 总80页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pentium® III Processor for the PGA370
Socket at 500 MHz to 1 GHz
Datasheet
Product Features
■ Available in 1B GHz, 933, 866, 800EB, 733, ■ Dynamic execution micro architecture
667, 600EB, and 533EB MHz for a
■ Intel Processor Serial Number
■ Power Management capabilities
■ System Management mode
■ Multiple low-power states
133 MHz system bus
■ Available in 900, 850, 800, 750, 700, 650,
600E, 550E, and 500E MHz for a 100 MHz
system bus
■ Optimized for 32-bit applications running on
■ System bus frequency at 100 MHz and
133 MHz ("E" denotes support for Advanced
Transfer Cache and Advanced system
buffering; "B" denotes support for a
advanced 32-bit operating systems
■ Flip Chip Pin Grid Array (FC-PGA) packaging
technology; FC-PGA processors deliver high
performance with improved handling protection
and socketability
133MHz system bus where both bus
frequencies are available for order per each
given core frequency; See Table 1 for a
summary of features for each line item.)
■ Integrated high performance 16 KB instruction
and 16 KB data, nonblocking, level one cache
■ Available in versions that incorporate
256 KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC))
■ Dual Independent Bus (DIB) architecture:
Separate dedicated external System Bus and
dedicated internal high-speed cache bus
■ 256 KB Integrated Full Speed level two cache
allows for low latency on read/store operations
■ Double Quad Word Wide(256bit) cache data
bus provides extremely high throughput on
read/store operations.
■ 8-way cache associativity provides improved
cache hit rate on reads/store operations.
■ Internet Streaming SIMD Extensions for
■ Error-correcting code for System Bus data
enhanced video, sound and 3D performance
■ Enables systems which are scaleable for up to
■ Binary compatible with applications running
on previous members of the Intel
microprocessor line
two processors
The Pentium® III processor is designed for high-performance desktops and for workstations and
servers. It is binary compatible with previous Intel Architecture processors. The Pentium III processor
provides great performance for applications running on advanced operating systems such as Windows*
98, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel processors—
the dynamic execution, Dual Independent Bus architecture plus Intel MMX™ technology and Internet
Streaming SIMD Extentions— bringing a new level of performance for systems buyers. The Pentium®
III processor is scaleable to two processors in a multiprocessor system and extends the power of the
Pentium® II processor with performance headroom for business media, communication and internet
capabilities. Systems based on
Pentium® III processors also
include the latest features to
simplify system management and
lower the cost of ownership for
large and small business
environments. The Pentium® III
processor offers great performance
for today’s and tomorrow’s
applications.
FC-PGA370 Package
October 2000
Order Number: 245264-007
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifcations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Contents
1.0
Introduction.........................................................................................................................7
1.1
Terminology...........................................................................................................8
1.1.1 Package and Processor Terminology ......................................................8
1.1.2 Processor Naming Convention.................................................................9
Related Documents.............................................................................................10
1.2
2.0
Electrical Specifications....................................................................................................11
2.1
2.2
Processor System Bus and VREF........................................................................11
Clock Control and Low Power States..................................................................12
2.2.1 Normal State—State 1 ...........................................................................13
2.2.2 AutoHALT Powerdown State—State 2...................................................13
2.2.3 Stop-Grant State—State 3 .....................................................................13
2.2.4 HALT/Grant Snoop State—State 4 ........................................................14
2.2.5 Sleep State—State 5..............................................................................14
2.2.6 Deep Sleep State—State 6 ....................................................................14
2.2.7 Clock Control..........................................................................................15
Power and Ground Pins ......................................................................................15
2.3.1 Phase Lock Loop (PLL) Power...............................................................16
Decoupling Guidelines .......................................................................................16
2.4.1 Processor VCCCORE Decoupling............................................................16
2.4.2 Processor System Bus AGTL+ Decoupling............................................16
Processor System Bus Clock and Processor Clocking.......................................17
2.5.1 Mixing Processors of Differrent Frequencies .........................................17
Voltage Identification...........................................................................................17
Processor System Bus Unused Pins...................................................................19
Processor System Bus Signal Groups ................................................................19
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................20
2.8.2 System Bus Frequency Select Signals (BSEL[1:0])...............................21
Test Access Port (TAP) Connection....................................................................22
Maximum Ratings................................................................................................22
Processor DC Specifications...............................................................................23
AGTL+ System Bus Specifications .....................................................................29
System Bus AC Specifications............................................................................29
2.13.1 I/O Buffer Model .....................................................................................30
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
Signal Quality Specifications............................................................................................38
3.1
3.2
3.3
BCLK and PICCLK Signal Quality Specifications and Measurement Guidelines38
AGTL+ Signal Quality Specifications and Measurement Guidelines ..................39
AGTL+ Signal Quality Specifications and Measurement Guidelines ..................40
3.3.1 Overshoot/Undershoot Guidelines .........................................................40
3.3.2 Overshoot/Undershoot Magnitude .........................................................41
3.3.3 Overshoot/Undershoot Pulse Duration...................................................41
3.3.4 Activity Factor.........................................................................................41
3.3.5 Reading Overshoot/Undershoot Specification Tables............................42
3.3.6 Determining if a System meets the Overshoot/Undershoot
Specifications .........................................................................................43
Datasheet
3
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.4
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........45
3.4.1 Overshoot/Undershoot Guidelines.........................................................46
3.4.2 Ringback Specification...........................................................................46
3.4.3 Settling Limit Guideline ..........................................................................46
4.0
5.0
Thermal Specifications and Design Considerations.........................................................47
4.1
Thermal Specifications........................................................................................47
4.1.1 Thermal Diode........................................................................................48
Mechanical Specifications...............................................................................................50
5.1
5.2
5.3
FC-PGA Mechanical Specifications ....................................................................50
Processor Markings ............................................................................................52
Processor Signal Listing......................................................................................52
6.0
Boxed Processor Specifications.......................................................................................64
6.1
Mechanical Specifications for the Boxed Intel® Pentium® III Processor..............64
6.1.1 Boxed Processor Thermal Cooling Solution Dimensions.......................64
6.1.2 Boxed Processor Heatsink Weight.........................................................67
6.1.3 Boxed Processor Thermal Cooling Solution Clip ...................................67
Thermal Specifications........................................................................................68
6.2.1 Boxed Processor Cooling Requirements ...............................................68
Electrical Requirements for the Boxed Intel® Pentium® III Processor.................69
6.3.1 Fan Heatsink Power Supply...................................................................69
6.2
6.3
7.0
Processor Signal Description...........................................................................................71
7.1
7.2
Alphabetical Signals Reference ..........................................................................71
Signal Summaries...............................................................................................78
4
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
List of Figures
1
Second Level (L2) Cache Implementation ...........................................................7
AGTL+ Bus Topology in a Uniprocessor Configuration ......................................12
AGTL+ Bus Topology in a Dual-Processor Configuration...................................12
Stop Clock State Machine...................................................................................12
Processor VccCMOS Package Routing..............................................................16
BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........21
BCLK, PICCLK, and TCK Generic Clock Waveform...........................................35
System Bus Valid Delay Timings ........................................................................35
System Bus Setup and Hold Timings..................................................................35
System Bus Reset and Configuration Timings....................................................36
Power-On Reset and Configuration Timings.......................................................36
Test Timings (TAP Connection) ..........................................................................37
Test Reset Timings .............................................................................................37
BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................39
Low to High AGTL+ Receiver Ringback Tolerance.............................................40
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform.......................45
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1 ..................45
Processor Functional Die Layout for CPUIDs up to and including 0683h...........48
Package Dimensions...........................................................................................50
Top Side Processor Markings .............................................................................52
Intel® Pentium® III Processor Pinout..................................................................53
Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket.........64
Space Requirements for the Boxed Processor to 850MHz.................................65
Space Requirements for the Boxed Processor from 866 to 933MHz..................65
Space Requirements for the Boxed Processor at 1 GHz....................................66
Dimensions of Mechanical Step Feature in Heatsink Base.................................66
Dimensions of Notches in Heatsink Base ..........................................................67
Clip Keepout Requirements for the PGA370 (Top View) ....................................68
Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor
Fan Heatsinks in the PGA370 Socket.................................................................69
Boxed Processor Fan Heatsink Power Cable Connector Description.................70
Motherboard Power Header Placement Relative to the Boxed
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Intel® Pentium® III Processor.............................................................................70
Datasheet
5
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
List of Tables
1
Processor Identification.........................................................................................9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Voltage Identification Definition ..........................................................................18
System Bus Signal Groups ................................................................................20
Frequency Select Truth Table for BSEL[1:0] ......................................................21
Absolute Maximum Ratings ................................................................................22
Voltage and Current Specifications.....................................................................24
AGTL+ Signal Groups DC Specifications ...........................................................28
Non-AGTL+ Signal Group DC Specifications .....................................................28
Processor AGTL+ Bus Specifications ................................................................29
System Bus AC Specifications (Clock) ...............................................................30
Valid System Bus to Core Frequency Ratios .....................................................31
System Bus AC Specifications (AGTL+ Signal Group).......................................32
System Bus AC Specifications (CMOS Signal Group) .......................................32
System Bus AC Specifications (Reset Conditions) ............................................33
System Bus AC Specifications (APIC Clock and APIC I/O)................................33
System Bus AC Specifications (TAP Connection) ..............................................34
BCLK/PICCLK Signal Quality Specifications for Simulation
at the Processor Pins..........................................................................................38
18
AGTL+ Signal Groups Ringback Tolerance Specifications
at the Processor Pins..........................................................................................39
Example Platform Information.............................................................................42
100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance
19
20
at Processor Pins................................................................................................43
133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance ....................44
33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance
21
22
at Processor Pins................................................................................................44
23
Signal Ringback Specifications for Non-AGTL+ Signal Simulation
at the Processor Pins .........................................................................................46
Intel® Pentium® III Processor for the PGA370 Socket Thermal Design Power .47
Thermal Diode Parameters.................................................................................49
Thermal Diode Interface......................................................................................49
Intel® Pentium® III Processor Package Dimensions..........................................51
Processor Die Loading Parameters ....................................................................51
Signal Listing in Order by Signal Name ..............................................................54
Signal Listing in Order by Pin Number................................................................59
Boxed Processor Fan Heatsink Spatial Dimensions...........................................66
Fan Heatsink Power and Signal Specifications...................................................70
Signal Description ...............................................................................................71
Output Signals.....................................................................................................78
Input Signals .......................................................................................................79
Input/Output Signals (Single Driver)....................................................................80
Input/Output Signals (Multiple Driver) .................................................................80
24
25
26
27
28
29
30
31
32
33
34
35
36
37
6
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.0
Introduction
The Intel® Pentium® III processor for the PGA370 socket is the next member of the P6 family, in
the Intel IA-32 processor line and hereafter will be referred to as the “Pentium III processor”, or
simply “the processor”. The processor uses the same core and offers the same performance as the
Intel® Pentium® III processor for the SC242 connector, but utilizes a new package technology
called flip-chip pin grid array, or FC-PGA. This package utilizes the same 370-pin zero insertion
force socket (PGA370) used by the Intel® CeleronTM processor. Thermal solutions are attached
directly to the back of the processor core package without the use of a thermal plate or heat
spreader.
The Pentium III processor, like its predecessors in the P6 family of processors, implements a
Dynamic Execution microarchitecture—a unique combination of multiple branch prediction, data
flow analysis, and speculative execution. This enables these processors to deliver higher
performance than the Intel Pentium processor, while maintaining binary compatibility with all
previous Intel Architecture processors. The processor also executes Intel® MMXTM technology
instructions for enhanced media and communication performance just as it’s predecessor, the
Intel Pentium III processor. Additionally, Pentium III processor executes Streaming SIMD (single-
instruction, multiple data) Extensions for enhanced floating point and 3-D application
performance. The concept of processor identification, via CPUID, is extended in the processor
family with the addition of a processor serial number. Refer to the Intel® Processor Serial Number
application note for more detailed information. The processor utilizes multiple low-power states
such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times.
The processor includes an integrated on-die, 256 KB, 8-way set associative level-two (L2) cache.
The L2 cache implements the new Advanced Transfer Cache Architecture with a 256-bit wide bus.
The processor also includes a 16 KB level one (L1) instruction cache and 16 KB L1 data cache.
These cache arrays run at the full speed of the processor core. As with the Intel Pentium III
processor for the SC242 connector, the Pentium III processor for the PGA370 socket has a
dedicated L2 cache bus, thus maintaining the dual independent bus architecture to deliver high bus
bandwidth and performance (see Figure 1). Memory is cacheable for 64 GB of addressable
memory space, allowing significant headroom for desktop systems. Refer to the Specification
Update document for this processor to determine the cacheability and cache configuration options
for a specific processor. The Specification Update document can be requested at your nearest Intel
sales office.
The processor utilizes the same multiprocessing system bus technology as the Pentium II processor.
This allows for a higher level of performance for both uni-processor and two-way multiprocessor
systems. The system bus uses a variant of GTL+ signaling technology called Assisted Gunning
Transceiver Logic (AGTL+) signaling technology.
Figure 1. Second Level (L2) Cache Implementation
L2
Processor
Core
Processor
Core
Tag
L2
Intel® Pentium® III SECC2 Processor
Intel® Pentium® III FC-PGA Processor
Datasheet
7
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.1
Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
chipset components), and other bus agents.
1.1.1
Package and Processor Terminology
The following terms are used often in this document and are explained here for clarification:
• Pentium® III processor - The entire product including all internal components.
• PGA370 socket - 370-pin Zero Insertion Force (ZIF) socket which a FC-PGA or PPGA
packaged processor plugs into.
• FC-PGA - Flip Chip Pin Grid Array. The package technology used on Pentium III processors
for the PGA370 socket.
• Advanced Transfer Cache (ATC) - New L2 cache architecture unique to the 0.18 micron
Pentium III processors. ATC consists of microarchitectural improvements that provide a higher
data bandwidth interface into the processor core that is completely scaleable with the
processor core frequency.
• Keep-out zone - The area on or near a FC-PGA packaged processor that system designs can
not utilize.
• Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.
• OLGA - Organic Land Grid Array. The package technology for the core used in S.E.C.C. 2
processors that permits attachment of the heatsink directly to the die.
• PPGA - Plastic Pin Grid Array. The package technology used for Intel® CeleronTM
processors that utilize the PGA370 socket.
• Processor - For this document, the term processor is the generic form of the Pentium III
processor for the PGA370 socket in the FC-PGA package.
• Processor core - The processor’s execution engine.
• S.E.C.C. - The processor package technology called “Single Edge Contact Cartridge”. Used
with Intel® Pentium® II processors.
• S.E.C.C. 2 - The follow-on to S.E.C.C. processor package technology. This differs from its
predecessor in that it has no extended thermal plate, thus reducing thermal resistance. Used
with Intel® Pentium® III processors and latest versions of the Intel® Pentium® II processor.
• SC242 - The 242-contact slot connector (previously referred to as slot 1 connector) that the
S.E.C.C. and S.E.C.C. 2 plug into, just as the Intel® Pentium® Pro processor uses socket 8.
The cache and L2 cache are an industry designated names.
8
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.1.2
Processor Naming Convention
A letter(s) is added to certain processors (e.g., 600EB MHz) when the core freqnency alone may
not uniquely identify the processor. Below is a summary of what each letter means as well as a
table listing all the available Pentium III processors for the PGA370 socket.
“B” — 133 MHz System Bus Frequency
“E” — Processor with "Advanced Transfer Cache" (CPUID 068xh and greater)
Table 1. Processor Identification
System Bus
Frequency
(MHz)
Core Frequency
(MHz)
L2 Cache Size
(Kbytes)
L2 Cache
Type
1
Processor
CPUID
2
500E
533EB
550E
600E
600EB
650
500
533
550
600
600
650
667
700
733
750
800
800
850
866
900
933
1000
100
133
100
100
133
100
133
100
133
100
100
133
100
133
100
133
133
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
ATC
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
667
700
733
750
800
800EB
850
866
900
933
1B GHz
NOTES:
®
1. Refer to the Pentium III Processor Specification Update for the exact CPUID for each processor.
2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.
With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same
frequency as the processor core and has enhanced buffering.
Datasheet
9
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.2
Related Documents
The reader of this specification should also be familiar with material and concepts presented in the
following documents 1,2
:
Document
Intel Order Number
®
AP-485, Intel Processor Identification and the CPUID Instruction
241618
243330
243334
245087
245085
245125
243193
243190
243191
243192
244001
243565
243502
244452
245264
244453
243658
243748
244410
245025
290675
290631
298021
245338
®
AP-585, Pentium II Processor GTL+ Guidelines
AP-589, Design for EMI
®
AP-905, Pentium III Processor Thermal Design Guidelines
®
AP-907, Pentium III Processor Power Distribution Guidelines
®
AP-909, Intel Processor Serial Number
®
Intel Architecture Software Developer's Manual
Volume I: Basic Architecture
Volume II: Instruction Set Reference
Volume III: System Programming Guide
P6 Family of Processors Hardware Developer’s Manual
IA-32 Processors and Related Products 1999 Databook
®
Pentium II Processor Developer’s Manual
®
Pentium III Processor Datasheet for SECC2
®
Pentium III Processor Datasheet for PGA370
®
Pentium III Processor Specification Update
®
TM
Intel Celeron Processor Datasheet
®
TM
Intel Celeron Processor Specificiation Update
370-Pin Socket (PGA370) Design Guidelines
PGA370 Heat Sink Cooling in MicroATX Chassis
®
Intel 810E Chipset Platform Design Guide
®
Intel 820 Chipset Platform Design Guide
®
Intel 840 Chipset Platform Design Guide
CK98 Clock Synthesizer/Driver Design Guidelines
®
3
Intel 810E Chipset Clock Synthesizer/Driver Specification
VRM 8.4 DC-DC Converter Design Guidelines
245335
Pentium III Processor for the PGA370 Socket I/O Buffer Models, XTK/XNS*
3
Format
®
3
Pentium Pro Processor BIOS Writer’s Guide
®
3
Extensions to the Pentium Pro Processor BIOS Writer’s Guide
Pentium III Thermal/Mechanical Solution Functional Guidelines
245241
1. Unless otherwise noted, this reference material can be found on the Intel Developer’s Website
located at http://developer.intel.com.
2. For a complete listing of Intel® Pentium® III processor reference material, please refer to the
Intel Developer’s Website at http://developer.intel.com/design/PentiumIII/.
3. This material is available through an Intel field sales representative.
10
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.0
Electrical Specifications
2.1
Processor System Bus and V
REF
The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Intel® Pentium® Pro processor system bus specification is similar to the GTL specification, but
was enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Intel® Pentium® II
Processor Developer’s Manual.
Current P6 family processors vary from the Intel Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Intel® CeleronTM, Pentium II,
and Pentium III processors are actively driven to VCCCORE for one clock cycle after the low to high
transition to improve rise times. These signals should still be considered open-drain and require
termination to a supply that provides the high signal level. Because this specification is different
from the standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and
other documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both
be used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by
the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by the motherboard
to the PGA370 socket for the processor core. Local VREF copies should also be generated on the
motherboard for all other devices on the AGTL+ system bus. Termination (usually a resistor at each
end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections
on the transmission line. The processor contains on-die termination resistors that provide
termination for one end of the AGTL+ bus, except for RESET#. These specifications assume
another resistor at the end of each signal trace to ensure adequate signal quality for the AGTL+
signals and provide backwards compatibility for the Intel Celeron processor; see Table 9 for the
bus termination voltage specifications for AGTL+. Refer to the Intel® Pentium® II Processor
Developer’s Manual for the AGTL+ bus specification. Solutions exist for single-ended termination
as well, though this implementation changes system design and eliminate backwards compatibility
for Intel Celeron processors in the PPGA package. Single-ended termination designs must still
provide an AGTL+ termination resistor on the motherboard for the RESET# signal. Figure 2 is a
schematic representation of the AGTL+ bus topology for the Pentium III processors in the PGA370
socket. Figure 3 is a schematic representation of the AGTL+ bus topoplogy in a dual-processor
configuration with Pentium III processors in the PGA370 socket.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus including trace lengths is highly recommended when designing a system with a heavily
loaded AGTL+ bus, especially for systems using a single set of termination resistors (i.e., those on
the processor die). Such designs will not match the solution space allowed for by installation of
termination resistors on the baseboard.
Datasheet
11
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 2. AGTL+ Bus Topology in a Uniprocessor Configuration
Processor
Chipset
Figure 3. AGTL+ Bus Topology in a Dual-Processor Configuration
Processor
Chipset
Processor
2.2
Clock Control and Low Power States
Processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 4 for a visual representation of the processor low power states.
Figure 4. Stop Clock State Machine
HALT Instruction and
HALT Bus Cycle Generated
1. Normal State
2. Auto HALT Power Down State
BCLK running.
INIT#, BINIT#, INTR,
SMI#, RESET#
Normal execution.
, NMI
Snoops and interrupts allowed.
STPCLK# Asserted
STPCLK# De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
and Stop-Grant State
entered from
AutoHALT
Snoop Event Occurs
Snoop Event Serviced
3. Stop Grant State
4. HALT/Grant Snoop State
BCLK running.
BCLK running.
Snoops and interrupts allowed.
Service snoops to caches.
SLP#
SLP#
Asserted
De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK
BCLK
Input
Input
Stopped
Restarted
6. Deep Sleep State
BCLK stopped.
No snoops or interrupts allowed.
PCB757a
12
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide.
2.2.1
2.2.2
Normal State—State 1
This is the normal operating state for the processor.
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI,
INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT
state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT
state.
2.2.3
Stop-Grant State—State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# and FLUSH# are not serviced during the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant
state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the
system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) occurs with the
assertion of the SLP# signal.
While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] are latched by the processor, and only
serviced when the processor returns to the Normal state. Only one occurrence of each event is
recognized and serviced upon return to the Normal state.
Datasheet
13
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.2.4
HALT/Grant Snoop State—State 4
The processor responds to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor stays in this state until the snoop on the system bus has been serviced
(whether by the processor or another agent on the system bus). After the snoop is serviced, the
processor returns to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5
Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK input be held low during the Deep Sleep State. Stopping
of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
14
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.2.7
Clock Control
BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does
not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance
into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Power and Ground Pins
The operating voltage of the Pentium III processor for the PGA370 socket is the same for the core
and the L2 cache; VCCCORE. There are four pins defined on the package for voltage identification
(VID). These pins specify the voltage required by the processor core. These have been added to
cleanly support voltage specification variations on current and future processors.
For clean on-chip power and voltage reference distribution, the Pentium III processors in the
FC-PGA package have 75 VCCCORE, 8 VREF, 15 VTT, and 77 VSS (ground) inputs. VCC
inputs supply the processor core, including the on-die L2 cache. VTT inputs (1.5V) are uCseOdREto
provide an AGTL+ termination voltage to the processor, and the VREF inputs are used as the
AGTL+ reference voltage for the processor. Note that not all VTT inputs must be connected to the
VTT supply. Refer to Section 5.3 for more details.
On the motherboard, all VCCCORE pins must be connected to a voltage island (an island is a portion
of a power plane that has been divided, or an entire plane). In addition, the motherboard must
implement the VTT pins as a voltage island or large trace. Similarly, all GND pins must be
connected to a system ground plane.
Three additional power related pins exist on a processors utilizing the PGA370 socket. They are
VCC1.5, VCC2.5 and VCC
.
CMOS
The VCCCMOS pin provides the CMOS voltage for the pull-up resistors required on the system
platform. A 2.5V source must be provided to the VCC2.5 pin and a 1.5V source must be provided
to the VCC1.5 pin. The source for VCC1.5 must be the same as the one supplying VTT. The processor
routes the compatible CMOS voltage source (1.5V or 2.5V) through the package and out to the
VCCCMOS output pin. Processors based on 0.25 micron technology (e.g., the Intel Celeron
processor) utilize 2.5V CMOS buffers. Processors based on 0.18 micron technology (e.g., the
Pentium III processor for the PGA370 socket) utilize 1.5V CMOS buffers. The signal VCORE
DET
can be used by hardware on the motherboard to detect which CMOS voltage the processor requires.
A VCOREDET connected to VSS within the processor indicates a 1.5V requirement on VCC
.
CMOS
Refer to Figure 5.
Each power signal must meet the specifications stated in Table 6 on page 24.
Datasheet
15
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 5. Processor VCCCMOS Package Routing
2.5V
2.5V Supply
VCC CMOS
Intel®
Pentium® III
Processor
0.1 uF
1.5V
1.5V Supply
CMOS Signals
CMOS
Pullups
*ICH or
Other Logic
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel® Pentium® III processor
for the PGA370 socket.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter specifications.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 6. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1
2.4.2
Processor VCCCORE Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 6) while maintaining the required tolerances (also defined in Table 6). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
Processor System Bus AGTL+ Decoupling
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ bus operation. See the AGTL+ buffer specification in the Intel® Pentium® II
Processor Developer's Manual for more information. Also, refer to the appropriate platform design
guide for recommended capacitor component placement.
16
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+
system bus timing parameters are specified with respect to the rising edge of the BCLK input. See
the P6 Family of Processors Hardware Developer's Manual for further details.
2.5.1
Mixing Processors of Differrent Frequencies
In two-way MP (multi-processor) systems, mixing processors of different internal clock
frequencies is not supported and has not been validated. Pentium III processors do not support a
variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not
valid. However, mixing processors of the same frequency but of different steppings is supported.
Details on support for mixed steppings is provided in the Pentium® III Processor Specification
Update.
Note: Not all Pentium III processors for the PGA370 socket are validated for use in dual processor (DP)
systems. Refer to the Pentium® III Processor Specification Update to determine which processors
are DP capable.
2.6
Voltage Identification
There are four voltage identification pins on the PGA370 socket. These pins can be used to support
automatic selection of VCCCORE voltages. These pins are not signals, but are either an open circuit
or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage
required by the processor core. The VID pins are needed to cleanly support voltage specification
variations on current and future processors. VID[3:0] are defined in Table 2. A ‘1’ in this table
refers to an open pin and a ‘0’ refers to a short to ground. The voltage regulator or VRM must
supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future processors, the range of values in bold in Table 2
should be supported. A smaller range will risk the ability of the system to migrate to a higher
performance processor and/or maintain compatibility with current processors.
Datasheet
17
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 2. Voltage Identification Definition 1, 2
VID3
VID2
VID1
VID0
Vcc
CORE
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.30
1.35
1.40
1.45
1.50
1.55
3
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
3
3
3
3
3
3
3
3
3
No Core
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on baseboard.
®
®
®
TM
3. To ensure a system is ready for the Intel Pentium III and Intel Celeron processors, the values in BOLD
in Table 2 should be supported.
Note that the ‘1111’ (all opens) ID can be used to detect the absence of a processor core in a given
socket as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see Section 7.0).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[3:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-
DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10 kΩ may be used to connect the VID signals to the
converter input. Note that no changes have been made to the physical connector or pin definitions
between the Intel-enabled VRM 8.2 and VRM 8.4 specifications. Intel requires that designs
utilize VRM 8.4 specifications to meet the Pentium III processor requirements.
18
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to VCCCORE, VREF, VSS, VTT, or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Section 5.3 for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
VCCCMOS even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (VIH) and logic low (VIL) requirements are met. See Table 8 for DC
specifications of non-AGTL+ signals.
Unused AGTL+ inputs must be properly terminated to VTT on PGA370 socket motherboards
which support the Intel Celeron and the Pentium III processors. For designs that intend to only
support the Pentium III processor, unused AGTL+ inputs will be terminated by the processor’s on-
die termination resistors and thus do not need to be terminated on the motherboard. However,
RESET# must always be terminated on the motherboard as the Pentium III processor for the
PGA370 socket does not provide on-die termination of this AGTL+ input.
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
VCCCMOS and meet VIH requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Pentium III processor for the
PGA370 socket includes on-die termination. Motherboard designs that also support
Intel Celeron processors in the PPGA package will need to provide AGTL+ termination on
the system motherboard as well. Platform designs that support dual processor configurations
will need to provide AGTL+ termination, via a termination package, in any socket not
populated with a processor.
AGTL+ input signals have differential input buffers which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) are only 1.5 V tolerant and must be pulled up to VCCCMOS. The CMOS, APIC, and
TAP outputs are open drain and must be pulled high to VCCCMOS. This ensures correct operation
for current Intel Pentium III and Intel Celeron processors.
The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0
for a description of these signals.
Datasheet
19
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 3. System Bus Signal Groups 1
Group Name
Signals
7
6
AGTL+ Input
BPRI#, BR1# , DEFER#, RESET# , RS[2:0]#, RSP#, TRDY#
PRDY#
AGTL+ Output
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0# , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
AGTL+ I/O
2
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
3
CMOS Input
4
CMOS Input
PWRGOOD
3
CMOS Output
FERR#, IERR#, THERMTRIP#
System Bus
Clock
BCLK
4
4
APIC Clock
PICCLK
3
APIC I/O
PICD[1:0]
3
TAP Input
TCK, TDI, TMS, TRST#
TDO
3
TAP Output
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
5
8
Power/Other
THERMDN, THERMDP, RTTCTRL , VCORE
, VID[3:0], VCC , VCC , VCC ,
DET 1.5 2.5 CMOS
VCC
, V
, VSS, VTT, Reserved
CORE
REF
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for Vcc
4. These signals are 2.5 V tolerant.
(1.5 V for the Pentium III processor) operation.
CMOS
5. VCC
is the power supply for the processor core and is described in Section 2.6.
CORE
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate V
VSS is system ground.
on the motherboard.
REF
VCC , VCC , Vcc
are described in Section 2.3.
1.5 2.5 CMOS
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
®
7. This signal is not supported by all processors. Refer to the Pentium III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pulldown resistor value.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP
signals are synchronous to TCK.
20
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.8.2
System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency. Table 2.9 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
determined by the processor(s), chipset, and clock synthesizer. All system bus agents must operate
at the same frequency. The Pentium III processor for the PGA370 socket operates at 100 MHz
or 133 MHz system bus frequency; 66 MHz system bus operation is not supported. Individual
processors will only operate at their specified front side bus (FSB) frequency, either 100 MHz or
133 MHz, not both.
On motherboards that support operation at either 100 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in Figure 6. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
Figure 6. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
3.3V
3.3V
Processor
1
K
1 K
Ω
Ω
BSEL0
BSEL1
10
K
Ω
Note
1
Clock Driver
10
K
10
K
Ω
Ω
Note
2
Note
2
Chipset
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implementation details.
Table 4. Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Frequency
0
0
1
1
0
1
0
1
66 MHz (unsupported)
100 MHz
Reserved
133 MHz
Datasheet
21
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be the first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect the rest of the chain
unless one of the other components is capable of accepting a 1.5V input. Similar considerations
must be made for TCK, TMS, and TRST# signals.
In a two-way MP system design, be cautious when including an empty PGA370 socket in the scan
chain. All sockets in the scan chain must have a processor installed to complete the chain or the
system must support a method to bypass the empty socket; PGA370 termination packages should
not connect TDI to TDO in order to avoid placing the TDO pull-up resistor in parallel.
2.10
Maximum Ratings
Table 5 contains processor stress ratings only. Functional operation at the absolute maximum and
minimum is not implied nor guaranteed. The processor should not receive a clock while subjected
to these conditions. Functional operating conditions are given in the AC and DC tables in
Section 2.11 through Section 2.13. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist damage from
static electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
–40
85
°C
VCC
and
Processor core voltage and termination
supply voltage with respect to VSS
CORE
–0.5
2.1
V
VTT
Vin
Vin
AGTL+ buffer input voltage
VTT - 2.18
VTT - 2.18
2.18
2.18
V
V
1, 2
AGTL
CMOS buffer DC input voltage with respect
to VSS
1.5
1, 2, 3
CMOS
CMOS buffer DC input voltage with respect
to VSS
Vin
2.5
-0.58
3.18
V
4
CMOS
IVID
Max VID pin current
5
5
mA
mA
ICPUPRES#
Max CPUPRES# pin current
NOTES:
1. Input voltage can never exceed VSS + 2.18 volts.
2. Input voltage can never go below VTT - 2.18 volts.
3. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups
only.
4. Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD only.
22
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the PGA370 socket pins (bottom side
of the motherboard). See Section 7.0 for the processor signal descriptions and Section 5.3 for the
signal listings.
Most of the signals on the processor system bus are in the AGTL+ signal group. These signals are
specified to be terminated to 1.5V. The DC specifications for these signals are listed in Table 7 on
page 28.
To allow connection with other devices, the clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 8 on
page 28.
Table 6 through Table 9 list the DC specifications for the Pentium III processor for the PGA370
socket. Specifications are valid only while meeting specifications for junction temperature, clock
frequency, and input voltages. Care should be taken to read all notes associated with each
parameter.
Datasheet
23
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 6. Voltage and Current Specifications 1, 2 (Sheet 1 of 3)
Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Core
Freq
CPUID
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
0x681
0x683
0x686
1.60
1.60
n/a
3,4
3,4
500E
MHz
1.65
1.65
n/a
3,4
3,4
533EB
MHz
1.60
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
1.65
1.65
1.70
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
550E
MHz
600E
MHz
600EB
MHz
650
MHz
VCC
CORE
VCC for Processor Core
V
667
MHz
700
MHz
733
MHz
750
MHz
800
MHz
800EB
MHz
24
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 6. Voltage and Current Specifications 1, 2 (Sheet 2 of 3)
Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Core
Freq
CPUID
0x681
0x683
0x686
0x681
0x683
0x686
1.65
1.65
1.70
1.65
1.65
1.70
3,4
3,4
3,4
3,4
3,4
3,4
850
MHz
866
MHz
V
VCC
VCC for Processor Core
CORE
900
MHz
0x686
1.70
3,4
0x683
0x686
0x683
0x686
0x686
1.65
1.70
1.70
1.70
1.76
3,4
3,4
3,4
3,4
933
MHz
1B
GHz
3,4, 20
Static AGTL+ bus
termination voltage
, 5, 16
, 5
VTT, VCC
VTT, VCC
1.455
1.365
-2%
1.50
1.50
1.545
1.635
+2%
V
V
V
V
1.5 ±3%
1.5
Transient AGTL+ bus
termination voltage
1.5 ±9%
±2%, 7
1.5
AGTL+ input reference
voltage
2/3
VTT
V
REF
CLKREF input
reference voltage
VCLKREF
1.169
1.25
1.331
±6.5%, 15
Baseboard Processor core voltage
–0.080
0.001
0.040
0.100
6
VCC
Tolerance,
Static
static tolerance level at
the PGA370 socket
pins
CORE
V
V
20, 21
Baseboard Processor core voltage
–0.130
–0.110
0.025
0.080
0.080
0.130
6
VCC
Tolerance,
Transient
transient tolerance level
at the PGA370 socket
pins
CORE
19
20, 21
500E MHz
10.0
10.6
11.0
12.0
12.0
13.0
13.3
14.0
14.6
15.0
16.0
16.0
16.2
16.3
17.0
17.7
19.4
20.8
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9, 20
533EB MHz
550E MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
850 MHz
866 MHz
900 MHz
933 MHz
1B GHz
ICC
ICC for processor core
A
CORE
1B GHz
ICC
ICC for Vcc
250
mA
CMOS
CMOS
Datasheet
25
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 6. Voltage and Current Specifications 1, 2 (Sheet 3 of 3)
Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
CLKREF voltage
supply current
ICLKREF
IVTT
60
2.7
2.5
2.5
2.2
240
8
µA
A
Termination voltage
supply current
10
ICC Stop-Grant for
processor core
ISGnt
A
8, 11
8
ICC Sleep for processor
core
ISLP
A
ICC Deep Sleep for
processor core
IDSLP
A
Power supply current
slew rate
dICCCORE/dt
A/µs 12, 13, 14
Termination current
slew rate
12, 13, See
A/µs
dI TT/dt
v
Table 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
®
TM
®
TM
Intel Celeron processor, see the Intel Celeron Processor Datasheet.
3. Vcc and Icc supply the processor core and the on-die L2 cache.
CORE
CORE
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. VTT and Vcc must be held to 1.5V ±9% while the AGTL+ bus is active. It is required that VTT and Vcc be
1.5
1.5
held to 1.5V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the soldered-side of the motherboard. VCC
must return to within the static
CORE
voltage specification within 100 µs after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelines for further details.
7. V
should be generated from VTT by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
REF
®
®
Intel Pentium II Processor Developer’s Manual for more details on V
.
REF
8. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of Vcc
CORE
(Vcc
). In this case, the maximum current level for the regulator, Icc
, can be reduced from
CORE_TYP
CORE_REG
the specified maximum current Icc
and is calculated by the equation:
CORE _MAX
Icc
= Icc
× (Vcc
- Vcc
) / Vcc
CORE_STATIC_TOLERANCE CORE_TYP
CORE_REG
CORE_MAX
CORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see Section 2.1).
11.The current specified is also for AutoHALT state.
12.Maximum values are specified by design/characterization at nominal Vcc
.
CORE
13.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5V or 3.3V supply. VTT should not be used due to risk of AGTL+ switching noise coupling to this analog
reference.
16.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables above.
17.FMB - Flexible Motherboard recommendation
18.These values are estimates based on preliminary simulation.
26
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
19.This specification applies to PGA370 processors operating at frequencies of 933MHz or higher.
20.This specification only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70V, however
the processor should be supplied 1.76V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM.
21.This specification applies only to 1B GHz S-spec #: SL4WM. This value is 60mV offset from the standard
specification and more at the Minimum specification. These tolerances are measured from a 1.70V base,
while Vcc supplied is 1.76V.
Datasheet
27
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 7. AGTL+ Signal Groups DC Specifications 1
Symbol
Parameter
Min
Max
- 0.200
Unit
Notes
VIL
Input Low Voltage
Input High Voltage
Buffer On Resistance
–0.150
V
V
V
Ω
6
REF
VIH
V
+ 0.200
VTT
2, 3, 6
5
REF
Ron
16.67
Leakage Current for inputs,
outputs, and I/O
IL
±100
µA
4
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All inputs, outputs, and I/O pins must comply with the signal quality specifications in Section 3.0.
3. Minimum and maximum VTT are given in Table 9 on page 29.
4. (0 ≤ VIN ≤ 1.5 V +3%) and (0≤VOUT≤1.5V+3%).
5. Refer to the processor I/O Buffer Models for I/V characteristics.
6. Steady state input voltage must not be above VSS + 1.65V or below VTT - 1.65V.
Table 8. Non-AGTL+ Signal Group DC Specifications 1
Symbol
Parameter
Input Low Voltage
Min
Max
- 0.200
REF
Unit
Notes
VIL
VIL
–0.150
-0.58
V
V
V
V
V
V
9
1.5
2.5
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
0.700
VTT
5, 8
6, 9
5, 8
2
VIH
VIH
V
+ 0.200
REF
1.5
2.000
3.18
2.5
VOL
VOH
0.400
7, 9, All outputs are
open-drain
Output High Voltage
VTT
V
IOL
ILI
Output Low Current
9
mA
µA
µA
Input Leakage Current
Output Leakage Current
±100
±100
3, 6
4, 7
ILO
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentum III processors at all frequencies.
2. Parameter measured at 9 mA (for use with TTL inputs).
3. (0 ≤ VIN ≤ 2.5V +5%).
4. (0 ≤ VOUT ≤ 2.5V +5%).
5. For BCLK specifications, refer to Table 17 on page 38.
6. (0 ≤ VIN ≤ 1.5V +3%).
7. (0 ≤ VOUT ≤ 1.5V +3%).
8. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD.
9. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD.
28
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT. These termination resistors are placed electrically between the ends of the signal
traces and the VTT voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called VREF. Refer to the appropriate platform design guide for more information
Table 9 below lists the nominal specification for the AGTL+ termination voltage (VTT). The
AGTL+ reference voltage (VREF) is generated on the system motherboard and should be set to 2/3
VTT for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the Intel® Pentium® II Processor Developer's Manual and AP-585,
Intel® Pentium® II Processor AGTL+ Guidelines.
Table 9. Processor AGTL+ Bus Specifications 1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
VTT
Bus Termination Voltage
Termination Resistor
1.50
V
Ω
V
3
4
5
On-die R
40
130
TT
V
Bus Reference Voltage
0.950
2/3 VTT
1.05
REF
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Pentium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. VTT and Vcc must be held to 1.5V ±9%. It is required that VTT and Vcc be held to 1.5V ±3% while the
1.5
1.5
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die R is determined by the resistor value measured by the RTTCTRL signal pin. See
TT
Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific
chipset/processor combination.
5. V
V
is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
decoupling on the motherboard.
REF
REF
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 10 through Table 16 list the AC specifications associated with the processor system bus.
These specifications are broken into the following categories: Table 10 contains the system bus
clock specifications, Table 12 contains the AGTL+ specifications, Table 13 contains the CMOS
signal group specifications, Table 14 contains timings for the reset conditions, Table 15 and covers
APIC bus timing, and Table 16 covers TAP timing.
All processor system bus AC specifications for the AGTL+ signal group are relative to the rising
edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’ logic
levels unless otherwise specified.
Datasheet
29
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) as the Pentium III Processor for the PGA370 Socket I/O Buffer
Models, XTK/XNS Format (Electronic Format).
AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
2.13.1
I/O Buffer Model
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s Developer’s Website (http://developer.intel.com). The model is for use in single processor
designs and assumes the presence of motherboard RTT values as described in Table 9 on page 29.
Table 10. System Bus AC Specifications (Clock)1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
100.00
133.33
4
4
System Bus Frequency
MHz
10.0
7.5
4, 5, 10
4, 5, 11
T1: BCLK Period
ns
ps
ns
ns
7
±250
±250
6, 7, 10
6, 7, 11
T2: BCLK Period Stability
T3: BCLK High Time
T4: BCLK Low Time
2.5
1.4
9, 10
9, 11
7
7
2.4
1.4
9, 10
9, 11
T5: BCLK Rise Time
T6: BCLK Fall Time
0.4
0.4
1.6
1.6
ns
ns
7
7
8, 12
8, 12
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00V at the processor pins.
3. N/A
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 MHz or 133 MHz, not both. Table 11 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5V–2.0V. BCLK fall time is measured between 2.0V–0.5V.
9. BCLK high time is measured as the period of time above 2.0V. BCLK low time is measured as the period of
time below 0.5V
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz.
11.This specification applies to Pentium III processors operating at a system bus frequency of 133 MHz.
12.Not 100% tested. Specified by design characterization as a clock driver requirement.
30
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 11. Valid System Bus to Core Frequency Ratios 1, 2, 3
Core Frequency
BCLK Frequency
Frequency
Multiplier
Processor
L2 Cache (MHz)
(MHz)
(MHz)
500E
533EB
550E
600E
600EB
650
500
533
550
600
600
650
667
700
733
750
800
800
850
866
900
933
1000
100
133
100
100
133
100
133
100
133
100
100
133
100
133
100
133
133
5
4
500
533
550
600
600
650
667
700
733
750
800
800
850
866
900
933
1000
11/2
6
9/2
13/2
5
667
700
7
733
11/2
15/2
8
750
800
800EB
850
6
17/2
13/2
9
866
900
933
7
1B GHz
15/2
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the
Pentium III processor.
3. Individual processors will only operate at their specified system bus frequency. Either 100 MHz or 133 MHz,
not both.
Datasheet
31
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 12. System Bus AC Specifications (AGTL+ Signal Group)1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
4, 10, 11
T7: AGTL+ Output Valid Delay
T8: AGTL+ Input Setup Time
0.40
3.25
ns
8
1.20
0.95
ns
ns
9
9
5, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
1.00
1.00
ns
9
8, 10
ms
10
6, 9, 10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.5V, V
at 1.0 V ±2% and with 56 Ω on-die
REF
R
.
TT
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchrounous.
7. Specification is for a minimum 0.40 V swing from V
rate of 0.3V/ns.
- 200 mV to V
+ 200 mV. This assumes an edge
REF
REF
8. Specification is for a maximum 1.0 V swing from VTT - 1V to VTT. This assumes an edge rate of 3V/ns.
9. This should be measured after VCC , VTT, Vcc , and BCLK become stable.
CORE
CMOS
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11.This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
Table 13. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
Active and
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
BCLKs
8
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
8, 11
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
, VTT, VCC
, and BCLK become stable.
CC
CORE
CMOS
32
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 14. System Bus AC Specifications (Reset Conditions) 1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time
Before deassertion
of RESET#
4
BCLKs
10
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time
After clock that
deasserts RESET#
2
20
BCLKs
10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
Table 15. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter
T21: PICCLK Frequency
Min
Max
Unit
Figure
Notes
2.0
30.0
10.5
10.5
0.25
0.25
5.0
33.3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
T22: PICCLK Period
500.0
7
7
T23: PICCLK High Time
@ > 1.7V
T24: PICCLK Low Time
7
@ < 0.7V
(0.7V - 1.7V)
(1.7V - 0.7V)
4
T25: PICCLK Rise Time
3.0
3.0
7
T26: PICCLK Fall Time
7
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
9
2.5
9
4
1.5
8.7
7, 8
7, 8
4, 5, 6
1.5
12.0
4, 5, 6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
Datasheet
33
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 16. System Bus AC Specifications (TAP Connection)1, 2, 3
T# Parameter
T30: TCK Frequency
Min
Max
Unit
Figure
Notes
16.667
MHz
ns
T31: TCK Period
60.0
25.0
25.0
7
7
7
10
T32: TCK High Time
T33: TCK Low Time
ns
V
V
+ 0.200V,
- 0.200V,
REF
10
ns
REF
(V
(V
- 0.200V) -
+ 0.200V),
REF
T34: TCK Rise Time
T35: TCK Fall Time
5.0
5.0
ns
ns
7
7
REF
4, 10
(V
(V
+ 0.200V) -
- 0.200V),
REF
REF
4, 10
10
T36: TRST# Pulse Width
40.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
12
12
12
12
12
12
12
12
Asynchronous,
5
T37: TDI, TMS Setup Time
T38: TDI, TMS Hold Time
14.0
1.0
5
T39: TDO Valid Delay
10.0
25.0
25.0
25.0
6, 7
T40: TDO Float Delay
6, 7, 10
6, 8, 9
6, 8, 9, 10
5, 8, 9
5, 8, 9
T41: All Non-Test Outputs Valid Delay
T42: All Non-Test Inputs Setup Time
T43: All Non-Test Inputs Setup Time
T44: All Non-Test Inputs Hold Time
2.0
5.0
13.0
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All
TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Note: For Figure 7 through Figure 13, the following apply:
1. Figure 7 through Figure 13 are to be used in conjunction with Table 10 through Table 16.
2. All AC timings for the AGTL+ signals at the processor pins are referenced to the BCLK rising
edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V
at the processor pins.
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
4. All AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
34
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 7. BCLK, PICCLK, and TCK Generic Clock Waveform
th
tr
V2
V3
CLK
V1
tf
tl
tp
Tr
Tf
Th
Tl
=
=
=
=
=
T5, T25, T34, (Rise Time)
T6, T26, T35, (Fall Time)
T3, T23, T32, (High Time)
T4, T24, T33, (Low Time)
Tp
T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK is referenced to 0.5V. TCK is referenced to V REF - 200mV.
PICCLK is referenced to 0.7V.
V2 = BCLK is referenced to 2.0V. TCK is referenced to VREF - 200mV.
PICCLK is referenced to 1.7V.
V3 = BCLK and PICCLK are referenced to 1.25V. TCK is referenced to V
.
REF
Figure 8. System Bus Valid Delay Timings
CLK
Tx
Tx
Valid
Valid
V
Signal
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group; 0.75V for CMOS, APIC and TAP signal groups
Figure 9. System Bus Setup and Hold Timings
CLK
Th
Ts
V
Valid
Signal
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
= 1.0V for AGTL+ signal group; 0.75V for APIC and TAP signal groups
V
Datasheet
35
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 10. System Bus Reset and Configuration Timings
BCLK
Tu
Tt
RESET#
Tv
Tx
Ty
Tz
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Safe
Valid
Tw
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Valid
Tt = T9 (AGTL+ Input Hold Time)
Tu = T8 (AGTL+ Input Setup Time)
Tv = T10 (RESET# Pulse Width)
Tw = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
Tx = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
Figure 11. Power-On Reset and Configuration Timings
BCLK
VccCORE, VTT
,
VREF
VIH,
min
P W R G O O D
VIL,
max
Ta
Tb
RESET#
TC
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Valid Ratio
Ta = T15 (PWRGOOD Inactive Pulse)
Tb = T10 (RESET# Pulse Width)
Tc = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
36
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 12. Test Timings (TAP Connection)
TCK
Tv
Tr
Tw
TDI, TMS
Ts
Input
Signal
Tx
Ty
Tu
Tz
T D O
Output
Signal
Tr = T43 (All Non-Test Inputs Setup Time)
Ts = T44 (All Non-Test Inputs Hold Time)
Tu = T40 (TDO Float Delay)
Tv = T37 (TDI, TMS Setup Time)
Tw = T38 (TDI, TMS Hold TIme)
Tx = T39 (TDO Valid Delay)
Ty = T41 (All Non-Test Outputs Valid Delay)
Tz = T42 (All Non-Test Outputs Float Time)
Figure 13. Test Reset Timings
TRST#
1.25V
Tq
Tq = T36 (TRST# Pulse Width)
Datasheet
37
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 17, Table 18, and Table 23 ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK and PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 17 describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals. Figure 14 describes the signal quality
waveform for the system bus clock at the processor pins.
Table 17. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins 1
T# Parameter
V1: BCLK VIL
Min
Nom
Max
Unit
Figure
Notes
0.500
0.700
V
V
V
V
V
V
V
V
V
14
14
14
14
14
14
14
14
14
V1: PICCLK VIL
V2: BCLK VIH
2.000
2.000
–0.58
2.000
2.000
V2 PICCLK VIH
V3: VIN Absolute Voltage Range
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
V5: PICCLK Falling Edge Ringback
3.18
2
2
2
2
0.500
0.700
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
38
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 14. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V3
V4
V2
V1
V5
V3
3.2
AGTL+ Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guide. Refer to the Intel® Pentium® II Processor
Developer's Manual (Order Number 243502) for the AGTL+ buffer specification.
Table 18 provides the AGTL+ signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Pentium III processor for the PGA370 socket maximum allowable overshoot and undershoot
specifications for a given duration of time are detailed in Table 20 through Table 22. Figure 15
shows the AGTL+ ringback tolerance and Figure 16 shows the overshoot/undershoot waveform.
Table 18. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins 1, 2, 3
T# Parameter
Min
Unit
Figure
Notes
α: Overshoot
100
0.50
±200
200
mV
ns
15
15
15
15
15
4, 8
τ: Minimum Time at High
ρ: Amplitude of Ringback
φ: Final Settling Voltage
mV
mV
ns
5, 6, 7, 8
8
δ: Duration of Squarewave Ringback
N/A
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See Figure 15 for the generic waveform.
3. All values specified by design characterization.
4. Please see Table 20 for maximum allowable overshoot.
5. Ringback between V
+ 100 mV and V
+ 200 mV or V
- 200 mV and V
- 100 mVs requires the
REF
REF
REF
REF
®
®
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel Pentium II
Developers Manual). Ringback below V + 100 mV or above V - 100 mV is not supported.
REF
REF
6. Intel recommends simulations not exceed a ringback value of V
sources of system noise.
±200 mV to allow margin for other
REF
7. A negative value for ρ indicates that the amplitude of ringback is above V
. (i.e., φ = -100 mV specifies the
REF
signal cannot ringback below V
+ 100 mV).
REF
8. φ and ρ: are measured relative to V . α: is measured relative to V
+ 200 mV.
REF
REF
Datasheet
39
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 15. Low to High AGTL+ Receiver Ringback Tolerance
τ
α
VREF + 0.2
φ
VREF
ρ
VREF - 0.2
δ
0.7V Clk Ref
Vstart
Clock
Time
Note: High to low case is analogous
3.3
AGTL+ Signal Quality Specifications and Measurement
Guidelines
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the Pentium III processor performance, care must be taken to ensure
that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will
impact results and may yield excessive overshoot/undershoot.
40
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This could be acomplished by simultaneously measuring the VTT plane while measuring the
signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform. The
true undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT - Signal_measured
Note: The converted undershoot waveform appears as a positive (overshoot) signal.
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
After the true waveform conversion, the undershoot/overshoot specifications shown in Table 20
through Table 22 can be applied to the converted undershoot waveform using the same magnitude
and pulse duration specifications used with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in Table 20 through Table 22. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must
all be used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.635V). The total time could encompass several
oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
Note: Oscillations below the reference voltage can not be substracted from the total overshoot/
undershoot pulse duration.
Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individual Pulse Duraitons to determine the total Overshoot/Undershoot Pulse Duration for that
total event.
3.3.4
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The specifications provided in Table 20 through Table 22 show the Maximum Pulse Duration
allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table
entry is independent of all others, meaning that the Pulse Duration reflects the existence of
overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot
Datasheet
41
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can
be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the
event occurs at all times and no other events can occur).
Note: Activity factor for AGTL+ signals is referenced to BCLK frequency.
Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
3.3.5
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Pentium III processor for the PGA370 socket is not
a simple single value. Instead, many factors are needed to determine what the over/undershoot
specification is. In addition to the magnitude of the overshoot, the following parameters must also
be known: the junction temperature the processor will be operating at, the width of the overshoot
(as measured above 1.635V) and the Activity Factor (AF). To determine the allowed overshoot for
a particular overshoot event, the following must be done:
1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal
operating with a 100 MHz system bus, use Table 20 (100MHz AGTL+ signal group). If the
signal is an AGTL+ signal operating with a 133MHz system bus, use Table 21 (133 MHz
AGTL+ signal group). If the signal is a CMOS signal, use Table 22 (33 MHz CMOS signal
group).
2. Determine the maximum junction temperature (Tj) for the range of processors that the system
will support (80oC or 85oC).
3. Determine the Magnitude of the overshoot (relative to VSS)
4. Determine the Activity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Below is an example showing how the maximum pulse duration is determined for a given
waveform.
Table 19. Example Platform Information
Required Information
Maximum Platform Support
Notes
FSB Signal Group
Max Tj
133 MHz AGTL+
85 °C
Overshoot Magnitude
2.13V
Measured Value
Measured overshoot occurs on
average every 20 clocks
Activity Factor (AF)
0.1
NOTES:
1. Corresponding Maximum Puse Duration Specification - 2.4 ns
2. Pulse Duration (measured) - 2.0 ns
Given the above parameters, and using Table 21 (85 oC/AF = 0.1 column) the maximum allowed
pulse duration is 2.4 ns. Since the measure pulse duration is 2.0 ns, this particular overshoot event
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
42
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.3.6
Determining if a System meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
you add the total impact of all overshoot events, the system may fail. A guideline to ensure a
system passes the overshoot and undershoot specifications is shown below. It is important to meet
these guidelines; otherwise, contact your Intrel field representative.
1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635V
OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables
OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 20 through Table 22.
NOTES:
1. Overshoot/Undershoot Magnitude = 2.18V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to VSS.
3. Undershoot is measured relative to VTT
4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V.
5. Rinbacks below VTT can not be subtracted from Overshoots/Undershoots
6. Lesser Undershoot does not allocate longer or larger Overshoot
7. OEM's are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines
provided in the specific platform design guide.
8. All values specified by design characterization
Table 20. 100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins1,2
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 85 °C
(ns)
Overshoot/
Undershoot
Magnitude
AF = 0.01
AF = 0.1
AF = 1
AF = 0.01
AF = 0.1
AF = 1
2.18 V
2.13 V
2.08 V
2.03 V
1.98 V
1.93 V
1.88 V
20
20
20
20
20
20
20
2.53
4.93
9.1
16.6
20
0.25
0.49
0.91
1.67
3.0
18.6
20
1.86
3.2
6.1
11.4
20
0.18
0.32
0.6
1.1
2
20
20
20
20
5.5
20
20
6.6
20
20
10
20
20
1. BCLK period is 10 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Datasheet
43
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 21. 133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance 1, 2
Maximum Pulse Duration at Tj = 80 Maximum Pulse Duration at Tj = 85 °C
°C (ns)
(ns)
Overshoot/Undershoot
Magnitude
AF = 0.01
AF = 0.1
AF = 1
AF = 0.01
AF = 0.1
AF = 1
2.18 V
2.13 V
2.08 V
2.03 V
1.98 V
1.93 V
1.88 V
15
15
15
15
15
15
15
1.9
3.7
6.8
12.5
15
0.19
0.37
0.68
1.25
2.28
4.1
14
15
15
15
15
15
15
1.4
2.4
4.6
8.6
15
0.14
0.24
0.46
0.84
1.5
15
15
5
15
7.5
15
15
1. BCLK period is 7.5 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 22. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins1, 2
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 85 °C
(ns)
Overshoot/
Undershoot
Magnitude
AF = 0.01
AF = 0.1
AF = 1
AF = 0.01
AF = 0.1
AF = 1
2.18 V
2.13 V
2.08 V
2.03 V
1.98 V
1.93 V
1.88 V
60
60
60
60
60
60
60
7.6
14.8
27.2
50
0.76
1.48
2.7
5
56
60
60
60
60
60
60
5.6
9.6
18.4
33
0.56
0.96
1.8
3.3
6
60
9.1
16.4
30
60
60
60
20
60
60
60
NOTES:
1. PICCLK period is 30 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
44
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 16. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
Time Dependent
Overshoot
Converted Undershoot
Waveform
Max
2.18V
2.08V
1.98V
1.88V
1.635V
VTT
Overshoot
Magnitude
Undershoot
Magnitude
Vss
Overshoot
Magnitude
=
Signal - Vss
VTT - Signal
Undershoot
Magnitude
=
Time Dependent
Undershoot
3.4
Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in Figure 17 for the non-
AGTL+ signal group.
Figure 17. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1
Settling Limit
Overshoot
V
HI
Rising-Edge
Ringback
Falling-Edge
Ringback
Settling Limit
V
LO
V
SS
Time
Undershoot
NOTES:
1. V = 1.5V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. V = 2.5 V for BCLK,
HI
HI
PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.
Datasheet
45
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.4.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates (see Figure 17 for non-AGTL+ signals). The processor can be damaged by
repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if
the overshoot is great enough). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the
ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the
absence of diodes on the input. These guidelines should be verified in simulations without the on-
chip ESD protection diodes present because the diodes will begin clamping the 1.5 V and 2.5 V
tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below
VSS. If signals are not reaching the clamping voltage, this will not be an issue. A system should not
rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.
Note: The undershoot guideline limits transitions exactly as described for the ATGL+ signals. See
Figure 16.
3.4.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See Figure 17 for an illustration of ringback. Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 23 for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor pins.
Table 23. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins 1
Maximum Ringback
Input Signal Group
Transition
(with Input Diodes Present)
Unit
Figure
2
Non-AGTL+ Signals
0 → 1
1 → 0
0 → 1
Vref + 0.200
Vref - 0.200
2.00
V
V
V
17
17
17
2
Non-AGTL+ Signals
PWRGOOD
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL+ signals except PWRGOOD.
3.4.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total signal swing (VHI –V ) above
LO
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
46
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
4.0
Thermal Specifications and Design Considerations
This chapter provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design
Guidelines (Order Number 245087). The Pentium III processor uses flip chip pin grid array
packaging technology and has a junction temperature (Tjunction) specified.
4.1
Thermal Specifications
Table 24 provides the thermal design power dissipation and maximum temperatures for the
Pentium III processor for the PGA370 socket. Systems should design for the highest possible
processor power, even if a processor with a lower thermal dissipation is planned. A thermal
solution should be designed to ensure the junction temperature never exceeds these specifications.
Table 24. Intel® Pentium® III Processor for the PGA370 Socket Thermal Design Power 1
Power
Power
Processor
Thermal
Design
5
5
Processor
Core
Frequency
(MHz)
Density
Density
T
L2 Cache
Size
(Kbytes)
Maximum
JUNCTION
2
2
(W/cm )
CPUID
up to
(W/cm )
for
4,6
Processor
T
Offset
(°C)
JUNCTION
2,3
Power
(°C)
CPUID
0686h
(W)
0683h
500E
533EB
550E
600E
600EB
650
500
533
550
600
600
650
667
700
733
750
800
800
850
866
900
933
1000
1000
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
13.2
14.0
14.5
15.8
15.8
17.0
17.5
18.3
19.1
19.5
20.8
20.8
22.5
22.9
23.2
24.5
26.1
29.6
18.2
19.3
20.0
21.8
21.8
23.4
24.1
25.2
26.3
26.9
28.7
28.7
31.0
31.5
N/A
20.8
22.0
22.8
24.8
24.8
26.7
27.5
28.7
30.0
30.6
32.6
32.6
35.2
35.9
37.1
38.4
40.9
43.9
85
85
85
82
82
82
82
80
80
80
80
80
80
80
75
75
70
70
1.9
2.0
2.1
2.3
2.3
2.5
2.5
2.7
2.8
2.8
3.0
3.0
3.3
3.3
3.6
3.6
3.8
3.8
667
700
733
750
800
800EB
850
866
900
933
33.8
36.0
N/A
1B GHz
7,8
1B GHz
NOTES:
1. These values are specified at nominal VCC
for the processor pins.
CORE
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tjunction specification.
3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to
Table 6 for voltage regulation and electrical specifications.
Datasheet
47
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
4. T
is the worst-case difference between the thermal reading from the on-die thermal diode and the
junctionoffset
hottest location on the processor’s core.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in Figure 18.
6. TJUNCTION offset values do not include any thermal diode kit measurement error. Diode kit measurement
®
®
error must be added to the TJUNCTION offset value from the table, as outlined in the Intel Pentium III
processor Thermal Metrology for CPUID-068h Family Processors (Order Number: 245301). Intel has
characterized the use of the Analog Devices AD1021 diode measurement kit and found its measurement
error to be 1 °C.
7. These values are estimates based on preliminary simulation.
8. This specification only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70V, however
the processor should be supplied 1.76V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM.
Figure 18 is a block diagram of the Pentium III processor die layout. The layout differentiates the
processor core from the cache die area. In effect, the thermal design power indentified in Table 24
is dissipated entirely from the processor core area. Thermal solution designs should compensate
for this smaller heat flux area and not assume that the power is uniformly distributed across the
entire die area. The drawing below does not depict the 5% die shrink (CPUID=0686h) values as
follows: Die Area (0.900), Core Area (0.642), Cache Area (0.258) cm2.
Figure 18. Processor Functional Die Layout for CPUIDs up to and including 0683h
Die Area (1.046 cm2)
Core Area (0.726 cm2)
Cache Area (0.320 cm2)
4.1.1
Thermal Diode
The Pentium III processor for the PGA370 socket incorporates an on-die diode that may be used to
monitor the die temperature (junction temperature). A thermal sensor located on the motherboard,
or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal
management or instrumentation purposes. Table 25 and Table 26 provide the diode parameter and
interface specifications.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-
die temperature gradients between the location of the thermal diode and the hottest location on the
die at a given point in time, and time based variations in the die temperature measurement. Time
based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is
slower than the rate at which the Tjunction temperature can change.
48
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 25. Thermal Diode Parameters1
Symbol
Parameter
Min
Typ
Max
Unit
Notes
I
Forward Bias Current
Diode Ideality Factor
5
300
µA
1
fw
n
1.0057
1.0080
1.0125
2, 3, 4
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 100° C with a forward bias current of 5 - 300 µA.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
I
=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the
fw
diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4. Not 100% tested. Specified by design characterization.
Table 26. Thermal Diode Interface
Pin Name
PGA370 Socket pin #
Pin Description
THERMDP
THERMDN
AL31
AL29
diode anode (p_junction)
diode cathode (n_junction)
Datasheet
49
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
5.0
Mechanical Specifications
The Pentium III processor uses a FC-PGA package technology. Mechanical specifications for the
processor are given in this section. See Section 1.1.1 for a complete terminology listing.
The processor utilizes a PGA370 socket for installation into the motherboard. Details on the socket
are available in the 370-Pin Socket (PGA370) Design Guidelines.
Note: For Figure 19, the following apply:
1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production
product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational
purposes only. Reference dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference dimensions are
NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in
parentheses without tolerances are reference dimensions.
4. Drawings are not to scale.
5.1
FC-PGA Mechanical Specifications
The following figure with package dimensions is provided to aid in the design of heatsink and clip
solutions as well as demonstrate where pin-side capacitors will be located on the processor.
Table 27 includes the measurements for these dimensions in both inches and millimeters.
Figure 19. Package Dimensions
50
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 27. Intel® Pentium® III Processor Package Dimensions
Millimeters
Inches
Symbol
Minimum
Maximum
Notes
Minimum
Maximum
Notes
A1
A2
B1
B2
C1
C2
D
0.787
1.000
11.226
9.296
0.889
1.200
11.329
9.398
0.031d
0.039
0.442
0.366
0.035
0.047
0.446
0.370
23.495 max
21.590 max
49.428
0.925 max
0.850 max
49.632
45.974
17.780
17.780
0.889
1.946
1.954
1.810
0.700
0.700
0.035
D1
G1
G2
G3
H
45.466
0.000
0.000
0.000
1.790
0
0
0
2.540
Nominal
0.100
Nominal
L
3.048
0.431
3.302
0.483
0.120
0.017
0.130
0.019
ΦP
Pin TP
Pin Diameter
0.508 Diameteric True Position (Pin-to-Pin)
0.020 Diameteric True Position (Pin-to-Pin)
NOTES:
1. Capacitors will be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and G3. This
area is a keepout zone for motherboard designers.
The bare processor die has mechanical load limits that should not be exceeded during heat sink
assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach
solution must not induce permanent stress into the processor substrate with the exception of a
uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and
static loading parameters are listed in Table 28.
For Table 28, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads
Table 28. Processor Die Loading Parameters
1
2
Parameter
Dynamic (max)
Static (max)
Unit
Silicon Die Surface
Silicon Die Edge
200
100
50
12
lbf
lbf
NOTES:
1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface
Datasheet
51
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
5.2
Processor Markings
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium III processor for the PGA370 socket. Table 27 lists the measurements
for the package dimensions.
Figure 20. Top Side Processor Markings
Static Mark ink printed at
substrate supplier
Country of Origin
III
pentium
logo
intel ®
MALAY
i (m) (c) ’99
RB80526PY550266
FFFFFFFF-0001 SSSSS
FPO # - S/N
S-spec#
Product Code
Dynamic Laser Mark
Swatch
5.3
Processor Signal Listing
Table 29 and Table 30 provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 21 provides a pin-side view of the Pentium III processor pin-out.
The following notes apply to Table 29 and Table 30:
NOTES:
1. These pins are required for backwards compatibility with other Intel processors. They are not used by the
Pentium III processor. Refer to the appropriate platform design guide and Section 7.1 for implementation
details.
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
platform design guide and Section 7.1 for implementation details. If backwards compatibility is not required,
then RESET2# (X4) should be connected to GND.
3. VCC V must be supplied by the same voltage source supplying the VTT pins.
1.5
®
4. These VTT pins must be left unconnected (N/C) for backwards compatibility with Intel Celeron™ processors
(CPUID 066xh). For designs which do not support the Intel Celeron processors (CPUID 066xh), and for
compatibility with future processors, these VTT pins should be connected to the VTT plane. Refer to the
appropriate platform design guide and Section 7.1 for implementation details. For dual processor designs,
these pins must be connected to VTT.
5. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left
connected to VCC
. Refer to the appropriate platform design guide for implementation details.
CORE
6. Previously, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
(N/C).
7. Previously, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED. Refer to the Peniutm III
®
processor Specification Update for a complete listing of processors that support DP operation.
52
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 21. Intel® Pentium® III Processor Pinout
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
VSS
A16
A6
VTT
BPRI
DEFER
VSS VCC
VTT
RP
TRDY
HIT
DRDY
BR0
ADS
TRST
TCK
TDI
TDO
VID2
A12
VTT
AP0
AP1
VTT
RSV
VCC
VSS
VSS
A28
VCC
A3
VSS
A11
VCC
VSS
A14
VCC
VSS
VCC
VCC
VSS
VID1
VCC
VTT
VSS
VSS
VSS
VSS
A15
A13
A9
A7
REQ4
REQ3
LOCK
VSS
VTT
VREF7
VCC
HITM
DBSY
P W R G D
VCC VSS
T H R M D N
RS2
T H R M D P
RSV
VID0
VSS
A21
VCC
VREF6
VSS
REQ0
VCC
REQ2
AERR
VCC
TMS
BSEL0
VSS
STPCLK
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VCC
BSEL1
SMI
VCC
VID3
VSS
RESET
A19
A10
A25
A5
A8
A4
BNR
REQ1
VTT
RS1
RS0
SLP
VCC
T H E R M
TRIP
VSS
VCC
INIT
IGNNE
FLUSH
EDGCTRL
VCC
VSS
VCC
VSS
A35
A31
A24
A17
A22
A20
A20M
IERR
VCC
VSS
VREF5
VSS
V_1.5
A33
VSS
VSS
VSS
VTT
VCC
FERR
RSP
A23
A18
A32
VCC
VSS
BR1
VCC
VSS
V_CMOS
VCC
V_2.5
VSS
VTT
A27
RSV
D0
A30
A26
A34
VCC
VSS
A29
Y
Y
CLKREF
VSS
VCC
X
X
RESET2
VCC
VCC
RSV
VSS
W
V
W
V
PLL1
VCC
BCLK
VSS
VCC
VSS
VCC
RSV
VCC
VSS
BERR
VREF4
Pin Side View
U
U
PLL2
VTT
VTT
D4
D15
VSS
T
T
D6
D1
VSS
VCC
VSS
VCC
VSS
VSS
S
S
RTT
CTRL
VCC
D8
D5
VCC
VSS
VTT
VTT
RSV
R
R
D17
D18
D11
VREF3
VCC
RSV
Q
Q
D12
D10
RSV
P
P
D9
VSS
VSS
N
N
D2
D14
VCC
RSV
RSV
RSV
RSV
M
M
D3
VCC
LINT0
L
L
D13
D7
D20
D30
D23
VSS
PICD1
VCC
PICD0
LINT1
PREQ
K
K
VCC
VSS
VREF2
VCC
D24
D19
VCC
VSS
VCC
J
J
PICCLK
VCC
H
H
D16
VSS
G
G
D21
VSS
BP2
VTT
RSV
BP3
F
F
VCC
VSS
VCC
VSS
D32
D22
D38
RSV
D27
D42
VCC
D41
D63
VSS
VCC
VCC
VSS
VSS
VCC
VSS
VSS
VCC
VSS
VSS
VREF0
VCC
VCC
VSS
VSS
VREF1
VSS
E
E
S L E W
CTRL
D26
D33
D25
VCC
D31
VSS
D34
VCC
D36
VSS
D45
VCC
D49
VSS
D40
VCC
RSV
D54
VTT
D62
D50
DEP6
DEP5
DEP4
DEP1
BPM1
VCC
D
D
VCC
D39
D52
VSS
VSS
VCC
VSS
VCC
VSS
C
C
VCC
D59
D55
D58
D56
DEP0
BPM0
CPUPRES
B
B
VCC
D35
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
BINIT
VSS
A
A
D37
D29
D28
D43
D44
D51
D47
D48
D57
D46
D53
D60
D61
DEP7
Dep7
DEP3
DEP2
PRDY
VSS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Datasheet
53
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AK8
A3#
AGTL+ I/O
B36
BINIT#
AGTL+ I/O
AH12
AH8
AN9
AL15
AH10
AL9
AH6
AK10
AN5
AL7
AK14
AL5
AN7
AE1
Z6
A4#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
CMOS Input
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
System Bus Clock
AGTL+ I/O
AH14
G33
E37
C35
E35
AN17
AN29
X2
BNR#
BP2#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ Input
AGTL+ I/O
AGTL+ Input
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
A5#
A6#
BP3#
A7#
BPM0#
BPM1#
BPRI#
BR0#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
AERR#
AP0#
AP1#
BCLK
BERR#
8
BR1#
AJ33
AJ31
Y33
C37
W1
T4
BSEL0
BSEL1
CLKREF
7
CPUPRES#
D0#
D1#
N1
D2#
AG3
AC3
AE33
AJ1
M6
U1
D3#
D4#
S3
D5#
T6
D6#
AE3
AB6
AB4
AF6
Y3
J1
D7#
S1
D8#
P6
D9#
Q3
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
M4
Q1
AA1
AK6
Z4
L1
N3
AA3
AD4
X6
U3
H4
R4
AC1
W3
P4
H6
AF4
AN31
AK24
AL11
AN13
W37
V4
L3
G1
F8
G3
K6
E3
E1
54
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name (Continued)
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
F12
D27#
AGTL+ I/O
C31
DEP1#
AGTL+ I/O
A5
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBSY#
DEFER#
DEP0#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ Input
AGTL+ I/O
A33
A31
E31
C29
E29
A29
AN27
AG1
AC35
AE37
AM22
AM26
AM30
AM34
AM6
AN3
B12
B16
B20
B24
B28
B32
B4
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
EDGCTRL
FERR#
FLUSH#
GND
AGTL+ I/O
A3
AGTL+ I/O
J3
AGTL+ I/O
C5
AGTL+ I/O
F6
AGTL+ I/O
C1
AGTL+ I/O
C7
AGTL+ I/O
5
B2
Power/Other
CMOS Output
CMOS Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
C9
A9
D8
D10
C15
D14
D12
A7
GND
GND
GND
GND
GND
A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16
AL27
AN19
C33
GND
GND
GND
GND
GND
GND
GND
B8
GND
D18
D2
GND
GND
D22
D26
D30
D34
D4
GND
GND
GND
GND
GND
E11
E15
E19
E7
GND
GND
GND
GND
F20
F24
F28
F32
GND
GND
GND
GND
Datasheet
55
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name (Continued)
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
F36
GND
Power/Other
V2
GND
Power/Other
G5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V34
X32
X36
Y37
Y5
GND
Power/Other
H2
GND
Power/Other
H34
K36
GND
Power/Other
GND
Power/Other
L5
GND
Power/Other
M2
Z2
GND
Power/Other
M34
P32
Z34
GND
Power/Other
AL25
AL23
AE35
AG37
AG33
M36
L37
HIT#
AGTL+ I/O
P36
HITM#
AGTL+ I/O
A37
IERR#
CMOS Output
CMOS Input
AB32
AC33
AC5
AD2
AD34
AF32
AF36
AG5
AH2
AH34
AJ11
AJ15
AJ19
AJ23
AJ27
AJ3
IGNNE#
INIT#
CMOS Input
LINT0/INTR
LINT1/NMI
LOCK#
PICCLK
PICD0
CMOS Input
CMOS Input
AK20
J33
AGTL+ I/O
APIC Clock Input
APIC I/O
J35
L35
PICD1
APIC I/O
W33
U33
A35
J37
PLL1
Power/Other
PLL2
Power/Other
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AGTL+ Output
CMOS Input
AK26
AK18
AH16
AH18
AL19
AL17
G37
L33
CMOS Input
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AJ7
AGTL+ I/O
AK36
AK4
AL1
AGTL+ I/O
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
AL3
N33
N35
N37
Q33
Q35
Q37
R2
AM10
AM14
AM18
Q5
R34
T32
T36
W35
Y1
U5
56
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name (Continued)
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AK30
Reserved
Reserved
Reserved
Reserved for future use
Reserved for future use
Reserved for future use
AGTL+ Input
AGTL+ Input
AGTL+ I/O
F30
VCC
Power/Other
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
6
AM2
F10
F34
F4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
8
X2
BR1#
H32
H36
J5
2
AH4
X4
RESET#
2
RESET2#
AN23
AH26
AH22
AK28
AC37
S35
RP#
AGTL+ I/O
K2
RS0#
AGTL + Input
AGTL+ Input
AGTL+ Input
AGTL+ Input
Power/Other
Power/Other
CMOS Input
K32
K34
M32
N5
RS1#
RS2#
RSP#
RTTCTRL
SLEWCTRL
SLP#
P2
E27
P34
R32
R36
S5
AH30
AJ35
AG35
AL33
AN35
AN37
AL29
AL31
AH28
AK32
AN25
AN33
AD36
Z36
SMI#
CMOS Input
STPCLK#
TCK
CMOS Input
TAP Input
T2
TDI
TAP Input
T34
V32
V36
W5
TDO
TAP Output
THERMDN
THERMDP
Power/Other
Power/Other
THERMTRIP# CMOS Output
X34
Y35
Z32
AF2
AF34
AH24
AH32
AH36
AJ13
AJ17
AJ21
AJ25
AJ29
AJ5
AK2
AK34
AM12
AM16
AM20
TMS
TAP Input
TRDY#
TRST#
AGTL+ Input
TAP Input
3
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
1.5
2.5
1
AB36
AA37
AA5
CMOS
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB2
AB34
AD32
AE5
E5
E9
F14
F2
F22
F26
Datasheet
57
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name (Continued)
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AM24
AM28
AM32
AM4
AM8
B10
B14
B18
B22
B26
B30
B34
B6
VCC
Power/Other
AL37
AJ37
E33
VID2
VID3
Power/Other
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
REF
REF
REF
REF
REF
REF
REF
REF
F18
K4
R6
V6
AD6
AK12
AK22
AH20
AK16
AL13
AL21
AN11
AN15
G35
AA33
AA35
AN21
E23
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
C3
D20
D24
D28
D32
D36
D6
4
4
4
4
4
4
4
4
E13
E17
AJ9
E21
AL35
AM36
S33
S37
RESERVE
VID0
U35
U37
VID1
58
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Table 30. Signal Listing in Order by Pin
Number (Continued)
Number
Pin
No.
Pin
No.
Pin Name
Signal Group
AGTL+ I/O
Pin Name
Signal Group
A3
D29#
AD34
AD36
AE1
GND
Power/Other
3
A5
D28#
D43#
D37#
D44#
D51#
D47#
D48#
D57#
D46#
D53#
D60#
D61#
DEP7#
DEP3#
DEP2#
PRDY#
GND
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ Output
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
CMOS Output
AGTL+ Input
Power/Other
AGTL+ I/O
Power/Other
Power/Other
VCC
1.5
Power/Other
AGTL+ I/O
A7
A17#
A22#
A9
AE3
AGTL+ I/O
A11
AE5
VCC
Power/Other
CMOS Input
CMOS Output
CMOS Input
Power/Other
AGTL+ I/O
CORE
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
AA1
AA3
AA5
AA33
AA35
AA37
AB2
AB4
AB6
AB32
AB34
AB36
AC1
AC3
AC5
AC33
AC35
AC37
AD2
AD4
AD6
AD32
AE33
AE35
AE37
AF2
A20M#
IERR#
FLUSH#
VCC
CORE
AF4
A35#
A25#
GND
AF6
AGTL+ I/O
AF32
AF34
AF36
AG1
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
VCC
CORE
GND
5
EDGCTRL
A19#
AG3
AG5
GND
Power/Other
CMOS Input
CMOS Input
CMOS Input
Power/Other
AGTL+ Input
AGTL+ I/O
AG33
AG35
AG37
AH2
INIT#
A27#
A30#
STPCLK#
IGNNE#
GND
VCC
VTT
VTT
VCC
VCC
CORE
4
2
AH4
RESET#
4
AH6
A10#
A5#
AH8
AGTL+ I/O
CORE
CORE
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AH32
AH34
AH36
AJ1
A8#
AGTL+ I/O
A24#
A23#
GND
A4#
AGTL+ I/O
BNR#
REQ1#
REQ2#
VTT
AGTL+ I/O
AGTL+ I/O
VCC
CORE
AGTL+ I/O
VCC
CMOS
Power/Other
AGTL+ Input
Power/Other
AGTL + Input
A33#
A20#
GND
RS1#
VCC
CORE
RS0#
GND
THERMTRIP# CMOS Output
FERR#
RSP#
GND
SLP#
CMOS Input
Power/Other
Power/Other
Power/Other
AGTL+ I/O
VCC
CORE
GND
A31#
VCC
CORE
V
5
A21#
GND
REF
VCC
AJ3
Power/Other
CORE
Datasheet
59
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Number (Continued)
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AJ5
VCC
Power/Other
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL31
AL33
AL35
AL37
AP0#
AGTL+ I/O
CORE
AJ7
GND
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Input
Power/Other
Power/Other
Power/Other
AGTL+ I/O
VTT
Power/Other
AGTL+ I/O
AJ9
VCC
A7#
CORE
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ33
AJ35
AJ37
AK2
GND
REQ4#
REQ3#
VTT
AGTL+ I/O
VCC
AGTL+ I/O
CORE
GND
Power/Other
AGTL+ I/O
VCC
HITM#
HIT#
CORE
GND
AGTL+ I/O
VCC
DBSY#
THERMDN
THERMDP
TCK
AGTL+ I/O
CORE
GND
Power/Other
Power/Other
TAP Input
VCC
CORE
GND
VCC
VID0
Power/Other
Power/Other
Reserved for future use
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
CORE
BSEL1
BSEL0
SMI#
VID2
6
AM2
Reserved
AM4
VCC
CORE
VID3
AM6
GND
VCC
AM8
VCC
CORE
CORE
AK4
GND
A28#
A3#
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM32
AM34
AM36
AN3
GND
AK6
VCC
CORE
AK8
AGTL+ I/O
GND
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AK32
AK34
AK36
AL1
A11#
AGTL+ I/O
VCC
CORE
V
6
Power/Other
AGTL+ I/O
GND
REF
A14#
VCC
CORE
VTT
Power/Other
AGTL+ I/O
GND
REQ0#
LOCK#
VCC
CORE
AGTL+ I/O
GND
V
7
Power/Other
AGTL+ I/O
VCC
CORE
REF
AERR#
PWRGOOD
RS2#
GND
CMOS Input
AGTL+ Input
Reserved for future use
TAP Input
VCC
CORE
GND
VID1
GND
A12#
A16#
A6#
Reserved
TMS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AN5
CORE
GND
GND
GND
A15#
A13#
A9#
AN7
AGTL+ I/O
AN9
AGTL+ I/O
AL3
AN11
AN13
AN15
AN17
VTT
Power/Other
AGTL+ I/O
AL5
AP1#
VTT
AL7
AGTL+ I/O
Power/Other
AGTL+ Input
AL9
AGTL+ I/O
BPRI#
60
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Number (Continued)
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AN19
AN21
AN23
AN25
AN27
AN29
AN31
AN33
AN35
AN37
B2
DEFER#
AGTL+ Input
Power/Other
AGTL+ I/O
AGTL+ Input
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
TAP Input
C25
D50#
AGTL+ I/O
4
VTT
C27
C29
C31
C33
C35
C37
D2
D56#
AGTL+ I/O
RP#
DEP5#
DEP1#
DEP0#
BPM0#
CPUPRES#
GND
AGTL+ I/O
TRDY#
DRDY#
BR0#
ADS#
TRST#
TDI
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
TAP Input
D4
GND
TDO
TAP Output
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
D6
VCC
CORE
D35#
GND
D8
D38#
D39#
D42#
D41#
D52#
GND
B4
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36
E1
AGTL+ I/O
B6
VCC
CORE
AGTL+ I/O
B8
GND
AGTL+ I/O
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
C1
VCC
CORE
AGTL+ I/O
GND
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
VCC
CORE
VCC
CORE
GND
GND
VCC
CORE
VCC
CORE
GND
GND
VCC
CORE
VCC
CORE
GND
GND
VCC
CORE
VCC
CORE
GND
GND
VCC
CORE
VCC
CORE
GND
D26#
D25#
VCC
CORE
E3
AGTL+ I/O
BINIT#
D33#
E5
VCC
CORE
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
E7
GND
C3
VCC
CORE
E9
VCC
CORE
C5
D31#
D34#
D36#
D45#
D49#
D40#
D59#
D55#
D54#
D58#
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
GND
C7
VCC
CORE
C9
GND
C11
C13
C15
C17
C19
C21
C23
VCC
CORE
GND
RESERVE
4
VTT
D62#
SLEWCTRL
DEP6#
Power/Other
AGTL+ I/O
Datasheet
61
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Number (Continued)
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No.
Pin
No.
Pin Name
DEP4#
Signal Group
Pin Name
Signal Group
E31
AGTL+ I/O
K2
VCC
Power/Other
CORE
E33
E35
E37
F2
V
0
Power/Other
AGTL+ I/O
K4
V
2
REF
Power/Other
REF
BPM1#
BP3#
K6
D24#
AGTL+ I/O
AGTL+ I/O
K32
K34
K36
L1
VCC
VCC
Power/Other
CORE
CORE
VCC
VCC
Power/Other
Power/Other
AGTL+ I/O
Power/Other
CORE
CORE
F4
GND
Power/Other
F6
D32#
D13#
AGTL+ I/O
F8
D22#
AGTL+ I/O
L3
D20#
AGTL+ I/O
F10
F12
F14
F16
F18
F20
F22
F24
F26
F28
F30
F32
F34
F36
G1
Reserved
D27#
Reserved for future use
AGTL+ I/O
L5
GND
Power/Other
L33
L35
L37
M2
Reserved
PICD1
LINT1/NMI
GND
Reserved for future use
APIC I/O
VCC
Power/Other
AGTL+ I/O
CORE
D63#
CMOS Input
V
1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
Power/Other
REF
GND
M4
D11#
AGTL+ I/O
VCC
M6
D3#
AGTL+ I/O
CORE
GND
M32
M34
M36
N1
VCC
Power/Other
CORE
VCC
GND
Power/Other
CORE
GND
LINT0/INTR
D2#
CMOS Input
VCC
AGTL+ I/O
CORE
GND
N3
D14#
AGTL+ I/O
VCC
N5
VCC
Power/Other
CORE
CORE
GND
N33
N35
N37
P2
Reserved
Reserved
Reserved
Reserved for future use
Reserved for future use
Reserved for future use
Power/Other
D21#
D23#
GND
G3
AGTL+ I/O
G5
Power/Other
AGTL+ I/O
VCC
CORE
G33
G35
G37
H2
BP2#
VTT
P4
D18#
D9#
AGTL+ I/O
Power/Other
Reserved for future use
Power/Other
AGTL+ I/O
P6
AGTL+ I/O
Reserved
GND
P32
P34
P36
Q1
GND
Power/Other
VCC
Power/Other
CORE
H4
D16#
D19#
GND
Power/Other
H6
AGTL+ I/O
D12#
AGTL+ I/O
H32
H34
H36
J1
VCC
Power/Other
Power/Other
Power/Other
AGTL+ I/O
Q3
D10#
AGTL+ I/O
CORE
GND
Q5
GND
Power/Other
VCC
Q33
Q35
Q37
R2
Reserved
Reserved
Reserved
Reserved
D17#
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
AGTL+ I/O
CORE
D7#
J3
D30#
AGTL+ I/O
J5
VCC
Power/Other
APIC Clock Input
APIC I/O
CORE
J33
J35
J37
PICCLK
PICD0
R4
R6
V
3
Power/Other
REF
PREQ#
CMOS Input
R32
VCC
Power/Other
CORE
62
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Number (Continued)
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No.
Pin
No.
Pin Name
GND
Signal Group
Pin Name
Signal Group
R34
Power/Other
Power/Other
AGTL+ I/O
V36
VCC
CORE
Power/Other
R36
S1
VCC
D8#
D5#
VCC
VTT
W1
W3
W5
W33
W35
W37
X2
D0#
A34#
AGTL+ I/O
CORE
AGTL+ I/O
S3
AGTL+ I/O
VCC
CORE
Power/Other
Power/Other
Reserved for future use
System Bus Clock
AGTL+ input
AGTL+ I/O
S5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
PLL1
CORE
4
S33
S35
S37
T2
Reserved
BCLK
RTTCTRL
4
8
VTT
BR1#
2
VCC
D1#
D6#
X4
RESET2#
A32#
CORE
T4
X6
AGTL+ I/O
T6
AGTL+ I/O
X32
X34
X36
Y1
GND
Power/Other
Power/Other
Power/Other
Reserved for future use
AGTL+ I/O
T32
T34
T36
U1
GND
Power/Other
Power/Other
Power/Other
AGTL+ I/O
VCC
CORE
VCC
GND
CORE
GND
D4#
Reserved
A26#
Y3
U3
D15#
GND
PLL2
AGTL+ I/O
Y5
GND
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
7
U5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
Y33
Y35
Y37
Z2
CLKREF
U33
U35
U37
V2
VCC
CORE
4
VTT
GND
GND
A29#
A18#
4
VTT
GND
Z4
V4
BERR#
Z6
AGTL+ I/O
V6
V
4
Power/Other
Power/Other
Power/Other
Z32
Z34
Z36
VCC
CORE
Power/Other
Power/Other
Power/Other
REF
V32
V34
VCC
GND
CORE
1
GND
VCC
2.5
Datasheet
63
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.0
Boxed Processor Specifications
The Intel® Pentium® III processor for the PGA370 socket is also offered as an Intel boxed
processor. Intel boxed processors are intended for system integrators who build systems from
motherboards and standard components. The boxed Pentium® III processor for the PGA370 socket
will be supplied with an unattached fan heatsink. This section documents motherboard and system
requirements for the fan heatsink that will be supplied with the boxed Pentium III processor. This
section is particularly important for OEMs that manufacture motherboards for system integrators.
Unless otherwise noted, all figures in this section are dimensioned in inches. Figure 22 shows a
mechanical representation of the boxed Intel Pentium® III processor for the PGA370 socket in the
Flip Chip Pin Grid Array (FC-PGA) package.
Note: Drawings in this section reflect only the specifications on the Intel Boxed Processor product. These
dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system
designer’s responsibility to consider their proprietary solution when designing to the required keep-
out zone on their system platform and chassis. Refer to the Intel® Pentium® III Processor Thermal/
Mechanical Functional Specifications for further guidance. Contact your local Intel Sales
Representative for this document.
Figure 22. Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket
6.1
Mechanical Specifications for the Boxed Intel® Pentium® III
Processor
6.1.1
Boxed Processor Thermal Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed Intel Pentium processor fan
heatsink in the FC-PGA package. The boxed processor in the FC-PGA package ships with an un-
attached fan heatsink. Figure 22 shows a mechanical representation of the boxed Intel Pentium III
processor for the PGA370 socket in the Flip Chip Pin Grid Array (FC-PGA) package.
The dimensions for the boxed processor with integrated fan heatsink are shown in Figure 23,
Figure 24, and Figure 25. There are three versions of the fan heatsink. The smallest solution is
shown in Figure 23 for 500 to 850MHz. The larger cooling solution Figure 24 is required for
Pentium III processors at frequencies of 866 to 933MHz. Figure 25 is the largest boxed processor
fan heatsink and is used for 1 GHz Pentium® III processor. General spatial specifications are also
outlined in Table 31. All dimensions are in inches unless otherwise noted.
64
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
The fan heatsink is designed to allow visibility of the FC-PGA processor markings located on top
of the package. The FC-PGA processor markings are visible after installation of the fan heatsink
due to notched sides of the heatsink base (specified in Figure 27). The boxed processor fan heatsink
is also asymmetrical in that the mechanical step feature (specified in Figure 26) must sit over the
socket’s cam. The step allows the heatsink to securely interface with the processor in order to meet
thermal requirements.
Note: The heatsink airflow keepout zones found in Table 31 and Figure 29 refer specifically to the
boxed processor’s active fan heatsink. This does not reflect the worst-case dimensions that may
exist with other third party passive or active fan heatsinks.
Figure 23. Space Requirements for the Boxed Processor to 850MHz
Figure 24. Space Requirements for the Boxed Processor from 866 to 933MHz
Datasheet
65
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 25. Space Requirements for the Boxed Processor at 1 GHz
Table 31. Boxed Processor Fan Heatsink Spatial Dimensionsa
Dimensions (Inches)
Min
Typ
Max
Fan Heatsink Length (see figure 23)
2.52
2.68
3.17
1.75
1.78
1.89
2.00
2.65
2.65
Fan Heatsink for 866 to 933 MHz Length (figure 24)
Fan Heatsink Length for 1 GHz (see figure 25)
Fan Heatsink Height (see figure 23)
Fan Heatsink for 866 to 933 MHz Height (figure 24)
Fan Heatsink Height for 1 GHz (see figure 25)
Fan Heatsink Width (see figure 23)
Fan Heatsink for 866 to 933 MHz Width (figure 24)
Fan Heatsink Width for 1 GHz (see figure 25)
Dimensions (Inches)
Min
Typ
Max
Fan Heatsink height above motherboard for all
frequencies
.30
.29
.33
Air Keepout Zones from end of Fan Heatsink for all
frequencies
.20
a. Drawings reflect only the specification of the Intel boxed processor product. These dimensions should not be used
as a universal keepout zone that covers all heatsinks. It is the system designer’s responsibility to consider their
own proprietary solution when designing the desired keepout zone in their system platform.
Figure 26. Dimensions of Mechanical Step Feature in Heatsink Base
0.043
0.472
66
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.1.2
Boxed Processor Heatsink Weight
The boxed processor thermal cooling solution will not weigh more than 180 grams.
Figure 27. Dimensions of Notches in Heatsink Base
6.1.3
Boxed Processor Thermal Cooling Solution Clip
The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.
Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach
tabs in a way that interferes with the installation of the boxed processor thermal cooling solution
(see Figure 28 for specification).
Datasheet
67
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 28. Clip Keepout Requirements for the PGA370 (Top View)
6.2
Thermal Specifications
This section describes the cooling requirements of the thermal cooling solution utilized by the
boxed processor.
6.2.1
Boxed Processor Cooling Requirements
The boxed processor is directly cooled with a fan heatsink. However, meeting the processor’s
temperature specification is also a function of the thermal design of the entire system, an ultimately
the responsibility of the system integrator. The processor temperature specification is found in
[Section 4.0] of this document. The boxed processor fan heatsink will keep the processor core at
the recommended specifications (see Table 24) in chassis that provide good thermal management.
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of
the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and
decreases fan life. Table 31 and Figure 29 illustrate an acceptable airspace clearance for the fan
heatsink. It is also recommended that the air temperature entering the fan be kept below 45ο C.
Meeting the processor’s temperature specification is the responsibility of the system integrator. The
processor temperature specification is found in [Section 4.0] of this document.
68
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 29. Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor Fan
Heatsinks in the PGA370 Socket
Measure ambient temperature 0.3"
above center of fan inlet
0.20 Min
Air Space
0.20 Min
Air Space
Fan Heatsink
Processor
arsp1.vsd
6.3
Electrical Requirements for the Boxed Intel® Pentium® III
Processor
6.3.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is attached
to the fan and will draw power from a power header on the motherboard. The power cable
connector and pinout are shown in Figure 30. Motherboards must provide a matched power header
to support the boxed processor. Table 32 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE (open-collector output) signal that
pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH to
match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE
signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard. Figure 31 shows the recommended location of the fan
power connector relative to the PGA370 socket. The motherboard power header should be
positioned within 4.00 inches (lateral) from the center of the PGA370 socket.
Datasheet
69
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 30. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin
1
Signal
GND
Straight square pin, 3-pin terminal housing with
polarizing ribs and friction locking ramp.
2
3
+12V
0.100" pin pitch, 0.025" square pin width.
SENSE
Waldom/Molex P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,
or equivalent.
1
2
3
Table 32. Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
+12 V: 12 volt fan power supply
IC: Fan current draw
10.8 V
12 V
13.2 V
100 mA
SENSE: SENSE frequency (motherboard should pull this
pin up to appropriate VCC with resistor)
2 pulses per
fan revolution
Figure 31. Motherboard Power Header Placement Relative to the Boxed Intel® Pentium® III
Processor
0.10"
R = 4.00”
PGA370
70
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
7.0
Processor Signal Description
This section provides an alphabetical listing of all the Intel® Pentium® III processor signals. The
tables at the end of this section summarize the signals by direction: output, input, and I/O.
7.1
Alphabetical Signals Reference
Table 33. Signal Description (Sheet 1 of 8)
Name
Type
Description
The A[35:3]# (Address) signals define a 236-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
A[35:3]#
I/O
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
®
®
pins to determine their power-on configuration. See the Intel Pentium II
Processor Developer’s Manual for details.
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
is only supported in real mode.
A20M#
I
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
ADS#
I/O
I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
AERR#
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the appropriate pins
of all processor system bus agents.
AP[1:0]#
BCLK
I/O
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
I
All external timing parameters are specified with respect to the BCLK signal.
Datasheet
71
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 2 of 8)
Name
Type
Description
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without
a bus protocol violation. It may be driven by all processor system bus agents, and
must connect the appropriate pins of all such agents, if used. However, Pentium III
processors do not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
BERR#
I/O
•
•
•
•
Enabled or disabled.
Asserted optionally for internal errors along with IERR#.
Asserted optionally by the request initiator of a bus transaction after it observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not affected.
BINIT#
I/O
If BINIT# observation is disabled during power-on configuration, a central agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of
the system.
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BNR#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BP[3:2]#
I/O
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPM[1:0]#
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BPRI#
I
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Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 3 of 8)
Name
Type
Description
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BREQ1#
BR0#
BR1#
BR1#
BR0#
BR0#
I/O
I
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate
bus signal protocol, as shown below.
BR1#
BR[1:0]# Signal Agent IDs
Pin Sampled Active in RESET#
Agent ID
BR0#
BR1#
0
3
These signals are used to select the system bus frequency. A BSEL[1:0] = “01”
selects a 100 MHz system bus frequency and a BSEL[1:0] = “11” selects a 133 MHz
system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the
same frequency. The Pentium III processor for the PGA370 socket operates at 100
MHz and 133 MHz system bus frequencies. Individual processors will only operate
at their specified front side bus (FSB) frequency. Either 100 MHz or 133 MHz, not
both.
BSEL[1:0]
I/O
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 Mhz system bus frequency. 66 MHz operation is
not support by the Pentium III processor for the PGA370 socket; therefore, BSEL0 is
ignored.
These signals must be pulled up to 2.5 V or 3.3V with 1 KΩ resistors and provided
as a frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See Section 2.8.2 for
implementation examples.
The CLKREF input is a filtered 1.25V supply voltage for the processor PLL. A
voltage divider and decoupling solution is provided by the motherboard. See the
design guide for implementation details.
CLKREF
I
Datasheet
73
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 4 of 8)
Name
Type
Description
The CPUPRES# signal is defined to allow a system design to detect the presence of
a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[3:0]= 1111 (see Section 2.6), a system can determine if a socket
is occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.
PGA370 Socket Occupation Truth Table
Signal
Value
Status
CPUPRES#
O
0
CPUPRES#
VID[3:0]
Processor core installed in the PGA370
socket.
Anything other
than ‘1111’
CPUPRES#
VID[3:0]
0
1111
Terminator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[3:0]
1
PGA370 socket not occupied.
Any value
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
D[63:0]#
DBSY#
I/O
I/O
I
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEFER#
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DEP[7:0]#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
DRDY#
I/O
O
The EDGCTRL input adjusts the edge rate of AGTL+ output buffers for previous
processors and should be pulled up to VCC
with a 51 Ω ±5% resistor. See the
CORE
EDGCTRL
FERR#
platform design guide for implementation details. This signal is not used by the
Pentium III processor.
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
O
74
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 5 of 8)
Name
Type
Description
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH#
I
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to
determine its power-on configuration. See the P6 Family of Processors Hardware
Developer’s Manual for details.
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
HIT#
I/O
I/O
HITM#
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The processor
will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IERR#
O
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE#
I
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must connect
the appropriate pins of all processor system bus agents.
INIT#
I
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
LINT[1:0]
I
®
®
on the Intel Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction end of the last transaction.
LOCK#
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
Datasheet
75
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 6 of 8)
Name
Type
Description
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICCLK
I
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PICD[1:0]
I/O
I
All Pentium III processors have an internal analog PLL clock generator that requires
a quiet power supply. PLL1 and PLL2 are inputs to this PLL and must be connected
PLL1, PLL2
to VCC
through a low pass filter that minimizes jitter. See the platform design
CORE
guide for implementation details.
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PRDY#
PREQ#
O
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (VCC
,
CORE
etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. The figure below illustrates the
relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in Table 13, and be followed by a 1 ms RESET# pulse.
PWRGOOD
I
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
REQ[4:0]#
I/O
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC
and
CORE
CLK have reached their proper specifications. On observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer’s Manual for details.
RESET#
I
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor
system bus agents.
The RESET2# pin is provided for compatibility with other Intel Architecture
processors. The Pentium III processor does not use the RESET2# pin. Refer to the
platform design guide for the proper connections of this signal.
RESET2#
RP#
I
I/O
I
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all
processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RS[2:0]#
76
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 7 of 8)
Name
Type
Description
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
RSP#
I
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
The RTTCTRL input signal provides AGTL+ termination control. The Pentium III
processor samples this input to sense the presence of motherboard AGTL+
termination. See the platform design guide for implementation details.
RTTCTRL
I
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Pentium III
processor samples this input to determine the slew rate for AGTL+ signals when it is
the driving agent. See the platform design guide for implementation details.
SLEWCTRL
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SLP#
I
I
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
SMI#
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
STPCLK#
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
I
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDI
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TDO
O
O
I
Thermal Diode Cathode. Used to calculate core (junction) temperature. See Section
4.1.
THERMDN
THERMDP
Thermal Diode Anode. Used to calculate core (junction) temperature. See Section
4.1.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
THERMTRIP#
O
Datasheet
77
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 33. Signal Description (Sheet 8 of 8)
Name
TMS
Type
Description
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRDY#
TRST#
I
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 2 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
VID[3:0]
O
The VCORE
pin indicate the type of processor core present. This pin will float for
based processor and will be shorted to VSS for the Pentium III
DET
VCORE
O
I
2.0V VCC
DET
CORE
processor.
The VCC V input pin provides the termination voltage for CMOS signals
1.5
interfacing to the processor. The Pentium III processor reroutes the 1.5V input to the
VCC
1.5
2.5
VCC
output via the package. The supply for VCC V must be the same one
CMOS
1.5
used to supply VTT
.
The VCC V input pin provides the termination voltage for CMOS signals
2.5
VCC
I
O
I
interfacing to processors which require 2.5V termination on the CMOS signals. This
signal is not used by the Pentium III processor.
The VCC
pin provides the CMOS voltage for use by the platform and is used for
CMOS
VCC
CMOS
terminating CMOS signals that interface to the processor.
The V
input pins supply the AGTL+ reference voltage, which is typically 2/3 of
is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
REF
REF
VTT. V
V
REF
logical 1.
7.2
Signal Summaries
Table 34 through Table 37 list attributes of the processor output, input, and I/O signals.
Table 34. Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES#
EDGCTRL
FERR#
Low
N/A
Low
Low
Low
High
Low
N/A
N/A
Asynch
Asynch
Asynch
Asynch
BCLK
Power/Other
Power/Other
CMOS Output
CMOS Output
AGTL+ Output
TAP Output
IERR#
PRDY#
TDO
TCK
THERMTRIP#
Asynch
Asynch
Asynch
CMOS Output
Power/Other
Power/Other
VCORE
DET
VID[3:0]
78
Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 35. Input Signals
Name
Active Level
Clock
Signal Group
Qualified
A20M#
BCLK
Low
High
Low
Low
Low
Low
Low
Low
High
High
High
High
Low
High
Low
Low
Low
N/A
Asynch
—
CMOS Input
System Bus Clock
AGTL+ Input
AGTL+ Input
AGTL+ Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
APIC Clock
CMOS Input
CMOS Input
AGTL+ Input
AGTL+ Input
AGTL+ Input
Power/Other
Power/Other
CMOS Input
CMOS Input
CMOS Input
TAP Input
Always1
Always
BPRI#
BCLK
BCLK
BCLK
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
—
Always
BR1#
Always
DEFER#
FLUSH#
IGNNE#
INIT#
Always
Always1
Always1
Always1
INTR
APIC disabled mode
APIC enabled mode
APIC disabled mode
Always
LINT[1:0]
NMI
PICCLK
PREQ#
PWRGOOD
RESET#
RS[2:0]#
RSP#
Asynch
Asynch
BCLK
BCLK
BCLK
Asynch
Asynch
Asynch
Asynch
Asynch
—
Always
Always
Always
Always
Always
RTTCTRL
SLEWCTRL
SLP#
N/A
Low
Low
Low
High
High
High
Low
Low
During Stop-Grant state
SMI#
STPCLK#
TCK
TDI
TCK
TAP Input
TMS
TCK
TAP Input
TRST#
TRDY#
Asynch
BCLK
TAP Input
AGTL+ Input
NOTE:
1. Synchronous assertion with active TDRY# ensures synchronization.
Datasheet
79
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 36. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
ADS#
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
Asynch
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
ADS#, ADS#+1
Always
AP[1:0]#
BP[3:2]#
BPM[1:0]#
BR0#
ADS#, ADS#+1
Always
Always
Always
BSEL[1:0]
D[63:0]#
DBSY#
Always
DRDY#
Always
DEP[7:0]#
DRDY#
LOCK#
DRDY#
Always
Always
REQ[4:0]#
RP#
ADS#, ADS#+1
ADS#, ADS#+1
Table 37. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
AERR#
BERR#
BINIT#
BNR#
Low
Low
Low
Low
Low
Low
High
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
PICCLK
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
APIC I/O
ADS#+3
Always
Always
Always
Always
Always
Always
HIT#
HITM#
PICD[1:0]
80
Datasheet
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