RD38F4050L0ZBQ0 [INTEL]
Memory Circuit, Flash+PSRAM, 16MX16, CMOS, PBGA88, 8 X 10 MM, SCSP-88;
| 型号： | RD38F4050L0ZBQ0 |
| 厂家： | 
INTEL |
| 描述： | Memory Circuit, Flash+PSRAM, 16MX16, CMOS, PBGA88, 8 X 10 MM, SCSP-88 静态存储器 内存集成电路 |
| 文件： | 总54页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
£
Intel StrataFlash Wireless Memory
System (LV18/LV30 SCSP)
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
Product Features
■ Device Architecture
■ xRAM Performance
—Code and data segment: 128- and 256-
Mbit density; PSRAM: 32- and 64-Mbit
density; SRAM: 8 Mbit density.
—PSRAM at 1.8 V I/O : 85 ns initial
access, 30 ns async page reads; 65 ns
initial access, 18 ns async page.
—Top or bottom parameter configuration.
—Asymmetrical blocking structure.
—SRAM at 1.8 or 3.0 V I/O: 70 ns initial
access.
■ Flash Performance
—16-KWord parameter blocks (Top or
Bottom); 64-K Word main blocks.
—Code Segment at 1.8 V I/O: 85 ns initial
access; 25 ns async page read; 14 ns
sync reads (tCHQV); 54 MHz CLK.
—Zero-latency block locking.
—Absolute write protection with block
lock down using F-WP#.
—Data Segment at 1.8 V I/O: 170 ns initial
access; 55 ns async page read.
■ Device Voltage
■ Flash Architecture
—Core: VCC = 1.8 V (typ).
—Hardware Read-While-Write/Erase.
—8-Mbit or 16-Mbit Multi-Partition.
—I/O: VCCQ = 1.8 V or 3.0 V (typ).
■ Device Concurrent Operations (3 Dies)
—Buffered EFP: 600 KB per second.
—2-Kbit One-Time Programmable (OTP)
Protection Register.
—Erase Performance: 384 KB per second
(main blocks).
—Software Read-While-Write/Erase.
—Single Full-Die Partition size.
■ Flash Software
£
■ Device Packaging
—88 balls (8 x 10 active ball matrix).
—Area: 8 x 10 mm or 8 x 11 mm.
—Height: 1.0 mm to 1.4 mm.
£
£
—Intel FDI, Intel PSM, and Intel
VFM.
—Common Flash Interface (CFI).
—Basic/Extended Command Set.
■ Quality and Reliability
—Extended Temp: –25 °C to +85 °C.
—Minimum 100 K flash block erase cycle.
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
with Asynchronous Static RAM device offers a high performance code and large embedded data
segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
µm ETOX™ VIII flash technology. The code segment flash die features 1.8 V low-power
operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
low-power operations optimized for cost sensitive asynchronous data applications. This device
integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
compatible with other SCSP families using the QUAD+ ballout package.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
253852-002
December 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LV18/LV30 SCSP datasheet may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2003
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................5
1.1
1.2
1.3
Nomenclature .......................................................................................................................5
Acronyms..............................................................................................................................7
Conventions..........................................................................................................................7
2.0 Functional Overview .....................................................................................................................9
2.1 Device Description................................................................................................................9
3.0 Package Information ...................................................................................................................11
3.1
3.2
3.3
3.4
3.5
One- and Two-Die SCSP....................................................................................................11
Four-Die SCSP ...................................................................................................................12
One-Die Intel£ UT-SCSP...................................................................................................13
Two-Die Intel£ UT-SCSP...................................................................................................14
Three-Die Intel£ UT-SCSP ................................................................................................15
4.0 Ballout and Signal Descriptions ................................................................................................16
4.1 Signal Descriptions .............................................................................................................18
5.0 Maximum Ratings and Operating Conditions...........................................................................21
5.1
5.2
Absolute Maximum Ratings ................................................................................................21
Operating Conditions ..........................................................................................................22
6.0 Electrical Specifications .............................................................................................................23
6.1 DC Current Characteristics.................................................................................................23
7.0 AC Characteristics ......................................................................................................................25
7.1
7.2
7.3
7.4
7.5
7.6
SCSP Device AC Test Conditions ......................................................................................25
SRAM and PSRAM Capacitance........................................................................................25
SRAM AC Read Specifications...........................................................................................25
SRAM AC Write Specifications...........................................................................................27
PSRAM AC Read Specifications ........................................................................................30
PSRAM AC Write Specifications ........................................................................................32
8.0 Power and Reset Specifications ................................................................................................34
9.0 Design Guide: Operation Overview ...........................................................................................35
9.1
9.2
Bus Operations ...................................................................................................................35
Flash Device Commands and Command Definitions .........................................................36
Datasheet
3
Contents
10.0 Flash Read Operation ................................................................................................................. 37
11.0 Flash Program Operation ........................................................................................................... 37
12.0 Flash Erase Operation ................................................................................................................ 37
13.0 Flash Suspend and Resume Operations................................................................................... 37
14.0 Flash Block Locking and Unlocking Operations...................................................................... 37
15.0 Flash Protection Register Operation......................................................................................... 37
16.0 Flash Configuration Operation................................................................................................... 37
17.0 Dual Operation Considerations..................................................................................................38
17.1 Product Configurations and Memory Partitioning ............................................................... 38
17.2 Product Segment Unique Features .................................................................................... 39
17.3 Flash Die Memory Map....................................................................................................... 40
18.0 PSRAM Operations...................................................................................................................... 45
18.1 PSRAM Power-up Sequence and Initialization................................................................... 45
18.2 PSRAM Mode Register....................................................................................................... 45
18.2.1 PSRAM Mode Register Setting .............................................................................46
18.2.2 Cautions for Setting PSRAM Mode Register ......................................................... 47
18.3 PSRAM Low-Power Mode..................................................................................................48
Appendix A Write State Machine ........................................................................................................ 49
Appendix B Common Flash Interface................................................................................................. 49
Appendix C Flash Flowcharts .............................................................................................................49
Appendix D Additional Information .................................................................................................... 50
Appendix E Ordering Information....................................................................................................... 51
Revision History
Date
Revision
Description
10/03r
-001
Initial Release
In the Valid Combinations Table: Added line item mehcanical
and ordering information for 256L+256V+64P+64P. Deleted
the TBD 5-die stack option. Revised the Matrix table.
12/03
-002
4
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
1.0
Introduction
This document provides information about the Intel StrataFlash® Wireless Memory System (LV18/
LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device, including
information on the features, characteristics, operations, and specifications for:
• Code and data segment flash dies
• SRAM and PSRAM dies
The intent of this document is to provide information where this 768-Mbit LVQ Family with
Asynchronous Static RAM Stacked Chip Scale Package (SCSP) device differs from the Intel
StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit LV Family device. Refer
to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP; 1024-
Mbit LV Family Datasheet (order number 253854) for flash product details not included in this
document.
1.1
Nomenclature
0x
0b
Hexadecimal prefix
Binary prefix
Byte
CFI
DU
8 bits
Common Flash Interface
Don’t Use
ETOX
k (noun)
Kb
EPROM Tunnel Oxide
1 thousand
1024 bits
KB
1024 bytes
Kword
M (noun)
Mb
1024 words
1 million
1,048,576 bits
1,048,576 bytes
One-time Programmable
Read Configuration Register
Reserved for Future Use
Stacked Chip Scale Package
Status Register
MB
OTP
RCR
RFU
SCSP
SR
SRD
Word
Status Register Data
16 bits
1.8 V Core
1.8 V I/O
Asserted
Deasserted
High-Z
range of 1.7 V – 1.95 V
range of 1.7 V – 1.95 V
Signal with logical voltage level VIL, or enabled
Signal with logical voltage level VIH, or disabled
Tri-stated or High Impedance
Driven
Low-Z
Datasheet
5
768-Mbit LVQ Family with Asynchronous Static RAM
Non-Array Reads
Flash reads which return flash Device Identifier, CFI Query, Protection
Register and Status Register information
Program
Write
An operation to Write data to the flash array
Bus cycle operation at the inputs of the flash die, in which a command
or data are sent to the flash array
Block
Group of cells, bits, bytes or words within the flash memory array that
get erased with one erase instruction
Parameter block
Main block
Any 16-Kword flash array block.
Any 64-Kword flash array block.
Top parameter
Previously referred to as a top-boot device, a device with flash
parameter partition located at the highest physical address of its
memory map for processor system boot up.
Bottom parameter
Previously referred to as a bottom-boot device, a device with flash
parameter partition located at the lowest physical address of its memory
map for processor system boot up.
Bottom-Top parameter Stacked-CSP device configuration of two flash dies in the same
segment arranged with the parameter partitions located at the lowest
and highest physical address of its memory map.
Partition
A group of flash blocks that shares common status register read state.
A flash partition containing parameter and main blocks.
A flash partition containing only main blocks.
Parameter partition
Main partition
Die
Individual physical flash die used in a stacked-CSP memory subsystem
device
Segment
A section of the SCSP memory subsystem divided for different
operating characteristics. The SCSP memory subsystem has three
segments: a code segment, a data segment, and an xRAM segment.
Code segment
Data segment
A segment that contains one or two flash memory dies optimized for
fast code or data reads. Each die features multi-partition synchronous
read-while-write or burst read-while-erase capability.
A segment contains one or two flash memory dies optimized for large
embedded data. Each die feature single-partition asynchronous read,
write, and erase operations.
xRAM segment
Subsystem
Device
A segment contains one or two xRAM memory dies. The xRAM
combinations could include SRAM, PSRAM, or LPSDRAM.
A stacked memory integration concept made up of multiple memory
dies arranged in Code, Data, and xRAM segments.
An individual flash die or a flash + xRAM SCSP.
6
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
1.2
Acronyms
Buffered-EFP
CUI
Buffered Enhanced Factory Programming
Command User Interface
OTP
One-Time Programmable
Protection Lock Register
PLR
PR
Protection Register
RCR
Read Configuration Register
Reserved for Future Use (all unused active signals in a package ballout)
Status Register
RFU
SR
WSM
APS
Write State Machine
Automatic Power Savings
Common Flash Interface
CFI
MLC technology
RWE
Multi-Level-Cell technology
Read-While-Erase
RWW
Read-While-Write
1.3
Conventions
VCC
VCC
Set
Signal or voltage connection
Signal or voltage level
Logical one (1)
Clear
0x
Logical zero (0)
Hexadecimal number prefix
Binary number prefix
0b
SR[4]
Denotes an individual flash status register bit, in this case bit 5 of
SR[7:0].
D[15:0]
A5
Denotes a group of similarly named signals, such as data bus.
Denotes one element of a signal group membership, in this case address
bit 5.
F[3:1]-CE#, F[2:1]-OE# This is the method used to refer to more than one chip-enable or output
enable at the same time. When each is referred to individually, the
reference will be F1-CE# and F1-OE# (for die #1), F2-CE# and F2-OE#
(for die #2), and F3-CE# and F3-OE#(for die #3). “F” denotes the flash
specific signal and “CE#” is the root signal name of the flash die. Other
Datasheet
7
768-Mbit LVQ Family with Asynchronous Static RAM
notation includes: “S” to denote SRAM, “P” to denote PSRAM, “D” to
denote LPSDRAM, and “R” to denote common RAM type signal
names.
ADV#
Denotes a global signal of the device, Address Valid because there is no
die specific reference.
8
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
2.0
Functional Overview
This section provides an overview of the code and embedded data segment features and
capabilities of the 768-Mbit LVQ Family with Asynchronous Static RAM device.
2.1
Device Description
The 768-Mbit LVQ Family with Asynchronous Static RAM device incorporates flash dies used as
code segment flash memory and large embedded data segment flash memory, along with xRAM
for a high performance, cost-effective high density memory system solution. This stacked device
uses the latest Intel StrataFlash® Wireless Memory System on 0.13 µm ETOX™ VIII process
technology.
The code segment is a high performance, multi-partition, synchronous burst-mode Read-While-
Write (RWW) or Read-While-Erase (RWE) flash memory die, while the large, embedded data
segment is a cost efficient, single-partition, asynchronous flash memory die.
The package for this device is available in a QUAD+ ballout, which supports flash only or flash +
PSRAM and/or SRAM stacked memory combinations. The SCSP in a QUAD+ ballout with a 0.8
mm ball pitch, 8x10 active ball matrix supports a memory subsystem up to 66 MHz on a x16-bit
bus width. See Figure 1, “LV18/LV30 device family block diagram” on page 9 for device block
diagram.
Figure 1. LV18/LV30 device family block diagram
LVQ Family
Code Segment
Data Segment
F1-CE#
F2-CE#
Flash Die # 1
(128- or 256-Mbit)
Flash Die # 2
(128- or 256-Mbit)
F-WE#
F[2:1]-OE#
F-RST#
F-VCC
F-VPP
Optional Flash Die # 3
(128- or 256-Mbit)
Optional Flash Die # 3
(128- or 256-Mbit)
F3-CE#
F3-CE#
VSS
VCCQ
F-WP#
CLK
A[MAX:MIN]
ADV#
WAIT
D[15:0]
xRAM Segment
S-VCC
P-VCC
S-CS1#
S-CS2
R-UB#
R-LB#
Die # 1
32- 64- or 128-
Mbit PSRAM
Die # 2
64- or 128-Mbit
PSRAM
P[2:1]-CS#
R-OE#
Die # 3
8-Mbit SRAM
P-MODE
/ P-CRE
R-WE#
Datasheet
9
768-Mbit LVQ Family with Asynchronous Static RAM
The 768-Mbit LVQ Family with Asynchronous Static RAM device consists of a 1.8 V flash
memory device with 1.8 V and 3.0 V I/O options. As shown in Figure 1, “LV18/LV30 device
family block diagram” on page 9, the device is available with a minimum of one flash die each per
code segment and data segment (flash die # 1 and flash die #2). An optional third flash die is
available for either the code or data segment. See Table 1, “768 Mbit LVQ Family Matrix” on
page 10 for possible combinations.
Designed for low-voltage systems, the LVQ supports read operations with F-VCC at 1.8 V, and
erase and program operations with F-Vpp at 1.8 V. Buffered Enhanced Factory Programming
(Buffered-EFP) provides the fastest flash array programming performance, with elevated F-VPP at
9.0 V to increase factory throughput. With F-VPP at 1.8 V, F-Vcc and F-Vcc can be tied together
for a simple, ultra-low-power design. In addition to voltage flexibility, a dedicated F-VPP
connection provides complete data protection when F-Vpp ≤ VPPLK
.
The Intel StrataFlash® Wireless Memory System provides data security through its individual zero-
latency block lock capability. Each memory block can be unlocked, locked, or locked-down by
hardware or software control.
Individualized F-CE# control allows the user to manage which flash die is asserted, furthering the
flexibility of power management while controlling data integrity per segment with F-WP#. The
F[2:1]-OE# in LVQ products with QUAD+ ballout are common internally
Table 1. 768 Mbit LVQ Family Matrix
Line Item
Flash Components
RAM Components
Package Size Notes
256L18 + 256L18
256L18 + 256V18
None
8x11x1.2
11x13x1.4
8x11x1.2
1
1
1
1.8 V I/O
64PS + 64PS
None
3.0 V I/O 256L30 + 256V30
NOTES:
1. Available in Top or Bottom Configurations.
10
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
3.0
Package Information
The 768-Mbit LVQ Family with Asynchronous Static RAM device is available with various die
combinations in both the standard Stacked Chip Scale Package (SCSP) and the Intel® Ultra-Thin
Stacked Chip Scale Package (Intel® UT-SCSP).
3.1
One- and Two-Die SCSP
Figure 2. Mechanical Specifications for One/Two-Die SCSP (8x10 mm)
A1 Index
Mark
S1
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
1
S2
A
A
B
C
D
B
C
D
E
F
E
F
D
e
G
G
H
H
J
J
K
K
L
L
M
M
b
E
Bottom View - Ball
Up
Top View - Ball Down
A2
A1
A
Y
Draw ing not to scale.
Millimeters
Nom
Inches
Nom
Di me ns ions
Pa ckage Height
Ball Height
Pa ckage Body Thickne ss
Ball (Lead) Width
Pa ckage Body Length
Pa ckage Body Width
Pitch
S ymbol
A
A1
A2
b
D
E
e
N
Mi n
Max Not e s
1.200
Min
Max
0.0472
0.200
0.0079
0.860
0.375
10.000
8.000
0.800
88
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.325
9.900
7.900
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
Ball (Lead) Count
Se ating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
0.700
0.0039
0.0512
0.0276
1.100
0.500
1.200
0.600
0.0433
0.0197
0.0472
0.0236
Datasheet
11
768-Mbit LVQ Family with Asynchronous Static RAM
3.2
Four-Die SCSP
Figure 3. Mechanical Specifications for Four-Die SCSP (11x13 mm)
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
D
e
G
G
H
J
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball Up
A
Top View - Ball Down
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Symbol
Min
Max Notes
1.400
Min
Max
0.0551
A
A1
A2
b
D
E
e
N
Y
S1
S2
0.200
0.0079
1.070
0.375
13.000
11.000
0.800
88
0.0421
0.0148
0.5118
0.4331
0.0315
88
0.325
12.900
10.900
0.425
13.100
11.100
0.0128
0.5079
0.4291
0.0167
0.5157
0.4370
0.100
2.800
2.200
0.0039
0.1102
0.0866
2.600
2.000
2.700
2.100
0.1024
0.0787
0.1063
0.0827
12
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
£
One-Die Intel UT-SCSP
3.3
Figure 4. Mechanical Specifications for One-Die Intel® UT-SCSP (8x11 mm)
A1 Index
Mark
S1
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
1
S2
A
A
B
C
B
C
D
E
F
D
E
F
D
e
G
H
G
H
J
J
K
K
L
L
M
M
b
E
Top View - Ball Down
Bottom View - Ball Up
A
A2
A1
Y
Drawing not to scale.
Note: Dimensions A1, A2, and b are preliminary
Millimeters
Nom
Inches
Nom
Dimensions
Symbol
Min
Max Notes
Min
Max
Package Height
Ball Height
A
A1
A2
b
D
E
1.00
0.0394
0.117
0.0046
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
0.740
0.350
11.00
8.00
0.80
88
0.0291
0.0138
0.4331
0.3150
0.0315
88
0.300
10.900
7.900
0.400
11.100
8.100
0.0118
0.4291
0.3110
0.0157
0.4370
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
1.200
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
Datasheet
13
768-Mbit LVQ Family with Asynchronous Static RAM
£
Two-Die Intel UT-SCSP
3.4
Figure 5. Mechanical Specifications for Two-Die Intel® UT-SCSP (8x11 mm)
A1 Index
Mark
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
A
B
C
D
B
C
D
E
F
G
H
J
E
F
D
e
G
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball
Up
Top View - Ball Down
A2
A1
A
Y
Draw ing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Pa ckage Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Pa ckage Body Length
Package Body Width
Pitch
Symbol
Min
Max Notes
1.200
Min
Max
0.0472
A
A1
A2
b
D
E
0.200
0.0079
0.860
0.375
11.000
8.000
0.800
88
0.0339
0.0148
0.4331
0.3150
0.0315
88
0.325
10.900
7.900
0.425
11.100
8.100
0.0128
0.4291
0.3110
0.0167
0.4370
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corne r to Ball A1 Distance Along E
Corne r to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
1.200
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
14
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
£
Three-Die Intel UT-SCSP
3.5
Figure 6. Mechanical Specifications for Three-Die Intel® UT-SCSP (8x11 mm)
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
A
B
C
D
B
C
D
E
F
E
F
D
e
G
H
J
G
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball
Up
Top View - Ball Down
A2
A1
A
Y
Draw ing not to scale.
Note:DimensionsA1,A2,andbarepreliminary
Millimeters
Nom
Inches
Nom
Dimens ions
S ymbol
Mi n
Max Notes
Min
Max
Package Height
Ball Height
A
A1
A2
b
D
E
1.20
0.0472
0.117
0.0046
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
0.910
0.350
11.00
8.00
0.80
88
0.0358
0.0138
0.4331
0.3150
0.0315
88
0.300
10.900
7.900
0.400
11.100
8.100
0.0118
0.4291
0.3110
0.0157
0.4370
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
1.200
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
Datasheet
15
768-Mbit LVQ Family with Asynchronous Static RAM
4.0
Ballout and Signal Descriptions
Figure 7, “QUAD+ Signal Ballout for LVQ Device Family” shows the signal ballout for the 768-
Mbit LVQ Family with Asynchronous Static RAM device, ideal for space-constrained board
applications and allowing density upgrades without PCB redesign. The user is responsible to adapt
for density upgrade flexibility in the PCB design.
16
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 7. QUAD+ Signal Ballout for LVQ Device Family
1
2
3
4
5
6
7
8
DU
DU
DU
DU
A
B
C
D
E
F
A4
A5
A18
R-LB#
A17
A7
A19
A23
A24
A25
VSS
VSS
F1-VCC F2-VCC
A21
A22
A9
A11
A12
A13
A15
A16
S-CS2
CLK
F-VPP,
F-VPEN
A3
R-WE# P1-CS#
A2
F-WP#
ADV#
A20
A8
A10
A14
A1
A6
R-UB# F-RST# F-WE#
G
H
J
A0
D8
D2
D1
D9
D10
D3
D5
D12
D4
D13
D14
D6
WAIT F2-CE#
R-OE#
D0
D7
F2-OE#
VCCQ
S-CS1# F1-OE#
D11
D15
K
L
P-Mode,
P-CRE
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ
VSS
DU
VSS
DU
VCCQ F1-VCC
VSS
VSS
VSS
DU
VSS
DU
M
Top View - Ball Side Down
Legend:
SRAM/PSRAM specific
Flash specific
Global
Datasheet
17
768-Mbit LVQ Family with Asynchronous Static RAM
4.1
Signal Descriptions
Table 2 describes the active signals used on the 768-Mbit LVQ Family with Asynchronous Static
RAM device.
Table 2. Signal Descriptions (Sheet 1 of 3)
Symbol
Type
Description
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
•
•
•
•
•
256-Mbit Die : AMAX= A23
128-Mbit Die : AMAX = A22
64-Mbit Die : AMAX = A21
32-Mbit Die : AMAX = A20
8-Mbit Die : AMAX = A18
A[MAX:MIN]
Input
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future device densities.
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs
data during read cycles. Data signals float when the device or its outputs are
deselected. Data are internally latched during writes on the flash device.
Input/
Output
D[15:0]
FLASH CHIP ENABLE: Low-true input.
F[3:1]-CE# low selects the associated flash memory die. When asserted, flash
internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby
levels, data and WAIT outputs are placed in high-Z state.
F[3:1]-CE#
Input
F1-CE# selects or deselects flash die #1; F2-CE# selects or deselects flash die #2
and is RFU on combinations with only one flash die. F3-CE# selects or deselects
flash die #3 and is RFU on stacked combinations with only one or two flash dies.
SRAM CHIP SELECT: Low-true / high-true input (S-CS1# / S-CS2 respectively).
When either/both SRAM Chip Select signals are asserted, SRAM internal control
logic, input buffers, decoders, and sense amplifiers are active. When either/both
Input SRAM Chip Select signals are deasserted, the SRAM is deselected and its power is
reduced to standby levels.
S-CS1#
S-CS2
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are
RFU on stacked combinations without SRAM die.
PSRAM CHIP SELECT: Low-true input.
When asserted, PSRAM internal control logic, input buffers, decoders, and sense
amplifiers are active. When deasserted, the PSRAM is deselected and its power is
reduced to standby levels.
P[2:1]-CS#
F[2:1]-OE#
Input
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with
PSRAM die. This ball is an RFU on stacked combinations without PSRAM. P2-CS#
selects PSRAM die #2 and is available only on stacked combinations with two
PSRAM dies. This ball is an RFU on stacked combinations without PSRAM or with a
single PSRAM.
FLASH OUTPUT ENABLE: Low-true input.
F[2:1]-OE# low enables the flash output buffers. F[2:1]-OE# high disables the flash
output buffers, and places the selected flash outputs in High-Z.
Input
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die
#2 and flash die #3. F2-OE# is available on stacked combinations with two or three
flash die and is RFU on stacked combinations with only one flash die.
18
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 2. Signal Descriptions (Sheet 2 of 3)
RAM OUTPUT ENABLE: Low-true input.
R-OE# low enables the selected RAM output buffers. R-OE# high disables the RAM
Input output buffers, and places the selected RAM outputs in High-Z.
R-OE#
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an
RFU on flash-only stacked combinations.
FLASH WRITE ENABLE: Low-true input.
F-WE#
R-WE#
Input
Input
F-WE# controls writes to the selected flash die. Address and data are latched on the
rising edge of F-WE#.
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SRAM die and is an
RFU on flash-only stacked combinations.
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read
mode and increments the internal address generator.
During synchronous read operations, addresses are latched on the rising edge of
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
CLK
Input
In asynchronous mode, addresses are latched on the rising edge ADV#, or are
continuously flow-through when ADV# is kept asserted.
WAIT: Output signal.
Indicates data is valid in synchronous array or non-array sync flash reads.
Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted.
With F-CE# and F-OE# at VIL, WAIT’s active output is VOL or VOH. WAIT is high-Z if
WAIT
Output
F-CE# or F-OE# is VIH
.
•
In synchronous array or non-array flash read modes, WAIT indicates invalid data
when asserted and valid data when deasserted.
•
In asynchronous flash page read, and all flash write modes, WAIT is deasserted.
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash
die.
F-WP#
ADV#
Input
Input
•
F-WP# low enables the lock-down mechanism where locked down blocks cannot
be unlocked with software commands.
•
F-WP# high disables the lock-down mechanism, allowing locked down blocks to
be unlocked with software commands.
ADDRESS VALID: Low-true input.
During synchronous flash read operations, addresses are latched on the rising edge
of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous flash read operations, addresses are latched on the rising edge of
ADV#, or are continuously flow-through when ADV# is kept asserted.
RAM UPPER / LOWER BYTE ENABLES: Low-true input.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on
Input D[15:8], and R-LB# low enables the RAM low-order bytes on D[7:0].
R-UB#
R-LB#
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die
and are RFU on flash-only stacked combinations.
FLASH RESET: Low-true input.
F-RST# low initializes flash internal circuitry and disables flash operations. F-RST#
Input
F-RST#
high enables flash operation. Exit from reset places the flash in asynchronous read
array mode.
Datasheet
19
768-Mbit LVQ Family with Asynchronous Static RAM
Table 2. Signal Descriptions (Sheet 3 of 3)
P-Mode (PSRAM Mode): Low-true input.
P-MODE is used to program the configuration register, and enter/exit Low-Power
Mode of PSRAM die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-Mode,
P-CRE
Input
P-CRE (PSRAM configuration register enable): High-true input.
P-CRE is high, write operations load the refresh control register or bus control
register.
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE s RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables
flash program/erase operations.
Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK
Power (VPENLK). Erase / program operations at invalid F-VPP (F-VPEN) voltages should not
be attempted. Refer to flash discrete product datasheet for additional details.
F-VPP,
F-VPEN
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP
products.
FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1;
F2-VCC supplies power to the core logic of flash die #2 and flash die #3. Write
operations are inhibited when F-VCC < VLKO. Device operations at invalid F-VCC
F[2:1]-VCC
Power
voltages should not be attempted.
F2-VCC is available on stacked combinations with two or three flash dies, and is an
RFU on stacked combinations with only one flash die.
SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC
P-VCC
Power
Power
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked
combinations without SRAM die.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked
combinations without PSRAM die.
VCCQ
VSS
Power DEVICE I/O POWER: Supply power for the device input and output buffers.
Power DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserved for future device functionality/
enhancements. Contact Intel regarding the use of balls designated RFU.
RFU
DU
Don’t Use: Do not connect to any other signal, or power supply; must be left floating.
20
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
NOTICE: This document contains information available at the time of its release. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet
before finalizing a design.
Table 3. Absolute Maximum Ratings
Parameter
MIN
MAX
Unit
Notes
Temperature under Bias Expanded
Storage Temperature
–25
–55
+85
°C
°C
5
5
+125
Voltage On Any Signal (except F-VCC, VCCQ, F-VPP,
S-VCC, and P-VCC)
–0.5
+3.6
V
1,5
F-VCC Voltage
–0.2
–0.2
–0.2
–0.2
–
+2.50
+2.50
+3.60
+10.0
100
V
V
1,5
1.8V I/O
3.0 V I/O
1,5
V
CCQ, P-VCC and S-VCC Voltage
V
1,5
F-VPP Voltage
V
1,2,3,5
4,5
ISH Output Short Circuit Current
NOTES:
mA
1. All specified voltages are relative to VSS. Minimum DC voltage is –0.5 V on input/output signals, –0.2 V
on VCCQ and F-VPP signals. During transitions, this level may overshoot to –2.0 V for periods < 20 ns.
Maximum DC voltage on F-VCC is VCC + 0.5 V, which during transitions may overshoot to F-Vcc +2.0 V
for periods <20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ +0.5 V, which during
transitions may overshoot to VCCQ + 2.0V for periods < 20ns.
2. Maximum DC voltage on F-VPP may overshoot to +10.0 V for periods < 20 ns.
3. Flash program/erase voltage (F-VPP) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V
for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total.
Operation with 9.0 V program/erase voltage may reduce flash block cycling capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Absolute DC specifications applies to each flash and RAM die in the SCSP device.
Datasheet
21
768-Mbit LVQ Family with Asynchronous Static RAM
5.2
Operating Conditions
Table 4. Extended Temperature Operation
Flash + Flash Flash + PSRAM Flash + PSRAM + SRAM2
Symbol
Parameter
MIN
MAX
MIN
MAX
MIN
MAX
T
Operating Temperature
–25
+85
–25
+85
–25
+85
°C
C
F-V
Flash Supply Voltage
Flash I/O Voltage
1.7
2.2
2.0
3.3
1.7
2.7
2.0
3.1
1.7
2.7
2.0
3.1
V
V
CC
3.0 V I/O
1.8 V I/O
V
CCQ
P-V
S-V
PSRAM and SRAM Supply
Voltage
CC
CC
1.7
2.0
1.8
1.95
–
–
V
1
V
F-VPP Voltage Supply (Logic Level)
Factory word programming F-VPP
0.9
8.5
2
0.9
8.5
2
0.9
8.5
2
V
V
PPL
1
V
9.5
9.5
9.5
PPH
NOTES:
1. Flash program/erase voltage (F-VPP) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V for 1000 cycles on
main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. Operation with 9.0 V program/erase
voltage may reduce flash block cycling capability.
2. SRAM is available only in 3.0 V I/O option.
22
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
6.0
Electrical Specifications
6.1
DC Current Characteristics
The DC current characteristics referenced in this document are for individual flash and RAM die in
the SCSP device. The total device current is determined by sum of the active and inactive currents
of each flash and RAM die in the SCSP device.
Note: Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for flash DC characteristics not included
in this document.
SRAM DC characteristics are shown in Table 5. PSRAM DC characteristics are shown in Table 6
on page 24.
NOTICE: Individual DC Characteristics of all dies in a SCSP device need to be considered
accordingly, depending on the SCSP device stacked combinations and operations.
Table 5. SRAM DC Characteristics
3.0 V SRAM
Parameter
Description
Test Conditions
Unit
MIN
MAX
3.3
–
S-V
Voltage Range
–
–
2.7
1.5
V
V
CC
V
S-VCC for Data Retention
DR
Operating Current at minimum cycle
time
I
I
IO = 0 mA
–
–
50
10
mA
mA
CC
Operating Current at maximum
cycle time (1 µs)
I
IIO = 0 mA
CC2
S-CS1#
≥
S-VCC-0.2V
≤ VSS+0.2V
or S-CS2
I
I
Standby Current
–
–
25
µ
µ
A
A
SB
Address/Data toggling at minimum
cycle time
Current in Data Retention mode
Output High Voltage
S-VCC = 1.5 V
12
–
DR
S-VCC
0.1
-
-
V
IOH = -100
µ
A
V
OH
IOL = 100
µA,
V
Output Low Voltage
Input High Voltage
-0.1
0.1
V
OL
VCCMIN
S-VCC
0.4
S-VCC
0.2
+
V
–
V
V
IH
V
*I
Input Low Voltage
–
-0.2
-1
0.6
+1
IL
Input Leakage Current
-0.2 < VIN < S-VCC+0.2 V
µ
A
A
IL
-0.2 < VIN < S-VCC+0.2 V
S-VCC = VDR
Input Leakage Current in Data
Retention Mode
*I
-1
+1
µ
LDR
NOTE: * Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.
Datasheet
23
768-Mbit LVQ Family with Asynchronous Static RAM
Table 6. PSRAM DC Characteristics
P-V = 1.8 V to 1.95 V
P-V = 2.7 V to 3.1 V
CC
CC
Parameter Description
Test Conditions
Unit
MIN
Typ
MAX
MIN
Typ
MAX
Operating
Current at
minimum
cycle time
I
IOUT=0mA
–
–
–
35
–
–
45
mA
CC
P-CS#
≥
P-VCC
-
≥
32-Mbit
64-Mbit
90
100
–
–
90
100
150
µ
µ
A
A
Standby
Current
I
0.2V,P-Mode
P-VCC-0.2V
SB1
N/A
110
16-Mbit
–
–
–
–
60
50
40
20
70
60
50
30
–
–
–
–
–
–
–
–
–
60
50
40
20
90
80
70
60
20
70
60
µ
µ
µ
µ
µ
µ
µ
µ
µ
A
A
A
A
A
A
A
A
A
8-Mbit
4-Mbit
0-Mbit
16-Mbit
8-Mbit
4-Mbit
0-Mbit
32-
Mbit
50
Partial Array
Refresh
Current
P-CS#
≥ P-VCC-
30
0.2V,
I
SB2
110
100
90
(Standby
Mode 2)
P-Mode
≤
0.2V
64-
Mbit
N/A
80
P-CS#
≥
P-VCC
-
32-Mbit
64-Mbit
–
20
30
30
Deep Power
Down
0.2V,
I
SBD
N/A
–
60
–
80
–
µ
A
P-Mode
≤
0.2V
Output High
Voltage
V
IOH = -0.5 mA
IOL = 1 mA
0.8VCCQ
–
–
–
–
0.8VCCQ
V
OH
Output Low
Voltage
V
0.2VCCQ
–
–
–
–
0.2VCCQ
V
V
V
OL
VCCQ
+ 0.3
Input High
Voltage
VCCQ
0.3
+
V
–
–
0.8VCCQ
-0.3
–
–
0.8VCCQ
-0.3
IH
Input Low
Voltage
V
*I
0.2VCCQ
+1.0
0.2VCCQ
+1.0
IL
IL
Input
Leakage
Current
VIN = 0V to VCCQ
–1.0
–1.0
–
–
–1.0
–1.0
–
–
µ
A
A
V
I/O = 0V to VCCQ
P-CS# = VIH or
R-WE# = VIH or
R-OE# = VIH
,
Input/Output
Leakage
Current
*I
+1.0
+1.0
µ
OL
NOTE: * VIN: Input voltage, VI/O: Input/Output voltage.
24
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
7.0
AC Characteristics
7.1
SCSP Device AC Test Conditions
Figure 8. Transient Equivalent Testing Load Circuit1,2
ZO = 50 Ohms
I/O
Output
CL =
30pf
50
Ohms
P_VCC/2 = VCCQ/2
NOTES:
1. Test configuration component value for worst case speed conditions.
2. CL includes jig capacitance.
7.2
SRAM and PSRAM Capacitance
SRAM and PSRAM capacitance is shown in Table 7, “SRAM and PSRAM Capacitance” on
page 25.
Note: Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for flash capacitance details not included
in this document.
Table 7. SRAM and PSRAM Capacitance
MAX
(SRAM)
MAX
(PSRAM)
Symbol
Parameter
Unit
Condition
CIN
COUT
Input Capacitance
Output Capacitance
6
7
8
pF
pF
VIN = 0 V
VOUT = 0 V
10
NOTE: Sampled, not 100% tested. TC = +25 °C, f = 1 MHz.
7.3
SRAM AC Read Specifications
Note: Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for flash details not included in this
document.
Datasheet
25
768-Mbit LVQ Family with Asynchronous Static RAM
Table 8. SRAM AC Read Specifications
#
Symbol
Parameter
MIN
MAX
Unit
Notes
R1
R2
R3
R3
R4
R5
R6
R7
R8
R9
tRC
tAA
Read Cycle Time
70
–
–
–
–
–
5
0
0
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Output Delay
S-CS1# to Output Delay
70
70
70
35
70
–
tCO1
tCO2
tOE
S-CS2 to Output Delay
R-OE# to Output Delay
tBA
R-UB#, R-LB# to Output Delay
S-CS1# or S-CS2 to Output in Low-Z
R-OE# to Output in Low-Z
S-CS1# or S-CS2 to Output in High-Z
R-OE# to Output in High-Z
tLZ
1,2
1
tOLZ
tHZ
–
25
25
1,2,3
1,3
tOHZ
Output Hold (from Address, S-CS1#,
S-CS2, or R-OE# Change, whichever
Occurs First)
R10
tOH
0
–
ns
R11
tBLZ
tBHZ
R-UB#, R-LB# to Output in Low-Z
R-UB#, R-LB# to Output in High-Z
0
0
–
ns
ns
1
1
R12
25
NOTES:
1. Sampled, not 100% tested.
2. At any given temperature and voltage condition, tHZ (MAX) is less than tLZ (MAX) for a given device and
from device-to-device interconnection.
3. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referenced to output voltage levels.
26
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 9. SRAM Read Waveform
Device
Data Valid
Standby
Address Selection
VIH
Address Stable
R1
VIL
VIH
S-CS1#
VIL
VIH
S-CS2
R3
VIL
R2
R8
VIH
R- O E #
VIL
R9
VIH
R-WE#
VIL
R4
R7
R10
VOH
R6
R11
High Z
High Z
DATA
Valid Output
VOL
VIH
R12
R5
-
R UB#, R-LB#
VIH
7.4
SRAM AC Write Specifications
Table 9. SRAM AC Write Specifications (Sheet 1 of 2)
#
Symbol Parameter
tWC Write Cycle Time
MIN
MAX
Unit
Notes
W1
70
0
–
–
ns
1
3
1
Address Setup to R-WE# (S-CS1#) and R-
UB#,R-LB# Going Low
W2
tAS
ns
W3
W4
tWP
tDW
R-WE# (S-CS1#) Pulse Width
Data to Write Time Overlap
55
30
–
–
ns
ns
Address Setup to R-WE# (S-CS1#) Going
High
W5
tAW
60
–
ns
S-CS1# (R-WE#) Setup to R-WE# (S-CS1#)
Going High
W6
W7
tCW
tDH
60
0
–
–
ns
ns
2
Data Hold from R-WE# (S-CS1#) High
Datasheet
27
768-Mbit LVQ Family with Asynchronous Static RAM
Table 9. SRAM AC Write Specifications (Sheet 2 of 2)
W8
tWR
Write Recovery
0
–
–
ns
ns
4
R-UB#, R-LB# Setup to R-WE# (S-CS1#)
Going High
W9
tBW
60
NOTES:
1. A write occurs during the S-CS1# and R-WE# asserted overlap (tWP). The write begins with the latest
transition of S-CS1# and R-WE# going low (R-UB# and/or R-LB# already asserted). The write ends at the
earliest transition of S-CS1# or R-WE# going high.
2. tCW is measured from S-CS1# going low to the end of a write.
3. tAS is measured from address valid to the beginning of a write.
4. tWR is measured from the end of a write to the address change; tWR applied in case a write ends as S-
CS1# or R-WE# going high.
Figure 10. SRAM Write Waveform
Device
Address Selection
Standby
VIH
Address Stable
ADDRESSES
S-CS1#
VIL
W1
VIH
W8
VIL
VIH
S-CS2
VIL
W6
VIH
VIL
VIH
VIL
R-OE#
R-WE#
W5
W3
W7
W4
VOH
VOL
High Z
High Z
Data In
W9
DATA
W2
VIH
VIH
R- UB#, R- LB#
Table 10. SRAM Data Retention Timing
Parameter
Description
MIN
MAX
Unit
tSDR
tRDR
Data Retention Set-up Time
0
–
–
ns
ns
Data Retention Recovery Time
70
28
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 11. SRAM Data Retention Waveform (S-CS1# Controlled)
tSDR
tRDR
Data Retention Mode
S-VCC
S-VCCmin
S-VIHmin
VDR
S-CS1#
VSS
Figure 12. SRAM Data Retention Waveform (S-CS2 Controlled)
tSDR
tRDR
Data Retention Mode
S-VCC
S-CS2
S-VCCMIN
VDR
VILMAX
VSS
Datasheet
29
768-Mbit LVQ Family with Asynchronous Static RAM
7.5
PSRAM AC Read Specifications
Table 11. PSRAM AC Read Specifications
P-V = 1.80 V to 1.95 V P-V = 2.7 V to 3.1 V
CC
CC
#
Symbol
Parameter
Unit Note
MIN
MAX
MIN
MAX
Read Cycle
R1
R2
tRC
Read Cycle Time
85*
–
–
85*
85*
65
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
tAA
Address access time
65
R3
tCO
P-CS# Low to Output Valid
–
–
65
R4
tOE
R-OE# Low to Output Valid
–
65
85*
–
45
R5
tBA
R-UB#, R-LB# Low to Output Valid
P-CS# Low to Output in Low-Z
R-OE# Low to Output in Low-Z
P-CS# High to Output in High-Z
R-OE# High to Output in High-Z
Output Hold from Address change
R-UB#, R-LB# Low to Output in Low-Z
R-UB#, R-LB# High to Output in High-Z
Address set to R-OE# low-level
R-OE# high-level to address hold
P-CS# high-level to address hold
R-LB#, R-UB# high-level to address hold
P-CS# low-level to R-OE# low-level
R-OE# low-level to P-CS# high-level
P-CS# high-level pulse width
–
–
65
5
R6
tLZ
10
5
–
10
5
–
R7
tOLZ
tHZ
tOHZ
tOH
–
–
R8
–
25
–
25
R9
–
25
–
25
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
5
–
5
–
tBLZ
tBHZ
tASO
tOHAH
tCHAH
tBHAH
tCLOL
tOLCH
tCP
5
–
5
–
–
25
–
25
0
–
0
–
1
-5
0
–
-5
0
–
–
–
1
1,2
3
0
–
0
–
0
10,000
0
10,000
60
10
10
–
–
45
10
10
–
–
–
–
–
–
tBP
R-UB#, R-LB# high-level pulse width
R-OE# high-level pulse width
tOP
10,000
10,000
3
4
Page Mode
PR1
PR2
tPC
tPA
Page Cycle Time
30
–
–
18
–
–
ns
ns
Page Mode Address Access Time
30
18
NOTES:
1. When R13 ≥ |R15|, |R16| and R19 ≥ 18 ns, the minimum value for R15 and R16 are -15 ns. (See also Figure 13,
“Conditions for Calculating the Minimum Value for R15 and R16” on page 31.)
2. R16 is specified from when both R-LB# and R-UB# become high-level.
3. R17and R21 (MAX) are applied while P-CS# is being hold at low-level.
4. See Figure 14, “AC Waveform for PSRAM Read Operations” on page 31.
5. * 32-Mbit 1.8V PSRAM initial read access timing specifications changed from 85 ns to 88 ns.
30
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 13. Conditions for Calculating the Minimum Value for R15 and R16
R15, R16
Address
R-UB#,R-LB#,
P-CS#
R-OE#
R13
Figure 14. AC Waveform for PSRAM Read Operations
R1
Vih
Address
Vil
R2
Vih
Vil
R3
R5
R4
P-CS#
R8
Vih
Vil
R-UB#,
R-LB#
R12
R9
Vih
Vil
R-OE#
R7
R11
R6
R10
Voh
Vol
Data
out
High-Z
Valid
Output
High-Z
NOTE: In a read cycle, P-Mode and R-WE# should be fixed to high-level.
Datasheet
31
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 15. AC Waveform for PSRAM 8-Word Page Read Operation
R1
Vih
A3-AMAX
Valid
Vil
Vih
Vil
Address
A0,A1,A2
P-CS#
000
001
111
R2
R3
PR1
R-OE#,
R-UB#,
R-LB#
PR2
R4
R9
Voh
Vol
High-Z
Data out
Qn
Qn+ 7
Qn+
6
NOTE: In a page read cycle, P-Mode and R-WE# should be fixed to high-level, and R-UB#, R-LB# are low-level.
7.6
PSRAM AC Write Specifications
Table 12. PSRAM AC Write Specifications
P-V = 1.80 V to 1.95 V P-V = 2.7 V to 3.1 V
CC
CC
#
Symbol
Parameter
Unit Note
MIN
MAX
MIN
MAX
W1
W2
W3
W4
W5
W6
W7
W8
W9
tWC
Write Cycle Time
85
0
–
65
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
1,4
4
tAS
Address Setup Time
–
–
tWP
tDW
tAW
tCW
tDH
tWR
tBW
Write Pulse Width
60
30
70
70
0
–
50
35
55
55
0
–
Data valid to Write End
–
–
4
Address valid to end of write
P-CS# to end of write
–
–
4
–
–
4
Data Hold time
–
–
4
Write Recovery
0
–
0
–
4
R-UB#, R-LB# Setup to end of Write
P-CS# high-level pulse width
R-UB#, R-LB# high-level pulse width
R-WE# high-level pulse width
R-OE# high-level to address hold
P-CS# high-level to address hold
R-UB#, R-LB# high-level to address hold
R-OE# high-level to R-WE# set
R-WE# high-level to R-OE# set
70
10
10
10
-5
0
–
55
10
10
10
-5
0
–
4
W10 tCP
W11 tBP
–
–
1
–
–
W12 tWHP
W13 tOHAH
W14 tCHAH
W15 tBHAH
W16 tOES
W17 tOEH
–
–
–
–
–
–
1
0
–
0
–
1,2
0
10,000
10,000
0
10,000
10,000
3
10
10
NOTES:
1. When W2 ≥ |W14|, |W15| and W10 ≥ 18 ns, W14 and W15 (MIN) are -15 ns. (See also Figure 16, “Conditions for
Calculating the Minimum Value for W14 and W15” on page 33.)
2. W15 is specified from when both R-LB# and R-UB# become high-level.
3. W16 and W17 (MAX) are applied while P-CS# is being hold at low-level.
4. See Figure 17, “AC Waveform for PSRAM Write Operation” on page 33.
32
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 16. Conditions for Calculating the Minimum Value for W14 and W15
W14, W15
Address
R-UB#,R-LB#,
P-CS#
W10
R-WE#
W2
Figure 17. AC Waveform for PSRAM Write Operation
W1
Vih
Address
Vil
W2
W8
Vih
Vil
W6
P-CS#
W5
W9
Vih
Vil
R-UB#,
R-LB#
Vih
Vil
W3
R-WE#
Low-Z
Voh
W4
Valid Data In
W7
High-Z
High-Z
Data I/O
Vol
NOTES:
1. During address transition, at least one of the pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should
be deasserted.
2. Do not input data to the I/O pins while they are in an output state.
3. In a write cycle, P-Mode and R-OE# should be fixed to high-level.
4. Write operation is done during the overlap time of a low-level P-CS#, R-WE#, R-LB# and/or R-UB#.
Datasheet
33
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 18. PSRAM Mode Register Update—Timing Waveform
R1
R1
W1
W1
Address
Highest Address
Highest Address
Highest Address
Highest Address
Mode Register Setting
P-CS#
R-OE#
W8
W7
W8
W3
W3
R-WE#
W7
W4
W4
Data I/O
0000H
000XH
R-UB#, R-LB#
8.0
Power and Reset Specifications
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
34
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
9.0
Design Guide: Operation Overview
9.1
Bus Operations
With F-CE# low and F-RST# high, the flash dies are enabled for normal operations. The flash
device internally decodes upper address inputs to determine the accessed partition or block.
In an asynchronous read operation, addresses are latched when ADV# transition from V to V ,
IL
IH
or continuously flows through if ADV# is held low. In synchronous-burst mode, addresses are
latched by the rising edge of ADV# or the next valid CLK edge when ADV# is low.
Table 13, “Flash + PSRAM + SRAM Bus Operations” summarizes the bus operations and voltage
levels that must be applied to individual flash die in each mode
Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 1 of 2)
Synchronous
Flash
DOUT
1,2,3,4
,5,6,9
Array and Non-
Array Read
H
H
H
L
L
L
H
H
H
L
L
H
H
L
Active
L
L
L
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
Asynchronous
Read
Flash
DOUT
1,2,3,4
,5,6,9
Deasserted
Deasserted
VPP1
or
VPP2
Flash
DIN
Write
H
3,4,6
Flash
Output Disable
Standby
H
H
L
L
H
X
H
H
X
H
X
X
H
X
X
High-Z
High-Z
High-Z
X
X
X
High-Z
High-Z
High-Z
4
4
4
High-Z
Flash
High-Z
Any xSRAM mode allowed
Flash
High-Z
Reset
Synchronous
Array and Non-
Array Read
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
H
H
H
H
H
L
H
H
H
H
H
X
L
L
L
L
H
H
L
Deasserted
Deasserted
Deasserted
High-Z
L
L
X
X
H
H
H
X
X
X
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
Async Read
Write
Vpp1
or
Vpp2
Flash
Die #2 3,4,6
DOUT
L
H
H
X
X
L
Flash#
2 High-
Z
Output Disable
Standby
L
H
X
X
X
X
X
High-Z
High-Z
High-Z
4
4
4
Flash
#2
High-Z
H
X
High-Z
Any xSRAM mode allowed
Flash
#2
High-Z
Reset
High-Z
Datasheet
35
768-Mbit LVQ Family with Asynchronous Static RAM
Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 2 of 2)
PSRAM
DOUT
Read
X
X
H
H
L
L
X
X
X
X
High-Z
High-Z
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
1,3
3
PSRAM
DIN
Write
PSRAM
High-Z
Output Disable
H
X
4
PSRAM
High-Z
Any Flash or SRAM mode allowed
Standby
H
H
L
H
H
H
H
H
H
L
X
X
X
H
X
H
H
H
X
X
L
X
X
H
L
X
X
L
4
Low-Power
Mode
PSRAM
High-Z
4
SRAM
DOUT
Read
X
X
X
X
X
X
High-Z
High-Z
X
X
X
X
1,3,8
3,8
3,8
SRAM
DIN
Write
L
H
H
L
SRAM
High-Z
Output Disable
L
H
X
SRAM
High-Z
Any Flash or PSRAM mode allowed
Standby
H
H
X
H
X
X
X
4,8
7,8
SRAM
High-Z
Data Retention
Same as SRAM Standby
NOTES:
1. WAIT is active during sync burst read when F-CE# and OE# are asserted. WAIT is High-Z if F-CE# or OE# is deasserted.
2. FX-CE# is F1-CE# for Flash #1, F2-CE# for Flash #2, and F3-CE# for Flash #3. FX-OE# is F1-OE# for Flash #1, and F2-
OE# for Flash #2.
3. For Flash, FX-OE# and F-WE# should never be asserted simultaneously. For PSRAM or SRAM, R-OE# and R-WE# should
never be asserted simultaneously.
4. X can be VIL or VIH for inputs and VPP1, VPP2, VPPLK or VPPH for F-Vpp.
5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
6. Refer to Intel Strataflash® Wireless Memory System Datasheet for valid DIN during flash writes.
7. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.
8. P-Mode is high if PSRAM is in Standby. P-Mode is low if PSRAM is in Low-Power Mode. Please see Section 18.0, “PSRAM
Operations” on page 45 for more details on Standby and Low-Power Mode.
9. Data segment flash only operates in asynchronous mode, CLK is ignored and WAIT is deasserted.
9.2
Flash Device Commands and Command Definitions
Refer to the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family
Datasheet (order number 253854) for complete descriptions of flash modes and commands, for
command bus-cycle definitions, and for flowcharts that illustrate operational routines.
Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
36
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
10.0
11.0
12.0
13.0
14.0
15.0
16.0
Flash Read Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Program Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Erase Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Suspend and Resume Operations
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Block Locking and Unlocking Operations
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Protection Register Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Configuration Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Datasheet
37
768-Mbit LVQ Family with Asynchronous Static RAM
17.0
Dual Operation Considerations
17.1
Product Configurations and Memory Partitioning
By default, the first flash die is the first code segment flash die, a fast, eXecute-In-Place (XIP)
solution ideal for an instruction fetch application. This portion is the user-selected parameter
configuration option, made up of either a 128-Mbit flash die or a 256-Mbit flash die, each
containing one parameter partition and several main partitions. The parameter partition contains
four 16-KWord parameter blocks and seven 64-KWord main blocks; all main partitions consist of
eight 64-KWord main blocks.
The large, embedded data segment is a single partition asynchronous page-mode read device that
can be made up of multiple dies with densities of 128-Mbit or 256-Mbit. The single partition is
made up of four 16-Kword parameter blocks and 64-Kword main blocks. The data segment flash
die parameter configuration will always be the opposite of the code segment flash die parameter
configuration. See Table 14 on page 39 for examples of configuration options.
The code and embedded data portions of the LVQ device are both asymmetrical in blocking. Each
memory block features zero-latency block locking. Data integrity is protected even further with the
optional use of F-VPP and F-WP# to implement block lock down.
The user has the choice of selecting either a top or a bottom parameter partition configuration for
the code segment flash die. Depending on the choice of configuration, the data segment flash die in
the LVQ device will be parametrically opposed. For instance, if the user selects top parameter
configuration for the code segment flash die, the data segment flash die in the package will be
configured as bottom parameter configuration, and vice-versa. This ensures the largest number of
contiguous main block addresses for software efficiency.
The xRAM segment can consist of up to two Pseudo-SRAM (PSRAM) dies and one SRAM die
with the following possible densities:
• The first PSRAM die can have a density of 64-Mbit or 128-Mbit.
• The second PSRAM die can have a density of 64-Mbit or 32-Mbit.
• The SRAM die has a density of 8-Mbit.
For the code segment, the 128-Mbit flash die has an 8-Mbit partition block and the 256-Mbit flash
die has a 16-Mbit partition block. The minimum code + data density combination for the LV18/
LV30 family is 384 Mbit.
38
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
.
Figure 19. Top and Bottom Parameter Configurations
Bottom Parameter Partition Block Stacking
Convention
Top Parameter Partition Block Stacking
Convention
1-Code + 2-
Data
2-Code + 1-
Data
2-Code + 2-
Data
1-Code + 1-
Data
1-Code + 2-
Data
2-Code + 1-
Data
2-Code + 2-
Data
1-Code + 1-
Data
Data
Data
Data
Code
Code
Code
Code
Data
(Top)
(Top)
(Top)
(Top)
(Top)
(Top)
(Top)
(Top)
Data
Code
Data
Code
Data
Code
Data
Code
(Bottom)
(Bottom)
(Bottom)
(Bottom)
(Bottom)
(Bottom)
(Top)
(Top)
Main
Blocks
Main
Blocks
Parameter
Blocks
Data
Parameter
Blocks
Code
Code
Data
Data
Code
(Bottom)
(Bottom)
(Bottom)
(Bottom)
(Top)
(Top)
Data
Code
(Bottom)
(Bottom)
Table 14. LVQ die stacked configuration example (Top / Bottom Parameter)
Stacked Configuration Example (Top Parameter)
Flash die#1
Die Stack Configuration
Flash die #2
Flash die #3
(user selected)
Code only
Code+Data
Top
Top
Top
Top
NA
Bottom
Top
NA
NA
Code+Data+Data
Code+Code+Data
Bottom
Bottom
Top
Stacked Configuration Example (Bottom Parameter)
Flash die#1
(user selected)
Die Stack Configuration
Flash die #2
Flash die #3
Code
Bottom
Bottom
Bottom
Bottom
NA
NA
NA
Top
Top
Code+Data
Top
Code+Data+Data
Code+Code+Data
Bottom
Bottom
17.2
Product Segment Unique Features
The code segment of the 768-Mbit LVQ Family with Asynchronous Static RAM device includes
the following enhanced features unless specifically noted otherwise:
• 64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits for
each code segment flash die.
Datasheet
39
768-Mbit LVQ Family with Asynchronous Static RAM
• Traditional write, erase, and burst-mode read capabilities of Intel® Wireless flash memory.
• Simultaneous RWW/RWE operations, enabling a burst read operation in one partition while
simultaneous with program or erase operations in other partitions.
• Burst-read across partition boundaries, but not across segment dies within the subsystem.
Note: User application code is responsible for ensuring that burst-mode reads do not cross into a partition
that is in program or erase mode.
The embedded data segment includes the following features unless specifically noted otherwise:
• High Density offerings of up to 512 Mb designated specifically for large embedded data.
• Single partition asynchronous page-mode read operation, allowing for a cost-effective ideal
storage format.
• Read-while-program or read-while-erase operations can be accomplished with software
through program suspend and erase suspend operations.
17.3
Flash Die Memory Map
The 768-Mbit LVQ Family with Asynchronous Static RAM device is available in several density
and parameter configurations. The memory map is based on the stacking of individual flash die
density options of 128 Mbit or 256 Mbit. The memory map shows individual flash die
configurations and block/partition allocations.
The code segment flash die is made up of 128-Mbit dies or 256-Mbit dies, each containing one
parameter partition and several main partitions.
The 128-Mbit memory array is divided into sixteen 8-Mbit partitions. Each die density contains
one parameter partition and fifteen main partitions. The 8-Mbit top or bottom parameter partition
contains four 16-Kword blocks and seven 64-Kword blocks. Each of the remaining fifteen 8-Mbit
main partitions contains eight 64-Kword blocks.
The 256-Mbit memory array is divided into sixteen 16-Mbit partitions. Each device contains one
parameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter partition
contains four 16-Kword blocks and fifteen 64-Kword blocks. Each of the remaining fifteen 16-
Mbit main partitions contains sixteen 64-Kword blocks.
The data segment flash die density is made up of 128-Mbit dies or 256-Mbit dies, each containing
a single partition architecture made up of four 16-Kword parameter blocks and 64-Kword main
blocks. The memory map and partitioning for various flash die combinations, top and bottom
parameters and are shown in the following tables:
Note: Only 128-Mbit and 256-Mbit flash die densities are used in three flash die SCSP combinations.
• Table 17, “Three Flash Dies (Top Parameter) SCSP Memory Map” on page 43
• Table 15, “Two Flash Dies (Top Parameter) SCSP Memory Map” on page 41
• Table 16, “Two Flash Dies (Bottom Parameter) SCSP Memory Map” on page 42
• Table 18, “Three Flash Dies (Bottom Parameter) SCSP Memory Map” on page 44
40
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 15. Two Flash Dies (Top Parameter) SCSP Memory Map
128-Mbit Flash
Address Range
256-Mbit Flash
Partition
Size
(Mbit)
Partition
Size
(Mbit)
Flash
Die Stack
Block Size
(KW)
Partitioning
Die# Configuration
Blk#
Blk# Address Range
16
130 7FC000-7FFFFF
258 FFC000-FFFFFF
Parameter
Partition
16
64
127 7F0000-7F3FFF
126 7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
(Partition 0)
Code
64
64
120 780000-78FFFF
119 770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
1
8
(Top
Parameter)
Main Partitions
(Partition 1 to 7)
64
64
64 400000-4FFFFF
63 3F0000-3FFFFF
128 800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to
15)
64
0
000000-00FFFF
0
000000-00FFFF
64
...
130 7F0000-7FFFFF
258 FF0000-FFFFFF
Single Partition
64
64
67 400000-40FFFF
66 3F0000-3FFFFF
131 100000-10FFFF
130 7F0000-7FFFFF
4 x 16-Kword
Parameter
Blocks
Data
64
64
11 080000-08FFFF
10 070000-07FFFF
11 080000-08FFFF
10 070000-07FFFF
127 x 64-Kword
Main Blocks
(128-Mb)
2
(Bottom
Parameter)
255 x 64-Kword
Main Blocks
(256-Mb
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
Datasheet
41
768-Mbit LVQ Family with Asynchronous Static RAM
Table 16. Two Flash Dies (Bottom Parameter) SCSP Memory Map
128-Mbit Flash
Address Range
256-Mbit Flash
Blk# Address Range
Partition
Size
(Mbit)
Partition
Size
(Mbit)
Flash
Die Stack
Block
Size (KW)
Partitioning
Die# Configuration
Blk#
16
...
130 7F0000-7FFFFF
258 FF0000-FFFFFF
Single Partition
16
64
67
66
400000-40FFFF
3F0000-3FFFFF
131 100000-10FFFF
130 7F0000-7FFFFF
4 x 16-Kword
Parameter
Blocks
Data
127 x 64-Kword
Main Blocks
(128-Mb)
1
64
64
11
10
080000-08FFFF
070000-07FFFF
11
10
080000-08FFFF
070000-07FFFF
(Top
Parameter)
255 x 64-Kword
Main Blocks
(256-Mb
64
64
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
64
...
130 7FC000-7FFFFF
258 FFC000-FFFFFF
Parameter
Partition
64
64
127 7F0000-7F3FFF
126 7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
(Partition 0)
Code
64
64
120 780000-78FFFF
119 770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
2
8
(Bottom
Parameter)
Main Partitions
(Partition 1 to
7)
64
16
64
63
400000-4FFFFF
3F0000-3FFFFF
128 800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to
15)
16
0
000000-00FFFF
0
000000-00FFFF
42
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 17. Three Flash Dies (Top Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Blk# Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die Stack
Partitioning
Size
Size
Die# Configuration
(KW)
(Mbit)
Blk#
Address Range
16
130
7FC000-7FFFFF
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Code
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
1
2
3
8
(Top
Parameter)
Main Partitions
(Partition 1 to 7)
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to 15)
64
16
0
000000-00FFFF
7FC000-7FFFFF
0
000000-00FFFF
130
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Code
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
8
(Top
Parameter)
Main Partitions
(Partition 1 to 7)
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to 15)
64
0
000000-00FFFF
7F0000-7FFFFF
0
000000-00FFFF
64
...
130
258 FF0000-FFFFFF
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
100000-10FFFF
Single Partition
130 7F0000-7FFFFF
4 x 16-Kword
Parameter Blocks
Data
64
64
11
10
080000-08FFFF
070000-07FFFF
11
10
080000-08FFFF
070000-07FFFF
(Bottom
Parameter)
127 x 64-Kword Main
Blocks (128-Mb)
255 x 64-Kword Main
Blocks (256-Mb)
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
Datasheet
43
768-Mbit LVQ Family with Asynchronous Static RAM
Table 18. Three Flash Dies (Bottom Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Blk# Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die Stack
Partitioning
Size
Size
Die# Configuration
(KW)
(Mbit)
Blk#
Address Range
16
130
7F0000-7FFFFF
258 FF0000-FFFFFF
16
64
67
66
400000-40FFFF
3F0000-3FFFFF
131 100000-10FFFF
130 7F0000-7FFFFF
Single Partition
4 x 16-Kword
Parameter Blocks
Data
64
64
11
10
080000-08FFFF
070000-07FFFF
11
10
080000-08FFFF
070000-07FFFF
1
2
3
(Top
Parameter)
127 x 64-Kword Main
Blocks (128-Mb)
255 x 64-Kword Main
Blocks (256-Mb)
64
64
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
64
64
0
000000-003FFF
7FC000-7FFFFF
0
000000-003FFF
130
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
64
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Code
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
8
(Bottom
Parameter)
Main Partitions
(Partition 1 to 7)
64
16
64
63
400000-4FFFFF
3F0000-3FFFFF
128 800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to 15)
16
64
0
000000-00FFFF
7FC000-7FFFFF
0
000000-00FFFF
130
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
64
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Code
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
16
8
(Bottom
Parameter)
Main Partitions
(Partition 1 to 7)
64
16
64
63
400000-4FFFFF
3F0000-3FFFFF
128 800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8 to 15)
16
0
000000-00FFFF
0
000000-00FFFF
44
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
18.0
PSRAM Operations
18.1
PSRAM Power-up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up slew rate of the core P-
V
. Any power-up slew rate is possible under use conditions.
CC
The following power-up sequence and operation should be used before starting normal operation.
The PSRAM power-up sequence is represented in Figure 20. At power-up, hold P-Mode low for
the period of t
and transition P-CS# from low to high before transitioning P-Mode to a logical
VHMH
high. P-CS# and P-Mode must be held high for the period of t
operation is possible once the power up sequence is complete.
before normal PSRAM
MHCL
Figure 20. Timing Waveform for PSRAM Power-Up Sequence
Initialization
Normal Operation
P-CS#
tMHCL
tCHMH
P-Mode
tVHMH
P-Vcc
Vcc (MIN)
Table 19. PSRAM Initialization Timing
Parameter
Symbol
MIN
MAX
Unit
µs
Power application to P-Mode low-level hold
P-CS# high-level to P-Mode high-level
t
50
0
–
–
VHMH
t
ns
CHMH
Following power application, P-Mode high-
level hold to P-CS# low-level
t
200
–
µs
MHCL
18.2
PSRAM Mode Register
The PSRAM die has an internal register that helps control the Low-Power Mode of the PSRAM.
This register is called the Mode Register. A fraction of the PSRAM array can be enabled for refresh
by setting the Mode Register. Available fixed, partial-refresh fraction densities are 16 Mbit, 8 Mbit,
4 Mbit and 0 Mbit for all density options. Once the refresh density has been set in the Mode
Register, these settings are retained until they are set again while applying the power supply.
However, the Mode Register setting will become undefined if the power is turned off; therefore, it
is important that the Mode Register is set again after power application.
Datasheet
45
768-Mbit LVQ Family with Asynchronous Static RAM
18.2.1
PSRAM Mode Register Setting
Since the initial value of the PSRAM Mode Register at power application is undefined, the Mode
Register must be set after initialization at power application. When setting the density of partial
refresh, data is not guaranteed before entering the Low-Power Mode. (This is the same for reset.)
However, since Low-Power Mode is not entered unless P-Mode is a logical low, when partial
refresh is not used, it is not necessary to set the Mode Register. Also, when using page read without
using partial refresh, it is not necessary to set the Mode Register.
The PSRAM Mode Register setting can be entered by successively writing two specific data after
two continuous reads of the highest address. The Mode Register setting is a continuous four-cycle
operation: two read cycles and two writes cycles. See Table 20 for setting PSRAM Mode Register
command sequence. Figure 21, “PSRAM Mode Register Setting Flowchart” on page 47 shows the
steps in setting the Mode Register. Figure 18 on page 34 illustrates the timing waveform.
Table 20. Setting PSRAM Mode Register Command Sequence
Command
Sequence
1st Bus Cycle
(Read Cycle)
2nd Bus Cycle
(Read Cycle)
3rd Bus Cycle
(Write Cycle)
4th Bus Cycle
(Write Cycle)
Partial refresh
density
Address
Data
Address
Data
Address
Data
Address
Data
Highest
Address
Highest
Address
Highest
Address
Highest
Address
16-Mbit
8-Mbit
4-Mbit
0-Mbit
_
_
_
_
_
_
_
_
0x00
0x00
0x00
0x00
0x04
0x05
0x06
0x07
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
46
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 21. PSRAM Mode Register Setting Flowchart
START
Read Highest Address
by Toggling both P-CS#
and R-OE#
No
Read Highest Address
by Toggling both P-CS#
and R-OE#
No
No
Write to Highest Address
Data=00H
No
No
No
Fail
Write to Highest Address
Data=xxH
Mode Register
setting exit
Begin Normal
Operation
NOTE: xxH=0x04, 0x05, 0x06 or 0x07
18.2.2
Cautions for Setting PSRAM Mode Register
For the PSRAM Mode Register setting, the internal counter status is judged by toggling P-CS# and
R-OE#. Therefore, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice),
and toggle R-OE# like P-CS# at the first and second read cycles. If incorrect addresses or data are
written, or are written in an incorrect order, the setting of the PSRAM Mode Register will be set
incorrectly.
When the highest address is read consecutively three or more times, the Mode Register setting
entries are not performed correctly.
Note: Immediately after the highest address is read, the setting of the Mode Register is not performed
correctly.
Perform the setting of the Mode Register after power application or after accessing other than the
highest address.
Once the refresh density has been set in the Mode Register, the setting is retained until it is reset
again while power is continuously applied. However, the Mode Register setting becomes
undefined if the power is turned off. The Mode Register must be reset after after any power cycle.
Datasheet
47
768-Mbit LVQ Family with Asynchronous Static RAM
18.3
PSRAM Low-Power Mode
In addition to the regular Standby mode with a full density data hold, Low-Power Mode performs
partial density data refresh or zero density data refresh.
The Low-Power Mode allows the user to turn off sections of the PSRAM die to save refresh
current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with
P-Mode at a logical-low.
In regular Standby mode, both P-CS# and P-Mode are logical-high. But in Low-Power Mode, P-
Mode is a logical-low. In Low-Power Mode, if 0-Mbit setting is set as the density, it is necessary to
perform initialization the same way as after applying power in order to return to normal operation
from Low-Power Mode. Refer to Figure 20, “Timing Waveform for PSRAM Power-Up Sequence”
on page 45 for timing charts. When the density has been to set to 16 Mbit, 8 Mbit, or 4 Mbit in
Low-Power Mode, it is not necessary to perform initialization to return to normal operation from
Low-Power Mode. Refer to Figure 22, “PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit)
Waveform” for timing charts.
Figure 22. PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit) Waveform
P-Mode
P-CS#
Low Power Mode
(Partial Array Refresh/Zero Refresh)
tCHML
tMHCL1/tMHCL2
Table 21. PSRAM Low-Power Mode Entry/Exit Timing
Parameter
Description
MIN MAX Unit
tCHML
Low-Power Mode entry, P-CS# high-level to P-Mode# low-level
0
–
–
ns
ns
Low-Power Mode (16-, 8-, 4-Mbit hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
1
tMHCL1
30
Low-Power Mode (0-Mbit data hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
2
tMHCL2
200
–
µs
NOTES:
1. tMHCL1 is the time it takes to return to normal operation from Low-Power Mode (data hold: 16-, 8-, 4-Mbit).
2. tMHCL2 is the time it takes to return to normal operation from Low-Power Mode (0-Mbit data hold).
48
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix A Write State Machine
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Appendix B Common Flash Interface
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Appendix C Flash Flowcharts
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Datasheet
49
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix D Additional Information
:
Order Number
Document
Intel StrataFlash® Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LVX Family
Datasheet
253853
Intel StrataFlash® Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LV Family
Datasheet
253854
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. For the most current information on Intel® Flash memory products, software and tools, visit our website at
http://developer.intel.com/design/flash.
50
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix E Ordering Information
Figure 23 shows the decoder for the flash-only combinations in the 768-Mbit LVQ Family with
Asynchronous Static RAM device. Figure 24 shows the decoder for the flash + RAM combinations
in the 768-Mbit LVQ Family with Asynchronous Static RAM device.
Figure 23. Decoder for Flash-only Combinations
N Z 4 8 F 0 0 0 0 L V Y D Q 0
Device Details
1 = Original version of the products
Package
i.e. for this specific example:
SCSP Packages:
Speed (Code Die):
!
!
RD = SCSP
NZ = Intel ® Ultra-Thin SCSP
!
!
90 ns aysnc/14 ns sync for
256M flash @ 1.7 V - 2.0 V I/O
85 ns aysnc/14 ns sync
Lead-Free SCSP Packages:
for 256M flash @ 1.8 V - 2.0 V I/O
Speed (Data Die):
170 ns async @ 1.8V-2.0 V I/O
!
!
PF = SCSP
JZ = Intel® Ultra-Thin SCSP
55 ns t
APA
Product Line Designator
48F = Flash Memory Only
Async only
Flash Process Technology:
0.13 µm ETOX™ VIII Process
Pinout Indicator
Flash Density
0 = No die
Q= QUAD+ ballout
2 = 64-Mbit
3 = 128-Mbit
4 = 256-Mbit
Parameter Location
B = Bottom Parameter
T = Top Parameter
D = Bottom Parameter for
Flash Die #1, Top
Parameter for Flash Die #2
Product Family
L = Intel StrataFlash® Wireless Flash Memory (L18/L30)
V = Intel StrataFlash® Wireless Flash Memory System (LV18/LV30)
0 = No Die
Voltage
Y = 1.8 Volt Core and I/O
Z = 3 Volt I/O, 1.8 Volt Core
Datasheet
51
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 24. Decoder for Flash + PSRAM Combinations
R D 3 8 F 4 4 5 0 L V Y B Q 0
Device Details
1 = Original version of the products
i.e. for this specific example:
Speed (Code Die):
Package
SCSP Packages:
!
!
RD = SCSP
NZ = Intel® Ultra-Thin SCSP
!
90 ns aysnc/14 ns sync for
256M flash @ 1.7 V - 2.0 V I/O
85 ns aysnc/14 ns sync for
256M flash @ 1.8 V - 2.0 V I/O
Speed (Data Die):
Lead-Free SCSP Packages:
!
PF = SCSP
!
!
JZ = Intel® Ultra-Thin SCSP
170 ns async @ 1.8V-2.0 V I/O
55 ns t
Product Line Designator
38F = Flash + xRAM Combination
Async AoPnAly
Flash Process Technology:
0.13 µm ETOX™ VIII Process
Package Size:
8 x 11 x 1.2 mm
Flash Density
0 = No die
3 = 128-Mbit
Notes:
!
F1-OE# is internally shared between flas
die #1 and flash die #2. F2-OE# ball is
unused and should be treated as an RFU
4 = 256-Mbit
Pinout Indicator
Q= QUAD+ ballout
RAM Density
0 = No die
2 = 8-Mbit RAM
4 = 32-Mbit RAM
5 = 64-Mbit RAM
Parameter Location
B = Bottom Parameter
T = Top Parameter
Product Family
L = Intel StrataFlash® Wireless Flash Memory (L18/L30)
LV = Intel StrataFlash® Wireless Flash Memory System (LV18/LV30)
0 = No Die
D = Bottom Parameter for
Flash Die #1, Top
Parameter for Flash Die #2
Voltage
Y = 1.8 Volt Core and I/O
Z = 3 Volt I/O, 1.8 Volt Core
52
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 22. Valid Combinations
I/O Voltage
Combinations with 128-Mbit Flash
Combinations with 256-Mbit Flash
RD48F3000L0YTQ0
RD48F3000L0YBQ0
RD38F3040L0YTQ0
RD38F3040L0YBQ0
NZ48F4000L0YTQ0
NZ48F4000L0YBQ0
PF48F4000L0YTQ0*
PF48F4000L0YBQ0*
RD48F4400L0YDQ0
PF48F4400L0YDQ0*
RD38F4455LVYTQ0
RD38F4455LVYBQ0
NZ48F4000L0ZTQ0
NZ48F4000L0ZBQ0
RD48F4400L0ZDQ0
RD38F4050L0ZBQ0
RD38F4050L0ZTQ0
1.8 V I/O
RD48F3000L0ZTQ0
RD48F3000L0ZBQ0
RD38F3040L0ZTQ0
RD38F3040L0ZBQ0
RD38F3352LLZDQ0*
PF38F3352LLZDQ0*
3.0 V I/O
NOTE: * These are non-standard product line items and may not be productized.
Datasheet
53
768-Mbit LVQ Family with Asynchronous Static RAM
54
Datasheet
相关型号：
RD38F4420LVYTQ0
Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, QUAD, SCSP-88
INTEL
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