S82433NX_技术文档

82433LX/82433NX

LOCAL BUS ACCELERATOR (LBX)

Y

Supports the Full 64-bit Pentium

Dual-Port Architecture Allows

Concurrent Operations on the Host and

PCI Buses

É

Processor Data Bus at Frequencies up

to 66 MHz (82433LX and 82433NX)

Y

Operates Synchronously to the CPU

and PCI Clocks

Y

Drives 3.3V Signal Levels on the CPU

Data and Address Buses (82433NX)

Supports Burst Read and Writes of

Memory from the Host and PCI Buses

Provides a 64-Bit Interface to DRAM

and a 32-Bit Interface to PCI

Sequential CPU Writes to PCI

Converted to Zero Wait-State PCI

Five Integrated Write Posting and Read

Prefetch Buffers Increase CPU and PCI

Performance

Ð CPU-to-Memory Posted Write Buffer

4 Qwords Deep

Ð PCI-to-Memory Posted Write Buffer

Two Buffers, 4 Dwords Each

Ð PCI-to-Memory Read Prefetch Buffer

4 Qwords Deep

Ð CPU-to-PCI Posted Write Buffer

4 Dwords Deep

Ý

Bursts with Optional TRDY

Connection

Y

Byte Parity Support for the Host and

Memory Buses

Ð Optional Parity Generation for Host

to Memory Transfers

Ð Optional Parity Checking for the

Secondary Cache

Ð Parity Checking for Host and PCI

Memory Reads

Ð CPU-to-PCI Read Prefetch Buffer

4 Dwords Deep

Ð Parity Generation for PCI to Memory

Writes

Y

CPU-to-Memory and CPU-to-PCI Write

Posting Buffers Accelerate Write

Performance

Y

160-Pin QFP Package

Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the

host CPU/Cache and main memory, a 32-bit data path between the host CPU bus and PCI Local Bus, and a

32-bit data path between the PCI Local Bus and main memory. The dual-port architecture allows concurrent

operations on the host and PCI Buses. The LBXs incorporate three write posting buffers and two read prefetch

buffers to increase CPU and PCI performance. The LBX supports byte parity for the host and main memory

buses. The 82433NX is intended to be used with the 82434NX PCI/Cache/Memory Controller (PCMC). The

82433LX is intended to be used with the 82434LX PCMC. During bus operations between the host, main

memory and PCI, the PCMC commands the LBXs to perform functions such as latching address and data,

merging data, and enabling output buffers. Together, these three components form a ‘‘Host Bridge’’ that

provides a full function dual-port data path interface, linking the host CPU and PCI bus to main memory.

This document describes both the 82433LX and 82433NX. Shaded areas, like this one, describe the

82433NX operations that differ from the 82433LX.

December 1995

Order Number: 290478-004

82433LX/82433NX

290478–1

LBX Simplified Block Diagram

2

82433LX/82433NX

LOCAL BUS ACCELERATOR (LBX)

CONTENTS

PAGE

1.0 ARCHITECTURAL OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.1 Buffers in the LBX ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

1.2 Control Interface Groups ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

1.3 System Bus Interconnect ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Ý

1.4 PCI TRDY Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

1.5 Parity Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.0 SIGNAL DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.1 Host Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

2.2 Main Memory (DRAM) Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

2.3 PCI Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

2.4 PCMC Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

2.5 Reset and Clock Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

3.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

3.1 LBX Post and Prefetch Buffers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

3.1.1 CPU-TO-MEMORY POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

3.1.3 PCI-TO-MEMORY READ PREFETCH BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

3.1.4 CPU-TO-PCI POSTED WRITE BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

3.1.5 CPU-TO-PCI READ PREFETCH BUFFER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

3.2 LBX Interface Command Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

[

]

3.2.1 HOST INTERFACE GROUP: HIG 4:0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

[

]

3.2.2 MEMORY INTERFACE GROUP: MIG 2:0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

[

]

3.2.3 PCI INTERFACE GROUP: PIG 3:0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19

3.3 LBX Timing Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

[

]

3.3.1 HIG 4:0 COMMAND TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

[

]

3.3.2 HIG 4:0 MEMORY READ TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

[

]

3.3.3 MIG 2:0 COMMAND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

[

]

3.3.4 PIG 3:0 COMMAND, DRVPCI, AND PPOUT TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

[

]

3.3.5 PIG 3:0 : READ PREFETCH BUFFER COMMAND TIMING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

[

]

3.3.6 PIG 3:0 : END-OF-LINE WARNING SIGNAL: EOL ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

3.4 PLL Loop Filter Components ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

3.5 PCI Clock Considerations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

3

CONTENTS

PAGE

4.0 ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

4.2 Thermal Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

4.3 DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

4.3.1 82433LX LBX DC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

4.3.2 82433NX LBX DC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

4.4 82433LX AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

4.4.1 HOST AND PCI CLOCK TIMING, 66 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

4.4.2 COMMAND TIMING, 66 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

Ý

4.4.3 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING, 66 MHz

(82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

4.4.4 HOST AND PCI CLOCK TIMING, 60 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38

4.4.5 COMMAND TIMING, 60 MHz (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38

Ý

4.4.6 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING, 60 MHz

(82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39

4.4.7 TEST TIMING (82433LX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

4.5 82433NX AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

4.5.1 HOST AND PCI CLOCK TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

4.5.2 COMMAND TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

Ý

4.5.3 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING

(82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

4.5.4 TEST TIMING (82433NX) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42

4.5.5 TIMING DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

5.0 PINOUT AND PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

5.1 Pin Assignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45

5.2 Package Information ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50

6.0 TESTABILITY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51

6.1 NAND Tree ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51

6.1.1 TEST VECTOR TABLE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51

6.1.2 NAND TREE TABLE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51

6.2 PLL Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53

4

82433LX/82433NX

2. 32-bit multiplexed address/data bus of PCI.

1.0 ARCHITECTURAL OVERVIEW

3. 64-bit data bus of the main memory.

The 82430 PCIset consists of the 82434LX PCMC

and 82433LX LBX components plus either a PCI/

ISA bridge or a PCI/EISA bridge. The 82430NX PCI-

set consists of the 82434NX PCMC and 82433NX

LBX components plus either a PCI/ISA bridge or a

PCI/EISA bridge. The PCMC and LBX provide the

core cache and main memory architecture and

serves as the Host/PCI bridge. An overview of the

PCMC follows the system overview section.

In addition, the LBXs provide parity support for the

three areas noted above (discussed further in Sec-

tion 1.4).

1.1 Buffers in the LBX

The LBX components have five integrated buffers

designed to increase the performance of the Host

and PCI Interfaces of the 82430LX/82430NX

PCIset.

The Local Bus Accelerator (LBX) provides a high

performance data and address path for the

82430LX/82430NX PCIset. The LBX incorporates

five integrated buffers to increase the performance

of the Pentium processor and PCI master devices.

Two LBXs in the system support the following areas:

With the exception of the PCI-to-Memory write buffer

and the CPU-to-PCI write buffer, the buffers in the

LBX store data only, addresses are stored in the

PCMC component.

1. 64-bit data and 32-bit address bus of the Pentium

processor.

5

82433LX/82433NX

290478–2

NOTES:

1. CPU-to-Memory Posted Write Buffer: This buffer is 4 Qwords deep, enabling the Pentium processor to write back a

whole cache line in 4-1-1-1 timing, a total of 7 CPU clocks.

2. PCI-to-Memory Posted Write Buffer: A PCI master can post two consecutive sets of 4 Dwords (total of one cache

line) or two single non-consecutive transactions.

3. PCI-to-Memory Read Prefetch Buffer: A PCI master to memory read transaction will cause this prefetch buffer to

read up to 4 Qwords of data from memory, allowing up to 8 Dwords to be read onto PCI in a single burst transaction.

Ý

connect option allows zero-wait state burst writes to PCI, making this buffer especially useful for graphic write

4. CPU-to-PCI Posted Write Buffer: The Pentium processor can post up to 4 Dwords into this buffer. The TRDY

operations.

5. CPU-to-PCI Read Prefetch Buffer: This prefetch buffer is 4 Dwords deep, enabling faster sequential Pentium proc-

essor reads when targeting PCI.

Figure 1. Simplified Block Diagram of the LBX Data Buffers

6

82433LX/82433NX

1.2 Control Interface Groups

1.3 System Bus Interconnect

The LBX is controlled by the PCMC via the control

interface group signals. There are three interface

groups: Host, Memory, and PCI. These control

groups are signal lines that carry binary codes which

the LBX internally decodes in order to implement

specific functions such as latching data and steering

data from PCI to memory. The control interfaces are

described below.

The architecture of the 82430/82430NX PCIset

splits the 64-bit memory and host data buses into

logical halves in order to manufacture LBX devices

with manageable pin counts. The two LBXs interface

[

]

to the 32-bit PCI AD 31:0 bus with 16 bits each.

Each LBX connects to 16 bits of the AD 31:0 bus

[

]

[

]

and 32-bits of both the MD 0:63 bus and the

D 0:63 bus. The lower order LBX (LBXL) connects

]

to the low word of the AD 31:0 bus, while the high

order LBX (LBXH) connects to the high word of the

[

]

[

1. Host Interface Group: These control signals are

[

]

named HIG 4:0 and define a total of 29 (30 for

the 82433NX) discrete commands. The PCMC

sends HIG commands to direct the LBX to per-

form functions related to buffering and storing

host data and/or address.

[

]

AD 31:0 bus.

Since the PCI connection for each LBX falls on

16-bit boundaries, each LBX does not simply con-

nect to either the low Dword or high Dword of the

Qword memory and host buses. Instead, the low or-

der LBX buffers the first and third words of each

64-bit bus while the high order LBX buffers the sec-

ond and fourth words of the memory and host

buses.

2. Memory Interface Group: These control signals

[

]

are named MIG 2:0 and define a total of 7 dis-

crete commands. The PCMC sends MIG com-

mands to direct the LBX to perform functions re-

lated to buffering, storing, and retiring data to

memory.

3. PCI Interface Group: These control signals are

As shown in Figure 2, LBXL connects to the first and

third words of the 64-bit main memory and host data

buses. The same device also drives the first 16 bits

[

]

named PIG 3:0 and define a total of 15 discrete

commands. The PCMC sends PIG commands to

direct the LBX to perform functions related to

buffering and storing PCI data and/or address.

[

]

of the host address bus, A 15:0 . The LBXH device

connects to the second and fourth words of the

64-bit main memory and host data buses. Corre-

spondingly, LBXH drives the remaining 16 bits of the

[

]

host address bus, A 31:16 .

290478–3

Figure 2. Simplified Interconnect Diagram of LBXs to System Buses

7

82433LX/82433NX

Ý

1.4 PCI TRDY Interface

2.0 SIGNAL DESCRIPTIONS

The PCI control signals do not interface to the LBXs,

instead these signals connect to the 82434LX

PCMC component. The main function of the LBXs

PCI interface is to drive address and data onto PCI

when the CPU targets PCI and to latch address and

data when a PCI master targets main memory.

This section provides a detailed description of each

signal. The signals (Figure 3) are arranged in func-

tional groups according to their associated interface.

Ý

The ‘ ’ symbol at the end of a signal name indicates

that the active, or asserted state occurs when the

Ý

signal is at a low voltage level. When ‘ ’ is not pres-

Ý

The TRDY option provides the capability for zero-

ent after the signal name, the signal is asserted

when at the high voltage level.

wait state performance on PCI when the Pentium

processor performs sequential writes to PCI. This

Ý

option requires that PCI TRDY be connected to

each LBX, for a total of two additional connections in

The terms assertion and negation are used exten-

sively. This is done to avoid confusion when working

with a mixture of ‘active-low’ and ‘active-high’ sig-

nals. The term assert, or assertion indicates that a

signal is active, independent of whether that level is

represented by a high or low voltage. The term ne-

gate, or negation indicates that a signal is inactive.

Ý

the system. These two TRDY connections are in

Ý

addition to the single TRDY connection that the

PCMC requires.

1.5 Parity Support

The following notations are used to describe the sig-

nal type.

The LBXs support byte parity on the host bus (CPU

and second level cache) and main memory buses

(local DRAM). The LBXs support parity during the

address and data phases of PCI transactions to/

from the host bridge.

in

Input is a standard input-only signal.

out Totem Pole output is a standard active driver.

t/s Tri-State is a bi-directional, tri-state input/out-

put pin.

290478–4

Figure 3. LBX Signals

8

82433LX/82433NX

2.1 Host Interface Signals

Signal Type

Description

[

A 15:0

]

[

ADDRESS BUS: The bi-directional A 15:0 lines are connected to the address lines of the

host bus. The high order LBX (determined at reset time using the EOL signal) is

]

t/s

[

]

[

]

connected to A 31:16 , and the low order LBX is connected to A 15:0 . The host address

bus is common with the Pentium processor, second level cache, PCMC and the two

[

]

[

LBXs. During CPU cycles A 31:3 are driven by the CPU and A 2:0 are driven by the

PCMC, all are inputs to the LBXs. During inquire cycles the LBX drives the PCI master

]

[

]

address onto the host address lines A 31:0 . This snoop address is driven to the CPU and

the PCMC by the LBXs to snoop L1 and the integrated second level tags, respectively.

During PCI configuration cycles bound for the PCMC, the LBXs will send or receive the

configuration data to/from the PCMC by copying the host data bus to/from the host

address bus. The LBX drives both halves of the Qword host data bus with data from the

32-bit address during PCMC configuration read cycles. The LBX drives the 32-bit address

with either the low Dword or the high Dword during PCMC configuration write cycles.

In the 82433NX, these pins contain weak internal pull-down resistors.

The high order 82433NX LBX samples A11 at the falling edge of reset to configure the

LBX for PLL test mode. When A11 is sampled low, the LBX is in normal operating mode.

When A11 is sampled high, the LBX drives the internal HCLK from the PLL on the EOL

pin. Note that A11 on the high order LBX is connected to the A27 line on the CPU address

bus. This same address line is used to put the PCMC into PLL test mode.

[

D 31:0

]

[

HOST DATA: The bi-directional D 31:0 lines are connected to the data lines of the host

data bus. The high order LBX (determined at reset time using the EOL signal) is

]

t/s

[

]

[

]

connected to the host data bus D 63:48 and D 31:16 lines, and the low order LBX is

connected to the host data bus D 47:32 and D 15:0 lines. In the 82433LX, these pins

[

]

[

]

contain weak internal pull-up resistors.

In the 82433NX, these pins contain weak internal pull-down resistors.

[

HP 3:0

]

[ ]

HOST DATA PARITY: HP 3:0 are the bi-directional byte parity signals for the host data

[ ]

[

]

bus. The low order parity bit HP 0 corresponds to D 7:0 while the high order parity bit

[ ]

[

]

[

HP 3 corresponds to D 31:24 . The HP 3:0 signals function as parity inputs during write

cycles and as parity outputs during read cycles. Even parity is supported and the HP 3:0

]

[

]

[

]

signals follow the same timings as D 31:0 . In the 82433LX, these pins contain weak

internal pull-up resistors.

In the 82433NX, these pins contain weak internal pull-down resistors.

9

82433LX/82433NX

2.2 Main Memory (Dram) Interface Signals

Signal

Type

Description

[

MD 31:0

]

[

MEMORY DATA BUS: MD 31:0 are the bi-directional data lines for the memory data

bus. The high order LBX (determined at reset time using the EOL signal) is connected to

]

t/s

[

]

[

the memory data bus MD 63:48 and MD 31:16 lines, and the low order LBX is

connected to the memory data bus MD 47:32 and MD 15:0 lines. The MD 31:0

]

[

]

[

]

[

]

[

]

signals drive data destined for either the host data bus or the PCI bus. The MD 31:0

signals input data that originated from either the host data bus or the PCI bus. These

pins contain weak internal pull-up resistors.

[

MP 3:0

]

[

MEMORY PARITY: MP 3:0 are the bi-directional byte enable parity signals for the

memory data bus. The low order parity bit MP 0 corresponds to MD 7:0 while the high

]

t/s

[ ]

[

]

[ ]

[

]

[

order parity bit MP 3 corresponds to MD 31:24 . The MP 3:0 signals are parity outputs

during write cycles to memory and parity inputs during read cycles from memory. Even

]

[

]

[

parity is supported and the MP 3:0 signals follow the same timings as MD 31:0 . These

]

pins contain weak internal pull-up resistors.

2.3 PCI Interface Signals

Signal

Type

Description

[

AD 15:0

]

[

ADDRESS AND DATA: AD 15:0 are bi-directional data lines for the PCI bus. The

AD 15:0 signals sample or drive the address and data on the PCI bus. The high order

LBX (determined at reset time using the EOL signal) is connected to the PCI bus

]

t/s

[

]

[

]

[

AD 31:16 lines, and the low order LBX is connected to the PCI AD 15:0 lines.

]

Ý

TARGET READY: TRDY indicates the selected (targeted) device’s ability to complete

TRDY

in

Ý

the current data phase of the bus operation. For normal operation, TRDY is tied

asserted low. When the TRDY option is enabled in the PCMC (for zero wait-state PCI

Ý

burst writes), TRDY should be connected to the PCI bus.

2.4 PCMC Interface Signals

Signal

Type

Description

[

HIG 4:0

]

in

HOST INTERFACE GROUP: These signals are driven from the PCMC and control the

host interface of the LBX. The 82433LX decodes the binary pattern of these lines to

perform 29 unique functions (30 for the 83433NX). These signals are synchronous to the

rising edge of HCLK.

[

MIG 2:0

]

in

MEMORY INTERFACE GROUP: These signals are driven from the PCMC and control

the memory interface of the LBX. The LBX decodes the binary pattern of these lines to

perform 7 unique functions. These signals are synchronous to the rising edge of HCLK.

[

PIG 3:0

]

PCI INTERFACE GROUP: These signals are driven from the PCMC and control the PCI

interface of the LBX. The LBX decodes the binary pattern of these lines to perform 15

unique functions. These signals are synchronous to the rising edge of HCLK.

MDLE

MEMORY DATA LATCH ENABLE: During CPU reads from DRAM, the LBX uses a

[

]

[

]

clocked register to transfer data from the MD 31:0 and MP 3:0 lines to the D 31:0 and

HP 3:0 lines. MDLE is the clock enable for this register. Data is clocked into this register

[

]

[

]

when MDLE is asserted. The register retains its current value when MDLE is negated.

[

]

[

During CPU reads from main memory, the LBX tri-states the D 31:0 and HP 3:0 lines

]

e

on the rising edge of MDLE when HIG 4:0 NOPC.

[

]

DRVPCI in

DRIVE PCI BUS: This signals enables the LBX to drive either address or data

[

]

information onto the PCI AD 15:0 lines.

10

82433LX/82433NX

2.4 PCMC Interface Signals (Continued)

Signal Type

Description

EOL

t/s

End Of Line: This signal is asserted when a PCI master read or write transaction is about

to overrun a cache line boundary. The low order LBX will have this pin connected to the

PCMC (internally pulled up in the PCMC). The high order LBX connects this pin to a pull-

down resistor. With one LBX EOL line being pulled down and the other LBX EOL pulled

up, the LBX samples the value of this pin on the negation of the RESET signal to

determine if it’s the high or low order LBX.

PPOUT t/s

LBX PARITY: This signal reflects the parity of the 16 AD lines driven from or latched into

[

]

the LBX, depending on the command driven on PIG 3:0 . The PCMC uses PPOUT from

[

]

both LBXs (called PPOUT 1:0 ) to calculate the PCI parity signal (PAR) for CPU to PCI

transactions during the address phase of the PCI cycle. The LBX uses PPOUT to check

the PAR signal for PCI master transactions to memory during the address phase of the

PCI cycle. When transmitting data to PCI the PCMC uses PPOUT to calculate the proper

value for PAR. When receiving data from PCI the PCMC uses PPOUT to check the value

received on PAR.

If the L2 cache does not implement parity, the LBX will calculate parity so the PCMC can

drive the correct value on PAR during L2 reads initiated by a PCI master. The LBX

samples the PPOUT signal at the negation of reset and compares that state with the state

of EOL to determine whether the L2 cache implements parity. The PCMC internally pulls

[ ]

down PPOUT 0 and internally pulls up PPOUT 1 . The L2 supports parity if PPOUT 0 is

connected to the high order LBX and PPOUT 1 is connected to the low order LBX. The

[ ]

L2 is defined to not support parity if these connections are reversed, and for this case, the

LBX will calculate parity. For normal operations either connection allows proper parity to

be driven to the PCMC.

2.5 Reset and Clock Signals

Signal Type

Description

HCLK

in

HOST CLOCK: HCLK is input to the LBX to synchronize command and data from the host

and memory interfaces. This input is derived from a buffered copy of the PCMC HCLKx

output.

PCLK

in

PCI CLOCK: All timing on the LBX PCI interface is referenced to the PCLK input. All

output signals on the PCI interface are driven from PCLK rising edges and all input signals

on the PCI interface are sampled on PCLK rising edges. This input is derived from a

buffered copy of the PCMC PCLK output.

RESET in

RESET: Assertion of this signal resets the LBX. After RESET has been negated the LBX

configures itself by sampling the EOL and PPOUT pins. RESET is driven by the PCMC

CPURST pin. The RESET signal is synchronous to HCLK and must be driven directly by

the PCMC.

LP1

out

LOOP 1: Phase Lock Loop Filter pin. The filter components required for the LBX are

connected to these pins.

LP2

in

LOOP 2: Phase Lock Loop Filter pin. The filter components required for the LBX are

connected to these pins.

TEST

in

TEST: The TEST pin must be tied low for normal system operation.

TSCON in

TRI-STATE CONTROL: This signal enables the output buffers on the LBX. This pin must

be held high for normal operation. If TSCON is negated, all LBX outputs will tri-state.

11

82433LX/82433NX

1 Dword (Dword is position 0 shifted to 1, 1 shifted

to 2 etc.). The DRAM controller of the PCMC asserts

3.0 FUNCTIONAL DESCRIPTION

3.1 LBX Post and Prefetch Buffers

[

]Ý

the correct CAS 7:0

signals depending on the PCI

]Ý

signals stored in the PCMC for that

[

C/BE 3:0

Dword.

This section describes the five write posting and

read prefetching buffers implemented in the LBX.

The discussion in this section refers to the operation

of both LBXs in the system.

The End Of Line (EOL) signal is used to prevent PCI

master writes from bursting past the cache line

boundary. The device that provides ‘‘warning’’ to the

PCMC is the low order LBX. This device contains the

PCI master write low order address bits necessary to

determine how many Dwords are left to the end of

the line. Consequently, the LBX protocol uses the

EOL signal from the low order LBX to provide this

‘‘end-of-line’’ warning to the PCMC, so that it may

retry a PCI master write when it bursts past the

cache line boundary. This protocol is described fully

in Section 3.3.6.

3.1.1 CPU-TO-MEMORY POSTED WRITE

BUFFER

The write buffer is a queue 4 Qwords deep, it loads

Qwords from the CPU and stores Qwords to memo-

ry. It is 4 Qwords deep to accommodate write-backs

from the first or second level cache. It is organized

[

]

lines store Qwords into the buffer, while commands

as a simple FIFO. Commands driven on the HIG 4:0

The LBX calculates Dword parity on PCI write data,

sending the proper value to the PCMC on PPOUT.

The LBX generates byte parity on the MP signals for

writing into DRAM.

[

]

on the MIG 2:0 lines retire Qwords from the buffer.

While retiring Qwords to memory, the DRAM control-

ler unit of the PCMC will assert the appropriate MA,

[

]Ý

Ý

CAS 7:0 , and WE signals. The PCMC keeps

track of full/empty states, status of the data and

address.

3.1.3 PCI-TO-MEMORY READ PREFETCH

BUFFER

Byte parity for data to be written to memory is either

propagated from the host bus or generated by the

LBX. The LBX generates parity for data from the

second level cache when the second level cache

does not implement parity.

This buffer is organized as a line buffer (4 Qwords)

for burst transfers to PCI. The data is transferred into

the buffer a Qword at a time and read out a Dword at

a time. The LBX then effectively decouples the

memory read rate from the PCI rate to increase con-

currence.

3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER

Each new transaction begins by storing the first

Dword in the first location in the buffer. The starting

Dword for reading data out of the buffer onto PCI

must be specified within a Qword boundary; that is

the first requested Dword on PCI could be an even

or odd Dword. If the snoop for a PCI master read

results in a write-back from first or second level

caches, this write back is sent directly to PCI and

main memory. The following two paragraphs de-

scribe this process for cache line write-backs.

The buffer is organized as 2 buffers (4 Dwords

each). There is an address storage register for each

buffer. When an address is stored one of the two

buffers is allocated and subsequent Dwords of data

are stored beginning at the first location in that buff-

er. Buffers are retired to memory strictly in order,

Qword at a time.

[

]

Commands driven on the PIG 3:0 lines post ad-

dresses and data into the buffer. Commands driven

[

]

on HIG 4:0 result in addresses being driven on the

host address bus. Commands driven on MIG 2:0

Since the write-back data from L1 is in linear order,

writing into the buffer is straightforward. Only those

Qwords to be transferred into PCI are latched into

the PCI-to-memory read buffer. For example, if the

address targeted by PCI is in the 3rd or 4th Qword in

the line, the first 2 Qwords of write back data are

discarded and not written into the read buffer. The

primary cache write-back must always be written

[

]

result in data being retired to DRAM.

For cases where the address targeted by the first

e

[ ]

Dword is odd, i.e. A 2 1, and the data is stored in

an even location in the buffer, the LBX correctly

aligns the Dword when retiring the data to DRAM. In

other words the buffer is capable of retiring a Qword

to memory where the data in the buffer is shifted by

12

82433LX/82433NX

completely to the CPU-to-Memory posted Write

Buffer.

with some performance enhancements. An address

is stored in the LBX with each Dword of data. The

structure of the buffer accommodates the packetiza-

tion of writes to be burst on PCI. This is accom-

plished by effectively discarding addresses of data

Dwords driven within a burst. Thus, while an address

is stored for each Dword, an address is not neces-

sarily driven on PCI for each Dword. The PCMC de-

termines when a burst write may be performed

based on consecutive addresses. The buffer also

enables consecutive bytes to be merged within a

single Dword, accommodating byte, word, and misa-

ligned Dword string store and string move opera-

tions. Qword writes on the host bus are stored within

the buffer as two individual Dword writes, with sepa-

rate addresses.

If the PCI master read data is read from the second-

ary cache, it is not written back to memory. Write-

backs from the second level cache, when using

burst SRAMs, are in Pentium processor burst order

(the order depending on which Qword of the line is

targeted by the PCI read). The buffer is directly ad-

dressed when latching second level cache write-

back data to accommodate this burst order. For ex-

ample, if the requested Qword is Qword 1, then the

burst order is 1-0-3-2. Qword 1 is latched in buffer

location 0, Qword 0 is discarded, Qword 3 is latched

into buffer location 2 and Qword 2 is latched into

buffer location 1.

[

]

[

]

Commands driven on MIG 2:0 and HIG 4:0 enter

data into the buffer from the DRAM interface and the

host interface (i.e. the caches), respectively. Com-

The storing of an address with each Dword of data

allows burst writes to be retried easily. In order to

retry transactions, the FIFO is effectively ‘‘backed

up’’ by one Dword. This is accomplished by making

the FIFO physically one entry larger than it is logical-

ly. Thus, the buffer is physically 5 entries deep (an

entry consists of an address and a Dword of data),

while logically it is considered full when 4 entries

have been posted. This design allows the FIFO to

be backed up one entry when it is logically full.

[

]

mands driven on the PIG 3:0 lines drive data from

the buffer onto the PCI AD 31:0 lines.

[

]

Parity driven on the PPOUT signal is calculated from

the byte parity received on the host bus or the mem-

ory bus, whichever is the source. If the second level

cache is the source of the data and does not imple-

ment parity, the parity driven on PPOUT is generated

by the LBX from the second level cache data. If

main memory is the source of the read data, PCI

parity is calculated from the DRAM byte parity. Main

memory must implement byte parity to guarantee

correct PCI parity generation.

[

]

Commands driven on HIG 4:0 post addresses and

data into the buffer, and commands driven on

[

]

PIG 3:0 retire addresses and data from the buffer

[

]

and drive them onto the PCI AD 31:0 lines. As dis-

cussed previously, when bursting, not all addresses

are driven onto PCI.

3.1.4 CPU-TO-PCI POSTED WRITE BUFFER

Data parity driven on the PPOUT signal is calculated

from the byte parity received on the host bus. Ad-

dress parity driven on PPOUT is calculated from the

address received on the host bus.

The CPU-to-PCI Posted Write Buffer is 4 Dwords

deep. The buffer is constructed as a simple FIFO,

13

82433LX/82433NX

3.1.5 CPU-TO-PCI READ PREFETCH BUFFER

3.2 LBX Interface Command

Descriptions

This prefetch buffer is organized as a single buffer

4 Dwords deep. The buffer is organized as a simple

FIFO. reads from the buffer are sequential; the buff-

er does not support random access of its contents.

To support reads of less than a Dword the FIFO

read pointer can function with or without a pre-incre-

ment. The pointer can also be reset to the first entry

before a Dword is driven. When a Dword is read, it is

driven onto both halves of the host data bus.

This section describes the functionality of the HIG,

MIG and PIG commands driven by the PCMC to the

LBXs.

[

3.2.1 HOST INTERFACE GROUP: HIG 4:0

]

The Host Interface commands are shown in Table 1.

These commands are issued by the host interface of

the PCMC to the LBXs in order to perform the fol-

lowing functions:

[

]

Commands driven on the HIG 4:0 lines enable read

addresses to be sent onto PCI, the addresses are

[

]

driven using PIG 3:0 commands. Read data is

latched into the LBX by commands driven on the

Reads from CPU-to-PCI read prefetch buffer

when the CPU reads from PCI.

#

[

]

PIG 3:0 lines and the data is driven onto the host

data bus using commands driven on the HIG 4:0

Stores write-back data to PCI-to-memory read

#

[

]

prefetch buffer when PCI read address results in

a hit to a modified line in first or second level

caches.

lines.

The LBX calculates Dword parity on PCI read data,

sending the proper value to the PCMC on PPOUT.

The LBX does not generate byte parity on the host

data bus when the CPU reads PCI.

Posts data to CPU-to-memory write buffer in the

case of a CPU to memory write.

#

Posts data to CPU-to-PCI write buffer in the case

of a CPU to PCI write.

#

Drives host address to Data lines and data to ad-

dress lines for programming the PCMC configura-

tion registers.

#

14

82433LX/82433NX

Table 1. HIG Commands

Description

Command

NOPC

Code

00000b No Operation on CPU Bus

11100b CPU Memory Read

CMR

CPRF

00100b CPU Read First Dword from CPU-to-PCI Read Prefetch Buffer

CPRA

00101b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer, Toggle A

00110b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer, Toggle B

00111b CPU Read Qword from CPU-to-PCI Read Prefetch Buffer

01000b Store Write-Back Data Qword 0 to PCI-to-Memory Read Buffer

01001b Store Write-Back Data Qword 1 to PCI-to-Memory Read Buffer

01010b Store Write-Back Data Qword 2 to PCI-to-Memory Read Buffer

01011b Store Write-Back Data Qword 3 to PCI-to-Memory Read Buffer

01100b Post to CPU-to-Memory Write Buffer Qword

CPRB

CPRQ

SWB0

SWB1

SWB2

SWB3

PCMWQ

PCMWFQ

01101b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer First Qword

PCMWNQ 01110b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer Next Qword

PCPWL

MCP3L

MCP2L

MCP1L

PCPWH

MCP3H

MCP2H

MCP1H

LCPRAD

DPRA

10000b Post to CPU-to-PCI Write Low Dword

10011b Merge to CPU-to-PCI Write Low Dword 3 Bytes

10010b Merge to CPU-to-PCI Write Low Dword 2 Bytes

10001b Merge to CPU-to-PCI Write Low Dword 1 Byte

10100b Post to CPU-to-PCI Write High Dword

10111b Merge to CPU-to-PCI Write High Dword 3 Bytes

10110b Merge to CPU-to-PCI Write High Dword 2 Bytes

10101b Merge to CPU-to-PCI Write High Dword 1 Byte

00001b Latch CPU-to-PCI Read Address

11000b Drive Address from PCI A/D Latch to CPU Address Bus

11001b Drive Address from PCI-to-Memory Write Buffer to CPU Address Bus

11101b Address to Data Copy in the LBX

DPWA

ADCPY

DACPYH

DACPYL

PSCD

11011b Data to Address Copy in the LBX High Dword

11010b Data to Address Copy in the LBX Low Dword

01111b Post Special Cycle Data

DRVFF

PCPWHC

11110b Drive FF..FF (All 1’s) onto the Host Data Bus

00011b Post to CPU-to-PCI Write High Dword Configuration

NOTE:

All other patterns are reserved.

15

82433LX/82433NX

NOPC

CMR

No Operation is performed on the host

bus by the LBX hence it tri-states its

host bus drivers.

SWB0

SWB1

SWB2

This command stores a Qword from

the host data lines into location 0 of

the PCI-to-Memory Read Buffer. Parity

is either generated for the data or prop-

agated from the host bus based on the

state of the PPOUT signals sampled at

the negation of RESET when the LBXs

were initialized.

This command effectively drives

DRAM data onto the host data bus.

The LBX acts as a transparent latch in

this mode, depending on MDLE for

latch control. With the MDLE signal

high the CMR command will cause the

LBXs to buffer memory data onto the

host bus. When MDLE is low. The LBX

will drive onto the host bus whatever

memory data that was latched when

MDLE was negated.

This command, (similar to SWB0),

stores a Qword from the host data

lines into location 1 of the PCI-to-Mem-

ory Read Buffer. Parity is either gener-

ated from the data or propagated from

the host bus based on the state of the

PPOUT signal sampled at the falling

edge of RESET.

CPRF

CPRA

This command reads the first Dword of

the CPU-to-PCI read prefetch buffer.

The read pointer of the FIFO is set to

point to the first Dword. The Dword is

driven onto the high and low halves of

the host data bus.

This command, (similar to SWB0),

stores a Qword written back from the

first or second level cache into location

2 of the PCI-to-memory read buffer.

Parity is either generated from the data

or propagated from the host bus based

on the state of the PPOUT signal sam-

pled at the falling edge of RESET.

This command increments the read

pointer of the CPU-to-PCI read pre-

fetch buffer FIFO and drives that

Dword onto the host bus when it is

driven after a CPRF or CPRB com-

mand. If driven after another CPRA

command, the LBX drives the current

Dword while the read pointer of the

FIFO is not incremented. The Dword is

driven onto the upper and lower halves

of the host data bus.

SWB3

This command stores a Qword from

the host data lines into location 3 of

the PCI-to-Memory Read Buffer. Parity

is either generated for the data or prop-

agated from the host bus based on the

state of the PPOUT signal sampled at

the falling edge of RESET.

CPRB

This command increments the read

pointer of the CPU-to-PCI read pre-

fetch buffer FIFO and drives that

Dword onto the host bus when it is

driven after a CPRA command. If driv-

en after another CPRB command, the

LBX drives the current Dword while the

read pointer of the FIFO is not incre-

mented. The Dword is driven onto the

upper and lower halves of the host

data bus.

PCMWQ

This command posts one Qword of

data from the host data lines to CPU-

to-Memory Write Buffer in case of a

CPU memory write or a write-back from

the second level cache.

PCMWFQ If the PCI Memory read address leads

to a hit on a modified line in the first

level cache, then

a write-back is

scheduled and this data has to be writ-

ten into the CPU-to-Memory Write Buff-

er and PCI-to-Memory Read Buffer at

the same time. The write-back of the

first Qword is done by this command to

both the buffers.

CPRQ

This command drives the first Dword

stored in the CPU-to-PCI read prefetch

buffer onto the lower half of the host

data bus, and drives the second Dword

onto the upper half of the host data

bus, regardless of the state of the read

pointer. The read pointer is not affect-

ed by this command.

PCMWNQ This command follows the previous

command to store or post subsequent

write-back Qwords.

16

82433LX/82433NX

PCPWL

This command posts the low Dword of

a CPU-to-PCI write. The CPU-to-PCI

Write Buffer stores a Dword of PCI ad-

dress for every Dword of data. Hence,

this command also stores the address

of the Low Dword in the address loca-

tion for the data. Address bit 2 (A2) is

not stored directly. This command as-

sumes a value of 0 for A2 and this is

what is stored.

DPRA

DPWA

The PCI memory read address is

latched in the PCI A/D latch by a PIG

command LCPRAD, this address is

driven onto the host address bus by

DPRA. Used in PCI to memory read

transaction.

The DPWA command drives the ad-

dress of the current PCI Master Write

Buffer onto the host address bus. This

command is potentially driven for multi-

ple cycles. When it is no longer driven,

the read pointer will increment to point

to the next buffer, and a subsequent

DPWA command will read the address

from that buffer.

MCP3L

MCP2L

MCP1L

PCPWH

This command merges the 3 most sig-

nificant bytes of the low Dword of the

host data bus into the last Dword post-

ed to the CPU-to-PCI write buffer. The

address is not modified.

This command merges the 2 most sig-

nificant bytes of the low Dword of the

host data bus into the last Dword post-

ed to the CPU-to-PCI write buffer. The

address is not modified.

ADCPY

This command drives the host data

bus with the host address. The ad-

dress is copied on the high and low

halves of the Qword data bus; i.e.

[

]

[

]

A 31:0 is copied onto D 31:0 and

[

]

D 63:32 . This command is used when

the CPU writes to the PCMC configura-

tion registers.

This command merges the most signif-

icant byte of the low Dword of the host

data bus into the last Dword posted to

the CPU-to-PCI write buffer. The ad-

dress is not modified.

DACPYH

DACPYL

PSCD

This command drives the host address

bus with the high Dword of host data.

This command is used when the CPU

writes to the PCMC configuration regis-

ters.

This command posts the upper Dword

of a CPU-to-PCI write, with its address,

into the address location. Hence, to do

a Qword write PCPWL has to be fol-

lowed by a PCPWH. Address bit 2 (A2)

is not stored directly. This command

forces a value of 1 for A2 and this is

what is stored.

This command drives the host address

bus with the low Dword of host data.

This command is used when the CPU

writes to the PCMC configuration regis-

ters.

MCP3H

MCP2H

MCP1H

LCPRAD

This command merges the 3 most sig-

nificant bytes of the high Dword of the

host data bus into the last Dword post-

ed to the CPU-to-PCI Write Buffer. The

address is not modified.

This command is used to post the val-

ue of the Special Cycle code into the

CPU-to-PCI Posted Write Buffer. The

[

]

value is driven onto the A 31:0 lines

by the PCMC, after acquiring the ad-

dress bus by asserting AHOLD. The

This command merges the 2 most sig-

nificant bytes of the high Dword of the

host data bus into the last Dword post-

ed to the CPU-to-PCI Write Buffer. The

address is not modified.

[

]

value on the A 31:0 lines is posted

into the DATA location in the CPU-to-

PCI Posted Write Buffer.

DRVFF

This command causes the LBX to drive

all ‘‘1s’’ (i.e. FFFFFFFFh) onto the host

data bus. It is used for CPU reads from

PCI that terminate with master abort.

This command merges the most signif-

icant byte of the high Dword of the host

data bus into the last Dword posted to

the CPU-to-PCI Write Buffer. The ad-

dress is not modified.

PCPWHC

This command posts the high half of

the CPU data bus. The LBXs post the

high half of the data bus even if A2

from the PCMC is low. This command

is used during configuration writes

when using PCI configuration access

This command latches the host ad-

dress to drive on PCI for a CPU-to-PCI

read. It is necessary to latch the ad-

dress in order to drive inquire address-

es on the host address bus before the

CPU address is driven onto PCI.

Ý

mechanism 1.

17

82433LX/82433NX

[

3.2.2 MEMORY INTERFACE GROUP: MIG 2:0

]

The Memory Interface commands are shown in Table 2. These commands are issued by the DRAM controller

of the PCMC to perform the following functions:

Retires data from CPU-to-Memory Write Buffer to DRAM.

#

Stores data into PCI-to-Memory Read Buffer when the PCI read address is targeted to DRAM.

#

Retires PCI-to-Memory Write Buffer to DRAM.

#

Table 2. MIG Commands

Command Code

Description

NOPM

000b No Operation on Memory Bus

PMRFQ

PMRNQ

RCMWQ

RPMWQ

001b Place into PCI-to-Memory Read Buffer First Qword

010b Place into PCI-to-Memory Read Buffer Next Qword

100b Retire CPU-to-Memory Write Buffer Qword

101b Retire PCI-to-Memory Write Buffer Qword

RPMWQS 110b Retire PCI-to-Memory Write Buffer Qword Shifted

MEMDRV

111b Drive Latched Data Onto Memory Bus for 1 Clock Cycle

NOTE:

All other patterns are reserved.

NOPMN

PMRFQ

Operation on the memory bus. The LBX

tri-states its drivers driving the memory

bus.

RPMWQS This command retires one Qword of

data from one line of PCI-to-Memory

write buffer to DRAM. For this com-

mand the data in the buffer is shifted by

one Dword (Dword in position 0 is shift-

ed to 1, 1 to 2 etc.). This is because the

address targeted by the first Dword of

the write could be an odd Dword (i.e.,

The PCI-to-Memory read address tar-

gets memory if there is a miss on first

and second caches. This command

stores the first Qword of data starting at

the first location in the buffer. This buff-

er is 8 Dwords or 1 cache line deep.

[ ]

address bit 2 is a 1). To retire a misa-

ligned line this command has to be

used for all the data in the buffer. When

all the valid data in one buffer is retired,

the next RPMWQ (or RPMWQS) will

read data from the next buffer.

PMRNQ

RCMWQ

RPMWQ

This command stores subsequent

Qwords from memory starting at the

next available location in the PCI-to-

Memory Read Buffer. It is always used

after PMRFQ.

MEMDRV For a memory write operation the data

on the memory bus is required for more

than one clock cycle hence all DRAM

retires are latched and driven to the

memory bus in subsequent cycles by

this command.

This command retires one Qword from

the CPU-to-Memory Write Buffer to

DRAM. The address is stored in the ad-

dress queue for this buffer in the

PCMC.

This command retires one Qword of

data from one line of the PCI-to-Memo-

ry write buffer to DRAM. When all the

valid data in one buffer is retired, the

next RPMWQ (or RPMWQS) will read

data from the next buffer.

18

82433LX/82433NX

[

]

The PCI AD 31:0 lines are driven by asserting the

signal DRVPCI. This signal is used for both master

and slave transactions.

[

3.2.3 PCI INTERFACE GROUP: PIG 3:0

]

The PCI Interface commands are shown in Table 3.

These commands are issued by the PCI master/

slave interface of the PCMC to perform the following

functions:

Parity is calculated on either the value being driven

onto PCI or the value being received on PCI, de-

pending on the command. In Table 3, the PAR col-

umn has been included to indicate the value that the

PPOUT signals are based on. An ‘‘I’’ indicates that

the PPOUT signals reflect the parity of the AD lines

as inputs to the LBX. An ‘‘O’’ indicates that the

PPOUT signals reflect the value being driven on the

PCI AD lines. See Section 3.3.4 for the timing rela-

Slave posts address and data to PCI-to-Memory

Write Buffer.

#

Slave sends PCI-to-Memory read data on the AD

bus.

#

Slave latches PCI master memory address so

that it can be gated to the host address bus.

#

[

]

tionship between the PIG 3:0 command, the

AD 31:0 lines, and the PPOUT signals.

Master latches CPU-to-PCI read data from the

AD bus.

#

[

]

Master retires CPU-to-PCI write buffer.

#

Master sends CPU-to-PCI address to the AD bus.

#

Table 3. PIG Commands

Command

PPMWA

PPMWD

SPMRH

SPMRL

SPMRN

LCPRF

LCPRA

LCPRB

DCPWA

DCPWD

DCPWL

DCCPD

BCPWR

SCPA

Code

1000b

1001b

1101b

1100b

1110b

0000b

0001b

0010b

0100b

0101b

0110b

1011b

1010b

0111b

0011b

PAR

Description

Post to PCI-to-Memory Write Buffer Address

Post to PCI-to-Memory Write Buffer Data

Send PCI Master Read Data High Dword

Send PCI Master Read Data Low Dword

Send PCI Master Read Data Next Dword

Latch CPU Read from PCI into Read Prefetch Buffer First Dword

Latch CPU Read from PCI into Prefetch Buffer Next Dword, A Toggle

Latch CPU Read from PCI into Prefetch Buffer Next Dword, B Toggle

Drive CPU-to-PCI Write Buffer Address

I

O

I

O

I

Drive CPU-to-PCI Write Buffer Data

Drive CPU-to-PCI Write Buffer Last Data

Discard Current CPU-to-PCI Write Buffer Data

Backup CPU-to-PCI Write Buffer for Retry

Send CPU-to-PCI Address

LPMA

Latch PCI Master Address

NOTE:

All other patterns are reserved.

19

82433LX/82433NX

PPMWA

This command selects a new buffer

LCPRB

When driven after a LCPRA com-

mand, this command latches the val-

and places the PCI master address

latch value into the address register

for that buffer. The next PPMWD

command posts write data in the first

location of this newly selected buff-

er. This command also causes the

EOL logic to decrement the count of

Dwords remaining in the line.

[

]

ue of the AD 31:0 lines into the next

location into the CPU-to-PCI Read

Prefetch Buffer. When driven after

another LCPRB command, this com-

[

]

mand latches the value on AD 31:0

into the same location in the CPU-to-

PCI Read Prefetch Buffer, overwrit-

ing the previous value.

PPMWD

SPMRH

SPMRL

This command stores the value in

the AD latch into the next data loca-

tion in the currently selected buffer.

This command also causes the EOL

logic to decrement the count of

Dwords remaining in the line.

DCPWA

DCPWD

This command drives the next ad-

dress in the CPU-to-PCI Write Buffer

onto PCI. The read pointer of the

FIFO is not incremented.

This command drives the next data

Dword in the CPU-to-PCI Write Buff-

er onto PCI. The read pointer of the

FIFO is incremented on the next

This command sends the high order

Dword from the first Qword of the

PCI-to-Memory Read Buffer onto

PCI. This command also causes the

EOL logic to decrement the count of

Dwords remaining in the line.

Ý

PCLK if TRDY is asserted.

DCPWL

DCCPD

BCPWR

This command drives the previous

data Dword in the CPU-to-PCI Write

Buffer onto PCI. This is the data

which was driven by the last DCPWD

command. The read pointer of the

FIFO is not incremented.

This command sends the low order

Dword from the first Qword of the

PCI-to-Memory Read Buffer onto

PCI. This command also selects the

Dword alignment for the transaction

and causes the EOL logic to decre-

ment the count of Dwords remaining

in the line.

This command discards the current

Dword in the CPU-to-PCI Write Buff-

er. This is used to clear write data

when the write transaction termi-

nates with master abort, where

SPMRN

This command sends the next

Dword from the PCI-to-Memory

Read Buffer onto PCI. This com-

mand also causes the EOL logic to

decrement the count of Dwords re-

maining in the line. This command is

used for the second and all subse-

quent Dwords of the current transac-

tion.

Ý

TRDY is never asserted.

For this command the CPU-to-PCI

Write Buffer is ‘‘backed up’’ one en-

try such that the address/data pair

last driven with the DCPWA and

DCPWD commands will be driven

[

]

again on the AD 31:0 lines when

the commands are driven again.

This command is used when the tar-

get has retried the write cycle.

LCPRF

LCPRA

This command acquires the value of

[

]

the AD 31:0 lines into the first loca-

tion in the CPU-to-PCI Read Pre-

fetch Buffer until a different com-

mand is driven.

SCPA

LPMA

This command drives the value on

the host address bus onto PCI.

This command stores the previous

When driven after a LCPRF or

LCPRB command, this command

[

]

AD 31:0 value into the PCI master

address latch. If the EOL logic deter-

mines that the requested Dword is

the last Dword of a line, then the

EOL signal will be asserted; other-

wise the EOL signal will be negated.

[

]

latches the value of the AD 31:0

lines into the next location into the

CPU-to-PCI Read Prefetch Buffer.

When driven after another LCPRA

command, this command latches

[

]

the value on AD 31:0 into the same

location in the CPU-to-PCI Read

Prefetch Buffer, overwriting the pre-

vious value.

20

82433LX/82433NX

The Drive commands in Figure 4 are any of the

following:

3.3 LBX Timing Diagrams

This section describes the timing relationship be-

tween the LBX control signals and the interface

buses.

CMR

CPRF

CPRA

DPWA

DRVFF

CPRB

CPRQ

DACPYH

DPRA

ADCPY

DACPYL

The Latch command in Figure 4 is any of the

following:

[

]

3.3.1 HIG 4:0 COMMAND TIMING

SWB0

SWB1

SWB2

SWB3

[

]

The commands driven on HIG 4:0 can cause the

host address bus and/or the host data bus to be

driven and latched. The following timing diagram il-

lustrates the timing relationship between the driven

command and the buses. The ‘‘host bus’’ in Figure 4

could be address and/or data.

PCMWQ

MCP3L

MCP3H

PCMWFQ

MCP2L

MCP2H

PCMWNQ

MCP1L

PCPWL

PCPWH

PSCD

LCPRAD

Note that the Drive command takes two cycles to

drive the host data bus, but only one to drive the

address. When the NOPC command is sampled, the

LBX takes only one cycle to release the host bus.

290478–5

[

]

Figure 4. HIG 4:0 Command Timing

21

82433LX/82433NX

synchronous register inside the LBX to the HD and

HP lines. MDLE acts as a clock enable for this regis-

ter. When MDLE is asserted, the LBX samples the

MD and MP lines. When MDLE is negated, the MD

and HD register retains its current value.

[

]

3.3.2 HIG 4:0 MEMORY READ TIMING

Figure 5 illustrates the timing relationship between

[

]

[

]

[

]Ý

the HIG 4:0 , MIG 2:0 , CAS 7:0 , and MDLE sig-

nals for DRAM memory reads. The delays shown in

the diagram do not represent the actual AC timings,

but are intended only to show how the delay affects

the sequencing of the signals.

The LBX releases the HD bus based on sampling

[

]

the NOPC command on the HIG 4:0 lines and

MDLE being asserted. By delaying the release of the

HD bus until MDLE is asserted, the LBX provides

hold time for the data with respect to the write en-

[

]

When the CPU is reading from DRAM, the HIG 4:0

lines are driven with the CMR command that causes

the LBX to drive memory data onto the HD bus. Until

the MD bus is valid, the HD bus is driven with invalid

[

able strobes (CWE 7:0

cache.

]Ý

)

of the second level

[

]Ý

data. When CAS 7:0

comes valid after the DRAM CAS 7:0

time. The MD and MP lines are directed through a

assert, the MD bus be-

[

]Ý

access

290478–6

Figure 5. CPU Read from Memory

22

82433LX/82433NX

The data on the MD bus is sampled at the end of the

first cycle into the LBX based on sampling the Latch

[

]

3.3.3 MIG 2:0 COMMAND

[

Figure 6 illustrates the timing of the MIG 2:0 com-

mands with respect to the MD bus, CAS 7:0 , and

Ý

WE . Figure 6 shows the MD bus transitioning from

a read to a write cycle.

]

[

command. The CAS 7:0 signals can be negated

in the next cycle. The WE signal is asserted in the

]Ý

[

]Ý

Ý

next cycle. The required delay between the asser-

Ý

[

]Ý

tion of WE and the assertion of CAS 7:0 means

that the MD bus has 2 cycles to turn around; hence

the NOPM command driven in the second clock.

The LBX starts to drive the MD bus based on sam-

pling the Retire command at the end of the third

clock. After the Retire command is driven for 1 cy-

cle, the data is held at the output by the MEMDRV

command. The LBX releases the MD bus based on

sampling the NOPM command at the end of the

sixth clock.

The Latch command in Figure 6 is any of the

following:

PMRFQ

PMRNQ

The Retire command in Figure 6 is any of the

following:

RCMWQ RPMWQ

RPMWQS

290478–7

[

]

Figure 6. MIG 2:0 Command Timing

23

82433LX/82433NX

The DRVPCI signal is driven synchronous to the PCI

bus, enabling the LBXs to initiate driving the PCI

[

]

3.3.4 PIG 3:0 COMMAND, DRVPCI, AND PPOUT

TIMING

[

]

AD 31:0 lines one clock after DRVPCI is asserted.

As shown in Figure 7, if DRVPCI is asserted in cycle

[

]

Figure 7 illustrates the timing of the PIG 3:0 com-

mands, the DRVPCI signal, and the PPOUT 1:0 sig-

]

nal relative to the PCI AD 31:0 lines.

a

[

]

[

]

N, the PCI AD 31:0 lines are driven in cycle N 1.

The negation of the DRVPCI signal causes the LBXs

to asynchronously release the PCI bus, enabling the

[

]

The Drive commands in Figure 7 are any of the fol-

lowing:

LBXs to cease driving the PCI AD 31:0 lines in the

same clock that DRVPCI is negated. As shown in

Figure 7, if DRVPCI is negated in cycle N, the PCI

SPMRH SPMRL

SPMRN

[

]

AD 31:0 lines are released in cycle N.

DCPWA DCPWD DCPWL

SCPA

PCI address and data parity is available at the LBX

interface on the PPOUT lines from the LBX. The par-

ity for data flow from PCI to LBX is valid 1 clock

cycle after data on the AD bus. The parity for data

flow from LBX to PCI is valid in the same cycle as

The Latch commands in Figure 7 are any of the fol-

lowing:

PPMWA PPMWD LPMA

[

]

The following commands do not fit in either catego-

ry, although they function like Latch type commands

the data. When the AD 31:0 lines transition from

input to output, there is no conflict on the parity lines

due to the dead cycle for bus turnaround. This is

illustrated in the sixth and seventh clock of Figure 7.

[

]

with respect to the PPOUT 1:0 signals. They are

described in Section 3.3.5.

LCPRF

LCPRA

LCPRB

290478–8

[

]

Figure 7. PIG 3:0 Command Timing

24

82433LX/82433NX

[

]

[

The HIG 4:0 and PIG 3:0 lines are defined to en-

able the features described previously. The LCPRF

]

[

]

3.3.5 PIG 3:0 : READ PREFETCH BUFFER

COMMAND TIMING

[

]

PIG 3:0 command latches the first PCI read Dword

into the first location in the CPU-to-PCI read prefetch

Ý

buffer. This command is driven until TRDY is sam-

pled asserted. The valid Dword would then be in the

Ý

first location of the buffer. The cycle after TRDY is

sampled asserted, the PCMC drives the LCPRA

[

command on the PIG 3:0 lines. This action latches

the value on the PCI AD 31:0 lines into the next

The structure of the CPU-to-PCI read prefetch buffer

requires special considerations due to the partition

of the PCMC and LBX. The PCMC interfaces only to

the PCI control signals, while the LBXs interface only

to the data. Therefore, it is not possible to latch a

Dword of data into the prefetch buffer after it is quali-

Ý

fied by TRDY . Instead, the data is repetitively

latched into the same location until TRDY is sam-

pled asserted. Only after TRDY is sampled assert-

]

[

]

Ý

Dword location in the buffer. Again, the LCPRA com-

Ý

mand is driven until TRDY is sampled asserted.

Each cycle the LCPRA command is driven, data is

latched into the same location in the buffer. When

ed is data valid in the buffer. A toggling mechanism

is implemented to advance the write pointer to the

next Dword after the current Dword has been quali-

Ý

TRDY is sampled asserted, the PCMC drives the

Ý

[ ]

LCPRB command on the PIG 3:0 lines. This latches

fied by TRDY

.

[

]

the value on the AD 31:0 lines into the next location

in the buffer, the oneafter the location that the previ-

ous LCPRA command latched data into. After

Other considerations of the partition are taken into

account on the host side as well. When reading from

the buffer, the command to drive the data onto the

host bus is sent before it is known that the entry is

valid. This method avoids the wait-state that would

Ý

TRDY has been sampled asserted again, the com-

mand switches back to LCPRA. In this way, the

same location in the buffer can be filled repeatedly

until valid, and when it is known that the location is

valid, the next location can be filled.

Ý

be introduced by waiting for an entry’s TRDY to be

asserted before sending the command to drive the

entry onto the host bus. The FIFO structure of the

buffer also necessitates a toggling scheme to ad-

vance to the next buffer entry after the current entry

has been successfully driven. Also, this method

gives the LBX the ability to drive the same Dword

twice, enabling reads of less than a Dword to be

serviced by the buffer; reads of individual bytes of a

Dword would read the same Dword 4 times.

[

]

The commands for the HIG 4:0 , CPRF, CPRA, and

CPRB, work exactly the same way. If the same com-

mand is driven, the same data is driven. Driving an

appropriately different command results in the next

data being driven. Figure 8 illustrates the usage of

these commands.

25

82433LX/82433NX

290478–9

[

]

Figure 8. PIG 3:0 CPU-to-PCI Read Prefetch Buffer Commands

Figure 8 shows an example of how the PIG com-

mands function on the PCI side. The LCPRF com-

latching a new value into the first location of the read

prefetch buffer. At this point the data is not the cor-

[

]

Ý

mand is driven on the PIG 3:0 lines until TRDY is

sampled asserted at the end of the fifth PCI clock.

Ý

rect value, since TRDY has not yet been asserted

on PCI. The LCPRF command is driven again in the

Ý

The LCPRA command is then driven until TRDY is

again sampled asserted at the end of the seventh

Ý

PCI clock. TRDY is sampled asserted again so

LCPRB is driven only once. Finally, LCPRA is driven

Ý

fifth PCI clock while TRDY is sampled asserted at

the end of this clock. The requested data for the

read is then latched into the first location of the read

prefetch buffer and driven onto the host data bus,

becoming valid at the end of CPU clock 12. The

Ý

again until the last TRDY is asserted at the end of

Ý

the tenth PCI clock. In this way, 4 Dwords are

latched in the read CPU-to-PCI prefetch buffer.

BRDY signal can therefore be driven asserted in

this clock. The following read transaction (issued in

CPU clock 15) requests the next Dword, and so the

[

]

Figure 8 also shows an example of how the HIG

commands function on the host side of the LBX.

Two clocks after sampling the CPRF command, the

LBX drives the host data bus. The data takes two

cycles to become stable. The first data driven in this

case is invalid, since the data has not arrived on PCI.

The data driven on the host bus changes in the sev-

enth host clock, since the LCPRF command has

CPRA command is driven on the HIG 4:0 lines, ad-

vancing to read the next location in the read pre-

fetch buffer. As the correct data is already there, the

command is driven only once for this transaction.

The next read transaction requests data in the same

Dword as the previous. Therefore, the CPRA com-

mand is driven again, the buffer is not advanced,

and the same Dword is driven onto the host bus.

[

]

been driven on the PIG 3:0 lines the previous cycle,

26

82433LX/82433NX

captured in the PCI AD latch at the end of the first

clock to the posting buffer, and open the PCI AD

latch in order to capture the data. This data will be

posted to the write buffer in the following cycle by

the PPMWD command.

[

]

3.3.6 PIG 3:0 : END-OF-LINE

WARNING SIGNALS: EOL

When posting PCI master writes, the PCMC must be

informed when the line boundary is about to be over-

run, as it has no way of determining this itself (recall

that the PCMC does not receive any address bits

from PCI). The low order LBX determines this, as it

contains the low order bits of the PCI master write

address and also tracks how many Dwords of write

data have been posted. Therefore, the low order

LBX component sends the ‘‘end-of-line’’ warning to

the PCMC. This is accomplished with the EOL signal

driven from the low order LBX to the PCMC. Figure 9

illustrates the timing of this signal.

3. The EOL signal is first negated when the LPMA

[

]

command is driven on the PIG 3:0 signals. How-

ever, if the first data Dword accepted is also the

last that should be accepted, the EOL signal will

be asserted in the third clock. This is the ‘‘end-of-

line’’ indication. In this case, the EOL signal is as-

serted as soon as the LPMA command has been

latched. The action by the PCMC in response is to

Ý

negate TRDY and assert STOP in the fifth

clock. Note that the EOL signal is asserted even

Ý

1. The FRAME signal is sampled asserted in the

first cycle. The LPMA command is driven on the

Ý

before the MEMCS signal is sampled asserted

in this case. The EOL signal will remain asserted

until the next time the LPMA command is driven.

[

]

PIG 3:0 signals to hold the address while it is

being decoded (e.g. in the MEMCS decode cir-

Ý

4. If the second Dword is the last that should be

accepted, the EOL signal will be asserted in the

fifth clock to negate TRDY and assert STOP

on the following clock. The EOL signal is asserted

in response to the PPMWA command being sam-

cuit of the 82378 SIO). The first data (D0) remains

Ý

on the bus until TRDY is asserted in response

to MEMCS being sampled asserted in the third

Ý

clock.

Ý

2. The PPMWA command is driven in response to

pled, and relies on the knowledge that TRDY for

Ý

sampling MEMCS asserted. TRDY is asserted

in this cycle indicating that D0 has been latched at

the end of the fourth clock. The action of the

PPMWA command is to transfer the PCI address

the first Dword of data will be sampled asserted

by the master in the same cycle (at the end of the

fourth clock). Therefore, to prevent a third asser-

Ý

tion of TRDY in the sixth clock, the EOL signal

must be asserted in the fifth clock.

290478–10

Figure 9. EOL Signal Timing for PCI Master Writes

27

82433LX/82433NX

A similar sequence is defined for PCI master reads.

While it is possible to know when to stop driving read

data due to the fact that the read address is latched

into the PCMC before any read data is driven on PCI,

the use of the EOL signal for PCI master reads sim-

plifies the logic internal to the PCMC. Figure 10 illus-

1. The LPMA command sampled at the end of the

second clock causes the EOL signal to assert if

there is only one Dword left in the line, otherwise

Ý

it will be negated. The first TRDY will also be

the last, and the STOP signal will be asserted

Ý

with TRDY

.

[

trates the timing of EOL with respect to the PIG 3:0

commands to drive out PCI read data.

]

2. The SPMRH command causes the count of the

number of Dwords left in the line to be decre-

mented. If this count reaches one, the EOL signal

Note that unlike the PCI master write sequence, the

Ý

STOP signal is asserted with the last data transfer,

not after.

Ý

is asserted. The next TRDY will be the last, and

STOP is asserted with TRDY

Ý

.

290478–11

Figure 10. EOL Signal Timing for PCI Master Reads

28

82433LX/82433NX

The high order 82433NX LBX samples A11 at the

falling edge of reset to configure the LBX for PLL

test mode. When A11 is sampled low, the LBX is in

normal operating mode. When A11 is sampled high,

the LBX drives the internal HCLK from the PLL on

the EOL pin. Note that A11 on the high order LBX is

connected to the A27 line on the CPU address bus.

This same address line is used to put the PCMC into

PLL test mode.

3.4 PLL Loop Filter Components

As shown in Figure 11, loop filter components are

required on the LBX components. A 4.7 KX 5% re-

sistor is typically connected between pins LP1 and

LP2. Pin LP2 has a path to the PLLAGND pin

through a 100X 5% series resistor and a 0.01 mF

10% series capacitor. The ground side of capacitor

C1 and the PLLVSS pin should connect to the

ground plane at a common point. All PLL loop filter

traces should be kept to minimal length and should

be wider than signal traces. Inductor L1 is connect-

ed to the 5V power supply on both the 82433LX and

82433NX.

Mercury

60 MHz

Mercury

66 MHz

Neptune

R1

R2

C2

R3

C1

4.7 KX

100X

2.2 KX

100X

4.7 KX

100X

Some circuit boards may require filtering the power

circuit to the LBX PLL. The circuit shown in Figure

11 will typically enable the LBX PLL to have higher

noise immunity than without. Pin PLLVDD is con-

0.01 mF

10X

0.01 mF

10X

0.01 mF

10X

0.47 mF

0.01 mF

0.47 mF

0.01 mF

0.47 mF

0.01 mF

nected to the 5V V

through a 10X 5% resistor.

The PLLVDD and PLLVSS pins are bypassed with a

CC

1

C1

0.01 mF 10% series capacitor.

290478–12

Figure 11. Loop Filter Circuit

29

82433LX/82433NX

ference in timing between the signal that appears at

the PCMC PCLKIN input pin and the signal that ap-

pears at the LBX PCLK input pin. For both the low

order LBX and the high order LBX, the PCLK rising

and falling edges must not be more than 1.25 ns

apart from the rising and falling edge of the PCMC

PCLKIN signal.

3.5 PCI Clock Considerations

There is a 1.25 ns clock skew specification between

the PCMC and the LBX that must be adhered to for

proper operation of the PCMC/LBX timing. As

shown in Figure 12, the PCMC drives PCLKOUT to

an external clock driver which supplies copies of

PCLK to PCI devices, the LBXs, and back to the

PCMC. The skew specification is defined as the dif-

290478–13

Figure 12. Clock Considerations

30

82433LX/82433NX

Maximum Power Dissipation: ÀÀÀÀÀÀ1.4W (82433LX)

Maximum Total Power Dissipation À1.4W (82433NX)

4.0 ELECTRICAL CHARACTERISTICS

4.1 Absolute Maximum Ratings

Maximum Power Dissipation, V

ÀÀÀÀÀÀÀÀ430 mW

CC3

The maximum total power dissipation in the

82433NX on the V and V pins is 1.4W. The

V

CC3

total power will not exceed 1.4W.

Table 4 lists stress ratings only. Functional operation

at these maximums is not guaranteed. Functional

operation conditions are given in Sections 4.2

and 4.3.

CC CC3

pins may draw as much as 430 mW, however,

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. The specifications are subject to

change without notice. Verify with your local Intel

Sales office that you have the latest data sheet be-

fore finalizing a design.

Extended exposure to the Absolute Maximum Rat-

ings may affect device reliability.

a

Case Temperature under Bias ÀÀÀÀÀÀÀ0 C to 85 C

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 40 C to 125 C

§

b

a

§

Voltage on Any Pin

with Respect to GroundÀÀÀÀÀ 0.3 to V

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

b

a

0.3V

CC

Supply Voltage

with Respect to V

b a

ÀÀÀÀÀÀÀÀÀÀÀÀ 0.3 to 7.0V

SS

4.2 Thermal Characteristics

The LBX is designed for operation at case temperatures between 0 C and 85 C. The thermal resistances of

§

the package are given in the following tables.

Table 4. Thermal Resistance

Parameter

Air Flow Rate (Linear Feet per Minute)

0

400

37.1

10

600

i

( C/Watt)

§

( C/Watt)

§

51.9

34.8

JA

JC

31

82433LX/82433NX

PCI Interface Signals

4.3 DC Characteristics

[

]

Ý

[

AD 15:0 (t/s), TRDY (in), PIG 3:0 (in), DRVPCI(in),

]

EOL(t/s), PPOUT(t/s)

Host Interface Signals

[

]

[

]

[

]

A 15:0 (t/s), D 31:0 (t/s), HIG 4:0 (in), HP 3:0 (t/s)

[

]

Reset and Clock Signals

HCLK(in), PCLK(in), RESET(in), LP1(out), LP2(in),

TEST(in)

Main Memory (DRAM) Interface Signals

]

MD 31:0 (t/s), MP 3:0 (t/s), MIG 2:0 (in), MDLE(in)

[

]

[

]

4.3.1 82433LX LBX DC CHARACTERISTICS

e

CASE

a

0 C to 85 C

Functional Operating Range: V

4.75 V to 5.25V; T

Typical

§

CC

Symbol

Parameter

Min

Max

0.8

a

Unit

V

Notes

b

V

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

Output Low Current

Output High Current

0.3

1

2

3

4

5

6

IL1

2.0

V

CC

0.3

V

IH1

b

c

V

0.3

V

IL2

CC

c

a

0.3

0.7

V

CC

V

IH2

CC

0.4

0.5

1

V

OL1

OH1

OL2

OH2

OL1

OH1

OL2

OH2

2.4

V

b

V

0.5

V

CC

I

mA

b

1

2

3

b

32

82433LX/82433NX

e

e a

0 C to 85 C (Continued)

Functional Operating Range: V

4.75V to 5.25V; T

§

CC

CASE

Symbol

Parameter

Min

Typical

Max

Unit

mA

pF

Notes

I

Output Low Current

Output High Current

Input Leakage Current

Input Capacitance

Output Capacitance

I/O Capacitance

3

7

OL3

OH3

IH

b

1

a

b

10

IL

C

4.6

4.3

4.6

IN

pF

OUT

I/O

pF

NOTES:

1. V and V

[

]

[

]

[

]

[

]

[

]

apply to the following signals: AD 15:0 , A 15:0 , D 31:0 , HP 3:0 , MD 31:0 , MP 3:0 , TRDY , RESET,

[

]

Ý

IL1

HCLK, PCLK

IH1

[ ] [ ] [ ]

apply to the following signals: HIG 4:0 , PIG 3:0 , MIG 2:0 , MDLE, DRVPCI

IH2

2. V

3. V

4. V

5. I

6. I

7. I

and V

IL2

OL1

OL2

OL1

OL2

OL3

[

]

[

]

[

]

[

]

[

]

[

]

and V

apply to the following signals: AD 15:0 , A 15:0 , D 31:0 , HP 3:0 , MD 31:0 , MP 3:0

apply to the following signals: PPOUT, EOL

OH1

OH2

and I

apply to the following signals: PPOUT, EOL

OH1

OH2

OH3

[

]

apply to the following signals: A 15:0 , D 31:0 , HP 3:0 , MD 31:0 , MP 3:0

apply to the following signals: AD 15:0

]

[

]

[

]

[

]

[

]

4.3.2 82433NX LBX DC CHARACTERISTICS

e

3.135 to 3.465V, T

CASE

a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; V

Min

§

CC

CC3

Symbol

Parameter

Typical

Max

Unit

V

Notes

b

V

Input Low Voltage

0.3

0.8

1

2

3

4

5

6

7

IL1

a

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

Output Low Current

Output High Current

2.0

V

0.3

V

IH1

CC

b

0.3

0.3 x V

V

IL2

CC

a

V

CC

0.7 x V

0.3

V

IH2

CC

b

0.3

0.8

V

IL3

a

CC3

2.0

V

0.3

V

IH3

0.4

0.5

1

V

OL1

OH1

OL2

OH2

OL1

OH1

OL2

OH2

2.4

V

b

V

0.5

V

CC

I

mA

b

1

2

3

33

82433LX/82433NX

e

Functional Operating Range: V

e

4.75V to 5.25V; V

3.135V to 3.465V,

CC

CC3

a

0 C to 85 C (Continued)

T

§

CASE

Symbol

Parameter

Min

Typical

Max

Unit

mA

pF

Notes

I

Output Low Current

Output High Current

Input Leakage Current

Input Capacitance

Output Capacitance

I/O Capacitance

3

8

OL3

OH3

IH

b

1

a

10

b

IL

C

4.6

4.3

4.6

IN

pF

OUT

I/O

pF

NOTES:

[ ] [ ] [ ] Ý

apply to the following signals: AD 15:0 , MD 31:0 , MP 3:0 , TRDY , RESET, HCLK, PCLK

1. V

2. V

3. V

4. V

5. V

6. I

7. I

8. I

and V

IL1

IL2

IH1

IH2

IH3

[

]

[

]

apply to the following signals: HIG 4:0 , PIG 3:0 , MIG 2:0 , MDLE, DRVPCI

apply to the following signals: A 15:0 , D 31:0 , HP 3:0

[

]

[

]

[

]

[

]

IL3

[

]

[

]

[

]

[

]

[

apply to the following signals: AD 15:0 , A 15:0 , D 31:0 , HP 3:0 , MD 31:0 , MP 3:0

]

[

]

and V

OL1

OL2

OL1

OL2

OL3

OH1

OH2

apply to the following signals: PPOUT, EOL

and I

apply to the following signals: PPOUT, EOL

OH1

OH2

OH3

[

]

apply to the following signals: A 15:0 , D 31:0 , HP 3:0 , MD 31:0 , MP 3:0

apply to the following signals: AD 15:0

]

[

]

[

]

[

]

and therefore drive 3.3V signal levels.

[

]

[

]

[

]

9. The output buffers for A 15:0 , D 31:0 and HP 3:0 are powered with V

[

]

CC3

34

82433LX/82433NX

e

In Figure 13 through Figure 21 VT 1.5V for the fol-

4.4 82433LX AC Characteristics

[

]

[

]

lowing signals: MD 31:0 , MP 3:0 , D 31:0 ,

HP 3:0 , A 15:0 , AD 15:0 , TRDY , HCLK, PCLK,

[

]

[

]

[

]

[

]

Ý

The AC specifications given in this section consist of

propagation delays, valid delays, input setup require-

ments, input hold requirements, output float delays,

output enable delays, clock high and low times and

clock period specifications. Figure 13 through Figure

21 define these specifications. Sections 4.3.1

through 4.3.3 list the AC Specifications.

RESET, TEST.

e

[

[ ]

VT 2.5V for the following signals: HIG 4:0 ,

PIG 3:0 , MIG 2:0 , MDLE, DRVPCI, PPOUT, EOL.

]

[

]

4.4.1 HOST AND PCI CLOCK TIMING, 66 MHZ (82433LX)

e

e a

0 C to 70 C

Functional Operating Range: V

4.9V to 5.25V; T

§

CC

CASE

Symbol

t1a

t1b

t1c

t1d

t1e

t1f

Parameter

HCLK Period

Min

15

Max

Figure

18

Notes

20

HCLK High Time

HCLK Low Time

HCLK Rise Time

HCLK Fall Time

HCLK Period Stability

PCLK Period

5

18

1.5

19

1

g

100

ps

t2a

t2b

t2c

t2d

t2e

t3

30

12

18

19

21

PCLK High Time

PCLK Low Time

PCLK Rise Time

PCLK Fall Time

HCLK to PCLK Skew

3

b

7.2

5.8

NOTE:

1. Measured on rising edge of adjacent clocks at 1.5 Volts.

35

82433LX/82433NX

4.4.2 COMMAND TIMING, 66 MHZ (82433LX)

Functional Operating Range: V

e

CASE

a

0 C to 70 C

4.9V to 5.25V; T

§

CC

Symbol

t10a

t10b

t11a

t11b

t12a

t12b

t13a

t13b

t14a

t14b

t15a

t15b

Parameter

HIG 4:0 Setup Time to HCLK Rising

Min

Max

Figure

15

Notes

[

]

5.4

[

]

HIG 4:0 Hold Time from HCLK Rising

0

15

[

]

MIG 2:0 Setup Time to HCLK Rising

5.4

0

15

[

]

MIG 2:0 Hold Time from HCLK Rising

15

[

]

PIG 3:0 Setup Time to PCLK Rising

15.6

b

15

[

]

PIG 3:0 Hold Time from PCLK Rising

MDLE Setup Time to HCLK Rising

MDLE Hold Time to HCLK Rising

DRVPCI Setup Time to PCLK Rising

DRVPCI Hold Time from PCLK Rising

RESET Setup Time to HCLK Rising

RESET Hold Time from HCLK Rising

1.0

15

5.7

15

b

0.3

6.5

15

b

0.5

15

3.1

0.3

15

36

82433LX/82433NX

Ý

4.4.3 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING, 66 MHz (82433LX)

e

CASE

a

0 C to 70 C

Functional Operating Range: V

Parameter

4.9V to 5.25V; T

§

CC

Symbol

t20a

t20b

t20c

t20d

t20e

t21a

t21b

t22a

t22b

t22c

t22d

t22e

t22f

Min

Max

Figure

17

Notes

[

]

AD 15:0 Output Enable Delay from PCLK Rising

2

7

0

2

7

0

[

]

AD 15:0 Valid Delay from PCLK Rising

11

14

1

[

]

AD 15:0 Setup Time to PCLK Rising

15

[

]

AD 15:0 Hold Time from PCLK Rising

15

[

]

AD 15:0 Float Delay from DRVPCI Falling

10

16

Ý

TRDY Setup Time to PCLK Rising

15

Ý

TRDY Hold Time from PCLK Rising

15

[

]

[

D 31:0 , HP 3:0 Output Enable Delay from HCLK Rising

]

7.7

17

2

[

]

[

D 31:0 , HP 3:0 Float Delay from HCLK Rising

]

3.1

2

15.5

11.0

7.7

16

[ [

D 31:0 , HP 3:0 Float Delay from MDLE Rising

]

16

3

2

[ [

D 31:0 , HP 3:0 Valid Delay from HCLK Rising

]

0

14

[ [

D 31:0 , HP 3:0 Setup Time to HCLK Rising

]

3.0

0.3

0

15

[ [

D 31:0 , HP 3:0 Hold Time from HCLK Rising

]

15

[

]

HA 15:0 Output Enable Delay from HCLK Rising

t23a

t23b

t23c

t23cc

t23d

t23e

t23f

15.2

16

17

[

]

HA 15:0 Float Delay from HCLK Rising

0

16

[

]

HA 15:0 Valid Delay from HCLK Rising

0

14

7

8

4

5

[

]

HA 15:0 Valid Delay from HCLK Rising

0

14.5

[

]

HA 15:0 Setup Time to HCLK Rising

15

4.1

0.3

0

15

14

15

14

16

17

[

]

HA 15:0 Setup Time to HCLK Rising

[

]

HA 15:0 Hold Time from HCLK Rising

[

]

[

MD 31:0 , MP 3:0 Valid Delay from HCLK Rising

]

t24a

t24b

t24c

t25

12.0

6

2

[

]

[

MD 31:0 , MP 3:0 Setup Time to HCLK Rising

]

4.0

0.4

2.3

0

[

]

[

]

MD 31:0 , MP 3:0 Hold Time from HCLK Rising

EOL, PPOUT Valid Delay from PCLK Rising

All Outputs Float Delay from TSCON Falling

All Outputs Enable Delay from TSCON Rising

17.2

30

t26a

t26b

0

30

NOTES:

1. Min: 0 pF, Max: 50 pF

2. 0 pF

[

]

3. When NOPC command sampled on previous rising HCLK on HIG 4:0

4. CPU to PCI Transfers

[

5. When ADCPY command is sampled on HIG 4:0

6. 50 pF

]

[

]

7. When DACPYL or DACPYH commands are sampled on HIG 4:0

8. Inquire cycle

37

82433LX/82433NX

4.4.4 HOST AND PCI CLOCK TIMING, 60 MHz (82433LX)

e

CASE

a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; T

§

CC

Symbol

t1a

t1b

t1c

t1d

t1e

t1f

Parameter

HCLK Period

Min

16.6

5.5

Max

20

Figure

18

Notes

HCLK High Time

HCLK Low Time

HCLK Rise Time

HCLK Fall Time

HCLK Period Stability

PCLK Period

18

5.5

18

1.5

19

1

g

100

ps

t2a

t2b

t2c

t2d

t2e

t3

33.33

13

18

19

21

PCLK High Time

PCLK Low Time

PCLK Rise Time

PCLK Fall Time

13

3

b

PCLK to PCMC PCLKIN: Input to Input Skew

7.2

5.8

NOTES:

1. Measured on rising edge of adjacent clocks at 1.5 Volts

4.4.5 COMMAND TIMING, 60 MHZ (82433LX)

e

a

0 C to 85 C

Functional Operating Range: V

Parameter

4.75V to 5.25V; T

§

CC

CASE

Symbol

t10a

t10b

t11a

t11b

t12a

t12b

t13a

t13b

t14a

t14b

t15a

t15b

Min

Max

Figure

15

Notes

[

]

HIG 4:0 Setup Time to HCLK Rising

6.0

[

]

HIG 4:0 Hold Time from HCLK Rising

0

15

[

]

MIG 2:0 Setup Time to HCLK Rising

6.0

0

15

[

]

MIG 2:0 Hold Time from HCLK Rising

15

[

]

PIG 3:0 Setup Time to PCLK Rising

16.0

0

15

[

]

PIG 3:0 Hold Time from PCLK Rising

MDLE Setup Time to HCLK Rising

MDLE Hold Time to HCLK Rising

DRVPCI Setup Time to PCLK Rising

DRVPCI Hold Time from PCLK Rising

RESET Setup Time to HCLK Rising

RESET Hold Time from HCLK Rising

15

5.9

15

b

0.3

7.0

15

b

0.5

15

3.4

0.4

15

38

82433LX/82433NX

Ý

4.4.6 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING, 60 MHz (82433LX)

e

CASE

a

0 C to 85 C

Functional Operating Range: V

Parameter

4.75V to 5.25V; T

§

CC

Symbol

t20a

t20b

t20c

t20d

t20e

t21a

t21b

t22a

t22b

t22c

t22d

t22e

t22f

Min

Max

Figure

17

Notes

[

]

AD 15:0 Output Enable Delay from PCLK Rising

2

[

]

AD 15:0 Valid Delay from PCLK Rising

2

11

14

1

[

]

AD 15:0 Setup Time to PCLK Rising

7

15

[

]

AD 15:0 Hold Time from PCLK Rising

0

15

[

]

AD 15:0 Float Delay from DRVPCI Falling

2

10

16

Ý

TRDY Setup Time to PCLK Rising

7

15

Ý

TRDY Hold Time from PCLK Rising

0

15

[

]

[

D 31:0 , HP 3:0 Output Enable Delay from HCLK Rising

]

0

7.9

17

2

[

]

[

D 31:0 , HP 3:0 Float Delay from HCLK Rising

]

3.1

2

15.5

11.0

7.8

16

[

]

[

D 31:0 , HP 3:0 Float Delay from MDLE Rising

]

16

3

2

[

]

[

D 31:0 , HP 3:0 Valid Delay from HCLK Rising

]

0

14

[

]

[

D 31:0 ,HP 3:0 Setup Time to HCLK Rising

]

3.4

0.3

0

15

[

]

[

D 31:0 , HP 3:0 Hold Time from HCLK Rising

]

15

[

]

HA 15:0 Output Enable Delay from HCLK Rising

t23a

t23b

t23c

t23cc

t23d

t23e

t23f

15.2

18.5

15.5

17

[

]

HA 15:0 Float Delay from HCLK Rising

0

16

[

]

HA 15:0 Valid Delay from HCLK Rising

0

14

7

8

4

5

[

]

HA 15:0 Valid Delay from HCLK Rising

0

[

]

HA 15:0 Setup Time to HCLK Rising

15.0

4.1

0.3

0

15

14

15

14

16

17

[

]

HA 15:0 Setup Time to HCLK Rising

[

]

HA 15:0 Hold Time from HCLK Rising

[

]

[

MD 31:0 , MP 3:0 Valid Delay from HCLK Rising

]

t24a

t24b

t24c

t25

12.0

6

2

[

]

[

MD 31:0 , MP 3:0 Setup Time to HCLK Rising

]

4.4

1.0

2.3

0

[

]

[

]

MD 31:0 , MP 3:0 Hold Time from HCLK Rising

EOL, PPOUT Valid Delay from PCLK Rising

All Outputs Float Delay from TSCON Falling

All Outputs Enable Delay from TSCON Rising

17.2

30

t26a

t26b

0

30

NOTES:

1. Min: 0 pF, Max: 50 pF

2. 0 pF

[

]

3. When NOPC command sampled on previous rising HCLK on HIG 4:0

4. CPU to PCI Transfers

[

5. When ADCPY command is sampled on HIG 4:0

6. 50 pF

]

[

]

7. When DACPYL or DACPYH commands are sampled on HIG 4:0

8. Inquire cycle

39

82433LX/82433NX

4.4.7 TEST TIMING (82433LX)

e

CASE

a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; T

§

CC

Symbol

Parameter

Min

Max

Figure

Notes

t30

All Test Signals Setup Time to

HCLK/PCLK Rising

10.0

In PLL Bypass

Mode

t31

All Test Signals Hold Time to

HCLK/PCLK Rising

12.0

In PLL Bypass

Mode

t32

t33

t34

Test Setup Time to HCLK/PCLK Rising

Test Hold Time to HCLK/PCLK Rising

PPOUT Valid Delay from PCLK Rising

15.0

5.0

15

0.0

500

In PLL Bypass

Mode

4.5 82433NX AC Characteristics

The AC specifications given in this section consist of propagation delays, valid delays, input setup require-

ments, input hold requirements, output float delays, output enable delays, clock high and low times and clock

period specifications. Figure 13 through Figure 21 define these specifications. Section 4.5 lists the AC Specifi-

cations.

e

A 15:0 , AD 15:0 , TRDY , HCLK, PCLK, RESET, TEST.

[

]

[

]

[

]

1.5V for the following signals: MD 31:0 , MP 3:0 , D 31:0 , HP 3:0 ,

[

]

In Figure 13 through Figure 21 VT

]

[

]

[

Ý

e

[ ] [ ] [ ]

2.5V for the following signals: HIG 4:0 , PIG 3:0 , MIG 2:0 , MDLE, DRVPCI, PPOUT, EOL.

VT

4.5.1 HOST AND PCI CLOCK TIMING, (82433NX)

e

e a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; V

3.135V to 3.465V, T

CASE

§

CC

CC3

Symbol

t1a

t1b

t1c

t1d

t1e

t1f

Parameter

HCLK Period

Min

15

5

Max

20

Figure

18

Notes

HCLK High Time

HCLK Low Time

HCLK Rise Time

HCLK Fall Time

18

5

18

1.5

19

1

g

HCLK Period Stability

PCLK Period

100

ps

t2a

t2b

t2c

t2d

t2e

t3

30

12

18

19

21

PCLK High Time

PCLK Low Time

PCLK Rise Time

PCLK Fall Time

HCLK to PCLK Skew

3

b

7.2

5.8

NOTE:

1. Measured on rising edge of adjacent clocks at 1.5 Volts.

40

82433LX/82433NX

4.5.2 COMMAND TIMING, (82433NX)

e

e a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; V

3.135V to 3.465V, T

CASE

§

CC

CC3

Symbol

t10a

t10b

t11a

t11b

t12a

t12b

t13a

t13b

t14a

t14b

t15a

t15b

Parameter

HIG 4:0 Setup Time to HCLK Rising

Min

5.5

Max

Figure

15

Notes

[

]

[

]

HIG 4:0 Hold Time from HCLK Rising

0

15

[

]

MIG 2:0 Setup Time to HCLK Rising

5.5

0

15

[

]

MIG 2:0 Hold Time from HCLK Rising

15

[

]

PIG 3:0 Setup Time to PCLK Rising

14.5

0.0

5.5

15

[

]

PIG 3:0 Hold Time from PCLK Rising

MDLE Setup Time to HCLK Rising

MDLE Hold Time to HCLK Rising

DRVPCI Setup Time to PCLK Rising

DRVPCI Hold Time from PCLK Rising

RESET Setup Time to HCLK Rising

RESET Hold Time from HCLK Rising

15

b

0.3

7.0

15

b

0.5

15

3.4

0.4

15

Ý

4.5.3 ADDRESS, DATA, TRDY , EOL, TEST, TSCON AND PARITY TIMING, (82433NX)

e

3.135V to 3.465V, T

CASE

a

0 C to 85 C

Functional Operating Range: V

Symbol

4.75V to 5.25V; V

§

CC

CC3

Parameter

Min

2

Max

Figure

17

Notes

[ ]

AD 15:0 Output Enable Delay from PCLK Rising

t20a

t20b

t20c

t20d

t20e

t21a

t21b

t22a

t22b

t22c

t22d

t22e

t22f

[

]

AD 15:0 Valid Delay from PCLK Rising

2

11

10

14

1

[

]

AD 15:0 Setup Time to PCLK Rising

7

15

[

]

AD 15:0 Hold Time from PCLK Rising

0

15

[

]

AD 15:0 Float Delay from DRVPCI Falling

2

16

Ý

TRDY Setup Time to PCLK Rising

7

15

Ý

TRDY Hold Time from PCLK Rising

0

15

[

]

[

D 31:0 , HP 3:0 Output Enable Delay from HCLK Rising

]

0

7.5

17

2

[

]

[

D 31:0 , HP 3:0 Float Delay from HCLK Rising

]

3.1

2

15.5

9.5

16

[

]

[

D 31:0 , HP 3:0 Float Delay from MDLE Rising

]

16

3

2

[

]

[

D 31:0 , HP 3:0 Valid Delay from HCLK Rising

]

0

7.5

14

[

]

[

D 31:0 ,HP 3:0 Setup Time to HCLK Rising

]

3.1

0.3

15

[

]

[

D 31:0 , HP 3:0 Hold Time from HCLK Rising

]

15

41

82433LX/82433NX

e

3.135V to 3.465V,

Functional Operating Range: V

e

4.75V to 5V; V

CC

CC3

a

0 C to 85 C (Continued)

T

§

CASE

Symbol

t23a

t23b

t23c

t23cc

t23d

t23e

t23f

Parameter

HA 15:0 Output Enable Delay from HCLK Rising

Min

Max

13.5

17.5

13.5

Figure

17

Notes

[

]

0

[

]

HA 15:0 Float Delay from HCLK Rising

0

16

[

]

HA 15:0 Valid Delay from HCLK Rising

0

14

7

8

4

5

[

]

HA 15:0 Valid Delay from HCLK Rising

0

[

]

HA 15:0 Setup Time to HCLK Rising

15

4.2

0.3

0

15

14

15

14

16

17

[

]

HA 15:0 Setup Time to HCLK Rising

[

]

HA 15:0 Hold Time from HCLK Rising

[

]

[

MD 31:0 , MP 3:0 Valid Delay from HCLK Rising

]

t24a

t24b

t24c

t25

12.0

6

2

[

]

[

MD 31:0 , MP 3:0 Setup Time to HCLK Rising

]

4.4

1.0

2.3

0

[

]

[

]

MD 31:0 , MP 3:0 Hold Time from HCLK Rising

EOL, PPOUT Valid Delay from PCLK Rising

All Outputs Float Delay from TSCON Falling

All Outputs Enable Delay from TSCON Rising

17.2

30

t26a

t26b

0

30

NOTE:

1. Min: 0 pF, Max: 50 pF

2. 0 pF

[

]

3. When NOPC command sampled on previous rising HCLK on HIG 4:0

4. CPU to PCI Transfers

[

5. When ADCPY command is sampled on HIG 4:0

]

6. 50 pF

7. When DACPYL or DACPYH commands are sampled on HIG 4:0

8. Inquire cycle

[

]

4.5.4 TEST TIMING (82433NX)

e

3.135V to 3.465V, T

CASE

a

0 C to 85 C

Functional Operating Range: V

4.75V to 5.25V; V

§

CC

CC3

Min

10.0

Symbol

Parameter

Max

Figure

Notes

t30

All Test Signals Setup Time to HCLK/

PCLK Rising

In PLL Bypass Mode

t31

All Test Signals Hold Time to HCLK/

PCLK Rising

12.0

In PLL Bypass Mode

t32

t33

t34

Test Setup Time to HCLK/PCLK Rising

Test Hold Time to HCLK/PCLK Rising

PPOUT Valid Delay from PCLK Rising

15.0

5.0

15

0.0

500

In PLL Bypass Mode

42

82433LX/82433NX

4.5.5 TIMING DIAGRAMS

290478–14

Figure 13. Propagation Delay

290478–15

Figure 14. Valid Delay from Rising Clock Edge

290478–16

Figure 15. Setup and Hold Times

290478–17

Figure 16. Float Delay

290478–18

Figure 17. Output Enable Delay

43

82433LX/82433NX

290478–19

Figure 18. Clock High and Low Times and Period

290478–20

Figure 19. Clock Rise and Fall Times

290478–21

Figure 20. Pulse Width

290478–22

Figure 21. Output to Output Delay

44

82433LX/82433NX

5.0 PINOUT AND PACKAGE INFORMATION

5.1 Pin Assignment

Pins 1, 22, 41, 61, and 150 are VDD3 pins on the 82433NX. These pins must be connected to the 3.3V power

supply. All other VDD pins on the 82433NX must be connected to the 5V power supply.

290478–23

Figure 22. 82433LX and 82433NX Pin Assignment

45

82433LX/82433NX

Table 5. 82433LX and 82433NX Numerical Pin Assignment

Ý

Pin Name

Type

Pin Name

D22

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

Type

t/s

V

Pin Name

D21

51

52

53

54

55

56

57

58

59

60

61

Type

t/s

V

(82433LX)

(82433NX)

1

V

DD

DD3

HP2

D25

D17

D19

D23

A14

A12

A8

D24

D27

D31

D30

D26

D29

D28

V

2

V

SS

PLLV

3

V

DD

SS

4

V

PLLAGND

LP2

5

V

6

in

LP1

7

out

in

HCLK

TEST

D6

8

V

SS

9

in

A6

V

10

11

12

13

14

15

16

17

18

19

20

21

22

t/s

in

A10

A3

V

(82433LX)

(82433NX)

V

DD

D2

DD3

D14

HIG0

HIG1

HIG2

HIG3

HIG4

MIG0

MIG1

MIG2

MD8

62

63

64

65

66

67

68

69

70

71

72

73

74

75

in

A4

D12

in

A9

D11

in

V

DD

HP1

D4

in

V

(82433LX)

DD

3 (82433NX)

DD

V

in

D0

V

42

43

44

45

46

47

48

49

50

V

in

SS

D16

A2

t/s

in

TSCON

A1

in

V

A0

t/s

SS

V

A5

MD24

MD0

V

(82433LX

DD

3 (82433NX)

DD

V

A15

A13

A11

A7

MD16

MD9

D20

D18

HP3

23

24

25

t/s

MD25

46

82433LX/82433NX

Table 5. 82433LX and 82433NX Numerical Pin Assignment (Continued)

Ý

Pin Name

MD1

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

Type

t/s

V

Pin Name

MD22

MD15

MD31

MD7

Type

t/s

V

Pin Name

AD11

Type

t/s

in

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

MD17

AD12

AD13

AD14

AD15

MDLE

MD10

V

SS

DD

V

MD23

V

DD

SS

Ý

TRDY

in

V

DD

V

SS

V

SS

V

RESET

MD26

MD2

in

MP0

MP2

MP1

MP3

AD0

AD1

AD2

AD3

t/s

V

t/s

V

PCLK

DRVPCI

PIG3

PIG2

PIG1

PIG0

D7

in

MD18

MD11

MD27

MD3

in

MD19

MD12

MD28

MD4

in

V

t/s

V

DD

V

SS

PPOUT

EOL

t/s

V

(82433LX)

3 (82433NX)

V

DD

V

DD

HP0

D8

151

152

153

154

155

156

157

158

159

160

t/s

V

MD20

t/s

V

SS

V

AD4

AD5

AD6

AD7

AD8

t/s

V

SS

D1

V

D5

MD13

MD29

MD5

t/s

D3

D10

D15

D13

D9

MD21

MD14

MD30

MD6

V

DD

AD9

t/s

AD10

V

DD

47

82433LX/82433NX

Table 6. 82433LX and 82433NX Alphabetical Pin Assignment List

Ý

Pin Name

A0

45

Type

t/s

Pin Name

AD13

AD14

AD15

D0

135

136

137

17

Type

t/s

Pin Name

D26

56

53

58

57

55

54

143

123

8

Type

t/s

in

A1

44

D27

A2

43

D28

A3

37

D29

A4

38

D1

153

11

D30

A5

46

D2

D31

A6

35

D3

155

16

DRVPCI

EOL

A7

50

D4

t/s

in

A8

34

D5

154

10

HCLK

HIG0

HIG1

HIG2

HIG3

HIG4

HP0

A9

39

D6

62

63

64

65

66

151

15

27

25

7

in

A10

A11

A12

A13

A14

A15

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

36

D7

148

152

159

156

14

in

49

D8

in

33

D9

in

48

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

in

32

t/s

out

in

47

13

HP1

116

117

118

119

125

126

127

128

129

131

132

133

134

158

12

HP2

HP3

157

18

LP1

LP2

6

29

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

72

76

85

89

93

100

104

108

70

t/s

24

30

23

51

26

31

52

28

48

82433LX/82433NX

Table 6. 82433LX and 82433NX Alphabetical Pin Assignment List (Continued)

Ý

Pin Name

MD9

74

Type

t/s

in

Pin Name

MIG1

68

Type

in

Pin Name

80

Type

V

DD

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MDLE

MIG0

78

MIG2

MP0

69

in

81

V

DD

87

112

114

113

115

142

147

146

145

144

5

t/s

in

94

V

91

MP1

110

120

121

130

139

150

V

98

MP2

V

102

106

73

MP3

V

PCLK

PIG0

PIG1

PIG2

PIG3

PLLAGND

V

in

V

77

in

V

(82433LX)

3 (82433NX)

V

DD

86

in

V

160

2

V

DD

SS

90

in

95

V

20

101

105

109

71

PLLV

3

V

DD

SS

21

4

V

42

PPOUT

RESET

TEST

122

83

t/s

in

59

60

75

9

in

79

84

TRDY

82

in

96

88

TSCON

19

in

97

92

V

(82433LX)

DD

3 (82433NX)

DD

1

V

111

124

140

141

149

99

V

(82433LX)

DD

3 (82433NX)

DD

22

V

103

107

138

67

V

40

41

V

DD

V

(82433LX)

DD

3 (82433NX)

DD

in

V

(82433LX)

DD

3 (82433NX)

DD

61

V

49

82433LX/82433NX

5.2 Package Information

290478–24

Figure 23. 82433LX and 82433NX 160-Pin QFP Package

Table 7. 160-Pin QFP Package Values

Min Value

(mm)

Max Value

Symbol

(mm)

Min Value

(mm)

Max Value

(mm)

Symbol

A

4.45

E

31.60

27.80

32.40

28.20

25.55

0.65

A1

A2

B

0.25

0.65

E1

E3

e

3.30

3.80

0.20

0.40

D

31.00

27.80

32.40

28.20

25.55

L

0.60

1.00

D1

D3

i

0

§

10

§

0.1

g

50

82433LX/82433NX

[

]

(000) and NOPC (00000) on the MIG 2:0 and

6.0 TESTABILITY

[

]

HIG 4:0 lines and driving two rising edges on

HCLK. A rising edge on PCLK with RESET high will

cause the LBXs to exit PLL bypass mode. TEST

must remain high throughout the use of the NAND

tree. The combination of TEST and DRVPCI high

with a rising edge of PCLK must be avoided. TSCON

must be driven high throughout testing since driving

it low would tri-state the output of the NAND tree. A

10 ns hold time is required on all inputs sampled by

PCLK or HCLK when in PLL bypass mode.

The TSCON pin may be used to help test circuits

surrounding the LBX. During normal operations, the

TSCON pin must be tied to VCC or connected to

VCC through a pull-up resistor. All LBX outputs are

tri-stated when the TSCON pin is held low or

grounded.

6.1 NAND Tree

A NAND tree is provided in the LBX for Automated

Test Equipment (ATE) board level testing. The

NAND tree allows the tester to set the connectivity

of each of the LBX signal pins.

6.1.1 TEST VECTOR TABLE

The following test vectors can be applied to the

82433LX and 82433NX to put it into PLL bypass

mode and to enable NAND tree testing.

The following steps must be taken to put the LBX

into PLL bypass mode and enable the NAND tree.

First, to enable PLL bypass mode, drive RESET in-

active, TEST active, and the DCPWA command

6.1.2 NAND TREE TABLE

Table 9 shows the sequence of the NAND tree in

the 82433LX and 82433NX. Non-inverting inputs are

driven directly into the input of a NAND gate in the

tree. Inverting inputs are driven into an inverter be-

fore going into the NAND tree. The output of the

NAND tree is driven on the PPOUT pin.

[

]

(0100) on the PIG 3:0 lines. Then drive PCLK from

low to high. DRVPCI must be held low on all rising

edges of PCLK during testing in order to ensure that

[

]

the LBX does not drive the AD 15:0 lines. The host

and memory buses are tri-stated by driving NOPM

Table 8. Test Vectors to put LBX Into PLL Bypass and Enable NAND Tree Testing

LBX

1

2

3

4

5

6

7

8

9

10

11

Ý

Pin/Vector

PCLK

0

1

0

1

[

PIG 3:0

]

0h

1

0h

1

0h

1

4h

0

4h

0

4h

0

4h

1

4h

1

4h

1

4h

1

4h

1

RESET

HCLK

0

1

0

1

0

[

MIG 2:0

]

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

0h

1

[

HIG 4:0

]

TEST

DRVPCI

0

51

82433LX/82433NX

Table 9. NAND Tree Sequence

Non-

Ý

Order Pin Signal

Order Pin

Signal

Order Pin

Signal

Inverting

1

10

11

12

13

14

15

16

17

18

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

D6

Y

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

62

63

64

65

66

67

68

69

70

71

A2

Y

N

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

72

73

74

75

76

77

78

82

83

84

85

86

87

88

89

90

91

92

93

95

98

99

MD0

N

Y

2

D2

A1

MD16

MD9

3

D14

D12

D11

HP1

D4

A0

4

A5

MD25

MD1

5

A15

A13

A11

A7

6

MD17

MD10

7

Ý

8

D0

TRDY

RESET

MD26

MD2

9

D16

D20

D18

HP3

D22

HP2

D25

D17

D19

D23

A14

A12

A8

D21

D24

D27

D31

D30

D26

D29

D28

HIG0

HIG1

HIG2

HIG3

HIG4

MIG0

MIG1

MIG2

MD8

MD24

N

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

MD18

MD11

MD27

MD3

MD19

MD12

MD28

MD4

MD20

MD13

MD29

A6

A10

A3

100 MD5

101 MD21

102 MD14

103 MD30

A4

A9

52

82433LX/82433NX

Table 9. NAND Tree Sequence (Continued)

Non-

Ý

Order Pin Signal

Order Pin

Signal

Order Pin

Signal

Inverting

79

80

81

82

83

84

85

86

87

88

89

90

91

82

93

104

105

106

107

108

109

112

113

114

115

116

117

118

119

123

MD6

MD22

MD15

MD31

MD7

MD23

MP0

MP2

MP1

MP3

AD0

N

Y

94

125 AD4

126 AD5

127 AD6

128 AD7

129 AD8

131 AD9

132 AD10

133 AD11

134 AD12

135 AD13

136 AD14

137 AD15

138 MDLE

143 DRVPCI

Y

N

108

109

110

111

112

113

114

115

116

117

118

119

120

121

144

145

146

147

148

151

152

153

154

155

156

157

158

159

PIG3

PIG2

PIG1

PIG0

D7

N

Y

95

96

97

98

99

HP0

D8

100

101

102

103

104

105

106

107

D1

D5

D3

D10

D15

D13

D9

AD1

AD2

AD3

EOL

6.2 PLL Test Mode

The high order 82433NX LBX samples A11 at the

falling edge of reset to configure the LBX for PLL

test mode. When A11 is sampled low, the LBX is in

normal operating mode. When A11 is sampled high,

the LBX drives the internal HCLK from the PLL on

the EOL pin.

53


型号：	S82433NX
厂家：	INTEL
描述：	LOCAL BUS ACCELERATOR (LBX) LOCAL BUS加速器（ LBX ）总线控制器微控制器和处理器外围集成电路 PC 时钟
文件：	总53页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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