SB80L186EC25_技术文档

80C186EC/80C188EC AND 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

X

Fully Static Operation

X

True CMOS Inputs and Outputs

Y

Integrated Feature Set:

Ð Low-Power, Static, Enhanced 8086

CPU Core

Ð Two Independent DMA Supported

UARTs, each with an Integral Baud

Rate Generator

Available in Extended Temperature

b a

Range ( 40 C to 85 C)

§

Supports 80C187 Numerics Processor

Y

Extension (80C186EC only)

Package Types:

Ð 100-Pin EIAJ Quad Flat Pack (QFP)

Ð 100-Pin Plastic Quad Flat Pack

(PQFP)

Ð 100-Pin Shrink Quad Flat Pack

(SQFP)

Ð Four Independent DMA Channels

Ð 22 Multiplexed I/O Port Pins

Ð Two 8259A Compatible

Programmable Interrupt Controllers

Ð Three Programmable 16-Bit Timer/

Counters

Ð 32-Bit Watchdog Timer

Ð Ten Programmable Chip Selects with

Integral Wait-State Generator

Ð Memory Refresh Control Unit

Ð Power Management Unit

Ð On-Chip Oscillator

Y

Speed Versions Available (5V):

Ð 25 MHz (80C186EC25/80C188EC25)

Ð 20 MHz (80C186EC20/80C188EC20)

Ð 13 MHz (80C186EC13/80C188EC13)

Speed Version Available (3V):

Ð 16 MHz (80L186EC16/80L188EC16)

Ð 13 MHz (80L186EC13/80L188EC13)

Ð System Level Testing Support

(ONCE Mode)

Y

Direct Addressing Capability to 1 Mbyte

Memory and 64 Kbyte I/O

Low-Power Operating Modes:

Ð Idle Mode Freezes CPU Clocks but

Keeps Peripherals Active

Ð Powerdown Mode Freezes All

Internal Clocks

Ð Powersave Mode Divides All Clocks

by Programmable Prescalar

The 80C186EC is a member of the 186 Integrated Processor Family. The 186 Integrated Processor Family

incorporates several different VLSI devices all of which share a common CPU architecture: the 8086/8088.

The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common

system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic

silicon die.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1996

May 1996

Order Number: 272434-004

80C186EC/80C188EC and 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION

EMBEDDED PROCESSOR

CONTENTS

PAGE

CONTENTS PAGE

Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

80C186EC CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4

Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

I

versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 29

CC

PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

AC CharacteristicsÐ80C186EC25 ÀÀÀÀÀÀÀÀÀ 30

AC CharacteristicsÐ80C186EC20/13 ÀÀÀÀÀ 32

AC CharacteristicsÐ80L186EC13 ÀÀÀÀÀÀÀÀÀ 33

AC CharacteristicsÐ80L186EC16 ÀÀÀÀÀÀÀÀÀ 34

Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

80C186EC PERIPHERAL

ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

Programmable Interrupt Controllers ÀÀÀÀÀÀÀÀÀ 7

Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Watchdog Timer Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

80C187 Interface (80C186EC only) ÀÀÀÀÀÀÀÀÀ 8

ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50

INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 51

ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀ 24

ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 25

Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

2

80C186EC/188EC, 80L186EC/188EC

272434–1

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC

Figure 1. 80C186EC/80L186EC Block Diagram

3

80C186EC/188EC, 80L186EC/188EC

INTRODUCTION

80C186EC CORE ARCHITECTURE

Bus Interface Unit

Unless specifically noted, all references to the

80C186EC apply to the 80C188EC, 80L186EC, and

80L188EC. References to pins that differ between

the 80C186EC/80L186EC and the 80C188EC/

80L188EC are given in parentheses. The ‘‘L’’ in the

part number denotes low voltage operation. Physi-

cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are

identical.

The 80C186EC core incorporates a bus controller

that generates local bus control signals. In addition,

it employs a HOLD/HLDA protocol to share the local

bus with other bus masters.

The bus controller is responsible for generating 20

bits of address, read and write strobes, bus cycle

status information and data (for write operations) in-

formation. It is also responsible for reading data

from the local bus during a read operation. A ready

input pin is provided to extend a bus cycle beyond

the minimum four states (clocks).

The 80C186EC is one of the highest integration

members of the 186 Integrated Processor Family.

Two serial ports are provided for services such as

interprocessor communication, diagnostics and mo-

dem interfacing. Four DMA channels allow for high

speed data movement as well as support of the on-

board serial ports. A flexible chip select unit simpli-

fies memory and peripheral interfacing. The three

general purpose timer/counters can be used for a

variety of time measurement and waveform genera-

tion tasks. A watchdog timer is provided to insure

system integrity even in the most hostile of environ-

ments. Two 8259A compatible interrupt controllers

handle internal interrupts, and, up to 57 external in-

terrupt requests. A DRAM refresh unit and 24 multi-

plexed I/O ports round out the feature set of the

80C186EC.

The bus controller also generates two control sig-

nals (DEN and DT/R) when interfacing to external

transceiver chips. This capability allows the addition

of transceivers for simple buffering of the multi-

plexed address/data bus.

Clock Generator

The 80C186EC provides an on-chip clock generator

for both internal and external clock generation. The

clock generator features a crystal oscillator, a divide-

by-two counter and three low-power operating

modes.

The future set of the 80C186EC meets the needs of

low-power, space-critical applications. Low-power

applications benefit from the static design of the

CPU and the integrated peripherals as well as low

voltage operation. Minimum current consumption is

achieved by providing a powerdown mode that halts

operaton of the device and freezes the clock cir-

cuits. Peripheral design enhancements ensure that

non-initialized peripherals consume little current.

The oscillator circuit is designed to be used with ei-

ther a parallel resonant fundamental or third-over-

tone mode crystal network. Alternatively, the oscilla-

tor circuit may be driven from an external clock

source. Figure 2 shows the various operating modes

of the oscillator circuit.

The 80L186EC is the 3V version of the 80C186EC.

The 80L186EC is functionally identical to the

The crystal or clock frequency chosen must be twice

the required processor operating frequency due to

the internal divide-by-two counter. This counter is

used to drive all internal phase clocks and the exter-

nal CLKOUT signal. CLKOUT is a 50% duty cycle

processor clock and can be used to drive other sys-

tem components. All AC timings are referenced to

CLKOUT.

80C186EC

embedded

processor.

Current

80C186EC users can easily upgrade their designs to

use the 80L186EC and benefit from the reduced

power consumption inherent in 3V operation.

Figure 1 shows a block diagram of the 80C186EC/

80C188EC. The execution unit (EU) is an enhanced

8086 CPU core that includes: dedicated hardware to

speed up effective address calculations, enhanced

execution speed for multiple-bit shift and rotate in-

structions and for multiply and divide instructions,

string move instructions that operate at full bus

bandwidth, ten new instructions and fully static oper-

ation. The bus interface unit (BIU) is the same as

that found on the original 186 family products, ex-

cept the queue-status mode has been deleted and

buffer interface control has been changed to ease

system design timings. An independent internal bus

is used for communication between the BIU and on-

chip peripherals.

The following parameters are recommended when

choosing a crystal:

Temperature Range:

Application Specific

ESR (Equivalent Series Res.):

40X max

C0 (Shunt Capacitance of Crystal):

(Load Capacitance):

7.0 pF max

g

20 pF 2 pF

C

L

Drive Level:

1 mW (max)

4

80C186EC/188EC, 80L186EC/188EC

272434–2

NOTE:

1. The LC network is only required when using a third overtone crystal.

Figure 2. 80C186EC Clock Connections

Ð 10-Output Chip-Select Unit

Ð 32-bit Watchdog Timer Unit

80C186EC PERIPHERAL

ARCHITECTURE

Ð I/O Port Unit

The 80C186EC integrates several common system

peripherals with a CPU core to create a compact, yet

powerful system. The integrated peripherals are de-

signed to be flexbile and provide logical interconnec-

tions between supporting units (e.g., the DMA unit

can accept requests from the Serial Communica-

tions Unit).

Ð Refresh Control Unit

Ð Power Management Unit

The registers associated with each integrated pe-

ripheral are contained within a 128 x 16-bit register

file called the Peripheral Control Block (PCB). The

base address of the PCB is programmable and can

be located on any 256 byte address boundary in ei-

ther memory or I/O space.

The list of integrated peripherals includes:

Ð Two cascaded, 8259A compatible, Programma-

ble Interrupt Controllers

Figure 3 provides a list of the registers associated

with the PCB. The Register Bit Summary individually

lists all of the registers and identifies each of their

programming attributes.

Ð 3-Channel Timer/Counter Unit

Ð 2-Channel Serial Communications Unit

Ð 4-Channel DMA Unit

5

80C186EC/188EC, 80L186EC/188EC

PCB

Function

Offset

00H

02H

04H

06H

08H

Master PIC Port 0

Master PIC Port 1

Slave PIC Port 0

Slave PIC Port 1

Reserved

40H

42H

44H

46H

48H

4AH

T2 Count

T2 Compare

Reserved

80H

82H

84H

86H

88H

8AH

8CH

8EH

90H

92H

94H

96H

98H

9AH

9CH

9EH

A0H

A2H

A4H

A6H

GCS0 Start

GCS0 Stop

GCS1 Start

GCS1 Stop

GCS2 Start

GCS2 Stop

GCS3 Start

GCS3 Stop

GCS4 Start

GCS4 Stop

GCS5 Start

GCS5 Stop

GCS6 Start

GCS6 Stop

GCS7 Start

GCS7 Stop

LCS Start

C0H DMA 0 Source Low

C2H DMA 0 Source High

C4H

DMA 0 Dest. Low

T2 Control

C6H DMA 0 Dest. High

Port 3 Direction

Port 3 Pin State

C8H

CAH

CCH

CEH

DMA 0 Count

DMA 0 Control

DMA Module Pri.

DMA Halt

0AH SCU Int. Req. Ltch.

0CH DMA Int. Req. Ltch.

0EH TCU Int. Req. Ltch.

4CH Port 3 Mux Control

4EH

50H

52H

Port 3 Data Latch

Port 1 Direction

Port 1 Pin State

10H

12H

14H

16H

18H

1AH

1CH

1EH

20H

22H

24H

26H

28H

2AH

2CH

2EH

30H

32H

34H

46H

38H

3AH

3CH

3EH

Reserved

D0H DMA 1 Source Low

D2H DMA 1 Source High

Reserved

54H Port 1 Mux Control

D4H

DMA 1 Dest. Low

Reserved

56H

58H

5AH

Port 1 Data Latch

Port 2 Direction

Port 2 Pin State

D6H DMA 1 Dest. High

Reserved

D8H

DAH

DCH

DEH

DMA 1 Count

DMA 1 Control

Reserved

5CH Port 2 Mux Control

Reserved

5EH

60H

62H

64H

66H

68H

6AH

6CH

6EH

70H

72H

74H

76H

78H

7AH

7CH

7EH

Port 2 Data Latch

SCU 0 Baud

SCU 0 Count

SCU 0 Control

SCU 0 Status

SCU 0 RBUF

SCU 0 TBUF

Reserved

WDT Reload High

WDT Reload Low

WDT Count High

WDT Count Low

WDT Clear

E0H DMA 2 Source Low

E2H DMA 2 Source High

LCS Stop

UCS Start

E4H

DMA 2 Dest. Low

UCS Stop

E6H DMA 2 Dest. High

A8H Relocation Register

E8H

EAH

ECH

EEH

DMA 2 Count

DMA 2 Control

Reserved

WDT Disable

Reserved

AAH

ACH

AEH

Reserved

T0 Count

SCU 1 Baud

SCU 1 Count

SCU 1 Control

SCU 1 Status

SCU 1 RBUF

SCU 1 TBUF

Reserved

B0H Refresh Base Addr.

F0H DMA 3 Source Low

F2H DMA 3 Source High

T0 Compare A

T0 Compare B

T0 Control

B2H

B4H

B6H

B8H

BAH

BCH

BEH

Refresh Time

Refresh Control

Refresh Address

Power Control

Reserved

F4H

DMA 3 Dest. Low

F6H DMA 3 Dest. High

T1 Count

F8H

FAH

FCH

FEH

DMA 3 Count

DMA 3 Control

Reserved

T1 Compare A

T1 Compare B

T1 Control

Step ID

Reserved

Powersave

Reserved

Figure 3. Peripheral Control Block Registers

6

80C186EC/188EC, 80L186EC/188EC

DMA requests can be external (on the DRQ pins),

internal (from Timer 2 or a serial channel) or soft-

ware initiated.

Programmable Interrupt Controllers

The 80C186EC utilizes two 8259A compatible Pro-

grammable Interrupt Controllers (PIC) to manage

both internal and external interrupts. The 8259A

modules are configured in a master/slave arrange-

ment.

The DMA Unit transfers data as bytes only. Each

data transfer requires at least two bus cycles, one to

fetch data and one to deposit. The minimum clock

count for each transfer is 8, but this will vary depend-

ing on synchronization and wait states.

Seven of the external interrupt pins, INT0 through

INT6, are connected to the master 8259A module.

The eighth external interrupt pin, INT7, is connected

to the slave 8259A module.

Chip-Select Unit

The 80C186EC Chip-Select Unit (CSU) integrates

logic which provides up to ten programmable chip-

selects to access both memories and peripherals. In

addition, each chip-select can be programmed to

automatically insert additional clocks (wait states)

into the current bus cycle, and/or automatically ter-

minate a bus cycle independent of the condition of

the READY input pin.

There are a total of 11 internal interrupt sources

from the integrated peripherals: 4 Serial, 4 DMA and

3 Timer/Counter.

Timer/Counter Unit

The 80C186EC Timer/Counter Unit (TCU) provides

three 16-bit programmable timers. Two of these are

highly flexible and are connected to external pins for

external control or clocking. The third timer is not

connected to any external pins and can only be

clocked internally. However, it can be used to clock

the other two timer channels. The TCU can be used

to count external events, time external events, gen-

erate non-repetitive waveforms or generate timed in-

terrupts.

I/O Port Unit

The I/O Port Unit on the 80C186EC supports two

8-bit channels and one 6-bit channel of input, output

or input/output operation. Port 1 is multiplexed with

the chip select pins and is output only. Port 2 is mul-

tiplexed with the pins for serial channels 1 and 2. All

Port 2 pins are input/output. Port 3 has a total of 6

pins: four that are multiplexed with DMA and serial

port interrupts and two that are non-multiplexed,

open drain I/O.

Serial Communications Unit

The 80C186EC Serial Communications Unit (SCU)

contains two independent channels. Each channel is

identical in operation except that only channel 0 is

directly supported by the integrated interrupt control-

ler (the channel 1 interrupts are routed to external

interrupt pins). Each channel has its own baud rate

generator and can be internally or externally clocked

up to one half the processor operating frequency.

Both serial channels can request service from the

DMA unit thus providing block reception and trans-

mission without CPU intervention.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen-

erates a periodic memory read bus cycle to keep

dynamic or pseudo-static memory refreshed. A 9-bit

counter controls the number of clocks between re-

fresh requests.

A 12-bit address generator is maintained by the RCU

and is presented on the A12:1 address lines during

the refresh bus cycle. Address bits A19:13 are pro-

grammable to allow the refresh address block to be

located on any 8 Kbyte boundary.

Independent baud rate generators are provided for

each of the serial channels. For the asynchronous

modes, the generator supplies an 8x baud clock to

both the receive and transmit shifting register logic.

A 1x baud clock is provided in the synchronous

mode.

Watchdog Timer Unit

The Watchdog Timer Unit (WDT) allows for graceful

recovery from unexpected hardware and software

upsets. The WDT consists of a 32-bit counter that

decrements every clock cycle. If the counter reach-

es zero before being reset, the WDTOUT pin is

DMA Unit

The four channel Direct Memory Access (DMA) Unit

is comprised of two modules with two channels

each. All four channels are identical in operation.

DMA transfers can take place from memory to mem-

ory, I/O to memory, memory to I/O or I/O to I/O.

7

80C186EC/188EC, 80L186EC/188EC

pulled low for four clock cycles. Logically ANDing

the WDTOUT pin with the power-on reset signal al-

lows the WDT to reset the device in the event of a

WDT timeout. If a less drastic method of recovery is

desired, WDTOUT can be connected directly to NMI

or one of the INT input pins. The WDT may also be

used as a general purpose timer.

and information, see the Intel Packaging Outlines

and Dimensions Guide (Order Number: 231369).

Prefix Identification

Table 1 lists the prefix identifications.

Table 1. Prefix Identification

Package

Type

Temperature

Range

Prefix Note

Power Management Unit

TS

QFP (EIAJ) Extended

The 80C186EC Power Management Unit (PMU) is

provided to control the power consumption of the

device. The PMU provides four power management

modes: Active, Powersave, Idle and Powerdown.

KU

SB

S

1

PQFP

SQFP

Extended/Commercial

QFP (EIAJ) Commercial

Active Mode indicates that all units on the

80C186EC are operating at (/2 the CLKIN frequency.

NOTE:

1. The 5V 25 MHz version is only available in commercial

a

temperature range corresponding to 0 C to 70 C am-

bient.

§

Idle Mode freezes the clocks of the Execution and

Bus units at a logic zero state (all peripherals contin-

ue to operate normally).

Pin Descriptions

The Powerdown Mode freezes all internal clocks at

a logic zero level and disables the crystal oscillator.

Each pin or logical set of pins is described in Table

2. There are four columns for each entry in the Pin

Description Table. The following sections describe

each column.

In Powersave Mode, all internal clock signals are di-

vided by a programmable prescalar (up to (/64 the

normal frequency). Powersave Mode can be used

with Idle Mode as well as during normal (Active

Mode) operation.

Column 1: Pin Name

In this column is a mnemonic that de-

scribes the pin function. Negation of the

signal name (i.e. RESIN) implies that the

signal is active low.

80C187 Interface (80C186EC only)

Column 2: Pin Type

The 80C186EC supports the direct connection of

the 80C187 Numerics Processor Extension. The

80C187 can dramatically improve the performance

of calculation intensive applications.

A pin may be either power (P), ground

(G), input only (I), output only (O) or in-

put/output (I/O). Please note that some

pins have more than

1

function.

A19/S6/ONCE, for example, is normally

an output but functions as an input dur-

ONCE Test Mode

ing

reset.

For

this

reason

A19/S6/ONCE is classified as an input/

output pin.

To facilitate testing and inspection of devices when

fixed into a target system, the 80C186EC has a test

mode available which forces all output and input/

output pins to be placed in the high-impedance

state. ONCE stands for ‘‘ON Circuit Emulation’’.

The ONCE mode is selected by forcing the

A19/S6/ONCE pin low during a processor reset

(this pin is weakly held high during reset to prevent

inadvertant entrance into ONCE Mode).

Column 3: Input Type (for I and I/O types only)

There are two different types of input

pins on the 80C186EC: asynchronous

and synchronous. Asynchronous pins

require that setup and hold times be met

only to guarantee recognition. Synchro-

nous input pins require that the setup

and hold times be met to guarantee

proper operation. Stated simply, missing

a setup or hold on an asynchronous pin

will result in something minor (i.e. a timer

count will be missed) whereas missing a

setup or hold on a synchronous pin will

result in system failure (the system will

‘‘lock up’’).

PACKAGE INFORMATION

This section describes the pin functions, pinout and

thermal characteristics for the 80C186EC in the

Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ

Quad Flat Pack (QFP) and the Shrink Quad Flat

Pack (SQFP). For complete package specifications

An input pin may also be edge or level

sensitive.

8

80C186EC/188EC, 80L186EC/188EC

Column 4: Output States (for O and I/O types

only)

the processor is in the Hold Acknowledge state.

R(Z) indicates that these pins will float while RESIN

is low. P(0) and I(0) indicate that these pins will drive

0 when the device is in either Powerdown or Idle

Mode.

The state of an output or I/O pin is de-

pendent on the operating mode of the

device. There are four modes of opera-

tion that are different from normal active

mode: Bus Hold, Reset, Idle Mode, Pow-

erdown Mode. This column describes

the output pin state in each of these

modes.

Some pins, the I/O Ports for example, can be pro-

grammed to perform more than one function. Multi-

function pins have a ‘‘/’’ in their signal name be-

tween the different functions (i.e. P3.0/RXI1). If the

input pin type or output pin state differ between func-

tions, then that will be indicated by separating the

state (or type) with a ‘‘/’’ (i.e. H(X)/H(Q)). In this

example when the pin is configured as P3.0 then its

hold output state is H(X); when configured as RXI1

its output state is H(Q).

The legend for interpreting the information in the Pin

Descriptions is shown in Table 1.

As an example, please refer to the table entry for

AD12:0. The ‘‘I/O’’ signifies that the pins are bidirec-

tional (i.e. have both an input and output function).

The ‘‘S’’ indicates that, as an input the signal must

be synchronized to CLKOUT for proper operation.

The ‘‘H(Z)’’ indicates that these pins will float while

All pins float while the processor is in the ONCE

Mode (with the exception of OSCOUT).

Table 1. Pin Description Nomenclature

Description

Symbol

a

Ground (connect to V

Input only pin

Output only pin

Input/Output pin

P

G

I

O

I/O

Power Pin (apply

V

)

SS

voltage)

CC

S(E)

S(L)

A(E)

A(L)

Synchronous, edge sensitive

Synchronous, level sensitive

Asynchronous, edge sensitive

Asynchronous, level sensitive

H(1)

H(0)

H(Z)

H(Q)

H(X)

Output driven to V during bus hold

CC

Output driven to V during bus hold

Output floats during bus hold

Output remains active during bus hold

Output retains current state during bus hold

SS

R(WH)

R(1)

R(0)

R(Z)

R(Q)

R(X)

Output weakly held at V during reset

CC

Output driven to V during reset

SS

Output floats during reset

Output remains active during reset

Output retains current state during reset

CC

I(1)

I(0)

I(Z)

I(Q)

I(X)

Output driven to V during Idle Mode

CC

Output driven to V during Idle Mode

Output floats during Idle Mode

Output remains active during Idle Mode

Output retains current state during Idle Mode

SS

P(1)

P(0)

P(Z)

P(Q)

P(X)

Output driven to V during Powerdown Mode

CC

Output driven to V during Powerdown Mode

Output floats during Powerdown Mode

Output remains active during Powerdown Mode

Output retains current state during Powerdown Mode

SS

9

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions

Output

States

Type

Input

Type

Pin Name

Pin Description

a

POWER 5V 10% power supply connection

g

V

P

G

I

Ð

CC

SS

Ð

GROUND

CLKIN

A(E)

Ð

CLocK INput is the external clock input. An external

oscillator operating at two times the required processor

operating frequency can be connected to CLKIN. For

crystal operation, CLKIN (along with OSCOUT) are the

crystal connections to an internal Pierce oscillator.

OSCOUT

O

Ð

H(Q)

R(Q)

I(Q)

OSCillator OUTput is only used when using a crystal to

generate the internal clock. OSCOUT (along with CLKIN)

are the crystal connections to an internal Pierce oscillator.

This pin can not be used as 2X clock output for non-

crystal applications (i.e. this pin is not connected for non-

crystal applications).

P(X)

CLKOUT

RESIN

O

I

Ð

H(Q)

R(Q)

I(Q)

CLocK OUTput provides a timing reference for inputs and

outputs of the processor, and is one-half the input clock

(CLKIN) frequency. CLKOUT has a 50% duty cycle and

transitions every falling edge of CLKIN.

P(X)

A(L)

Ð

RESet IN causes the processor to immediately terminate

any bus cycle in progress and assume an initialized state.

All pins will be driven to a known state, and RESOUT will

also be driven active. The rising edge (low-to-high)

transition synchronizes CLKOUT with CLKIN before the

processor begins fetching opcodes at memory location

0FFFF0H.

RESOUT

PDTMR

O

Ð

H(0)

R(1)

I(0)

RESet OUTput that indicates the processor is currently in

the reset state. RESOUT will remain active as long as

RESIN remains active.

P(0)

I/O

A(L)

H(WH)

R(Z)

P(WH)

I(WH)

Power-Down TiMeR pin (normally connected to an

external capacitor) that determines the amount of time the

processors waits after an exit from Powerdown before

resuming normal operation. The duration of time required

will depend on the startup characteristics of the crystal

oscillator.

NMI

I

A(E)

Ð

Non-Maskable Interrupt input causes a TYPE-2 interrupt

to be serviced by the CPU. NMI is latched internally.

TEST/BUSY

(TEST)

TEST is used during the execution of the WAIT instruction

to suspend CPU operation until the pin is sampled active

(LOW). TEST is alternately known as BUSY when

interfacing with an 80C187 numerics coprocessor

(80C186EC only).

A19/S6/ONCE

I/O

A(L)

H(Z)

R(WH)

I(0)

This pin drives address bit 19 during the address phase of

the bus cycle. During T2 and T3 this pin functions as

status bit 6. S6 is low to indicate CPU bus cycles and high

to indicate DMA or refresh bus cycles. During a processor

reset (RESIN active) this pin becomes the ONCE input

pin. Holding this pin low during reset will force the part into

ONCE Mode.

P(0)

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

10

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Input

Type

Output

States

Pin Name

Pin Description

Type

A18/S5

A17/S4

A16/S3

(A15:8)

I/O

A(L)

H(Z)

R(WH)

I(0)

These pins drive address information during the address

phase of the bus cycle. During T2 and T3 these pins drive

status information (which is always 0 on the 80C186EC).

These pins are used as inputs during factory test; driving

these pins low during reset will cause unspecified operation.

On the 80C188EC, A15:8 provide valid address information

for the entire bus cycle.

P(0)

AD15/CAS2

AD14/CAS1

AD13/CAS0

I/O

S(L)

H(Z)

R(Z)

I(0)

These pins are part of the multiplexed ADDRESS and DATA

bus. During the address phase of the bus cycle, address bits

15 through 13 are presented on these pins and can be

latched using ALE. Data information is transferred during the

data phase of the bus cycle. Pins AD15:13/CAS2:0 drive the

82C59 slave address information during interrupt

acknowledge cycles.

P(0)

AD12:0

(AD7:0)

I/O

O

S(L)

Ð

H(Z)

R(Z)

I(0)

These pins provide a multiplexed ADDRESS and DATA bus.

During the address phase of the bus cycle, address bits 0

through 12 (0 through 7 on the 80C188EC) are presented on

the bus and can be latched using ALE. Data information is

transferred during the data phase of the bus cycle.

P(0)

S2:0

H(Z)

R(1)

I(1)

Bus cycle Status are encoded on these pins to provide bus

transaction information. S2:0 are encoded as follows:

P(1)

S2

S1

S0

Bus Cycle Initiated

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge

Read I/O

Write I/O

Processor HALT

Instruction Queue Fetch

Read Memory

Write Memory

Passive (No bus activity)

ALE

O

Ð

H(0)

R(0)

I(0)

Address Latch Enable output is used to strobe address

information into a transparent type latch during the address

phase of the bus cycle.

P(0)

BHE

(RFSH)

H(Z)

R(Z)

I(1)

Byte High Enable output to indicate that the bus cycle in

progress is transferring data over the upper half of the data

bus. BHE and A0 have the following logical encoding:

P(1)

Encoding (for 80C186EC/

80L186EC only)

A0

BHE

0

1

0

1

0

1

Word transfer

Even Byte transfer

Odd Byte transfer

Refresh operation

On the 80C188EC/80L188EC, RFSH is asserted low to

indicate a refresh bus cycle.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

11

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Output

Input

Type

Pin Name

Pin Description

Type

States

RD

O

Ð

H(Z)

R(Z)

I(1)

ReaD output signals that the accessed memory or I/O

device should drive data information onto the data bus.

P(1)

WR

O

Ð

H(Z)

R(Z)

I(1)

WRite output signals that data available on the data bus are

to be written into the accessed memory or I/O device.

P(1)

READY

DEN

I

A(L)

S(L)

Ð

READY input to signal the completion of a bus cycle. READY

must be active to terminate any 80C186EC bus cycle, unless

it is ignored by correctly programming the Chip-Select unit.

(Note 1)

O

Ð

H(Z)

R(Z)

I(1)

Data ENable output to control the enable of bi-directional

transceivers in a buffered system. DEN is active only when

data is to be transferred on the bus.

P(1)

DT/R

LOCK

O

Ð

H(Z)

R(Z)

I(X)

Data Transmit/Receive output controls the direction of a bi-

directional buffer in a buffered system.

P(X)

I/O

A(L)

H(Z)

R(Z)

I(X)

LOCK output indicates that the bus cycle in progress is not

interruptable. The processor will not service other bus

requests (such as HOLD) while LOCK is active. This pin is

configured as a weakly held high input while RESIN is active

and must not be driven low.

P(X)

HOLD

HLDA

I

A(L)

Ð

HOLD request input to signal that an external bus master

wishes to gain control of the local bus. The processor will

relinquish control of the local bus between instruction

boundaries that are not LOCKed.

O

H(1)

R(0)

I(0)

HoLD Acknowledge output to indicate that the processor

has relinquished control of the local bus. When HLDA is

asserted, the processor will (or has) floated its data bus and

control signals allowing another bus master to drive the

signals directly.

P(0)

NCS

O

I

Ð

H(1)

R(1)

I(1)

Numerics Coprocessor Select output is generated when

acessing a numerics coprocessor. This signal does not exist

on the 80C188EC/80L188EC.

P(1)

ERROR

A(L)

Ð

ERROR input that indicates the last numerics processor

extension operation resulted in an exception condition. An

interrupt TYPE 16 is generated if ERROR is sampled active

at the beginning of a numerics operation. Systems not using

an 80C187 must tie ERROR to V . This signal does not

CC

exist on the 80C188EC/80L188EC.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

12

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Input

Type

Output

States

Pin Name

Pin Description

Type

PEREQ

I

A(L)

Ð

Processor Extension REQuest signals that a data

transfer between an 80C187 Numerics Processor

Extension and Memory is pending. Systems not using an

80C187 must tie this pin to V . This signal does not exist

SS

on the 80C188EC/80L188EC.

UCS

LCS

O

Ð

H(1)

R(1)

I(1)

Upper Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

programmed by the user. After reset, UCS is configured to

be active for memory accesses between 0FFC00H and

0FFFFFH.

P(1)

O

Ð

H(1)

R(1)

I(1)

Lower Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

programmed by the user. LCS is inactive after a reset.

P(1)

P1.0/GCS0

P1.1/GCS1

P1.2/GCS2

P1.3/GCS3

P1.4/GCS4

P1.5/GCS5

P1.6/GCS6

P1.7/GCS7

H(X)/H(1)

R(1)

These pins provide a multiplexed function. If enabled,

each pin can provide a General purpose Chip Select

output which will go active whenever the address of a

memory or I/O bus cycle is within the address limitations

programmed by the user. When not programmed as a

Chip-Select, each pin may be used as a general purpose

output port.

I(X)/I(1)

P(X)/P(1)

T0OUT

T1OUT

O

Ð

H(Q)

R(1)

I(Q)

Timer OUTput pins can be programmed to provide single

clock or continuous waveform generation, depending on

the timer mode selected.

P(X)

T0IN

T1IN

I

A(L)

A(E)

Ð

Timer INput is used either as clock or control signals,

depending on the timer mode selected. This pin may be

either level or edge sensitive depending on the

programming mode.

INT7:0

INTA

A(L)

A(E)

Ð

Maskable INTerrupt input will cause a vector to a specific

Type interrupt routine. The INT6:0 pins can be used as

cascade inputs from slave 8259A devices. The INT pins

can be configured as level or edge sensitive.

O

Ð

A(L)

Ð

H(1)

R(1)

I(1)

INTerrupt Acknowledge output is a handshaking signal

used by external 82C59A Programmable Interrupt

Controllers.

P(1)

P3.5

P3.4

I/O

O

H(X)

R(Z)

I(X)

Bidirectional, open-drain port pins.

H(X)

P3.3/DMAI1

P3.2/DMAI0

H(X)

R(0)

I(Q)

DMA Interrupt output goes active to indicate that the

channel has completed a transfer. DMAI1 and DMAI0 are

multiplexed with output only port functions.

P(X)

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

13

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Output

Input

Type

Pin Name

Pin Description

Type

States

P3.1/TXI1

O

Ð

H(X)/H(Q)

R(0)

I(Q)

Transmit Interrupt output goes active to indicate that

serial channel 1 has completed a transfer. TXI1 is

multiplexed with an output only Port function.

P(X)

P3.0/RXI1

WDTOUT

O

Ð

H(X)/H(Q)

R(0)

I(Q)

Receive Interrupt output goes active to indicate that

serial channel 1 has completed a reception. RXI1 is

multiplexed with an output only port function.

P(X)

O

Ð

H(Q)

R(1)

I(Q)

WatchDog Timer OUTput is driven low for four clock

cycles when the watchdog timer reaches zero. WDTOUT

may be ANDed with the power-on reset signal to reset the

processor when the watchdog timer is not properly reset.

P(X)

P2.7/CTS1

P2.3/CTS0

I/O

A(L)

H(X)

R(Z)

I(X)

Clear-To-Send input is used to prevent the transmission

of serial data on the TXD signal pin. CTS1 and CTS0 are

multiplexed with an I/O Port function.

P(X)

P2.6/BCLK1

P2.2/BCLK0

A(L)/

A(E)

H(X)

R(Z)

I(X)

Baud CLocK input can be used as an alternate clock

source for each of the integrated serial channels. The

BCLK inputs are multiplexed with I/O Port functions. The

BCLK input frequency cannot exceed (/2 the operating

frequency of the processor .

P(X)

P2.5/TXD1

P2.1/TXD0

I/O

A(L)

H(Q)

R(Z)

Transmit Data output provides serial data information.

The TXD outputs are multiplexed with I/O Port functions.

During synchronous serial communications, TXD will

function as a clock output.

I(X)/I(Q)

P(X)

P2.4/RXD1

P2.0/RXD0

H(X)/H(Q)

R(Z)

Receive Data input accepts serial data information. The

RXD pins are multiplexed with I/O Port functions. During

synchronous serial communications, RXD is bi-directional

and will become an output for transmission of data (TXD

becomes the clock).

I(X)/I(Q)

P(X)

DRQ3:0

I

A(L)

Ð

DMA ReQuest input pins are used to request a DMA

transfer. The timing of the request is dependent on the

programmed synchronization mode.

NOTES:

1. READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.

2. Pin names in parentheses apply to the 80C188EC/80L188EC.

14

80C186EC/188EC, 80L186EC/188EC

from the top side of the component (i.e. contacts

facing down).

Pinout

Tables 3 and 4 list the pin names with package loca-

tion for the 100-pin Plastic Quad Flat Pack (PQFP)

component. Figure 4 depicts the PQFP package as

viewed from the top side of the component (i.e. con-

tacts facing down).

Tables 7 and 8 list the pin names with package loca-

tion for the 100-pin Shrink Quad Flat Pack (SQFP)

component. Figure 6 depicts the SQFP package as

viewed from the top side of the component (i.e., con-

tacts facing down).

Tables 5 and 6 list the pin names with package loca-

tion for the 100-pin EIAJ Quad Flat Pack (QFP) com-

ponent. Figure 5 depicts the QFP package as viewed

Table 3. PQFP Pin Functions with Location

Bus Control Processor Control

Name Name Pin

ALE

AD Bus

Name

I/O

Name

UCS

LCS

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

73

72

71

70

66

65

64

63

60

59

58

57

56

55

52

51

78

79

80

50

49

85

47

46

48

44

45

34

RESIN

8

7

88

89

BHE (RFSH)

S0

S1

RESOUT

CLKIN

10

11

6

OSCOUT

CLKOUT

TEST/BUSY

(TEST)

P1.7/GCS7

P1.6/GCS6

P1.5/GCS5

P1.4/GCS4

P1.3/GCS3

P1.2/GCS2

P1.1/GCS1

P1.0/GCS0

90

91

92

93

94

95

96

97

S2

RD

83

WR

READY

DEN

PEREQ (V

SS

NCS (N.C.)

)

81

35

84

9

AD8 (A8)

AD9 (A9)

DT/R

LOCK

HOLD

HLDA

INTA

ERROR (V

PDTMR

NMI

)

CC

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13/CAS0

(A13/CAS0)

AD14/CAS1

(A14/CAS1)

AD15/CAS2

(A15/CAS2)

A16/S3

82

30

31

32

33

40

41

42

43

INT0

INT1

P2.7/CTS1

P2.6/BCLK1

P2.5/TXD1

P2.4/RXD1

P2.3/CTS0

P2.2/BCLK0

P2.1/TXD0

P2.0/RXD0

23

22

21

20

19

18

17

16

INT2

INT3

54

53

Power and Ground

INT4

INT5

Name

INT6

INT7

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

13

14

38

62

67

69

86

12

15

37

39

61

68

87

77

76

75

74

A17/S4

A18/S5

A19/S6/ONCE

P3.5

P3.4

29

28

27

26

25

24

P3.3/DMAI1

P3.2/DMAI0

P3.1/TXI1

P3.0/RXI1

T0IN

3

2

5

4

T0OUT

T1IN

T1OUT

DRQ0

DRQ1

DRQ2

DRQ3

98

99

100

1

WDTOUT

36

15

80C186EC/188EC, 80L186EC/188EC

Table 4. PQFP Pin Locations with Pin Name

Name

1

2

DRQ3

T0OUT

T0IN

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

DMAI0/P3.2

DMAI1/P3.3

P3.4

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

BHE (RFSH)

ALE

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

A17/S4

A16/S3

S0

3

AD15 (A15)

AD14 (A14)

AD13 (A13)

AD12 (A12)

AD11 (A11)

AD10 (A10)

AD9 (A9)

4

T1OUT

T1IN

P3.5

INT0

S1

S2

5

6

CLKOUT

RESOUT

RESIN

PDTMR

CLKIN

INT1

INT2

PEREQ (V

NMI

TEST

)

SS

7

8

INT3

INTA

9

ERROR (V )

CC

READY

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

NCS (N.C.)

WDTOUT

AD8 (A8)

V

OSCOUT

V

SS

CC

V

SS

CC

SS

CC

SS

V

AD7

AD6

AD5

AD4

UCS

LCS

CC

V

SS

V

INT4

INT5

INT6

INT7

HOLD

HLDA

DT/R

DEN

LOCK

WR

P1.7/GCS7

P1.6/GCS6

P1.5/GCS5

P1.4/GCS4

P1.3/GCS3

P1.2/GCS2

P1.1/GCS1

P1.0/GCS0

DRQ0

SS

P2.0/RXD0

P2.1/TXD0

P2.2/BCLK0

P2.3/CTS0

P2.4/RXD1

P2.5/TXD1

P2.6/BCLK1

P2.7/CTS1

P3.0/RXI1

P3.1/TXI1

V

CC

V

SS

V

CC

AD3

AD2

AD1

AD0

A19/S6/ONCE

A18/S5

DRQ1

DRQ2

RD

16

80C186EC/188EC, 80L186EC/188EC

272434–3

NOTE:

This is the FPO number location (indicated by X’s).

Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)

17

80C186EC/188EC, 80L186EC/188EC

Table 5. QFP Pin Names with Package Location

AD Bus

Name

Bus Control

Name

Processor Control

Name Pin

RESIN

I/O

Name

UCS

LCS

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

76

75

74

73

69

68

67

66

63

62

61

60

59

58

ALE

55

54

81

82

83

53

52

88

50

49

51

47

48

37

11

10

13

14

9

91

92

BHE (RFSH)

S0

S1

RESOUT

CLKIN

OSCOUT

CLKOUT

TEST/BUSY

(TEST)

P1.7/GCS7

P1.6/GCS6

P1.5/GCS5

P1.4/GCS4

P1.3/GCS3

P1.2/GCS2

P1.1/GCS1

P1.0/GCS0

93

94

S2

RD

86

95

96

WR

READY

DEN

PEREQ (V

SS

NCS (N.C.)

)

84

38

87

12

85

33

34

35

36

43

44

45

46

97

98

AD8 (A8)

AD9 (A9)

DT/R

LOCK

HOLD

HLDA

INTA

ERROR (V

PDTMR

NMI

)

99

100

CC

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13/CAS0

(A13/CAS0)

AD14/CAS1

(A14/CAS1)

AD15/CAS2

(A15/CAS2)

A16/S3

INT0

INT1

P2.7/CTS1

P2.6/BCLK1

P2.5/TXD1

P2.4/RXD1

P2.3/CTS0

P2.2/BCLK0

P2.1/TXD0

P2.0/RXD0

26

25

24

23

22

21

20

19

INT2

INT3

57

56

Power and Ground

INT4

INT5

Name

INT6

INT7

V

16

17

41

65

70

72

89

15

18

40

42

64

71

90

CC

SS

80

79

78

77

A17/S4

A18/S5

A19/S6/ONCE

P3.5

P3.4

32

31

30

29

28

27

P3.3/DMAI1

P3.2/DMAI0

P3.1/TXI1

P3.0/RXI1

T0IN

6

5

8

7

T0OUT

T1IN

T1OUT

DRQ0

DRQ1

DRQ2

DRQ3

1

2

3

4

WDTOUT

39

18

80C186EC/188EC, 80L186EC/188EC

Table 6. QFP Package Location with Pin Names

Name

1

2

DRQ0

DRQ1

DRQ2

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

P2.7/CTS1

P3.0/RXI1

P3.1/TXI1

DMAI0/P3.2

DMAI1/P3.3

P3.4

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

LOCK

WR

RD

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

AD0

A19/S6/ONCE

A18/S5

A17/S4

A16/S3

S0

3

4

DRQ3

T0OUT

T0IN

BHE (RFSH)

ALE

5

6

AD15 (A15)

AD14 (A14)

AD13 (A13)

AD12 (A12)

AD11 (A11)

AD10 (A10)

AD9 (A9)

AD8 (A8)

7

T1OUT

T1IN

P3.5

INT0

S1

S2

8

9

CLKOUT

RESOUT

RESIN

PDTMR

CLKIN

OSCOUT

INT1

INT2

PEREQ (V

NMI

TEST

)

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

INT3

INTA

ERROR (V )

CC

READY

NCS (N.C.)

WDTOUT

V

CC

V

SS

UCS

LCS

SS

V

SS

CC

SS

CC

V

AD7

AD6

AD5

AD4

CC

V

SS

V

INT4

INT5

INT6

INT7

HOLD

HLDA

DT/R

DEN

P1.7/GCS7

P1.6/GCS6

P1.5/GCS5

P1.4/GCS4

P1.3/GCS3

P1.2/GCS2

P1.1/GCS1

P1.0/GCS0

SS

P2.0/RXD0

P2.1/TXD0

P2.2/BCLK0

P2.3/CTS0

P2.4/RXD1

P2.5/TXD1

P2.6/BCLK1

V

CC

V

SS

V

CC

AD3

AD2

AD1

19

80C186EC/188EC, 80L186EC/188EC

272434–4

NOTE:

This is the FPO number location (indicated by X’s).

Figure 5. Quad Flat Pack (EIAJ) Pinout Diagram

20

80C186EC/188EC, 80L186EC/188EC

Table 7. SQFP Pin Functions with Location

Bus Control Processor Control

ALE

AD Bus

I/O

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

73

72

71

70

66

65

64

63

60

59

58

57

56

55

54

53

77

76

75

74

52

51

78

79

80

50

49

85

46

47

48

44

45

RESIN

RESOUT

CLKIN

OSCOUT

CLKOUT

TEST/BUSY

NMI

8

UCS

LCS

88

89

BHE (RFSH)

S0

S1

7

10

11

6

P1.0/GCS0

P1.1/GCS1

P1.2/GCS2

P1.3/GCS3

P1.4/GCS4

P1.5/GCS5

P1.6/GCS6

P1.7/GCS7

97

96

95

94

93

92

91

90

S2

RD

83

82

30

31

32

33

40

41

42

43

34

81

84

35

9

WR

READY

DT/R

DEN

INT0

INT1

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16

INT2

INT3

LOCK

HOLD

HLDA

INT4

INT5

P2.0/RXD0

P2.1/TXD0

P2.2/BCLK0

P2.3/CTS0

P2.4/RXD1

P2.5/TXD1

P2.6/BCLK1

P2.7/CTS1

16

17

18

19

20

21

22

23

INT6

INT7

INTA

PEREQ (V

ERROR (V

)

SS

A17

A18

)

CC

NCS (N.C.)

PDTMR

A19/ONCE

P3.0/RXI1

P3.1/TXI1

P3.2/DMAI0

P3.3/DMAI1

P3.4

24

25

26

27

28

29

Power and Ground

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

13

14

38

62

67

69

86

12

15

37

39

61

68

87

P3.5

DRQ0

DRQ1

DRQ2

DRQ3

98

99

100

1

T0IN

T0OUT

T1IN

3

2

5

T1OUT

WDTOUT

4

36

21

80C186EC/188EC, 80L186EC/188EC

Table 8. SQFP Pin Locations with Pin Names

Name

DRQ3

Name

76

77

78

79

80

81

82

83

A17

A16

S0

1

2

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

P3.2/DMAI0

P3.3/DMAI1

P3.4

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

BHE (RFSH)

ALE

T0OUT

T0IN

3

AD15 (A15)

AD14 (A14)

AD13 (A13)

AD12 (A12)

AD11 (A11)

AD10 (A10)

AD9 (A9)

S1

S2

4

T1OUT

T1IN

P3.5

5

INT0

PEREQ (V

MNI

)

SS

6

CLKOUT

RESOUT

RESIN

PDTMR

CLKIN

INT1

7

INT2

TEST/BUSY

(TEST)

8

INT3

9

INTA

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

ERROR (V

READY

)

CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

NSC (N.C.)

WDTOUT

AD8 (A8)

OSCOUT

V

SS

CC

V

CC

V

SS

CC

SS

CC

SS

AD7 (A7)

AD6 (A6)

AD5

UCS

LCS

INT4

INT5

INT6

INT7

HOLD

HLDA

DT/R

DEN

LOCK

WR

P1.7/GCS7

P1.6/GS6

P1.5/GCS5

P1.4/GCS4

P1.3/GCS3

P1.2/GCS2

P1.1/GCS1

P1.0/GCS0

DRQ0

P2.0/RXD0

P2.1/TXD0

P2.2/BCLK0

P2.3/CTS0

P2.4/RXD1

P2.5/TXD1

P2.6/BCLK1

P2.7/CTS1

P3.0/RXI1

P3.1/TXI1

AD4

V

CC

SS

CC

AD3

AD2

AD1

AD0

A19/ONCE

AD18

DRQ1

DRQ2

RD

22

80C186EC/188EC, 80L186EC/188EC

272434–5

NOTE:

This is the FPO number location (indicated by X’s)

Figure 6. 100-Pin Shrink Quad Flat Pack Package (SQFP)

23

80C186EC/188EC, 80L186EC/188EC

T

(the ambient temperature) can be calculated

A

Package Thermal Specifications

from i (thermal resistance from the case to ambi-

CA

ent) with the following equation:

The 80C186EC/80L186EC is specified for operation

when T (the case temperature) is within the range

C

e

b

P * i

T

C

b

a

A

CA

of 40 C to 100 C. T may be measured in any

C

§

environment to determine whether the processor is

within the specified operating range. The case tem-

perature must be measured at the center of the top

surface.

Typical values for i

in Table 9. P (the maximum power consumptionÐ

specified in Watts) is calculated by using the maxi-

at various airflows are given

CA

mum I

and V

of 5.5V.

CC

Table 9. Thermal Resistance (i ) at Various Airflows (in C/Watt)

§

CA

Airflow in ft/min (m/sec)

0

200

400

600

800

1000

(0)

(1.01)

(2.03)

(3.04)

(4.06)

(5.07)

i

(PQFP)

(QFP)

27.0

64.5

62.0

22.0

55.5

TBD

18.0

51.0

TBD

15.0

TBD

14.0

TBD

13.5

TBD

CA

(SQFP)

24

80C186EC/188EC, 80L186EC/188EC

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

b

a

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

b

a

Case Temperature Under BiasÀÀÀ 65 C to 100 C

§

Supply Voltage

b

a

with Respect to V ÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 6.5V

SS

Voltage on Other Pins

with Respect to V

b

ÀÀÀÀÀÀ 0.5V to V

a

0.5V

SS

CC

Low inductance capacitors and interconnects are

recommended for best high frequency electrical per-

formance. Inductance is reduced by placing the de-

coupling capacitors as close as possible to the proc-

Recommended Connections

Power and ground connections must be made to

multiple V and V pins. Every 80C186EC-based

essor V

and V package pins.

SS

CC SS

circuit board should include separate power (V

CC

)

CC

pin must be

and ground (V ) planes. Every V

SS

Always connect any unused input to an appropriate

signal level. In particular, unused interrupt inputs

(NMI, INT0:7) should be connected to V through a

CC

connected to the power plane, and every V

SS

must be connected to the ground plane. Liberal de-

coupling capacitance should be placed near the

processor. The processor can cause transient pow-

er surges when its output buffers transition, particu-

larly when connected to large capacitive loads.

SS

pull-down resistor. Leave any unused output pin un-

connected.

25

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80C186EC/80C188EC)

Symbol

Parameter

Supply Voltage

Min

Max

Units

V

Notes

V

4.5

5.5

CC

IL

b

Input Low Voltage

0.5

0.7 V

0.3 V

V

CC

a

V

CC

Input High Voltage

0.5

V

IH

CC

e

Output Low Voltage

Output High Voltage

Input Hysteresis on RESIN

0.45

V

I

3 mA (Min)

OL

OH

HYR

OL

b

e b

2 mA (Min)

V

0.5

V

CC

OH

0.5

V

s

V

g

I

Input Leakage Current for Pins:

AD15:0 (AD7:0, A15:8), READY,

HOLD, RESIN,

15

mA

0

V

LI

IN

CC

CLKIN, TEST/BUSY, NMI, INT7:0,

T0IN, T1IN, P2.7–P2.0, P3.5–P3.0,

DRQ3:0, PEREQ, ERROR

b

e

0.7 V

IN

(Note 1)

I

Input Leakage for Pins with Pullups

Active During Reset:

A19:16, LOCK

0.275

5

mA

V

LIU

CC

s

V

g

I

Output Leakage for Floated Output

Pins

15

mA

0.45

(Note 2)

V

LO

CC

OUT

CC

Supply Current Cold (in RESET)

80C186EC25

80C186EC20

125

100

70

mA

(Notes 3, 7)

(Note 3)

80C186EC13

I

Supply Current in Idle Mode

80C186EC25

80C186EC20

ID

92

76

50

mA

(Notes 4, 7)

(Note 4)

80C186EC13

Supply Current in Powerdown Mode

80C186EC25

80C186EC20

PD

100

mA

(Notes 5, 7)

(Note 5)

80C186EC13

e

C

Input Pin Capacitance

Output Pin Capacitance

0

15

pF

T

1 MHz

1 MHz (Note 6)

IN

F

OUT

NOTES:

1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as

CC

or GND.

specified in AC Test Conditions, and all floating outputs driven to V

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

6. Output Capacitance is the capacitive load of a floating output pin.

CC

a

7. Operating conditions for 25 MHz is 0 C to 70 C, V

e

g

5.0 10%.

§

CC

26

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80L186EC13/80L188EC13)

Symbol

Parameter

Supply Voltage

Min

Max

Units

V

Notes

V

2.7

5.5

CC

IL

b

Input Low Voltage

0.5

0.7 V

0.3 V

V

CC

a

V

CC

Input High Voltage

0.5

V

IH

CC

e

Output Low Voltage

Output High Voltage

Input Hysteresis on RESIN

0.45

V

I

3 mA (Min)

OL

OH

HYR

OL

b

e b

2 mA (Min)

V

0.5

V

CC

OH

0.5

V

s

V

g

I

Input Leakage Current for Pins:

AD15:0 (AD7:0, A15:8), READY,

HOLD, RESIN, CLKIN,

15

mA

0

V

LI

IN

CC

TEST/BUSY, NMI, INT7:0,

T0IN, T1IN, P2.7–P2.0, P3.5–P3.0,

DRQ3:0, PEREQ, ERROR

b

e

0.7 V

IN

(Note 1)

I

Input Leakage for Pins with Pullups

Active During Reset:

A19:16, LOCK

0.275

5

mA

V

LIU

CC

s

V

g

I

Output Leakage for Floated Output

Pins

15

mA

0.45

(Note 2)

V

LO

CC

ID

OUT

CC

Supply Current Cold (in RESET)

80L186EC-13

(Note 3)

(Note 4)

(Note 5)

36

mA

Supply Current in Idle Mode

80L186EC-13

24

Supply Current in Powerdown Mode

80L186EC-13

PD

30

15

mA

pF

e

C

Input Pin Capacitance

Output Pin Capacitance

0

T

1 MHz

1 MHz (Note 6)

IN

F

OUT

NOTES:

1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as

CC

or GND.

specified in AC Test Conditions, and all floating outputs driven to V

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

6. Output Capacitance is the capacitive load of a floating output pin.

CC

27

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80L186EC16/80L188EC16) (Operating Temperature 0 C to 70 C)

§

Symbol

Parameter

Supply Voltage

Min

Max

Units

V

Notes

V

3.0

5.5

CC

IL

b

Input Low Voltage

0.5

0.7 V

0.3 V

V

CC

a

V

CC

Input High Voltage

0.5

V

IH

CC

e

Output Low Voltage

Output High Voltage

Input Hysteresis on RESIN

0.45

V

I

3 mA (Min)

e b

2 mA (Min)

OL

OH

HYR

OL

b

V

0.5

V

CC

OH

0.5

V

s

V

g

I

Input Leakage Current for Pins:

AD15:0 (AD7:0, A15:8), READY,

HOLD, RESIN, CLKIN,

15

mA

0

V

LI

IN

CC

TEST/BUSY, NMI, INT7:0,

T0IN, T1IN, P2.7–P2.0, P3.5–P3.0,

DRQ3:0, PEREQ, ERROR

b

e

0.7 V

IN

(Note 1)

I

Input Leakage for Pins with Pullups

Active During Reset:

A19:16, LOCK

0.275

5

mA

V

LIU

CC

s

V

g

I

Output Leakage for Floated Output

Pins

15

mA

0.45

(Note 2)

V

LO

CC

ID

OUT

CC

Supply Current Cold (in RESET)

80L186EC-16

(Note 3)

(Note 4)

(Note 5)

45

mA

Supply Current in Idle Mode

80L186EC-16

35

Supply Current in Powerdown Mode

80L186EC-16

PD

50

15

mA

pF

e

C

Input Pin Capacitance

Output Pin Capacitance

0

T

1 MHz

1 MHz (Note 6)

IN

F

OUT

NOTES:

1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as

CC

or GND.

specified in AC Test Conditions, and all floating outputs driven to V

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL

CC

or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

CC

or GND.

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V

6. Output Capacitance is the capacitive load of a floating output pin.

CC

28

80C186EC/188EC, 80L186EC/188EC

PDTMR Pin Delay Calculation

I

CC

versus Frequency and Voltage

The I consumed by the processor is composed of

CC

two components:

The PDTMR pin provides a delay between the as-

sertion of NMI and the enabling of the internal

clocks when exiting Powerdown Mode. A delay is

required only when using the on chip oscillator to

allow the crystal or resonator circuit to stabilize.

1. I ÐThe quiescent current that represents inter-

PD

nal device leakage. Measured with all inputs at

either V

or ground and no clock applied.

CC

2. I

ÐThe switching current used to charge and

CCS

NOTE:

discharge internal parasitic capacitance when

changing logic levels. I is related to both the

frequency of operation and the device supply

The PDTMR pin function does not apply when

RESIN is asserted (i.e. a device reset while in Pow-

erdown is similar to a cold reset and RESIN must

remain active until after the oscillator has stabilized.

CCS

voltage (V ). I

is given by the formula:

CC CCS

2

e

V

Power

.

V * I

* C

* f

DEV

To calculate the value of capacitor to use to provide

a desired delay, use the equation:

e

. . I

V * C

* f

CCS

DEV

c

e

C

Where:

440

t

(5V, 25 C)

§

PD

e

V

C

f

Supply Voltage (V

)

CC

Where:

e

Device Capacitance

DEV

e

Operating Frequency

t

desired delay in seconds

e

C

capacitive load on PDTMR in microfarads

PD

Measuring C

would be difficult. Instead, C

on a device like the 80C186EC

is calculated using

values measured at

PD

Example. For a delay of 300 ms, a capacitor value of

PD

b

e

0.132 mF is required.

6

e

c

the above formula with I

CC

known V and frequency. Using the C value, the

C

440 (300 10

PD

Round up to a standard (available) capacitor value.

CC PD

user can calculate I at any voltage and frequency

CC

within the specified operating range.

NOTE:

The above equation applies to delay time longer

than 10 ms and will compute the TYPICAL capaci-

tance needed to achieve the desired delay. A delay

Example. Calculate typical I at 14 MHz, 5.2V V

CC

.

CC

e

a

I

a

b

variance of

temperature, voltage, and device process ex-

tremes. In general, higher V and/or lower tem-

50% to

25% can occur due to

CC

PD

0.1 mA

56.2 mA

CCS

a

5.2V * 0.77 * 14 MHz

CC

peratures will decrease delay time, while lower V

CC

and/or higher temperature will increase delay time.

Parameter

CPD

CPD (Idle Mode)

Typical

0.77

Max

1.37

0.96

Units

Notes

1, 2

mA/V*MHz

0.55

1, 2

NOTES:

1. Maximum C is measured at 40 C with all outputs loaded as specified in the AC test conditions and the device in reset

b

§

PD

(or Idle Mode). Due to tester limitations, CLKOUT and OSCOUT also have 50 pF loads that increase I

by V*C*F.

CC

2. Typical C is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode).

§

PD

29

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC25

25 MHz

Symbol

Parameter

Units

Notes

Min

Max

INPUT CLOCK

T

CLKIN Frequency

CLKIN Period

0

20

8

50

%

10

MHz

ns

1

F

1

C

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

ns

1, 2

1, 3

CH

CL

CR

CF

8

1

ns

1

OUTPUT CLOCK

T

CLKIN to CLKOUT Delay

CLKOUT Period

0

17

ns

1, 4

1

CD

2*T

C

b

a

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

(T/2)

5

(T/2)

5

1

PH

PL

PR

PF

1

6

1, 5

1

6

OUTPUT DELAYS

T

ALE, S2:0, DEN, DT/R,

BHE (RFSH), LOCK, A19:16

3

17

ns

1, 4, 6, 7

CHOV1

T

GCS0:7, LCS, UCS, NCS, RD, WR

3

20

17

ns

1, 4, 6, 8

1, 4, 6

CHOV2

BHE (RFSH), DEN, LOCK, RESOUT,

HLDA, T0OUT, T1OUT, A19:16

CLOV1

T

RD, WR, GCS7:0, LCS, UCS, AD15:0

(AD7:0, A15:8), NCS, INTA1:0, S2:0

3

0

20

ns

1, 4, 6

CLOV2

CHOF

CLOF

RD, WR, BHE (RFSH), DT/R,

LOCK, S2:0, A19:16

1

DEN, AD15:0 (AD7:0, A15:8)

30

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC25 (Continued)

25 MHz

Symbol

Parameter

Units

Notes

Min

Max

SYNCHRONOUS INPUTS

T

TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0,

P2.6, P2.7

10

ns

1, 9

CHIS

T

TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0

AD15:0 (AD7:0), READY

3

10

3

ns

1, 9

1, 10

1, 9

CHIH

CLIS

CLIH

CLIS

CLIH

READY, AD15:0 (AD7:0)

HOLD, PEREQ, ERROR

10

3

HOLD, PEREQ, ERROR

1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V for high time, V for low time.

IH IL

3. Only required to guarantee I . Maximum limits are bounded by T , T

C

and T

.

CL

CC

CH

4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6. See Figure 14 for rise and fall times.

7. T

8. T

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

applies to RD and WR only after a HOLD release.

CHOV1

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

31

80C186EC/188EC, 80L186EC/188EC

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EC-20/80C186EC-13

Symbol

Parameter

Min

Max

Min

Max

Unit Notes

INPUT CLOCK

20 MHz

13 MHz

TF

TC

TCH

TCL

TCR

TCF

CLKIN Frequency

CLKIN Period

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

0

25

10

1

40

%

10

0

38.5

12

1

26

%

10

MHz

ns

1

1, 2

1, 3

1

ns

OUTPUT CLOCK

T

CLKIN to CLKOUT Delay

CLKOUT Period

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

0

17

0

23

ns

1, 4

1

1, 5

CD

2 * TC

b

a

b

a

(T/2) 5 (T/2)

b

(T/2) 5 (T/2)

5 (T/2) 5 (T/2)

b

5 (T/2) 5 (T/2)

5

PH

PL

PR

PF

1

6

1

6

OUTPUT DELAYS

T

ALE, S2:0, DEN, DT/R,

BHE (RFSH), LOCK, A19:16

3

0

20

23

20

23

25

3

0

25

30

25

30

ns 1, 4, 6, 7

ns 1, 4, 6, 8

ns 1, 4, 6

CHOV1

CHOV2

CLOV1

CLOV2

CHOF

GCS7:0, LCS, UCS,

RD, WR, NCS, WDTOUT

BHE (RFSH), DEN, LOCK, RESOUT,

HLDA, T0OUT, T1OUT

RD, WR, GSC7:0, LCS, UCS, AD15:0

(AD7:0, A15:8), NCS, INTA, S2:0, A19:16

RD, WR, BHE (RFSH), DT/R, LOCK,

S2:0, A19:16

ns

1

DEN, AD15:0 (AD7:0, A15:8)

CLOF

INPUT REQUIREMENTS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

10

3

10

3

ns

1, 9

CHIS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

CHIH

T

AD15:0 (AD7:0), READY

10

3

10

3

ns

1, 10

1, 9

CLIS

CLIH

CLIS

CLIH

AD15:0 (AD7:0), READY

HOLD, RESIN, PEREQ, ERROR, DRQ3:0

HOLD, RESIN, REREQ, ERROR, DRQ3:0

10

3

10

3

1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V for high time, V for low time.

IH IL

3. Only required to guarantee I . Maximum limits are bounded by T , T

C

and T

.

CL

CC

CH

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

6. See Figure 15 for rise and fall times.

7. T

8. T

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

applies to RD and WR only after a HOLD release.

CHOV1

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

32

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC13

Symbol

Parameter

Min

Max

Unit

Notes

INPUT CLOCK

13 MHz

T

CLKIN Frequency

CLKIN Period

0

38.5

15

1

26

%

10

MHz

ns

1

F

1

C

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

ns

1, 2

1, 3

CH

CL

CR

CF

ns

1

OUTPUT CLOCK

T

CLKIN to CLKOUT Delay

CLKOUT Period

0

20

ns

1, 4

1

CD

2 * TC

b

a

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

(T/2)

5

(T/2)

5

1

PH

PL

PR

PF

1

10

1, 5

1

OUTPUT DELAYS

T

S2:0, DT/R, BHE, LOCK

3

28

32

ns

1, 4, 6, 7

1, 4, 6, 8

CHOV1

CHOV2

LCS, UCS, DEN, A19:16, RD, WR, NCS,

WDTOUT, ALE

T

GCS7:0

3

34

28

32

ns

1, 4, 6

CHOV3

CLOV1

CLOV2

LOCK, RESOUT, HLDA, T0OUT, T1OUT

RD, WR, AD15:0 (AD7:0, A15:8), BHE

(RFSH), NCS, INTA, DEN

T

GSC7:0, LCS, UCS

S2:0, A19:16

3

0

34

37

30

ns

1, 4, 6

1

CLOV3

CLOV4

CHOF

RD, WR, BHE (RFSH), DT/R, LOCK,

S2:0, A19:16

T

DEN, AD15:0 (AD7:0, A15:8)

0

35

ns

1

CLOF

INPUT REQUIREMENTS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

20

3

ns

1, 9

CHIS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

CHIH

T

AD15:0 (AD7:0), READY

20

3

ns

1, 10

1, 9

CLIS

CLIH

CLIS

CLIH

AD15:0 (AD7:0), READY

HOLD, RESIN, PEREQ, ERROR, DRQ3:0

HOLD, RESIN, REREQ, ERROR, DRQ3:0

20

3

1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V for high time, V for low time.

IH IL

3. Only required to guarantee I . Maximum limits are bounded by T , T

C

and T

.

CL

CC

CH

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

33

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC13 (Continued)

NOTES:

6. See Figure 15 for rise and fall times.

7. T

8. T

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

applies to RD and WR only after a HOLD release.

CHOV1

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

AC CharacteristicsÐ80L186EC16 (Operating Temperature 0 C to 70 C)

§

Max

Symbol

Parameter

Min

Unit

Notes

INPUT CLOCK

16 MHz

T

CLKIN Frequency

CLKIN Period

0

31.25

13

1

32

%

10

MHz

ns

1

F

1

C

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

ns

1, 2

1, 3

CH

CL

CR

CF

ns

1

OUTPUT CLOCK

T

CLKIN to CLKOUT Delay

CLKOUT Period

0

20

ns

1, 4

1

CD

2 * TC

b

a

CLKOUT High Time

CLKOUT Low Time

CLKOUT Rise Time

CLKOUT Fall Time

(T/2)

5

(T/2)

5

1

PH

PL

PR

PF

1

9

1, 5

1

9

OUTPUT DELAYS

T

S2:0, DT/R, BHE, LOCK

3

25

30

ns

1, 4, 6, 7

1, 4, 6, 8

CHOV1

CHOV2

LCS, UCS, DEN, A19:16, RD, WR, NCS,

WDTOUT, ALE

T

GCS7:0

3

32

25

30

ns

1, 4, 6

CHOV3

CLOV1

CLOV2

LOCK, RESOUT, HLDA, T0OUT, T1OUT

RD, WR, AD15:0 (AD7:0, A15:8), BHE

(RFSH), NCS, INTA, DEN

T

GSC7:0, LCS, UCS

S2:0, A19:16

3

0

32

34

28

ns

1, 4, 6

1

CLOV3

CLOV4

CHOF

RD, WR, BHE (RFSH), DT/R, LOCK,

S2:0, A19:16

T

DEN, AD15:0 (AD7:0, A15:8)

0

32

ns

1

CLOF

INPUT REQUIREMENTS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

15

3

ns

1, 9

CHIS

T

TEST, NMI, T1IN, T0IN, READY,

CTS1:0, BCLK1:0, P3.4, P3.5

CHIH

T

AD15:0 (AD7:0), READY

15

3

ns

1, 10

1, 9

CLIS

CLIH

CLIS

CLIH

AD15:0 (AD7:0), READY

HOLD, RESIN, PEREQ, ERROR, DRQ3:0

15

3

1, 9

34

80C186EC/188EC, 80L186EC/188EC

AC CharacteristicsÐ80L186EC16 (Continued)

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measure at V for high time, V for low time.

IH IL

3. Only required to guarantee I . Maximum limits are bounded by T , T

CC

and T

.

CL

C

CH

4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.

6. See Figure 15 for rise and fall times.

7. T

8. T

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

applies to RD and WR only after a HOLD release.

CHOV1

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)

Symbol

Parameter

Min

Max

Unit

Notes

RELATIVE TIMINGS

b

T

ALE Active Pulse Width

T

15

ns

LHLL

b

AD Valid Setup before ALE Falls

Chip Select Valid before ALE Falls

AD Hold after ALE Falls

(/2T

10

15

10

AVLL

PLLL

b

1

LLAX

LLWL

LLRL

ALE Falling to WR Falling

ALE Falling to RD Falling

1

WR Rising to Next ALE Rising

AD Float to RD Falling

WHLH

AFRL

RLRH

WLWH

RHAX

WHDX

WHPH

RHPH

PHPL

0

b

RD Active Pulse Width

2T

5

2

WR Active Pulse Width

b

15

RD Rising to Next Address Active

Output Data Hold after WR Rising

WR Rise to Chip Select Rise

RD Rise to Chip Select Rise

T

b

15

b

(/2T

10

1

b

Chip Select Inactive to Next Chip

Select Active

T

ONCE Active Setup to RESIN Rising

ONCE Hold after RESIN Rise

T

ns

OVRH

RHOX

IHIL

T

b

INTA High to Next INTA Low

during INTA Cycle

4T

2T

5

4

b

T

INTA Active Pulse Width

ns

2, 4

ILIH

CAS2:0 Setup before 2nd INTA

Pulse Low

8T

CVIL

T

CAS2:0 Hold after 2nd INTA Pulse Low

Interrupt Resolution Time

4T

ns

2, 4

3

ILCX

IRES

IRLH

IRHIF

150

IR Low Time to Reset Edge Detector

IR Hold Time after 1st INTA Falling

50

25

4, 5

35

80C186EC/188EC, 80L186EC/188EC

Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)

NOTES:

1. Assumes equal loading on both pins.

2. Can be extended using wait states.

3. Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the

8259A module going active. This is not directly measureable by the user. For interrupt pin INT7 the delay from an active

signal to an active input to the CPU would actually be twice the T

modules.

value since the signal must pass through two 8259A

IRES

4. See INTA Cycle Waveforms for definition.

5. To guarantee interrupt is not spurious.

Serial Port Mode 0 Timings (80C186EC-25/20/13, 80L186EC-16/13)

Symbol

Parameter

Min

Max

Unit

Notes

RELATIVE TIMINGS

a

T

TXD Clock Period

TXD Clock Low to Clock High (N 1)

T (n

1)

ns

1, 2

1

XLXL

XLXH

XHXL

QVXH

l

b

a

35

2T

T

35

2T

T

e

l

b

a

35

TXD Clock Low to Clock High (N

1)

35

1

b

a

35

TXD Clock High to Clock Low (N 1)

(n

1) T

35

(n

1) T

a

1, 2

1

e

b

TXD Clock High to Clock Low (N

1)

T

35

T

35

b

35

RXD Output Data Setup to TXD

l

Clock High (N 1)

1)T

1, 2

b

T

RXD Output Data Setup to TXD

e

T

ns

1

QVXH

XHQX

XHQZ

DVXH

XHDX

Clock High (N

1)

b

RXD Output Data Hold after TXD

l

Clock High (N 1)

2T

T

b

RXD Output Data Hold after TXD

e

Clock High (N

1)

a

20

RXD Output Data Float after Last

TXD Clock High

T

a

RXD Input Data Setup to TXD

Clock High

T

20

RXD Input Data Setup after TXD

Clock High

0

NOTES:

1. See Figure 13 for Waveforms.

2. n is the value in the BxCMP register ignoring the ICLK bit.

36

80C186EC/188EC, 80L186EC/188EC

AC TEST CONDITIONS

The AC specifications are tested with the 50 pF load

shown in Figure 7. See the Derating Curves section

to see how timings vary with load capacitance.

272434–6

e

C

L

50 pF for all signals

Specifications are measured at the V /2 crossing

CC

point, unless otherwise specified. See AC Timing

Waveforms for AC specification definitions, test pins

and illustrations.

Figure 7. AC Test Load

AC TIMING WAVEFORMS

272434–7

Figure 8. Input and Output Clock Waveforms

37

80C186EC/188EC, 80L186EC/188EC

272434–8

Figure 9. Output Delay and Float Waveforms

272434–9

Figure 10. Input Setup and Hold

272434–10

Figure 11. Relative Interrupt Signal Timings

38

80C186EC/188EC, 80L186EC/188EC

272434–11

Figure 12. Relative Signal Waveform

272434–12

Figure 13. Serial Port Mode 0 Waveform

39

80C186EC/188EC, 80L186EC/188EC

DERATING CURVES

272434–13

Figure 14. Typical Output Delay Variations versus Load Capacitance

272434–14

Figure 15. Typical Rise and Fall Variations versus Load Capacitance

rectly using a RC reset circuit, but the designer must

ensure that the ramp time for V is not so long that

RESET

CC

RESIN is never sampled at a logic low level when

The processor will perform a reset operation any

time the RESIN pin is active. The RESIN pin is syn-

chronized before it is presented internally, which

means that the clock must be operating before a

reset can take effect. From a power-on state, RESIN

must be held active (low) in order to guarantee cor-

rect initialization of the processor. Failure to pro-

vide RESIN while the device is powering up will

result in unspecified operation of the device.

V

CC

reaches minimum operating conditions.

Figure 17 shows the timing sequence when RESIN

is applied after V is stable and the device has

CC

been operating. Note that a reset will terminate all

activity and return the processor to a known operat-

ing state. Any bus operation that is in progress at the

time RESIN is asserted will terminate immediately

(note that most control signals will be driven to their

inactive state first before floating).

Figure 16 shows the correct reset sequence when

first applying power to the processor. An external

clock connected to CLKIN must not exceed the V

threshold being applied to the processor. This is nor-

mally not a problem if the clock driver is supplied

with the same V that supplies the processor.

When attaching a crystal to the device, RESIN must

remain active until both V and CLKOUT are stable

CC

While RESIN is active, bus signals LOCK,

A19/S16/ONCE and A18:16 are configured as in-

puts and weakly held high by internal pullup transis-

tors. Only A19/ONCE can be overdriven to a low

and is used to enable the ONCE Mode. Forcing

LOCK or A18:16 low at any time while RESIN is low

is prohibited and will cause unspecified device oper-

ation.

CC

(the length of time is application specific and de-

pends on the startup characteristics of the crystal

circuit). The RESIN pin is designed to operate cor-

40

80C186EC/188EC, 80L186EC/188EC

Figure 16. Cold RESET Waveforms

41

80C186EC/188EC, 80L186EC/188EC

Figure 17. Warm RESET Waveforms

42

80C186EC/188EC, 80L186EC/188EC

bus signals to CLKOUT. These figures along with

the information present in AC Specifications allow

the user to determine all the critical timing analysis

needed for a given application.

BUS CYCLE WAVEFORMS

Figures 18 through 24 present the various bus cy-

cles that are generated by the processor. What is

shown in the figure is the relationship of the various

272434–17

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 18. Memory Read, I/O Read, Instruction Fetch and Refresh Waveforms

43

80C186EC/188EC, 80L186EC/188EC

272434–18

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 19. Memory Write and I/O Write Cycle Waveforms

44

80C186EC/188EC, 80L186EC/188EC

272434–19

NOTES:

1. Address information is invalid. If previous bus cycle was a read, then the AD15:0 (AD7:0) lines will float during T1.

Otherwise, the AD15:0 (AD7:0) lines will continue to drive during T1 (data is invalid). All other control lines are in their

inactive state.

2. All address lines drive zeros while in Powerdown or Idle Mode.

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 20. Halt Cycle Waveforms

45

80C186EC/188EC, 80L186EC/188EC

272434–20

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 21. Interrupt Acknowledge Cycle Waveforms

46

80C186EC/188EC, 80L186EC/188EC

272434–21

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 22. HOLD/HLDA Cycle Waveforms

47

80C186EC/188EC, 80L186EC/188EC

272434–22

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 23. Refresh during HLDA Waveforms

48

80C186EC/188EC, 80L186EC/188EC

272434–23

NOTES:

1. READY must be low by either edge to cause a wait state.

2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.

Pin names in parentheses apply to 80C188EC/80L188EC.

Figure 24. READY Cycle Waveforms

49

80C186EC/188EC, 80L186EC/188EC

All instructions which involve memory accesses can

require one or two additional clocks above the mini-

mum timings shown due to the asynchronous hand-

shake between the bus interface unit (BIU) and exe-

cution unit.

80C186EC/80C188EC EXECUTION

TIMINGS

A determination of program execution timing must

consider the bus cycles necessary to prefetch in-

structions as well as the number of execution unit

cycles necessary to execute instructions. The fol-

lowing instruction timings represent the minimum

execution time in clock cycles for each instruction.

The timings given are based on the following as-

sumptions:

With a 16-bit BIU, the 80C186EC has sufficient bus

performance to ensure that an adequate number of

prefetched bytes will reside in the queue (6 bytes)

most of the time. Therefore, actual program execu-

tion time will not be substantially greater than that

derived from adding the instruction timings shown.

The opcode, along with any data or displacement

#

required for execution of a particular instruction,

has been prefetched and resides in the queue at

the time it is needed.

The 80C188EC 8-bit BIU is limited in its performance

relative to the execution unit. A sufficient number of

prefetched bytes may not reside in the prefetch

queue (4 bytes) much of the time. Therefore, actual

program execution time will be substantially greater

than that derived from adding the instruction timings

shown.

No wait states or bus HOLDs occur.

#

All word-data is located on even-address bound-

aries (80C186EC only).

#

All jumps and calls include the time required to fetch

the opcode of the next instruction at the destination

address.

50

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY

80C186EC 80C188EC

Function

Format

Comments

Clock

Cycles

DATA TRANSFER

e

MOV

Move:

Register to Register/Memory

Register/memory to register

Immediate to register/memory

Immediate to register

1 0 0 0 1 0 0 w

1 0 0 0 1 0 1 w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

mod reg r/m

mod 000 r/m

data

2/12

2/9

12/13

3/4

8

2/12*

2/9*

12/13

3/4

e

data

data if w

1

8/16-bit

e

data if w

1

Memory to accumulator

addr-low

addr-high

8*

Accumulator to memory

addr-low

9

9*

Register/memory to segment register

Segment register to register/memory

mod 0 reg r/m

2/9

2/11

2/13

2/15

e

PUSH

Push:

Memory

Register

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

0 1 1 0 1 0 s 0

mod 1 1 0 r/m

16

10

9

20

14

13

14

Segment register

Immediate

e

data

data if s

0

10

e

PUSHA

Push All

Pop:

Memory

0 1 1 0 0 0 0 0

36

68

e

POP

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

(regⁱ01)

20

10

8

24

14

12

Register

Segment register

e

POPA

Pop All

0 1 1 0 0 0 0 1

51

83

XCHG

Exchange:

Register/memory with register

Register with accumulator

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

4/17

3

4/17*

3

e

IN

Input from:

Fixed port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

port

10

8

10*

8*

Variable port

e

OUT

Output to:

Fixed port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

9

7

9*

7*

15

6

Variable port

e

XLAT

Translate byte to AL

11

6

e

LEA

LDS

LES

Load EA to register

Load pointer to DS

Load pointer to ES

mod reg r/m

(modⁱ11)

18

2

26

2

e

LAHF

SAHF

Load AH with flags

Store AH into flags

e

3

e

PUSHF

Push flags

Pop flags

9

13

12

e

POPF

8

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

51

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC 80C188EC

Function

Format

Comments

Clock

Cycles

DATA TRANSFER (Continued)

e

SEGMENT

Segment Override:

CS

0 0 1 0 1 1 1 0

0 0 1 1 0 1 1 0

0 0 1 1 1 1 1 0

0 0 1 0 0 1 1 0

2

SS

DS

ES

ARITHMETIC

e

ADD

Add:

Reg/memory with register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

data if s w 01

data

e

data if w

1

8/16-bit

e

ADC

Add with carry:

Reg/memory with register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

mod reg r/m

mod 0 1 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

data if s w 01

data

data if w

e

INC

Increment:

Register/memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

3/15

3

3/15*

3

e

SUB

Subtract:

Reg/memory and register to either

Immediate from register/memory

Immediate from accumulator

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

e

data if s w 01

data

e

data if w

1

8/16-bit

e

SBB

Subtract with borrow:

Reg/memory and register to either

Immediate from register/memory

Immediate from accumulator

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

e

data if s w 01

data

data if w

e

DEC

Decrement

Register/memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

3/15

3

3/15*

3

e

CMP

Compare:

Register/memory with register

Register with register/memory

Immediate with register/memory

Immediate with accumulator

0 0 1 1 1 0 1 w

0 0 1 1 1 0 0 w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

1 1 1 1 0 1 1 w

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

mod reg r/m

mod 1 1 1 r/m

data

3/10

3/4

3/10

8

3/10*

3/4

3/10*

8

e

data if s w 01

data

e

data if w

1

8/16-bit

e

NEG

AAA

DAA

AAS

DAS

Change sign register/memory

ASCII adjust for add

mod 0 1 1 r/m

Decimal adjust for add

4

ASCII adjust for subtract

Decimal adjust for subtract

7

4

e

MUL

Multiply (unsigned):

1 1 1 1 0 1 1 w

mod 100 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

26–28

35–37

32–34

41–43

26–28

35–37

32–34

41–43*

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

52

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC

Clock

80C188EC

Clock

Function

Format

Comments

Cycles

ARITHMETIC (Continued)

e

IMUL

Integer multiply (signed):

1 1 1 1 0 1 1 w

mod 1 0 1 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

25–28

34–37

31–34

40–43

25–28

34–37

32–34

40–43*

e

(signed)

e

0

IMUL

Integer Immediate multiply

0 1 1 0 1 0 s 1

1 1 1 1 0 1 1 w

mod reg r/m

data

data if s

22–25/

29–32

22–25/

29–32

e

DIV

Divide (unsigned):

mod 1 1 0 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

29

38

35

44

29

38

35

44*

e

IDIV

Integer divide (signed):

1 1 1 1 0 1 1 w

mod 1 1 1 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

44–52

53–61

50–58

59–67

44–52

53–61

50–58

59–67*

e

AAM

AAD

CBW

CWD

ASCII adjust for multiply

ASCII adjust for divide

Convert byte to word

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

19

15

2

19

15

2

Convert word to double word

4

LOGIC

Shift/Rotate Instructions:

Register/Memory by 1

1 1 0 1 0 0 0 w

1 1 0 1 0 0 1 w

1 1 0 0 0 0 0 w

mod TTT r/m

2/15

a

Register/Memory by CL

5

n/17

n

5

n/17

n

a

Register/Memory by Count

mod TTT r/m

count

5

n

5

n

TTT Instruction

0 0 0

0 0 1

0 1 0

0 1 1

ROL

ROR

RCL

RCR

1 0 0 SHL/SAL

1 0 1

1 1 1

SHR

SAR

e

AND

And:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 1 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

e

data

data if w

1

e

data if w

1

8/16-bit

e

TEST And function to flags, no result:

Register/memory and register

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

3/10

4/10

3/4

3/10

4/10*

3/4

Immediate data and register/memory

Immediate data and accumulator

data

e

data if w

e

OR Or:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 0 0 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

data

data if w

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

53

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC 80C188EC

Function

Format

Comments

Clock

Cycles

LOGIC (Continued)

e

XOR

Exclusive or:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

1 1 1 1 0 1 1 w

mod reg r/m

mod 1 1 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

1

data

data if w

e

data if w

1

8/16-bit

e

NOT

Invert register/memory

mod 0 1 0 r/m

3/10

3/10*

STRING MANIPULATION

e

MOVS

CMPS

SCAS

LODS

STOS

Move byte/word

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

0 1 1 0 1 1 1 w

14

22

15

12

10

14

14*

22*

15*

12*

10*

14

Compare byte/word

Scan byte/word

Load byte/wd to AL/AX

Store byte/wd from AL/AX

e

INS

Input byte/wd from DX port

e

OUTS

Output byte/wd to DX port

14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

e

a

8 8n*

MOVS

CMPS

SCAS

LODS

STOS

Move string

Compare string

Scan string

Load string

1 1 1 1 0 0 1 0

1 1 1 1 0 0 1 z

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

8

8n

a

5

6

22n

15n

11n

5

6

22n*

15n*

11n*

a

Store string

6

9n

8n

6

9n*

8n*

e

a

INS

Input string

8

e

OUTS

Output string

1 1 1 1 0 0 1 0

0 1 1 0 1 1 1 w

8n

8n*

CONTROL TRANSFER

e

CALL

Call:

Direct within segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

disp-low

disp-high

15

19

Register/memory

mod 0 1 0 r/m

13/19

17/27

indirect within segment

Direct intersegment

1 0 0 1 1 0 1 0

1 1 1 1 1 1 1 1

segment offset

segment selector

23

31

i

(mod 11)

Indirect intersegment

mod 0 1 1 r/m

38

54

e

JMP

Unconditional jump:

Short/long

1 1 1 0 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 1 1 1

disp-low

14

Direct within segment

disp-high

Register/memory

mod 1 0 0 r/m

11/17

11/21

indirect within segment

Direct intersegment

Indirect intersegment

1 1 1 0 1 0 1 0

segment offset

segment selector

14

26

14

34

i

(mod 11)

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

54

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC

Clock

80C188EC

Clock

Function

Format

Comments

Cycles

CONTROL TRANSFER (Continued)

e

RET

Return from CALL:

Within segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

16

20

Within seg adding immed to SP

Intersegment

data-low

data-high

18

22

30

Intersegment adding immediate to SP

data-low

disp

25

33

e

JE/JZ

Jump on equal/zero

4/13

5/15

6/16

4/13

5/15

6/16

JMP not

taken/JMP

taken

e

JL/JNGE

JLE/JNG

JB/JNAE

JBE/JNA

Jump on less/not greater or equal

Jump on less or equal/not greater

Jump on below/not above or equal

Jump on below or equal/not above

e

JP/JPE

Jump on parity/parity even

Jump on overflow

Jump on sign

e

JO

JS

e

JNE/JNZ

JNL/JGE

JNLE/JG

JNB/JAE

JNBE/JA

JNP/JPO

Jump on not equal/not zero

Jump on not less/greater or equal

Jump on not less or equal/greater

Jump on not below/above or equal

Jump on not below or equal/above

Jump on not par/par odd

e

JNO

JNS

Jump on not overflow

Jump on not sign

e

JCXZ

LOOP

Jump on CX zero

Loop CX times

e

LOOP not

taken/LOOP

taken

e

LOOPZ/LOOPE

LOOPNZ/LOOPNE

Loop while zero/equal

e

Loop while not zero/equal

e

ENTER

Enter Procedure

1 1 0 0 1 0 0 0

data-low

data-high

L

e

l

L

0

1

15

25

19

29

a

b

a

b

22 16(n 1) 26 20(n 1)

e

LEAVE

Leave Procedure

1 1 0 0 1 0 0 1

8

e

INT

Interrupt:

Type specified

Type 3

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

type

47

45

47

45

if INT. taken/

if INT. not

taken

e

INTO

Interrupt on overflow

48/4

e

IRET

Interrupt return

1 1 0 0 1 1 1 1

0 1 1 0 0 0 1 0

28

e

BOUND

Detect value out of range

mod reg r/m

33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

55

80C186EC/188EC, 80L186EC/188EC

INSTRUCTION SET SUMMARY (Continued)

80C186EC 80C188EC

Function

Format

Clock

Comments

Cycles

PROCESSOR CONTROL

e

CLC

CMC

STC

CLD

STD

Clear carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 1 1 0 0 0 0

2

6

2

3

2

6

2

3

Complement carry

Set carry

Clear direction

Set direction

e

CLI

STI

Clear interrupt

Set interrupt

e

HLT

Halt

e

0

WAIT

LOCK

Wait

if TEST

e

Bus lock prefix

e

NOP

No Operation

1 0 0 1 0 0 0 0

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.

The Effective Address (EA) of the memory operand

is computed according to the mod and r/m fields:

Segment Override Prefix

reg

0

1

0

e

if mod

11 then r/m is treated as a REG field

e

00 then DISP

high are absent

0*, disp-low and disp-

reg is assigned according to the following:

Segment

e

01 then DISP disp-low sign-extended

to 16-bits, disp-high is absent

if mod

reg

00

01

10

11

Register

ES

CS

e

(BX)

if mod

if r/m

10 then DISP

disp-high: disp-low

e

a

000 then EA

001 then EA

010 then EA

011 then EA

100 then EA

101 then EA

110 then EA

111 then EA

(SI)

(DI)

(SI)

(DI)

DISP

e

(BX)

(BP)

SS

DS

a

(SI)

DISP

REG is assigned according to the following table:

e

0)

a

(DI)

(BP)

(BX)

DISP

DISP*

DISP

e

16-Bit (w

1)

8-Bit (w

000 AL

a

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

DISP follows 2nd byte of instruction (before data if

required)

e

110 then EA

*except if mod

disp-high: disp-low.

00 and r/m

111 DI

EA calculation time is 4 clock cycles for all modes,

and is included in the execution times given whenev-

er appropriate.

The physical addresses of all operands addressed

by the BP register are computed using the SS seg-

ment register. The physical addresses of the desti-

nation operands of the string primitive operations

(those addressed by the DI register) are computed

using the ES segment, which may not be overridden.

56

80C186EC/188EC, 80L186EC/188EC

ERRATA

REVISION HISTORY

An 80C186EC/80L186EC with a STEPID value of

0002H has no known errata. A device with a STEPID

of 0002H can be visually identified by noting the

presence of an ‘‘A’’ or ‘‘B’’ alpha character next to

the FPO number or the absence of any alpha char-

acter. The FPO number location is shown in Figures

4, 5 and 6.

This data sheet replaces the following data sheets:

272072-003 80C186EC

272076-003 80C188EC

272332-001 80L186EC

272333-001 80L188EC

272373-001 SB80C188EC/SB80L188EC

272372-001 SB80C186EC/SB80L186EC

57


型号：	SB80L186EC25
厂家：	INTEL
描述：	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS 16位高集成嵌入式处理器
文件：	总57页 (文件大小：787K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SB80L186EC25 [INTEL]

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