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SB80L188EB13 [INTEL]

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS; 16位高集成嵌入式处理器
SB80L188EB13
型号： SB80L188EB13
厂家： INTEL    INTEL
描述：

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
16位高集成嵌入式处理器

外围集成电路 时钟
文件： 总59页 (文件大小：779K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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80C186EB/80C188EB AND 80L186EB/80L188EB  
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS  
X
True CMOS Inputs and Outputs  
Full Static Operation  
X
Y
Y
Integrated Feature Set  
Available in Extended Temperature  
b a  
Ð Low-Power Static CPU Core  
Ð Two Independent UARTs each with  
an Integral Baud Rate Generator  
Ð Two 8-Bit Multiplexed I/O Ports  
Ð Programmable Interrupt Controller  
Ð Three Programmable 16-Bit  
Timer/Counters  
Range ( 40 C to 85 C)  
§
§
Speed Versions Available (3V):  
Y
Y
Ð 16 MHz (80L186EB16/80L188EB16)  
Ð 13 MHz (80L186EB13/80L188EB13)  
Ð 8 MHz (80L186EB8/80L188EB8)  
Low-Power Operating Modes:  
Ð Idle Mode Freezes CPU Clocks but  
keeps Peripherals Active  
Ð Powerdown Mode Freezes All  
Internal Clocks  
Ð Clock Generator  
Ð Ten Programmable Chip Selects with  
Integral Wait-State Generator  
Ð Memory Refresh Control Unit  
Ð System Level Testing Support (ONCE  
Mode)  
Y
Y
Supports 80C187 Numeric Coprocessor  
Interface (80C186EB PLCC Only)  
Y
Y
Direct Addressing Capability to 1 Mbyte  
Memory and 64 Kbyte I/O  
Available In:  
Ð 80-Pin Quad Flat Pack (QFP)  
Ð 84-Pin Plastic Leaded Chip Carrier  
(PLCC)  
Speed Versions Available (5V):  
Ð 25 MHz (80C186EB25/80C188EB25)  
Ð 20 MHz (80C186EB20/80C188EB20)  
Ð 13 MHz (80C186EB13/80C188EB13)  
Ð 80-Pin Shrink Quad Flat Pack (SQFP)  
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new  
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent  
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.  
272433–1  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
October 1995  
COPYRIGHT INTEL CORPORATION, 1995  
Order Number: 272433-004  
©
1
80C186EB/80C188EB and 80L186EB/80L188EB  
16-Bit High-Integration Embedded Processors  
CONTENTS  
PAGE  
CONTENTS PAGE  
Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23  
INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4  
DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24  
CORE ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4  
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4  
Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4  
I
versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 27  
CC  
PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 27  
AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28  
AC CharacteristicsÐ80C186EB25 ÀÀÀÀÀÀÀÀÀ 28  
AC CharacteristicsÐ80C186EB20/13 ÀÀÀÀÀ 30  
AC CharacteristicsÐ80L186EB16 ÀÀÀÀÀÀÀÀÀ 32  
Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36  
Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37  
80C186EC PERIPHERAL  
ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5  
Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5  
Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5  
Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
80C187 Interface (80C186EB Only) ÀÀÀÀÀÀÀÀÀ 7  
ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7  
AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38  
AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38  
DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41  
RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42  
BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45  
EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52  
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 53  
ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59  
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59  
PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8  
Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8  
Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8  
80C186EB PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14  
PACKAGE THERMAL  
SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22  
ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 23  
Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23  
2
2
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–2  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB  
Figure 1. 80C186EB/80C188EB Block Diagram  
3
3
80C186EB/80C188EB, 80L186EB/80L188EB  
INTRODUCTION  
cept the queue status mode has been deleted and  
buffer interface control has been changed to ease  
system design timings. An independent internal bus  
is used to allow communication between the BIU  
and internal peripherals.  
Unless specifically noted, all references to the  
80C186EB apply to the 80C188EB, 80L186EB, and  
80L188EB. References to pins that differ between  
the 80C186EB/80L186EB and the 80C188EB/  
80L188EB are given in parentheses. The ‘‘L’’ in the  
part number denotes low voltage operation. Physi-  
cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are  
identical.  
CORE ARCHITECTURE  
Bus Interface Unit  
The 80C186EB is the first product in a new genera-  
tion of low-power, high-integration microprocessors.  
It enhances the existing 186 family by offering new  
features and new operating modes. The 80C186EB  
is object code compatible with the 80C186XL/  
80C188XL microprocessors.  
The 80C186EB core incorporates a bus controller  
that generates local bus control signals. In addition,  
it employs a HOLD/HLDA protocol to share the local  
bus with other bus masters.  
The bus controller is responsible for generating 20  
bits of address, read and write strobes, bus cycle  
status information, and data (for write operations) in-  
formation. It is also responsible for reading data off  
the local bus during a read operation. A READY in-  
put pin is provided to extend a bus cycle beyond the  
minimum four states (clocks).  
The 80L186EB is the 3V version of the 80C186EB.  
The 80L186EB is functionally identical to the  
80C186EB  
embedded  
processor.  
Current  
80C186EB users can easily upgrade their designs to  
use the 80L186EB and benefit from the reduced  
power consumption inherent in 3V operation.  
The local bus controller also generates two control  
signals (DEN and DT/R) when interfacing to exter-  
nal transceiver chips. (Both DEN and DT/R are  
available on the PLCC devices, only DEN is avail-  
able on the QFP and SQFP devices.) This capability  
allows the addition of transceivers for simple buffer-  
ing of the multiplexed address/data bus.  
The feature set of the 80C186EB meets the needs  
of low power, space critical applications. Low-Power  
applications benefit from the static design of the  
CPU core and the integrated peripherals as well as  
low voltage operation. Minimum current consump-  
tion is achieved by providing a Powerdown mode  
that halts operation of the device, and freezes the  
clock circuits. Peripheral design enhancements en-  
sure that non-initialized peripherals consume little  
current.  
Clock Generator  
The processor provides an on-chip clock generator  
for both internal and external clock generation. The  
clock generator features a crystal oscillator, a divide-  
by-two counter, and two low-power operating  
modes.  
Space critical applications benefit from the inte-  
gration of commonly used system peripherals. Two  
serial channels are provided for services such as  
diagnostics, inter-processor communication, modem  
interface, terminal display interface, and many oth-  
ers. A flexible chip select unit simplifies memory and  
peripheral interfacing. The interrupt unit provides  
sources for up to 129 external interrupts and will pri-  
oritize these interrupts with those generated from  
the on-chip peripherals. Three general purpose tim-  
er/counters and sixteen multiplexed I/O port pins  
round out the feature set of the 80C186EB.  
The oscillator circuit is designed to be used with ei-  
ther a parallel resonant fundamental or third-over-  
tone mode crystal network. Alternatively, the oscilla-  
tor circuit may be driven from an external clock  
source. Figure 2 shows the various operating modes  
of the oscillator circuit.  
The crystal or clock frequency chosen must be twice  
the required processor operating frequency due to  
the internal divide-by-two counter. This counter is  
used to drive all internal phase clocks and the exter-  
nal CLKOUT signal. CLKOUT is a 50% duty cycle  
processor clock and can be used to drive other sys-  
tem components. All AC timings are referenced to  
CLKOUT.  
Figure 1 shows a block diagram of the 80C186EB/  
80C188EB. The Execution Unit (EU) is an enhanced  
8086 CPU core that includes: dedicated hardware to  
speed up effective address calculations, enhance  
execution speed for multiple-bit shift and rotate in-  
structions and for multiply and divide instructions,  
string move instructions that operate at full bus  
bandwidth, ten new instruction, and fully static oper-  
ation. The Bus Interface Unit (BIU) is the same as  
that found on the original 186 family products, ex-  
4
4
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–4  
272433–3  
(A) Crystal Connection  
(B) Clock Connection  
NOTE:  
The L C network is only required when using a third-  
overtone crystal.  
1
1
Figure 2. Clock Configurations  
The following parameters are recommended when  
choosing a crystal:  
Figure 3 provides a list of the registers associated  
with the PCB. The Register Bit Summary at the end  
of this specification individually lists all of the regis-  
ters and identifies each of their programming attri-  
butes.  
Temperature Range:  
ESR (Equivalent Series Resistance):  
C0 (Shunt Capacitance of Crystal):  
Application Specific  
40X max  
7.0 pF max  
g
20 pF 2 pF  
1 mW max  
C
Drive Level:  
(Load Capacitance):  
L
Interrupt Control Unit  
The 80C186EB can receive interrupts from a num-  
ber of sources, both internal and external. The inter-  
rupt control unit serves to merge these requests on  
a priority basis, for individual service by the CPU.  
Each interrupt source can be independently masked  
by the Interrupt Control Unit (ICU) or all interrupts  
can be globally masked by the CPU.  
80C186EB PERIPHERAL  
ARCHITECTURE  
The 80C186EB has integrated several common sys-  
tem peripherals with a CPU core to create a com-  
pact, yet powerful system. The integrated peripher-  
als are designed to be flexible and provide logical  
interconnections between supporting units (e.g., the  
interrupt control unit supports interrupt requests  
from the timer/counters or serial channels).  
Internal interrupt sources include the Timers and Se-  
rial channel 0. External interrupt sources come from  
the five input pins INT4:0. The NMI interrupt pin is  
not controlled by the ICU and is passed directly to  
the CPU. Although the Timer and Serial channel  
each have only one request input to the ICU, sepa-  
rate vector types are generated to service individual  
interrupts within the Timer and Serial channel units.  
The list of integrated peripherals includes:  
7-Input Interrupt Control Unit  
#
3-Channel Timer/Counter Unit  
#
2-Channel Serial Communications Unit  
#
10-Output Chip-Select Unit  
#
#
Timer/Counter Unit  
I/O Port Unit  
The 80C186EB Timer/Counter Unit (TCU) provides  
three 16-bit programmable timers. Two of these are  
highly flexible and are connected to external pins for  
control or clocking. A third timer is not connected to  
any external pins and can only be clocked internally.  
However, it can be used to clock the other two timer  
channels. The TCU can be used to count external  
events, time external events, generate non-repeti-  
tive waveforms, generate timed interrupts. etc.  
Refresh Control Unit  
#
#
Power Management Unit  
The registers associated with each integrated peri-  
heral are contained within a 128 x 16 register file  
called the Peripheral Control Block (PCB). The PCB  
can be located in either memory or I/O space on  
any 256 Byte address boundary.  
5
5
80C186EB/80C188EB, 80L186EB/80L188EB  
PCB  
PCB  
PCB  
PCB  
Function  
Function  
Function  
Function  
Offset  
Offset  
Offset  
Offset  
00H  
02H  
04H  
06H  
08H  
0AH  
0CH  
Reserved  
End Of Interrupt  
Poll  
40H  
Timer2 Count  
80H  
82H  
84H  
86H  
88H  
8AH  
8CH  
8EH  
90H  
92H  
94H  
96H  
98H  
9AH  
9CH  
9EH  
A0H  
A2H  
A4H  
A6H  
A8H  
AAH  
ACH  
AEH  
B0H  
B2H  
B4H  
B6H  
B8H  
BAH  
BCH  
BEH  
GCS0 Start  
GCS0 Stop  
GCS1 Start  
GCS1 Stop  
GCS2 Start  
GCS2 Stop  
GCS3 Start  
GCS3 Stop  
GCS4 Start  
GCS4 Stop  
GCS5 Start  
GCS5 Stop  
GCS6 Start  
GCS6 Stop  
GCS7 Start  
GCS7 Stop  
LCS Start  
C0H  
C2H  
C4H  
C6H  
C8H  
CAH  
CCH  
CEH  
D0H  
D2H  
D4H  
D6H  
D8H  
DAH  
DCH  
DEH  
E0H  
E2H  
E4H  
E6H  
E8H  
EAH  
ECH  
EEH  
F0H  
F2H  
F4H  
F6H  
F8H  
FAH  
FCH  
FEH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
42H Timer2 Compare  
44H  
46H  
48H  
4AH  
4CH  
4EH  
50H  
52H  
54H  
56H  
58H  
5AH  
5CH  
5EH  
60H  
62H  
64H  
66H  
68H  
6AH  
6CH  
6EH  
70H  
72H  
74H  
76H  
78H  
7AH  
7CH  
7EH  
Reserved  
Timer2 Control  
Reserved  
Poll Status  
Interrupt Mask  
Priority Mask  
In-Service  
Reserved  
Reserved  
0EH Interrupt Request  
Reserved  
10H  
12H  
14H  
16H  
18H  
1AH  
1CH  
1EH  
20H  
22H  
24H  
26H  
28H  
2AH  
2CH  
2EH  
30H  
Interrupt Status  
Timer Control  
Serial Control  
INT4 Control  
INT0 Control  
INT1 Control  
INT2 Control  
INT3 Control  
Reserved  
Port 1 Direction  
Port 1 Pin  
Port 1 Control  
Port 1 Latch  
Port 2 Direction  
Port 2 Pin  
Port 2 Control  
Port 2 Latch  
Serial0 Baud  
Serial0 Count  
Serial0 Control  
Serial0 Status  
Serial0 RBUF  
Serial0 TBUF  
Reserved  
Reserved  
LCS Stop  
Reserved  
UCS Start  
Reserved  
UCS Stop  
Reserved  
Relocation  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Timer0 Count  
Serial1 Baud  
Serial1 Count  
Serial1 Control  
Serial1 Status  
Serial1 RBUF  
Serial1 TBUF  
Reserved  
Refresh Base  
Refresh Time  
Refresh Control  
Reserved  
32H Timer0 Compare A  
34H Timer0 Compare B  
36H  
38H  
Timer0 Control  
Timer1 Count  
Power Control  
Reserved  
3AH Timer1 Compare A  
3CH Timer1 Compare B  
Step ID  
3EH  
Timer1 Control  
Reserved  
Reserved  
Figure 3. Peripheral Control Block Registers  
6
6
80C186EB/80C188EB, 80L186EB/80L188EB  
A 12-bit address generator is maintained by the RCU  
and is presented on the A12:1 address lines during  
the refresh bus cycle. Address bits A19:13 are pro-  
grammable to allow the refresh address block to be  
located on any 8 Kbyte boundary.  
Serial Communications Unit  
The Serial Control Unit (SCU) of the 80C186EB con-  
tains two independent channels. Each channel is  
identical in operation except that only channel 0 is  
supported by the integrated interrupt controller  
(channel 1 has an external interrupt pin). Each  
channel has its own baud rate generator that is in-  
dependent of the Timer/Counter Unit, and can be  
internally or externally clocked at up to one half the  
80C186EB operating frequency.  
Power Management Unit  
The 80C186EB Power Management Unit (PMU) is  
provided to control the power consumption of the  
device. The PMU provides three power modes: Ac-  
tive, Idle, and Powerdown.  
Independent baud rate generators are provided for  
each of the serial channels. For the asynchronous  
modes, the generator supplies an 8x baud clock to  
both the receive and transmit register logic. A 1x  
baud clock is provided in the synchronous mode.  
Active Mode indicates that all units on the  
80C186EB are functional and the device consumes  
maximum power (depending on the level of periph-  
eral operation). Idle Mode freezes the clocks of the  
Execution and Bus units at a logic zero state (all  
peripherals continue to operate normally).  
Chip-Select Unit  
The Powerdown mode freezes all internal clocks at  
a logic zero level and disables the crystal oscillator.  
All internal registers hold their values provided V  
is maintained. Current consumption is reduced to  
just transistor junction leakage.  
The 80C186EB Chip-Select Unit (CSU) integrates  
logic which provides up to ten programmable chip-  
selects to access both memories and peripherals. In  
addition, each chip-select can be programmed to  
automatically insert additional clocks (wait-states)  
into the current bus cycle and automatically termi-  
nate a bus cycle independent of the condition of the  
READY input pin.  
CC  
80C187 Interface (80C186EB Only)  
The 80C186EB (PLCC package only) supports the  
direct connection of the 80C187 Numerics Coproc-  
essor.  
I/O Port Unit  
The I/O Port Unit (IPU) on the 80C186EB supports  
two 8-bit channels of input, output, or input/output  
operation. Port 1 is multiplexed with the chip select  
pins and is output only. Most of Port 2 is multiplexed  
with the serial channel pins. Port 2 pins are limited to  
either an output or input function depending on the  
operation of the serial pin it is multiplexed with.  
ONCE Test Mode  
To facilitate testing and inspection of devices when  
fixed into a target system, the 80C186EB has a test  
mode available which forces all output and input/  
output pins to be placed in the high-impedance  
state. ONCE stands for ‘‘ON Circuit Emulation’’. The  
ONCE mode is selected by forcing the A19/ONCE  
pin LOW (0) during a processor reset (this pin is  
weakly held to a HIGH (1) level) while RESIN is ac-  
tive.  
Refresh Control Unit  
The Refresh Control Unit (RCU) automatically gen-  
erates a periodic memory read bus cycle to keep  
dynamic or pseudo-static memory refreshed. A 9-bit  
counter controls the number of clocks between re-  
fresh requests.  
7
7
80C186EB/80C188EB, 80L186EB/80L188EB  
PACKAGE INFORMATION  
The Pin Type column contains two kinds of informa-  
tion. The first symbol indicates whether a pin is pow-  
er (P), ground (G), input only (I), output only (O) or  
input/output (I/O). Some pins have multiplexed  
functions (for example, A19/S6). Additional symbols  
indicate additional characteristics for each pin. Table  
2 lists all the possible symbols for this column.  
This section describes the pins, pinouts, and thermal  
characteristics for the 80C186EB in the Plastic  
Leaded Chip Carrier (PLCC) package, Shrink Quad  
Flat Pack (SQFP), and Quad Flat Pack (QFP) pack-  
age. For complete package specifications and infor-  
mation, see the Intel Packaging Outlines and Dimen-  
sions Guide (Order Number: 231369).  
The Input Type column indicates the type of input  
(Asynchronous or Synchronous).  
Asynchronous pins require that setup and hold times  
be met only in order to guarantee recognition at a  
particular clock edge. Synchronous pins require that  
setup and hold times be met to guarantee proper  
operation. For example, missing the setup or hold  
time for the SRDY pin (a synchronous input) will re-  
sult in a system failure or lockup. Input pins may also  
be edge- or level-sensitive. The possible character-  
istics for input pins are S(E), S(L), A(E) and A(L).  
Prefix Identification  
With the extended temperature range, operational  
characteristics are guaranteed over the temperature  
b
a
range corresponding to 40 C to 85 C ambient.  
Package types are identified by a two-letter prefix to  
§
§
the part number. The prefixes are listed in Table 1.  
Table 1. Prefix Identification  
Package  
Type  
Temperature  
Type  
The Output States column indicates the output  
state as a function of the device operating mode.  
Output states are dependent upon the current activi-  
ty of the processor. There are four operational  
states that are different from regular operation: bus  
hold, reset, Idle Mode and Powerdown Mode. Ap-  
propriate characteristics for these states are also in-  
dicated in this column, with the legend for all possi-  
ble characteristics in Table 2.  
Prefix Note  
TN  
TS  
PLCC  
Extended  
QFP (EIAJ) Extended  
SB  
N
1
1
1
SQFP  
PLCC  
Extended/Commercial  
Commercial  
S
QFP (EIAJ) Commercial  
The Pin Description column contains a text de-  
scription of each pin.  
NOTE:  
1. The 5V 25 MHz and 3V 16 MHz versions are only avail-  
able in commercial temperature range corresponding to  
a
0 C to 70 C ambient.  
As an example, consider AD15:0. I/O signifies the  
pins are bidirectional. S(L) signifies that the input  
function is synchronous and level-sensitive. H(Z)  
signifies that, as outputs, the pins are high-imped-  
ance upon acknowledgement of bus hold. R(Z) sig-  
nifies that the pins float during reset. P(X) signifies  
that the pins retain their states during Powerdown  
Mode.  
§
§
Pin Descriptions  
Each pin or logical set of pins is described in Table  
3. There are three columns for each entry in the Pin  
Description Table.  
The Pin Name column contains a mnemonic that  
describes the pin function. Negation of the signal  
name (for example, RESIN) denotes a signal that is  
active low.  
8
8
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 2. Pin Description Nomenclature  
Description  
Symbol  
a
Ground (Connect to V  
P
Power Pin (Apply  
V Voltage)  
CC  
)
SS  
G
I
Input Only Pin  
Output Only Pin  
Input/Output Pin  
O
I/O  
S(E)  
S(L)  
A(E)  
A(L)  
Synchronous, Edge Sensitive  
Synchronous, Level Sensitive  
Asynchronous, Edge Sensitive  
Asynchronous, Level Sensitive  
H(1)  
H(0)  
H(Z)  
H(Q)  
H(X)  
Output Driven to V during Bus Hold  
CC  
Output Driven to V during Bus Hold  
SS  
Output Floats during Bus Hold  
Output Remains Active during Bus Hold  
Output Retains Current State during Bus Hold  
R(WH)  
R(1)  
R(0)  
Output Weakly Held at V during Reset  
CC  
Output Driven to V during Reset  
CC  
Output Driven to V during Reset  
SS  
Output Floats during Reset  
R(Z)  
R(Q)  
R(X)  
Output Remains Active during Reset  
Output Retains Current State during Reset  
I(1)  
I(0)  
I(Z)  
I(Q)  
I(X)  
Output Driven to V during Idle Mode  
CC  
Output Driven to V during Idle Mode  
SS  
Output Floats during Idle Mode  
Output Remains Active during Idle Mode  
Output Retains Current State during Idle Mode  
P(1)  
P(0)  
P(Z)  
P(Q)  
P(X)  
Output Driven to V during Powerdown Mode  
CC  
Output Driven to V during Powerdown Mode  
SS  
Output Floats during Powerdown Mode  
Output Remains Active during Powerdown Mode  
Output Retains Current State during Powerdown Mode  
9
9
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 3. Pin Descriptions  
Output  
Pin  
Pin  
Input  
Type  
Description  
Name  
Type  
States  
V
V
P
G
I
Ð
Ð
POWER connections consist of four pins which must be  
shorted externally to a V board plane.  
CC  
CC  
Ð
Ð
Ð
GROUND connections consist of six pins which must be  
shorted externally to a V board plane.  
SS  
SS  
CLKIN  
A(E)  
CLocK INput is an input for an external clock. An external  
oscillator operating at two times the required processor  
operating frequency can be connected to CLKIN. For crystal  
operation, CLKIN (along with OSCOUT) are the crystal  
connections to an internal Pierce oscillator.  
OSCOUT  
O
Ð
H(Q)  
R(Q)  
P(Q)  
OSCillator OUTput is only used when using a crystal to  
generate the external clock. OSCOUT (along with CLKIN)  
are the crystal connections to an internal Pierce oscillator.  
This pin is not to be used as 2X clock output for non-crystal  
applications (i.e., this pin is N.C. for non-crystal applications).  
OSCOUT does not float in ONCE mode.  
CLKOUT  
RESIN  
O
I
Ð
H(Q)  
R(Q)  
P(Q)  
CLocK OUTput provides a timing reference for inputs and  
outputs of the processor, and is one-half the input clock  
(CLKIN) frequency. CLKOUT has a 50% duty cycle and  
transistions every falling edge of CLKIN.  
A(L)  
Ð
RESet IN causes the processor to immediately terminate  
any bus cycle in progress and assume an initialized state. All  
pins will be driven to a known state, and RESOUT will also  
be driven active. The rising edge (low-to-high) transition  
synchronizes CLKOUT with CLKIN before the processor  
begins fetching opcodes at memory location 0FFFF0H.  
RESOUT  
PDTMR  
O
Ð
H(0)  
R(1)  
P(0)  
RESet OUTput that indicates the processor is currently in  
the reset state. RESOUT will remain active as long as RESIN  
remains active.  
I/O  
A(L)  
H(WH)  
R(Z)  
P(1)  
Power-Down TiMeR pin (normally connected to an external  
capacitor) that determines the amount of time the processor  
waits after an exit from power down before resuming normal  
operation. The duration of time required will depend on the  
startup characteristics of the crystal oscillator.  
NMI  
I
I
A(E)  
A(E)  
Ð
Ð
Non-Maskable Interrupt input causes a TYPE-2 interrupt to  
be serviced by the CPU. NMI is latched internally.  
TEST/BUSY  
(TEST)  
TEST is used during the execution of the WAIT instruction to  
suspend CPU operation until the pin is sampled active  
(LOW). TEST is alternately known as BUSY when interfacing  
with an 80C187 numerics coprocessor (80C186EB only).  
AD15:0  
(AD7:0)  
I/O  
S(L)  
H(Z)  
R(Z)  
P(X)  
These pins provide a multiplexed Address and Data bus.  
During the address phase of the bus cycle, address bits 0  
through 15 (0 through 7 on the 80C188EB) are presented on  
the bus and can be latched using ALE. 8- or 16-bit data  
information is transferred during the data phase of the bus  
cycle.  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
10  
10  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 3. Pin Descriptions (Continued)  
Pin  
Pin  
Input Output  
Description  
Name  
Type Type States  
A18:16  
I/O  
A(L)  
H(Z)  
R(WH)  
P(X)  
These pins provide multiplexed Address during the address  
phase of the bus cycle. Address bits 16 through 19 are presented  
on these pins and can be latched using ALE. These pins are  
driven to a logic 0 during the data phase of the bus cycle. On the  
80C188EB, A15–A8 provide valid address information for the  
entire bus cycle. During a processor reset (RESIN active), A19/  
ONCE is used to enable ONCE mode. A18:16 must not be driven  
low during reset or improper operation may result.  
A19/ONCE  
(A15:A8)  
(A18:16)  
(A19/ONCE)  
S2:0  
O
Ð
H(Z)  
R(Z)  
P(1)  
Bus cycle Status are encoded on these pins to provide bus  
transaction information. S2:0 are encoded as follows:  
S2 S1 S0  
Bus Cycle Initiated  
Interrupt Acknowledge  
Read I/O  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write I/O  
Processor HALT  
Queue Instruction Fetch  
Read Memory  
Write Memory  
Passive (no bus activity)  
ALE  
O
O
Ð
Ð
H(0)  
R(0)  
P(0)  
Address Latch Enable output is used to strobe address  
information into a transparent type latch during the address phase  
of the bus cycle.  
BHE  
(RFSH)  
H(Z)  
R(Z)  
P(X)  
Byte High Enable output to indicate that the bus cycle in progress  
is transferring data over the upper half of the data bus. BHE and  
A0 have the following logical encoding  
A0  
BHE  
Encoding (for the 80C186EB/80L186EB only)  
0
0
1
1
0
1
0
1
Word Transfer  
Even Byte Transfer  
Odd Byte Transfer  
Refresh Operation  
On the 80C188EB/80L188EB, RFSH is asserted low to indicate a  
refresh bus cycle.  
RD  
O
O
Ð
Ð
H(Z)  
R(Z)  
P(1)  
ReaD output signals that the accessed memory or I/O device  
must drive data information onto the data bus.  
WR  
H(Z)  
R(Z)  
P(1)  
WRite output signals that data available on the data bus are to be  
written into the accessed memory or I/O device.  
READY  
DEN  
I
A(L)  
S(L)  
Ð
READY input to signal the completion of a bus cycle. READY  
must be active to terminate any bus cycle, unless it is ignored by  
correctly programming the Chip-Select Unit.  
O
Ð
H(Z)  
R(Z)  
P(1)  
Data ENable output to control the enable of bi-directional  
transceivers in a buffered system. DEN is active only when data is  
to be transferred on the bus.  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
11  
11  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 3. Pin Descriptions (Continued)  
Output  
Pin  
Pin  
Input  
Type  
Description  
Name  
Type  
States  
DT/R  
O
Ð
H(Z)  
R(Z)  
P(X)  
Data Transmit/Receive output controls the direction of a  
bi-directional buffer in a buffered system. DT/R is only  
available for the PLCC package.  
LOCK  
O
Ð
H(Z)  
R(WH)  
P(1)  
LOCK output indicates that the bus cycle in progress is not  
to be interrupted. The processor will not service other bus  
requests (such as HOLD) while LOCK is active. This pin is  
configured as a weakly held high input while RESIN is  
active and must not be driven low.  
HOLD  
HLDA  
I
A(L)  
Ð
Ð
HOLD request input to signal that an external bus master  
wishes to gain control of the local bus. The processor will  
relinquish control of the local bus between instruction  
boundaries not conditioned by a LOCK prefix.  
O
H(1)  
R(0)  
P(0)  
HoLD Acknowledge output to indicate that the processor  
has relinquished control of the local bus. When HLDA is  
asserted, the processor will (or has) floated its data bus  
and control signals allowing another bus master to drive the  
signals directly.  
NCS  
(N.C.)  
O
I
Ð
H(1)  
R(1)  
P(1)  
Numerics Coprocessor Select output is generated when  
accessing a numerics coprocessor. NCS is not provided on  
the QFP or SQFP packages. This signal does not exist on  
the 80C188EB/80L188EB.  
ERROR  
(N.C.)  
A(L)  
Ð
ERROR input that indicates the last numerics coprocessor  
operation resulted in an exception condition. An interrupt  
TYPE 16 is generated if ERROR is sampled active at the  
beginning of a numerics operation. ERROR is not provided  
on the QFP or SQFP packages. This signal does not exist  
on the 80C188EB/80L188EB.  
PEREQ  
(N.C.)  
I
A(L)  
Ð
Ð
CoProcessor REQuest signals that a data transfer  
between an External Numerics Coprocessor and Memory is  
pending. PEREQ is not provided on the QFP or SQFP  
packages. This signal does not exist on the 80C188EB/  
80L188EB.  
UCS  
LCS  
O
H(1)  
R(1)  
P(1)  
Upper Chip Select will go active whenever the address of  
a memory or I/O bus cycle is within the address limitations  
programmed by the user. After reset, UCS is configured to  
be active for memory accesses between 0FFC00H and  
0FFFFFH.  
O
O
Ð
Ð
H(1)  
R(1)  
P(1)  
Lower Chip Select will go active whenever the address of  
a memory bus cycle is within the address limitations  
programmed by the user. LCS is inactive after a reset.  
P1.0/GCS0  
P1.1/GCS1  
P1.2/GCS2  
P1.3/GCS3  
P1.4/GCS4  
P1.5/GCS5  
P1.6/GCS6  
P1.7/GCS7  
H(X)/H(1)  
R(1)  
P(X)/P(1)  
These pins provide a multiplexed function. If enabled, each  
pin can provide a Generic Chip Select output which will go  
active whenever the address of a memory or I/O bus cycle  
is within the address limitations programmed by the user.  
When not programmed as a Chip-Select, each pin may be  
used as a general purpose output Port. As an output port  
pin, the value of the pin can be read internally.  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
12  
12  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 3. Pin Descriptions (Continued)  
Pin  
Pin  
Input  
Type  
Output  
States  
Description  
Name  
Type  
T0OUT  
T1OUT  
O
Ð
H(Q)  
R(1)  
P(Q)  
Timer OUTput pins can be programmed to provide a  
single clock or continuous waveform generation,  
depending on the timer mode selected.  
T0IN  
T1IN  
I
I
A(L)  
A(E)  
Ð
Timer INput is used either as clock or control signals,  
depending on the timer mode selected.  
INT0  
INT1  
INT4  
A(E,L)  
Ð
Maskable INTerrupt input will cause a vector to a  
specific Type interrupt routine. To allow interrupt  
expansion, INT0 and/or INT1 can be used with  
INTA0 and INTA1 to interface with an external slave  
controller.  
INT2/INTA0  
INT3/INTA1  
I/O  
A(E,L)  
H(1)  
R(Z)  
P(1)  
These pins provide a multiplexed function. As inputs,  
they provide a maskable INTerrupt that will cause  
the CPU to vector to a specific Type interrupt routine.  
As outputs, each is programmatically controlled to  
provide an INTERRUPT ACKNOWLEDGE  
handshake signal to allow interrupt expansion.  
P2.7  
P2.6  
I/O  
I
A(L)  
A(L)  
H(X)  
R(Z)  
P(X)  
BI-DIRECTIONAL, open-drain Port pins.  
CTSO  
P2.4/CTS1  
Ð
Clear-To-Send input is used to prevent the  
transmission of serial data on their respective TXD  
signal pin. CTS1 is multiplexed with an input only port  
function.  
TXD0  
P2.1/TXD1  
O
Ð
H(X)/H(Q)  
R(1)  
P(X)/P(Q)  
Transmit Data output provides serial data  
information. TXD1 is multiplexed with an output only  
Port function. During synchronous serial  
communications, TXD will function as a clock output.  
RXD0  
P2.0/RXD1  
I/O  
A(L)  
R(Z)  
H(Q)  
P(X)  
Receive Data input accepts serial data information.  
RXD1 is multiplexed with an input only Port function.  
During synchronous serial communications, RXD is  
bi-directional and will become an output for  
transmission or data (TXD becomes the clock).  
P2.5/BCLK0  
P2.2/BCLK1  
I
A(L)/A(E)  
Ð
Baud CLocK input can be used as an alternate clock  
source for each of the integrated serial channels.  
BCLKx is multiplexed with an input only Port function,  
and cannot exceed a clock rate greater than one-half  
the operating frequency of the processor.  
P2.3/SINT1  
O
Ð
H(X)/H(Q)  
R(0)  
P(X)/P(X)  
Serial INTerrupt output will go active to indicate  
serial channel 1 requires service. SINT1 is  
multiplexed with an output only Port function.  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
13  
13  
80C186EB/80C188EB, 80L186EB/80L188EB  
80C186EB PINOUT  
Tables 6 and 7 list the 80C186EB/80C188EB pin  
names with package location for the 80-pin Quad  
Flat Pack (QFP) component. Figure 6 depicts the  
complete 80C186EB/80C188EB (QFP package) as  
viewed from the top side of the component (i.e., con-  
tacts facing down).  
Tables 4 and 5 list the 80C186EB/80C188EB pin  
names with package location for the 84-pin Plastic  
Leaded Chip Carrier (PLCC) component. Figure 5  
depicts the complete 80C186EB/80C188EB pinout  
(PLCC package) as viewed from the top side of the  
component (i.e., contacts facing down).  
Tables 8 and 9 list the 80186EB/80188EB pin  
names with package location for the 80-pin Shrink  
Quad Flat Pack (SQFP) component. Figure 7 depicts  
the complete 80C186EB/80C188EB (SQFP pack-  
age) as viewed from the top side of the component  
(i.e., contacts facing down).  
Table 4. PLCC Pin Names with Package Location  
Bus Control Processor Control  
Name Location Name Location  
ALE  
Address/Data Bus  
I/O  
Name  
AD0  
Location  
Name  
UCS  
LCS  
Location  
61  
66  
68  
70  
72  
74  
76  
78  
62  
67  
69  
71  
73  
75  
77  
79  
80  
81  
82  
83  
6
7
RESIN  
37  
38  
30  
29  
28  
27  
26  
25  
24  
21  
20  
19  
AD1  
BHE (RFSH)  
RESOUT  
AD2  
P1.0/GCS0  
P1.1/GCS1  
P1.2/GCS2  
P1.3/GCS3  
P1.4/GCS4  
P1.5/GCS5  
P1.6/GCS6  
P1.7/GCS7  
S0  
S1  
S2  
10  
9
CLKIN  
41  
40  
44  
AD3  
OSCOUT  
CLKOUT  
AD4  
8
AD5  
RD  
4
5
TEST/BUSY  
14  
AD6  
WR  
NCS (N.C.)  
60  
39  
3
AD7  
READY  
18  
PEREQ (N.C.)  
ERROR (N.C.)  
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
A16  
DEN  
11  
16  
DT/R  
PDTMR  
36  
T0OUT  
T0IN  
45  
46  
47  
48  
LOCK  
15  
NMI  
17  
31  
32  
33  
34  
35  
INT0  
HOLD  
HLDA  
13  
12  
T1OUT  
T1IN  
INT1  
INT2/INTA0  
INT3/INTA1  
INT4  
RXD0  
53  
52  
54  
51  
Power  
TXD0  
P2.5/BCLK0  
CTS0  
Name  
Location  
A17  
A18  
V
SS  
2, 22, 43  
P2.0/RXD1  
P2.1/TXD1  
P2.2/BCLK1  
P2.3/SINT1  
P2.4/CTS1  
57  
58  
59  
55  
56  
A19/ONCE  
63, 65, 84  
V
CC  
1, 23  
42, 64  
P2.6  
P2.7  
50  
49  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
14  
14  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 5. PLCC Package Locations with Pin Name  
Location  
Name  
Location  
Name  
Location  
Name  
Location  
Name  
1
2
V
V
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
V
V
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
V
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
V
V
CC  
SS  
SS  
CC  
SS  
CLKOUT  
T0OUT  
SS  
CC  
3
ERROR (N.C.)  
RD  
P1.4/GCS4  
P1.3/GCS3  
P1.2/GCS2  
P1.1/GCS1  
P1.0/GCS0  
LCS  
AD1  
4
T0IN  
AD9 (A9)  
AD2  
5
WR  
T1OUT  
6
ALE  
T1IN  
AD10 (A10)  
AD3  
7
BHE (RFSH)  
S2  
P2.7  
8
P2.6  
AD11 (A11)  
AD4  
9
S1  
UCS  
CTS0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
S0  
INT0  
TXD0  
AD12 (A12)  
AD5  
DEN  
INT1  
RXD0  
HLDA  
INT2/INTA0  
INT3/INTA1  
INT4  
P2.5/BCLK0  
P2.3/SINT1  
P2.4/CTS1  
P2.0/RXD1  
P2.1/TXD1  
P2.2/BCLK1  
NCS (N.C.)  
AD0  
AD13 (A13)  
AD6  
HOLD  
TEST/BUSY  
LOCK  
AD14 (A14)  
AD7  
PDTMR  
DT/R  
RESIN  
AD15 (A15)  
A16  
NMI  
RESOUT  
PEREQ (N.C.)  
OSCOUT  
CLKIN  
READY  
P1.7/GCS7  
P1.6/GCS6  
P1.5/GCS5  
A17  
A18  
AD8 (A8)  
A19/ONCE  
V
CC  
V
V
SS  
SS  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
15  
15  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–5  
NOTE:  
This is the FPO number location (indicated by X’s).  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram  
16  
16  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 6. QFP Pin Name with Package Location  
Bus Control Processor Control  
Name Location Name Location  
ALE RESIN  
Address/Data Bus  
I/O  
Name  
AD0  
Location  
Name  
UCS  
LCS  
Location  
10  
15  
17  
19  
21  
23  
25  
27  
11  
16  
18  
20  
22  
24  
26  
28  
29  
30  
31  
32  
38  
39  
68  
69  
71  
70  
74  
46  
67  
48  
62  
63  
64  
65  
66  
61  
60  
59  
58  
57  
56  
55  
52  
51  
50  
75  
76  
77  
78  
3
AD1  
BHE (RFSH)  
RESOUT  
CLKIN  
AD2  
P1.0/GCS0  
P1.1/GCS1  
P1.2/GCS2  
P1.3/GCS3  
P1.4/GCS4  
P1.5/GCS5  
P1.6/GCS6  
P1.7/GCS7  
T0OUT  
S0  
S1  
S2  
42  
41  
40  
AD3  
OSCOUT  
CLKOUT  
TEST  
AD4  
AD5  
RD  
36  
37  
49  
AD6  
PDTMR  
NMI  
WR  
AD7  
READY  
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
A16  
INT0  
DEN  
43  
47  
INT1  
LOCK  
INT2/INTA0  
INT3/INTA1  
INT4  
HOLD  
HLDA  
45  
44  
T0IN  
T1OUT  
T1IN  
RXD0  
Power  
TXD0  
2
Name  
Location  
P2.5/BCLK0  
CTS0  
4
V
12, 14, 33  
35, 53, 73  
13, 34  
A17  
1
SS  
A18  
P2.0/RXD1  
P2.1/TXD1  
P2.2/BCLK1  
P2.3/SINT1  
P2.4/CTS1  
7
V
CC  
A19/ONCE  
8
54, 72  
9
5
6
P2.6  
P2.7  
80  
79  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
17  
17  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 7. QFP Package Location with Pin Names  
Location  
Name  
CTS0  
Location  
Name  
Location  
Name  
Location  
Name  
UCS  
1
2
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
AD4  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
S1  
S0  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
TXD0  
AD12 (A12)  
AD5  
INT0  
3
RXD0  
DEN  
INT1  
4
P2.5/BCLK0  
P2.3/SINT1  
P2.4/CTS1  
P2.0/RXD1  
P2.1/TXD1  
P2.2/BCLK1  
AD0  
AD13 (A13)  
AD6  
HLDA  
INT2/INTA0  
INT3/INTA1  
INT4  
5
HOLD  
6
AD14 (A14)  
AD7  
TEST  
7
LOCK  
PDTMR  
RESIN  
8
AD15 (A15)  
A16  
NMI  
9
READY  
P1.7/GCS7  
P1.6/GCS6  
P1.5/GCS5  
RESOUT  
OSCOUT  
CLKIN  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A17  
AD8 (A8)  
A18  
V
V
V
A19/ONCE  
V
V
SS  
CC  
SS  
CC  
SS  
V
V
V
V
V
SS  
CC  
SS  
SS  
CC  
CLKOUT  
T0OUT  
T0IN  
AD1  
P1.4/GCS4  
P1.3/GCS3  
P1.2/GCS2  
P1.1/GCS1  
P1.0/GCS0  
LCS  
AD9 (A9)  
AD2  
RD  
WR  
T1OUT  
T1IN  
AD10 (A10)  
AD3  
ALE  
BHE (RFSH)  
S2  
P2.7  
AD11 (A11)  
P2.6  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
18  
18  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–6  
NOTE:  
This is the FPO number location (indicated by X’s).  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
Figure 5. Quad Flat Pack Pinout Diagram  
19  
19  
80C186EB/80C188EB, 80L186EB/80L188EB  
Table 8. SQFP Pin Functions with Location  
Bus Control Processor Control  
AD Bus  
I/O  
Ý
Ý
Ý
LCS  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
47  
52  
54  
56  
58  
60  
62  
64  
48  
53  
55  
57  
59  
61  
63  
65  
66  
67  
68  
69  
ALE  
BHE (RFSH  
75  
76  
79  
78  
77  
73  
74  
6
RESIN  
25  
26  
28  
27  
31  
3
UCS  
18  
17  
Ý
Ý
)
RESOUT  
CLKIN  
Ý
Ý
Ý
S0  
S1  
S2  
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
OSCOUT  
CLKOUT  
Ý
TEST /BUSY  
P1.0/GCS0  
P1.1/GCS1  
P1.2/GCS2  
P1.3/GCS3  
P1.4/GCS4  
P1.5/GCS5  
P1.6/GCS6  
P1.7/GCS7  
16  
15  
14  
13  
12  
9
Ý
RD  
Ý
WR  
READY  
NMI  
INT0  
INT1  
5
19  
20  
21  
22  
23  
24  
Ý
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
A16  
DEN  
LOCK  
80  
4
Ý
Ý
Ý
INT2/INTA0  
INT3/INTA1  
INT4  
8
HOLD  
HLDA  
2
7
1
PDTMR  
P2.0/RXD1  
P2.1/TXD1  
44  
45  
46  
42  
43  
41  
37  
36  
P2.2/BCLK1  
P2.3/SINT1  
Power and Ground  
Ý
V
V
V
V
V
V
V
V
V
V
11  
P2.4/CTS1  
P2.5/BCLK0  
P2.6  
CC  
CC  
CC  
CC  
SS  
SS  
SS  
SS  
SS  
SS  
29  
50  
71  
10  
30  
49  
51  
70  
72  
A17  
A18  
A19/ONCE  
P2.7  
Ý
CTS0  
38  
39  
40  
TXD0  
RXD0  
T0IN  
T1IN  
33  
35  
32  
34  
T0OUT  
T1OUT  
Table 9. SQFP Pin Locations with Pin Names  
Ý
Ý
1
2
3
4
5
6
7
8
9
HLDA  
HOLD  
21 INT1/INTA0  
22 INT3/INTA1  
23 INT4  
41 P2.5/BCLK0  
42 P2.3/SINT1  
61 AD13 (A13)  
62 AD6  
63 AD14 (A14)  
64 AD7  
65 AD15 (A15)  
66 A16  
67 A17  
68 A18  
69 A19/ONCE  
Ý
Ý
TEST  
LOCK  
NMI  
43 P2.4/CTS1  
44 P2.0/RXD1  
45 P2.1/TXD1  
46 P2.2/BCLK1  
47 AD0  
Ý
24 PDTMR  
25 RESIN  
Ý
READY  
26 RESOUT  
27 OSCOUT  
28 CLKIN  
Ý
Ý
Ý
P1.7/GCS7  
P1.6/GCS6  
P1.5/GCS5  
48 AD8 (A8)  
29  
30  
V
V
49  
50  
51  
V
V
V
CC  
SS  
CC  
SS  
10  
11  
V
V
70  
71  
72  
V
V
V
SS  
CC  
SS  
SS  
CC  
SS  
31 CLKOUT  
32 T0OUT  
33 T0IN  
34 T1OUT  
35 T1IN  
36 P2.7  
Ý
Ý
Ý
Ý
Ý
12 P1.4/GCS4  
13 P1.3/GCS3  
14 P1.2/GCS2  
15 P1.1/GCS1  
16 P1.0/GCS0  
52 AD1  
53 AD9 (A9)  
54 AD2  
55 AD10 (A10)  
56 AD3  
Ý
73 RD  
Ý
74 WR  
75 ALE  
76 BHE (RFSH  
Ý
Ý
)
Ý
Ý
Ý
Ý
Ý
17 LCS  
18 UCS  
37 P2.6  
57 AD11 (A11)  
58 AD4  
59 AD12 (A12)  
60 AD5  
77 S2  
78 S1  
79 S0  
Ý
38 CTS0  
39 TXD0  
40 RXD0  
19 INT0  
20 INT1  
Ý
80 DEN  
NOTE:  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
20  
20  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–7  
NOTE:  
XXXXXXXXC indicates Intel FPO number.  
Pin names in parentheses apply to the 80C188EB/80L188EB.  
Figure 6. SQFP Package  
21  
21  
80C186EB/80C188EB, 80L186EB/80L188EB  
T
(the ambient temperature) can be calculated  
A
PACKAGE THERMAL  
SPECIFICATIONS  
from i (thermal resistance from the case to ambi-  
CA  
ent) with the following equation:  
The 80C186EB/80L186EB is specified for operation  
when T (the case temperature) is within the range  
e
b
P*i  
T
A
T
C
CA  
C
b
a
b
of 40 C to 100 C (PLCC package) or 40 C to  
114 C (QFP package). T may be measured in  
§
§
§
Typical values for i  
at various airflows are given  
CA  
a
§
C
in Table 10. P (the maximum power consumption,  
specified in watts) is calculated by using the maxi-  
mum ICC as tabulated in the DC specifications and  
any environment to determine whether the proces-  
sor is within the specified operating range. The case  
temperature must be measured at the center of the  
top surface.  
V
CC  
of 5.5V.  
Table 10. Thermal Resistance (i ) at Various Airflows (in C/Watt)  
§
CA  
Airflow Linear ft/min (m/sec)  
0
200  
400  
600  
800 1000  
(0) (1.01) (2.03) (3.04) (4.06) (5.07)  
i
i
i
(PLCC)  
(QFP)  
30 24  
58 47  
21  
43  
19  
40  
17  
38  
16.5  
36  
CA  
CA  
CA  
(SQFP)  
70 TBD TBD TBD TBD TBD  
22  
22  
80C186EB/80C188EB, 80L186EB/80L188EB  
ELECTRICAL SPECIFICATIONS  
Absolute Maximum Ratings  
NOTICE: This data sheet contains preliminary infor-  
mation on new products in production. It is valid for  
the devices indicated in the revision history. The  
specifications are subject to change without notice.  
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
§
§
b
a
Case Temp under Bias ÀÀÀÀÀÀÀÀÀ 65 C to 120 C  
§
§
Supply Voltage  
b
a
a
with Respect to V ÀÀÀÀÀÀÀÀÀÀÀ 0.5V to  
SS  
6.5V  
0.5V  
Voltage on other Pins  
with Respect to V  
b
ÀÀÀÀÀÀ 0.5V to V  
CC  
SS  
Low inductance capacitors and interconnects are  
recommended for best high frequency electrical per-  
formance. Inductance is reduced by placing the de-  
coupling capacitors as close as possible to the proc-  
Recommended Connections  
Power and ground connections must be made to  
multiple V and V pins. Every 80C186EB-based  
CC SS  
circuit board should include separate power (V  
essor V  
and V package pins.  
SS  
)
CC  
pin must be  
CC  
and ground (V ) planes. Every V  
SS  
CC  
Always connect any unused input to an appropriate  
signal level. In particular, unused interrupt inputs  
(INT0:4) should be connected to V through a pull-  
up resistor (in the range of 50 KX). Leave any un-  
used output pin or any NC pin unconnected.  
connected to the power plane, and every V  
pin  
SS  
must be connected to the ground plane. Pins identi-  
fied as ‘‘NC’’ must not be connected in the system.  
Liberal decoupling capacitance should be placed  
near the processor. The processor can cause tran-  
sient power surges when its output buffers tran-  
sition, particularly when connected to large capaci-  
tive loads.  
CC  
23  
23  
80C186EB/80C188EB, 80L186EB/80L188EB  
DC SPECIFICATIONS (80C186EB/80C188EB)  
Symbol  
Parameter  
Supply Voltage  
Min  
Max  
Units  
V
Notes  
V
V
V
V
V
V
4.5  
5.5  
CC  
b
Input Low Voltage  
0.5  
0.3 V  
V
IL  
CC  
a
V
CC  
Input High Voltage  
0.7 V  
0.5  
V
IH  
CC  
e
Output Low Voltage  
Output High Voltage  
Input Hysterisis on RESIN  
0.45  
V
I
I
3 mA (Min)  
OL  
OH  
HYR  
OL  
b
e b  
2 mA (MIn)  
V
0.5  
V
CC  
OH  
0.50  
V
s
s
g
I
Input Leakage Current for Pins:  
AD15:0 (AD7:0), READY, HOLD,  
RESIN, CLKIN, TEST, NMI, INT4:0,  
T0IN, T1IN, RXD0, BCLK0, CTS0,  
RXD1, BCLK1, CTS1, P2.6, P2.7  
15  
mA  
0V  
0V  
V
V
V
V
LI1  
IN  
IN  
CC  
CC  
s
k
g
g
7
I
I
I
I
Input Leakage Current for Pins:  
ERROR, PEREQ  
0.275  
0.275  
mA  
mA  
mA  
LI2  
LI3  
LO  
CC  
b
b
e
0.7 V (Note 1)  
IN CC  
Input Leakage Current for Pins:  
A19/ONCE, A18:16, LOCK  
5.0  
V
s
s
g
Output Leakage Current  
15  
0.45  
V
OUT  
(Note 2)  
V
CC  
Supply Current Cold (RESET)  
80C186EB25  
115  
108  
73  
mA  
mA  
mA  
(Notes 3, 7)  
(Note 3)  
80C186EB20  
80C186EB13  
(Note 3)  
I
I
Supply Current Idle  
80C186EB25  
ID  
91  
76  
48  
mA  
mA  
mA  
(Notes 4, 7)  
(Note 4)  
80C186EB20  
80C186EB13  
(Note 4)  
Supply Current Powerdown  
80C186EB25  
PD  
100  
100  
100  
15  
mA  
mA  
mA  
pF  
pF  
(Notes 5, 7)  
(Note 5)  
80C186EB20  
80C186EB13  
(Note 5)  
e
e
C
C
Input Pin Capacitance  
Output Pin Capacitance  
0
0
T
T
1 MHz  
1 MHz (Note 6)  
IN  
F
F
15  
OUT  
NOTES:  
1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more  
current than specified (on any of these pins) may invoke a factory test mode.  
2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.  
3. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as  
CC  
or GND.  
specified in AC Test Conditions, and all floating outputs driven to V  
4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL  
CC  
CC  
or GND.  
5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with  
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
CC  
CC  
or GND.  
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
6. Output Capacitance is the capacitive load of a floating output pin.  
CC  
e
g
5.0 10%.  
7. Operating temperature for 25 MHz is 0 C to 70 C, V  
§
§
CC  
24  
24  
80C186EB/80C188EB, 80L186EB/80L188EB  
DC SPECIFICATIONS (80L186EB16) (operating temperature, 0 C to 70 C)  
§
Units  
§
Symbol  
Parameter  
Supply Voltage  
Min  
Max  
Notes  
V
V
V
V
V
V
3.0  
5.5  
V
V
V
V
V
V
CC  
b
Input Low Voltage  
0.5  
0.3 V  
CC  
IL  
a
0.5  
Input High Voltage  
0.7 V  
V
CC  
IH  
CC  
e
OL  
Output Low Voltage  
Output High Voltage  
Input Hysterisis on RESIN  
0.45  
I
I
1.6 mA (Min) (Note 1)  
OL  
OH  
HYR  
b
e b  
1 mA (Min) (Note 1)  
V
0.5  
CC  
OH  
0.50  
s
s
g
I
Input Leakage Current for pins:  
AD15:0 (AD7:0), READY, HOLD,  
RESIN, CLKIN, TEST, NMI,  
INT4:0, T0IN, T1IN, RXD0,  
BCLK0, CTS0, RXD1, BCLK1,  
CTS1, SINT1, P2.6, P2.7  
15  
mA 0V  
V
V
CC  
LI1  
IN  
b
b
e
0.7 V (Note 2)  
IN CC  
I
Input Leakage Current for Pins:  
A19/ONCE, A18:16, LOCK  
0.275  
2
mA  
V
LI2  
s
s
g
I
I
Output Leakage Current  
15  
mA 0.45  
V
V
(Note 3)  
CC  
LO  
OUT  
Supply Current (RESET, 3.3V)  
80L186EB16  
CC3  
54  
mA (Note 4)  
mA (Note 5)  
mA (Note 6)  
I
I
Supply Current Idle (3.3V)  
80L186EB16  
ID3  
38  
Supply Current Powerdown (3.3V)  
80L186EB16  
PD3  
40  
15  
15  
e
e
C
C
Input Pin Capacitance  
Output Pin Capacitance  
0
0
pF  
pF  
T
T
1 MHz  
IN  
F
F
1 MHz (Note 7)  
OUT  
NOTES:  
1. I and I  
e
measured at V  
CC  
3.0V.  
OL  
OH  
2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more  
current than specified (on any of these pins) may invoke a factory test mode.  
3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.  
4. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as  
CC  
or GND.  
specified in AC Test Conditions, and all floating outputs driven to V  
5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL  
CC  
CC  
or GND.  
6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with  
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
CC  
CC  
or GND.  
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
7. Output Capacitance is the capacitive load of a floating output pin.  
CC  
25  
25  
80C186EB/80C188EB, 80L186EB/80L188EB  
DC SPECIFICATIONS (80L186EB13/80L188EB13, 80L186EB8/80L188EB8)  
Symbol  
Parameter  
Supply Voltage  
Min  
Max  
Units  
Notes  
V
V
V
V
V
V
2.7  
5.5  
V
V
V
V
V
V
CC  
b
Input Low Voltage  
0.5  
0.3 V  
CC  
IL  
a
0.5  
Input High Voltage  
0.7 V  
V
CC  
IH  
CC  
e
Output Low Voltage  
Output High Voltage  
Input Hysterisis on RESIN  
0.45  
I
I
1.6 mA (Min) (Note 1)  
OL  
OH  
HYR  
OL  
b
e b  
1 mA (Min) (Note 1)  
V
0.5  
CC  
OH  
0.50  
s
s
g
I
Input Leakage Current for pins:  
AD15:0 (AD7:0), READY, HOLD,  
RESIN, CLKIN, TEST, NMI,  
INT4:0, T0IN, T1IN, RXD0,  
BCLK0, CTS0, RXD1, BCLK1,  
CTS1, SINT1, P2.6, P2.7  
15  
mA 0V  
V
V
CC  
LI1  
IN  
b
b
e
0.7 V (Note 2)  
IN CC  
I
Input Leakage Current for Pins:  
A19/ONCE, A18:16, LOCK  
0.275  
2
mA  
V
LI2  
s
s
g
I
I
Output Leakage Current  
15  
mA 0.45  
V
V
(Note 3)  
CC  
LO  
OUT  
Supply Current (RESET, 5.5V)  
80L186EB13  
80L186EB8  
CC5  
73  
45  
mA (Note 4)  
mA (Note 4)  
I
I
I
I
I
Supply Current (RESET, 2.7V)  
80L186EB13  
80L186EB8  
CC3  
ID5  
36  
22  
mA (Note 4)  
mA (Note 4)  
Supply Current Idle (5.5V)  
80L186EB13  
80L186EB8  
48  
31  
mA (Note 5)  
mA (Note 5)  
Supply Current Idle (2.7V)  
80L186EB13  
80L186EB8  
ID3  
24  
15  
mA (Note 5)  
mA (Note 5)  
Supply Current Powerdown (5.5V)  
80L186EB13  
80L186EB8  
PD5  
PD3  
100  
100  
mA (Note 6)  
mA (Note 6)  
Supply Current Powerdown (2.7V)  
80L186EB13  
80L186EB8  
30  
30  
mA (Note 6)  
mA (Note 6)  
e
e
C
C
Input Pin Capacitance  
Output Pin Capacitance  
0
0
15  
15  
pF  
pF  
T
T
1 MHz  
IN  
F
F
1 MHz (Note 7)  
OUT  
NOTES:  
1. I and I  
e
measured at V  
CC  
2.7V.  
OL  
OH  
2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more  
current than specified (on any of these pins) may invoke a factory test mode.  
3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.  
4. Measured with the device in RESET and at worst case frequency, V , and temperature with ALL outputs loaded as  
CC  
or GND.  
specified in AC Test Conditions, and all floating outputs driven to V  
5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, V , and temperature with ALL  
CC  
CC  
or GND.  
6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, V , and temperature with  
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
CC  
CC  
or GND.  
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to V  
7. Output Capacitance is the capacitive load of a floating output pin.  
CC  
26  
26  
80C186EB/80C188EB, 80L186EB/80L188EB  
PDTMR PIN DELAY CALCULATION  
I
CC  
VERSUS FREQUENCY AND VOLTAGE  
The current (I ) consumption of the processor is  
and  
The PDTMR pin provides a delay between the as-  
sertion of NMI and the enabling of the internal  
clocks when exiting Powerdown. A delay is required  
only when using the on-chip oscillator to allow the  
crystal or resonator circuit time to stabilize.  
CC  
essentially composed of two components; I  
PD  
I
.
CCS  
I
is the quiescent current that represents internal  
PD  
device leakage, and is measured with all inputs or  
floating outputs at GND or V (no clock applied to  
the device). I  
NOTE:  
CC  
is equal to the Powerdown current  
The PDTMR pin function does not apply when  
RESIN is asserted (i.e., a device reset during Pow-  
erdown is similar to a cold reset and RESIN must  
remain active until after the oscillator has stabi-  
lized).  
PD  
and is typically less than 50 mA.  
I
is the switching current used to charge and  
CCS  
discharge parasitic device capacitance when chang-  
ing logic levels. Since I is typically much greater  
than I , I can often be ignored when calculating  
CCS  
To calculate the value of capacitor required to pro-  
vide a desired delay, use the equation:  
PD PD  
I
.
CC  
c
e
C
440  
t
(5V, 25 C)  
§
desired delay in seconds  
I
is related to the voltage and frequency at which  
the device is operating. It is given by the formula:  
PD  
CCS  
e
Where: t  
2
e
c
e
c
c
Power  
.
V
I
V
C
f
e
DEV  
C
PD  
capacitive load on PDTMR in mi-  
crofarads  
e
e
e
c
c
. . I  
I
I
V
C
f
CC  
CCS  
DEV  
e
Where: V  
Device operating voltage (V  
)
CC  
EXAMPLE: To get a delay of 30b0 ms, a capacitor  
e
C
Device capacitance  
Device operating frequency  
6
e
c
c
required. Round up to standard (available) capaci-  
e
) 0.132 mF is  
DEV  
value of C  
440  
(300  
10  
PD  
e
f
tive values.  
e
e
I
I
Device current  
CCS  
CC  
NOTE:  
Measuring C  
would be difficult. Instead, C  
on a device like the 80C186EB  
DEV  
is calculated using  
the above formula by measuring I at a known V  
The above equation applies to delay times greater  
than 10 ms and will compute the TYPICAL capaci-  
tance needed to achieve the desired delay. A delay  
DEV  
CC  
and frequency (see Table 11). Using this C  
ue, I can be calculated at any voltage and fre-  
CC  
quency within the specified operating range.  
CC  
val-  
DEV  
a
b
variance of  
temperature, voltage, and device process ex-  
tremes. In general, higher V and/or lower tem-  
50% or  
25% can occur due to  
CC  
perature will decrease delay time, while lower V  
CC  
and/or higher temperature will increase delay time.  
EXAMPLE: Calculate the typical I when operating  
CC  
at 10 MHz, 4.8V.  
e
e
CCS  
c
c
&
28 mA  
I
I
4.8  
0.583  
10  
CC  
Table 11. Device Capacitance (C  
) Values  
Units  
DEV  
Parameter  
Typ  
Max  
1.02  
Notes  
C
C
(Device in Reset)  
(Device in Idle)  
0.583  
0.408  
mA/V*MHz  
mA/V*MHz  
1, 2  
DEV  
0.682  
1, 2  
DEV  
b
1. Max C  
DEV  
is calculated at 40 C, all floating outputs driven to V  
§
or GND, and all  
CC  
outputs loaded to 50 pF (including CLKOUT and OSCOUT).  
2. Typical C is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and  
§
DEV  
OSCOUT, which are not loaded.  
27  
27  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EB25  
25 MHz  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
INPUT CLOCK  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
0
20  
8
50  
%
%
%
MHz  
ns  
1
F
1
C
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
ns  
ns  
1, 2  
1, 2  
1, 3  
1, 3  
CH  
CL  
CR  
CF  
8
1
7
ns  
ns  
1
7
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
0
16  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
CD  
2*T  
C
b
b
a
a
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
1
PH  
PL  
PR  
PF  
1
1
6
1, 5  
1, 5  
1
6
OUTPUT DELAYS  
T
T
T
ALE, S2:0, DEN, DT/R, BHE (RFSH), LOCK, A19:16  
GCS0:7, LCS, UCS, NCS, RD, WR  
3
3
3
17  
20  
17  
ns  
ns  
ns  
1, 4, 6, 7  
1, 4, 6, 8  
1, 4, 6  
CHOV1  
CHOV2  
CLOV1  
BHE (RFSH), DEN, LOCK, RESOUT, HLDA, T0OUT,  
T1OUT, A19:16  
T
RD, WR, GCS7:0, LCS, UCS, AD15:0 (AD7:0, A15:8),  
NCS, INTA1:0, S2:0  
3
20  
ns  
1, 4, 6  
CLOV2  
T
T
RD, WR, BHE (RFSH), DT/R, LOCK, S2:0, A19:16  
DEN, AD15:0 (AD7:0, A15:8)  
0
0
20  
20  
ns  
ns  
1
1
CHOF  
CLOF  
28  
28  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EB25 (Continued)  
25 MHz  
Units Notes  
Min Max  
Symbol  
Parameter  
SYNCHRONOUS INPUTS  
T
CHIS  
T
CHIH  
T
CLIS  
T
CLIH  
T
CLIS  
T
CLIH  
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0, P2.6, P2.7  
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0  
AD15:0 (AD7:0), READY  
10  
3
ns  
ns  
ns  
ns  
ns  
ns  
1, 9  
1, 9  
10  
3
1, 10  
1, 10  
1, 9  
READY, AD15:0 (AD7:0)  
HOLD, PEREQ, ERROR  
10  
3
HOLD, PEREQ, ERROR  
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measure at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
C
and T  
.
CL  
CC  
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
29  
29  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EB20/80C186EB13  
20 MHz  
13 MHz  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
Min  
Max  
INPUT CLOCK  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
0
25  
10  
10  
1
40  
%
%
%
0
38.5  
12  
12  
1
26  
%
%
%
MHz  
ns  
1
F
1
C
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
ns  
ns  
1, 2  
1, 2  
1, 3  
1, 3  
CH  
CL  
CR  
CF  
8
8
ns  
ns  
1
8
1
8
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
0
17  
0
23  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
CD  
2*T  
2*T  
C
C
b
b
a
a
b
b
a
a
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
1
PH  
PL  
PR  
PF  
1
1
6
1
6
1, 5  
1, 5  
1
6
1
6
OUTPUT DELAYS  
T
ALE, S2:0, DEN, DT/R,  
BHE (RFSH), LOCK,  
A19:16  
3
22  
3
25  
ns  
1, 4, 6, 7  
CHOV1  
T
T
GCS0:7, LCS, UCS, NCS,  
RD, WR  
3
3
27  
22  
3
3
30  
25  
ns  
ns  
1, 4, 6, 8  
1, 4, 6  
CHOV2  
BHE (RFSH), DEN, LOCK,  
RESOUT, HLDA, T0OUT,  
T1OUT, A19:16  
CLOV1  
T
RD, WR, GCS7:0, LCS,  
UCS, AD15:0 (AD7:0,  
A15:8), NCS, INTA1:0, S2:0  
3
27  
3
30  
ns  
1, 4, 6  
CLOV2  
T
T
RD, WR, BHE (RFSH),  
DT/R, LOCK, S2:0, A19:16  
0
0
25  
25  
0
0
25  
25  
ns  
ns  
1
1
CHOF  
DEN, AD15:0 (AD7:0,  
A15:8)  
CLOF  
30  
30  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EB20/80C186EB13 (Continued)  
20 MHz  
13 MHz  
Min Max  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
SYNCHRONOUS INPUTS  
T
TEST, NMI, INT4:0, BCLK1:0, T1:0IN,  
READY, CTS1:0, P2.6, P2.7  
10  
3
10  
3
ns  
ns  
1, 9  
1, 9  
CHIS  
T
TEST, NMI, INT4:0, BCLK1:0, T1:0IN,  
READY, CTS1:0  
CHIH  
T
T
T
T
AD15:0 (AD7:0), READY  
READY, AD15:0 (AD7:0)  
HOLD, PEREQ, ERROR  
HOLD, PEREQ, ERROR  
10  
3
10  
3
ns  
ns  
ns  
ns  
1, 10  
1, 10  
1, 9  
CLIS  
CLIH  
CLIS  
CLIH  
10  
3
10  
3
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measure at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
C
and T  
.
CL  
CC  
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
31  
31  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EB16  
16 MHz  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
INPUT CLOCK  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
0
32  
%
%
%
MHz  
ns  
1
F
31.25  
13  
13  
1
1
C
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
ns  
ns  
1, 2  
1, 2  
1, 3  
1, 3  
CH  
CL  
CR  
CF  
8
ns  
ns  
1
8
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
0
30  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
CD  
2*T  
C
b
b
a
a
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
1
PH  
PL  
PR  
PF  
1
1
9
1, 5  
1, 5  
1
9
OUTPUT DELAYS  
T
T
T
T
T
T
T
DT/R, LOCK, A19:16, R  
3
3
3
3
3
3
3
22  
27  
25  
30  
33  
22  
27  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4, 6, 7  
1, 4, 6, 8  
1, 4  
CHOV1  
CHOV2  
CHOV3  
CHOV4  
CHOV5  
CLOV1  
CLOV2  
FSH  
GCS0:7, LCS, UCS, NCS, RD, WR  
BHE, DEN  
ALE  
1, 4  
S2:0  
1, 4  
LOCK, RESOUT, HLDA, T0OUT, T1OUT, A19:16  
1, 4, 6  
1, 4, 6  
RD, WR, GCS7:0, LCS, UCS, NCS, INTA1:0, AD15:0  
(AD7:0, A15:8)  
T
T
T
T
RD, WR, BHE (RFSH), DT/R, LOCK, S2:0, A19:16  
0
0
3
3
25  
25  
25  
33  
ns  
ns  
ns  
ns  
1
CHOF  
DEN, AD15:0 (AD7:0, A15:8)  
1
CLOF  
BHE, DEN  
S2:0  
1, 4, 6  
1, 4, 6  
CLOV3  
CLOV5  
32  
32  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EB16 (Continued)  
16 MHz  
Units Notes  
Min Max  
Symbol  
Parameter  
SYNCHRONOUS INPUTS  
T
CHIS  
T
CHIH  
T
CLIS  
T
CLIH  
T
CLIS  
T
CLIH  
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0, P2.6, P2.7  
15  
3
ns  
ns  
ns  
ns  
ns  
ns  
1, 9  
1, 9  
TEST, NMI, INT4:0, T1:0IN, BCLK1:0, READY, CTS1:0  
AD15:0 (AD7:0), READY  
READY, AD15:0 (AD7:0)  
HOLD  
15  
3
1, 10  
1, 10  
1, 9  
15  
3
HOLD  
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measure at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
C
and T  
.
CL  
CC  
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
33  
33  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EB13/80L186EB8  
13 MHz  
8 MHz  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
Min  
Max  
INPUT CLOCK  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
0
38.5  
15  
15  
1
26  
%
%
%
8
8
0
62.5  
15  
15  
1
16  
%
%
%
8
8
MHz  
ns  
ns  
ns  
ns  
ns  
1
1
1, 2  
1, 2  
1, 3  
1, 3  
r
C
CH  
CL  
CR  
CF  
1
1
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
0
10  
0
50  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
1
1
1, 5  
1, 5  
CD  
2*T  
(T/2)  
(T/2)  
2*T  
(T/2)  
(T/2)  
C
C
b
b
a
a
b
b
a
a
(T/2)  
(T/2)  
5
5
5
5
(T/2)  
(T/2)  
5
5
5
5
PH  
PL  
PR  
PF  
1
1
10  
10  
1
1
15  
15  
OUTPUT DELAYS  
T
ALE, S2-0, DEN, DT/R,  
BHE (RFSH), LOCK,  
A19:16  
3
25  
3
30  
ns  
1, 4, 6, 7  
CHOV1  
T
T
GCS0:7, LCS, UCS,  
NCS, RD, WR  
3
3
30  
25  
3
3
35  
30  
ns  
ns  
1, 4,6, 8  
1, 4, 6  
CHOV2  
CLOV1  
BHE (RFSH), DEN,  
LOCK, RESOUT, HLDA,  
T0OUT, T1OUT, A19:16  
T
S2:0, RD, WR, GCS7:0,  
LCS, UCS, NCS,  
INTA1:0, AD15:0 (AD7:0,  
A15:8)  
3
30  
3
35  
ns  
1, 4, 6  
CLOV2  
T
T
RD, WR, BHE (RFSH),  
DT/R, LOCK, S2:0,  
A19:16  
0
0
30  
30  
0
0
30  
35  
ns  
ns  
1
1
CHOF  
CLOF  
DEN, AD15:0  
(AD7:0, A15:8)  
34  
34  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EB13/80L186EB8 (Continued)  
13 MHz  
8 MHz  
Max  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
Min  
SYNCHRONOUS INPUTS  
T
T
TEST, NMI, INT4:0,  
BCLK1:0, T1:0IN, READY  
CTS1:0, P2.6, P2.7  
20  
25  
ns  
ns  
1, 9  
1, 9  
CHIS  
CHIH  
TEST, NMI, INT4:0, T1:0IN,  
BCLK1:0, READY, CTS1:0  
3
3
T
T
T
T
AD15:0 (AD7:0), READY  
READY, AD15:0 (AD7:0)  
HOLD  
20  
3
25  
3
ns  
ns  
ns  
ns  
1, 10  
1, 10  
1, 9  
CLIS  
CLIH  
CLIS  
CLIH  
20  
3
25  
3
HOLD  
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measured at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
C
and T  
.
CL  
CC  
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
35  
35  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS (Continued)  
Relative Timings (80C186EB25, 20, 13/80L186EB16, 13, 8)  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
RELATIVE TIMINGS  
b
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ALE Rising to ALE Falling  
T
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
b
(/2T 10  
Address Valid to ALE Falling  
Chip Selects Valid to ALE Falling  
Address Hold from ALE Falling  
ALE Falling to WR Falling  
AVLL  
b
(/2T 10  
1
PLLL  
b
(/2T 10  
LLAX  
b
(/2T 15  
1
1
1
LLWL  
LLRL  
b
(/2T 15  
ALE Falling to RD Falling  
b
WR Rising to ALE Rising  
(/2T  
10  
WHLH  
AFRL  
RLRH  
WLWH  
RHAV  
WHDX  
WHPH  
RHPH  
PHPL  
OVRH  
RHOX  
Address Float to RD Falling  
RD Falling to RD Rising  
0
b
(2*T)  
(2*T)  
5
5
2
2
b
WR Falling to WR Rising  
b
b
RD Rising to Address Active  
Output Data Hold after WR Rising  
WR Rising to Chip Select Rising  
RD Rising to Chip Select Rising  
CS Inactive to CS Active  
T
T
15  
15  
b
(/2T  
10  
1
1
1
3
3
b
(/2T 10  
b
T
(/2T  
10  
ONCE Active to RESIN Rising  
ONCE Hold from RESIN Rising  
T
NOTES:  
1. Assumes equal loading on both pins.  
2. Can be extended using wait states.  
3. Not tested  
36  
36  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC SPECIFICATIONS (Continued)  
Serial Port Mode 0 Timings (80C186EB25, 20, 13/80L186EB16, 13, 8)  
Symbol Parameter Min  
Max  
Unit Notes  
a
T
T
T
T
T
T
T
T
T
T
T
T
TXD Clock Period  
TXD Clock Low to Clock High (n 1)  
T (n  
1)  
ns  
ns  
1, 2  
1
XLXL  
l
b
a
2T  
T
35  
35  
2T  
T
35  
35  
XLXH  
XLXH  
XHXL  
XHXL  
QVXH  
QVXH  
XHQX  
XHQX  
XHQZ  
DVXH  
XHDX  
e
l
b
a
TXD Clock Low to Clock High (n  
1)  
ns  
1
b
b
b
35 (n 1) T  
a
TXD Clock High to Clock Low (n 1)  
(n  
1) T  
35 ns  
35 ns  
1, 2  
1
e
b
a
a
TXD Clock High to Clock Low (n  
1)  
T
35  
T
l
RXD Output Data Setup to TXD Clock High (n 1) (n  
b
b
35  
1) T  
ns  
1, 2  
1
e
b
35  
RXD Output Data Setup to TXD Clock High (n  
1)  
T
ns  
l
RXD Output Data Hold after TXD Clock High (n 1)  
b
2T 35  
ns  
1
e
b
RXD Output Data Hold after TXD Clock High (n  
1)  
T
35  
20  
ns  
1
RXD Output Data Float after Last TXD Clock High  
RXD Input Data Setup to TXD Clock High  
RXD Input Data Hold after TXD Clock High  
T
20  
ns  
1
a
T
ns  
1
0
ns  
1
NOTES:  
1. See Figure 12 for waveforms.  
2. n is the value of the BxCMP register ignoring the ICLK Bit (i.e., ICLK  
e
0).  
37  
37  
80C186EB/80C188EB, 80L186EB/80L188EB  
AC TEST CONDITIONS  
The AC specifications are tested with the 50 pF load  
shown in Figure 7. See the Derating Curves section  
to see how timings vary with load capacitance.  
272433–8  
e
C
L
50 pF for all signals.  
Figure 7. AC Test Load  
Specifications are measured at the V /2 crossing  
CC  
point, unless otherwise specified. See AC Timing  
Waveforms, for AC specification definitions, test  
pins, and illustrations.  
AC TIMING WAVEFORMS  
272433–9  
Figure 8. Input and Output Clock Waveform  
38  
38  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–10  
NOTE:  
20% V  
k
k
80% V  
Float  
CC  
CC  
Figure 9. Output Delay and Float Waveform  
272433–11  
Figure 10. Input Setup and Hold  
39  
39  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–12  
NOTE:  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 11. Relative Signal Waveform  
272433–13  
Figure 12. Serial Port Mode 0 Waveform  
40  
40  
80C186EB/80C188EB, 80L186EB/80L188EB  
DERATING CURVES  
TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE  
272433–14  
Figure 13  
TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE  
272433–15  
Figure 14  
41  
41  
80C186EB/80C188EB, 80L186EB/80L188EB  
RESET  
circuit). The RESIN pin is designed to operate cor-  
rectly using an RC reset circuit, but the designer  
must ensure that the ramp time for V  
is not so  
long that RESIN is never really sampled at a logic  
The processor will perform a reset operation any  
time the RESIN pin active. The RESIN pin is actually  
synchronized before it is presented internally, which  
means that the clock must be operating before a  
reset can take effect. From a power-on state, RESIN  
must be held active (low) in order to guarantee cor-  
rect initialization of the processor. Failure to pro-  
vide RESIN while the device is powering up will  
result in unspecified operation of the device.  
CC  
low level when V  
conditions.  
reaches minimum operating  
CC  
Figure 16 shows the timing sequence when RESIN  
is applied after V is stable and the device has  
CC  
been operating. Note that a reset will terminate all  
activity and return the processor to a known operat-  
ing state. Any bus operation that is in progress at the  
time RESIN is asserted will terminate immediately  
(note that most control signals will be driven to their  
inactive state first before floating).  
Figure 14 shows the correct reset sequence when  
first applying power to the processor. An external  
clock connected to CLKIN must not exceed the V  
CC  
threshold being applied to the processor. This is nor-  
mally not a problem if the clock driver is supplied  
While RESIN is active, bus signals LOCK, A19/  
ONCE, and A18:16 are configured as inputs and  
weakly held high by internal pullup transistors. Only  
19/ONCE can be overdriven to a low and is used to  
enable ONCE Mode. Forcing LOCK or A18:16 low at  
any time while RESIN is low is prohibited and will  
cause unspecified device operation.  
with the same V  
that supplies the processor.  
When attaching a crystal to the device, RESIN must  
CC  
remain active until both V and CLKOUT are stable  
CC  
(the length of time is application specific and de-  
pends on the startup characteristics of the crystal  
42  
42  
80C186EB/80C188EB, 80L186EB/80L188EB  
Figure 15. Cold Reset Waveforms  
43  
43  
80C186EB/80C188EB, 80L186EB/80L188EB  
Figure 16. Warm Reset Waveforms  
44  
44  
80C186EB/80C188EB, 80L186EB/80L188EB  
bus signals to CLKOUT. These figures along with  
the information present in AC Specifications allow  
the user to determine all the critical timing analysis  
needed for a given application.  
BUS CYCLE WAVEFORMS  
Figures 17 through 23 present the various bus cy-  
cles that are generated by the processor. What is  
shown in the figure is the relationship of the various  
272433–18  
NOTE:  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 17. Read, Fetch, and Refresh Cycle Waveforms  
45  
45  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–19  
NOTE:  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 18. Write Cycle Waveforms  
46  
46  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–20  
NOTE:  
The address driven is typically the location of the next instruction prefetch. Under a majority of instruction sequences the  
AD15:0 (AD7:0) bus will float, while the A19:16 (A19:8) bus remains driven and all bus control signals are driven to their  
inactive state.  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 19. Halt Cycle Waveforms  
47  
47  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–21  
NOTE:  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 20. Interrupt Acknowledge Cycle Waveform  
48  
48  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–22  
NOTE:  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 21. HOLD/HLDA Waveforms  
49  
49  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–23  
NOTES:  
1. READY must be low by either edge to cause a wait state.  
2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 22. Refresh during Hold Acknowledge  
50  
50  
80C186EB/80C188EB, 80L186EB/80L188EB  
272433–24  
NOTES:  
1. READY must be low by either edge to cause a wait state.  
2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.  
Pin names in parentheses apply to 80C188EB/80L188EB  
Figure 23. Ready Waveforms  
51  
51  
80C186EB/80C188EB, 80L186EB/80L188EB  
EXECUTION TIMINGS  
All instructions which involve memory accesses can  
require one or two additional clocks above the mini-  
mum timings shown due to the asynchronous hand-  
shake between the bus interface unit (BIU) and exe-  
cution unit.  
A determination of program execution timing must  
consider the bus cycles necessary to prefetch in-  
structions as well as the number of execution unit  
cycles necessary to execute instructions. The fol-  
lowing instruction timings represent the minimum  
execution time in clock cycles for each instruction.  
The timings given are based on the following as-  
sumptions:  
With a 16-bit BIU, the 80C186EB has sufficient bus  
performance to ensure that an adequate number of  
prefetched bytes will reside in the queue (6 bytes)  
most of the time. Therefore, actual program execu-  
tion time will not be substantially greater than that  
derived from adding the instruction timings shown.  
The opcode, along with any data or displacement  
#
required for execution of a particular instruction,  
has been prefetched and resides in the queue at  
the time it is needed.  
The 80C188EB 8-bit BIU is limited in its performance  
relative to the execution unit. A sufficient number of  
prefetched bytes may not reside in the prefetch  
queue (4 bytes) much of the time. Therefore, actual  
program execution time will be substantially greater  
than that derived from adding the instruction timings  
shown.  
No wait states or bus HOLDs occur.  
#
All word-data is located on even-address bound-  
aries (80C186EB only).  
#
All jumps and calls include the time required to fetch  
the opcode of the next instruction at the destination  
address.  
52  
52  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY  
80C186EB 80C188EB  
Function  
Format  
Clock  
Clock  
Comments  
Cycles  
Cycles  
DATA TRANSFER  
e
MOV  
Move:  
Register to Register/Memory  
Register/memory to register  
Immediate to register/memory  
Immediate to register  
1 0 0 0 1 0 0 w  
1 0 0 0 1 0 1 w  
1 1 0 0 0 1 1 w  
1 0 1 1 w reg  
1 0 1 0 0 0 0 w  
1 0 1 0 0 0 1 w  
1 0 0 0 1 1 1 0  
1 0 0 0 1 1 0 0  
mod reg r/m  
mod reg r/m  
mod 000 r/m  
data  
2/12  
2/9  
12/13  
3/4  
8
2/12*  
2/9*  
12/13  
3/4  
e
data  
data if w  
1
8/16-bit  
8/16-bit  
e
data if w  
1
Memory to accumulator  
addr-low  
addr-high  
addr-high  
8*  
Accumulator to memory  
addr-low  
9
9*  
Register/memory to segment register  
Segment register to register/memory  
mod 0 reg r/m  
mod 0 reg r/m  
2/9  
2/11  
2/13  
2/15  
e
PUSH  
Push:  
Memory  
Register  
1 1 1 1 1 1 1 1  
0 1 0 1 0 reg  
0 0 0 reg 1 1 0  
0 1 1 0 1 0 s 0  
mod 1 1 0 r/m  
16  
10  
9
20  
14  
13  
14  
Segment register  
Immediate  
e
data  
data if s  
0
10  
e
PUSHA  
Push All  
Pop:  
Memory  
0 1 1 0 0 0 0 0  
36  
68  
e
POP  
1 0 0 0 1 1 1 1  
0 1 0 1 1 reg  
0 0 0 reg 1 1 1  
mod 0 0 0 r/m  
(regi01)  
20  
10  
8
24  
14  
12  
Register  
Segment register  
e
e
POPA  
Pop All  
0 1 1 0 0 0 0 1  
51  
83  
XCHG  
Exchange:  
Register/memory with register  
Register with accumulator  
1 0 0 0 0 1 1 w  
1 0 0 1 0 reg  
mod reg r/m  
4/17  
3
4/17*  
3
e
IN  
Input from:  
Fixed port  
1 1 1 0 0 1 0 w  
1 1 1 0 1 1 0 w  
port  
port  
10  
8
10*  
8*  
Variable port  
e
OUT  
Output to:  
Fixed port  
1 1 1 0 0 1 1 w  
1 1 1 0 1 1 1 w  
1 1 0 1 0 1 1 1  
1 0 0 0 1 1 0 1  
1 1 0 0 0 1 0 1  
1 1 0 0 0 1 0 0  
1 0 0 1 1 1 1 1  
1 0 0 1 1 1 1 0  
1 0 0 1 1 1 0 0  
1 0 0 1 1 1 0 1  
9
7
9*  
7*  
15  
6
Variable port  
e
XLAT  
Translate byte to AL  
11  
6
e
LEA  
LDS  
LES  
Load EA to register  
Load pointer to DS  
Load pointer to ES  
mod reg r/m  
mod reg r/m  
mod reg r/m  
(modi11)  
(modi11)  
18  
18  
2
26  
26  
2
e
e
e
LAHF  
SAHF  
Load AH with flags  
Store AH into flags  
e
3
3
e
PUSHF  
Push flags  
9
13  
12  
e
POPF  
Pop flags  
8
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
53  
53  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY (Continued)  
80C186EB 80C188EB  
Function  
Format  
Clock  
Clock  
Comments  
Cycles  
Cycles  
DATA TRANSFER (Continued)  
e
SEGMENT  
Segment Override:  
CS  
0 0 1 0 1 1 1 0  
0 0 1 1 0 1 1 0  
0 0 1 1 1 1 1 0  
0 0 1 0 0 1 1 0  
2
2
2
2
2
2
2
2
SS  
DS  
ES  
ARITHMETIC  
e
ADD  
Add:  
Reg/memory with register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 0 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 0 0 1 0 w  
mod reg r/m  
mod 0 0 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4  
e
data if s w 01  
data  
e
e
data if w  
1
1
8/16-bit  
8/16-bit  
e
ADC  
Add with carry:  
Reg/memory with register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 1 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 0 1 0 w  
mod reg r/m  
mod 0 1 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4  
e
data if s w 01  
data  
data if w  
e
INC  
Increment:  
Register/memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 0 reg  
mod 0 0 0 r/m  
3/15  
3
3/15*  
3
e
SUB  
Subtract:  
Reg/memory and register to either  
Immediate from register/memory  
Immediate from accumulator  
0 0 1 0 1 0 d w  
1 0 0 0 0 0 s w  
0 0 1 0 1 1 0 w  
mod reg r/m  
mod 1 0 1 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4  
e
data if s w 01  
data  
e
e
data if w  
1
1
8/16-bit  
8/16-bit  
e
SBB  
Subtract with borrow:  
Reg/memory and register to either  
Immediate from register/memory  
Immediate from accumulator  
0 0 0 1 1 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 1 1 0 w  
mod reg r/m  
mod 0 1 1 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4*  
e
data if s w 01  
data  
data if w  
e
DEC  
Decrement  
Register/memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 1 reg  
mod 0 0 1 r/m  
3/15  
3
3/15*  
3
e
CMP  
Compare:  
Register/memory with register  
Register with register/memory  
Immediate with register/memory  
Immediate with accumulator  
0 0 1 1 1 0 1 w  
0 0 1 1 1 0 0 w  
1 0 0 0 0 0 s w  
0 0 1 1 1 1 0 w  
1 1 1 1 0 1 1 w  
0 0 1 1 0 1 1 1  
0 0 1 0 0 1 1 1  
0 0 1 1 1 1 1 1  
0 0 1 0 1 1 1 1  
mod reg r/m  
mod reg r/m  
mod 1 1 1 r/m  
data  
3/10  
3/10  
3/10  
3/4  
3/10  
8
3/10*  
3/10*  
3/10*  
3/4  
3/10*  
8
e
data if s w 01  
data  
e
data if w  
1
8/16-bit  
e
e
e
e
e
NEG  
AAA  
DAA  
AAS  
DAS  
Change sign register/memory  
ASCII adjust for add  
mod 0 1 1 r/m  
Decimal adjust for add  
4
4
ASCII adjust for subtract  
Decimal adjust for subtract  
7
7
4
4
e
MUL  
Multiply (unsigned):  
1 1 1 1 0 1 1 w  
mod 100 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
26–28  
35–37  
32–34  
41–43  
26–28  
35–37  
32–34  
41–43*  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
54  
54  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY (Continued)  
80C186EB 80C188EB  
Function  
Format  
Clock  
Clock  
Comments  
Cycles  
Cycles  
ARITHMETIC (Continued)  
e
IMUL  
Integer multiply (signed):  
1 1 1 1 0 1 1 w  
mod 1 0 1 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
25–28  
34–37  
31–34  
40–43  
25–28  
34–37  
31–34  
40–43*  
e
(signed)  
e
0
IMUL  
Integer Immediate multiply  
0 1 1 0 1 0 s 1  
1 1 1 1 0 1 1 w  
mod reg r/m  
data  
data if s  
22–25/  
29–32  
22–25/  
29–32  
e
DIV  
Divide (unsigned):  
mod 1 1 0 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
29  
38  
35  
44  
29  
38  
35  
44*  
e
IDIV  
Integer divide (signed):  
1 1 1 1 0 1 1 w  
mod 1 1 1 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
44–52  
53–61  
50–58  
59–67  
44–52  
53–61  
50–58  
59–67*  
e
e
e
e
AAM  
AAD  
CBW  
CWD  
ASCII adjust for multiply  
ASCII adjust for divide  
Convert byte to word  
1 1 0 1 0 1 0 0  
1 1 0 1 0 1 0 1  
1 0 0 1 1 0 0 0  
1 0 0 1 1 0 0 1  
0 0 0 0 1 0 1 0  
0 0 0 0 1 0 1 0  
19  
15  
2
19  
15  
2
Convert word to double word  
4
4
LOGIC  
Shift/Rotate Instructions:  
Register/Memory by 1  
1 1 0 1 0 0 0 w  
1 1 0 1 0 0 1 w  
1 1 0 0 0 0 0 w  
mod TTT r/m  
mod TTT r/m  
2/15  
2/15  
a
a
a
a
a
a
Register/Memory by CL  
5
5
n/17  
n/17  
n
n
5
5
n/17  
n/17  
n
n
a
a
Register/Memory by Count  
mod TTT r/m  
count  
TTT Instruction  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
ROL  
ROR  
RCL  
RCR  
1 0 0 SHL/SAL  
1 0 1  
1 1 1  
SHR  
SAR  
e
AND  
And:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 1 0 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 0 0 1 0 w  
mod reg r/m  
mod 1 0 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4*  
e
e
e
data  
data if w  
data if w  
data if w  
1
1
1
e
data if w  
1
1
1
8/16-bit  
8/16-bit  
8/16-bit  
e
TEST And function to flags, no result:  
Register/memory and register  
1 0 0 0 0 1 0 w  
1 1 1 1 0 1 1 w  
1 0 1 0 1 0 0 w  
mod reg r/m  
mod 0 0 0 r/m  
data  
3/10  
4/10  
3/4  
3/10*  
4/10*  
3/4  
Immediate data and register/memory  
Immediate data and accumulator  
data  
e
data if w  
e
OR Or:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 0 1 0 d w  
1 0 0 0 0 0 0 w  
0 0 0 0 1 1 0 w  
mod reg r/m  
mod 0 0 1 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4*  
data  
e
data if w  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
55  
55  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY (Continued)  
80C186EB 80C188EB  
Function  
Format  
Clock  
Clock  
Comments  
Cycles  
Cycles  
LOGIC (Continued)  
e
XOR  
Exclusive or:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 1 1 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 1 0 1 0 w  
1 1 1 1 0 1 1 w  
mod reg r/m  
mod 1 1 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4  
e
1
data  
data if w  
e
data if w  
1
8/16-bit  
e
NOT  
Invert register/memory  
mod 0 1 0 r/m  
3/10  
3/10*  
STRING MANIPULATION  
e
e
e
e
e
MOVS  
CMPS  
SCAS  
LODS  
STOS  
Move byte/word  
1 0 1 0 0 1 0 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
0 1 1 0 1 1 0 w  
0 1 1 0 1 1 1 w  
14  
22  
15  
12  
10  
14  
14  
14*  
22*  
15*  
12*  
10*  
14  
Compare byte/word  
Scan byte/word  
Load byte/wd to AL/AX  
Store byte/wd from AL/AX  
e
INS  
Input byte/wd from DX port  
e
OUTS  
Output byte/wd to DX port  
14  
Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)  
e
e
e
e
e
a
a
8 8n*  
MOVS  
CMPS  
SCAS  
LODS  
STOS  
Move string  
Compare string  
Scan string  
Load string  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 0 1 0 0 1 0 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
0 1 1 0 1 1 0 w  
8
8n  
a
a
5
5
6
22n  
15n  
11n  
5
5
6
22n*  
15n*  
11n*  
a
a
a
a
a
a
Store string  
6
9n  
8n  
6
9n*  
8n*  
e
a
a
a
a
INS  
Input string  
8
8
8
8
e
OUTS  
Output string  
1 1 1 1 0 0 1 0  
0 1 1 0 1 1 1 w  
8n  
8n*  
CONTROL TRANSFER  
e
CALL  
Call:  
Direct within segment  
1 1 1 0 1 0 0 0  
1 1 1 1 1 1 1 1  
disp-low  
disp-high  
15  
19  
Register/memory  
mod 0 1 0 r/m  
13/19  
17/27  
indirect within segment  
Direct intersegment  
1 0 0 1 1 0 1 0  
1 1 1 1 1 1 1 1  
segment offset  
segment selector  
23  
31  
i
(mod 11)  
Indirect intersegment  
mod 0 1 1 r/m  
38  
54  
e
JMP  
Unconditional jump:  
Short/long  
1 1 1 0 1 0 1 1  
1 1 1 0 1 0 0 1  
1 1 1 1 1 1 1 1  
disp-low  
disp-low  
14  
14  
14  
14  
Direct within segment  
disp-high  
Register/memory  
mod 1 0 0 r/m  
11/17  
11/21  
indirect within segment  
Direct intersegment  
Indirect intersegment  
1 1 1 0 1 0 1 0  
segment offset  
segment selector  
14  
26  
14  
34  
i
(mod 11)  
1 1 1 1 1 1 1 1  
mod 1 0 1 r/m  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
56  
56  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY (Continued)  
80C186EB  
Clock  
80C188EB  
Clock  
Function  
Format  
Comments  
Cycles  
Cycles  
CONTROL TRANSFER (Continued)  
e
RET  
Return from CALL:  
Within segment  
1 1 0 0 0 0 1 1  
1 1 0 0 0 0 1 0  
1 1 0 0 1 0 1 1  
1 1 0 0 1 0 1 0  
0 1 1 1 0 1 0 0  
0 1 1 1 1 1 0 0  
0 1 1 1 1 1 1 0  
0 1 1 1 0 0 1 0  
0 1 1 1 0 1 1 0  
0 1 1 1 1 0 1 0  
0 1 1 1 0 0 0 0  
0 1 1 1 1 0 0 0  
0 1 1 1 0 1 0 1  
0 1 1 1 1 1 0 1  
0 1 1 1 1 1 1 1  
0 1 1 1 0 0 1 1  
0 1 1 1 0 1 1 1  
0 1 1 1 1 0 1 1  
0 1 1 1 0 0 0 1  
0 1 1 1 1 0 0 1  
1 1 1 0 0 0 1 1  
1 1 1 0 0 0 1 0  
1 1 1 0 0 0 0 1  
1 1 1 0 0 0 0 0  
16  
20  
Within seg adding immed to SP  
Intersegment  
data-low  
data-high  
data-high  
18  
22  
22  
30  
Intersegment adding immediate to SP  
data-low  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
25  
33  
e
JE/JZ  
Jump on equal/zero  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
5/15  
6/16  
6/16  
6/16  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
5/15  
6/16  
6/16  
6/16  
JMP not  
taken/JMP  
taken  
e
e
e
e
JL/JNGE  
JLE/JNG  
JB/JNAE  
JBE/JNA  
Jump on less/not greater or equal  
Jump on less or equal/not greater  
Jump on below/not above or equal  
Jump on below or equal/not above  
e
JP/JPE  
Jump on parity/parity even  
Jump on overflow  
Jump on sign  
e
e
JO  
JS  
e
e
e
e
e
e
JNE/JNZ  
JNL/JGE  
JNLE/JG  
JNB/JAE  
JNBE/JA  
JNP/JPO  
Jump on not equal/not zero  
Jump on not less/greater or equal  
Jump on not less or equal/greater  
Jump on not below/above or equal  
Jump on not below or equal/above  
Jump on not par/par odd  
e
e
JNO  
JNS  
Jump on not overflow  
Jump on not sign  
e
JCXZ  
LOOP  
Jump on CX zero  
Loop CX times  
e
LOOP not  
taken/LOOP  
taken  
e
LOOPZ/LOOPE  
LOOPNZ/LOOPNE  
Loop while zero/equal  
e
Loop while not zero/equal  
e
ENTER  
Enter Procedure  
1 1 0 0 1 0 0 0  
data-low  
data-high  
L
e
e
l
L
L
L
0
1
1
15  
25  
19  
29  
a
b
a
b
22 16(n 1) 26 20(n 1)  
e
LEAVE  
Leave Procedure  
1 1 0 0 1 0 0 1  
8
8
e
INT  
Interrupt:  
Type specified  
Type 3  
1 1 0 0 1 1 0 1  
1 1 0 0 1 1 0 0  
1 1 0 0 1 1 1 0  
type  
47  
45  
47  
45  
if INT. taken/  
if INT. not  
taken  
e
INTO  
Interrupt on overflow  
48/4  
48/4  
e
IRET  
Interrupt return  
1 1 0 0 1 1 1 1  
0 1 1 0 0 0 1 0  
28  
28  
e
BOUND  
Detect value out of range  
mod reg r/m  
33–35  
33–35  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
57  
57  
80C186EB/80C188EB, 80L186EB/80L188EB  
INSTRUCTION SET SUMMARY (Continued)  
80C186EB 80C188EB  
Function  
Format  
Clock  
Clock  
Comments  
Cycles  
Cycles  
PROCESSOR CONTROL  
e
e
e
e
e
CLC  
CMC  
STC  
CLD  
STD  
Clear carry  
1 1 1 1 1 0 0 0  
1 1 1 1 0 1 0 1  
1 1 1 1 1 0 0 1  
1 1 1 1 1 1 0 0  
1 1 1 1 1 1 0 1  
1 1 1 1 1 0 1 0  
1 1 1 1 1 0 1 1  
1 1 1 1 0 1 0 0  
1 0 0 1 1 0 1 1  
1 1 1 1 0 0 0 0  
2
2
2
2
2
2
2
2
6
2
3
2
2
2
2
2
2
2
2
6
2
3
Complement carry  
Set carry  
Clear direction  
Set direction  
e
CLI  
STI  
Clear interrupt  
Set interrupt  
e
e
HLT  
Halt  
e
e
0
WAIT  
LOCK  
Wait  
if TEST  
e
Bus lock prefix  
e
NOP  
No Operation  
1 0 0 1 0 0 0 0  
(TTT LLL are opcode to processor extension)  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
reg is assigned according to the following:  
Segment  
FOOTNOTES  
The Effective Address (EA) of the memory operand  
is computed according to the mod and r/m fields:  
reg  
00  
01  
10  
11  
Register  
ES  
CS  
e
e
if mod  
if mod  
11 then r/m is treated as a REG field  
e
00 then DISP  
high are absent  
0*, disp-low and disp-  
SS  
DS  
e
e
tended to 16-bits, disp-high is absent  
if mod  
01 then DISP  
disp-low sign-ex-  
REG is assigned according to the following table:  
e
0)  
e
e
e
e
e
e
e
e
e
e
if mod  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
e
16-Bit (w  
1)  
8-Bit (w  
000 AL  
(BX)  
e
e
e
e
e
e
e
000 AX  
001 CX  
010 DX  
011 BX  
100 SP  
101 BP  
110 SI  
(BX)  
(BP)  
(BP)  
001 CL  
010 DL  
011 BL  
100 AH  
101 CH  
110 DH  
111 BH  
(SI)  
(DI)  
(BP)  
(BX)  
DISP follows 2nd byte of instruction (before data if  
required)  
111 DI  
The physical addresses of all operands addressed  
by the BP register are computed using the SS seg-  
ment register. The physical addresses of the desti-  
nation operands of the string primitive operations  
(those addressed by the DI register) are computed  
using the ES segment, which may not be overridden.  
e
e
e
110 then EA  
*except if mod  
disp-high: disp-low.  
00 and r/m  
EA calculation time is 4 clock cycles for all modes,  
and is included in the execution times given whenev-  
er appropriate.  
Segment Override Prefix  
0
0
1
reg  
1
1
0
58  
58  
80C186EB/80C188EB, 80L186EB/80L188EB  
5. SINT1 will only go active for one clock period  
when a receive or transmit interrupt is pending  
(i.e., it does not remain active until the S1STS  
register is read). If SINT1 is to be connected to  
any of the processor interrupt lines (INT0–INT4),  
then it must be latched by user logic.  
ERRATA  
An 80C186EB/80L186EB with a STEPID value of  
0001H has the following known errata. A device with  
a STEPID of 0001H can be visually identified by the  
presence of an ‘‘A’’ alpha character next to the  
FPO number. The FPO number location is shown in  
Figures 4, 5 and 6.  
An 80C186EB/80L186EB with a STEPID value of  
0001H or 0002H has the following known errata. A  
device with a STEPID of 0002H can be visually iden-  
tified by noting the presence of a ‘‘B’’, ‘‘C’’, ‘‘D’’, or  
‘‘E’’ alpha character next to the FPO number. The  
FPO number location is shown in Figures 4, 5 and 6.  
1. A19/ONCE is not latched by the rising edge of  
RESIN. A19/ONCE must remain active (LOW) at  
all times to remain in the ONCE Mode. Removing  
A19/ONCE after RESIN is high will return all out-  
put pins to  
80C186EB will remain in a reset state.  
a driving state, however, the  
1. An internal condition with the interrupt controller  
can cause no acknowledge cycle on the INTA1  
line in response to INT1. This errata only occurs  
when Interrupt 1 is configured in cascade mode  
and a higher priority interrupt exists. This errata  
will not occur consistantly, it is dependent on in-  
terrupt timing.  
2. During interrupt acknowledge (INTA) bus cycles,  
the bus controller will ignore the state of the  
READY pin if the previous bus cycle ignored the  
state of the READY pin. This errata can only oc-  
cur if the Chip-Select Unit is being used. All active  
chip-selects must be programmed to use READY  
(RDY bit must be programmed to a 1) if wait-  
states are required for INTA bus cycles.  
REVISION HISTORY  
3. CLKOUT will transition off the rising edge of  
CLKIN rather than the falling edge of CLKIN. This  
This data sheet replaces the following data sheets:  
270803-004 80C186EB  
270885-003 80C188EB  
does not affect any bus timings other than T  
.
CD  
4. RESIN has a hysterisis of only 130 mV. It is rec-  
ommended that RESIN be driven by a Schmitt  
triggered device to avoid processor lockup during  
reset using an RC circuit.  
270921-003 80L186EB  
270920-003 80L188EB  
272311-001 SB80C188EB/SB80L188EB  
272312-001 SB80C186EB/SB80L186EB  
59  
59  

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