T2500_技术文档

Intel® Core™ Duo Processor and

Intel® Core™ Solo Processor

on 65 nm Process

Datasheet

January 2007

Document Number: 309221-006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

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MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® Core™ Duo processor and the Intel® Core™ Solo processor may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different

processor families. See http://www.intel.com/products/processor_number for details.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Intel Core Duo, Intel Core Solo, Pentium, Intel SpeedStep, MMX and the Intel logo are registered trademarks or trademarks of Intel Corporation

and its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction..............................................................................................................7

1.1

1.2

Terminology .......................................................................................................9

References .........................................................................................................9

2

Low Power Features................................................................................................ 11

2.1

Clock Control and Low Power States .................................................................... 11

2.1.1 Core Low-Power States ........................................................................... 13

2.1.1.1 C0 State.................................................................................. 13

2.1.1.2 C1/AutoHALT Powerdown State .................................................. 13

2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13

2.1.1.4 Core C2 State........................................................................... 13

2.1.1.5 Core C3 State........................................................................... 14

2.1.1.6 Core C4 State........................................................................... 14

2.1.2 Package Low Power States ...................................................................... 14

2.1.2.1 Normal State............................................................................ 14

2.1.2.2 Stop-Grant State ...................................................................... 14

2.1.2.3 Stop Grant Snoop State............................................................. 15

2.1.2.4 Sleep State.............................................................................. 15

2.1.2.5 Deep Sleep State...................................................................... 16

2.1.2.6 Deeper Sleep State................................................................... 16

Enhanced Intel SpeedStep® Technology .............................................................. 17

Extended Low Power States................................................................................ 18

FSB Low Power Enhancements............................................................................ 19

Processor Power Status Indicator (PSI#) Signal..................................................... 19

2.2

2.3

2.4

2.5

3

Electrical Specifications........................................................................................... 21

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Power and Ground Pins ...................................................................................... 21

FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 21

Voltage Identification......................................................................................... 21

Catastrophic Thermal Protection.......................................................................... 24

Signal Terminations and Unused Pins................................................................... 25

FSB Frequency Select Signals (BSEL[2:0])............................................................ 25

FSB Signal Groups............................................................................................. 25

CMOS Signals ................................................................................................... 27

Maximum Ratings.............................................................................................. 27

3.10 Processor DC Specifications ................................................................................ 28

4

5

Package Mechanical Specifications and Pin Information.......................................... 41

4.1

Package Mechanical Specifications....................................................................... 41

4.1.1 Package Mechanical Drawings .................................................................. 41

4.1.2 Processor Component Keep-Out Zones...................................................... 46

4.1.3 Package Loading Specifications ................................................................ 46

4.1.4 Processor Mass Specifications .................................................................. 46

Processor Pinout and Pin List .............................................................................. 47

Alphabetical Signals Reference............................................................................ 49

4.2

4.3

Thermal Specifications and Design Considerations .................................................. 79

5.1

Thermal Specifications ....................................................................................... 85

5.1.1 Thermal Diode ....................................................................................... 85

5.1.2 Thermal Diode Offset.............................................................................. 87

5.1.3 Intel® Thermal Monitor........................................................................... 87

5.1.4 Digital Thermal Sensor (DTS)................................................................... 89

5.1.5 Out of Specification Detection .................................................................. 90

Datasheet

3

5.1.6 PROCHOT# Signal Pin .............................................................................90

Figures

1

2

3

Package-Level Low Power States ................................................................................12

Core Low Power States..............................................................................................12

Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and

Intel Core Solo Processor SV......................................................................................35

Deeper Sleep V_CCand I_CCLoadline for Intel Core Duo Processor (SV, LV & ULV) and

Intel Core Solo Processor SV......................................................................................36

Active VCC and ICC Loadline for Intel Core Solo Processor ULV.......................................37

Deeper Sleep V_CCand I_CCLoadline for Intel Core Solo Processor ULV ..............................38

Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................42

Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................43

Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................44

4

5

6

7

8

9

10 Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ...............................................45

Tables

1

Coordination of Core-Level Low Power States at the Package Level .................................11

2

3

4

5

6

7

8

9

Voltage Identification Definition..................................................................................21

BSEL[2:0] Encoding for BCLK Frequency......................................................................25

FSB Pin Groups ........................................................................................................26

Processor DC Absolute Maximum Ratings.....................................................................27

Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) .....28

Voltage and Current Specifications for Intel Core Solo Processor SV (Standard Voltage).....30

Voltage and Current Specifications for Intel Core Duo Processor LV (Low Voltage).............31

Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV)........32

10 Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage)...33

11 FSB Differential BCLK Specifications............................................................................39

12 AGTL+ Signal Group DC Specifications ........................................................................39

13 CMOS Signal Group DC Specifications..........................................................................40

14 Open Drain Signal Group DC Specifications ..................................................................40

15 The Coordinates of the Processor Pins as Viewed from the Top of the Package..................47

16 The Coordinates of the Processor Pins as Viewed from the Top of the Package .................48

17 Signal Description.....................................................................................................49

18 Pin Listing by Pin Name.............................................................................................59

19 Pin Listing by Pin Number..........................................................................................69

20 Power Specifications for the Intel Core Duo Processor SV (Standard Voltage) ...................80

21 Power Specifications for the Intel Core Solo Processor SV (Standard Voltage)...................81

22 Power Specifications for the Intel Core Duo Processor LV (Low Voltage)...........................82

23 Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage (ULV) ................83

24 Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage).................84

25 Thermal Diode Interface............................................................................................85

26 Thermal Diode Parameters using Diode Mode...............................................................86

27 Thermal Diode Parameters using Transistor Mode .........................................................86

28 Thermal Diode n_trimand Diode Correction Toffset..........................................................87

4

Datasheet

Revision History

Revision

Description

Date

-001

Initial Release

January 2006

•

Added references to ULV processor throughout the document

Replaced references to the terminology Deep C4 voltage with Intel® Enhanced Deeper

Sleep Voltage throughout the document.

•

Replaced references to Enhanced Low Power states with CxE Low Power States

Section 3.10

— Included Table 10 Voltage and Current Specifications for Intel Core Solo Processor

-002

April 2006

ULV

— Included Figure 5 Active VCC and ICC Load Line for Intel Core Solo Processor ULV

— Included Figure 6 Deeper Sleep VCC and ICC Load Line for Intel Core Solo

Processor ULV

•

Chapter 5

— Included Table 24 Power Specifications for the Intel Core Solo Processor ULV (Ultra

Low Voltage)

•

Added Intel® Core™ Duo Processor T2300E and Intel® Core™ Solo Processor T1400

specifications.

-003

-004

May 2006

June 2006

Added references to Intel Core Duo Processor, Ultra Low Voltage (ULV) throughout the

document

CxE low power states now also referred to as Extended Low Power States

Section 3.10

— Updated Table 6 - Added Icc spec for T2700

— Included Table 9 Voltage and Current Specifications Intel Core Duo Processor, Ultra

Low Voltage (ULV)

Chapter 5

•

— Updated Table 20 - Added TDP for T2700

— Included Table 23 - Power Specification for Intel Core Duo Processor Ultra Low

Voltage (ULV)

•

In Chapter 3:

— Added L2500 processor specifications to Table 8.

— Added U2400 processor specifications to Table 9.

In Chapter 5:

— Added L2500 processor power specifications to Table 22.

— Added U2400 processor power specifications to Table 23.

-005

-006

September 2006

January 2007

•

In Chapter 3:

— Added U1500 processor specifications to Table 10.

In Chapter 5:

— Added U1500 processor power specifications to Table 24.

§

Datasheet

5

6

Datasheet

Introduction

1 Introduction

The Intel® Core^TMDuo processor and the Intel® Core^TMSolo processor are built on

Intel’s next generation 65 nanometer process technology with copper interconnect. The

Intel Core Solo processor refers to a single core processor and the Intel Core Duo

processor refers to a dual core processor. This document provides specifications for all

Intel Core Duo processor and Intel Core Solo processor in standard voltage (SV), low

voltage (LV) and ultra low voltage (ULV) products.

Note:

All instances of the “processor” in this document refer to the Intel Core Duo processor

and Intel Core Solo processor with 2-MB L2 cache, unless specified otherwise.

Intel processor numbers are not a measure of performance. Processor numbers

differentiate features within each processor family, not across different processor

families. See www.intel.com/products/processor_number for details.

The following list provides some of the key features on this processor:

• First dual core processor for mobile

• Supports Intel® Architecture with Dynamic Execution

• On-die, primary 32-KB instruction cache and 32-KB write-back data cache

• On-die, 2-MB second level cache with Advanced Transfer Cache Architecture

• Data Prefetch Logic

• Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)

• The Intel Core Duo processor and Intel Core Solo processor standard voltage and

low voltage processors are offered at 667-MHz FSB

• The Intel Core Duo processor and Intel Core Solo processor ultra low voltage are

offered at 533-MHz FSB

• Advanced power management features including Enhanced Intel SpeedStep®

Technology

• Digital thermal sensor (DTS)

• The Intel Core Duo processor and Intel Core Solo processor standard voltage are

offered in both the Micro-FCPGA and the Micro-FCBGA packages

• Intel Core Duo processor low voltage is offered only in the Micro-FCBGA package

• The Intel Core Duo processor and Intel Core Solo processor ultra low voltage are

offered only in Micro-FCBGA package

• Execute Disable Bit support for enhanced security

• Intel® Virtualization Technology

• Intel® Enhanced Deeper Sleep and Dynamic Cache Sizing

The processor maintains support for MMX™ technology, Streaming SIMD instructions,

and full compatibility with IA-32 software. The processor features on-die, 32-KB, Level

1 instruction and data caches and a 2-MB level 2 cache with Advanced Transfer Cache

Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2

cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties.

The processor includes the Data Cache Unit Streamer which enhances the performance

of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Writer Order

Buffer depth is enhanced to help with the write-back latency performance.

Datasheet

7

Introduction

In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are

13 new instructions which extend the capabilities of Intel processor technology further.

These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics

and other entertainment applications, such as gaming, will have the opportunity to take

advantage of these new instructions as platforms with the processor and SSE3 become

available in the market place.

The processor’s FSB utilizes a split-transaction, deferred reply protocol. The FSB uses

Source-Synchronous Transfer (SST) of address and data to improve performance by

transferring data four times per bus clock. The 4X data bus can deliver data four times

per bus clock and is referred as “quad-pumped” or 4X data bus, the address bus can

deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X

address bus. Working together, the 4X data bus and the 2X address bus provide a data

bus bandwidth of up to 5.33 GB/second. The FSB uses Advanced Gunning Transceiver

Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low

power enhancements.

The processor features Enhanced Intel SpeedStep Technology, which enables real-time

dynamic switching between multiple voltage and frequency points. The processor

features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep low power C-states.

The processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and

surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The

Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF)

socket, which is referred to as the mPGA479M socket.

The processor supports the Execute Disable Bit capability. This feature, combined with

a support operating system, allows memory to be marked as executable or non

executable. If code attempts to run in non-executable memory the processor raises an

error to the operating system. This feature can prevent some classes of viruses or

worms that exploit buffer overrun vulnerabilities and can thus help improve the overall

security of the system. See the Intel® Architecture Software Developer's Manual for

more detailed information.

Intel Virtualization Technology is a set of hardware enhancements to Intel server and

client systems that combined with the appropriate software, will enable enhanced

virtualization robustness and performance for both enterprise and consumer uses. Intel

Virtualization Technology forms the foundation of Intel technologies focused on

improved virtualization, safer computing, and system stability. For client systems, Intel

Virtualization Technology’s hardware-based isolation helps provide the foundation for

highly available and more secure client virtualization partitions.

8

Datasheet

Introduction

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

XXXX means that the specification or value is yet to be determined.

#

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document. Chipset references in this document are to the Mobile Intel®

945 Express Chipset family unless specified otherwise.

Document

Number

Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm

Process Specification Update

309222

Mobile Intel® 945 Express Chipset Family Datasheet

Mobile Intel® 945 Express Chipset Family Specification Update

Intel® I/O Controller Hub 7 (ICH7) Family Datasheet

Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

Intel® Architecture Software Developer's Manual

Volume 1 Basic Architecture

309219

309220

307013

307014

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

AP-485, Intel® Processor Identification and CPUID Instruction Application

Note

241618

§

Datasheet

9

Introduction

10

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low Power States

The Intel Core Duo processor and Intel Core Solo processor support low power states

both at the individual core level and the package level for optimal power management.

A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low

power states. Refer to Figure 2 for a visual representation of the core low power states

for the Intel Core Duo processor and Intel Core Solo processor. When both cores

coincide in a common core low power state, the central power management logic

ensures the Intel Core Duo processor enters the respective package low power state by

initiating a P_LVLx (P_LVL2, P_LVL3, and P_LVL4) I/O read to the Mobile Intel 945

Express Chipset family. Package low power states include Normal, Stop Grant, Stop

Grant Snoop, Sleep, Deep Sleep, and Deeper Sleep. Refer Figure 1 for a visual

representation of the package low-power states for the Intel Core Duo processor and

Intel Core Solo processor and to Table 1 for a mapping of core low power states to

package low power states.

The processor implements two software interfaces for requesting low power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are

converted to equivalent MWAIT C-state requests inside the processor and do not

directly result in I/O reads on the processor FSB. The monitor address does not need to

be setup before using the P_LVLx I/O read interface. The sub-state hints used for each

P_LVLx read can be configured in a software programmable MSR.

When software running on a core requests the C4 state, that core enters the core C4

state, which is identical to the core C3 state. When both cores have requested C4 then

the Intel Core Duo processor will enter the Deeper Sleep state.

If a core encounters a chipset break event while STPCLK# is asserted, then it asserts

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to

system logic that individual cores should return to the C0 state and the Intel Core Duo

processor should return to the Normal state. Same mechanism is also applicable for the

Intel Core Solo processor.

Table 1.

Coordination of Core-Level Low Power States at the Package Level

Dual Core: Core1 State

Single

Resolved

Package State

Core

C0

C1¹

C2

C3

C4

C0

C1^†

C2

Normal

Stop Grant

Deep Sleep

Stop Grant

Deep Sleep

Stop Grant

Deep Sleep

C3

Deeper Sleep /

Intel®

C4

Deeper Sleep

Normal

Stop Grant

Deep Sleep

Enhanced

Deeper Sleep

NOTE:

1.

AutoHALT or MWAIT/C1.

Datasheet

11

Low Power Features

Figure 1.

Package-Level Low Power States

SLP# asserted

DPSLP# asserted

DPRSTP# asserted

STPCLK# asserted

Deeper

Sleep^†

Stop

Grant

Deep

Sleep

Normal

Sleep

STPCLK# de-asserted

SLP# de-asserted

DPSLP# de-asserted

DPRSTP# de-asserted

Snoop

serviced occurs

Stop

Grant

Snoop

† — Deeper Sleep includes the Deeper Sleep and the Intel Enhanced Deeper Sleep state.

Figure 2.

Core Low Power States

Stop

Grant

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

de-asserted

asserted

STPCLK#

de-asserted

STPCLK#

asserted

C1/

MWAIT

C1/Auto

Halt

Core state

break

HLT instruction

Halt break

MWAIT(C1)

C0

Core State

break

P_LVL2 or

MWAIT(C2)

P_LVL4 or

MWAIT(C4)

Core state

break

C4^{† ‡}

C2^†

Core

state

break

P_LVL3 or

MWAIT(C3)

C3^†

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.

‡ — Core C4 state supports the package level Intel Enhanced Deeper sleepstate.

12

Datasheet

Low Power Features

2.1.1

Core Low-Power States

2.1.1.1

C0 State

This is the normal operating state for the Intel Core Duo processor and Intel Core Solo

processor.

2.1.1.2

C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when the processor core executes the HALT

instruction. The processor core will transition to the C0 state upon the occurrence of

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the

processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® Architecture Software

Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information.

The system can generate an STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

While in AutoHALT Powerdown state, the dual core processor will process bus snoops

and snoops from the other core, and the single core processor will process only the bus

snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to

process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3

2.1.1.4

C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT

instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state

except that there is an additional event that can cause the processor core to return to

the C0 state: the Monitor event. See the Intel® Architecture Software Developer's

Manual, Volumes 2A/2B: Instruction Set Reference, for more information.

Core C2 State

Individual cores of the Intel Core Duo processor and Intel Core Solo processor can

enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2)

instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle

unless the STPCLK# pin is also asserted.

While in C2 state, the dual core processor will process bus snoops and snoops from the

other core, and the single core processor will process only the bus snoops. The

processor core will enter a snoopable sub-state (not shown in Figure 2) to process the

snoop and then return to the C2 state.

Datasheet

13

Low Power Features

2.1.1.5

Core C3 State

Core C3 state is a very low power state the processor core can enter while maintaining

context. Individual cores of the Intel Core Duo processor and Intel Core Solo processor

can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3)

instruction. Before entering the C3 state, the processor core flushes the contents of its

L1 caches into the processor’s L2 cache. Except for the caches, the processor core

maintains all its architectural state in the C3 state. The Monitor remains armed if it is

configured. All of the clocks in the processor core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB or when the other core of the dual core

processor accesses cacheable memory. The processor core will transition to the C0

state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or

FSB interrupt message. RESET# will cause the processor core to immediately initialize

itself.

2.1.1.6

Core C4 State

Individual cores of the Intel Core Duo processor and Intel Core Solo processor can

enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4)

instruction. The processor core behavior in the C4 state is identical to the behavior in

the C3 state. The only difference is that if both processor cores are in C4, then the

central power management logic will request that the entire dual core processor enter

the Deeper Sleep package low power state (see Section 2.1.2.5). The single core

processor would be put into the Deeper Sleep State in C4 state if the low power state

coordination logic is enabled.

To enable the package level Intel Enhanced Deeper Sleep Low Voltage, Dynamic Cache

Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software

programmable MSR.

2.1.2

Package Low Power States

The package level low power states are applicable for the Intel Core Duo processor as

well as the Intel Core Solo processor. The package level low power states are described

in Section 2.1.2.1 through Section Section 2.1.2.6.

2.1.2.1

2.1.2.2

Normal State

This is the normal operating state for the processor. The processor enters the Normal

state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

Stop-Grant State

When the STPCLK# pin is asserted, each core of the Intel Core Duo processor and Intel

Core Solo processor enters the Stop-Grant state within 20 bus clocks after the

response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Processor cores that are already in the C2, C3, or C4 state remain in their current low-

power state. When the STPCLK# pin is deasserted, each core returns to its previous

core low power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

14

Datasheet

Low Power Features

RESET# will cause the processor to immediately initialize itself, but the processor will

stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#,

DPSLP#, and DPRSTP# pins must be deasserted more than 450 µs prior to RESET#

deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK#

should be deasserted ten or more bus clocks after the deassertion of SLP#.

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt or monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the entire dual core

processor should return to the Normal state.

A transition to the Stop Grant Snoop state will occur when the processor detects a

snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see

Section 2.1.2.4) will occur with the assertion of the SLP# signal.

2.1.2.3

2.1.2.4

Stop Grant Snoop State

The processor will respond to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor will return

to the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

Sleep State

The Sleep state is a low power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through Stop-Grant State. If RESET# is driven active while the processor

is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately

after RESET# is asserted to ensure the processor correctly executes the Reset

sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur.

Datasheet

15

Low Power Features

2.1.2.5

Deep Sleep State

Deep Sleep state is a very low power state the processor can enter while maintaining

context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform level

power savings. BCLK stop/restart timings on appropriate chipset-based platforms with

the CK410M clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of

DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to

allow for PLL stabilization) must occur before the processor can be considered to be in

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep

state, it will not respond to interrupts or snoop transactions. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable

behavior.

2.1.2.6

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to

one of two lower levels. One lower core voltage level is achieved by entering the base

Deeper Sleep state. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the

lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper

Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered

through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache

has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for

further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep

state.

In response to entering Deeper Sleep, the processor will drive the VID code

corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by

DPRSTP# deassertion when either core requests a core state other than C4 or either

core requests a processor performance state other than the lowest operating point.

2.1.2.6.1

Intel Enhanced Deeper Sleep State

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power

saving capabilities by allowing the processor to further reduce core voltage once the L2

cache has been reduced to zero ways and completely shut down. The following events

occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 I/O read or an MWAIT(C4) instruction

and then progressively reduces the L2 cache to zero.

• The processor drives the VID code corresponding to the Intel Enhanced Deeper

Sleep state core voltage on the VID[6:0] pins.

16

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Low Power Features

2.1.2.6.2

Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable

number of L2 cache ways upon each Deeper Sleep entry under the following

conditions:

• The second core is already in C4 and the Intel Enhanced Deeper Sleep state is

enabled (as specified in Section 2.1.2.6.1).

• The C0 timer, which tracks continuous residency in the Normal package state, has

not expired. This timer is cleared during the first entry into Deeper Sleep to allow

consecutive Deeper Sleep entries to shrink the L2 cache as needed.

• The FSB speed to processor core speed ratio is below the predefined L2 shrink

threshold.

If the FSB speed to processor core speed ratio is above the predefined L2 shrink

threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio

will not be taken into account for Dynamic Cache Sizing decisions.

Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep

state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways.

If the L2 cache reduction conditions stated above still exist when the last core returns

to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be

shrunk to zero again. If a core requests a processor performance state resulting in a

higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the

second core (not the one currently entering the interrupt routine) requests the C1, C2,

or C3 states, then the whole L2 will be expanded when the next INTR event would

occur.

L2 cache shrink prevention may be enabled as needed on occasion through an

MWAIT(C4) sub-state field. If shrink prevention is enabled, then the processor does not

enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in

full size.

2.2

Enhanced Intel SpeedStep® Technology

Intel Core Duo processor and Intel Core Solo processor feature Enhanced Intel

SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep

Technology:

• Multiple voltage/frequency operating points provide optimal performance at the

lowest power.

• Voltage/Frequency selection is software controlled by writing to processor MSR’s

(Model Specific Registers).

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch free

transitions.

• Low transition latency and large number of transitions possible per second.

— Processor core (including L2 cache) is unavailable for up to 10 μs during the

frequency transition

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17

Low Power Features

— The bus protocol (BNR# mechanism) is used to block snooping

• Improved Intel® Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high,

the processor can automatically perform a transition to a lower frequency/

voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up transition to the previous frequency/voltage point

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system level thermal management.

• Enhanced thermal management features.

— Digital thermal sensor and thermal interrupts

— TM1 in addition to TM2 in case of non successful TM2 transition.

— dual core thermal management synchronization.

Each core in the Intel Core Duo processor implements an independent MSR for

controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the

same frequency and voltage. The processor has performance state coordination logic to

resolve frequency and voltage requests from the two cores into a single frequency and

voltage request for the package as a whole. If both cores request the same frequency

and voltage then the Intel Core Duo processor will transition to the requested common

frequency and voltage. If the two cores have different frequency and voltage requests

then the Intel Core Duo processor will take the highest of the two frequencies and

voltages as the resolved request and transition to that frequency and voltage.

2.3

Extended Low Power States

The Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly

reducing the performance state of the processor when it enters a package low power

state. Instead of directly transitioning into the package low power states, the extended

low power state first reduces the performance state of the processor by performing an

Enhanced Intel SpeedStep Technology transition down to the lowest operating point.

Upon receiving a break event from the package low power state, control will be

returned to software while an Enhanced Intel SpeedStep Technology transition up to

the initial operating point occurs. The advantage of this feature is that it significantly

reduces leakage while in the package low power states.

The processor implements two software interfaces for requesting extended low power

states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring

a software programmable MSR bit to automatically promote package low power states

to extended low power states.

Note:

C2E and C4E must be enabled via the BIOS for the processor to remain within

specification.

Enhanced Intel SpeedStep Technology transitions are multistep processes that require

clocked control. These transitions cannot occur when the processor is in the Sleep or

Deep Sleep package low power states since processor clocks are not active in these

states. C4E is an exception to this rule when the Hard C4E configuration is enabled in a

software programmable MSR bit. This C4E low power state configuration will lower core

voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will

automatically transition to the lowest operating voltage and frequency to reduce snoop

service latency. The transition to the lowest operating point or back to the original

software requested point may not be instantaneous. Furthermore, upon very frequent

transitions between active and idle states, the transitions may lag behind the idle state

18

Datasheet

Low Power Features

entry resulting in the processor either executing for a longer time at the lowest

operating point or running idle at a high operating point. Observations and analyses

show this behavior should not significantly impact total power savings or performance

score while providing power benefits in most other cases.

2.4

FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On Die Termination disabling

• Low VCCP (I/O termination voltage)

The Intel Core Duo processor and Intel Core Solo processor incorporate the DPWR#

signal that controls the data bus input buffers on the processor. The DPWR# signal

disables the buffers when not used and activates them only when data bus activity

occurs, resulting in significant power savings with no performance impact. BPRI#

control also allows the processor address and control input buffers to be turned off

when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power

reduction in chipset address and control input buffers when the processor deasserts its

BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the

signals are driven low, resulting in additional power savings. The low I/O termination

voltage is on a dedicated voltage plane independent of the core voltage, enabling low

I/O switching power at all times.

2.5

Processor Power Status Indicator (PSI#) Signal

The Intel Core Duo processor and Intel Core Solo processor incorporate the PSI# signal

that is asserted when the processor is in a reduced power consumption state. PSI# can

be used to improve intermediate and light load efficiency of the voltage regulator,

resulting in platform power savings and improved battery life. The algorithm that the

Intel Core Duo processor and Intel Core Solo processor use for determining when to

assert PSI# is different from the algorithm used in previous Intel® Pentium® M

processors.

§

Datasheet

19

Low Power Features

20

Datasheet

Electrical Specifications

3 Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower

planes while all V_SSpins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. Please contact your

Intel representative for more details. The processor V_CCpins must be supplied the

voltage determined by the VID (Voltage ID) pins.

3.2

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the Intel Core Duo processor and Intel

Core Solo processors’ core frequency is a multiple of the BCLK[1:0] frequency. The

processor uses a differential clocking implementation.

3.3

Voltage Identification

The processor uses seven voltage identification pins, VID[6:0], to support automatic

selection of power supply voltages. The VID pins for the processor are CMOS outputs

driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to low-

voltage level.

Table 2.

Voltage Identification Definition (Sheet 1 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

Datasheet

21

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 2 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

22

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Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 3 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

Datasheet

23

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 4 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

3.4

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough such that

the processor cannot be protected in all conditions without the removal of power to the

processor. If the external thermal sensor detects a catastrophic processor temperature

of 125°C (maximum), or if the THERMTRIP# signal is asserted, the V_CCsupply to the

processor must be turned off within 500 ms to prevent permanent silicon damage due

to thermal runaway of the processor.

24

Datasheet

Electrical Specifications

3.5

Signal Terminations and Unused Pins

All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V_CC,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the

processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected.

The TEST1 pin must have a stuffing option connection to V_SS. The TEST2 pin must have

a 51 Ω ±5%, pull-down resistor to V_SS.

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the Mobile Intel

945 Express Chipset family on the platform. The BSEL encoding for BCLK[1:0] is shown

in Table 3:

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BCLK

BSEL[2]

BSEL[1]

BSEL[0]

Frequency

L

H

L

RESERVED

133 MHz

RESERVED

166 MHz

H

3.7

FSB Signal Groups

In order to simplify the following discussion, the FSB signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use

GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the

AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+

Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when

driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 4 identifies which signals are common clock, source synchronous,

and asynchronous.

Datasheet

25

Electrical Specifications

Table 4.

FSB Pin Groups

Signal Group

Type

Signals¹

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,

TRDY#

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

Synchronous to

BCLK[1:0]

ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#, DRDY#, HIT#,

HITM#, LOCK#, PRDY#³

Signals

Associated Strobe

REQ[4:0]#, A[16:3]#

A[31:17]#

ADSTB[0]#

ADSTB[1]#

Synchronous to

Assoc. Strobe

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

AGTL+ Source Synchronous I/O

Synchronous to

BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Asynchronous

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous

FERR#, IERR#, THERMTRIP#

PROCHOT#⁴

PSI#, VID[6:0], BSEL[2:0]

Synchronous to

TCK

CMOS Input

TCK, TDI, TMS, TRST#

TDO

Synchronous to

TCK

Open Drain Output

FSB Clock

Clock

BCLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST2, TEST1,

Power/Other

THERMDA, THERMDC, V_CC, V_CCA, V_CCP, V_CCSENSE, V_SS

,

V_SSSENSE

NOTES:

1.

2.

Refer to Table 17 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board, these signals are

used to support a debug port interposer. In systems with the debug port implemented on the system

board, these signals are no connects.

3.

4.

BPM[2:1]# and PRDY# are AGTL+ output only signals.

PROCHOT# signal type is open drain output and CMOS input.

26

Datasheet

Electrical Specifications

3.8

3.9

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for at least three BCLKs in order for

the processor to recognize them. See Section 3.10 for the DC specifications for the

CMOS signal groups.

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings. Only within specified

operation limits, can functionality and long-term reliability be expected.

At condition outside functional operation condition limits, but within absolute maximum

and minimum ratings, neither functionality nor long term reliability can be expected. If

a device is returned to conditions within functional operation limits after having been

subjected to conditions outside these limits, but within the absolute maximum and

minimum ratings, the device may be functional, but with its lifetime degraded on

exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from electro static

discharge, precautions should always be taken to avoid high static voltages or electric

fields.

Table 5.

Processor DC Absolute Maximum Ratings

Symbol

T_STORAGE

V_CC

Parameter

Processor Storage Temperature

Min

Max

Unit

Notes

-40

-0.3

85

1.6

°C

V

2

Any Processor Supply Voltage with Respect to V_SS

AGTL+ Buffer DC Input Voltage with Respect to V_SS

1

V_inAGTL+

V

1, 2

V_{inAsynch_CMOS}CMOS Buffer DC iNput Voltage with Respect to V_SS

V

NOTES:

1.

2.

This rating applies to any processor pin.

Contact Intel for storage requirements in excess of one year.

Datasheet

27

Electrical Specifications

3.10

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and

signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group.

The DC specifications for these signals are listed in Table 12. DC specifications for the

CMOS group are listed in Table 13.

Table 6 through Table 14 list the DC specifications for the processor and are valid only

while meeting specifications for junction temperature, clock frequency, and input

voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer

to the highest and lowest core operating frequencies supported on the processor. Active

mode load line specifications apply in all states except in the Deep Sleep and Deeper

Sleep states. V_CC,BOOTis the default voltage driven by the voltage regulator at power

up in order to set the VID values. Unless specified otherwise, all specifications for the

processor are at Tjunction = 100°C. Care should be taken to read all notes associated

with each parameter.

Table 6.

Symbol

Voltage and Current Specifications for Intel Core Duo Processor SV (Standard

Voltage) (Sheet 1 of 2)

Parameter

Min

Typ

Max

Unit

Notes

1, 2

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.1625

0.7625

1.3

1.0

V

1, 2

2, 8

2

1.20

1.05

1.5

0.997

1.425

0.55

1.102

1.575

0.85

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCat Deeper Sleep Voltage

1, 2, 12

1, 2

V_CCat Intel Enhanced Deeper Sleep

Voltage

V_CCDC4

I_CCDES

0.50

0.80

36

V

A

I_CCfor Intel® Core™ Duo Processor SV

Recommended Design Target

5

I_CCfor Intel Core Duo Processor SV

Processor

Core Frequency/Voltage

Number

T2700

T2600

T2500

T2400

T2300

T2300E

N/A

2.33 GHz and HFM V_CC

2.16 GHz and HFM V_CC

2.00 GHz and HFM V_CC

1.83 GHz and HFM V_CC

1.66 GHz and HFM V_CC

1 GHz and LFM V_CC

34

I_CC

34

A

3,12,13

34

15.5

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

12.5

23.3

A

3,4

ISGNT

I_CCSleep

LFM

I_SLP

12.4

23.2

HFM

28

Datasheet

Electrical Specifications

Table 6.

Symbol

I_DSLP

Voltage and Current Specifications for Intel Core Duo Processor SV (Standard

Voltage) (Sheet 2 of 2)

Parameter

Min

Typ

Max

Unit

Notes

I_CCDeep Sleep

LFM

HFM

11.8

20.9

A

3, 4

I_DPRSLP

I_DC4

I_CCDeeper Sleep

7.6

6.7

A

3, 4

4

I_CCIntel Enhanced Deeper Sleep

V_CCPower Supply Current Slew Rate at

CPU Package Pin

dI_CC/DT

I_CCA

600

120

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

6.0

2.5

A

10

9

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

2.

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

Specified at 100°C Tj.

Specified at the VID voltage.

The I_CCDES(max) specification of 36 A comprehends only Intel Core Duo processor SV HFM frequencies.

Platforms should be designed to 44 A to be compatible with next generation processor.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

6.

7.

Measured at the bulk capacitors on the motherboard.

8.

V_CC, boot tolerance is shown in Figure 3.

9.

This is a steady-state I_CCPcurrent specification, which is applicable when both V_CCPand V_CCcore are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_CCcore is low.

10.

11.

12.

Specified at the nominal V_CC

.

If a given Operating Systems C-State model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

13.

T2300E does not support Intel Virtualization Technology.

Datasheet

29

Electrical Specifications

Table 7.

Symbol

Voltage and Current Specifications for Intel Core Solo Processor SV (Standard

Voltage)

Parameter

Min

Typ

Max

Unit

Notes

1, 2

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.1625

0.7625

1.3

1.0

V

A

1, 2

2, 8

2

1.20

1.05

1.5

0.997

1.425

0.55

1.102

1.575

0.85

0.80

36

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCDC4

I_CCDES

V_CCat Deeper Sleep Voltage

1, 2, 12

1, 2

V_CCat Intel Enhanced Deeper Sleep Voltage

I_CCfor Intel® Core™ Solo Processor SV

I_CCfor Intel Core Solo Processor SV

0.50

5

Processor

Core Frequency/Voltage

Number

I_CC

T1400

T1300

N/A

1.83 GHz and HFM V_CC

1.66 GHz and HFM V_CC

1 GHz and LFM V_CC

34

15.5

A

3,11

3,4

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

12.5

23.3

I_SGNT

I_CCSleep

LFM

I_SLP

12.4

23.2

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

11.8

20.9

I_DPRSLP

I_DC4

I_CCDeeper Sleep

7.6

6.7

A

3,4

4

I_CCIntel Enhanced Deeper Sleep

V_CCPower Supply Current Slew Rate at CPU

Package Pin

dI_CC/DT

I_CCA

600

120

A/µs 6, 7

mA

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before Vcc Stable

I_CCfor V_CCPSupply after Vcc Stable

6.0

2.5

A

10

9

ICCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

2.

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

Specified at 100°C Tj.

Specified at the VID voltage.

The I_CCDES(max) specification of 36 A comprehends only Intel Core Solo processor SV HFM frequencies.

30

Datasheet

Electrical Specifications

6.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

Measured at the bulk capacitors on the motherboard.

7.

8.

V_CC, boot tolerance is shown in Figure 3.

9.

This is a steady-state Iccp current specification, which is applicable when both V_CCPand Vcc core are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and Vcc core is low.

10.

11.

12.

Specified at the nominal V_CC

.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

Table 8.

Voltage and Current Specifications for Intel Core Duo Processor LV (Low

Voltage)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.0000

0.7625

1.2125

1.0000

V

1, 2, 3

2, 8

1.20

1.05

1.5

0.997

1.425

0.55

1.102

1.575

0.85

2

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCat Deeper Sleep Voltage

1, 2, 12

1, 2

V_CCat Intel® Enhanced Deeper Sleep

Voltage

V_CCDC4

I_CCDES

0.50

0.80

19

V

A

I_CCfor Intel® Core™ Duo Processor LV

Icc for Intel Core Duo Processor LV

5

Processor

Core Frequency/Voltage

Number

I_CC

L2500

L2400

L2300

N/A

1.83 GHz and HFM V_CC

1.66 GHz and HFM V_CC

1.50 GHz and HFM V_CC

1 GHz and LFM V_CC

19

A

3,11

19

15.5

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

12.5

13.5

A

3,4

ISGNT

I_CCSleep

LFM

I_SLP

12.4

13.3

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

11.8

12.0

I_DPRSLP

I_DC4

I_CCDeeper Sleep

7.6

6.7

A

3,4

4

I_CCIntel Enhanced Deeper Sleep

V_CCPower Supply Current Slew Rate at

CPU Package Pin

dI_CC/DT

I_CCA

600

120

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

6.0

2.5

A

10

9

I_CCP

Datasheet

31

Electrical Specifications

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

2.

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

Specified at 100°C Tj.

Specified at the VID voltage.

The I_CCDES(max) specification of 19 A comprehends only Intel Core Duo processor LV HFM frequencies.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7.

Measured at the bulk capacitors on the motherboard.

8.

V_CC, boot tolerance is shown in Figure 3.

9.

This is a steady-state Iccp current specification, which is applicable when both V_CCPand V_CCcore are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_CCcore is low.

10.

11.

12.

Specified at the nominal V_CC

.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

Table 9.

Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage

(ULV) (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1, 2

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

0.85

0.8

1.1

1.0

V

A

1, 2

2, 7, 9

2

1.20

1.05

1.5

0.997

1.425

0.55

0.5

1.102

1.575

0.85

0.8

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCDC4

I_CCDES

V_CCat Deeper Sleep voltage

1, 2, 13

5

V_CCat Intel® Enhanced Deeper Sleep Voltage

I_CCfor Intel® Core™ Duo Processor ULV

Icc for Intel Core Duo Processor ULV

14

Processor

Core Frequency/Voltage

Number

I_CC

U2500

U2400

N/A

1.20 GHz and HFM V_CC

1.06 GHz and HFM V_CC

800 MHz and LFM V_CC

13.9

10.5

A

3, 12

3,4

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

5.4

6.4

I_SGNT

I_CCSleep

LFM

I_SLP

5.3

6.3

3,4

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

4.8

5.4

A

3,4

4

I_DPRSLP

I_CCDeeper Sleep

3.6

32

Datasheet

Electrical Specifications

Table 9.

Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage

(ULV) (Sheet 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_DC4

I_CCCIntel Enhanced Deeper Sleep

3.3

A

4

V_CCPower Supply Current Slew Rate at CPU

Package Pin

dI_CC/DT

I_CCA

600

120

A/µs 6, 8

mA

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPsupply after V_CCStable

6.0

2.5

A

11

10

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and can not be altered. Individual maximum VID values are calibrated during

manufacturing such that two processors at the same frequency may have different settings within the VID

range. Note that this differs from the VID employed by the processor during a power management event

(Thermal Monitor 2, Enhanced Intel SpeedStep technology, or C1E).

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

2.

3.

4.

5.

Specified at 100°C Tj.

Specified at the VID voltage.

The I_CCDES(max) specification of 14A comprehends Intel Core Duo processor ultra low voltage HFM

frequencies.

6.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7.

Reserved.

8.

Measured at the bulk capacitors on the motherboard.

9.

V_CC, boot tolerance is shown in Figure 3.

10.

11.

12.

13.

This is a steady-state Iccp current specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

Specified at the nominal V_CC

.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

Table 10.

Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra

Low Voltage) (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1, 2

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

0.85

0.8

1.1

1.0

V

1, 2

2, 8

2

1.20

1.05

1.5

0.997

1.425

0.55

1.102

1.575

0.85

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCat Deeper Sleep Voltage

1, 2, 12

1, 2

V_CCat Intel Enhanced Deeper Sleep

Voltage

V_CCDC4

I_CCDES

0.50

0.80

8

V

A

I_CCfor Intel® Core™ Solo Processor ULV

5

Datasheet

33

Electrical Specifications

Table 10.

Symbol

Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra

Low Voltage) (Sheet 2 of 2)

Parameter

Min

Typ

Max

Unit

Notes

I_CCfor Intel Core Solo Processor ULV

Processor

Core Frequency/Voltage

Number

I_CC

U1500

U1400

U1300

N/A

1.33 GHz and HFM V_CC

1.20 GHz and HFM V_CC

1.06 GHz and HFM V_CC

800 MHz and LFM V_CC

8

A

3,11

8

6.4

I_CCAuto-Halt & Stop-Grant

I_AH

,

LFM

HFM

3.9

4.6

A

3,4

I_SGNT

I_CCSleep

LFM

I_SLP

3.8

4.5

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

3.3

3.6

I_DPRSLP

I_DC4

I_CCDeeper Sleep

2.4

2.3

A

3,4

4

I_CCIntel Enhanced Deeper Sleep

V_CCPower Supply Current Slew Rate at

CPU Package Pin

dI_CC/DT

I_CCA

600

120

A/µs 6, 7

mA

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

6.0

2.5

A

10

9

ICCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

2.

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

Specified at 100°C Tj.

Specified at the VID voltage.

This specification comprehends Intel Core Duo processor ULV processor HFM frequencies.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7.

Measured at the bulk capacitors on the motherboard.

8.

Vcc, boot tolerance is shown in Figure 5.

9.

This is a steady-state I_CCPcurrent specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

10.

11.

12.

Specified at the nominal V_CC

.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

34

Datasheet

Electrical Specifications

Figure 3.

Active V_CCand I_CCLoadline for Intel Core Duo Processor (SV, LV & ULV) and

Intel Core Solo Processor SV

V_CC[V]

Slope = -2.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V_CCmax {HFM|LFM}

V_{CC, DC}max {HFM|LFM}

10mV= RIPPLE

V_CCnom {HFM|LFM}

V_{CC, DC}min {HFM|LFM}

V_CCmin {HFM|LFM}

+/-V_CCnom * 1.5%

= VR St. Pt. Error 1/

I_CC[A]

0

I_CCmax {HFM|LFM}

Note 1/ V_CCSet Point Error Tolerance is per below:

Tolerance Active Mode VID Code Range

V

--------------- --^C--^C----------------------------------------------------

+/-1.5%

+/-11.5mV

V_CC> 0.7500V (VID 0111100).

V_CC< 0.7500V (VID 0111100)

Datasheet

35

Electrical Specifications

Figure 4.

Deeper Sleep V_CCand I_CCLoadline for Intel Core Duo Processor (SV, LV & ULV)

and Intel Core Solo Processor SV

V_CC-CORE[V]

Slope = -2.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V

_CC-COREmax {Deeper Sleep}

13mV= RIPPLE

for PSI# Asserted

V

_{CC-CORE, DC}max

{Deeper Sleep}

V_CC-COREnom

{Deeper Sleep}

V

_{CC-CORE, DC}min

{Deeper Sleep}

V_CC-COREmin {Deeper Sleep}

+/-V_CC-CORETolerance

= VR St. Pt. Error 1/

I_CC-CORE

[A]

0

I_CC-COREmax

{Deeper Sleep}

Note 1/ Deeper Sleep V_{C C -C O R E}Set Point Error Tolerance is per below :

Tolerance - PSI# Ripple

------------------------------

+/-[(VID*1.5%) - 3 mV]

V_{C C - C O R E}VID Voltage Range

--------------------------------------------------------

V_{C C - C O R E}> 0.7500V

+/-(11.5 mV - 3 mV)

+/- (25 mV - 3 mV)

0.7500V < V_{C C -C O R E}< 0.5000V

0.5000V < V_{C C -C O R E}< 0.4125V

NOTE: For low voltage, if PSI# is not asserted, then the 13-mV ripple allowance becomes 10 mV.

36

Datasheet

Electrical Specifications

Figure 5.

Active V_CCand I_CCLoadline for Intel Core Solo Processor ULV

V_CC-CORE[V]

Slope = -5.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V_CC-COREmax {HFM|LFM}

V_{CC-CORE, DC}max {HFM|LFM}

10mV= RIPPLE

V_CC-COREnom {HFM|LFM}

V_{CC-CORE, DC}min {HFM|LFM}

V_CC-COREmin {HFM|LFM}

+/-V_CC-CORETolerance

= VR St. Pt. Error 1/

0

I_CC-COREmax

{HFM|LFM}

Note 1/ V_CC-CORESet Point Error Tolerance is per below:

Tolerance V_CC-COREVID Voltage Range

--------------- --------------------------------------------------------

+/-1.5% V_CC-CORE> 0.7500V

+/-11.5mV 0.75000V < V_CC-CORE< 0.5000V

Datasheet

37

Electrical Specifications

Figure 6.

Deeper Sleep V_CCand I_CCLoadline for Intel Core Solo Processor ULV

V_CC-CORE[V]

Slope = -5.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V

_CC-COREmax {Deeper Sleep}

_{CC-CORE, DC}max

{Deeper Sleep}

V

10 mV= RIPPLE

V_CC-COREnom

{Deeper Sleep}

V_{CC-CORE, DC}min

{Deeper Sleep}

V_CC-COREmin {Deeper Sleep}

+/-V_CC-CORETolerance

=VRSt. Pt. Error 1/

I_CC-CORE

[A]

0

I_CC-COREmax

{Deeper Sleep}

Note 1/ Deeper Sleep V_CC-CORESet Point Error Tolerance is per below:

Tolerance V_CC-COREVID Voltage Range

------------------------------ --------------------------------------------------------

+/- (VID*1.5%)

+/- 11.5 mV

+/- 25 mV

V_CC-CORE> 0.7500V

0.7500V < V_CC-CORE< 0.5000V

0.5000V < V_CC-CORE< 0.4125V

38

Datasheet

Electrical Specifications

Table 11.

Symbol

FSB Differential BCLK Specifications

Parameter

Min

Typ

Max

Unit

Notes¹

V_IL

Input Low Voltage

Input High Voltage

Crossing Voltage

0

V

V_IH

0.660

0.25

0.710

0.35

0.85

0.55

V_CROSS

ΔV_CROSS

V_TH

V

2

6

3

4

5

Range of Crossing Points

Threshold Region

0.14

V

V_CROSS-0.100

0.95

V_CROSS+0.100

± 100

V

I_LI

Input Leakage Current

Pad Capacitance

µA

pF

Cpad

1.2

1.45

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3.

Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver

switches. It includes input threshold hysteresis.

4.

5.

6.

For Vin between 0 V and V_IH.

Cpad includes die capacitance only. No package parasitics are included.

ΔV_CROSSis defined as the total variation of all crossing voltages as defined in note 2.

Table 12.

Symbol

AGTL+ Signal Group DC Specifications

Parameter

I/O Voltage

Min

Typ

Max

Unit

Notes¹

V_CCP

GTLREF

V_IH

0.997

1.05

1.102

V

Reference Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Termination Resistance

Buffer on Resistance

Input Leakage Current

Pad Capacitance

2/3 V_CCP

6

3,6

2,4

6

GTLREF+0.1

-0.1

V_CCP+0.1

V_IL

0

GTLREF-0.1

V_OH

R_TT

V_CCP

55

50

61

Ω

7,10

5

R_ON

I_LI

22.3

25.5

28.7

± 100

2.75

Ω

µA

pF

8

Cpad

1.8

2.3

9

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

_ILis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.

_IHis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

_IHand V_OHmay experience excursions above V_CCP. However, input signal drivers must comply with the

V

3.

4.

V

signal quality specifications.

5.

6.

This is the pull-down driver resistance.

GTLREF should be generated from V_CCPwith a 1% tolerance resistor divider. Tolerance of resistor divider

decides the tolerance of GTLREF. The V_CCPreferred to in these specifications is the instantaneous V_CCP

.

7.

R_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver.

8.

Specified with on die R_TTand R_ONare turned off.

9.

10.

Cpad includes die capacitance only. No package parasitics are included.

This spec applies to all AGTL+ signals except for PREQ#. R_TTfor PREQ# is between 1.5 kΩ to 6.0 kΩ.

Datasheet

39

Electrical Specifications

.

Table 13.

CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min

Typ

Max

Unit Notes¹

V_CCP

V_IL

1.0

-0.1

0.7

-0.1

0.9

1.3

1.05

0.0

1.10

0.33

1.20

0.11

1.20

4.1

V

Input Low Voltage CMOS

Input High Voltage

V

2, 3

2

V_IH

1.05

0

V_OL

Output Low Voltage

V

2

V_OH

I_OL

Output High Voltage

Output Low Current

Output High Current

Input Leakage Current

Pad Capacitance

V_CCP

V

2

mA

µA

pF

4

I_OH

4.1

5

I_LI

±100

2.75

1.45

6

Cpad1

Cpad2

1.8

2.3

1.2

7

Pad Capacitance for CMOS Input

0.95

8

NOTES:

1.

2.

3.

4.

5.

6.

7.

8.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_CCPreferred to in these specifications refers to instantaneous V_CCP

Reserved.

Measured at 0.1*V_CCP

.

Measured at 0.9*V_CCP

.

For Vin between 0 V and V_CCP. Measured when the driver is tristated.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#,PWRGOOD. No package parasitics are included.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

Table 14.

Symbol

Open Drain Signal Group DC Specifications

Parameter

Min

Typ

Max

Unit Notes¹

V_OH

V_OL

Output High Voltage

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

1.0

0

1.05

1.10

0.20

50

V

3

I_OL

11.40

mA

µA

pF

2

4

5

I_Leak

Cpad

±200

2.75

1.8

2.3

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2*V_CCP

_OHis determined by value of the external pullup resistor to V_CCP. Please contact your Intel representative

.

V

for details.

4.

5.

For Vin between 0 V and V_OH.

Cpad includes die capacitance only. No package parasitics are included.

§

40

Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin

Information

4.1

Package Mechanical Specifications

The Intel Core Duo processor and Intel Core Solo processor are available in 478-pin

Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions

are shown in Figure 7 through Figure 10. Table 15 (two sheets) shows a top-view of

package pin-out with their functionalities.

Warning:

The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors

are electrically conductive, care should be taken to avoid contacting the capacitors with

other electrically conductive materials on the motherboard. Doing so may short the

capacitors, and possibly damage the device or render it inactive.

4.1.1

Package Mechanical Drawings

Different views showing all pertinent dimensions of the Micro-FCPGA package are

shown in Figure 7 and continued in Figure 8. Views and pertinent dimensions for Micro-

FCBGA package are shown in Figure 9 and continued in Figure 10.

Datasheet

41

Package Mechanical Specifications and Pin Information

Figure 7.

Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

42

Datasheet

Package Mechanical Specifications and Pin Information

Figure 8.

Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

Datasheet

43

Package Mechanical Specifications and Pin Information

Figure 9.

Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)

44

Datasheet

Package Mechanical Specifications and Pin Information

Figure 10.

Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)

Datasheet

45

Package Mechanical Specifications and Pin Information

4.1.2

4.1.3

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-

out zone requirements. A thermal and mechanical solution design must not intrude into

the required keep-out zones. Decoupling capacitors are typically mounted in the keep-

out areas. The location and quantity of the capacitors may change, but will remain

within the component keep-in. See Figure 7 and Figure 9 for keep-out zones.

Package Loading Specifications

Maximum mechanical package loading specifications are given in Figure 7 and Figure 9.

These specifications are static compressive loading in the direction normal to the

processor. This maximum load limit should not be exceeded during shipping conditions,

standard use condition, or by thermal solution. In addition, there are additional load

limitations against transient bend, shock, and tensile loading. These limitations are

more platform specific, and should be obtained by contacting your field support.

Moreover, the processor package substrate should not be used as a mechanical

reference or load-bearing surface for thermal and mechanical solution.

4.1.4

Processor Mass Specifications

The typical mass of the processor is given in Figure 7 and Figure 9. This mass includes

all the components that are included in the package.

46

Datasheet

Package Mechanical Specifications and Pin Information

4.2

Processor Pinout and Pin List

Table 15 shows the top view pinout of the processor. The pin list arranged in two

different formats is shown in the following pages.

Table 15.

The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 1 of 2)

1

2

3

4

5

6

7

8

9

10

11

12

13

A

SMI#

INIT#

VSS

FERR#

DPSLP#

A20M#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

A

B

C

RESET#

RSVD

VSS

LINT1

IGNNE

#

THERM

TRIP#

RSVD

VSS

LINT0

VSS

VCC

VSS

VCC

VSS

C

D

E

STPCLK

#

PWRGO

OD

D

E

VSS

RSVD

BNR#

VSS

SLP#

DPRSTP

#

DBSY#

HITM#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

F

BR0#

VSS

RS[0]#

RS[2]#

RS[1]#

VSS

RSVD

HIT#

F

G

TRDY#

BPRI#

G

REQ[1]

#

H

J

ADS#

A[9]#

VSS

LOCK#

A[3]#

VSS

DEFER#

VSS

VCCP

VSS

H

J

REQ[3]

#

VSS

REQ[2]

#

REQ[0]

#

K

L

A[6]#

K

L

ADSTB[

0]#

REQ[4]

#

A[13]#

VSS

A[4]#

M

N

P

R

T

A[7]#

VSS

A[8]#

A[12]#

VSS

A[5]#

A[10]#

VSS

RSVD

VSS

RSVD

VCCP

VSS

M

N

P

R

T

A[15]#

A[16]#

VSS

A[14]#

A[24]#

VSS

A[11]#

VSS

A[19]#

A[26]#

VSS

VCCP

VSS

RSVD

A[23]#

A[25]#

A[18]#

U

COMP[2]

A[21]#

U

ADSTB

[1]#

V

COMP[3]

VSS

RSVD

VSS

VCCP

V

W

Y

VSS

A[31]#

RSVD

VSS

A[30]#

A[17]#

VSS

A[27]#

VSS

A[29]#

RSVD

VSS

A[28]#

A[22]#

VSS

A[20]#

VSS

W

Y

AA

AB

RSVD

TDO

TDI

VCC

VSS

VCC

VSS

VCC

VSS

AA

AB

RSVD

TMS

TRST#

BPM[3]

#

AC

AD

AE

AF

PREQ#

BPM[2]#

VSS

PRDY#

VSS

TCK

VSS

VID[0]

PSI#

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AC

AD

AE

AF

BPM[1]

#

BPM[0]

#

VSS

SENSE

VID[6]

VID[4]

VSS

VID[2]

VCC

SENSE

RSVD

VID[5]

VSS

VID[3]

VID[1]

VSS

VCC

VSS

VCC

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

Datasheet

47

Package Mechanical Specifications and Pin Information

Table 16.

The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 2 of 2)

14

15

16

17

18

19

20

21

22

23

24

THRMDA

VSS

25

THRMDC

RSVD

VSS

26

A

B

C

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BCLK[1]

VSS

BCLK[0]

BSEL[0]

VSS

A

B

C

VCC

BSEL[1]

RSVD

VCCA

TEST1

DBR#

BSEL[2]

RSVD

PROC

HOT#

D

VCC

VSS

VCC

VSS

IERR#

RSVD

VSS

DPWR#

TEST2

VSS

D

E

F

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DRDY#

VCCP

VSS

D[0]#

VSS

D[7]#

D[4]#

VSS

D[1]#

D[9]#

VSS

D[6]#

VSS

D[2]#

D[13]#

VSS

E

F

G

H

DSTBP[0]#

D[3]#

VSS

D[5]#

D[15]#

G

H

DSTBN[0]#

D[12]#

DINV[0

]#

J

VCCP

VSS

D[11]#

D[10]#

VSS

J

K

L

VCCP

VSS

D[14]#

D[21]#

VSS

D[8]#

VSS

D[17]#

D[20]#

VSS

K

L

D[22]#

D[29]#

DINV[1

]#

M

VCCP

VSS

D[23]#

DSTBN[1]#

VSS

M

N

P

VCCP

VSS

D[16]#

D[25]#

VSS

D[31]#

VSS

DSTBP[1]#

D[24]#

VSS

N

P

D[26]#

D[18]#

COMP

[0]

R

T

VCCP

VSS

RSVD

D[19]#

VSS

D[28]#

D[27]#

VSS

R

T

D[30]#

D[38]#

VSS

COMP

[1]

U

D[39]#

D[37]#

U

V

W

Y

VCCP

VSS

DINV[2]#

VSS

D[34]#

DSTBN[2]#

VSS

D[35]#

VSS

V

W

Y

D[41]#

D[45]#

D[36]#

D[42]#

DSTBP[2]#

D[44]#

A

AA

VSS

VCC

VSS

VCC

VSS

VCC

D[51]#

VSS

D[32]#

D[47]#

VSS

D[43]#

VSS

A

B

AB

AC

VCC

VSS

VCC

VSS

VCC

VSS

D[52]#

VSS

D[50]#

D[48]#

VSS

D[33]#

VSS

D[40]#

D[53]#

VSS

DINV[3

]#

D[49]#

D[46]# AC

A

D

A

GTLREF

D

D[54]#

D[59]#

DSTBN[3]#

D[57]#

AE

AF

VSS

VCC

14

VCC

15

VSS

16

VCC

17

VCC

18

VSS

19

VCC

20

D[58]#

VSS

D[55]#

D[62]#

22

VSS

D[56]#

23

DSTBP[3]#

VSS

D[60]#

D[61]#

25

VSS

D[63]#

26

AE

AF

21

24

48

Datasheet

Package Mechanical Specifications and Pin Information

4.3

Alphabetical Signals Reference

Table 17.

Signal Description (Sheet 1 of 9)

Name

Type

Description

A[31:3]# (Address) define a 2³²-byte physical memory address

space. In sub-phase 1 of the address phase, these pins transmit the

address of a transaction. In sub-phase 2, these pins transmit

transaction type information. These signals must connect the

appropriate pins of both agents on the Intel® Core™ Duo processor

and the Intel® Core™ Solo processor FSB. A[31:3]# are source

synchronous signals and are latched into the receiving buffers by

ADSTB[1:0]#. Address signals are used as straps which are

sampled before RESET# is deasserted.

Input/

Output

A[31:3]#

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address

wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only

supported in real mode.

A20M#

Input

A20M# is an asynchronous signal. However, to ensure recognition

of this signal following an Input/Output write instruction, it must be

valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction.

Input/

Output

ADS#

Address strobes are used to latch A[31:3]# and REQ[4:0]# on their

rising and falling edges. Strobes are associated with signals as

shown below.

Associated

Input/

Output

Signals

Strobe

ADSTB[1:0]#

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[31:17]#

ADSTB[1]#

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All FSB agents must receive these signals to drive their

outputs and latch their inputs.

BCLK[1:0]

BNR#

Input

All external timing parameters are specified with respect to the

rising edge of BCLK0 crossing V_CROSS

.

BNR# (Block Next Request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus

stall, the current bus owner cannot issue any new transactions.

Input/

Output

Datasheet

49

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 2 of 9)

Name

Type

Description

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor which indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[3:0]# should connect the

appropriate pins of all processor FSB agents.This includes debug or

performance monitoring tools.

Output

BPM[2:1]#

BPM[3,0]#

Input/

Output

Please contact your Intel representative for more detailed

information.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the FSB. It must connect the appropriate pins of both FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes

the other agent to stop issuing new requests, unless such requests

are part of an ongoing locked operation. The priority agent keeps

BPRI# asserted until all of its requests are completed, then releases

the bus by deasserting BPRI#.

BPRI#

Input

BR0# is used by the processor to request the bus. The arbitration is

done between the processor (Symmetric Agent) and the Mobile

Intel® 945 Express Chipset family (High Priority Agent).

Input/

Output

BR0#

BSEL[2:0] (Bus Select) are used to select the processor input clock

frequency. Table 3 defines the possible combinations of the signals

and the frequency associated with each combination. The required

frequency is determined by the processor, chipset and clock

synthesizer. All agents must operate at the same frequency. The

processor operates at 667-MHz or 533-MHz system bus frequency

(166-MHz or 133-MHz BCLK[1:0] frequency, respectively).

BSEL[2:0]

COMP[3:0]

Output

Analog

COMP[3:0] must be terminated on the system board using

precision (1% tolerance) resistors. Please contact your Intel

representative for more implementation details.

50

Datasheet

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 3 of 9)

Name

Type

Description

D[63:0]# (Data) are the data signals. These signals provide a 64-

bit data path between the FSB agents, and must connect the

appropriate pins on both agents. The data driver asserts DRDY# to

indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the

falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of

16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals to

data strobes and DINV#.

Quad-Pumped Signal Groups

Input/

Output

D[63:0]#

Data

Group

DSTBN#/

DSTBP#

DINV#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

DBR# (Data Bus Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a

debug port interposer so that an in-target probe can drive system

reset. If a debug port is implemented in the system, DBR# is a no

connect in the system. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the FSB to indicate that the data bus is in use. The

data bus is released after DBSY# is deasserted. This signal must

connect the appropriate pins on both FSB agents.

Input/

Output

DBSY#

DEFER#

DEFER# is asserted by an agent to indicate that a transaction

cannot be guaranteed in-order completion. Assertion of DEFER# is

normally the responsibility of the addressed memory or Input/

Output agent. This signal must connect the appropriate pins of both

FSB agents.

Input

Datasheet

51

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 4 of 9)

Name

Type

Description

DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals. The DINV[3:0]#

signals are activated when the data on the data bus is inverted. The

bus agent will invert the data bus signals if more than half the bits,

within the covered group, would change level in the next cycle.

DINV[3:0]# Assignment to Data Bus

Input/

Output

Data Bus

Bus Signal

DINV[3:0]#

Signals

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DPRSTP# when asserted on the platform causes the processor to

transition from the Deep Sleep State to the Deeper Sleep state. In

order to return to the Deep Sleep State, DPRSTP# must be

deasserted. DPRSTP# is driven by the Intel® ICH7M chipset.

DPRSTP#

Input

DPSLP# when asserted on the platform causes the processor to

transition from the Sleep State to the Deep Sleep state. In order to

return to the Sleep State, DPSLP# must be deasserted. DPSLP# is

driven by the ICH7M chipset.

DPSLP#

DPWR#

DRDY#

Input

DPWR# is a control signal from the Mobile Intel 945 Express

Chipset family used to reduce power on the processor data bus

input buffers.

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of both FSB agents.

Input/

Output

Data strobe used to latch in D[63:0]#.

Associated

Signals

Strobe

Input/

Output

D[15:0]#, DINV[0]#

DSTBN[0]#

DSTBN[3:0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#

Data strobe used to latch in D[63:0]#.

Associated

Signals

Strobe

Input/

Output

D[15:0]#, DINV[0]#

DSTBP[0]#

DSTBP[3:0]#

D[31:16]#, DINV[1]# DSTBP[1]#

D[47:32]#, DINV[2]# DSTBP[2]#

D[63:48]#, DINV[3]# DSTBP[3]#

52

Datasheet

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 5 of 9)

Name

Type

Description

FERR# (Floating-point Error)PBE#(Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating point

when the processor detects an unmasked floating-point error.

FERR# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using

MS-DOS*-type floating-point error reporting. When STPCLK# is

asserted, an assertion of FERR#/PBE# indicates that the processor

has a pending break event waiting for service. The assertion of

FERR#/PBE# indicates that the processor should be returned to the

Normal state. When FERR#/PBE# is asserted, indicating a break

event, it will remain asserted until STPCLK# is deasserted.

Assertion of PREQ# when STPCLK# is active will also cause an

FERR# break event.

FERR#/PBE#

Output

For additional information on the pending break event functionality,

including identification of support of the feature and enable/disable

information, refer to Volume 3 of the Intel ^®Architecture Software

Developer’s Manual and AP-485, Intel ^®Processor Identification and

CPUID Instruction Application Note.

For termination requirements please contact your Intel

representative.

GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF should be set at 2/3 V_CCP. GTLREF is used by the AGTL+

receivers to determine if a signal is a logical 0 or logical 1. Please

contact your Intel representative for more information regarding

GTLREF implementation.

GTLREF

Input

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT#

and HITM# together to indicate that it requires a snoop stall, which

can be continued by reasserting HIT# and HITM# together.

HIT#

HITM#

Input/

Output

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may optionally

be converted to an external error signal (e.g., NMI) by system core

logic. The processor will keep IERR# asserted until the assertion of

RESET#, BINIT#, or INIT#.

IERR#

Output

For termination requirements please contact your Intel

representative.

IGNNE# (Ignore Numeric Error) is asserted to force the processor

to ignore a numeric error and continue to execute noncontrol

floating-point instructions. If IGNNE# is deasserted, the processor

generates an exception on a noncontrol floating-point instruction if

a previous floating-point instruction caused an error. IGNNE# has

no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition

of this signal following an Input/Output write instruction, it must be

valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

Datasheet

53

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 6 of 9)

Name

Type

Description

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point

registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an Input/Output Write

instruction, it must be valid along with the TRDY# assertion of the

corresponding Input/Output Write bus transaction. INIT# must

connect the appropriate pins of both FSB agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST).

For termination requirements please contact your Intel

representative.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1

becomes NMI, a nonmaskable interrupt. INTR and NMI are

backward compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both

FSB agents. For a locked sequence of transactions, LOCK# is

asserted from the beginning of the first transaction to the end of

the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of

the FSB, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the FSB

throughout the bus locked operation and ensure the atomicity of

lock.

Probe Ready signal used by debug tools to determine processor

debug readiness.

PRDY#

PREQ#

Output

Input

Please contact your Intel representative for more implementation

details.

Probe Request signal used by debug tools to request debug

operation of the processor.

Please contact your Intel representative for more implementation

details.

54

Datasheet

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 7 of 9)

Name

Type

Description

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has

been activated, if enabled. As an input, assertion of PROCHOT# by

the system will activate the TCC, if enabled. The TCC will remain

active until the system deasserts PROCHOT#.

Input/

Output

PROCHOT#

By default PROCHOT# is configured as an output only. Bidirectional

PROCHOT# must be enabled via the BIOS.

For termination requirements please contact your Intel

representative.

This signal may require voltage translation on the motherboard.

Please contact your Intel representative for more details.

Processor Power Status Indicator signal. This signal is asserted

when the processor is in a normal state (HFM and LFM) and lower

state (Deep Sleep and Deeper Sleep).

PSI#

Output

Please contact your Intel representative for more details on the

PSI# signal.

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. ‘Clean’

implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must

then transition monotonically to a high state.

PWRGOOD

Input

The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It

should be driven high throughout boundary scan operation.

For termination requirements please contact your Intel

representative.

REQ[4:0]# (Request Command) must connect the appropriate pins

of both FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are

source synchronous to ADSTB[0]#.

Input/

Output

REQ[4:0]#

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at

least two milliseconds after VCC and BCLK have reached their

proper specifications. On observing active RESET#, both FSB

agents will deassert their outputs within two clocks. All processor

straps must be valid within the specified setup time before RESET#

is deasserted.

RESET#

Input

For termination requirements please contact your Intel

representative and implementation details. There is a 55 Ω

(nominal) on die pull-up resistor on this signal.

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins of both FSB agents.

RS[2:0]#

RSVD

These pins are RESERVED and must be left unconnected on the

board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use. Please

contact your Intel representative for more details.

Reserved

/No

Connect

Datasheet

55

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 8 of 9)

Name

Type

Description

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the

processor stops providing internal clock signals to all units, leaving

only the Phase-Locked Loop (PLL) still operating. Processors in this

state will not recognize snoops or interrupts. The processor will

recognize only assertion of the RESET# signal, deassertion of SLP#,

and removal of the BCLK input while in Sleep state. If SLP# is

deasserted, the processor exits Sleep state and returns to Stop-

Grant state, restarting its internal clock signals to the bus and

processor core units. If DPSLP# is asserted while in the Sleep state,

the processor will exit the Sleep state and transition to the Deep

Sleep state.

SLP#

Input

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt, the

processor saves the current state and enter System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

SMI#

Input

If SMI# is asserted during the deassertion of RESET# the processor

will tristate its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to

enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock

signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted,

the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus

clock; STPCLK# is an asynchronous input.

STPCLK#

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TCK

TDI

Input

Please contact your Intel representative for termination

requirements and implementation details.

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

Please contact your Intel representative for termination

requirements and implementation details.

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification

support.

TDO

Output

Please contact your Intel representative for termination

requirements and implementation details.

TEST1 must have a stuffing option of separate pull-down resistor to

V_SS

.

TEST1

TEST2

Input

Please contact your Intel representative for more detailed

information.

TEST2 must have a 51 Ω ±5% pull-down resistor to V_SS. Please

contact your Intel representative for more details.

THERMDA

THERMDC

Other

Thermal Diode Anode.

Thermal Diode Cathode.

56

Datasheet

Package Mechanical Specifications and Pin Information

Table 17.

Signal Description (Sheet 9 of 9)

Name

Type

Description

The processor protects itself from catastrophic overheating by use

of an internal thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there are no false

trips. The processor will stop all execution when the junction

temperature exceeds approximately 125°C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

THERMTRIP#

Output

For termination requirements please contact your Intel

representative.

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools.

TMS

Input

Please contact your Intel representative for termination

requirements and implementation details.

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

TRDY#

TRST#

Please contact your Intel representative for termination

requirements and implementation details.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

Please contact your Intel representative for termination

requirements and implementation details.

V_CC

Input

Processor core power supply.

V_CCAprovides isolated power for the internal processor core PLL’s.

Please contact your Intel representative for complete

implementation details.

V_CCA

V_CCP

Processor I/O Power Supply.

V_CCSENSEtogether with V_SSSENSEare voltage feedback signals to

IMVP6 that control the 2.1-mΩ loadline at the processor die. It

should be used to sense voltage near the silicon with little noise.

Please contact your Intel Representative for more information

regarding termination and routing recommendations.

V_CCSENSE

VID[6:0]

V_SSSENSE

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (V_CC). Unlike some previous generations

of processors, these are CMOS signals that are driven by the Intel

Core Duo processor and Intel Core Solo processor. The voltage

supply for these pins must be valid before the VR can supply V_CCto

the processor. Conversely, the VR output must be disabled until the

voltage supply for the VID pins becomes valid. The VID pins are

needed to support the processor voltage specification variations.

See Table 2 for definitions of these pins. The VR must supply the

voltage that is requested by the pins, or disable itself.

V

_SSSENSEtogether with V_CCSENSEare voltage feedback signals to

Intel® MVP6 that control the 2.1-mΩ loadline at the processor die.

It should be used to sense ground near the silicon with little noise.

Please contact your Intel Representative for more information

regarding termination and routing recommendations.

§

Datasheet

57

Package Mechanical Specifications and Pin Information

58

Datasheet

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Number

Signal

Buffer Type

Direction

Number

Signal

Buffer Type

Direction

Source

Synch

Input/

Output

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

Y5

Source

Synch

Input/

Output

A[3]#

J4

Source

Synch

Input/

Output

U2

R4

T5

Source

Synch

Input/

Output

A[4]#

L4

M3

K5

M1

N2

J1

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[5]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[6]#

Source

Synch

Input/

Output

T3

Source

Synch

Input/

Output

A[7]#

Source

Synch

Input/

Output

W3

W5

Y4

Source

Synch

Input/

Output

A[8]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[9]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

N3

P5

P2

L1

P4

P1

R1

Y2

U5

R3

W6

U4

Source

Synch

Input/

Output

W2

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[31]#

A20M#

ADS#

Y1

A6

H1

Source

Synch

Input/

Output

CMOS

Input

Common

Clock

Input/

Output

Source

Synch

Input/

Output

ADSTB[0]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

L2

ADSTB[1]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

V4

BCLK[0]

BCLK[1]

A22

A21

Bus Clock

Input

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Common

Clock

Input/

Output

BNR#

E2

Source

Synch

Input/

Output

Common

Clock

Input/

Output

BPM[0]#

BPM[1]#

BPM[2]#

AD4

AD3

AD1

Source

Synch

Input/

Output

Common

Clock

Output

Source

Synch

Input/

Output

Common

Clock

Source

Synch

Input/

Output

Datasheet

59

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

Common

Clock

Input/

Output

Source

Synch

Input/

Output

BPM[3]#

BPRI#

BR0#

AC4

G5

F1

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

J24

Common

Clock

Source

Synch

Input/

Output

Input

J23

Common

Clock

Input/

Output

Source

Synch

Input/

Output

H26

F26

K22

H25

N22

K25

P26

R23

L25

L22

L23

M23

P25

P22

P23

T24

R24

BSEL[0]

BSEL[1]

BSEL[2]

B22

B23

C21

CMOS

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Input/

Output

Source

Synch

Input/

Output

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

R26

U26

U1

Power/Other

Input/

Output

Source

Synch

Input/

Output

Input/

Output

Source

Synch

Input/

Output

Input/

Output

Source

Synch

Input/

Output

V1

Source

Synch

Input/

Output

Source

Synch

Input/

Output

E22

F24

E26

H22

F23

G25

E25

E23

K24

G24

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[1]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[2]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[3]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[4]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[5]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[6]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[7]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[8]#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[9]#

60

Datasheet

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[29]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

L26

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

AC22

AC23

AB22

AA21

AB21

AC25

AD20

AE22

AF23

AD24

AE21

AD21

AE25

AF25

AF22

Source

Synch

Input/

Output

Source

Synch

Input/

Output

T25

Source

Synch

Input/

Output

Source

Synch

Input/

Output

N24

AA23

AB24

V24

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

V26

Source

Synch

Input/

Output

Source

Synch

Input/

Output

W25

U23

U25

U22

AB25

W22

Y23

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Source

Synch

Input/

Output

AA26

Y26

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[63]#

DBR#

AF26

C20

E1

Source

Synch

Input/

Output

CMOS

Output

Y22

Common

Clock

Input/

Output

DBSY#

Source

Synch

Input/

Output

AC26

AA24

Common

Clock

DEFER#

H5

Input

Source

Synch

Input/

Output

Source

Synch

Input/

Output

DINV[0]#

J26

Datasheet

61

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

Source

Synch

Input/

Output

LINT0

LINT1

C6

B4

CMOS

Input

DINV[1]#

DINV[2]#

DINV[3]#

M26

V23

Source

Synch

Input/

Output

Common

Clock

Input/

Output

LOCK#

PRDY#

PREQ#

H4

Source

Synch

Input/

Output

AC20

Common

Clock

AC2

AC1

D21

Output

Input

DPRSTP#

DPSLP#

E5

B5

CMOS

Input

Common

Clock

Common

Clock

PROCHOT

#

Input/

Output

DPWR#

DRDY#

D24

F21

Input

Open Drain

Common

Clock

Input/

Output

PSI#

AE6

D6

CMOS

Output

Input

PWRGOOD

DSTBN[0]

#

Source

Synch

Input/

Output

H23

M24

W24

AD23

G22

N25

Y25

Source

Synch

Input/

Output

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

RESET#

RS[0]#

K3

H2

K2

J3

DSTBN[1]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

DSTBN[2]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

DSTBN[3]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

DSTBP[0]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

L5

B1

F3

F4

G3

DSTBP[1]

#

Source

Synch

Input/

Output

Common

Clock

Input

DSTBP[2]

#

Source

Synch

Input/

Output

Common

Clock

DSTBP[3]

#

Source

Synch

Input/

Output

AE24

Common

Clock

RS[1]#

FERR#

A5

Open Drain

Output

Input

Common

Clock

RS[2]#

GTLREF

AD26

Power/Other

Common

Clock

Input/

Output

RSVD

D2

Reserved

HIT#

G6

E4

F6

Common

Clock

Input/

Output

HITM#

D3

C1

IERR#

IGNNE#

INIT#

D20

C4

Open Drain

CMOS

Output

Input

AF1

D22

B3

CMOS

62

Datasheet

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

RSVD

SLP#

C23

C24

AA1

AA4

AB2

AA3

M4

Reserved

CMOS

VCC

AA20

AF20

AE20

AB18

AB17

AA18

AA17

AD18

AD17

AC18

AC17

AF18

AF17

AE18

AE17

AB15

AA15

AD15

AC15

AF15

AE15

AB14

AA13

AD14

AC13

AF14

AE13

AB12

AA12

AD12

Power/Other

N5

T2

V3

B2

C3

T22

B25

D7

Input

Output

SMI#

STPCLK#

TCK

A3

CMOS

D5

CMOS

AC5

AA6

AB3

C26

D25

A24

A25

CMOS

TDI

CMOS

TDO

Open Drain

Test

TEST1

TEST2

THERMDA

THERMDC

Test

Power/Other

THERMTRI

P#

C7

Open Drain

CMOS

Output

Input

TMS

AB5

G2

Common

Clock

TRDY#

TRST#

VCC

AB6

CMOS

AB20

Power/Other

Datasheet

63

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

VCC

AC12

AF12

AE12

AB10

AB9

AA10

AA9

AD10

AD9

AC10

AC9

AF10

AF9

Power/Other

VCC

C17

F18

F17

E18

E17

B15

A15

D15

C15

F15

E15

B14

A13

D14

C13

F14

E13

B12

A12

D12

C12

F12

E12

B10

B9

Power/Other

AE10

AE9

AB7

AA7

AD7

AC7

B20

A20

F20

E20

B18

B17

A18

A10

A9

A17

D18

D17

C18

D10

D9

C10

64

Datasheet

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

VCC

C9

Power/Other

CMOS

VID[3]

VID[4]

VID[5]

VID[6]

VSS

AF4

CMOS

Output

VCC

F10

F9

AE3

CMOS

VCC

AF2

CMOS

VCC

E10

E9

AE2

CMOS

VCC

AB26

AA25

AD25

AE26

AB23

AC24

AF24

AE23

AA22

AD22

AC21

AF21

AB19

AA19

AD19

AC19

AF19

AE19

AB16

AA16

AD16

AC16

AF16

AE16

AB13

AA14

Power/Other

VCC

B7

VCC

A7

VCC

F7

VCC

E7

VCCA

VCCP

VCCSENSE

VID[0]

VID[1]

VID[2]

B26

K6

J6

M6

N6

T6

R6

K21

J21

M21

N21

T21

R21

V21

W21

V6

G21

AF7

AD6

AF5

AE5

Output

CMOS

Datasheet

65

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

VSS

AD13

AC14

AF13

AE14

AB11

AA11

AD11

AC11

AF11

AE11

AB8

AA8

AD8

AC8

AF8

Power/Other

VSS

F5

E6

H6

J5

Power/Other

M5

L6

P6

R5

V5

U6

Y6

A4

D4

E3

H3

G4

K4

L3

P3

N4

T4

U3

Y3

W4

D1

C2

F2

G1

K1

J2

AE8

AA5

AD5

AC6

AF6

AB4

AC3

AF3

AE4

AB1

AA2

AD2

AE1

B6

C5

66

Datasheet

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

Number

Buffer Type

VSS

M2

Power/Other

VSS

B13

A14

D13

C14

F13

E14

B11

A11

D11

C11

F11

E11

B8

Power/Other

N1

T1

R2

V2

W1

A26

D26

C25

F25

B24

A23

D23

E24

B21

C22

F22

E21

B19

A19

D19

C19

F19

E19

B16

A16

D16

C16

F16

E16

A8

D8

C8

F8

E8

G26

K26

J25

M25

N26

T26

R25

V25

W26

H24

G23

K23

Datasheet

67

Package Mechanical Specifications and Pin Information

Table 18.

Pin Name

Pin Listing by Pin Name

Signal

Direction

Number

Buffer Type

VSS

VSSSENSE

L24

P24

N23

T23

U24

Y24

W23

H21

J22

Power/Other

M22

L21

P21

R22

V22

U21

Y21

AE7

Output

68

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Buffer Type

Number

Pin Name

Direction

Buffer Type

AA7

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

Power/other

Power/Other

A3

SMI#

VSS

CMOS

Input

AA8

A4

Power/Other

Open Drain

CMOS

AA9

A5

FERR#

A20M#

VCC

Output

Input

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

A6

A7

Power/Other

Bus Clock

A8

VSS

A9

VCC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

AA1

AA2

AA3

AA4

AA5

AA6

VCC

VSS

VCC

VSS

VCC

VSS

Source

Synch

Input/

Output

AA21

AA22

AA23

D[51]#

VSS

VCC

Power/Other

VCC

Source

Synch

Input/

Output

D[32]#

VSS

VCC

Source

Synch

Input/

Output

AA24

AA25

AA26

D[47]#

VSS

BCLK[1]

BCLK[0]

VSS

Input

Power/Other

Bus Clock

Source

Synch

Input/

Output

Power/Other

Reserved

D[43]#

THERMDA

THERMDC

VSS

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

VSS

Power/Other

Reserved

RSVD

TDO

VSS

Open Drain

Power/Other

CMOS

Output

RSVD

VSS

Power/Other

Reserved

TMS

TRST#

VCC

Input

RSVD

VSS

CMOS

Reserved

Power/Other

CMOS

VSS

TDI

Input

Datasheet

69

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

AB9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

Source

Synch

Input/

Output

AC20

AC21

AC22

DINV[3]#

VSS

Power/Other

Source

Synch

Input/

Output

AB21

D[52]#

Source

Synch

Input/

Output

D[48]#

Source

Synch

Input/

Output

AB22

AB23

AB24

D[50]#

VSS

Source

Synch

Input/

Output

AC23

AC24

AC25

D[49]#

VSS

Power/Other

Source

Synch

Input/

Output

D[33]#

Source

Synch

Input/

Output

D[53]#

Source

Synch

Input/

Output

AB25

AB26

AC1

D[40]#

VSS

Source

Synch

Input/

Output

AC26

D[46]#

Power/Other

Common

Clock

AD1

AD2

AD3

BPM[2]#

VSS

Output

Common

Clock

PREQ#

Input

Power/Other

Common

Clock

AC2

AC3

AC4

PRDY#

VSS

Output

Common

Clock

BPM[1]#

Output

Power/Other

Common

Clock

Input/

Output

AD4

BPM[0]#

Common

Clock

Input/

Output

BPM[3]#

AD5

AD6

AD7

AD8

AD9

VSS

Power/Other

CMOS

AC5

AC6

AC7

AC8

AC9

TCK

VSS

VCC

VSS

VCC

CMOS

Input

VID[0]

VCC

Output

Power/Other

VSS

VCC

70

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

Source

Synch

Input/

Output

AE21

D[58]#

Source

Synch

Input/

Output

AD20

D[54]#

Source

Synch

Input/

Output

AE22

AE23

AE24

D[55]#

VSS

Source

Synch

Input/

Output

AD21

AD22

AD23

D[59]#

VSS

Power/Other

DSTBP[3]

#

Source

Synch

Input/

Output

DSTBN[3]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

AE25

D[60]#

Source

Synch

Input/

Output

AD24

D[57]#

AE26

AF1

VSS

Power/Other

Reserved

AD25

AD26

AE1

VSS

Power/Other

CMOS

RSVD

VID[5]

VSS

GTLREF

VSS

Input

AF2

CMOS

Output

AF3

Power/Other

CMOS

AE2

VID[6]

VID[4]

VSS

Output

AF4

VID[3]

VID[1]

VSS

Output

AE3

CMOS

AF5

CMOS

AE4

Power/Other

CMOS

AF6

Power/Other

AE5

VID[2]

PSI#

Output

AF7

VCCSENSE

VSS

AE6

CMOS

AF8

AE7

VSSSENSE

VSS

Power/Other

AF9

VCC

AE8

AF10

AF11

AF12

AF13

VCC

AE9

VCC

VSS

AE10

AE11

VCC

VSS

Datasheet

71

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

VSS

Power/Other

CMOS

VCC

VSS

VCC

VSS

BSEL[0]

BSEL[1]

VSS

Output

CMOS

Source

Synch

Input/

Output

Power/Other

Reserved

AF22

D[62]#

RSVD

VCCA

RSVD

VSS

Source

Synch

Input/

Output

AF23

AF24

AF25

D[56]#

VSS

Power/Other

Reserved

Power/Other

C2

Power/Other

Reserved

Source

Synch

Input/

Output

D[61]#

C3

RSVD

IGNNE#

VSS

Source

Synch

Input/

Output

AF26

B1

D[63]#

RESET#

C4

CMOS

Input

C5

Power/Other

CMOS

Common

Clock

Input

C6

LINT0

Input

B2

RSVD

INIT#

LINT1

DPSLP#

VSS

Reserved

THERMTRI

P#

C7

Open Drain

Output

B3

CMOS

Input

C8

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

B4

CMOS

C9

B5

CMOS

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

B6

Power/Other

B7

VCC

B8

VSS

B9

VCC

B10

B11

B12

B13

B14

B15

VCC

VSS

VCC

VSS

VCC

72

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

C20

C21

C22

C23

C24

C25

C26

D1

DBR#

BSEL[2]

VSS

CMOS

Output

Common

Clock

D24

DPWR#

Input

CMOS

D25

D26

TEST2

VSS

Test

Power/Other

Reserved

Power/Other

RSVD

VSS

Common

Clock

Input/

Output

E1

DBSY#

Reserved

Power/Other

Test

Common

Clock

Input/

Output

E2

E3

E4

BNR#

VSS

TEST1

VSS

Power/Other

Reserved

Common

Clock

Input/

Output

HITM#

D2

RSVD

VSS

D3

Reserved

E5

DPRSTP#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

CMOS

Input

D4

Power/Other

CMOS

E6

Power/Other

D5

STPCLK#

PWRGOOD

SLP#

VSS

Input

E7

D6

CMOS

E8

D7

CMOS

E9

D8

Power/Other

Open Drain

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

D9

VCC

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

IERR#

Output

Source

Synch

Input/

Output

E22

D[0]#

PROCHOT

#

Input/

Output

D21

Open Drain

Source

Synch

Input/

Output

E23

E24

D[7]#

VSS

D22

D23

RSVD

VSS

Reserved

Power/Other

Datasheet

73

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

Source

Synch

Input/

Output

F25

F26

G1

VSS

Power/Other

E25

E26

D[6]#

D[2]#

Source

Synch

Input/

Output

D[13]#

VSS

Source

Synch

Input/

Output

Power/Other

Common

Clock

Input/

Output

F1

F2

F3

BR0#

VSS

Common

Clock

G2

TRDY#

Input

Power/Other

Common

Clock

G3

G4

G5

RS[2]#

VSS

Common

Clock

RS[0]#

Input

Power/Other

Common

Clock

F4

RS[1]#

Common

Clock

BPRI#

Input

F5

VSS

RSVD

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

Reserved

Common

Clock

Input/

Output

G6

HIT#

VCCP

F6

F7

Power/Other

G21

G22

G23

G24

Power/Other

F8

DSTBP[0]

#

Source

Synch

Input/

Output

F9

VSS

Power/Other

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

Source

Synch

Input/

Output

D[9]#

Source

Synch

Input/

Output

G25

G26

H1

D[5]#

VSS

Power/Other

Common

Clock

Input/

Output

ADS#

Source

Synch

Input/

Output

H2

H3

H4

REQ[1]#

VSS

Power/Other

Common

Clock

Input/

Output

LOCK#

Common

Clock

H5

DEFER#

Input

Common

Clock

Input/

Output

F21

F22

F23

DRDY#

VSS

H6

VSS

Power/Other

H21

Source

Synch

Input/

Output

D[4]#

Source

Synch

Input/

Output

H22

H23

D[3]#

Source

Synch

Input/

Output

F24

D[1]#

DSTBN[0]

#

Source

Synch

Input/

Output

74

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

H24

H25

VSS

Power/Other

Source

Synch

Input/

Output

K24

D[8]#

Source

Synch

Input/

Output

D[15]#

Source

Synch

Input/

Output

K25

K26

L1

D[17]#

VSS

Source

Synch

Input/

Output

H26

D[12]#

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

J1

J2

J3

A[9]#

VSS

A[13]#

Power/Other

ADSTB[0]

#

Source

Synch

Input/

Output

L2

L3

L4

Source

Synch

Input/

Output

REQ[3]#

VSS

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

J4

A[3]#

A[4]#

J5

VSS

Power/Other

Source

Synch

Input/

Output

L5

REQ[4]#

J6

VCCP

VSS

L6

VSS

Power/Other

J21

J22

L21

Source

Synch

Input/

Output

L22

D[21]#

Source

Synch

Input/

Output

J23

D[11]#

Source

Synch

Input/

Output

L23

L24

L25

D[22]#

VSS

Source

Synch

Input/

Output

J24

J25

J26

K1

D[10]#

VSS

Power/Other

Source

Synch

Input/

Output

D[20]#

Source

Synch

Input/

Output

DINV[0]#

VSS

Source

Synch

Input/

Output

L26

D[29]#

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

K2

REQ[2]#

M1

M2

M3

A[7]#

VSS

Source

Synch

Input/

Output

Power/Other

K3

K4

K5

REQ[0]#

VSS

Source

Synch

Input/

Output

A[5]#

Power/Other

Source

Synch

Input/

Output

M4

RSVD

VSS

Reserved

A[6]#

M5

Power/Other

K6

VCCP

Power/Other

M6

VCCP

VSS

K21

M21

M22

Source

Synch

Input/

Output

K22

K23

D[14]#

VSS

Power/Other

Datasheet

75

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

Source

Synch

Input/

Output

Source

Synch

Input/

Output

M23

D[23]#

P22

D[25]#

DSTBN[1]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

M24

M25

M26

N1

P23

P24

P25

D[26]#

VSS

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

DINV[1]#

VSS

D[24]#

Power/Other

Source

Synch

Input/

Output

P26

D[18]#

Source

Synch

Input/

Output

N2

A[8]#

Source

Synch

Input/

Output

R1

R2

R3

A[16]#

VSS

Source

Synch

Input/

Output

N3

A[10]#

Power/Other

N4

VSS

Power/Other

Reserved

Source

Synch

Input/

Output

A[19]#

N5

RSVD

VCCP

Source

Synch

Input/

Output

R4

A[24]#

N6

Power/Other

N21

R5

VSS

Power/Other

Source

Synch

Input/

Output

R6

VCCP

VSS

N22

N23

N24

D[16]#

VSS

R21

R22

Power/Other

Source

Synch

Input/

Output

D[31]#

Source

Synch

Input/

Output

R23

D[19]#

DSTBP[1]

#

Source

Synch

Input/

Output

N25

N26

P1

Source

Synch

Input/

Output

R24

R25

R26

D[28]#

VSS

Power/Other

Source

Synch

Input/

Output

A[15]#

Input/

Output

COMP[0]

Source

Synch

Input/

Output

P2

P3

P4

A[12]#

VSS

T1

T2

VSS

Power/Other

Reserved

Power/Other

RSVD

Source

Synch

Input/

Output

Source

Synch

Input/

Output

A[14]#

T3

T4

T5

A[26]#

VSS

Source

Synch

Input/

Output

Power/Other

P5

A[11]#

Source

Synch

Input/

Output

A[25]#

P6

VSS

Power/Other

P21

T6

VCCP

Power/Other

T21

76

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Pin Name

Direction

Buffer Type

T22

T23

RSVD

VSS

Reserved

V22

V23

VSS

Power/Other

Source

Synch

Input/

Output

DINV[2]#

Source

Synch

Input/

Output

T24

D[27]#

Source

Synch

Input/

Output

V24

V25

V26

W1

D[34]#

VSS

Source

Synch

Input/

Output

T25

T26

U1

D[30]#

VSS

Power/Other

Source

Synch

Input/

Output

D[35]#

VSS

Input/

Output

COMP[2]

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

U2

U3

U4

A[23]#

VSS

W2

A[30]#

Power/Other

Source

Synch

Input/

Output

W3

W4

W5

A[27]#

VSS

Source

Synch

Input/

Output

A[21]#

Power/Other

Source

Synch

Input/

Output

Source

Synch

Input/

Output

U5

A[18]#

A[28]#

U6

VSS

Power/Other

Source

Synch

Input/

Output

W6

A[20]#

VCCP

U21

W21

W22

W23

W24

Power/Other

Source

Synch

Input/

Output

U22

D[39]#

Source

Synch

Input/

Output

D[41]#

VSS

Source

Synch

Input/

Output

U23

U24

U25

D[37]#

VSS

Power/Other

DSTBN[2]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

D[38]#

Source

Synch

Input/

Output

W25

W26

Y1

D[36]#

VSS

Input/

Output

U26

V1

COMP[1]

COMP[3]

Power/Other

Input/

Output

Source

Synch

Input/

Output

A[31]#

V2

V3

VSS

Power/Other

Reserved

Source

Synch

Input/

Output

Y2

Y3

Y4

A[17]#

VSS

RSVD

Power/Other

ADSTB[1]

#

Source

Synch

Input/

Output

V4

Source

Synch

Input/

Output

A[29]#

V5

VSS

Power/Other

Source

Synch

Input/

Output

Y5

Y6

A[22]#

VSS

V6

VCCP

V21

Power/Other

Datasheet

77

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Number

Signal

Number

Pin Name

Direction

Buffer Type

Y21

Y22

VSS

Power/Other

Source

Synch

Input/

Output

D[45]#

Source

Synch

Input/

Output

Y23

Y24

Y25

D[42]#

VSS

Power/Other

DSTBP[2]

#

Source

Synch

Input/

Output

Source

Synch

Input/

Output

Y26

D[44]#

78

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

The processor requires a thermal solution to maintain temperatures within operating

limits as set forth in Section 5.1. Any attempt to operate that processor outside these

operating limits may result in permanent damage to the processor and potentially other

components in the system. As processor technology changes, thermal management

becomes increasingly crucial when building computer systems. Maintaining the proper

thermal environment is key to reliable, long-term system operation. A complete

thermal solution includes both component and system level thermal management

features. Component level thermal solutions include active or passive heatsinks or heat

exchangers attached to the processor exposed die. The solution should make firm

contact to the die while maintaining processor mechanical specifications such as

pressure. A typical system level thermal solution may consist of a processor fan ducted

to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct

die attachment. A secondary fan or air from the processor fan may also be used to cool

other platform components or to lower the internal ambient temperature within the

system.

To allow for the optimal operation and long-term reliability of Intel processor-based

systems, the system/processor thermal solution should be designed such that the

processor remains within the minimum and maximum junction temperature (Tj)

specifications at the corresponding thermal design power (TDP) value listed in Table 20

to Table 22. Thermal solutions not designed to provide this level of thermal capability

may affect the long-term reliability of the processor and system.

The maximum junction temperature is defined by an activation of the processor Intel

Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real

applications are unlikely to cause the processor to consume the theoretical maximum

power dissipation for sustained time periods. Intel recommends that complete thermal

solution designs target the TDP indicated in Table 20 to Table 22. The Intel Thermal

Monitor feature is designed to help protect the processor in the unlikely event that an

application exceeds the TDP recommendation for a sustained period of time. For more

details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel

Thermal Monitor feature must be enabled for the processor to remain within

specification.

Datasheet

79

Thermal Specifications and Design Considerations

Table 20.

Power Specifications for the Intel Core Duo Processor SV (Standard Voltage)

Processor

Number

Core Frequency

& Voltage

Thermal Design

Power

Symbol

Unit

Notes

T2700

31

2.33 GHz & HFM V_CC

T2600

T2500

T2400

T2300

T2300E

N/A

2.16 GHz & HFM V_CC

2.00 GHz & HFM V_CC

31

At 100°C

1.83 GHz & HFM V_CC

1.66 GHz & HFM V_CC

1.00 GHz & LFM V_CC

TDP

31

W

Notes 1, 4,

5

31

13.1

Symbol

Parameter

Min Typ Max Unit

Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

At 50°C

15.8

4.8

W

P_SGNT

Note 2

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

At 50°C

P_SLP

15.5

4.7

Note 2

Deep Sleep Power

at HFM V_CC

At 35°C

P_DSLP

10.5

3.4

W

Note 2

at LFM V_CC

At 35°C

P_DPRSLP

Deeper Sleep Power

2.2

Note 2

At 35°C

P_DC4

T_J

Intel® Enhanced Deeper Sleep Power

Junction Temperature

1.8

W

Note 2

0

100

°C

Notes 3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

4.

5.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specification.

T2300E does not support Intel Virtualization Technology.

80

Datasheet

Thermal Specifications and Design Considerations

Table 21.

Power Specifications for the Intel Core Solo Processor SV (Standard Voltage)

Processor

Number

Core Frequency

& Voltage

Thermal Design

Power

Symbol

Unit

Notes

T1400

1.83 GHz & HFM V_CC

1.66 GHz & HFM V_CC

1.00 GHz & LFM V_CC

27

At 100°C

TDP

T1300

N/A

W

Notes 1, 4

13.1

Symbol

Parameter

Min Typ Max Unit

Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

At 50°C

15.8

4.8

W

P_SGNT

Note 2

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

At 50°C

P_SLP

15.5

4.7

Note 2

Deep Sleep Power

at HFM V_CC

At 35°C

P_DSLP

10.5

3.4

W

Note 2

at LFM V_CC

At 35°C

P_DPRSLP

Deeper Sleep Power

2.2

Note 2

At 35°C

P_DC4

T_J

Intel® Enhanced Deeper Sleep Power

Junction Temperature

1.8

W

Note 2

0

100

°C

Notes 3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specification.

Datasheet

81

Thermal Specifications and Design Considerations

Table 22.

Power Specifications for the Intel Core Duo Processor LV (Low Voltage)

Processor

Number

Core Frequency

& Voltage

Thermal Design

Power

Symbol

Unit

Notes

L2500

1.83 GHz & HFM V_CC

1.66 GHz & HFM V_CC

1.50 GHz & HFM V_CC

1.00 GHz & LFM V_CC

15

L2400

L2300

N/A

At 100°C

TDP

W

15

Notes 1, 4

13.1

Symbol

Parameter

Min Typ Max

Unit

Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

At 50°C

6.0

4.8

W

P_SGNT

Note 2

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

At 50°C

P_SLP

5.8

4.7

W

Note 2

Deep Sleep Power

at HFM V_CC

At 35°C

P_DSLP

5.7

3.4

W

Note 2

at LFM V_CC

At 35°C

P_DPRSLP

Deeper Sleep Power

2.2

1.8

Note 2

At 35°C

P_DC4

T_J

Intel® Enhanced Deeper Sleep Power

Junction Temperature

W

Note 2

0

100

°C

Notes 3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specification.

82

Datasheet

Thermal Specifications and Design Considerations

Table 23.

Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage

(ULV)

Processor

Number

Core Frequency

& Voltage

Thermal Design

Power

Symbol

Unit

Notes

U2500

1.20 GHz & HFM V_CC

1.06 GHz & HFM V_CC

800 MHz & LFM V_CC

9

At 100°C

TDP

U2400

N/A

W

Unit

W

Notes1, 4

7.5

Symbol

Parameter

Min Typ Max

Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

At 50°C

3.7

2.6

P_SGNT

Note 2

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

At 50°C

P_SLP

3.6

2.5

W

Note 2

Deep Sleep Power

at HFM V_CC

At 35°C

P_DSLP

2.2

1.8

W

Note 2

at LFM V_CC

At 35°C

P_DPRSLP

Deeper Sleep Power

1.3

1.1

Note 2

At 35°C

P_DC4

T_J

Intel® Enhanced Deeper Sleep Power

Junction Temperature

W

Note 2

0

100

°C

Notes 3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specification.

Datasheet

83

Thermal Specifications and Design Considerations

Table 24.

Power Specifications for the Intel Core Solo Processor ULV (Ultra Low

Voltage)

Processor

Number

Core Frequency

& Voltage

Thermal Design

Power

Symbol

Unit

Notes

1.33 GHz and HFM V_CC

1.20 GHz and HFM

U1500

5.5

5

U1400

U1300

At 100°C

TDP

V

_CC1.06 GHz and LFM

W

Notes 1, 4

V_CC

800 MHz and LFM V_CC

Symbol

Parameter

Min Typ Max

Unit

Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

At 50°C

3.0

2.2

W

P_SGNT

Note 2

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

At 50°C

P_SLP

2.9

2.1

W

Note 2

Deep Sleep Power

at HFM V_CC

At 35°C

P_DSLP

1.5

1.2

W

Note 2

at LFM V_CC

At 35°C

P_DPRSLP

Deeper Sleep Power

0.7

0.6

Note 2

At 35°C

P_DC4

T_J

Intel® Enhanced Deeper Sleep Power

Junction Temperature

W

Note 2

0

100

°C

Notes 3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specification.

84

Datasheet

Thermal Specifications and Design Considerations

5.1

Thermal Specifications

The processor incorporates three methods of monitoring die temperature, the digital

thermal sensor (DTS), Intel Thermal Monitor and the thermal diode. The Intel Thermal

Monitor (detailed in Section 5.1.3) must be used to determine when the maximum

specified processor junction temperature has been reached.

5.1.1

Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is

used as a thermal diode, with its collector shorted to Ground. The thermal diode, can

be read by an off-die analog/digital converter (a thermal sensor) located on the

motherboard, or a stand-alone measurement kit. The thermal diode may be used to

monitor the die temperature of the processor for thermal management or

instrumentation purposes but is not a reliable indication that the maximum operating

temperature of the processor has been reached. When using the thermal diode, a

temperature offset value must be read from a processor Model Specific Register (MSR)

and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal

diode usage recommendation when the PROCHOT# signal is not asserted.

Note:

The reading of the external thermal sensor (on the motherboard) connected to the

processor thermal diode signals, will not necessarily reflect the temperature of the

hottest location on the die. This is due to inaccuracies in the external thermal sensor,

on-die temperature gradients between the location of the thermal diode and the hottest

location on the die, and time based variations in the die temperature measurement.

Time based variations can occur when the sampling rate of the thermal diode (by the

thermal sensor) is slower than the rate at which the T_Jtemperature can change.

Offset between the thermal diode-based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic

mode activation of thermal control circuit. This temperature offset must be taken into

account when using the processor thermal diode to implement power management

events. This offset is different than the diode Toffset value programmed into the

processor Model Specific Register (MSR).

Table 25, Table 26, Table 27, and Table 28 provide the diode interface and

specifications. Two different sets of diode parameters are listed in Table 26 and

Table 27. The Diode Model parameters (Table 26) apply to traditional thermal sensors

that use the Diode Equation to determine the processor temperature. Transistor Model

parameters (Table 27) have been added to support thermal sensors that use the

transistor equation method. The Transistor Model may provide more accurate

temperature measurements when the diode ideality factor is closer to the maximum or

minimum limits. Please contact your external thermal sensor supplier for their

recommendation. This thermal diode is separate from the Intel Thermal Monitor's

thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.

Table 25.

Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

A24

A25

Thermal diode anode

Thermal diode cathode

Datasheet

85

Thermal Specifications and Design Considerations

Table 26.

Thermal Diode Parameters using Diode Mode

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_FW

n

Forward Bias Current

Diode Ideality Factor

Series Resistance

5

-

200

1.050

6.24

µA

-

1

1.000

2.79

1.009

4.52

2, 3, 4

2, 3, 5

R_T

Ω

NOTES:

1.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Intel does not support or recommend operation of the thermal diode when the processor

power supplies are not within their specified tolerance range.

Characterized across a temperature range of 50 - 100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by

the diode equation:

2.

3.

4.

I

_FW= I_S* (e ^{qV /nkT}–1)

D

where I_S= saturation current, q = electronic charge, V_D= voltage across the diode, k =

Boltzmann Constant, and T = absolute temperature (Kelvin).

5.

The series resistance, R_T, is provided to allow for a more accurate measurement of the

junction temperature. R_T, as defined, includes the lands of the processor but does not

include any socket resistance or board trace resistance between the socket and the

external remote diode thermal sensor. R_Tcan be used by remote diode thermal sensors

with automatic series resistance cancellation to calibrate out this error term. Another

application is that a temperature offset can be manually calculated and programmed into

an offset register in the remote diode thermal sensors as exemplified by the equation:

T_error= [R_T* (N-1) * I_FWmin] / [nk/q * ln N]

where T_error= sensor temperature error, N = sensor current ratio, k = Boltzmann

Constant, q = electronic charge.

Table 27.

Thermal Diode Parameters using Transistor Mode

Symbol

I_FW

Parameter

Min

Typ

Max

Unit

Notes

Forward Bias Current

Emitter Current

5

-

200

µA

-

1, 2

I_E

n_Q

Transistor Ideality

0.997

0.3

1.001

4.52

1.005

0.760

6.24

3, 4, 5

3, 4

Beta

R_T

Series Resistance

2.79

Ω

3, 6

NOTES:

1.

2.

3.

4.

5.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Same as I_FWin Table 25.

Characterized across a temperature range of 50 - 100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

/n

I

_C= I_S* (e ^qVBE ^kT–1)

Q

Where I_S= saturation current, q = electronic charge, V_BE= voltage across the transistor

base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

temperature (Kelvin).

6.

The series resistance, R_T,provided in the Diode Model Table (Table 26) can be used for


型号：	T2500
厂家：	INTEL
描述：	Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process 在65纳米制程的英特尔酷睿双核处理器和英特尔酷睿单核处理器
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中文：	中文翻译
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T2500 [INTEL]

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