T5600_技术文档

Intel® Core™2 Duo Mobile Processor

for Intel® Centrino® Duo Mobile

Processor Technology

Datasheet

September 2007

Document Number: 314078-004

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information here is subject to change without notice. Do not finalize a design with this information.

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Enhanced Intel SpeedStep® Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at

http://processorfinder.intel.com or contact your Intel representative for more information

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an

Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with

your system vendor for more information.

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2

Datasheet

Contents

1

Introduction..............................................................................................................7

1.1

1.2

Terminology .......................................................................................................9

References ....................................................................................................... 10

2

Low Power Features................................................................................................ 11

2.1

Clock Control and Low Power States .................................................................... 11

2.1.1 Core Low Power State Descriptions........................................................... 13

2.1.2 Package Low Power State Descriptions...................................................... 15

Enhanced Intel SpeedStep® Technology .............................................................. 18

Extended Low Power States................................................................................ 19

FSB Low Power Enhancements............................................................................ 19

Processor Power Status Indicator (PSI#) Signal..................................................... 20

2.2

2.3

2.4

2.5

3

Electrical Specifications........................................................................................... 21

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Power and Ground Pins ...................................................................................... 21

FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 21

Voltage Identification......................................................................................... 21

Catastrophic Thermal Protection.......................................................................... 25

Reserved and Unused Pins.................................................................................. 25

FSB Frequency Select Signals (BSEL[2:0])............................................................ 26

FSB Signal Groups............................................................................................. 26

CMOS Signals ................................................................................................... 28

Maximum Ratings.............................................................................................. 28

3.10 Processor DC Specifications ................................................................................ 29

4

5

Package Mechanical Specifications and Pin Information.......................................... 39

4.1

4.2

4.3

Package Mechanical Specifications....................................................................... 39

Processor Pinout and Pin List .............................................................................. 49

Alphabetical Signals Reference............................................................................ 73

Thermal Specifications and Design Considerations .................................................. 81

5.1

Thermal Specifications ....................................................................................... 85

5.1.1 Thermal Diode ....................................................................................... 85

5.1.2 Thermal Diode Offset.............................................................................. 85

5.1.3 Intel® Thermal Monitor........................................................................... 87

5.1.4 Digital Thermal Sensor............................................................................ 89

5.1.5 Out of Specification Detection .................................................................. 90

5.1.6 PROCHOT# Signal Pin............................................................................. 90

Datasheet

3

Figures

1

2

3

4

Core Low Power States..............................................................................................12

Package Low Power States.........................................................................................13

Deeper Sleep V_CCand I_CCLoadline for Dual-core Standard Voltage Processors..................34

Deeper Sleep V_CCand I_CCLoadline for Dual-core Low Voltage and

Ultra Low Voltage Processor.......................................................................................35

Active V_CCand I_CCLoadline for Intel Core 2 Solo Processor, Ultra Low Voltage..................36

4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................40

4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................41

2-MB Micro-FCPGA Processor Package Drawing.............................................................42

2-MB Micro-FCPGA Processor Package Drawing.............................................................43

5

6

7

8

9

10 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................44

11 4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................45

12 2-MB Micro-FCBGA Processor Package Drawing ............................................................46

13 1-MB Micro-FCBGA Processor Package Drawing (2 of 2).................................................47

14 1-MB Micro-FCBGA Processor Package Drawing (2 of 2).................................................48

Tables

1

Coordination of Core Low Power States at the Package Level..........................................13

2

3

4

5

6

7

8

9

Voltage Identification Definition..................................................................................22

BSEL[2:0] Encoding for BCLK Frequency......................................................................26

FSB Pin Groups ........................................................................................................27

Processor Absolute Maximum Ratings..........................................................................28

Voltage and Current Specifications for Dual-core Standard Voltage Processors..................29

Voltage and Current Specifications for Dual-core Low Voltage Processors .........................31

Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors..32

AGTL+ Signal Group DC Specifications ........................................................................37

10 CMOS Signal Group DC Specifications..........................................................................38

11 Open Drain Signal Group DC Specifications ..................................................................38

12 The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 1 of 2)..........................................................................................................50

13 The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 2 of 2)..........................................................................................................51

14 Pin Listing by Pin Name.............................................................................................53

15 Pin Listing by Pin Number..........................................................................................64

16 Signal Description.....................................................................................................73

17 Power Specifications for the Dual-core Standard Voltage Processor..................................82

18 Power Specifications for the Dual-core Low Voltage Processor.........................................83

19 Power Specifications for the Single and Dual-core Ultra Low Voltage Processor..................84

20 Thermal Diode ntrim and Diode Correction Toffset ........................................................86

21 Thermal Diode Interface............................................................................................86

22 Thermal Diode Parameters using Diode Mode...............................................................86

23 Thermal Diode Parameters Using Transistor Model ........................................................87

4

Datasheet

Revision History

Revision

Number

Description

Revision Date

-001

-002

-003

Initial release

August 2006

•

Added Information for L7400 and L7200 Low-Voltage Processors

Updated Table 08 in Chapter 3

Updated Table 17 in Chapter 5

December 2006

May 2007

•

Added L-2 die package information

•

Added Information for U2200 and U2100 Ultra Low-Voltage Processors

Updated Electrical Specifications in Chapter 3 for ULV Processors

Updated Thermal Specifications in Chapter 5 for ULV Processors

Added A-1 die package information

-004

September 2007

§ §

Datasheet

5

6

Datasheet

Introduction

1

Introduction

The Intel® Core™2 Duo mobile processor for Intel® Centrino® Duo mobile technology

based on the Intel® 945 Express Chipset family is built on 65-nanometer process

technology and is the next generation high-performance, low-power mobile processor

based on the Intel® Core™ architecture.

Note:

All references to the word “processor” in this document are references to the Intel Core

2 Duo mobile processor with 533- and 667-MHz front side bus (FSB), unless specified

otherwise.

The following list provides some of the key features on this processor:

• Dual-core processor for mobile with enhanced performance

• Intel® 64 architecture

• Supports Intel Architecture with Dynamic Execution

• On-die, primary 32-kB instruction cache and 32-kB write-back data cache per core

• On-die, up to 4-MB second level shared cache with Advanced Transfer Cache

Architecture

• Data Prefetch Logic

• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and

Supplemental Streaming SIMD Extensions 3 (SSSE3)

• 667-MHz, Source-Synchronous FSB for Standard Voltage processors

• Advanced Power Management features including Enhanced Intel SpeedStep®

Technology

• Intel® Enhanced Deeper Sleep state and Dynamic Cache Sizing

• Digital Thermal Sensor

• Micro-FCPGA and Micro-FCBGA packaging technologies

• Intel® Virtualization Technology

• Execute Disable Bit support for enhanced security

Note:

64-bit computing on Intel architecture requires a computer system with a processor,

chipset, BIOS, operating system, device drivers and applications enabled for Intel 64

architecture. Processors will not operate (including 32-bit operation) without an Intel

64 architecture-enabled BIOS. Performance will vary depending on your hardware and

software configurations. Consult with your system vendor for more information.

The Intel Core 2 Duo mobile processor will be manufactured on Intel’s 65-nanometer

process technology. The processor maintains support for MMX^TMtechnology, Streaming

SIMD instructions, and full compatibility with IA-32 software. In addition, the Intel Core

2 Duo mobile processor supports Intel 64 architecture which is enabled by 64-bit

operating systems and consists of 64-bit instructions and registers. Further details on

Intel Extended Memory 64 Technology and its programming model can be found in the

Intel Extended Memory 64 Technology Software Developer’s Guide. The Intel Core 2

Duo mobile processor features on-die, 32-kB level 1 instruction and data caches and

features up to a 4-MB level 2 cache with Advanced Transfer Cache Architecture. The

processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1

cache requests occurs, resulting in reduced bus cycle penalties. The processor includes

the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by

requesting L1 warm-ups earlier. In addition, the Write Order Buffer depth is enhanced

to help with the write-back latency performance.

Datasheet

7

Introduction

In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2) and

Streaming SIMD Extensions 3 (SSE3), the processor supports Supplemental Streaming

SIMD Extensions 3 (SSSE3) to speed up media algorithms like encoding and decoding.

Advanced Dynamic Execution improves speculative execution and branch prediction

internal to the processor. The floating point and multi-media units include 128-bit wide

registers and a separate register for data movement. Streaming SIMD3 (SSE3)

instructions provide highly efficient double-precision floating point, SIMD integer, and

memory management operations. Also, these instructions enhance the performance of

optimized applications for the digital home such as video, image processing and media

compression technology.

The processor features Enhanced Intel SpeedStep Technology, which enables real-time

dynamic switching between multiple voltage and frequency points. The processor

features the Auto Halt, Stop Grant, Deep Sleep, and Intel Enhanced Deeper Sleep C-

states. Enhanced thermal management capabilities are implemented including Intel®

Thermal Monitor 1 and Intel Thermal Monitor 2 to provide efficient and effective cooling

in high temperatures.

The Intel Core 2 Duo mobile processor utilizes socketable Micro Flip-Chip Pin Grid Array

(Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA)

package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount,

Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket.

Intel Core 2 Duo mobile processor supports the Execute Disable Bit capability. This

feature combined with a supporting operating system allows memory to be marked as

executable or non executable. If code attempts to run in non-executable memory the

processor raises an error to the operating system. This feature can prevent some

classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help

improve the overall security of the system. See the Intel® 64 and IA-32 Intel®

Architectures Software Developer's Manual for more detailed information.

Intel Virtualization Technology is a set of hardware enhancements to Intel server and

client systems that combined with the appropriate software, will enable enhanced

virtualization robustness and performance for both enterprise and consumer uses. Intel

Virtualization Technology forms the foundation of Intel technologies focused on

improved virtualization, safer computing, and system stability. For client systems, Intel

Virtualization Technology’s hardware-based isolation helps provide the foundation for

highly available and more secure client virtualization partitions.

8

Datasheet

Introduction

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX

means that the specification or value is yet to be determined.

#

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Intel®

Virtualization

Technology

Processor virtualization which when used in conjunction with Virtual

Machine Monitor software enables multiple, robust independent software

environments inside a single platform.

Processor core die with integrated L1 and L2 cache. All AC timing and

signal integrity specifications are at the pads of the processor core.

Processor Core

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor lands should not be

connected to any supply voltages, have any I/Os biased or receive any

clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device

removed from packaging material) the processor must be handled in

accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage

Conditions

V_CC

V_SS

The processor core power supply

The processor ground reference

Datasheet

9

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document. Also note that with Intel Centrino Duo technology, the Intel

Core 2 Duo mobile processor supports Mobile Intel® 945GM/GT/GMS/PM and 940GML

Express Chipset family and Intel® 82801GBM (also known as ICH7M).

Document

Number

Intel® Core™2 Duo Processor for Intel® Centrino® Duo Technology

Specification Update

314079

Mobile Intel® 945 Express Chipset Family Chipset Datasheet

Mobile Intel® 945 Express Chipset Family Chipset Specification Update

Intel® I/O Controller Hub 7 (ICH7) Family Datasheet

Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual

Volume 1: Basic Architecture

309219

309220

307013

307014

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

Intel® 64 and IA-32 Architectures Software Developer's Manual

Documentation Changes

252046

241618

AP-485 Intel® Processor Identification and the CPUID Instruction

§ §

10

Datasheet

Low Power Features

2

Low Power Features

2.1

Clock Control and Low Power States

The Intel Core 2 Duo mobile processor supports low power states both at the individual

core level and the package level for optimal power management. A core may

independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states.

Refer to Figure 1 for a visual representation of the core low power states for the

processor. When both cores coincide in a common core low power state, the central

power management logic ensures the entire Intel Core 2 Duo mobile processor enters

the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and

P_LVL4) I/O read to the Intel 945GM/GT/GMS/PM and 940GML Express Chipset family.

Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep

Sleep, and Deeper Sleep. Refer to Figure 2 for a visual representation of the package

low power states for the Intel Core 2 Duo mobile processor and to Table 1 for a

mapping of core low power states to package low power states.

The Intel Core 2 Duo mobile processor implements two software interfaces for

requesting low power states: MWAIT instruction extensions with sub-state hints and

P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address

space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests

inside the processor and do not directly result in I/O reads on the processor FSB. The

monitor address does not need to be setup before using the P_LVLx I/O read interface.

The sub-state hints used for each P_LVLx read can be configured through a software

programmable Model Specific Register (MSR).

If a core encounters a chipset break event while STPCLK# is asserted, then it asserts

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to

system logic that individual cores should return to the C0 state and the Intel Core 2

Duo mobile processor should return to the Normal state.

Datasheet

11

Low Power Features

Figure 1.

Core Low Power States

Stop

Grant

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

de-asserted

asserted

STPCLK#

de-asserted

STPCLK#

asserted

C1/

MWAIT

C1/Auto

Halt

Core state

break

HLT instruction

MWAIT(C1)

Halt break

C0

Core State

break

P_LVL2 or

MWAIT(C2)

P_LVL4 or

MWAIT(C4)

Core state

break

C4^{† ‡}

C2^†

Core

state

break

P_LVL3 or

MWAIT(C3)

C3^†

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.

‡ — Core C4 state includes the Intel Enhanced Deeper Sleep state.

12

Datasheet

Low Power Features

Figure 2.

Package Low Power States

SLP# asserted

DPSLP# asserted

DPRSTP# asserted

STPCLK# asserted

Deeper

Sleep^†

Stop

Grant

Deep

Sleep

Normal

Sleep

STPCLK# de-asserted

SLP# de-asserted

DPSLP# de-asserted

DPRSTP# de-asserted

Snoop

serviced occurs

Stop

Grant

Snoop

† — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.

Table 1.

Coordination of Core Low Power States at the Package Level

Package State

Core1 State

C1/Auto

HALT/

MWAIT

Core0 State

C0

C2

C3

C4

Normal

C1/AutoHALT/

MWAIT

C2

C3

Normal

Stop-Grant

Deep Sleep

Stop-Grant

Deep Sleep

Deeper Sleep/

Intel®

Enhanced

C4

Normal

Stop-Grant

Deep Sleep

Deeper Sleep

2.1.1

Core Low Power State Descriptions

2.1.1.1

Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2

Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel®

Architectures Software Developer's Manual, Volume 3A/3B: System Programmer's

Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

Datasheet

13

Low Power Features

While in AutoHALT Powerdown state, the Intel Core 2 Duo mobile processor will process

bus snoops and snoops from the other core. The processor core will enter a snoopable

sub-state (not shown in Figure 1) to process the snoop and then return to the

AutoHALT Powerdown state.

2.1.1.3

2.1.1.4

Core C1/MWAIT Powerdown State

C1/MWAIT is a low power state entered when the processor core executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor core to return to

the C0 state. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's

Manual, Volume 2A/2B: Instruction Set Reference for more information.

Core C2 State

Individual cores of the Intel Core 2 Duo mobile processor can enter the C2 state by

initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the

processor will not issue a Stop-Grant Acknowledge special bus cycle unless the

STPCLK# pin is also asserted.

While in the C2 state, the Intel Core 2 Duo mobile processor will process bus snoops

and snoops from the other core. The processor core will enter a snoopable sub-state

(not shown in Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5

Core C3 State

Individual cores of the Intel Core 2 Duo mobile processor can enter the C3 state by

initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering

C3, the processor core flushes the contents of its L1 caches into the processor’s L2

cache. Except for the caches, the processor core maintains all its architectural state in

the C3 state. The Monitor remains armed if it is configured. All of the clocks in the

processor core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB or when the other core of the Intel

Core 2 Duo mobile processor accesses cacheable memory. The processor core will

transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0]

(NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to

immediately initialize itself.

2.1.1.6

Core C4 State

Individual cores of the Intel Core 2 Duo mobile processor can enter the C4 state by

initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor

core behavior in the C4 state is nearly identical to the behavior in the C3 state. The

only difference is that if both processor cores are in C4, then the central power

management logic will request that the entire Intel Core 2 Duo mobile processor enter

the Deeper Sleep package low power state (see Section 2.1.2.6).

To enable the package level Intel® Enhanced Deeper Sleep state, Dynamic Cache

Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software

programmable MSR to enable the Intel Enhanced Deeper Sleep state.

14

Datasheet

Low Power Features

2.1.2

Package Low Power State Descriptions

2.1.2.1

Normal State

This is the normal operating state for the processor. The Intel Core 2 Duo mobile

processor remains in the Normal state when at least one of its cores is in the C0, C1/

AutoHALT, or C1/MWAIT state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each core of the Intel Core 2 Duo mobile processor

enters the Stop-Grant state within 20 bus clocks after the response phase of the

processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are

already in the C2, C3, or C4 state remain in their current low power state. When the

STPCLK# pin is deasserted, each core returns to its previous core low power state.

Note:

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will

stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#,

SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to

RESET# deassertion (AC Specification T45). When re-entering the Stop-Grant state

from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the

deassertion of SLP# (AC Specification T75).

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt or monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor

should return to the Normal state.

A transition to the Stop-Grant Snoop state will occur when the processor detects a

snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see

Section 2.1.2.4) will occur with the assertion of the SLP# signal.

2.1.2.3

2.1.2.4

Stop-Grant Snoop State

The processor will respond to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor will return

to the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

Sleep State

The Sleep state is a low power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

Datasheet

15

Low Power Features

Note:

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through Stop-Grant state. If RESET# is driven active while the processor

is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately

after RESET# is asserted to ensure the processor correctly executes the Reset

sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5.). While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur.

2.1.2.5

Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform level

power savings. BCLK stop/restart timings on Intel 945GM/GT/GMS/PM and 940GML

Express Chipset family based platforms with the CK410M clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of

DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to

allow for PLL stabilization) must occur before the processor can be considered to be in

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding tosnoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep

state, it will not respond to interrupts or snoop transactions. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable

behavior.

2.1.2.6

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to

one of two lower levels. One lower core voltage level is achieved by entering the base

Deeper Sleep state. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the

lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper

Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered

through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache

has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for

further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep

state.

In response to entering Deeper Sleep, the Intel Core 2 Duo mobile processor will drive

the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.

16

Datasheet

Low Power Features

Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by

DPRSTP# deassertion when either core requests a core state other than C4 or either

core requests a processor performance state other than the lowest operating point.

2.1.2.6.1

Intel Enhanced Deeper Sleep State

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power

saving capabilities by allowing the processor to further reduce core voltage once the L2

cache has been reduced to zero ways and completely shut down. The following events

occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 I/O Read or an MWAIT(C4).

• The processor triggers a special chipset sequence to notify the chipset to redirect

all FSB traffic, except APIC messages, to memory. The snoops are replied as misses

by the chipset and are directed to main memory instead of the L2 cache.

• The processor will drive the VID code corresponding to the Intel Enhanced Deeper

Sleep state core voltage on the VID[6:0] pins.

2.1.2.6.2

Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable

number of L2 cache ways upon each Deeper Sleep entry under the following

conditions:

• The second core is already in C4 and core sub-state Intel Enhanced Deeper Sleep

state is enabled (as specified in Section 2.1.2.6.1).

• The C0 timer, which tracks continuous residency in the Normal package state, has

not expired. This timer is cleared during the first entry into Deeper Sleep to allow

consecutive Deeper Sleep entries to shrink the L2 cache as needed.

• The FSB speed to processor core speed ratio is below the predefined L2 shrink

threshold.

If the FSB speed to processor core speed ratio is above the predefined L2 shrink

threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio

will not be taken into account for Dynamic Cache Sizing decisions.

Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep

state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways.

If the L2 cache reduction conditions stated above still exist when the last core returns

to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be

shrunk to zero again. If a core requests a processor performance state resulting in a

higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the

second core (not the one currently entering the interrupt routine) requests the C1, C2,

or C3 states, then the whole L2 will be expanded when the next INTR event would

occur.

L2 cache shrink prevention may be enabled as needed on occasion through an

MWAIT(C4) sub-state field. If shrink prevention is enabled, then the Intel Core 2 Duo

mobile processor does not enter the Intel Enhanced Deeper Sleep state since the L2

cache remains valid and in full size.

Datasheet

17

Low Power Features

2.2

Enhanced Intel SpeedStep® Technology

The Intel Core 2 Duo mobile processor features Enhanced Intel SpeedStep Technology.

Following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software controlled by writing to processor

MSRs:

— . If the target frequency is higher than the current frequency, Vcc is ramped up

in steps by placing new values on the VID pins and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch free

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 μs during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high,

the processor can automatically perform a transition to a lower frequency and

voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up transition to the previous frequency and voltage point

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system level thermal management.

• Enhanced thermal management features.

— Digital Thermal Sensor and Out of Specification detection.

— Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of

unsuccessful Intel Thermal Monitor 2 transition.

— Dual-core thermal management synchronization.

Each core in the processor implements an independent MSR for controlling Enhanced

Intel SpeedStep Technology, but both cores must operate at the same frequency and

voltage. The processor has performance state coordination logic to resolve frequency

and voltage requests from the two cores into a single frequency and voltage request for

the package as a whole. If both cores request the same frequency and voltage, then

the processor will transition to the requested common frequency and voltage. If the

two cores have different frequency and voltage requests, then the processor will take

the highest of the two frequencies and voltages as the resolved request and transition

to that frequency and voltage.

18

Datasheet

Low Power Features

2.3

Extended Low Power States

Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly

reducing the performance state of the processor when it enters a package low power

state. Instead of directly transitioning into the package low power state, the extended

low power state first reduces the performance state of the processor by performing an

Enhanced Intel SpeedStep Technology transition down to the lowest operating point.

Upon receiving a break event from the package low power state, control will be

returned to software while an Enhanced Intel SpeedStep Technology transition up to

the initial operating point occurs. The advantage of this feature is that it significantly

reduces leakage while in the package low power states.

Note:

Long-term reliability may not be assured if Extended Low Power States are not

enabled.

The processor implements two software interfaces for requesting extended package

low power states: MWAIT instruction extensions with sub-state hints and via BIOS by

configuring a software programmable MSR to automatically promote package low

power states to extended package low power states.

Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the

processor to remain within specification.

Enhanced Intel SpeedStep Technology transitions are multistep processes that require

clocked control. These transitions cannot occur when the processor is in the Sleep or

Deep Sleep package low power states since processor clocks are not active in these

states. Extended Deeper Sleep is an exception to this rule when the Hard C4E

configuration is enabled through a software programmable MSR. This Extended Deeper

Sleep state configuration will lower the core voltage to the Deeper Sleep level while in

Deeper Sleep and, upon exit, will automatically transition to the lowest operating

voltage and frequency to reduce snoop service latency. The transition to the lowest

operating point or back to the original software requested point may not be

instantaneous. Furthermore, upon very frequent transitions between active and idle

states, the transitions may lag behind the idle state entry resulting in the processor

either executing for a longer time at the lowest operating point or running idle at a high

operating point. Observations and analyses show this behavior should not significantly

impact total power savings or performance score while providing power benefits in

most other cases.

2.4

FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-die Termination disabling

• Low V_CCP(I/O termination voltage)

Datasheet

19

Low Power Features

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in chipset address and control input buffers when the

processor deasserts its BR0# pin. The On-die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

2.5

Processor Power Status Indicator (PSI#) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a

reduced power consumption state. PSI# can be used to improve intermediate and light

load efficiency of the voltage regulator, resulting in platform power savings and

extended battery life. The algorithm that the processor uses for determining when to

assert PSI# is different from the algorithm used in previous Intel® Pentium® M

processors. For Intel Core 2 processor with Intel Centrino Duo mobile technology, PSI#

signal functionality is supported only in idle state.

§ §

20

Datasheet

Electrical Specifications

3

Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower planes

while all V_SSpins must be connected to system ground planes. Use of multiple power

and ground planes is recommended to reduce I*R drop. Please contact your Intel

representative for more details. The processor V_CCpins must be supplied the voltage

determined by the VID (Voltage ID) pins.

3.2

3.3

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the core frequency is a multiple of the

BCLK[1:0] frequency. The processor uses a differential clocking implementation.

Voltage Identification

The processor uses seven voltage identification pins, VID[6:0], to support automatic

selection of power supply voltages. The VID pins for processor are CMOS outputs

driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to low-

voltage level.

Datasheet

21

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 1 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

Vcc (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

22

Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 2 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

Vcc (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

Datasheet

23

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 3 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

Vcc (V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

24

Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 4 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

Vcc (V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

3.4

3.5

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough such that

the processor cannot be protected in all conditions without the removal of power to the

processor. If the external thermal sensor detects a catastrophic processor temperature

of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the

processor must be turned off within 500 ms to prevent permanent silicon damage due

to thermal runaway of the processor. THERMTRIP# functionality is not guaranteed if the

PWRGOOD signal is not asserted.

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Figure 12 for a pin listing of the processor

and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected.

The TEST1 and TEST2 pin must have a stuffing option connection to V_SSseparately via

1-kΩ, pull-down resistors.

Datasheet

25

Electrical Specifications

For testing purposes it is recommended, but not required, to route the TEST3 and

TEST4 pins through a ground referenced 55-Ω trace that ends in a via that is near a

GND via and is accessible through an oscilloscope connection.

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the Intel 945GM/

GT/GMS/PM and 940GML Express Chipset family on the platform. The BSEL encoding

for BCLK[1:0] is shown in Table 3.

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BCLK

BSEL[2]

BSEL[1]

BSEL[0]

Frequency

L

H

L

RESERVED

133 MHz

H

RESERVED

166 MHz

H

3.7

FSB Signal Groups

In order to simplify the following discussion, the FSB signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use

GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the

AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+

Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when

driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependent upon the rising edge of BCLK0 ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 4 identifies which signals are common clock, source synchronous,

and asynchronous.

26

Datasheet

Electrical Specifications

Table 4.

FSB Pin Groups

Signal Group

Type

Signals¹

Synchronous

to BCLK[1:0]

BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#, DPWR#,

TRDY#

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

Synchronous

to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#, DRDY#, HIT#,

HITM#, LOCK#, PRDY#³

AGTL+ Source Synchronous I/O Synchronous

to assoc.

strobe

Signals

REQ[4:0]#,

Associated Strobe

ADSTB[0]#

ADSTB[1]#

A[16:3]#

A[35:17]#⁶

DSTBP0#,

DSTBN0#

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP1#,

DSTBN1#

DSTBP2#,

DSTBN2#

DSTBP3#,

DSTBN3#

Synchronous

AGTL+ Strobes

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

to BCLK[1:0]

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

CMOS Input

Asynchronous

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous FERR#, IERR#, THERMTRIP#

Asynchronous PROCHOT#⁴

Asynchronous PSI#, VID[6:0], BSEL[2:0]

Synchronous

TCK, TDI, TMS, TRST#

to TCK

CMOS Input

Synchronous

TDO

Open Drain Output

FSB Clock

to TCK

Clock

BCLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST2, TEST1,

THERMDA, THERMDC, V_CC, V_CCA, V_CCP,V_{CC_SENSE}, V_SS,

V_{SS_SENSE}

Power/Other

NOTES:

1.

Refer to Chapter 4, “Package Mechanical Specifications and Pin Information” for signal descriptions and

termination requirements.

2.

In processor systems without a debug port implemented on the board, these signals are used to support

debug port interposers. In systems with the debug port implemented on the board, these signals are no

connects.

3.

4.

5.

BPM[2:1]# and PRDY# are AGTL+ output only signals.

PROCHOT# signal type is open drain output and CMOS input.

On-die termination differs from other AGTL+ signals, please contact your Intel representative for more

details.

6.

When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected.

Datasheet

27

Electrical Specifications

3.8

3.9

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for more than four BCLKs in order

for the processor to recognize them. See Section 3.10 for the DC specifications for the

CMOS signal groups.

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings. Within functional operation

limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 5.

Processor Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes¹

TSTORAGE

Processor storage temperature

-40

85

°C

2,3,4

Any processor supply voltage with

respect to V_SS

V_CC

-0.3

-0.1

1.55

V

AGTL+ buffer DC input voltage with

respect to V_SS

V_inAGTL+

V_{inAsynch_CMOS}

NOTES:

CMOS buffer DC input voltage with

respect to V_SS

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

specifications must be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias. For

functional operation, please refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long term reliability of the processor.

3.

4.

28

Datasheet

Electrical Specifications

3.10

Processor DC Specifications

Note:

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise.

See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals

on the FSB are in the AGTL+ signal group. The DC specifications for these signals are

listed in Table 9. DC specifications for the CMOS group are listed in Table 10.

Table 6 through Table 11 list the DC specifications for the processor and are valid only

while meeting specifications for junction temperature, clock frequency, and input

voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer

to the highest and lowest core operating frequencies supported on the processor. Active

mode load line specifications apply in all states except in the Deep Sleep and Deeper

Sleep states. V_CC,BOOTis the default voltage driven by the voltage regulator at power

up in order to set the VID values. Unless specified otherwise, all specifications for the

processor are at Tjunction = 100°C. Care should be taken to read all notes associated

with each parameter.

Table 6.

Symbol

Voltage and Current Specifications for Dual-core Standard Voltage Processors

(Sheet 1 of 2)

Parameter

Min

Typ

Max

Unit

Notes

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.0375

0.75

1.3000

0.95

V

1, 2

2, 8

1.20

1.05

1.5

1.00

1.425

0.60

1.10

1.575

0.80

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCDC4

V_CCat Deeper Sleep Voltage

1, 2, 12

1,2

V_CCat Intel® Enhanced Deeper Sleep Voltage

0.55

0.70

I_CCfor Processors

I_CCDES

Recommended Design Targets:

44

A

5

I_CCfor Processors

Processor

Core Frequency/Voltage

Number

T7600

T7400

T7200

T5600

T5500

2.33 GHz and HFM V_CC

2.17 GHz and HFM V_CC

2.00 GHz and HFM V_CC

1.83 GHz and HFM V_CC

1.67 GHz and HFM V_CC

1.00 GHz and LFM V_CC

41

3, 8, 12

3, 8, 13

I_CC

41

A

41

27.3

I_CCAuto-Halt and Stop-Grant

I_AH,

LFM

HFM

18.0

26.7

A

3,4

I_SGNT

I_CCSleep

LFM

I_SLP

17.8

26.1

HFM

Datasheet

29

Electrical Specifications

Table 6.

Symbol

I_DSLP

Voltage and Current Specifications for Dual-core Standard Voltage Processors

(Sheet 2 of 2)

Parameter

Min

Typ

Max

Unit

Notes

I_CCDeep Sleep

LFM

HFM

17.0

23.7

A

3,4

I_DPRSLP

I_CCDC4

I_CCDeeper Sleep

12.1

9.9

3,4

4

I_CCIntel Enhanced Deeper Sleep

V_CCPower Supply Current Slew Rate at CPU

Package Pin

dI_CC/DT

I_CCA

600

130

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

9

I_CCP

10

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

2.

3.

4.

5.

Specified at 100°C Tj.

Specified at the VID voltage.

The I_CCDES(max) specification of 44 A comprehends processor I_CCdesign target for Intel Core2 Duo mobile

processor for Intel Centrino Duo mobile technology.

6.

Base on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7.

Measured at the bulk capacitors on the motherboard.

8.

Specified at nominal V_CC.

9.

10.

11.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel

Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID.

12.

13.

T7600, T7400, T7200 processors feature 4-MB cache.

T5600, T5500 processors feature 2-MB cache.

30

Datasheet

Electrical Specifications

Table 7.

Symbol

Voltage and Current Specifications for Dual-core Low Voltage Processors

Parameter

Min

Typ

Max

Unit

Notes

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

0.9

1.1

V

1, 2

2, 8

0.75

0.95

1.20

1.05

1.5

1.00

1.425

0.6

1.10

1.575

0.8

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCat Deeper Sleep Voltage

1, 2, 12

1,2

V_CCat Intel® Enhanced Deeper Sleep

Voltage

V_CCDC4

0.55

0.7

V

I_CCfor Processors

I_CCDES

Recommended Design Targets:

23

A

5

Processor

Core Frequency/Voltage

Number

I_CC

L7400

L7200

1.50 GHz and HFM V_CC

1.33 GHz and HFM V_CC

1.00 GHz and LFM V_CC

23

3,9,13

A

19.7

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

10.4

11.5

A

3,4

I_SGNT

I_CCSleep

LFM

I_SLP

10.1

11.2

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

9.4

9.9

A

I_DPRSLP

I_DC4

I_CCDeeper Sleep

7.4

5.4

3,4

I_CCIntel Enhanced Deeper Sleep State

V_CCPower Supply Current Slew Rate at CPU

Package Pin

dI_CC/DT

I_CCA

600

130

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

10

11

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).

2.

3.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

Specified at 100°C Tj.

Datasheet

31

Electrical Specifications

4.

5.

Specified at the VID voltage.

The I_CCDES(max) specification of 23 A comprehends only Intel Core 2 Duo mobile processor HFM

frequencies with Intel Centrino Duo mobile technology.

6.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7.

Measured at the bulk capacitors on the motherboard.

8.

V

_CC,BOOTtolerance shown in Figure 3.

9.

Specified at nominal V_CC

.

10.

11.

12.

This is a steady-state Icc current specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel

Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID

Table 8.

Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage

Processors (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

0.8

0.975

0.95

V

1, 2

2, 8

0.75

1.20

1.05

1.5

1.00

1.425

0.60

1.10

1.575

0.80

V_CCA

PLL Supply Voltage

V_CCDPRSLP

V_CCat Deeper Sleep Voltage

1, 2, 12

1, 2

V_CCat Intel® Enhanced Deeper Sleep

Voltage

V_CCDC4

0.55

0.70

V

17 (dual

core)

I_CCfor Processors

I_CCDES

A

5

Recommended Design Targets:

8 (single

core)

Processor

Core Frequency/Voltage

Number

16

U7600

U7500

U2200

U2100

1.20 GHz and HFM V_CC

1.06 GHz and HFM V_CC

1.20 GHz and HFM V_CC

1.06 GHz and HFM V_CC

0.80 GHz and LFM V_CC

I_CC

8

A

3, 9

8

13.8-DC

6.9-SC

I_CCAuto-Halt & Stop-Grant

I_AH,

LFM

HFM

6.5

7.4

A

3, 4

I_SGNT

I_CCSleep

LFM

I_SLP

6.3

7.3

HFM

I_CCDeep Sleep

I_DSLP

LFM

HFM

5.7

6.2

I_DPRSLP

I_CCDC4

I_CCDeeper Sleep

4.9

4.0

A

3, 4

I_CCIntel Enhanced Deeper Sleep

32

Datasheet

Electrical Specifications

Table 8.

Symbol

Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage

Processors (Sheet 2 of 2)