TE28F160B3BC80 [INTEL]
3 Volt Advanced Boot Block Flash Memory; 3伏高级启动区块快闪记忆体
| 型号： | TE28F160B3BC80 |
| 厂家： | 
INTEL |
| 描述： | 3 Volt Advanced Boot Block Flash Memory |
| 文件： | 总58页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 Volt Advanced Boot Block Flash
Memory
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Preliminary Datasheet
Product Features
■ Flexible SmartVoltage Technology
—2.7 V–3.6 V Read/Program/Erase
—12 V VPP Fast Production Programming
■ 2.7 V or 1.65 V I/O Option
—Reduces Overall System Power
■ High Performance
■ Intel® Flash Data Integrator Software
—Flash Memory Manager
—System Interrupt Manager
—Supports Parameter Storage, Streaming
Data (e.g., Voice)
■ Extended Cycling Capability
—Minimum 100,000 Block Erase Cycles
Guaranteed
—2.7 V–3.6 V: 70 ns Max Access Time
■ Optimized Block Sizes
■ Automatic Power Savings Feature
—Typical ICCS after Bus Inactivity
■ Standard Surface Mount Packaging
—48-Ball CSP Packages
—Eight 8-KB Blocks for Data,Top or
Bottom Locations
—Up to One Hundred Twenty-Seven 64-
KB Blocks for Code
■ Block Locking
—40- and 48-Lead TSOP Packages
—VCC-Level Control through WP#
■ Low Power Consumption
—9 mA Typical Read Current
■ Absolute Hardware-Protection
—VPP = GND Option
■ Density and Footprint Upgradeable for
common package
—4-, 8-, 16-, 32- and 64-Mbit Densities
■ ETOX™ VII (0.18 µ) Flash Technology
—28F160/320/640B3xC
—4-, 8-, 16-, and 32-Mbit also exist on
ETOX™ V (0.4µ) and/or ETOX ™ VI
(0.25µ) Flash Technology
—VCC Lockout Voltage
■ Extended Temperature Operation
—–40 °C to +85 °C
■ x8 not recommended for new designs
■ Automated Program and Block Erase
—Status Registers
■ 4-Mbit density not recommended for new
designs
The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm
technology, represents a feature-rich solution at overall lower system cost. The 3 Volt Advanced
Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP
packages. The x8 option of this product family will only be available in 40-lead TSOP and 48-
ball µBGA* packages. Additional information on this product family can be obtained by
accessing Intel’s website at: http://www.intel.com/design/flash.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290580-012
October 2000
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation 1999– 2000.
*Other brands and names are the property of their respective owners.
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Contents
1.0
Introduction..................................................................................................................1
1.1 Product Overview..................................................................................................2
Product Description..................................................................................................3
2.0
2.1
2.2
Package Pinouts ...................................................................................................3
Block Organization ................................................................................................7
2.2.1 Parameter Blocks.....................................................................................7
2.2.2 Main Blocks..............................................................................................7
3.0
Principles of Operation............................................................................................7
3.1
3.2
3.3
Bus Operation .......................................................................................................7
3.1.1 Read.........................................................................................................8
3.1.2 Output Disable..........................................................................................8
3.1.3 Standby ....................................................................................................8
3.1.4 Deep Power-Down / Reset.......................................................................8
3.1.5 Write.........................................................................................................9
Modes of Operation...............................................................................................9
3.2.1 Read Array ...............................................................................................9
3.2.2 Read Identifier........................................................................................11
3.2.3 Read Status Register .............................................................................11
3.2.4 Program Mode........................................................................................12
3.2.5 Erase Mode............................................................................................12
Block Locking ......................................................................................................14
3.3.1 WP# = VIL for Block Locking ..................................................................14
3.3.2 WP# = VIH for Block Unlocking ..............................................................15
3.4
3.5
V
PP Program and Erase Voltages.......................................................................15
3.4.1 PP = VIL for Complete Protection .........................................................15
V
Power Consumption............................................................................................15
3.5.1 Active Power ..........................................................................................16
3.5.2 Automatic Power Savings (APS)............................................................16
3.5.3 Standby Power.......................................................................................16
3.5.4 Deep Power-Down Mode .......................................................................16
Power-Up/Down Operation .................................................................................16
3.6.1 RP# Connected to System Reset...........................................................17
3.6
3.7
3.6.2
VCC, VPP and RP# Transitions...............................................................17
Power Supply Decoupling ...................................................................................17
4.0
Electrical Specifications........................................................................................18
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings.................................................................................18
Operating Conditions...........................................................................................19
Capacitance ........................................................................................................19
DC Characteristics ..............................................................................................20
AC Characteristics —Read Operations...............................................................23
AC Characteristics —Write Operations...............................................................27
Program and Erase Timings................................................................................31
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5.0
6.0
7.0
Reset Operations .....................................................................................................33
Ordering Information..............................................................................................34
Additional Information...........................................................................................36
Appendix A Write State Machine Current/Next States .................................................37
Appendix B Architecture Block Diagram...........................................................................38
Appendix C Word-Wide Memory Map Diagrams.............................................................39
Appendix D Byte-Wide Memory Map Diagrams ..............................................................45
Appendix E Program and Erase Flowcharts....................................................................48
iv
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Revision History
Number
Description
-001
Original version
Section 3.4, V Program and Erase Voltages, added
PP
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
-002
I
maximum specification change from ±25 µA to ±50 µA
PPR
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V read specification (Section 3.4)
PP
Removed 120 ns and 150 ns speed offerings
-003
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A –A = 0 when in read identifier mode (Section 3.2.2)
1
20
Status register clarification for SR3 (Table 7)
V
and V absolute maximum specification = 3.7 V (Section 4.1)
CC
CCQ
Combined I
Combined I
and I
into one specification (Section 4.4)
into one specification (Section 4.4)
PPW
PPE
CCW
and I
CCE
Max Parameter Block Erase Time (t
/t
) reduced to 4 sec (Section 4.7)
) reduced to 5 sec (Section 4.7)
) changed to 5 µs typical and 20 µs maximum
WHQV2 EHQV2
/t
/t
-004
Max Main Block Erase Time (t
Erase suspend time @ 12 V (t
(Section 4.7)
WHQV3 EHQV3
WHRH2 EHRH2
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
I
test conditions corrected (Section 4.4)
PPD
-005
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
V
and V Specification change (Section 4.4)
IH
IL
I
test conditions clarification (Section 4.4)
CCS
Added Command Sequence Error Note (Table 7)
Datasheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
-006
-007
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
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Number
Description
-008
-009
4-Mbit packaging and addressing information corrected throughout document
Corrected 4-Mbit memory addressing tables in Appendices D and E
Max I
changed to 25 µA
CCD
-010
V
Max on 32 M (28F320B3) changed to 3.3 V
CC
Added 64-Mbit density and faster speed offerings
Removed access time vs. capacitance load curve
-011
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
-012
Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit
device.
Minor text edits throughout document.
vi
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1.0
Introduction
This datasheet contains the specifications for the 3 Volt Advanced Boot Block flash memory
family, which is optimized for low power, portable systems. This family of products features
1.65 V–2.5 V or 2.7 V–3.6 V I/Os and a low VCC/VPP operating range of 2.7 V–3.6 V for read,
program, and erase operations. In addition this family is capable of fast programming at 12 V.
Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except
where noted otherwise) and “VPP = 12 V” refers to 12 V ±5%. Section 1.0 and 2.0 provide an
overview of the flash memory family including applications, pinouts and pin descriptions. Section
3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other
reference information.
The 3 Volt Advanced Boot Block flash memory features:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility
• Program Suspend to Read command
• VCCQ input of 1.65 V–2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and
V
CCQ location
• Maximum program and erase time specification for improved data storage.
Table 1. 3 Volt Advanced Boot Block Feature Summary
28F400B3(2), 28F800B3,
28F004B3(2), 28F008B3,
28F016B3
Feature
28F160B3, 28F320B3(3)
28F640B3
,
Reference
Section 4.2,
Section 4.4
Section 4.2, 4.4
Section 4.2, 4.4
Table 3
V
Read Voltage
2.7 V– 3.6 V
CC
V
V
I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
2.7 V– 3.6 V or 11.4 V– 12.6 V
CCQ
Program/Erase Voltage
PP
Bus Width
Speed
8 bit
16 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
Section 4.5
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
512 Kbit x 8 (4 Mbit)
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
Memory Arrangement
Section 2.2
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4 Mbit) or
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Sixty-three 64-Kbyte main blocks (32 Mbit)
One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)
Section 2.2
Appendix C
Blocking (top or bottom)
Locking
WP# locks/unlocks parameter blocks
Section 3.3
Table 8
All other blocks protected using V
Extended: –40 °C to +85 °C
100,000 cycles
PP
Operating Temperature
Program/Erase Cycling
Section 4.2, 4.4
Section 4.2, 4.4
48-Lead TSOP,
48-Ball µBGA CSP(2)
48-Ball VF BGA(4)
40-lead TSOP(1)
48-Ball µBGA* CSP(2)
,
Packages
,
Figure 3, Figure 4
NOTES:
1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
2. 4-Mbit density not available in µBGA* CSP.
3. V Max is 3.3 V on 0.25µm 32-Mbit devices.
CC
4. 4- and 64-Mbit densities not available on 48-Ball VF BGA.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.1
Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and
erase operation. All 3 Volt Advanced Boot Block flash memory products provide program/erase
capability at 2.7 V or 12 V (for fast production programming) and read with VCC at 2.7 V. Since
many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can
provide substantial power savings.
The 3 Volt Advanced Boot Block flash memory products are available in either x8 or x16 packages
in the following densities: (see Section 6.0, “Ordering Information” on page 34 for availability.)
• 4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes
of 8-bits each
• 8-Mbit (8,388,608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
• 16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
• 32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each
• 64-Mbit (67,108,864-bit) flash memory organized as 4096 Kwords of 16 bits each
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map in order to accommodate different microprocessor protocols for kernel code
location. The upper two (or lower two) parameter blocks can be locked to provide complete code
security for system initialization code. Locking and unlocking is controlled by WP# (see Section
3.3, “Block Locking” on page 14 for details).
The Command User Interface (CUI) serves as the interface between the microprocessor or
microcontroller and the internal operation of the flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for program and erase
operations, including verification, thereby un-burdening the microprocessor or microcontroller.
The status register indicates the status of the WSM by signifying block erase or word program
completion and status.
The 3 Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings
(APS) feature which minimizes system current drain, allowing for very low power designs. This
mode is entered following the completion of a read cycle (approximately 300 ns later).
The RP# pin provides additional protection against unwanted command writes that may occur
during system reset and power-up/down sequences due to invalid system bus conditions (see
Section 3.6, “Power-Up/Down Operation” on page 16).
Section 3.0, “Principles of Operation” on page 7 gives detailed explanation of the different modes
of operation. Complete current and voltage specifications can be found in Section 4.4, “DC
Characteristics” on page 20. Refer to Section 4.5, “AC Characteristics —Read Operations” on
page 23 for read, program and erase performance specifications.
2
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2.0
Product Description
This section explains device pin description and package pinouts.
2.1
Package Pinouts
The 3 Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1),
48-lead TSOP (x16, Figure 2) and 48-ball µBGA(x8 and x16, Figure 3 and Figure 4, respectively)
and 48-ball VF BGA (x16, Figure 4) packages. In all figures, pin changes necessary for density
upgrades have been circled.
Figure 1. 40-Lead TSOP Package for x8 Configurations
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
16 M
8 M
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
GND
CE#
A0
A8
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
TOP VIEW
4 M
A2
A1
0580_01
NOTES:
1. 40-Lead TSOP available for 8- and 16-Mbit densities only.
2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on
Pin 38.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 2. 48-Lead TSOP Package for x16 Configurations
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
A8
64 M
32 M
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
16 M
0580_02
NOTE: Lower densities will have NC on the upper address pins. For example, an 16-Mbit device will have NC
on Pins 9 and 10.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A14
A12
A8
VPP
WP#
A20
A7
A4
8M
A15
A10
A13
NC
A11
D7
WE#
A9
RP#
A19
A18
A5
A3
A2
A1
A16
A6
A17
D5
NC
NC
D4
D2
D3
NC
NC
NC
CE#
D0
A0
VCCQ
GND
D6
GND
OE#
NC
VCC
D1
0580_04
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A is the upgrade address for the
20
16-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
4
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Figure 4. x16 48-Ball Very Thin Profile Pitch BGA and µBGA* Chip Size Package (Top View,
Ball Down)
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A13
A11
A8
VPP
WP#
A19
A7
A4
A14
A10
WE#
A9
RP#
A21
A18
A17
A5
A3
A2
A1
32M
64M
A15
A12
A20
A6
A16
D14
D15
D7
D5
D6
D11
D12
D4
D2
D3
D8
D9
CE#
D0
A0
VCCQ
GND
GND
OE#
D13
VCC
D10
D1
0580_03
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A is the upgrade address for the
19
16-Mbit device. A is the upgrade address for the 32-Mbit device. A is the upgrade address for the 64-Mbit
20
21
device.
2. 4-Mbit density not available in µBGA CSP.
Table 2, “3 Volt Advanced Boot Block Pin Descriptions” on page 6 details the usage of each device
pin.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 2. 3 Volt Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
A –A
INPUT
28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
0
21
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
INPUT/
command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
DQ –DQ
0
7
OUTPUT internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state
when the chip is de-selected. Not included on x8 products.
DQ –
INPUT/
OUTPUT
8
DQ
15
CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#
CE#
INPUT
is active low. CE# high de-selects the memory device and reduces power consumption to standby
levels.
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation.
OE# is active low.
OE#
WE#
INPUT
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (V , V ) to control reset/deep power-down
IL
IH
mode.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs
to High-Z, resets the Write State Machine, and minimizes current levels (I ).
RP#
INPUT
CCD
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-
low to logic-high, the device defaults to the read array mode.
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked, preventing program and erase
operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and
either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
WP#
INPUT
INPUT
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
See Section 3.3 for details on write protection.
OUTPUT V : Enables all outputs to be driven to 1.8 V – 2.5 V while the V is at 2.7 V–3.3 V. If the
CC
CC
V
is regulated to 2.7 V–2.85 V, V
can be driven at 1.65 V–2.5 V to achieve lowest power
CC
CCQ
V
V
CCQ
CC
operation (see Section 4.4).
This input may be tied directly to V (2.7 V–3.6 V).
CC
DEVICE POWER SUPPLY: 2.7 V–3.6 V
PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. V may
PP
be the same as V (2.7 V–3.6 V) for single supply voltage operation. For fast programming at
CC
manufacturing, 11.4 V–12.6 V may be supplied to V . This pin cannot be left floating. Applying
PP
11.4 V–12.6 V to V can only be done for a maximum of 1000 cycles on the main blocks and 2500
PP
V
PP
cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum (see
PP
Section 3.4 for details).
V
< V
protects memory contents against inadvertent or unintended program and erase
PPLK
PP
commands.
GND
NC
GROUND: For all internal circuitry. All ground inputs must be connected.
NO CONNECT: Pin may be driven or left floating.
6
3UHOLPLQDU\
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2.2
Block Organization
The 3 Volt Advanced Boot Block is an asymmetrically-blocked architecture that enables system
integration of code and data within a single flash device. Each block can be erased independently
of the others up to 100,000 times. For the address locations of each block, see the memory maps in
Appendix C.
2.2.1
Parameter Blocks
The 3 Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate
storage of frequently updated small parameters (e.g., data that would normally be stored in an
EEPROM). By using software techniques, the word-rewrite functionality of EEPROMs can be
emulated. Each device contains eight parameter blocks of 8-Kbytes/4-Kwords (8192 bytes/4,096
words) each.
2.2.2
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks
(65,536 bytes/32,768 words) for data or code storage. The 4-Mbit device contains seven main
blocks; 8-Mbit device contains fifteen main blocks; 16-Mbit flash has thirty-one main blocks;
32-Mbit has sixty-three main blocks; 64-Mbit has one hundred twenty-seven main blocks.
3.0
Principles of Operation
Flash memory combines EEPROM functionality with in-circuit electrical program and erase
capability. The 3 Volt Advanced Boot Block flash memory family utilizes a Command User
Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI
allows for 100% CMOS-level control inputs and fixed power supplies during erasure and
programming.
When VPP < VPPLK, the device will only execute the following commands successfully: Read
Array, Read Status Register, Clear Status Register and Read Identifier. The device provides
standard EEPROM read, standby and output disable operations. Manufacturer identification and
device identification data can be accessed through the CUI. All functions associated with altering
memory contents, namely program and erase, are accessible via the CUI. The internal Write State
Machine (WSM) completely automates program and erase operations while the CUI signals the
start of an operation and the status register reports status. The CUI handles the WE# interface to the
data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operation
3 Volt Advanced Boot Block flash memory devices read, program and erase in-system via the local
CPU or microcontroller. All bus cycles to or from the flash memory conform to standard micro-
controller bus cycles. Four control pins dictate the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 3. Bus Operations(1)
Mode
Note
RP#
CE#
OE#
WE#
DQ
DQ
8–15
0–7
Read (Array, Status, or Identifier)
2–4
2
V
V
V
V
V
V
V
V
D
D
OUT
IH
IH
IH
IL
IL
IH
IL
IH
IH
OUT
Output Disable
Standby
Reset
V
High Z
High Z
High Z
High Z
High Z
High Z
IH
2
V
X
X
2, 7
2, 5–7
V
X
X
X
IL
Write
V
V
V
V
D
D
IN
IH
IL
IH
IL
IN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be V , V for control pins and addresses.
IL
IH
3. See DC Characteristics for V
, V
, V
, V
, V
voltages.
PPLK
PP1
PP2
PP3
PP4
4. Manufacturer and device codes may also be accessed in read identifier mode (A –A = 0). See Table 5.
1
21
5. Refer to Table 6 for valid D during a write operation.
IN
6. To program or erase the lockable blocks, hold WP# at V
.
IH
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
3.1.1
Read
The flash memory has four read modes available: read array, read identifier, read status and read
query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode
command must be issued to the CUI to enter the corresponding mode. Upon initial device power-
up or after exit from reset, the device automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active it enables the flash memory device. OE# is the data output control and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
VIH. Figure 7 illustrates a read cycle.
3.1.2
3.1.3
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a
high-impedance state.
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during program or erase operation, the device continues to consume active power until
the program or erase operation is complete.
3.1.4
Deep Power-Down / Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-
impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required
until the initial read access outputs are valid. A delay (tPHWL or tPHEL) is required after return from
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read array mode, and the status register is set to 80H. This case is shown in
Figure 9A.
8
3UHOLPLQDU\
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If RP# is taken low for time tPLPH during a program or erase operation, the operation will be
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence: When RP# goes low, the device shuts down the operation in progress, a
process which takes time tPLRH to complete. After this time tPLRH, the part will either reset to read
array mode (if RP# has gone high during tPLRH, Figure 9B) or enter reset mode (if RP# is still logic
low after tPLRH, Figure 9C). In both cases, after returning from an aborted operation, the relevant
time tPHQV or tPHWL/tPHEL must be waited before a read or write operation is initiated, as
discussed in the previous paragraph. However, in this case, these delays are referenced to the end
of tPLRH rather than when RP# goes high.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel® Flash memories allow
proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.5
Write
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to
the Command User Interface (CUI) using standard microprocessor write timings to control flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 8
illustrates a program and erase operation. The available commands are shown in Table 6, and
Appendix A provides detailed information on moving between the different modes of operation
using CUI commands.
There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of the requested task (unless that operation is
aborted by either RP# being driven to VIL for tPLRH or an appropriate suspend command).
3.2
Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read
identifier, read status and read query (see Appendix B). The write modes are program and block
erase. Three additional modes (erase suspend to program, erase suspend to read and program
suspend to read) are available only during suspended operations. These modes are reached using
the commands summarized in Table 4. A comprehensive chart showing the state transitions is in
Appendix A.
3.2.1
Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will
respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
3UHOLPLQDU\
9
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
When the device is in read array mode, four control signals control data output:
• WE# must be logic high (VIH)
• CE# must be logic low (VIL)
• OE# must be logic low (VIL)
• RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can take place.
Table 4. Command Codes and Descriptions
Code
Device Mode
Description
00, 01,
60, 2F,
C0, 98
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to redefine these
codes for future functions.
FF
Read Array
Places the device in read array mode, such that array data will be output on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 3.2.4.
40
Program Set-Up
Alternate
Program Set-Up
10
20
(See 40H/Program Set-Up)
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”
(b) place the device into the read status register mode, and (c) wait for another command. See
Section 3.2.5.
Erase Set-Up
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches, and begin erasing the block indicated on the address pins. During erase, the
device will only respond to the Read Status Register and Erase Suspend commands. The
device will output status register data when CE# or OE# is toggled.
D0
If a program or erase operation was previously suspended, this command will resume that
operation
Program / Erase
Resume
Issuing this command will begin to suspend the currently executing program/erase operation.
The status register will indicate when the operation has been successfully suspended by
Program / Erase setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit
B0
70
Suspend
(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if it is driven to V . See Section 3.2.4.1 and Section 3.2.4.1.
IL
This command places the device into read status register mode. Reading the device will output
the contents of the status register, regardless of the address presented to the device. The
device automatically enters this mode after a program or erase operation has been initiated.
See Section 3.2.3.
Read Status
Register
The WSM can set the block lock status (SR.1) , V status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
PP
Clear Status
Register
50
90
Puts the device into the intelligent identifier read mode, so that reading the device will output
Read Identifier
the manufacturer and device codes (A = 0 for manufacturer, A = 1 for device, all other
0
0
address inputs must be 0). See Section Section 3.2.2.
NOTE: See Appendix A for mode transition information.
10
3UHOLPLQDU\
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3.2.2
Read Identifier
To read the manufacturer and device codes, the device must be in read identifier mode, which can
be reached by writing the Read Identifier command (90H). Once in read identifier mode, A0 = 0
outputs the manufacturer’s identification code and A0 = 1 outputs the device identifier (see
Table 5) Note: A1–A21 = 0. To return to read array mode, write the Read Array command (FFH).
Table 5. Read Identifier Table
Device Identifier
Size
Mfr. ID
0089H
0089H
-T
-B
(Top Boot)
(Bottom Boot)
28F004B3
28F400B3
28F008B3
28F800B3
28F016B3
28F160B3
28F320B3
28F640B3
D4H
8894H
D2H
D5H
8895H
D3H
8892H
D0H
8893H
D1H
8890H
8896H
8898H
8891H
8897H
8899H
0089H
3.2.3
Read Status Register
The device status register indicates when a program or erase operation is complete and the success
or failure of that operation. To read the status register issue the Read Status Register (70H)
command to the CUI. This causes all subsequent read operations to output data from the status
register until another command is written to the CUI. To return to reading from the array, issue the
Read Array (FFH) command.
The status register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status register contents change while being read. CE# or
OE# must be toggled with each subsequent status read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was successful in performing the desired operation (see
Table 7 on page 14).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these
bits can only be cleared through the Clear Status Register (50H) command. By allowing the system
software to control the resetting of these bits, several operations may be performed (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) before
3UHOLPLQDU\
11
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
reading the status register to determine if an error occurred during that series. Clear the status
register before beginning another command or sequence. Note, again, that the Read Array
command must be issued before data can be read from the memory array.
3.2.4
Program Mode
Programming is executed using a two-write sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program desired bits
of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If the user
attempts to program “1”s, the memory cell contents do not change and no error occurs.
The status register indicates programming status: while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the Program Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If
SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program
command. If SR.1 is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status register reads, be
sure to reset the CUI to read array mode.
3.2.4.1
Suspending and Resuming Program
The Program Suspend halts the in-progress program operation to read data from another location of
memory. Once the programming process starts, writing the Program Suspend command to the CUI
requests that the WSM suspend the program sequence (at predetermined points in the program
algorithm). The device continues to output status register data after the Program Suspend command
is written. Polling status register bits SR.7 and SR.2 will determine when the program operation
has been suspended (both will be set to “1”). tWHRH1/tEHRH1 specify the program suspend latency.
A Read Array command can now be written to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended, are Read Status
Register, Read Identifier, and Program Resume. After the Program Resume command is written to
the flash memory, the WSM will continue with the program process and status register bits SR.2
and SR.7 will automatically be cleared. After the Program Resume command is written, the device
automatically outputs status register data when read (see Appendix E for Program Suspend and
Resume Flowchart). VPP must remain at the same VPP level used for program while in program
suspend mode. RP# must also remain at VIH.
3.2.5
Erase Mode
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally-timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
12
3UHOLPLQDU\
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When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that
V
PP supply voltage was not within acceptable limits.
After an erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from or program data to
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when the erase operation has been suspended.
A Read Array/Program command can now be written to the CUI in order to read data from/
program data to blocks other than the one currently suspended. The Program command can
subsequently be suspended to read yet another array location. The only valid commands while
erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking
CE# to VIH. This reduces active current consumption.
Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase
operation, the status register must be read and cleared before the next instruction is issued.
Table 6. Command Bus Definitions (1,4)
First Bus Cycle
Addr
Second Bus Cycle
Command
Read Array
Notes
Oper
Data
Oper
Addr
Data
Write
Write
Write
Write
X
X
X
X
FFH
90H
70H
50H
Read Identifier
2
Read
Read
IA
X
ID
Read Status Register
Clear Status Register
SRD
40H /
10H
Program
3
Write
X
Write
Write
PA
BA
PD
Block Erase/Confirm
Write
Write
Write
X
X
X
20H
B0H
D0H
D0H
Program/Erase Suspend
Program/Erase Resume
NOTES:
PA: Program Address
PD: Program Data
ID: Identifier Data
BA: Block Address
IA: Identifier Address
SRD: Status Register Data
1. Bus operations are defined in Table 3.
2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
= 0 for manufacturer code, A = 1 for device code. A –A = 0.
A
0
0
1
21
3. Either 40H or 10H command is valid although the standard is 40H.
4. When writing commands to the device, the upper data bus [DQ –DQ ] should be either V or V , to
8
15
IL
IH
minimize current draw.
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7. Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
Check Write State Machine bit first to determine word program
or block erase completion, before checking program or erase
status bits.
1 = Ready
0 = Busy
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set at “1” until
an Erase Resume command is issued.
0 = Erase In Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
When this bit is set to “1,” WSM has attempted but failed to
program a word.
0 = Successful Word Program
SR.3 = V STATUS (VPPS)
The V status bit does not provide continuous indication of
PP
PP
1 = V Low Detect, Operation Abort
V
level. The WSM interrogates V level only after the
PP
PP PP
0 = V OK
Program or Erase command sequences have been entered,
and informs the system if V has not been switched on. The
PP
PP
V
is also checked before the operation is verified by the
PP
WSM. The V status bit is not guaranteed to report accurate
PP
feedback between V
max and V
min or between V
PPLK
PP1 PP1
max and V
min.
PP4
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
When program suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
0 = Program in Progress/Completed
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Operation aborted
If a program or erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
0 = No operation to locked blocks
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.
3.3
Block Locking
The 3 Volt Advanced Boot Block flash memory architecture features two hardware-lockable
parameter blocks.
3.3.1
WP# = V for Block Locking
IL
The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block
will result in an error, which will be reflected in the status register. For top configuration, the top
two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit, blocks
#37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8 Mbit, blocks #13 and #14 for the 4 Mbit)
are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for
4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless
V
PP is below VPPLK).
14
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.3.2
WP# = V for Block Unlocking
IH
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all
block locking and VPP provides protection against spurious writes. Table 8 defines the write
protection methods.
Table 8. Write Protection Truth Table for the Advanced Boot Block Flash Memory Family
V
WP#
RP#
Write Protection Provided
PP
X
X
X
V
All Blocks Locked
IL
IH
IH
IH
V
V
V
V
All Blocks Locked
IL
≥ V
≥ V
V
Lockable Blocks Locked
All Blocks Unlocked
PPLK
PPLK
IL
V
IH
3.4
V
Program and Erase Voltages
PP
Intel® 3 Volt Advanced Boot Block products provide in-system programming and erase at 2.7 V.
For customers requiring fast programming in their manufacturing environment, 3 Volt Advanced
Boot Block includes an additional low-cost 12 V programming feature.
The 12 V VPP mode enhances programming performance during the short period of time typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during program and erase operations for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum.
Warning: Stressing the device beyond these limits may cause permanent damage.
During read operations or idle times, VPP may be tied to a 5 V supply. For program and erase
operations, a 5 V supply is not permitted. The VPP must be supplied with either 2.7 V–3.6 V or
11.4 V–12.6 V during program and erase operations.
3.4.1
V
= V for Complete Protection
PP IL
The VPP programming voltage can be held low for complete write protection of all blocks in the
flash device. When VPP is below VPPLK, any program or erase operation will result in a error,
prompting the corresponding status register bit (SR.3) to be set.
3.5
Power Consumption
Intel Flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its
standby mode, where current consumption is even lower. The combination of these features can
minimize memory power consumption, and therefore, overall system power consumption.
3UHOLPLQDU\
15
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.5.1
3.5.2
3.5.3
Active Power
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for ICC current values. Active power is the largest contributor to
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to ICCS. The flash stays in this static state with outputs valid
until a new location is read.
Standby Power
With CE# at a logic-high level (VIH) and device in read mode, the flash memory is in standby
mode, which disables much of the device’s circuitry and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or program operations, the device will continue to
perform the operation and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This will provide a
more accurate measure of application-specific power and energy requirements.
3.5.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes,
RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery
from deep power-down requires a minimum time of tPHQV (see AC Characteristics—Read
Operations, Section 4.5).
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to
the device clears the status register).
3.6
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required, since the device is indifferent as to which power supply,
V
PP or VCC, powers-up first.
16
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.6.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.6.2
V
, V and RP# Transitions
CC PP
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
CC transitions above VLKO (Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after VPP transitions down to
V
PPLK), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
1. Standby current levels (ICCS
2. Read current levels (ICCR
)
)
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection will suppress these transient voltage
peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and
GND, and between its VPP and GND. These high-frequency, inherently low-inductance capacitors
should be placed as close as possible to the package leads.
3UHOLPLQDU\
17
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Extended Operating Temperature
During Read
–40 °C to +85 °C
During Block Erase and Program
Temperature under Bias
Storage Temperature
–40 °C to +85 °C
–40 °C to +85 °C
–65 °C to +125 °C
Voltage On Any Pin (except V , V
and V ) with Respect to GND –0.5 V to +3.7 V(1)
PP
CC
CCQ
V
V
Voltage (for Block Erase and Program) with Respect to GND
–0.5 V to +13.5 V(1,2,3)
–0.2 V to +3.7 V(4)
100 mA(5)
PP
CC
and V
Supply Voltage with Respect to GND
CCQ
Output Short Circuit Current
NOTES:
1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods <20 ns.
Maximum DC voltage on input/output pins is V +0.5 V, with allowable overshoot to V +1.5 for periods of
CC
CC
<20 ns
2. Maximum DC voltage on V may overshoot to +14.0 V for periods <20 ns.
PP
3. V Program voltage is normally 2.7 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a
PP
maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase.
V
may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details.
PP
4. Minimum DC voltage is -0.5 V on V and V
, with allowable undershoot to -2.0 V for periods <20 ns.
CC
CCQ
Maximum DC voltage on V and V
pins is V +0.5 V, with allowable overshoot to V +1.5 for periods
CC
CCQ
CC CC
of <20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
NOTICE: This datasheet contains preliminary information on new products in production. Specifications are
subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before
finalizing a design.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
18
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.2
Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
T
Operating Temperature
–40
2.7
+85
3.6
°C
A
V
V
V
V
V
V
V
V
V
V
1, 2
CC1
V
Supply Voltage
2.7
2.85
3.3
Volts
Volts
CC2
CC
2.7
CC3
1
1
2.7
3.6
CCQ1
CCQ2
CCQ3
PP1
I/O Supply Voltage
1.65
1.8
2.5
2.5
2.7
3.6
2.7
2.85
3.3
PP2
Program and Erase Voltage
Block Erase Cycling
Volts
2.7
PP3
3, 4
4
11.4
100,000
12.6
PP4
Cycling
Cycles
NOTES:
1. V
, V
, and V
must share the same supply when all three are between 2.7 V and 3.6 V.
PP3
CC1
CCQ1
2. V Max is 3.3 V on 0.25µm 32-Mbit devices.
CC
3. During read operations or idle time, 5 V may be applied to V indefinitely. V must be at valid levels for
PP
PP
program and erase operations
4. Applying V = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on
PP
the main blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of
PP
80 hours maximum. See Section 3.4 for details.
4.3
Capacitance
T
= 25 °C, f = 1 MHz
A
Sym
Parameter
Notes
Typ
Max
Units
Conditions
= 0 V
C
C
Input Capacitance
Output Capacitance
1
1
6
8
pF
pF
V
IN
IN
10
12
V
= 0 V
OUT
OUT
NOTE: Sampled, not 100% tested.
3UHOLPLQDU\
19
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.4
DC Characteristics
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit
Test Conditions
CCQ
Note
Typ
Max
Typ
Max
Typ
Max
V
V
V
= V Max
CC
CC
I
Input Load Current
1,2
± 1
± 1
± 1
µA
= V
Max
LI
CCQ
CCQ
= V
or GND
IN
CCQ
V
V
V
= V Max
CC
CC
I
Output Leakage Current
1,2
1,2
± 10
15
35
15
25
18
18
5
± 10
50
50
20
25
15
15
5
± 10
250
250
20
µA
µA
µA
µA
µA
mA
mA
µA
= V
Max
LO
CCQ
CCQ
= V
or GND
IN
CCQ
V
Standby Current for
V
= V Max
CC
CC
CC
7
18
7
20
20
7
150
150
7
0.18 Micron Product
CE# = RP# = V
or during Program/
Erase Suspend
CCQ
I
I
I
CCS
CCD
CCR
V
Standby Current for
CC
0.25 Micron and
0.4 Micron Product
1,2
WP# = V
or GND
CCQ
V
Power-Down Current
CC
1,2
V
V
V
= V Max
CC
for 0.18 Micron Product
CC
= V
Max
CCQ
CCQ
V
Power-Down Current
= V
or GND
CC
IN
CCQ
for 0.25 Micron and
0.4 Micron Product
1,2
7
7
7
25
RP# = GND ± 0.2 V
V
Read Current for
CC
V
V
= V Max
CC
1,2,3
1,2,3
9
8
9
15
CC
0.18 Micron Product
= V
Max
CCQ
CCQ
OE# = V , CE# =V
f = 5 MHz, I
Inputs = V or V
IH
IL
V
Read Current for
CC
=0 mA
OUT
0.25 and 0.4 Micron
Product
10
0.2
8
9
15
IL
IH
V
Deep Power-Down
RP# = GND ± 0.2 V
PP
I
I
0.2
0.2
5
PPD
PPR
Current
V
V
V
V
≤ V
≤ V
> V
PP
PP
PP
PP
CC
2
±15
2
±15
2
±15
µA
µA
CC
V
Read Current
1,4
PP
50
200
50
200
50
200
CC
=V
PP1, 2, 3
18
8
55
15
55
30
18
10
18
10
55
30
55
30
18
10
18
10
55
30
55
30
mA
mA
mA
mA
V
+ V Program
Program in Progress
CC
PP
Current for 0.18 Micron
Product
1,2,4
V
= V
PP
PP4
Program in Progress
I
I
CCW+
PPW
V
=V
PP
PP1, 2, 3
18
10
V
+ V Program
PP
Program in Progress
CC
Current for 0.25 Micron
and 0.4 Micron Product
1,2,4
V
= V
PP
PP4
Program in Progress
20
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
DC Characteristics, Continued
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit
Test Conditions
CCQ
Note
Typ
Max
Typ
Max
Typ
Max
V
= V
PP1, 2, 3
PP
16
45
21
45
21
45
mA
mA
mA
mA
Program in
Progress
V
+ V Erase Current
PP
CC
1,2,4
for 0.18 Micron Product
V
= V
PP4
PP
16
20
16
45
45
45
16
21
16
45
45
45
16
21
16
45
45
45
Program in
Progress
I
CCE
+I
PPE
V
= V
PP PP1, 2, 3
Program in
Progress
V
+ V Erase Current
PP
CC
for 0.25 Micron and 0.4
Micron Product
1,2,4
1,4
V
= V
PP4
PP
Program in
Progress
V
= V
PP1, 2, 3, 4
PP
I
V
Erase Suspend
Program or Erase
Suspend in
Progress
PPES
PP
50
200
50
200
50
200
µA
Current
I
PPWS
DC Characteristics, Continued
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit
Test Conditions
CCQ
Note
Min
Max
Min
Max
Min
Max
V
*
CC
V
Input Low Voltage
–0.4
–0.4
0.4
–0.4
0.4
V
V
IL
0.22 V
V
V
V
V
V
CCQ
CCQ
CCQ
CCQ
CCQ
V
Input High Voltage
2.0
IH
+0.3V –0.4V +0.3V –0.4V +0.3V
V
V
= V Min
CC
CC
V
Output Low Voltage
Output High Voltage
–0.1
0.1
-0.1
0.1
-0.1
0.1
1.5
V
= V
Min
OL
CCQ
CCQ
I
= 100 µA
OL
V
V
= V Min
CC
CC
V
V
V
CCQ
–0.1V
CCQ
CCQ
V
V
V
V
= V
Min
OH
CCQ
CCQ
–0.1V
–0.1V
I
= –100 µA
OH
Complete Write
Protection
V
Lock-Out Voltage
5
1.5
3.6
1.5
PPLK
PP
V
V
V
V
5
5
2.7
V
V
V
V
PP1
PP2
PP3
PP4
2.7
2.85
12.6
V
during Program and
PP
Erase Operations
5
2.7
3.3
5,6
11.4
1.5
12.6
11.4
1.5
11.4
12.6
V
Prog/Erase
CC
V
1.5
1.2
V
V
LKO
Lock Voltage
V
Prog/Erase
CCQ
V
1.2
1.2
LKO2
Lock Voltage
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V , T = +25 °C.
CC
A
3UHOLPLQDU\
21
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2. Since each column lists specifications for a different V and V
voltage range combination, the test
CCQ
CC
conditions V Max, V
Max, V Min, and V
Min refer to the maximum or minimum V or V
CC
CCQ
CC
CCQ CC CCQ
voltage listed at the top of each column. V Max is 3.3 V on 0.25µm 32-Mbit devices.
CC
3. Automatic Power Savings (APS) reduces I
4. Sampled, not 100% tested.
to approximately standby levels in static operation.
CCR
5. Erase and program are inhibited when V < V
and not guaranteed outside the valid V ranges of
PP
PP
PPLK
V
, V
V
and V
For read operations or during idle time, a 5 V supply may be applied to V
PP1
PP2, PP3
P
P
4
.
P
P
indefinitely. However, V must be at valid levels for program and erase operations.
PP
6. Applying V = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
PP
main blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours
PP
maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to
V
indefinitely. However, V must be at valid levels for program and erase operations.
PP
PP
Figure 5. Input/Output Reference Waveform
VCCQ
VCCQ
VCCQ
2
OUTPUT
INPUT
TEST POINTS
2
0.0
0580_05
NOTE: AC test inputs are driven at V
for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
CCQ
timing ends, at V
/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
CCQ
when V
= V
Min.
CCQ
CCQ
Figure 6. Test Configuration
V
CCQ
R
R
1
Device
under
Test
Out
CL
2
0580_06
NOTE: See table for component values.
Test Configuration Component Values for Worst
Case Speed Conditions
Test Configuration
CL (pF)
R1 (Ω)
R2 (Ω)
V
V
V
Standard Test
Standard Test
Standard Test
50
50
50
25 K
14.5 K
16 K
25 K
14.5 K
16 K
CCQ1
CCQ2
CCQ3
NOTE: C includes jig capacitance.
L
22
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.5
AC Characteristics —Read Operations
Density
Product
4/8 Mbit
90 ns
110 ns
3.0 V–3.6 V 2.7 V–3.6 V
#
Sym
Parameter
Unit
V
3.0 V–3.6 V
2.7 V–3.6 V
CC
Min
Max
Min
Max
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
Read Cycle Time
80
90
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address to Output Delay
CE# to Output Delay(1)
OE# to Output Delay(1)
RP# to Output Delay
CE# to Output in Low Z(2)
OE# to Output in Low Z(2)
CE# to Output in High Z(2)
OE# to Output in High Z(2)
80
80
90
90
100
100
30
110
110
30
AVQV
t
t
ELQV
30
30
GLQV
PHQV
t
600
600
600
600
t
0
0
0
0
0
0
0
0
ELQX
GLQX
EHQZ
t
t
t
25
25
25
25
25
25
25
25
GHQZ
Output Hold from Address,
CE#, or OE# Change,
R10
t
0
0
0
0
ns
OH
Whichever Occurs First(2)
NOTES:
1. OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum allowable
input slew rate.
3UHOLPLQDU\
23
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
Product
VCC
16 Mbit
90 ns
70 ns
80 ns
110 ns
3.0 V–3.6 V 2.7 V–3.6 V
Para-
meter
#
Sym
Unit
2.7 V–3.6 V
2.7 V–3.6 V
3.0 V–3.6 V
2.7 V–3.6 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
R1
R2
tAVAV Read Cycle Time
70
80
80
90
100
110
ns
ns
Address to Output
tAVQV
Delay
70
70
80
80
80
80
90
90
100
100
110
110
CE# to Output
tELQV
R3
ns
Delay(1)
OE# to Output
tGLQV
R4
R5
R6
20
20
30
30
30
30
ns
ns
ns
Delay(1)
tPHQV RP# to Output Delay
150
150
600
600
600
600
CE# to Output in
tELQX
0
0
0
0
0
0
0
0
0
0
0
0
Low Z(2)
OE# to Output in
R7
R8
R9
tGLQX
ns
ns
ns
Low Z(2)
CE# to Output in
tEHQZ
20
20
20
20
25
25
25
25
25
25
25
25
High Z(2)
OE# to Output in
tGHQZ
High Z(2)
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First(2)
R10
tOH
0
0
0
0
0
0
ns
NOTES:
1. OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
24
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
Product
32 Mbit
100 ns
70 ns
90 ns
110 ns
Para-
meter
#
Sym
Unit
V
2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2.7 V–3.3 V
CC
Min Max Min Max Min Max Min Max Min Max Min Max
R1
R2
t
Read Cycle Time
70
90
90
100
100
110
ns
ns
AVAV
Address to Output
Delay
t
70
70
90
90
90
90
100
100
30
100
100
30
110
110
30
AVQV
CE# to Output
Delay(1)
R3
R4
R5
R6
R7
R8
R9
t
ns
ns
ns
ns
ns
ns
ns
ELQV
GLQV
PHQV
OE# to Output
Delay(1)
t
20
20
30
RP# to Output
Delay
t
150
150
600
600
600
600
CE# to Output in
Low Z(2)
t
0
0
0
0
0
0
0
0
0
0
0
0
ELQX
GLQX
EHQZ
GHQZ
OE# to Output in
Low Z(2)
t
t
CE# to Output in
High Z(2)
20
20
20
20
25
25
25
25
25
25
25
25
OE# to Output in
High Z(2)
t
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First(2)
R10
t
0
0
0
0
0
0
ns
OH
NOTES:
1. OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
3UHOLPLQDU\
25
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
Product
64 Mbit
90 ns
2.7 V–3.6 V
100 ns
#
Sym
Parameter
Unit
V
2.7 V–3.6 V
CC
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
Read Cycle Time
90
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
Address to Output Delay
CE# to Output Delay
90
90
100
100
20
AVQV
ELQV
GLQV
PHQV
1
1
t
OE# to Output Delay
20
t
RP# to Output Delay
150
150
t
CE# to Output in Low Z
OE# to Output in Low Z
CE# to Output in High Z
OE# to Output in High Z
Output Hold from Address, CE#, or
2
2
2
2
0
0
0
0
ELQX
GLQX
EHQZ
GHQZ
t
t
20
20
20
20
t
R10
t
2
0
0
ns
OH
OE# Change, Whichever Occurs First
NOTES:
1. OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
2. Sampled, but not 100% tested.
See Figure 7 for the AC waveform for read operations.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
Figure 7. AC Waveform: Read Operations
Device
Address Selection
Standby
Data Valid
VIH
Address Stable
ADDRESSES (A)
CE# (E)
VIL
VIH
R1
VIL
R8
R9
VIH
VIL
OE# (G)
VIH
VIL
WE# (W)
R4
R3
R7
R10
VOH
VOL
R6
High Z
High Z
DATA (D/Q)
Valid Output
R2
VIH
VIL
RP# (P)
R5
26
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.6
AC Characteristics —Write Operations
Density
Product
4/8 Mbit
90 ns
110 ns
#
Sym
Parameter
Unit
3.0 V – 2.7 V –
3.0 V –
3.6 V
2.7 V –
3.6 V
V
CC
3.6 V
Min
3.6 V
Min
Note
Min
Min
t
t
/
PHWL
PHEL
W1
W2
W3
W4
W5
W6
W7
W8
W9
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
600
0
600
0
600
0
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
/
ELWL
WLEL
0
70
60
70
0
t
t
/
ELEH
1
2
2
70
50
70
0
70
50
70
0
70
60
70
0
WLWH
t
t
/
/
/
/
/
DVWH
DVEH
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
t
t
AVWH
AVEH
t
t
WHEH
EHWH
t
t
WHDX
EHDX
2
2
1
0
0
0
0
t
t
WHAX
EHAX
0
0
0
0
t
t
WHWL /
EHEL
30
30
30
30
t
t
/
VPWH
VPEH
W10
W11
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
3
3
200
0
200
0
200
0
200
0
ns
ns
PP
t
QVVL
PP
NOTES:
1. Refer to command definition table (Table 6) for valid A or D
.
IN
IN
2. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
WP
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, Write pulse width
WP
WLWH
ELEH
WLEH
ELWH
high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
WPH
(whichever goes low first). Hence, t
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
3. Sampled, but not 100% tested.
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
3UHOLPLQDU\
27
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
Product
16 Mbit
90 ns
3.0 V –
70 ns
80 ns
110 ns
#
Sym
Parameter
Unit
2.7 V –
3.6 V
2.7 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
2.7 V –
3.6 V
VCC
3.6 V
3.6 V
Note
Min
Min
Min
Min
Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#)
Going Low
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
150
150
600
0
600
600
0
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#) Going
Low
0
45
40
50
0
0
50
40
50
0
0
70
50
70
0
0
70
60
70
0
tELEH
tWLWH
/
WE# (CE#) Pulse Width
1
2
2
70
50
70
0
70
60
70
0
tDVWH
tDVEH
/
/
/
/
/
Data Setup to WE# (CE#) Going High
tAVWH
tAVEH
Address Setup to WE# (CE#) Going
High
tWHEH
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
tWHDX
tEHDX
Data Hold Time from WE# (CE#) High
2
2
1
0
0
0
0
0
0
tWHAX
tEHAX
Address Hold Time from WE# (CE#)
High
0
0
0
0
0
0
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3
3
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
W11 tQVVL
NOTES:
1. Refer to command definition table (Table 6) for valid A or D
.
IN
IN
2. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going
WP
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, Write pulse width
WP
WLWH
ELEH
WLEH
ELWH
high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
WPH
(whichever goes low first). Hence, t
3. Sampled, but not 100% tested.
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
28
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
Product
32 Mbit
90 ns
70 ns
90 ns
110 ns
#
Sym
Parameter
Unit
2.7 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
3.3 V
2.7 V –
3.3 V
3.0 V –
3.3 V
2.7 V –
3.3 V
VCC
Note
Min
Min
Min
Min
Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#)
Going Low
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
150
150
600
0
600
600
0
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#) Going
Low
0
45
40
50
0
0
60
40
60
0
0
70
50
70
0
0
70
60
70
0
tELEH
tWLWH
/
WE# (CE#) Pulse Width
1
2
2
70
50
70
0
70
60
70
0
tDVWH
tDVEH
/
/
/
/
/
Data Setup to WE# (CE#) Going High
tAVWH
tAVEH
Address Setup to WE# (CE#) Going
High
tWHEH
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
tWHDX
tEHDX
Data Hold Time from WE# (CE#) High
2
2
1
0
0
0
0
0
0
tWHAX
tEHAX
Address Hold Time from WE# (CE#)
High
0
0
0
0
0
0
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3
3
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
W11 tQVVL
NOTES:
1. Refer to command definition table (Table 6) for valid A or D
.
IN
IN
2. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
WP
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, Write pulse width
WP
WLWH
ELEH
WLEH
ELWH
high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
WPH
(whichever goes low first). Hence, t
3. Sampled, but not 100% tested.
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
3UHOLPLQDU\
29
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
Product
64 Mbit
90 ns
100 ns
#
Sym
Parameter
Unit
2.7 V –
3.6 V
2.7 V –
3.6 V
V
CC
Note
Min
Min
t
/
PHWL
W1
W2
W3
W4
W5
W6
W7
W8
W9
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PHEL
t
/
ELWL
0
60
40
60
0
0
70
40
60
0
t
WLEL
t
t
/
ELEH
1
2
2
WLWH
t
/
DVWH
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
t
DVEH
t
/
/
AVWH
t
AVEH
t
t
t
t
t
WHEH
t
EHWH
/
WHDX
2
2
1
0
0
t
EHDX
/
WHAX
0
0
t
EHAX
WHWL /
30
30
t
EHEL
/
VPWH
W10
W11
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
3
3
200
0
200
0
ns
ns
PP
PP
t
VPEH
t
QVVL
NOTES:
1. Refer to command definition table (Table 6) for valid A or D
.
IN
IN
2. Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going
WP
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, Write pulse width
WP
WLWH
ELEH
WLEH
ELWH
high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
WPH
(whichever goes low first). Hence, t
3. Sampled, but not 100% tested.
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
30
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.7
Program and Erase Timings
V
2.7 V–3.6 V
11.4 V–12.6 V
PP
Symbol
Parameter
Units
Notes
Typ(1)
Max
Typ(1)
Max
8-KB Parameter Block
Program Time (Byte)
2, 3
0.16
0.10
1.2
0.48
0.08
0.24
s
s
s
t
t
BWPB
4-KW Parameter Block
Program Time (Word)
2, 3
0.30
3.7
0.03
0.6
0.12
1.7
64-KB Main Block
Program Time (Byte)
2, 3, 4
BWMB
32-KW Main Block
Program Time(Word)
2, 3
2, 3, 4
2,3
0.8
17
12
2.4
165
200
0.24
8
1
s
Byte Program Time
185
185
µs
µs
Word Program Time for
0.18 Micron Product
8
t
/ t
WHQV1 EHQV1
Word Program Time for 0.25
Micron and 0.4 Micron Products
2, 3
2, 3, 4
2, 3
22
1
200
4
8
185
4
µs
s
8-KB Parameter Block
Erase Time (Byte)
0.8
0.4
1
t
t
/ t
WHQV2 EHQV2
4-KW Parameter Block
Erase Time (Word)
0.5
1
4
4
s
64-KB Main Block
Erase Time (Byte)
2, 3, 4
2, 3
5
5
s
/ t
WHQV3 EHQV3
32-KW Main Block
Erase Time (Word)
1
5
0.6
5
s
t
t
/ t
Program Suspend Latency
Erase Suspend Latency
5
5
10
20
5
5
10
20
µs
µs
WHRH1 EHRH1
/ t
WHRH2 EHRH2
NOTES:
1. Typical values measured at nominal voltages and T = +25 °C.
A
2. Excludes external system-level overhead.
3. Sampled, not 100% tested.
4. x8 not available on 0.18 µm offerings
3UHOLPLQDU\
31
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 8. AC Waveform: Program and Erase Operations
A
B
C
D
E
F
VIH
ADDRESSES [A]
CE#(WE#) [E(W)]
AIN
AIN
VIL
VIH
W8
(Note 1)
W5
VIL
VIH
W6
W2
OE# [G]
VIL
VIH
W9
(Note 1)
WE#(CE#) [W(E)]
VIL
W3
W4
W7
VIH
VIL
High Z
W1
Valid
SRD
DATA [D/Q]
DIN
DIN
DIN
VIH
VIL
VIH
VIL
RP# [P]
WP#
W10
W11
VPPH 2
VPPH
VPPLK
VIL
1
V
[V]
PP
0580_08
NOTES:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading
Status Register Data.
A. V Power-Up and Standby.
CC
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
32
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
Reset Operations
Figure 9. AC Waveform: Deep Power-Down/Reset Operation
V
IH
RP# (P)
tPHQV
tPHWL
tPHEL
VIL
tPLPH
(A) Reset during Read Mode
Abort
Complete
t PLRH
tPHQV
tPHWL
tPHEL
VIH
VIL
RP# (P)
t PLPH
tPLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
tPHQV
tPHWL
tPHEL
Down
t PLRH
VIH
VIL
RP# (P)
t PLPH
(C) Reset Program or Block Erase,
>
tPLPH t PLRH
0580_09
Reset Specifications
V
= 2.7 V–3.6 V
CC
Symbol
Parameter
Notes
Unit
Min
Max
RP# Low to Reset during Read
t
t
1,2
2,3
100
ns
PLPH
(If RP# is tied to V , this specification is not applicable)
CC
RP# Low to Reset during Block Erase or Program
22
µs
PLRH
NOTES:
1. If t
is <100 ns the device may still RESET but this is not guaranteed
PLPH
2. .Sampled, but not 100% tested.
3. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete
within 100 ns.
3UHOLPLQDU\
33
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
6.0
Ordering Information
T E 2 8 F 3 2 0 B 3 T C 7 0
Access Speed (ns)
(70, 80, 90, 100, 110)
Package
TE = 40-Lead/48-Lead TSOP
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
Lithography
Not Present = 0.4 µm
A = 0.25 µm
Product line designator
for all Intel® Flash products
C = 0.18 µm
T = Top Blocking
Device Density
B = Bottom Blocking
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
400 = x16 (4 Mbit)
Product Family
B3 = 3 Volt Advanced Boot Block
V
V
CC = 2.7 V - 3.6 V
PP = 2.7 V - 3.6 V or
11.4 V - 12.6 V
016 = x8 (16 Mbit)
008 = x8 (8 Mbit)
004 = x8 (4 Mbit)
34
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Ordering Information Valid Combinations
40-Lead TSOP
48-Ball µBGA* CSP(1,2)
48-Lead TSOP
48-Ball µBGA CSP(1,2)
48-Ball VF BGA
TE28F640B3TC90
TE28F640B3BC90
TE28F640B3TC100
TE28F640B3BC100
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
TE28F160B3BC80
TE28F160B3TA90(3)
TE28F160B3BA90(3)
TE28F160B3TA110(3)
TE28F160B3BA110(3)
TE28F800B3TA90(3)
TE28F800B3BA90(3)
TE28F800B3TA110(3)
TE28F800B3BA110(3)
TE28F400B3T90
GT28F640B3TC90
GT28F640B3BC90
GT28F640B3TC100
GT28F640B3BC100
Ext. Temp.
64 Mbit
GE28F320B3TC70
GE28F320B3BC70
GE28F320B3TC90
GE28F320B3BC90
Ext. Temp.
32 Mbit
GT28F320B3TA100
GT28F320B3BA100
GT28F320B3TA110
GT28F320B3BA110
GE28F160B3TC70
GE28F160B3BC70
GE28F160B3TC80
GE28F160B3BC80
Ext. Temp.
16 Mbit
TE28F016B3TA90(3)
TE28F016B3BA90(3)
TE28F016B3TA110(3)
TE28F016B3BA110(3)
TE28F008B3TA90(3)
TE28F008B3BA90(3)
TE28F008B3TA110(3)
TE28F008B3BA110(3)
TE28F004B3T90
GT28F016B3TA90(3)
GT28F016B3BA90(3)
GT28F016B3TA110(3)
GT28F016B3BA110(3)
GT28F008B3T90
GT28F160B3TA90(3)
GT28F160B3BA90(3)
GT28F160B3TA110(3)
GT28F160B3BA110(3)
GT28F800B3T90
GE28F800B3TA90
GE28F800B3BA90
GE28F008B3TA90
GE28F008B3BA90
GT28F008B3B90
GT28F800B3B90
Ext. Temp.
8 Mbit
GT28F008B3T110
GT28F008B3B110
GT28F800B3T110
GT28F800B3B110
TE28F004B3B90
TE28F400B3B90
Ext. Temp
4 Mbit
TE28F004B3T110
TE28F004B3B110
TE28F400B3T110
TE28F400B3B110
NOTES:
1. The 48-ball µBGA package top side mark reads F160B3 [or F800B3]. This mark is identical for both x8 and
x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture.
However, once the devices are removed from the shipping media, it may be difficult to differentiate based on
the top side mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for
further details) enables x8 and x16 µBGA package product differentiation.
2. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the
first character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other
assembly codes without an “E” or “S” as the first character are production units.
3. Product can be ordered in either 0.25 µm or 0.4 µm material. The “A” before the access speed specifies
0.25 µm material. For new designs, Intel recommends using 0.25 µm Advanced Boot Block devices.
3UHOLPLQDU\
35
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.0
Additional Information
Order Number
Document/Tool
297948
292199
292200
Note 2
3 Volt Advanced Boot Block Flash Memory Family Specification Update
AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory
AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory
3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)
http://developer.intel.com/design/flash/swtools
Contact your Intel Representative
297874
Intel® Flash Data Integrator (IFDI) Software Developer’s Kit
IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical
documentation and tools.
3. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our
microsite at http://developer.intel.com/design/flash/abblock.
36
3UHOLPLQDU\
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Appendix A Write State Machine Current/Next States
Command Input (and Next State)
Data
When
Read
Read
Array
(FFH)
Program
Setup (10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
Current State SR.7
Read
Array
Program
Setup
Erase
Setup
Read
Read
Array
Read
Read Array
“1”
“1”
Array
Read Array
Read Array
Read Array
Status
Identifier
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
Read Status
Status
Read
Identifier
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
“1”
“1”
Identifier
Status
Prog. Setup
Program (Command Input = Data to be Programmed)
Prog.Susp.
Program
(continue)
“0”
“1”
Status
Status
Program (continue)
to Rd.
Status
Program (continue)
Prog.
Sus. to
Read
Prog.
Susp. to
Read
Prog.
Sus. to
Read
Prog.
Susp. to
Read
Program
Suspend to
Read Status
Program
Susp. to
Read Array
Program Suspend
to Read Array
Program
(continue)
Program
(continue)
Array
Status
Array
Identifier
Prog.
Susp. to
Read
Prog.
Susp. to
Read
Prog.
Sus. to
Read
Prog.
Susp. to
Read
Program
Suspend to
Read Array
Program
Susp. to
Program Suspend
to Read Array
Program
Program
“1”
“1”
Array
(continue)
(continue)
Read Array
Array
Status
Array
Identifier
Prog.
Susp. to
Read
Prog.
Susp. to
Read
Prog.
Sus. to
Read
Prog.
Susp. to
Read
Prog.Susp.to
Read
Identifier
Program
Susp. to
Read Array
Program Suspend
to Read Array
Program
(continue)
Program
(continue)
Identifier
Array
Status
Array
Identifier
Program
Read
Array
Program
Setup
Erase
Setup
Read
Read
Array
Read
“1”
“1”
“1”
Status
Status
Status
Read Array
Erase
(complete)
Status
Identifier
Erase
Erase
Erase Setup
Erase Command Error
Erase Command Error
(continue) Cmd. Error (continue)
Erase Cmd.
Error
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
Read Array
EraseSus.
to Read
Status
Erase
“0”
“1”
Status
Status
Erase (continue)
Erase (continue)
(continue)
Erase
Susp. to
Read
Erase
Erase
Erase
Erase
Suspend to
Status
Erase
Ers. Susp.
to Read
Identifier
Program
Setup
Susp. to
Read
Susp. to Susp. to
Erase
Erase
Erase
Susp. to
Erase
Erase
Erase
Read
Status
Read
Array
Read Array
Array
Array
Erase
Susp. to
Read
Erase
Susp. to
Read
Erase
Erase
Erase Susp.
to Read
Array
Erase
Susp. to
Read Array
Ers. Susp.
to Read
Identifier
Program
Setup
Susp. to Susp. to
“1”
Array
Read
Status
Read
Array
Array
Array
Erase
Susp. to
Read
Erase
Susp. to
Read
Erase
Erase
Erase Susp.
to Read
Identifier
Erase
Susp. to
Read Array
Ers. Susp.
to Read
Identifier
Program
Setup
Susp. to Susp. to
“1”
“1”
Identifier
Status
Read
Status
Read
Array
Array
Array
Erase
(complete)
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
Read Array
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix B Architecture Block Diagram
DQ0-DQ15
VCCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
Input Buffer
VPP
Address
Latch
X-Decoder
VCC
GND
Address
Counter
0580-C1
38
3UHOLPLQDU\
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Appendix C Word-Wide Memory Map Diagrams
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW)
Size
(KW)
16 Mbit
32 Mbit
8 Mbit
16 Mbit
32 Mbit
4
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF 0E8000-0EFFFF
E0000-E7FFF 0E0000-0E7FFF
D8000-DFFFF 0D8000-0DFFFF
D0000-D7FFF 0D0000-0D7FFF
C8000-CFFFF 0C8000-0CFFFF
This column continues on next page
This column continues on next page
3UHOLPLQDU\
39
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit and 32-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
16 Mbit
Bottom Boot
16 Mbit
Size
(KW)
Size
(KW)
32 Mbit
32 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
C0000-C7FFF 0C0000-0C7FFF
B8000-BFFFF 0B8000-0BFFFF
B0000-B7FFF
0B0000-0B7FFF
A8000-AFFFF 0A8000-0AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4
4
4
4
4
4
4
40
3UHOLPLQDU\
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4-Mbit and 8-Mbit Word-Wide Memory Addressing
Top Boot
Bottom Boot
Size
(KW)
Size
(KW)
4 Mbit
4 Mbit
8 Mbit
3F000-3FFFF
3E000-3EFFF
3D000-3DFFF
3C000-3CFFF
3B000-3BFFF
3A000-3AFFF
39000-39FFF
38000-38FFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
7F000-7FFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
7E000-7EFFF
7D000-7DFFF
7C000-7CFFF
7B000-7BFFF
7A000-7AFFF
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
4
4
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4
4
4
4
4
4
32
32
32
32
32
32
32
4
4
4
4
4
4
4
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
32 Mbit
Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
64 Mbit
4
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
This column continues on next page
This column continues on next page
42
3UHOLPLQDU\
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16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
32 Mbit
Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
64 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-21FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
F0000-F7FFF
F0000-F7FFF
E8000-EFFFF
E8000-EFFFF
E0000-E7FFF
E0000-E7FFF
D8000-DFFFF
D8000-DFFFF
D0000-D7FFF
D0000-D7FFF
C8000-CFFFF
C8000-CFFFF
This column continues on next page
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3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
32 Mbit
Bottom Boot
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
32 Mbit
64 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4
4
4
4
4
4
4
44
3UHOLPLQDU\
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Appendix D Byte-Wide Memory Map Diagrams
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
8 Mbit
Size (KB)
8 Mbit
16 Mbit
Size (KB)
16 Mbit
8
FE000-FFFFF
FC000-FDFFF
FA000-FBFFF
F8000-F9FFF
F6000-F7FFF
F4000-F5FFF
F2000-F3FFF
F0000-F1FFF
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
1FE000-1FFFFF
1FC000-1FDFFF
1FA000-1FBFFF
1F8000-1F9FFF
1F6000-1F7FFF
1F4000-1F5FFF
1F2000-1F3FFF
1F0000-1F1FFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
000000-00FFFF
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
8
8
8
8
8
8
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1F0000-1FFFFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
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This column continues on next page
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8-Mbit and 16-Mbit Byte-Wide Memory Addressing (Continued)
Top Boot
8 Mbit
Bottom Boot
Size (KB)
16 Mbit
Size (KB)
8 Mbit
16 Mbit
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
00E000-00FFFF
00C000-00DFFF
00A000-00BFFF
008000-009FFF
006000-007FFF
004000-005FFF
002000-003FFF
000000-001FFF
F0000-FFFFF
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
8
8
8
8
8
8
8
46
3UHOLPLQDU\
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4-Mbit Byte-Wide Memory Addressing
Bottom Boot
Top Boot
Size
(KB)
Size
4 Mbit
4 Mbit
(KB)
8
8
7E000-7FFFF
7C000-7DFFF
7A000-7BFFF
78000-79FFF
76000-77FFF
74000-75FFF
72000-73FFF
70000-71FFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
64
64
64
64
64
64
64
8
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
8
8
8
8
8
8
64
64
64
64
64
64
64
8
8
8
8
8
8
8
3UHOLPLQDU\
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix E Program and Erase Flowcharts
Figure 10. Program Flowchart
Start
Bus Operation
Command
Comments
Write
Write
Program Setup
Program
Data = 40H
Write 40H
Data = Data to Program
Addr = Location to Program
Program Address/Data
Read Status Register
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Yes
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Standby
Command
Comments
Check SR.3
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4
1 = VPP Program Error
Standby
0
SR.4 =
0
Check SR.1
1
1
1 = Attempted Program to
Locked Block - Program
Aborted
Standby
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Program Successful
0580_E1
48
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 11. Program Suspend/Resume Flowchart
Bus
Operation
Command
Comments
Data = B0H
Start
Write B0H
Program
Suspend
Write
Write
Addr = X
Data = 70H
Addr = X
Read Status
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Check SR.2
1 = Program Suspended
0 = Program Completed
0
0
Standby
Write
SR.7 =
1
Data = FFH
Addr = X
Read Array
SR.2 =
Program Completed
Read array data from block
other than the one being
programmed.
Read
1
Program
Resume
Data = D0H
Addr = X
Write
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
0580_E2
3UHOLPLQDU\
49
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 12. Block Erase Flowchart
Start
Bus Operation
Command
Comments
Data = 20H
Write
Erase Setup
Addr = Within Block to Be
Erased
Write 20H
Data = D0H
Write
Erase Confirm
Addr = Within Block to Be
Erased
Write D0H and
Block Address
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Suspend
Check SR.7
1 = WSM Ready
0 = WSM Busy
Erase Loop
Standby
No
0
Yes
SR.7 =
Suspend Erase
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
1
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Command
Comments
Check SR.3
Standby
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4,5
Standby
Standby
Standby
Both 1 = Command Sequence
Error
0
SR.4,5 =
0
1
1
1
Check SR.5
1 = Block Erase Error
Command Sequence
Error
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
SR.5 =
0
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
Attempted Erase of
Locked Block - Aborted
SR.1 =
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
0580_E3
50
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 13. Erase Suspend/Resume Flowchart
Bus Operation
Write
Command
Erase Suspend
Read Status
Comments
Data = B0H
Start
Write B0H
Addr = X
Data = 70H
Addr = X
Write
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
0
Standby
Write
SR.7 =
1
Data = FFH
Addr = X
Read Array
0
SR.6 =
Erase Completed
Read array data from block
other than the one being
erased.
Read
1
Data = D0H
Addr = X
Write
Erase Resume
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
0580_E4
3UHOLPLQDU\
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