TF28F010-90 [INTEL]
Flash, 128KX8, 90ns, PDSO32, 0.310 X 0.720 INCH, REVERSE, TSOP-32;
| 型号： | TF28F010-90 |
| 厂家： | 
INTEL |
| 描述： | Flash, 128KX8, 90ns, PDSO32, 0.310 X 0.720 INCH, REVERSE, TSOP-32 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y
Y
Y
Flash Electrical Chip-Erase
Ð 1 Second Typical Chip-Erase
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Quick Pulse Programming Algorithm
Ð 10 ms Typical Byte-Program
Ð 2 Second Chip-Program
Y
Y
Y
Noise Immunity Features
g
Ð Maximum Latch-Up Immunity
Ð
10% V
Tolerance
CC
Y
Y
Y
100,000 Erase/Program Cycles
through EPI Processing
g
12.0V 5% V
PP
ETOXTM Nonvolatile Flash Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
High-Performance Read
Ð 65 ns Maximum Access Time
Y
CMOS Low Power Consumption
Ð 10 mA Typical Active Current
Ð 50 mA Typical Standby Current
Ð 0 Watts Data Retention Power
JEDEC-Standard Pinouts
Ð 32-Pin Plastic Dip
Ð 32-Lead PLCC
Ð 32-Lead TSOP
(See Packaging Spec., Order 231369)
Y
Integrated Program/Erase Stop Timer
Ý
Y
Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process
technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V V supply, the 28F010 performs
PP
100,000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase
algorithms.
Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 65 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 mA trans-
lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
b
on address and data pins, from 1V to V
a
1V.
CC
With Intel’s ETOX process base, the 28F010 builds on years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290207-010
28F010
290207–1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
A –A
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
0
16
DQ –DQ
0
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
7
Ý
CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers,
Ý
Ý
decoders and sense amplifiers. CE is active low; CE high
deselects the memory device and reduces power consumption to
standby levels.
Ý
OE
INPUT
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
Ý
during a read cycle. OE is active low.
Ý
WE
WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
Ý
and data is latched on the rising edge of the WE pulse.
s
Note: With V
6.5V, memory contents cannot be altered.
PP
V
PP
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
g
DEVICE POWER SUPPLY (5V 10%)
V
V
CC
GROUND
SS
NC
NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.
2
28F010
28F010
290207–3
290207–2
290207–17
290207–18
Figure 2. 28F010 Pin Configurations
3
28F010
Material and labor costs associated with code
changes increases at higher levels of system inte-
gration Ð the most costly being code updates after
sale. Code ‘‘bugs’’, or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the re-
moval of EPROM components or entire boards. With
the 28F010, code updates are implemented locally
via an edge-connector, or remotely over a commun-
cation link.
APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These fea-
tures make the 28F010 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F010’s reprogrammability and non-
volatility make it the obvious and ideal replacement
for EPROM.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption Ð a consideration particularly impor-
tant in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and applica-
tion code. With updatable code, system manufactur-
ers can easily accommodate last-minute changes as
revisions are made.
Flash memory’s electrical chip erasure, byte pro-
grammability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a ‘‘blank slate’’ in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ‘‘blank slate’’.
In diskless workstations and terminals, network traf-
fic reduces to a minimum and systems are instant-
on. Reliability exceeds that of electromechanical
media. Often in these environments, power interrup-
tions force extended re-boot periods for all net-
worked terminals. This mishap is no longer an issue
if boot code, operating systems, communication pro-
tocols and primary applications are flash-resident in
each terminal.
A high degree of on-chip feature integration simpli-
fies memory-to-processor interfacing. Figure 4 de-
picts two 28F010s tied to the 80C186 system bus.
The 28F010’s architecture minimizes interface cir-
cuitry needed for complete in-circuit updates of
memory contents.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F010 flash memory offers a solid
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With stan-
dard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume nec-
essary to layout multiple 28F010s. TSOP is particu-
larly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
state alternative in
a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
‘‘execute in place’’ memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
With cost-effective in-system reprogramming, ex-
tended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today’s designs.
The need for code updates pervades all phases of a
system’s life Ð from prototyping to system manufac-
ture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F010 allows in-
circuit alterability; this eliminates unnecessary han-
dling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexi-
bility.
4
28F010
Figure 3. TSOP Serpentine Layout
5
28F010
290207–4
Figure 4. 28F010 in a 80C186 System
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or out-
put data for erase and program verification.
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power sup-
plies during erasure and programming; and maxi-
mum EPROM compatibility.
Integrated Stop Timer
Successive command write cycles define the dura-
tions of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simpli-
fied timing control over these operations; thus elimi-
nating the need for maximum program/erase timing
specifications. Programming and erase pulse dura-
tions are minimums only. When the stop timer termi-
nates a program or erase operation, the device en-
ters an inactive state and remains inactive until re-
ceiving the appropriate verify or reset command.
In the absence of high voltage on the V pin, the
PP
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelli-
gent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is ap-
plied to the V pin. In addition, high voltage on V
PP
PP
enables erasure and programming of the device. All
functions associated with altering memory con-
tentsÐIntelligent Identifier, erase, erase verify, pro-
gram, and program verifyÐare accessed via the
command register.
Write Protection
The command register is only active when V is at
PP
high voltage. Depending upon the application, the
system designer may choose to make the V pow-
PP
er supply switchableÐavailable only when memory
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
e
updates are desired. When V
V
, the con-
PPL
PP
6
28F010
Table 2. 28F010 Bus Operations
(1)
Ý
Ý
Ý
WE
Mode
Read
V
A
A
9
CE
OE
DQ –DQ
0
PP
0
7
V
A
A
V
V
V
V
V
Data Out
PPL
PPL
PPL
PPL
PPL
PPH
PPH
PPH
PPH
0
9
IL
IL
IH
Output Disable
Standby
V
V
V
V
X
X
V
Tri-State
Tri-State
IL
IH
IH
X
X
V
X
X
IH
READ-ONLY
(2)
(3)
e
e
Intelligent Identifier (Mfr)
V
IL
V
V
V
V
V
V
V
V
V
V
V
V
V
Data
Data
89H
ID
ID
IL
IL
IL
IL
IH
IL
IL
IL
IH
IH
IH
IH
IH
(2)
(3)
Intelligent Identifier (Device)
Read
V
IH
B4H
(4)
V
V
V
V
A
A
Data Out
Tri-State
Tri-State
0
9
Output Disable
X
X
V
READ/WRITE
(5)
Standby
X
X
V
X
X
(6)
Write
A
A
V
V
V
IL
Data In
0
9
IL
IH
NOTES:
1. Refer to DC Characteristics. When V
e
V
PPL
memory contents can be read but not written or erased.
PP
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. V is the Intelligent Identifier high voltage. Refer to DC Characteristics.
ID
e
4. Read operations with V
V
PPH
may access array data or the Intelligent Identifier codes.
PP
a
5. With V at high voltage, the standby current equals I
I
(standby).
PP
PP
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be V or V
CC
.
IH
IL
tents of the register default to the read command,
making the 28F010 a read-only memory. In this
mode, the memory contents cannot be altered.
erase verification. When V is low (V
), the read
PPL
PP
operation can only access the array data.
Output Disable
Or, the system designer may choose to ‘‘hardwire’’
, making the high voltage supply constantly
V
PP
Ý
With OE at a logic-high level (V ), output from the
IH
available. In this case, all Command Register func-
tions are inhibited whenever V is below the write
lockout voltage V
device is disabled. Output pins are placed in a high-
impedance state.
CC
. (See Power Up/Down Protec-
LKO
tion) The 28F010 is designed to accommodate ei-
ther design practice, and to encourage optimization
of the processor-memory interface.
Standby
Ý
With CE at a logic-high level, the standby opera-
tion disables most of the 28F010’s circuitry and sub-
stantially reduces device power consumption. The
outputs are placed in a high-impedance state, inde-
The two-step program/erase write sequence to the
Command Register provides additional software
write protections.
Ý
pendent of the OE signal. If the 28F010 is dese-
lected during erasure, programming, or program/
erase verification, the device draws active current
until the operation is terminated.
BUS OPERATIONS
Read
Intelligent Identifier Operation
The 28F010 has two control functions, both of which
must be logically active, to obtain data at the out-
Ý
puts. Chip-Enable (CE ) is the power control and
should be used for device selection. Output-Enable
The Intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B4H). Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms.
Ý
(OE ) is the output control and should be used to
gate data from the output pins, independent of de-
vice selection. Refer to AC read timing waveforms.
When V is high (V
PP
), the read operation can be
PPH
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
7
28F010
Ý
Ý
With CE and OE at a logic low level, raising A9
to high voltage V (see DC Characteristics) acti-
used to store the command, along with address and
data information needed to execute the command.
ID
vates the operation. Data read from locations 0000H
and 0001H represent the manufacturer’s code and
the device code, respectively.
Ý
The command register is written by bringing WE to
a logic-low level (V ), while CE is low. Addresses
Ý
IL
Ý
are latched on the falling edge of WE , while data is
Ý
latched on the rising edge of the WE pulse. Stan-
dard microprocessor write timings are used.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the tar-
get system. Following a write of 90H to the com-
mand register, a read from address location 0000H
outputs the manufacturer code (89H). A read from
address 0001H outputs the device code (B4H).
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
Write
When low voltage is applied to the V pin, the con-
PP
Device erasure and programming are accomplished
via the command register, when high voltage is ap-
tents of the command register default to 00H, en-
abling read-only operations.
plied to the V
pin. The contents of the register
PP
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.
Placing high voltage on the V pin enables read/
PP
write operations. Device operations are selected by
writing specific data patterns into the command reg-
ister. Table
commands.
3
defines these 28F010 register
The command register itself does not occupy an ad-
dressable memory location. The register is a latch
Table 3. Command Definitions
First Bus Cycle
Bus
Second Bus Cycle
Command
Cycles
Req’d
(1)
(2)
(3)
(1)
(2)
Address
(3)
Data
Operation
Write
Address
Data
Operation
Read Memory
1
3
X
00H
90H
Read Intelligent Identifier
(4)
Codes
Write
IA
Read
IA
ID
(5)
Set-up Erase/Erase
2
2
2
2
2
Write
Write
Write
Write
Write
X
EA
X
20H
A0H
40H
C0H
FFH
Write
Read
Write
Read
Write
X
X
20H
EVD
PD
(5)
Erase Verify
(6)
Set-up Program/Program
PA
X
(6)
Program Verify
X
PVD
FFH
(7)
Reset
X
X
NOTES:
1. Bus operations are defined in Table 2.
e
2. IA
Identifier address: 00H for manufacturer code, 01H for device code.
Erase Address: Address of memory location to be read during erase verify.
Program Address: Address of memory location to be programmed.
e
EA
PA
e
Ý
Addresses are latched on the falling edge of the WE pulse.
e
e
e
89H, Device B4H).
3. ID
Identifier Data: Data read from location IA during device identification (Mfr
e
EVD
e
PD
PVD
Erase Verify Data: Data read from location EA during erase verify.
Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE
Ý
Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
.
e
4. Following the Read int ligent ID command, two read operations access manufacturer and device codes.
e
5. Figure 6 illustrates the Quick Erase Algorithm.
6. Figure 5 illustrates the Quick Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8
28F010
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Read Command
While V is high, for erasure and programming,
PP
memory contents can be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register con-
tents are altered.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The address
for the byte to be verified must be supplied as it is
Ý
latched on the falling edge of the WE pulse. The
register write terminates the erase operation with the
Ý
rising edge of its WE pulse.
The default contents of the register upon V pow-
PP
er-up is 00H. This default value ensures that no spu-
rious alteration of memory contents occurs during
the V power transition. Where the V supply is
PP
PP
hard-wired to the 28F010, the device powers-up and
remains enabled for reads until the command-regis-
ter contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
The 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be ac-
cessible while the device resides in the target sys-
tem. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, mul-
tiplexing high voltage onto address lines is not a de-
sired system-design practice.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is com-
plete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick Erase algorithm, illus-
trates how commands and bus operations are com-
bined to perform electrical erasure of the 28F010.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
The 28F010 contains an Intelligent Identifier opera-
tion to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the com-
mand write, a read cycle from address 0000H re-
trieves the manufacturer code of 89H. A read cycle
from address 0001H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.
Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
Once the program set-up operation is performed,
Ý
the next WE pulse causes a transition to an active
programming operation. Addresses are internally
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Ý
latched on the falling edge of the WE pulse. Data
Ý
WE pulse and terminates with the rising edge of
the next WE pulse (i.e., Erase-Verify Command).
Ý
is internally latched on the rising edge of the WE
Ý
Ý
pulse. The rising edge of WE also begins the pro-
gramming operation. The programming operation
Ý
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased. Also, chip-erasure can only occur when
terminates with the next rising edge of WE , used
to write the program-verify command. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
high voltage is applied to the V pin. In the absence
PP
9
28F010
2 MV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure.
Program-Verify Command
The 28F010 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at ran-
dom. Following each programming operation, the
byte just programmed must be verified.
The 28F010 is capable or 100,000 program/erase
cycles. The device is programmed and erased using
Intel’s Quick Pulse Programming and Quick Erase
algorithms. Intel’s algorithmic approach uses a se-
ries of operations (pulses), along with byte verifica-
tion, to completely and reliably erase and program
the device.
The program-verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the ris-
Ý
ing edge of its WE pulse. The program-verify oper-
ation stages the device for verification of the byte
last programmed. No new address information is
latched.
For further information, see Reliability Report RR-60.
QUICK PULSE PROGRAMMING ALGORITHM
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F010 Quick Pulse Programming algorithm, il-
lustrates how commands are combined with bus op-
erations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
The Quick Pulse Programming algorithm uses pro-
gramming operations of 10 ms duration. Each opera-
tion is followed by a byte verification to determine
when the addressed byte has been successfully pro-
grammed. The algorithm allows for up to 25 pro-
gramming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with V at high voltage. Figure 5 illus-
PP
trates the Quick Pulse Programming algorithm.
Reset Command
QUICK ERASE ALGORITHM
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
Intel’s Quick Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algo-
rithm employs a closed-loop flow, similar to the
Quick Pulse Programming algorithm, to simulta-
neously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory.
Reading FFH data from the device would immedi-
ately be followed by device programming.
EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some sup-
pliers have implemented redundancy schemes, re-
ducing cycling failures to insignificant levels. Howev-
er, redundancy requires that cell size be doubledÐ
an expensive solution.
For devices being erased and reprogrammed, uni-
form and reliable erasure is ensured by first pro-
gramming all bits in the device to their charged state
e
Pulse Programming algorithm, in approximately two
(Data
00H). This is accomplished, using the Quick
seconds.
Erase execution then continues with an initial erase
e
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probabili-
ty of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
operation. Erase verification (data
FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is en-
countered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored ad-
dress location. Erasure typically occurs in one sec-
ond. Figure 6 illustrates the Quick Erase algorithm.
10
28F010
Bus
Operation
Command
Comments
Standby
Wait for V Ramp to V (1)
PP PPH
Initialize Pulse-Count
e
40H
Write
Write
Set-up
Program
Data
Program
Valid Address/Data
Standby
Write
Duration of Program
)
Operation (t
WHWH1
(2)
e
Operation
Program
Verify
Data
C0H; Stops Program
(3)
Standby
Read
t
WHGL
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
e
Data 00H, Resets the
Register for Read Operations
Write
Read
Standby
Wait for V Ramp to V (1)
PP PPL
290207–5
NOTES:
1. See DC Characteristics for the value of V
3. Refer to principles of operation.
and
PPH
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice.
V
.
PPL
2. Program Verify is only performed after byte program-
ming. A final read/compare may be performed (option-
al) after the register is written with the Read command.
Figure 5. 28F010 Quick Pulse Programming Algorithm
11
28F010
Bus
Operation
Command
Comments
e
Entire Memory Must
Before Erasure
00H
Use Quick Pulse
Programming Algorithm
(Figure 5)
Standby
Wait for V Ramp to V (1)
PP PPH
Initialize Addresses and
Pulse-Count
e
e
Write
Write
Set-up
Erase
Data
Data
20H
20H
Erase
Standby
Write
Duration of Erase Operation
)
(t
WHWH2
(2)
e
e
Erase
Verify
Addr
Data
Byte to Verify;
A0H; Stops Erase
(3)
Operation
t
WHGL
Standby
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
e
Data 00H, Resets the
Register for Read Operations
Write
Read
Standby
Wait for V Ramp to V (1)
PP PPL
290207–6
1. See DC Characteristics for the value of V and
3. Refer to principles of operation.
PPH
V
.
PPL
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice.
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
Figure 6. 28F010 Quick Erase Algorithm
12
28F010
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
DESIGN CONSIDERATIONS
Two-Line Output Control
V
Trace on Printed Circuit Boards
PP
Flash-memories are often used in larger memory ar-
rays. Intel provides two read-control inputs to ac-
commodate multiple memory connections. Two-line
control provides for:
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V power sup-
PP
ply trace. The V pin supplies the memory cell cur-
PP
rent for programming. Use similar trace widths and
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
layout considerations given the V power bus. Ad-
equate V
CC
supply traces and decoupling will de-
PP
crease V voltage spikes and overshoots.
PP
To efficiently use these two control inputs, an ad-
dress-decoder output should drive chip-enable,
while the system’s read signal controls all flash-
memories and other parallel memories. This assures
that only enabled memory devices have active out-
puts, while deselected devices maintain the low
power standby condition.
Power Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is indifferent
as to which power supply, V or V , powers up
CC
PP
first. Power supply sequencing is not required. Inter-
nal circuitry in the 28F010 ensures that the com-
mand register is reset to the read mode on power
up.
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling. System designers
are interested in three supply current (I ) issuesÐ
A system designer must guard against active writes
CC
for V
voltages above V
when V
Since both WE and CE must be low for a com-
is active.
CC
LKO
PP
standby, active, and transient current peaks pro-
duced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Ý
Ý
mand write, driving either to V will inhibit writes.
IH
The control register architecture provides an added
level of protection since alteration of memory con-
tents only occurs after successful completion of the
two-step command sequences.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 mF ceramic capacitor
28F010 Power Dissipation
connected between V and V , and between V
SS
CC
PP
and V
.
SS
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection, between V and V . The bulk capaci-
CC SS
tor will overcome voltage slumps caused by printed-
(4)
Table 4. 28F010 Typical Update Power Dissipation
Power Dissipation
(Watt-Seconds)
Operation
Notes
Array Program/Program Verify
Array Erase/Erase Verify
One Complete Cycle
1
2
3
0.171
0.136
0.478
NOTES:
1. Formula to calculate typical Program/Program Verify Power
e
typical
c
Prog Pulses (t
c
c
c
[
Ý
Ý
V
Ý
Bytes
typical Prog Pulses (t
I
PP2
PP
WHWH1
a
c
a
c
c
c
a
typical t
WHGL
]
[
Ý
typical
typical .
t
I
typical)
V
CC
Bytes
I
I
WHGL
PP4
WHWH1
CC2
CC4
]
2. Formula to calculate typical Erase/Erase Verify Power
e
typical
c
a
c
c
[
V
(V
c
typical
t
typical
I
typical
t
WHGL
PP
PP3
ERASE
PP5
a
c
a
c
Ý
t
WHGL
Ý
]
[
]
Bytes) .
Bytes)
3. One Complete Cycle
4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
V
(I
typical
e
t
typical
a
I
CC CC3
ERASE
Array Preprogram
CC5
Array Erase
a
Program.
13
28F010
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
(1)
(1)
a
§
§
a
During Erase/Program ÀÀÀÀÀÀÀÀÀ0 C to 70 C
§
§
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C
(2)
(2)
(1)
(2)
b
a
§
§
b
a
During Erase/Program ÀÀÀÀÀÀ 40 C to 85 C
§
§
b
a
Temperature Under BiasÀÀÀÀÀÀÀ 10 C to 80 C
§
§
b
a
a
Temperature Under BiasÀÀÀÀÀÀÀ 50 C to 95 C
§
§
b
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
§
§
Voltage on Any Pin with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
Voltage on Pin A with
(3)
b
a
9
(3, 4)
b
a
Respect to Ground ÀÀÀÀÀÀÀ 2.0V to 13.5V
Supply Voltage with
V
PP
Respect to Ground
During Erase/ProgramÀÀÀÀ 2.0V to 14.0V
Supply Voltage with
(3, 4)
b
a
V
CC
(3)
b
a
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
(5)
OPERATING CONDITIONS
Limits
Unit
Max
Symbol
Parameter
Min
(1)
T
A
Operating Temperature
0
70
C
C
§
§
(2)
b
a
85
T
A
Operating Temperature
40
(6)
V
V
V
Supply Voltage (10%)
4.50
4.75
5.50
5.25
V
CC
CC
CC
(7)
V
Supply Voltage (5%)
V
CC
NOTES:
1. Operating Temperature is for commercial product as defined by this specification.
2. Operating Temperature is for extended temperature products as defined by this specification.
b
b
3. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is V
a
a
0.5V, which may overshoot to V
2.0V for
CC
CC
periods less than 20 ns.
4. Maximum DC voltage on A or V may overshoot to 14.0V for periods less than 20 ns.
a
5. Output shorted for no more than one second. No more than one output shorted at a time.
9
PP
6. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for
testing characteristics.
7. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(4)
Min Typical
Max
e
V
g
I
I
I
I
Input Leakage Current
Output Leakage Current
1
1
1
1
1.0
mA
V
V
V
Max
CC
or V
LI
CC
IN
e
CC
SS
e
g
10
1.0
30
mA
V
V
V
V
Max
CC
LO
CC
e
or V
OUT
CC
SS
e
V
V
Standby Current
0.3
10
mA
mA
V
CC
CE
V
V
IH
Max
CC
CCS
CC1
CC
CC
e
Ý
e
6 MHz, I
e
Ý
V
0 mA
Active Read Current
V
V
Max, CE
e
CC
CC
IL
e
f
OUT
14
28F010
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products
(Continued)
Limits
(4)
Symbol
Parameter
Notes
Unit
Test Conditions
Min Typical
Max
10
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1.0
5.0
5.0
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
15
e
V
PPH
Program Verify Current
15
mA V
PP
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
Leakage Current
1, 2
5.0
90
15
mA V
CC5
CC
PP
PP
Erase Verify in Progress
s
g
I
I
V
V
1
1
10
mA V
mA V
V
V
V
V
PPS
PP1
PP
PP
PP
PP
CC
CC
CC
l
s
e
Read Current
200
PP
or Standby Current
g
10.0
I
I
I
I
V
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1, 2
8.0
6.0
2.0
2.0
30
mA V
V
PPH
PP2
PP3
PP4
PP5
PP
PP
PP
PP
Programming in Progress
e
V
PPH
30
5.0
5.0
0.8
mA V
PP
Erasure in Progress
e
V
PPH
Program Verify Current
Erase Verify Current
mA V
PP
Program Verify in Progress
e
Erase Verify in Progress
mA V
V
PPH
PP
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
V
V
V
IL
a
CC
2.0
V
0.5
IH
OL
e
e
0.45
V
V
Min
CC
CC
5.8 mA
I
OL
e
V
V
Output High Voltage
2.4
V
V
V
I
V
e b
Min
CC
2.5 mA
OH1
CC
OH
A
A
V
Intelligent Identifer Voltage
11.50
13.00
200
ID
9
e
V
ID
I
Intelligent Identifier Current 1, 2
90
mA A
ID
9
9
V
PPL
V
PPH
V
LKO
during Read-Only
0.00
11.40
2.5
6.5
V
V
V
NOTE: Erase/Program are
Inhibited when V
PP
e
V
PPL
Operations
PP
V during Read/Write
PP
Operations
12.60
V
Erase/Write Lock Voltage
CC
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(4)
Min Typical
Max
e
V
g
I
I
I
I
Input Leakage Current
Output Leakage Current
1
1
1
1
1.0 mA
V
V
V
Max
CC
or V
LI
CC
IN
e
CC
SS
e
g
10 mA
V
V
V
V
Max
CC
LO
CC
e
or V
OUT
CC
SS
e
V
V
Standby Current
50
10
100
30
mA
V
CE
V
V
Max
CC
CCS
CC1
CC
CC
CC
e
Ý
g
0.2V
CC
e
6 MHz, I
e
Ý
V
0 mA
Active Read Current
mA
V
V
Max, CE
e
CC
CC
IL
e
f
OUT
15
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products (Continued)
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(4)
Min
Typical
1.0
Max
10
I
I
I
V
CC
V
CC
V
CC
Programming Current
Erase Current
1, 2
1, 2
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
5.0
15
e
Program Verify Current 1, 2
5.0
15
mA
V
V , Program
PPH
PP
Verify in Progress
e
V
PP
I
V
Erase Verify Current
1, 2
5.0
90
15
mA
V
, Erase
CC5
CC
PPH
Verify in Progress
s
g
I
I
V
V
Leakage Current
Read Current, ID
1
1
10
mA
mA
V
PP
V
PP
V
PP
V
PP
V
CC
V
CC
V
CC
PPS
PP1
PP
l
s
e
200
PP
Current or Standby Current
g
10
I
I
I
I
V
Programming
1, 2
1, 2
1, 2
1, 2
8.0
6.0
2.0
2.0
30
mA
mA
mA
mA
V
PPH
PP2
PP3
PP4
PP5
PP
Current
Programming in Progress
e
V
PPH
V
PP
Erase Current
30
5.0
5.0
V
PP
Erasure in Progress
e
V
PP
Program Verify
V
V
PPH
, Program
PP
Verify in Progress
Current
Erase Verify
e
V
PP
V
V
PPH
, Erase
PP
Verify in Progress
Current
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
0.7 V
CC
V
0.5
IH
OL
CC
e
e
0.45
V
V
Min
CC
CC
5.8 mA
I
OL
e
e b
e b
V
V
V
0.85 V
V
V
V
Min, I
Min, I
2.5 mA
OH1
OH2
ID
CC
CC
CC
CC
OH
Output High Voltage
V
V
b
e
V
CC
0.4
V
100 mA
CC
OH
A
Intelligent Identifier
11.50
13.00
200
9
Voltage
e
V
ID
I
A
Intelligent Identifier
1, 2
90
mA
V
A
ID
9
9
Current
V
PPL
V
PPH
V
LKO
V
during Read-Only
0.00
11.40
2.5
6.5
NOTE: Erase/Programs are
PP
Operations
e
Inhibited when V
PP
V
PPL
V
during Read/Write
12.60
V
PP
Operations
V
Erase/Write Lock
V
CC
Voltage
16
28F010
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐExtended Temperature
Products
Limits
(4)
Symbol
Parameter
Notes
Unit
Test Conditions
Min Typical
Max
e
V
g
I
I
I
I
Input Leakage Current
Output Leakage Current
1
1
1
1
1.0
mA V
V
Max
CC
LI
CC
IN
e
V
or V
CC SS
e
g
10
mA V
V
V
Max
CC
or V
CC SS
LO
CC
e
V
OUT
e
V
V
Standby Current
0.3
10
1.0
mA V
CC
CE
V
V
IH
Max
CC
CCS
CC1
CC
CC
e
Ý
e
6 MHz, I
e
Ý
V
0 mA
Active Read Current
30
mA V
f
V
Max, CE
e
CC
e
CC
IL
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1.0
5.0
5.0
30
30
30
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
e
V
PPH
Program Verify Current
mA V
PP
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
1, 2
5.0
90
30
mA V
CC5
CC
PP
Erase Verify in Progress
s
g
I
I
V
V
Leakage Current
Read Current
1
1
10
mA V
mA V
V
V
V
V
PPS
PP1
PP
PP
PP
PP
PP
PP
CC
CC
CC
l
s
e
200
or Standby Current
g
10.0
I
I
I
I
V
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1, 2
8.0
6.0
2.0
2.0
30
mA V
V
PPH
PP2
PP3
PP4
PP5
PP
PP
PP
PP
Programming in Progress
e
V
PPH
30
5.0
5.0
0.8
mA V
PP
Erasure in Progress
e
V
PPH
Program Verify Current
Erase Verify Current
mA V
PP
Program Verify in Progress
e
Erase Verify in Progress
mA V
V
PPH
PP
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
V
V
V
IL
a
CC
2.0
V
0.5
IH
OL
e
0.45
V
V
5.8 mA
Min
CC
CC
e
I
OL
e
V
V
Output High Voltage
2.4
V
V
V
I
V
e b
Min
CC
2.5 mA
OH1
ID
CC
OH
A
A
V
Intelligent Identifer Voltage
11.50
13.00
500
9
e
V
ID
I
Intelligent Identifier Current 1, 2
90
mA A
ID
9
9
V
V
V
during Read-Only
0.00
11.40
2.5
6.5
V
V
V
NOTE: Erase/Program are
Inhibited when V
PPL
PPH
LKO
PP
e
V
PPL
Operations
PP
V during Read/Write
PP
Operations
12.60
V
Erase/Write Lock Voltage
CC
17
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature
Products
Limits
Symbol
Parameter
Notes
Unit
mA
Test Conditions
(4)
Min
Typical
Max
e
V
g
I
I
I
I
I
Input Leakage
Current
1
1
1.0
V
V
V
Max
CC
or V
LI
CC
IN
e
CC
SS
e
g
Output Leakage
Current
10
mA
V
V
V
Max
CC
LO
CC
e
V
or V
OUT
CC
SS
e
V Standby
CC
Current
1
50
10
100
30
mA
V
CC
CE
V
Max
CC
CCS
CC1
CC2
e
Ý
g
V
0.2V
CC
e
10 MHz, I
e
V
Ý
0 mA
V Active Read
CC
Current
1
mA V
f
V
Max, CE
e
CC
e
CC
IL
OUT
V Programming
CC
Current
1, 2
1.0
10
mA Programming in Progress
I
I
V
Erase Current
1, 2
1, 2
5.0
5.0
30
30
mA Erasure in Progress
CC3
CC4
CC
e
Program Verify in Progress
V
Program Verify
mA V
V
PPH
CC
PP
Current
Erase Verify
Current
e
V
PPH
I
V
1, 2
5.0
90
30
mA V
CC5
CC
PP
Erase Verify in Progress
s
g
I
I
V
Leakage Current
1
1
10
mA
mA
V
PP
V
PP
V
PP
V
V
V
PPS
PP1
PP
CC
CC
CC
l
s
V Read Current,
PP
ID Current or
Standby Current
200
g
10
e
Programming in Progress
I
I
I
I
V Programming
PP
Current
1, 2
1, 2
1, 2
1, 2
8.0
6.0
2.0
2.0
30
mA V
V
PPH
PP2
PP3
PP4
PP5
PP
e
V
PPH
V
Erase Current
30
5.0
5.0
mA V
PP
PP
PP
Erasure in Progress
e
Program Verify in Progress
V
Program Verify
mA V
V
PPH
PP
Current
e
V
PPH
V Erase Verify
PP
Current
mA V
PP
Erase Verify in Progress
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
0.7 V
V
CC
0.5
IH
OL
CC
e
0.45
V
V
5.8 mA
Min
CC
CC
e
I
OL
e
V
V
V
0.85 V
V
I
V
e b
Min
CC
2.5 mA
OH1
OH2
ID
CC
CC
OH
Output High Voltage
V
b
e
V
V
0.4
V
Min
100 mA
CC
CC
OH
CC
e b
I
A
Voltage
Intelligent Identifer
11.50
13.00
500
V
9
e
V
ID
I
A
Current
Intelligent Identifier 1, 2
90
mA
A
ID
9
9
18
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature
Products (Continued)
Limits
Symbol
Parameter
Notes
Unit
V
Test Conditions
NOTE: Erase/Programs are
(4)
Min Typical
Max
V
PPL
V
PPH
V
LKO
V during Read-Only
PP
Operations
0.00
6.5
e
V
PPL
Inhibited when V
PP
V during Read/Write
PP
Operations
11.40
2.5
12.60
V
V Erase/Write Lock
CC
Voltage
V
e
e
1.0 MHz
CAPACITANCE T
25 C, f
§
A
Limits
Min
Symbol
Parameter
Notes
Unit
Conditions
Max
8
e
C
C
Address/Control Capacitance
Output Capacitance
3
3
pF
pF
V
V
0V
IN
IN
e
12
0V
OUT
OUT
NOTES:
e
e
e
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
5.0V, V
12.0V, T
25 C. These currents
§
CC
PP
4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
19
28F010
AC TESTING INPUT/OUTPUT
(1)
WAVEFORM
HIGH SPEED AC TESTING INPUT/OUTPUT
(2)
WAVEFORM
290207–7
290207–8
AC test inputs are driven at V
(2.4 V
) for a Logic
TTL
) for a Logic ‘‘0’’. Input timing
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and
0.0V for a Logic ‘‘0’’. Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
OH
‘‘1’’ and V
(0.45 V
OL
begins at V (2.0 V
ing ends at V and V . Input rise and fall times (10%
TTL
) and V (0.8 V
). Output tim-
IH
TTL IL TTL
k
90%) 10 ns.
IH IL
k
to 90%) 10 ns.
(1)
(2)
AC TESTING LOAD CIRCUIT
HIGH SPEED AC TESTING LOAD CIRCUIT
e
e
includes Jig Capacitance
e
3.3 KX
C
C
R
100 pF
includes Jig Capacitance
3.3 KX
C
C
R
30 pF
L
L
L
L
290207–22
290207–23
e
L
L
(1)
(2)
HIGH-SPEED AC TEST CONDITIONS
AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.45V and 2.4V
Input Timing Reference Level ÀÀÀÀÀÀÀ0.8V and 2.0V
Output Timing Reference Level ÀÀÀÀÀÀ0.8V and 2.0V
Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ100 pF
Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.0V and 3.0V
Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V
Output Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V
Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30 pF
NOTES:
1. Testing characteristics for 28F010-65 in standard configuration, and 28F010-90, 28F010-120, and 28F010-150.
2. Testing characteristics for 28F010-65 in high speed configuration.
20
28F010
AC CHARACTERISTICSÐRead Only OperationsÐCommercial and Extended
Temperature Products
21
28F010
Figure 7. AC Waveforms for Read Operations
22
28F010
(1)
AC CHARACTERISTICSÐWrite/Erase/Program Only Operations
Commercial and Extended Temperature Products
Ð
23
28F010
290207–15
290207–13
Figure 10. Typical Erase Capability
Figure 8. Typical Programming Capability
290207–16
290207–14
Figure 11. Typical Erase Time at 12V
Figure 9. Typical Program Time at 12V
24
28F010
Figure 12. AC Waveforms for Programming Operations
25
28F010
Figure 13. AC Waveforms for Erase Operations
26
28F010
Ý
AC CHARACTERISTICSÐAlternative CE -Controlled WritesÐCommercial and
Extended Temperature
27
28F010
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
1, 3, 4
1, 2, 4
Min
Typical
Max
10
Unit
Sec
Sec
Chip Erase Time
Chip Program Time
1
2
12.5
NOTES:
1. ‘‘Typicals’’ are not guaranteed, but based on samples from production lots. Data taken at 25 C, 12.0V V
.
§
PP
6 msec write recovery),
a
2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program
while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes 00H programming prior to erasure.
4. Excludes system level overhead.
28
28F010
NOTE:
Alternative CE -Controlled Write Timings also apply to erase operations.
Ý
Figure 14. Alternate AC Waveforms for Programming Operations
29
28F010
ORDERING INFORMATION
290207–20
VALID COMBINATIONS:
P28F010-65
P28F010-90
P28F010-120
P28F010-150
N28F010-65
TN28F010-90
N28F010-90
N28F010-120
N28F010-150
E28F010-65
E28F010-90
E28F010-120
E28F010-150
F28F010-65
F28F010-90
F28F010-120
F28F010-150
TE28F010-90
TF28F010-90
ADDITIONAL INFORMATION
Order
Number
294005
ER-20,
ER-24,
ER-28,
RR-60,
AP-316,
AP-325
‘‘ETOX Flash Memory Technology’’
‘‘Intel Flash Memory’’
294008
294012
293002
292046
292059
‘‘ETOX III Flash Memory Technology’’
‘‘ETOX Flash Memory Reliability Data Summary’’
‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
‘‘Guide to Flash Memory Reprogramming’’
REVISION HISTORY
Number
Description
Removed 200 ns Speed Bin
007
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC Test Conditions
Added ‘‘dimple’’ to F TSOP Package
Corrected Serpentine Layout
008
009
010
Corrected AC Waveforms
Added Extended Temperature Options
Added 28F010-65 and 28F010-90 speeds
Ý
Revised Symbols, i.e., CE, OE, etc. to CE , OE , etc.
Ý
Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table
Textual Changes or Edits
Corrected Erase/Program Times
30
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