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AD7530 [INTERSIL]

10-Bit, 12-Bit, Multiplying D/A Converters; 10位， 12位，乘法D / A转换器
AD7530
型号： AD7530
厂家： Intersil    Intersil
描述：

10-Bit, 12-Bit, Multiplying D/A Converters
10位， 12位，乘法D / A转换器

转换器
文件： 总9页 (文件大小：141K)
中文：  中文翻译
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AD7520, AD7530,  
AD7521, AD7531  
August 1997  
10-Bit, 12-Bit, Multiplying D/A Converters  
Features  
Description  
• AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit and The AD7520/AD7530 and AD7521/AD7531 are monolithic,  
10-Bit Linearity  
high accuracy, low cost 10-bit and 12-bit resolution,  
multiplying digital-to-analog converters (DAC). Intersil’  
thin-film on CMOS processing gives up to 10-bit accuracy  
with TTL/CMOS compatible operation. Digital inputs are fully  
protected against static discharge by diodes to ground and  
positive supply.  
• AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit and  
10-Bit Linearity  
• Low Power Dissipation (Max) . . . . . . . . . . . . . . . .20mW  
o
• Low Nonlinearity Tempco at 2ppm of FSR/ C  
Typical applications include digital/analog interfacing,  
multiplication and division, programmable power supplies,  
CRT character generation, digitally controlled gain circuits,  
integrators and attenuators, etc.  
• Current Settling Time to 0.05% of FSR . . . . . . . . 1.0µs  
• Supply Voltage Range . . . . . . . . . . . . . . . . ±5V to +15V  
• TTL/CMOS Compatible  
The AD7530 and AD7531 are identical to the AD7520 and  
AD7521, respectively, with the exception of output leakage  
current and feedthrough specifications.  
• Full Input Static Protection  
• /883B Processed Versions Available  
Ordering Information  
o
PART NUMBER  
AD7520JN, AD7530JN  
AD7520KN, AD7530KN  
AD7521JN, AD7531JN  
AD7521KN, AD7531KN  
AD7520LN, AD7530LN  
AD7521LN, AD7531LN  
AD7520JD  
LINEARITY (INL, DNL)  
0.2% (8-Bit)  
TEMP. RANGE ( C)  
0 to 70  
PACKAGE  
16 Ld PDIP  
PKG. NO.  
E16.3  
0.1% (9-Bit)  
0 to 70  
16 Ld PDIP  
E16.3  
E18.3  
E18.3  
E16.3  
E18.3  
F16.3  
F16.3  
F16.3  
F16.3  
F16.3  
0.2% (8-Bit)  
0 to 70  
18 Ld PDIP  
0.1% (9-Bit)  
0 to 70  
18 Ld PDIP  
0.05% (10-Bit)  
0.05% (10-Bit)  
0.2% (8-Bit)  
-40 to 85  
-40 to 85  
-25 to 85  
-25 to 85  
-25 to 85  
-55 to 125  
-55 to 125  
16 Ld PDIP  
18 Ld PDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
AD7520KD  
0.1% (9-Bit)  
AD7520LD  
0.05% (10-Bit)  
0.2% (8-Bit)  
AD7520SD, AD7520SD/883B  
AD7520UD, AD7520UD/883B  
0.05% (10-Bit)  
Pinouts  
AD7520, AD7530  
AD7521, AD7531  
(CERDIP, PDIP)  
(PDIP)  
TOP VIEW  
TOP VIEW  
I
I
1
2
3
4
5
6
7
8
16 R  
I
I
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
R
V
OUT1  
FEEDBACK  
OUT1  
OUT2  
GND  
FEEDBACK  
15 V  
OUT2  
GND  
REF  
REF  
14 V+  
V+  
BIT 1 (MSB)  
BIT 2  
13 BIT 10 (LSB)  
12 BIT 9  
BIT 12 (LSB)  
BIT 11  
BIT 1 (MSB)  
BIT 2  
BIT 3  
11 BIT 8  
BIT 3  
BIT 10  
10 BIT 7  
BIT 4  
BIT 4  
BIT 9  
9
BIT 6  
BIT 5  
BIT 5  
BIT 8  
BIT 6  
10 BIT 7  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
File Number 3104.1  
10-7  
AD7520, AD7530, AD7521, AD7531  
Absolute Maximum Ratings  
Thermal Information  
o
o
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V 16 Ld PDIP Package . . . . . . . . . . . . . . . .  
100  
90  
75  
N/A  
N/A  
20  
REF  
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND  
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+  
18 Ld PDIP Package . . . . . . . . . . . . . . . .  
CERDIP Package . . . . . . . . . . . . . . . . . .  
o
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175 C  
Operating Conditions  
o
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150 C  
o
o
Temperature Ranges  
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C  
JD, KD, LD Versions . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C  
SD, UD Versions . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
o
o
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C  
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep  
unused units in conductive foam at all times.  
Do not apply voltages higher than V  
NOTE:  
or less than GND potential on any terminal except V  
REF  
and R .  
FEEDBACK  
DD  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
o
Electrical Specifications V+ = +15V, V  
= +10V, T = 25 C Unless Otherwise Specified  
A
REF  
AD7520/AD7530  
AD7521/AD7531  
PARAMETER  
SYSTEM PERFORMANCE (Note 2)  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
10  
-
10  
-
10  
12  
-
12  
-
12  
Bits  
o
o
Nonlinearity  
J, S  
S Over -55 C to 125 C  
(Notes 2, 5) (Figure 3)  
±0.2  
(8-Bit)  
±0.2  
(8-Bit)  
% of  
FSR  
o
o
K
T Over -55 C to 125 C  
(Figure 2)  
-
-
-
-
±0.1  
(9-Bit)  
-
-
-
-
±0.1  
(9-Bit)  
% of  
FSR  
L, U  
-10V ≤ V  
≤ +10V  
±0.05  
(10-Bit)  
±0.05  
(10-Bit)  
% of  
FSR  
REF  
o
o
U Over -55 C to 125 C  
(Figure 2)  
Nonlinearity Tempco  
Gain Error  
-10V ≤ V  
REF  
(Notes 3, 4)  
≤ +10V  
-
-
-
-
-
±2  
-
-
-
-
-
-
±2  
-
ppm of  
FSR/ C  
o
±0.3  
±0.3  
% of  
FSR  
Gain Error Tempco  
-
-
±10  
-
-
±10  
ppm of  
o
FSR/ C  
Output Leakage Current  
(Either Output)  
Over the Specified  
Temperature Range  
±200  
(±300)  
±200  
(±300)  
nA  
DYNAMIC CHARACTERISTICS  
Output Current Settling Time  
To 0.05% of FSR (All Digital  
Inputs Low To High And High  
To Low) (Note 4) (Figure 7)  
-
-
1.0  
-
-
-
-
1.0  
-
-
µs  
Feedthrough Error  
V
= 20V  
P-P  
, 10kHz  
10  
10  
mV  
P-P  
REF  
(50kHz) All Digital Inputs Low  
(Note 4) (Figure 6)  
REFERENCE INPUT  
Input Resistance  
All Digital Inputs High  
5
10  
20  
5
10  
20  
kΩ  
I
at Ground  
OUT1  
ANALOG OUTPUT  
Output Capacitance  
I
I
I
I
All Digital Inputs High  
(Note 4) (Figure 5)  
-
-
-
-
200  
75  
-
-
-
-
-
-
-
-
200  
75  
-
-
-
-
pF  
pF  
pF  
pF  
OUT1  
OUT2  
OUT1  
OUT2  
All Digital Inputs Low  
(Note 4) (Figure 5)  
75  
75  
200  
200  
10-8  
AD7520, AD7530, AD7521, AD7531  
o
Electrical Specifications V+ = +15V, V  
= +10V, T = 25 C Unless Otherwise Specified (Continued)  
REF  
A
AD7520/AD7530  
AD7521/AD7531  
PARAMETER  
Output Noise  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
Both Outputs  
(Note 4) (Figure 4)  
-
Equivalent  
to 10kΩ  
-
-
Equivalent  
to 10kΩ  
-
Johnson  
Noise  
DIGITAL INPUTS  
Low State Threshold, V  
Over the Specified  
Temperature Range  
-
2.4  
-
-
-
-
0.8  
-
-
2.4  
-
-
-
-
0.8  
-
V
V
IL  
High State Threshold, V  
IH  
V
= 0V or +15V  
IN  
Input Current, I , I  
IL IH  
±1  
±1  
µA  
Input Coding  
See Tables 1 and 2  
Binary/Offset Binary  
POWER SUPPLY CHARACTERISTICS  
Power Supply Rejection  
V+ = 14.5V to 15.5V  
-
±0.005  
-
-
±0.005  
-
% FSR/  
(Note 3) (Figure 3)  
% ∆V+  
Power Supply Voltage Range  
I+  
+5 to +15  
+5 to +15  
V
All Digital Inputs at 0V or V+  
Excluding Ladder Network  
-
-
-
±1  
-
2
-
-
-
-
±1  
-
2
-
µA  
All Digital Inputs High or Low  
Excluding Ladder Network  
-
-
mA  
Total Power Dissipation  
NOTES:  
Including the Ladder Network  
20  
20  
mW  
2. Full scale range (FSR) is 10V for Unipolar and ±10V for Bipolar modes.  
3. Using internal feedback resistor R  
.
FEEDBACK  
4. Guaranteed by design, or characterization and not production tested.  
5. Accuracy not guaranteed unless outputs at GND potential.  
6. Accuracy is tested and guaranteed at V+ = 15V only.  
Functional Diagram  
V
10kΩ  
10kΩ  
10kΩ  
10kΩ  
REF  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
GND  
SPDT NMOS  
SWITCHES  
I
OUT2  
I
OUT1  
10kΩ  
R
MSB  
BIT 2  
BIT 3  
FEEDBACK  
NOTES:  
Switches shown for Digital Inputs “High”.  
Resistor values are typical.  
10-9  
AD7520, AD7530, AD7521, AD7531  
Pin Descriptions  
AD7520/30 AD7521/31  
PIN NAME  
DESCRIPTION  
Current Out summing junction of the R2R ladder network.  
Current Out virtual ground, return path for the R2R ladder network.  
Digital Ground. Ground potential for digital side of D/A.  
1
2
1
2
I
I
OUT1  
OUT2  
3
3
GND  
4
4
Bits 1(MSB) Most Significant Digital Data Bit.  
5
5
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
V+  
Digital Bit 2.  
6
6
Digital Bit 3.  
7
7
Digital Bit 4.  
8
8
Digital Bit 5.  
9
9
Digital Bit 6.  
10  
11  
12  
13  
-
10  
11  
12  
13  
14  
15  
16  
17  
18  
Digital Bit 7.  
Digital Bit 8.  
Digital Bit 9.  
Digital Bit 10 (AD7521/31). Least Significant Digital Data Bit (AD7520/30).  
Digital Bit 11 (AD7521/31).  
-
Least Significant Digital Data Bit (AD7521/31).  
Power Supply +5V to +15V.  
14  
15  
16  
V
Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.  
Feedback resistor used for the current to voltage conversion when using an external Op Amp.  
REF  
R
FEEDBACK  
Definition of Terms  
Nonlinearity: Error contributed by deviation of the DAC or current reference and an operational amplifier are all that  
transfer function from a “best straight line” through the actual is required for most voltage output applications.  
plot of transfer function. Normally expressed as a percent-  
age of full scale range or in (sub)multiples of 1 LSB.  
A simplified equivalent circuit of the DAC is shown in the  
Functional Diagram. The NMOS SPDT switches steer the lad-  
Resolution: It is addressing the smallest distinct analog  
output change that a D/A converter can produce. It is  
commonly expressed as the number of converter bits. A  
converter with resolution of n bits can resolve output changes  
der leg currents between I  
and I buses which must  
OUT1  
OUT2  
be held either at ground potential. This configuration main-  
tains a constant current in each ladder leg independent of the  
input code.  
-N  
-N  
of 2 of the full-scale range, e.g., 2  
V
for a unipolar  
REF  
Converter errors are further reduced by using separate  
metal interconnections between the major bits and the  
outputs. Use of high threshold switches reduce offset (leak-  
age) errors to a negligible level.  
conversion. Resolution by no means implies linearity.  
Settling Time: Time required for the output of a DAC to set-  
tle to within specified error band around its final value (e.g.,  
1
/ LSB) for a given digital input change, i.e., all digital inputs  
2
The level shifter circuits are comprised of three inverters with  
positive feedback from the output of the second to the first, see  
Figure 1. This configuration results in TTL/CMOS compatible  
operation over the full military temperature range. With the lad-  
der SPDT switches driven by the level shifter, each switch is  
binarily weighted for an ON resistance proportional to the  
LOW to HIGH and HIGH to LOW.  
Gain Error: The difference between actual and ideal analog  
output values at full scale range, i.e., all digital inputs at  
HIGH state. It is expressed as a percentage of full scale  
range or in (sub)multiples of 1 LSB.  
Feedthrough Error: Error caused by capacitive coupling respective ladder leg current. This assures a constant voltage  
from V  
to I  
with all digital inputs LOW.  
drop across each switch, creating equipotential terminations for  
the 2R ladder resistors and highly accurate leg currents.  
REF  
OUT1  
Output Capacitance: Capacitance from I  
and I  
OUT2  
OUT1  
terminals to ground.  
V+  
1 3  
Output Leakage Current: Current which appears on I  
terminal when all digital inputs are LOW or on I  
terminal when all digital inputs are HIGH.  
OUT1  
OUT2  
6
4
TO LADDER  
8
9
Detailed Description  
DTL/TTL/  
CMOS INPUT  
2
5
7
The AD7520, AD7530, AD7521 and AD7531 are monolithic,  
multiplying D/A converters. A highly stable thin film R-2R  
resistor ladder network and NMOS SPDT switches form the  
basis of the converter circuit, CMOS level shifters permit low  
power TTL/CMOS compatible operation. An external voltage  
I
I
OUT2 OUT1  
FIGURE 1. CMOS SWITCH  
10-10  
AD7520, AD7530, AD7521, AD7531  
Test Circuits The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531.  
V
REF  
+15V  
BIT 1  
(MSB)  
R
FEEDBACK  
15  
4
5
16  
1
+15V  
UNGROUNDED  
SINE WAVE  
GENERATOR  
I
OUT1  
10-BIT  
BINARY  
COUNTER  
-
AD7520  
HA2600  
+
500kΩ  
I
BIT 10  
(LSB)  
400Hz 1V  
10kΩ  
OUT2  
P-P  
13  
3
2
0.01%  
5K 0.01%  
+10V  
V
1MΩ  
REF  
-
GND  
CLOCK  
HA2600  
BIT 1  
5kΩ 0.01%  
(MSB)  
+
-
R
I
15 14  
V
FEEDBACK  
REF  
BIT 1  
(LSB)  
4
HA2600  
+
16  
1
10kΩ 0.01%  
OUT1  
5
-
LINEARITY  
ERROR  
X 100  
AD7520  
12-BIT  
I
HA2600  
+
BIT 10  
(LSB)  
OUT2  
BIT 10  
BIT 11  
REFERENCE  
DAC  
13  
3
2
BIT 12  
GND  
FIGURE 2. NONLINEARITY  
FIGURE 3. POWER SUPPLY REJECTION  
+11V (ADJUST FOR V  
OUT  
= 0V)  
+15V  
1K  
f = 1kHz  
BW = 1Hz  
NC +15V  
+15V  
100Ω  
10kΩ  
15µF  
I
OUT2  
15 14  
QUAN  
TECH  
MODEL 134D  
WAVE  
4
2
BIT 1 (MSB)  
15  
4
5
14  
16  
-
5
NC  
AD7520  
101ALN  
I
OUT1  
V
1
13  
+
3
OUT  
AD7520  
ANALYZER  
1kΩ  
1
2
50kΩ 1kΩ  
0.1µF  
100mV  
1MHz  
P-P  
13  
50V  
3
BIT 10 (LSB)  
SCOPE  
FIGURE 4. NOISE  
FIGURE 5. OUTPUT CAPACITANCE  
5t: 1% SETTLING (1mV)  
8t: 0.03% SETTLING  
t = RISE TIME  
EXTRAPOLATE  
+15V  
+15V  
V
= 20V  
P-P  
REF  
V
REF  
100kHz SINE WAVE  
-10V  
15  
4
5
14  
16  
BIT 1 (MSB)  
BIT 1 (MSB)  
15  
14  
4
5
+5V  
0V  
I
I
OUT1  
OUT2  
3
2
AD7520  
SCOPE  
-
1
2
+100mV  
AD7520  
HA2600  
+
V
1
OUT  
DIGITAL  
INPUT  
I
13  
3
OUT2  
13  
2
BIT 10 (LSB)  
3
100Ω  
BIT 10 (LSB)  
GND  
GND  
FIGURE 6. FEEDTHROUGH ERROR  
FIGURE 7. OUTPUT CURRENT SETTLING TIME  
10-11  
AD7520, AD7530, AD7521, AD7531  
“Digital Input Code/Analog Output Value” table for bipolar  
mode is given in Table 2.  
Applications  
Unipolar Binary Operation  
+15V  
R3  
V
The circuit configuration for operating the AD7520 in unipo-  
lar mode is shown in Figure 8. Similar circuits can be used  
for AD7521, AD7530 and AD7531. With positive and nega-  
REF  
10MΩ  
BIT 1  
(MSB)  
15  
4
5
14  
16  
R
FEEDBACK  
tive V  
values the circuit is capable of 2-Quadrant multipli-  
REF  
I
OUT1  
I
1
2
cation. The “Digital Input Code/Analog Output Value” table  
for unipolar mode is given in Table 1.  
AD7520  
-
R1 10K R2 10K  
0.01% 0.01%  
OUT2  
13  
3
+
-
BIT 10  
(LSB)  
+15V  
V
REF  
+
15  
4
5
14  
16  
R
I
BIT 1 (MSB)  
FEEDBACK  
OUT1  
-
AD7520  
DIGITAL  
INPUT  
1
2
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)  
TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE  
V
OUT  
+
I
OUT2  
13  
3
BIT 10 (LSB)  
GND  
DIGITAL INPUT  
1111111111  
1000000001  
1000000000  
0111111111  
0000000001  
0000000000  
ANALOG OUTPUT  
-(N-1)  
-V  
0
(1-2  
REF  
)
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT  
MULTIPLICATION)  
-(N-1)  
-V  
(2  
)
REF  
TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION  
-(N-1)  
(2  
V
V
V
)
REF  
REF  
REF  
DIGITAL INPUT  
1111111111  
1000000001  
1000000000  
0111111111  
0000000001  
0000000000  
ANALOG OUTPUT  
-(N-1)  
(1-2  
)
-N  
-V  
(1-2  
1
)
REF  
-N  
-V  
REF  
( / + 2  
)
2
NOTES:  
1. LSB = 2  
-(N-1)  
V
.
2. N = 10 for 7520, 7521;  
N = 12 for 7530, 7531.  
REF  
-V  
-V  
-V  
0
/2  
REF  
REF  
REF  
1
-N  
( / -2  
2
)
A “Logic 1” input at any digital input forces the corresponding  
ladder switch to steer the bit current to I bus. A “Logic 0”  
input forces the bit current to I  
-N  
(2  
)
OUT1  
bus. For any code the  
OUT2  
I
and I  
OUT2  
bus currents are complements of one  
changes the polarity of  
out-  
OUT1  
NOTES:  
1. LSB = 2  
another. The current amplifier at I  
-N  
OUT2  
V
.
REF  
I
current and the transconductance amplifier at I  
OUT2  
OUT1  
2. N = 10 for 7520, 7530;  
N = 12 for 7521, 7531.  
put sums the two currents. This configuration doubles the out-  
put range. The difference current resulting at zero offset binary  
code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected  
Zero Offset Adjustment  
by using an external resistor, (10MΩ), from V  
to I .  
REF  
OUT2  
1. Connect all digital inputs to GND.  
Offset Adjustment  
2. Adjust the offset zero adjust trimpot of the output  
1. Adjust V  
to approximately +10V.  
REF  
2. Connect all digital inputs to “Logic 1”.  
3. Adjust I amplifier offset adjust trimpot for 0V ±1mV at  
operational amplifier for 0V at V  
.
OUT  
Gain Adjustment  
OUT2  
amplifier output.  
1. Connect all digital inputs to V+.  
I
OUT2  
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.  
5. Adjust I amplifier offset adjust trimpot for 0V ±1mV at  
-N  
2. Monitor VOUT for a -V  
(1-2 ) reading. (N = 10 for  
REF  
AD7520/30 and N = 12 for AD7521/31).  
OUT1  
3. To decrease V  
, connect a series resistor (0 to 250Ω)  
V
.
OUT  
between the reference voltage and the V  
OUT  
terminal.  
REF  
Gain Adjustment  
4. To increase V  
OUT  
, connect a series resistor (0 to 250Ω) in  
1. Connect all digital inputs to V+.  
the I  
amplifier feedback loop.  
OUT1  
(N-1)  
2. Monitor V  
OUT  
for a -V  
REF  
(1-2- volts reading. (N = 10 for  
Bipolar (Offset Binary) Operation  
AD7520 and AD7530, and N = 12 for AD7521 and AD7531).  
The circuit configuration for operating the AD7520 in the  
bipolar mode is given in Figure 9. Similar circuits can be  
used for AD7521, AD7530 and AD7531. Using offset binary  
digital input codes and positive and negative reference volt-  
age values, 4-Quadrant multiplication can be realized. The  
3. To increase V , connect a series resistor of up to 250Ω  
OUT  
and R  
between V  
.
OUT  
FEEDBACK  
4. To decrease V  
OUT  
, connect a series resister of up to 250Ω  
between the reference voltage and the V  
terminal.  
REF  
10-12  
AD7520, AD7530, AD7521, AD7531  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
101 mils x 103 mils (2565micrms x 2616micrms)  
Type: PSG/Nitride  
PSG: 7 ±1.4kÅ  
Nitride: 8 ±1.2kÅ  
METALLIZATION:  
Type: Pure Aluminum  
Thickness: 10 ±1kÅ  
PROCESS:  
CMOS Metal Gate  
Metallization Mask Layout  
AD7520, AD7530  
PIN 4  
BIT 1  
(MSB)  
PIN 7  
BIT 4  
PIN 6  
BIT 3  
PIN 5  
BIT 2  
PIN 3  
GND  
PIN 2  
PIN 8  
BIT 5  
I
2
OUT  
PIN 1  
I
1
OUT  
PIN 9  
BIT 6  
PIN 10  
BIT 7  
PIN 16  
R
FEEDBACK  
PIN 11  
BIT 8  
PIN 15  
V
REF  
PIN 14  
V+  
PIN 12  
BIT 9  
PIN 13  
BIT 10  
(LSB)  
NC  
NC  
10-13  
AD7520, AD7530, AD7521, AD7531  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
101 mils x 103 mils (2565micrms x 2616micrms)  
Type: PSG/Nitride  
PSG: 7 ±1.4kÅ  
Nitride: 8 ±1.2kÅ  
METALLIZATION:  
Type: Pure Aluminum  
Thickness: 10 ±1kÅ  
PROCESS:  
CMOS Metal Gate  
Metallization Mask Layout  
AD7521, AD7531  
PIN 4  
BIT 1  
(MSB)  
PIN 7  
BIT 4  
PIN 6  
BIT 3  
PIN 5  
BIT 2  
PIN 3  
GND  
PIN 2  
PIN 8  
BIT 5  
I
2
OUT  
PIN 1  
I
1
OUT  
PIN 9  
BIT 6  
PIN 10  
BIT 7  
PIN 18  
R
FEEDBACK  
PIN 11  
BIT 8  
PIN 17  
V
REF  
PIN 16  
V+  
PIN 12  
BIT 9  
PIN 13  
BIT 10  
PIN 14  
BIT 11  
PIN 15  
BIT 12  
(LSB)  
10-14  
AD7520, AD7530, AD7521, AD7531  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
Taiwan Limited  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
10-15  

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