CA3096A [INTERSIL]
NPN/PNP Transistor Arrays; NPN / PNP晶体管阵列
| 型号： | CA3096A |
| 厂家： | 
Intersil |
| 描述： | NPN/PNP Transistor Arrays |
| 文件： | 总14页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3096, CA3096A,
CA3096C
December 1997
NPN/PNP Transistor Arrays
Applications
Description
• Five-Independent Transistors
- Three NPN and
The CA3096C, CA3096, and CA3096A are general purpose
high voltage silicon transistor arrays. Each array consists of
five independent transistors (two PNP and three NPN types)
on a common substrate, which has a separate connection.
Independent connections for each transistor permit maxi-
mum flexibility in circuit design.
- Two PNP
• Differential Amplifiers
• DC Amplifiers
• Sense Amplifiers
Types CA3096A, CA3096, and CA3096C are identical, except
that the CA3096A specifications include parameter matching
• Level Shifters
and greater stringency in I
, I
, and V (SAT). The
• Timers
CBO CEO
CE
CA3096C is a relaxed version of the CA3096.
• Lamp and Relay Drivers
• Thyristor Firing Circuits
• Temperature Compensated Amplifiers
• Operational Amplifiers
CA3096, CA3096A, CA3096C
Essential Differences
CHARACTERISTIC
CA3096A
CA3096
CA3096C
Ordering Information
V
(V) (Min)
NPN
(BR)CEO
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
35
35
24
o
PACKAGE
PNP
-40
-40
-24
CA3096AE
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld SOIC
E16.3
M16.15
V
(V) (Min)
NPN
(BR)CBO
CA3096AM
(3096A)
45
45
30
CA3096AM96
(3096A)
-55 to 125 16 Ld SOIC Tape M16.15
and Reel
PNP
-40
-40
-24
h
h
at 1mA
FE
CA3096CE
CA3096E
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld SOIC
E16.3
E16.3
M16.15
NPN
PNP
150-500
20-200
150-500
20-200
100-670
15-200
CA3096M
(3096)
at 100µA
FE
PNP
40-250
40-250
30-300
CA3096M96
(3096)
-55 to 125 16 Ld SOIC Tape M16.15
and Reel
I
(nA) (Max)
NPN
CBO
40
100
100
Pinout
PNP
-40
-100
-100
CA3096, CA3096A, CA3096C
(PDIP, SOIC)
I
(nA) (Max)
NPN
CEO
TOP VIEW
100
1000
1000
PNP
-100
-1000
-1000
1
2
3
4
5
6
7
8
16 SUBSTRATE
V
(V) (Max)
NPN
CE SAT
15
14
13
12
11
10
9
0.5
0.7
0.7
Q
1
Q
Q
|V | (mV) (Max)
IO
5
4
NPN
PNP
5
5
-
-
-
-
Q
Q
2
3
|I | (µA) (Max)
IO
NPN
PNP
0.6
-
-
-
-
0.25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 595.4
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
CA3096, CA3096A, CA3096C
Absolute Maximum Ratings
Operating Conditions
o
o
NPN
PNP
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to 125 C
Collector-to-Emitter Voltage, V
CEO
CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 35V
CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
-40V
-24V
Thermal Information
o
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
Collector-to-Base Voltage, V
CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V
CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Collector-to-Substrate Voltage, V
CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V
CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Emitter-to-Substrate Voltage, V
EIO
CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . .
CBO
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation (Each Transistor, Note 3) . . . . . 200mW
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
90
125
-40V
-24V
(Note 1)
CIO
o
-
-
o
o
o
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
-
-
-40V
-24V
CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emitter-to-Base Voltage, V
EBO
CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . 6V
CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
-40V
-24V
Collector Current, I (All Types) . . . . . . . . . . . . 50mA
-10mA
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3096 is isolated from the substrate by an integral diode. The substrate (Terminal 16) must be
connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor
action.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal
resistances to calculate the junction temperature.
o
Electrical Specifications For Equipment Design, At T = 25 C
A
CA3096
TYP
CA3096A
TYP
CA3096C
TYP
TEST
CONDITIONS
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
DC CHARACTERISTICS FOR EACH NPN TRANSISTOR
I
V
= 10V,
= 0
-
0.001
100
-
-
0.001
0.006
40
-
-
0.001
0.006
100
nA
nA
CBO
CB
I
E
I
V
= 10V,
-
0.006
1000
100
1000
CEO
CE
I
= 0
B
V
V
I
= 1mA, I = 0
B
35
45
50
-
-
35
45
50
-
-
24
30
35
80
-
-
V
V
(BR)CEO
(BR)CBO
C
I
I
= 10µA,
= 0
100
100
C
E
V
V
I
I
= 10µA,
= I = 0
E
45
6
100
8
-
-
45
6
100
8
-
-
30
6
80
8
-
-
V
V
(BR)CIO
(BR)EBO
CI
B
I
I
= 10µA,
= 0
E
C
V
V
I
= 10µA
6
-
7.9
9.8
0.7
6
-
7.9
9.8
0.5
6
-
7.9
9.8
0.7
V
V
Z
Z
l
= 10mA,
= 1mA
0.24
0.24
0.24
CE SAT
C
I
B
V
(Note 4)
I
V
= 1mA,
0.6
150
-
0.69
390
1.9
0.78
500
-
0.6
150
-
0.69
390
1.9
0.78
500
-
0.6
100
-
0.69
390
1.9
0.78
670
-
V
BE
C
= 5V
CE
h
(Note 4)
FE
o
|∆V /∆T| (Note 4)
BE
I
= 1mA,
mV/ C
C
V
= 5V
CE
DC CHARACTERISTICS FOR EACH PNP TRANSISTOR
= -10V, -0.06
I
V
-
-100
-
-0.006
-40
-
-0.06
-100
nA
CBO
CB
= 0
I
E
2
CA3096, CA3096A, CA3096C
o
Electrical Specifications For Equipment Design, At T = 25 C (Continued)
A
CA3096
TYP
CA3096A
TYP
CA3096C
TYP
TEST
CONDITIONS
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
I
V
= -10V,
CE
-
-0.12
-1000
-
-0.12
-100
-
-0.12
-1000
nA
CEO
I
= 0
B
V
V
V
V
V
V
I
I
= -100µA,
= 0
-40
-40
-40
40
-
-75
-80
-
-
-40
-40
-40
40
-
-75
-80
-
-
-24
-24
-24
24
-
-30
-60
-80
80
-
-
V
V
V
V
V
V
(BR)CEO
(BR)CBO
(BR)EBO
(BR)ElO
CE SAT
C
B
I
I
= -10µA,
= 0
C
E
I
I
= -10µA,
= 0
-100
100
-0.16
-0.6
85
-
-100
100
-0.16
-0.6
85
-
-
E
C
I
I
= 10µA,
= I = 0
C
-
-
-
EI
B
I
I
= -1mA,
= -100µA
-0.4
-0.7
250
200
-
-0.4
-0.7
250
200
-
-0.16
-0.6
85
-0.4
-0.7
300
200
-
C
B
(Note 4)
(Note 4)
I
= -100µA,
= -5V
-0.5
40
20
-
-0.5
40
20
-
-0.5
30
15
-
BE
C
V
CE
I = -100µA,
C
h
FE
V
= -5V
CE
I
= -1mA,
47
47
47
C
V
= -5V
CE
o
|∆V /∆T| (Note 4)
BE
I
= -100µA,
2.2
2.2
2.2
mV/ C
C
V
= -5V
CE
I
I
Collector-Cutoff Current
Collector-Cutoff Current
V
Emitter-to-Base Zener Voltage
CBO
Z
V
V
Collector-to-Emitter Saturation Voltage
Base-to-Emitter Voltage
CEO
CE SAT
BE
V
V
V
V
Collector-to-Emitter Breakdown Voltage
Collector-to-Base Breakdown Voltage
Collector-to-Substrate Breakdown Voltage
Emitter-to-Base Breakdown Voltage
(BR)CEO
(BR)CBO
(BR)CIO
(BR)EBO
h
DC Forward-Current Transfer Ratio
FE
|∆V /∆T| Magnitude of Temperature Coefficient:
BE
(for each transistor)
NOTE:
4. Actual forcing current is via the emitter for this test.
o
Electrical Specifications For Equipment Design At T = 25 C (CA3096A Only)
A
CA3096A
TYP
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
FOR TRANSISTORS Q AND Q (AS A DIFFERENTIAL AMPLIFIER)
1
2
Absolute Input Offset Voltage
|V
|
V
= 5V, I = 1mA
-
-
-
0.3
0.07
1.1
5
0.6
-
mV
CE
C
IO
Absolute Input Offset Current
|I
|
µA
IO
o
∆V
Absolute Input Offset Voltage
Temperature Coefficient
µV/ C
IO
-----------------
∆T
FOR TRANSISTORS Q AND Q (AS A DIFFERENTIAL AMPLIFIER)
4
5
Absolute Input Offset Voltage
|V
|
V
R
= -5V, I = -100µA
-
-
-
0.15
2
5
250
-
mV
nA
IO
CE
= 0
C
S
Absolute Input Offset Current
|I
|
IO
o
∆V
Absolute Input Offset Voltage
Temperature Coefficient
0.54
µV/ C
IO
-----------------
∆T
3
CA3096, CA3096A, CA3096C
o
Electrical Specifications Typical Values Intended Only for Design Guidance At T = 25 C
A
TYPICAL
VALUES
PARAMETER
SYMBOL
TEST CONDITIONS
UNITS
DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR
Noise Figure (Low Frequency)
Low-Frequency, Input Resistance
Low-Frequency Output Resistance
NF
f = 1kHz, V
CE
= 5V, I = 1mA, R = 1kΩ
2.2
10
80
dB
kΩ
kΩ
C
S
R
f = 1.0kHz, V
= 5V I = 1 mA
C
I
CE
CE
R
f = 1.0kHz, V
= 5V I = 1 mA
C
O
Admittance Characteristics
Forward Transfer Admittance
g
b
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
= 5V, I = 1mA
7.5
-j13
2.2
mS
mS
mS
mS
mS
mS
MHz
MHz
pF
FE
FE
CE
CE
CE
CE
CE
CE
C
y
FE
= 5V, I = 1mA
C
Input Admittance
Output Admittance
g
= 5V, I = 1mA
C
IE
IE
y
IE
b
= 5V, I = 1mA
j3.1
0.76
j2.4
280
335
0.75
0.46
3.2
C
g
b
= 5V, I = 1mA
C
OE
OE
y
OE
= 5V, I = 1mA
C
Gain-Bandwidth Product
f
V
V
V
V
V
= 5V, I = 1.0mA
C
T
CE
CE
EB
CB
= 5V, I = 5mA
C
Emitter-To-Base Capacitance
Collector-To-Base Capacitance
Collector-To-Substrate Capacitance
C
C
= 3V
= 3V
EB
pF
CB
C
= 3V
CI
pF
CI
DYNAMIC CHARACTERISTICS FOR EACH PNP TRANSISTOR
Noise Figure (Low Frequency)
Low-Frequency Input Resistance
Low-Frequency Output Resistance
Gain-Bandwidth Product
NF
f = 1kHz, I = 100µA, R = 1kΩ
3
dB
kΩ
kΩ
MHz
pF
C
S
R
f = 1kHz, V
= 5V, I = 100µA
27
I
CE
C
R
f = 1kHz, V
= 5V, I = 100µA
680
6.8
O
CE
C
f
V
V
V
V
= 5V, I = 100µA
T
CE
EB
CB
C
Emitter-To-Base Capacitance
Collector-To-Base Capacitance
Base-To-Substrate Capacitance
C
C
= -3V
= -3V
0.85
2.25
3.05
EB
pF
CB
C
= 3V
BI
pF
BI
Typical Applications
9
8
7
6
5
4
3
2
1
0
(SUBSTRATE)
16
CENTER FREQUENCY: 1kHz
2
f
500Ω
1
1
3kΩ
1µF
0.1µF
1kΩ
Q
4
3
15 10
14
12
11
Q
5
3kΩ
V+ = 10V
13
1kΩ
0.1µF
OUTPUT
6
4
7
44003
9
f
500Ω
2
Q
5
2
8
-20
-10
- f > 0
0
= f
10
f - f > 0
1
20
f
f
2
1
1
2
2
NOTE: F OR F < 10kHz
1
2
FREQUENCY DEVIATION (kHz)
FIGURE 1. FREQUENCY COMPARATOR USING CA3096
FIGURE 2. FREQUENCY COMPARATOR CHARACTERISTICS
4
CA3096, CA3096A, CA3096C
Typical Applications (Continued)
3
G
MT
MT
1
NTC
SENSOR
10kΩ
10kΩ
5.1kΩ
1kΩ
T2300B
10
13
2
2
+
-
Q
14
100µF
12V
5
11
Q
120V
AC
4
Q
1
6
4
12
15
1
7
R
P
5
Q
LOAD
2
6.8kΩ
2W
Q
5.1kΩ
10kΩ
3
8
9
16
FIGURE 3. LINE-OPERATED LEVEL SWITCH USING CA3096A OR CA3096
+6V
40841
MOSFET
13
20kΩ
5kΩ
5kΩ
Q
5
14
15
OUTPUT
10
3
6
4
9
7
20kΩ
1kΩ
11
Q
4
5
8
Q
1
Q
Q
2
3
1
12
2
50MΩ
5µF
1kΩ
3.9kΩ
10kΩ
16
TIME DELAY CHANGES ±7%
FOR SUPPLY VOLTAGE CHANGE OF ±10%
FIGURE 4. ONE-MINUTE TIMER USING CA3096A AND A MOSFET
V+
1kΩ
R
1kΩ
36
L
---------------
= ±
V
T
I
R
O
L
E
12
O
+V
V
T
IF I = 1mA AND R = 1kΩ
O
L
Q
t
IN
4
11
14
V
= ± 36mV
T
10
2kΩ
-V
T
15
Q
5
13
4
6
3
100Ω
V
Q
2
IN
Q
1
5
1
E
O
0
100Ω
2
9
t
I
O
1kΩ
8
Q
1kΩ
3
7
V-
FIGURE 5. CA3096A SMALL-SIGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY
5
CA3096, CA3096A, CA3096C
Typical Applications (Continued)
1.5V
LAMP GE 2158D
OR EQUIVALENT
13
Q
5
2kΩ
14
15
10kΩ
10
9
Q
Q
3
8
11
4
3
6
2
12
7
1.5MΩ
Q
1
Q
5
1
2
4
2kΩ
5µF
500kΩ
1kΩ
16
(SUBSTRATE)
FIGURE 6. TEN-SECOND TIMER OPERATED FROM 1.5V SUPPLY USING CA3096
+6V
100kΩ
6.2kΩ
6.2kΩ
1%
1%
1%
OUTPUT
10
13
6
5
3
NOTES:
Q
Q
11
14
1
INPUT
100kΩ
Q
Q
1
4
5
2
5. Can be operated with either dual
supply or single supply.
100kΩ
1%
4
2
12
15
1%
6. Wide-inputcommonmoderange
+5V to -5V.
9
7
7. Low bias current: <1µA.
Q
3
8
5kΩ
1%
51kΩ
1%
51kΩ
300Ω
1kΩ
1%
1%
1%
-6V
16
FIGURE 7. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA3096A
70
60
50
40
30
20
10
1
10
100
1000
FREQUENCY (kHz)
FIGURE 8. FREQUENCY RESPONSE
6
CA3096, CA3096A, CA3096C
Typical Performance Curves
4
10
10
3
10
1
V
Z
V
= 10V
2
CE
10
V
= 5V
CE
10
-1
10
1
-2
-1
10
10
7
7.5
8
8.5
9
-100
-75
-50
-25
0
25
o
50
75
100
ZENER VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 9. BASE-TO-EMITTER ZENER CHARACTERISTIC (NPN)
FIGURE 10. COLLECTOR CUT-OFF CURRENT (I
) vs
CEO
TEMPERATURE (NPN)
3
10
500
o
T
= 85 C
A
2
10
400
300
200
100
0
o
V
= 15V
T
= 25 C
CB
A
10
1
V
= 10V
CB
o
T
= -40 C
V
= 5V
A
CB
-1
10
10
-2
-75
-50
-25
0
25
50
75
100
0.01
0.1
1
10
o
TEMPERATURE ( C)
COLLECTOR CURRENT (mA)
FIGURE 11. COLLECTOR CUT-OFF CURRENT (I
TEMPERATURE (NPN)
) vs
FIGURE 12. TRANSISTOR (NPN) h vs COLLECTOR
FE
CBO
CURRENT
0.9
V
= 5V
CE
o
I
I
I
I
= 10mA, 1.67mV/ C
C
C
C
C
0.9
0.8
0.7
0.6
0.5
0.4
o
0.8
0.7
0.6
0.5
0.4
= 5mA, 1.77mV/ C
o
= 1mA, 1.90mV/ C
o
= 100µA, 2.05mV/ C
-40
-20
0
20
40
60
80
100
0.01
0.1
1
10
o
COLLECTOR CURRENT (mA)
TEMPERATURE ( C)
FIGURE 13. V
(NPN) vs COLLECTOR CURRENT
FIGURE 14. V
(NPN) vs TEMPERATURE
BE
BE
7
CA3096, CA3096A, CA3096C
Typical Performance Curves (Continued)
4
3
2
10
10
10
o
T
= 85 C
A
1.0
0.8
0.6
0.4
0.2
0.1
o
V = -15V
CE
T
= 25 C
A
β = 10
V
= -10V
CE
o
V
= -5V
T
= -40 C
CE
A
10
1
-50
-25
0
25
50
75
100
0.1
1.0
10
100
o
COLLECTOR CURRENT (mA)
TEMPERATURE ( C)
FIGURE 15. V
(NPN) vs COLLECTOR CURRENT
FIGURE 16. COLLECTOR CUT-OFF CURRENT (I
TEMPERATURE (PNP)
) vs
CEO
CE SAT
3
10
110
100
90
80
70
60
50
40
30
20
10
0
V
= 20V
CE
V
= -15V
CB
V
= 5V
CE
V
= -10V
CB
2
10
V
= -5V
CB
V
= 1V
CE
10
1
-50
-25
0
25
50
o
75
100
0.01
0.1
1.0
10
TEMPERATURE ( C)
COLLECTOR CURRENT (mA)
FIGURE 17. COLLECTOR CUT-OFF CURRENT (I
) vs
CBO
FIGURE 18. TRANSISTOR (PNP) h vs COLLECTOR CURRENT
FE
TEMPERATURE (PNP)
100
1.0
V
= 5V
CE
V
= 5V
CE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= 100µA
C
80
60
40
20
0
I
I
= 10µA
C
= 1mA
C
I
= 5mA
C
-40
-20
0
20
40
o
60
80
0.01
0.1
1.0
10
TEMPERATURE ( C)
COLLECTOR CURRENT (mA)
FIGURE 19. TRANSISTOR (PNP) h vs TEMPERATURE
FE
FIGURE 20. V
(PNP) vs COLLECTOR CURRENT
BE
8
CA3096, CA3096A, CA3096C
Typical Performance Curves (Continued)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
o
I
= 5mA, ∆V /∆T - 0.97mV/ C
C
BE
o
I
= 1mA, -1.84mV/ C
C
o
I
= 100µA, -2.2mV/ C
C
-40
-20
0
20
40
o
60
80
0.01
0.1
1.0
10
TEMPERATURE ( C)
COLLECTOR CURRENT (mA)
FIGURE 21. V
(PNP) vs TEMPERATURE
FIGURE 22. MAGNITUDE OF INPUT OFFSET VOLTAGE |V | vs
IO
BE
COLLECTOR CURRENT FOR NPN TRANSISTOR
Q
- Q
2
1
18
16
14
12
10
8
0.5
R
= 500Ω
SOURCE
0.4
0.3
0.2
0.1
0
I
= 3mA
C
1mA
10µA
6
100µA
4
2
0
0.01
0.1
1.0
FREQUENCY (kHz)
10
100
0.01
0.1
1
10
COLLECTOR CURRENT (mA)
FIGURE 23. MAGNITUDE OF INPUT OFFSET VOLTAGE |V | vs
IO
FIGURE 24. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS
COLLECTOR CURRENT FOR PNP TRANSISTOR
Q
- Q
5
4
18
16
14
12
10
8
28
R
= 1kΩ
SOURCE
R
= 10kΩ
SOURCE
24
20
16
12
8
I
= 3mA
C
I
= 3mA
C
1mA
1mA
6
10µA
10µA
4
4
100µA
100µA
2
0
0.01
0
0.01
0.1
1
10
100
0.1
1.0
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
FIGURE 25. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS
FIGURE 26. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS
9
CA3096, CA3096A, CA3096C
Typical Performance Curves (Continued)
400
300
200
100
0
28
24
20
16
12
8
R
= 100kΩ
V
= 5V
SOURCE
R
CE
= 1MΩ
SOURCE
I
= 1mA
C
100µA
10µA
100µA
4
10µA
0
0.01
0.1
1.0
10
0.1
1
10
100
FREQUENCY (kHz)
COLLECTOR CURRENT (mA)
FIGURE 27. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS
FIGURE 28. GAIN-BANDWIDTH PRODUCT vs COLLECTOR
CURRENT (NPN)
4.0
3.5
3.0
1000
f = 1kHz
C
CI
100
2.5
2.0
1.5
1.0
0.5
NPN
PNP
10
C
EB
2
C
CB
1
0.01
0
1
3
4
5
6
7
8
9
10
0.1
1
10
BIAS VOLTAGE (V)
COLLECTOR CURRENT (mA)
FIGURE 29. CAPACITANCE vs BIAS VOLTAGE (NPN)
FIGURE 30. INPUT RESISTANCE vs COLLECTOR CURRENT
4
10
40
f = 1kHz
g
I = 1mA
C
FE
30
20
10
0
NPN
3
2
10
PNP
10
g
100µA
100µA
FE
b
10
1
FE
-10
-20
b
1mA
10
FE
0.01
0.1
1.0
10
1
100
COLLECTOR CURRENT (mA)
FREQUENCY (MHz)
FIGURE 31. OUTPUT RESISTANCE vs COLLECTOR CURRENT
FIGURE 32. FORWARD TRANSCONDUCTANCE vs FREQUENCY
10
CA3096, CA3096A, CA3096C
Typical Performance Curves (Continued)
6
5
4
3
2
1
0
g
b
IE
IE
I
= 10mA
C
2.5
2.0
1.5
1.0
0.5
0
I
= 1mA
C
b
OE
10mA
1mA
100µA
b
OE
100µA
10µA
1mA
1mA
g
OE
100µA
g
100µA
OE
10µA
100
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
FIGURE 33. INPUT ADMITTANCE vs FREQUENCY
FIGURE 34. OUTPUT ADMITTANCE vs FREQUENCY
30
20
10
0
30
20
10
0
R
= 500Ω
SOURCE
R
= 1kΩ
SOURCE
I
= 1mA
C
I
= 1mA
C
10µA
10µA
100µA
100µA
0.01
0.1
1.0
FREQUENCY (kHz)
10
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 35. NOISE FIGURE vs FREQUENCY (PNP)
FIGURE 36. NOISE FIGURE vs FREQUENCY (PNP)
8
7
6
5
4
40
30
20
10
0
R
= 10kΩ
V
= 5V
SOURCE
CE
I
= 1mA
C
100µA
10µA
0.1
1.0
10
0.01
0.1
1.0
FREQUENCY (kHz)
10
100
COLLECTOR CURRENT (mA)
FIGURE 37. NOISE FIGURE vs FREQUENCY (PNP)
FIGURE 38. GAIN-BANDWIDTH PRODUCT vs COLLECTOR
CURRENT (PNP)
11
CA3096, CA3096A, CA3096C
Typical Performance Curves (Continued)
6
5
4
3
2
C
BI
C
BC
C
BE
1
0
0
1
2
3
4
5
6
7
8
9
10
BIAS VOLTAGE (V)
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
CA3096H
Metallization Mask Layout
0
10
20
30
40
40
30
20
10
0
37-45
(0.940-1.143)
4-10 (0.102-0.254)
37-45
(0.940-1.143)
Dimensions in parentheses are in millimeters and are derived from the
-3
basic inch dimensions as indicated. Grid graduations are in mils (10
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
12
CA3096, CA3096A, CA3096C
Dual-In-Line Plastic Packages (PDIP)
D
E
E16.3 (JEDEC MS-001-BB ISSUE D)
BASE
PLANE
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A2
A
-C-
INCHES
MILLIMETERS
SEATING
PLANE
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
L
C
L
D1
B1
A
A1
A2
B
-
4
eA
A1
A
D1
e
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
C
eC
B
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
eB
0.010 (0.25)
C
B
S
M
-
NOTES:
B1
C
8, 10
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
D
5
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
D1
E
5
0.325
0.280
8.25
7.11
6
4. Dimensions A, A1 and L are measured with the package seated in JE-
E1
e
5
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
B
e
6. E and
are measured with the leads constrained to be perpendic-
A
-
0.430
0.150
-
10.92
3.81
7
-C-
ular to datum
.
L
0.115
2.93
4
9
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
N
16
16
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
13
CA3096, CA3096A, CA3096C
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
M
L
M
B
0.25(0.010)
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
-
9
SEATING PLANE
A
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
D
h x 45
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
M
M
S
B
0.25(0.010)
C
A
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
14
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