CA3310M [INTERSIL]
CMOS, 10-Bit, A/D Converters with Internal Track and Hold; CMOS ， 10位，具有内部采样和保持的A / D转换器
| 型号： | CA3310M |
| 厂家： | 
Intersil |
| 描述： | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| 文件： | 总15页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3310, CA3310A
CMOS, 10-Bit, A/D Converters
with Internal Track and Hold
August 1997
Features
Description
The Intersil CA3310 is a fast, low power, 10-bit successive
approximation analog-to-digital converter, with microprocessor-
compatible outputs. It uses only a single 3V to 6V supply and
typically draws just 3mA when operating at 5V. It can accept full
rail-to-rail input signals, and features a built-in track and hold.
The track and hold will follow high bandwidth input signals, as it
has only a 100ns (typical) input time constant.
• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .15mW
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . 3V to 6V
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 13µs
• Built-In Track and Hold
• Rail-to-Rail Input Range
The ten data outputs feature full high-speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. Separate 8 MSB and 2 LSB enables,
a data ready flag, and conversion start and ready reset
inputs complete the microprocessor interface.
• Latched Three-state Output Drivers
• Microprocessor-Compatible Control Lines
• Internal or External Clock
An internal, adjustable clock is provided and is available as
an output. The clock may also be driven from an external
source.
Applications
• Fast, No-Droop, Sample and Hold
• Voice Grade Digital Audio
• DSP Modems
Ordering Information
PART
LINEARITY
TEMP.
PKG.
NO.
o
NUMBER (INL, DNL) RANGE ( C) PACKAGE
• Remote Low Power Data Acquisition Systems
• µP Controlled Systems
CA3310E
CA3310AE
CA3310M
CA3310AM
CA3310D
CA3310AD
±0.75 LSB
±0.5 LSB
±0.75 LSB
±0.5 LSB
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld SOIC
-40 to 85 24 Ld SOIC
E24.6
E24.6
M24.3
M24.3
±0.75 LSB -55 to 125 24 Ld SBDIP D24.6
±0.5 LSB -55 to 125 24 Ld SBDIP D24.6
Pinout
CA3310, CA3310A
(PDIP, SBDIP, SOIC)
TOP VIEW
D0 (LSB)
D1
1
2
3
4
5
6
7
8
9
24
V
V
V
DD
23
22
21
IN
D2
+
REF
R
D3
EXT
D4
20 CLK
19 STRT
D5
D6
18
17
16
V
-
REF
D7
V
+
-
AA
D8
V
AA
D9 (MSB) 10
DRDY 11
15 OEL
14 OEM
V
(GND) 12
13 DRST
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number 3095.1
6-6
CA3310, CA3310A
Functional Block Diagram
STRT
R
V
EXT
DD
ALL
CLOCK
LOGIC
CLK
V
SS
DRDY
CONTROL
AND
Q
V
IN
TIMING
DRST
CLK
CLR
OEM
V
+
16C
8C
4C
2C
C
REF
D9 (MSB)
50Ω
SUBSTRATE
RESISTANCE
D8
D7
D6
D5
D4
D3
D2
D1
V
+
-
AA
10-BIT
EDGE
TRIGGERED
“D”
32
31
V
10-BIT
AA
C
SUCCESSIVE
APPROXIMATION
REGISTER
16C
8C
4C
2C
C
LATCH
D0 (LSB)
OEL
C
V
-
REF
6-7
CA3310, CA3310A
Typical Application Schematics
+5V SUPPLY
0.1µF CER
+
4.7µF
TAN
A
D
8
V
+
V
DD
AA
100Ω ±10%
4.5V
75V
3
1
6
START CONVERSATION
V
V
+
STRT
REF
REF
+
4.7µF
ICL7663S
TAN
DRST
OEM
OEL
RESET FLAG
A
5K
ADJUST
GAIN
HIGH BYTE ENABLE
LOW BYTE ENABLE
28.7K
-
4
5
CA3310/A
A
D0 - D9
A
A
OUTPUT DATA
DATA READY FLAG
2MHz CLOCK
NC
A
V
-
AA
R3
R2
R1
R4
100
0.1
+8V
TO
+15V
DRDY
CLK
A
OPTIONAL
CLAMP
7
A
R
3
2
EXT
8
V
DD
+
-
+
6
V
V
IN
IN
CA3140
V
SS
-
5
UNLESS NOTED,
ALL RESISTORS =
1% METAL FILM,
R5
47pF
10K
1
4
D
POTS = 10 TURN, CERMET
ADJUST
OFF SET
D = DIGITAL GROUND
A = ANALOG GROUND
0.1
A
D
A
-1V
TO
100
-15V
INPUT RANGE
0V TO 2.5V
0V TO 5V
R1
R2
R3
R4
R5
4.99K
9.09K
4.53K
4.53K
9.09K
9.09K
OPEN
OPEN
OPEN
9.09K
9.09K
4.99K
4.99K
10K
9.09K
4.53K
4.53K
4.53K
4.53K
4.99K
10K
0V TO 10V
-2.5V TO +2.5V
-5V TO +5V
4.99K
10K
4.99K
10K
6-8
CA3310, CA3310A
Absolute Maximum Ratings
Thermal Information
o
o
Digital Supply Voltage V . . . . . . . . . . . . . . .V -0.5V to V +7V
DD SS SS
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
Analog Supply Voltage (V +) . . . . . . . . . . . . . . . . . . . . .V
±0.5V
+ 0.5V
PDIP Package . . . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
75
70
75
N/A
22
N/A
AA
DD
DD
Any Other Terminal . . . . . . . . . . . . . . . . .V -0.5V to V
SS
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Drain Current, per Output. . . . . . . . . . . . . . . . . . ±35mA
Total DC Supply or Ground Current . . . . . . . . . . . . . . . . . . . ±70mA
o
o
o
o
Maximum Storage Temperature (T
) . . . . . . . . . .-65 C to 150 C
STG
o
Operating Conditions
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
Temperature Range (T )
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Package Type E, M . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
A
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, V = V + = 5V, V
+ = 4.608V, V = V - = V
- = GND, CLK = External 1MHz,
REF
A
DD
AA
REF
SS
AA
Unless Otherwise Specified
PARAMETER
ACCURACY (See Text For Definitions)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Differential Linearity Error
Integral Linearity Error
Gain Error
CA3310
CA3310A
CA3310
CA3310A
CA3310
CA3310A
CA3310
CA3310A
±0.5
±0.25
±0.5
±0.25
±0.25
-
±0.75
±0.5
±0.75
±0.5
±0.5
±0.25
±0.5
±0.25
-
-
-
-
-
Offset Error
-
±0.25
-
-
ANALOG OUTPUT
Input Resistance
In Series with Input Sample
Capacitors
-
330
-
Ω
Input Capacitance
Input Capacitance
Input Current
During Sample State
During Hold State
-
-
-
-
-
300
-
-
pF
pF
µA
µA
µA
20
-
At V = V
IN
+ = 5V
- = 0V
+300
-100
1
REF
REF
At V = V
IN
-
Static Input Current
STRT = V+, CLK = V+
-
At V = V
IN
+ = 5V
REF
At V = V
IN
- = 0V
-
-
-
-1
µA
V
REF
Input + Full-Scale Range
Input - Full-Scale Range
Input Bandwidth
(Note 2)
(Note 2)
V
- +1
V
+0.3
DD
REF
V
-0.3
-
V
+ -1
V
SS
REF
From Input RC Time Constant
-
1.5
-
MHz
DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Over V
= 3V to 6V (Note 2)
= 3V to 6V (Note 2)
70
-
-
-
-
% of
DD
DD
V
DD
Low-Level Input Voltage
Over V
30
% of
V
DD
Input Leakage Current
Input Capacitance
Input Current
Except CLK
(Note 2)
-
-
-
-
-
-
±1
10
µA
pF
µA
CLK Only (Note 2)
±400
6-9
CA3310, CA3310A
o
Electrical Specifications T = 25 C, V = V + = 5V, V
+ = 4.608V, V = V - = V
- = GND, CLK = External 1MHz,
REF
A
DD
AA
REF
SS
AA
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS D0 - D9, DRDY
High-Level Output Voltage
Low-Level Output Voltage
Three-State Leakage
Output Capacitance
I
I
= -4mA
4.6
-
-
-
-
-
V
V
SOURCE
= 6mA
-
-
-
0.4
±1
20
SINK
Except DRDY
µA
pF
Except DRDY (Note 2)
CLK OUTPUT
High-Level Output Voltage
Low-Level Output Voltage
TIMING
I
I
= 100µA (Note 2)
4
-
-
-
-
V
V
SOURCE
= 100µA (Note 2)
1
SlNK
Clock Frequency
Internal, CLK and R
Open
200
600
-
300
800
4
400
kHz
kHz
MHz
kHz
ns
EXT
Internal, CLK Shorted to R
1000
EXT
External, Applied to CLK (Note 2) (Max)
(Min)
2
-
100
100
10
-
Clock Pulse Width, t
Conversion Time
, t
LOW HIGH
External, Applied to CLK:
See Figure 1 (Note 2)
-
Internal, CLK Shorted to R
See Figure 1
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EXT
Aperture Delay, t APR
100
150
250
200
-120
160
10
D
Clock to Data Ready Delay, t DRDY
D1
See Figure 1
-
Clock to Data Ready Delay, t DRDY
D2
See Figure 1
-
Clock to Data Delay, t Data
See Figure 1
-
D
Start Removal Time, t STRT
See Figures 3 and 4 (Note 1)
See Figure 4
-
R
Start Setup Time, t
STRT
-
SU
Start Pulse Width, t STRT
See Figures 3 and 4
See Figures 3 and 4
See Figure 3
-
W
Start to Data Ready Delay, t DRDY
D3
-
170
200
-80
10
Clock Delay from Start, t CLK
-
D
Ready Reset Removal Time, t DRST
See Figure 50 (Note 1)
See Figure 5
-
R
Ready Reset Pulse Width, t DRST
W
-
Ready Reset to Data Ready Delay,
See Figure 5
-
35
t
DRDY
D4
Output Enable Delay, t
See Figure 2
See Figure 2
-
-
40
50
-
-
ns
ns
EN
Output Disable Delay, t
DIS
SUPPLIES
Supply Operating Range, V
DD
or V
AA
(Note 2)
3
-
-
6
8
-
V
mA
Supply Current, I
DD
+ I
AA
See Figures 14, 15
Clock Stopped During Cycle 1
At 120Hz, See Figure 13
See Figure 10
3
Supply Standby Current
Analog Supply Rejection
Reference Input Current
-
3.5
25
160
mA
-
-
mV/V
µA
-
-
TEMPERATURE DEPENDENCY
Offset Drift
o
At 0 to 1 Code Transition
At 1022 to 1023 Code Transition
See Figure 7
-
-
-
-4
-6
-
-
-
µV/ C
o
Gain Drift
µV/ C
o
Internal Clock Speed
NOTES:
-0.5
%/ C
1. A (-) removal time means the signal can be removed after the reference signal.
2. Parameter not tested, but guaranteed by design or characterization.
6-10
CA3310, CA3310A
Timing Diagrams
1
2
1
3
4
5 - 12
13
2
3
CLK
t
HIGH
t
DRDY
DRDY
D1
t
LOW
t
DRDY
D2
t
DATA
D
D0 - D9
INPUT
DATA N - 1
DATA N
HOLD
TRACK N
TRACK N + 1
t
APR
D
FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH
OEL OR OEM
t
DIS
t
EN
90%
D0 - D1 OR
D2- D9
50%
Z
= 50pF TO GND
L
1kΩ TO GND
TO OUTPUT PIN
= 50pF TO GND
OFF TO HIGH
OFF TO LOW
Z
L
50%
1kΩ TO V
DD
10%
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
13
1
2
3
4
5
CLK
(INTERNAL)
t
CLK
D
t
STRT
R
t
STRT
W
DON’T CARE
DRDY
STRT
t
D3
DRDY
INPUT
HOLD
HOLD
TRACK
FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK
6-11
CA3310, CA3310A
Timing Diagrams (Continued)
13
1
2
2
2
3
4
5
CLK
(EXTERNAL)
t
STRT
SU
t STRT
W
t
STRT
R
DON’T CARE
DRDY
STRT
DRDY
t
D3
HOLD
INPUT
HOLD
TRACK
FIGURE 4. STRT PULSED LOW, DRST TIED HIGH, EXTERNAL CLOCK
13
1
CLK
(INTERNAL
OR
DON’T CARE
EXTERNAL)
t
DRST
R
t
DRST
W
DRST
DRDY
t
D4
DRDY
FIGURE 5. DRST PULSED LOW, STRT TIED HIGH
Typical Performances Curves
800
700
= 3V - 6V = V
V
= V + = 3V - 6V
AA
DD
INTERNAL CLOCK MAY NOT
V
+
DD
AA
5
4
3
V
= 6V
DD
5V
4V
V
= 6V
WORK AT V
DD
TEMPERATURE < -40 C
< 4V FOR
o
DD
600
500
400
5V
4V
R
R
= SHORTED
= OPEN
EXT
EXT
3V
300
200
100
6V
2
1
3V
5V
4V
-55 -40
0
3V
0
SHORT
10
100
1000
OPEN
0
25
85
125
EXTERNAL RESISTANCE (kΩ)
o
TEMPERATURE ( C)
FIGURE 7. INTERNAL CLOCK FREQUENCY vs
TERMPERATURE AND SUPPLY VOLTAGE
FIGURE 6. INTERNAL CLOCK FREQUENCY vs EXTERNAL
RESISTANCE
6-12
CA3310, CA3310A
Typical Performances Curves (Continued)
+80
+60
+50
+40
V
V
+ = 3 - 6V
AA
V
+ = 3 - 6V
AA
+ = V
= V
+
REF
AA
DD
V
+ = 6V
AA
V
+ = V
= V
+
REF
+60
AA
DD
CLOCK = INTERNAL,
FREE RUNNING
+40
+30
+20
(+) I
PEAK
3V
5V
+20
0
4V
4V
3V
+10
0
6V
5V
= 6V
-20
-40
-10
(-) I
PEAK
V
AA
-20
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 8. PEAK INPUT CURRENT vs INPUT VOLTAGE
FIGURE 9. AVERAGE INPUT CURRENT vs INPUT VOLTAGE
80
60
40
20
0
40
30
20
V
+ = V
= V
+
REF
AA
DD
I
AVE
CLOCK INTERNAL,
FREE RUNNING
5
I
PEAK
GAIN
4
3
OFFSET
2
10
0
DLE
1
ILE
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
V
+ VOLTAGE (V)
REF
REFERENCE VOLTAGE (V)
FIGURE 10. V
+ CURRENT vs V
+ VOLTAGE
REF
FIGURE 11. NORMALIZED GAIN, OFFSET, INTEGRAL AND
DIFFERENTIAL LINEARITY ERRORS vs
REFERENCE VOLTAGE
REF
8
1000
V
= V
AA
= V
+ = 5V
DD
REF
= 1MHz
7
f
CLOCK
6
5
V
= (+) FULL SCALE
IN
ILE
100
4
3
2
V
= (-) FULL SCALE
IN
DLE
OFFSET
1
0
GAIN
10
100
1000
, RIPPLE FREQUENCY (Hz)
AA
10,000
100,000
0.1
1
2
3
4
5
V
CLOCK FREQUENCY (MHz)
FIGURE 12. NORMALIZED GAIN, OFFSET, INTEGRAL AND
DIFFERENTIAL LINEARITY ERRORS vs CLOCK
SPEED
FIGURE 13. V SUPPLY SENSITIVITY
AA
6-13
CA3310, CA3310A
Typical Performances Curves (Continued)
12
8
7
6
V
= 3-6V
DD
AND R
V
= V
AA
= V
= 3 - 6V
REF
DD
= OPEN OR SHORTED.
EXT
CLOCK = INTERNAL, FREE RUNNING
= V
LOAD = 50pF/OUTPUT
10
8
CONTINUOUS CONVERSIONS
V
+
AA
DD
V
= 6V, R = SHORT
EXT
DD
5
4
6V
5V, OPEN
5V, SHORT
6
V
= 6V, R = OPEN
EXT
DD
3
2
1
0
4
5V
4V, OPEN
4V, SHORT
3V, SHORT
2
4V
3V, OPEN
3V
1.0
CLOCK FREQUENCY (MHz)
0
0
0.5
1.5
2.0
2.5
3.0
3.5
-50
25
TEMPERATURE ( C)
85
125
-40
0
o
FIGURE 14. SUPPLY CURRENT vs CLOCK FREQUENCY
FIGURE 15. SUPPLY CURRENT vs TEMPERATURE
TABLE 1. PIN DESCRIPTIONS
DESCRIPTION
PIN NUMBER
NAME
0
9
1-10
D0 - D9
Three-State outputs for data bits representing 2 (LSB) through 2 (MSB).
11
DRDY
Output flag signifying new data is available. Goes high at end of clock period 13, goes low when new
conversion started. Also reset asynchronously by DRST.
12
13
14
15
16
17
18
19
20
21
22
23
24
V
Digital Ground.
SS
DRST
OEM
OEL
Active low input, resets DRDY.
Active low input, three-state enable of D2 - D9.
Active low input, three-state enable of D0, D1.
Analog Ground.
V
-
AA
V
+
Analog + Supply.
AA
V
-
Reference input voltage, sets 0 code (-) end of input range.
Active Low Start Conversion Input. Recognized after end of clock period 13.
Clock input or output. Conversion functions are synchronous to high-going edge.
Clock adjust input when using internal clock.
Reference input voltage, set 1023 code (+) end of input range.
Analog Input.
REF
STRT
CLK
R
EXT
V
+
REF
V
lN
V
Digital + Supply.
DD
TABLE 2. OUTPUT CODES
CODE
DESCRIPTION
BINARY OUTPUT CODE
INPUT
VOLTAGE (NOTE 1)
MSB
LSB
(V
– V
) = 4.608V
(V
– V
)
REF-
REF+
REF-
(V)
DECIMAL
COUNT
REF+
LSB = ---------------------------------------------
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
1024
Zero
0.000
0
1
1 LSB
1
0.0045
1.152
2.304
3.456
4.6035
0
0
0
0
0
0
0
0
0
1
/
/
/
(V
(V
(V
+ - V
+ - V
+ - V
-)
-)
-)
0
1
0
0
0
0
0
0
0
0
256
512
768
1023
4
2
4
REF
REF
REF
REF
REF
REF
1
3
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
(V
+ - V
-) - 1 LSB
REF
1
1
1
1
1
1
1
1
1
1
REF
NOTE:
1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
6-14
CA3310, CA3310A
Device Operation
The CA3310 is a CMOS 10-bit, analog-to-digital converter The R
that uses capacitor-charge balancing to successively frequency by connecting a resistor between R
EXT
pin allows adjusting of the internal clock
and CLK.
EXT
approximate the analog input. A binarily weighted capacitor Figure 6 shows the typical relationship between the resistor
network forms the D-to-A “Heart” of the device. See the and clock speed, while Figure 7 shows clock speed versus
Functional Diagram of the CA3310.
temperature and supply voltage.
The capacitor network has a common node which is connected
to a comparator. The second terminal of each capacitor is indi-
The internal clock will shut down if the A/D is not restarted after
a conversion. This is described under Control Timing. The clock
could also be shut down with an open collector driver applied to
the CLK pin. This should only be done during the sample por-
tion (the first three periods) of a conversion cycle, and might be
useful for using the device as a digital sample and hold: this is
described further under Applications.
vidually switchable to the input, V
+ or V -.
REF
REF
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input.
The comparator is being auto-balanced at its trip point, thus
setting the voltage at the capacitor common node.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again only during the sam-
ple portion of a conversion cycle. At other times, it must be
above the minimum frequency shown in the specifications.
During the fourth period, all capacitors are disconnected
from the input, the one representing the MSB (D9) is con-
nected to the V
to V
REF
+ terminal, and the remaining capacitors
-. The capacitor-common node, after the charges
REF
balance out, will represent whether the input was above or
1
below / of (V
+ - V
).
2
REF
REF
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 13) of the A/D, the
output might be invalid due to balancing capacitor droop.
At the end of the fourth period, the comparator output is
stored and the MSB capacitor is either left connected to
V
+ (if the comparator was high) or returned to V
-.
REF
REF
4
An external clock must also meet the minimum t
and
times shown in the specifications. A violation may
3
1
LOW
This allows the next comparison to be at either / or / of
(V
4
t
HIGH
+ - V
-).
REF
REF
cause an internal miscount and invalidate the results.
At the end of periods 5 through 12, capacitors representing
the next to MSB (D8) through the next to LSB (D1) are
tested, the result stored, and each capacitor either left at
Control Signals
The CA3310 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sions, or if STRT is tied low, may be allowed to free-run. In
the free-running mode, illustrated in Figure 1, each
conversion takes 13 clock periods.
V
+ or at V -.
REF
REF
At the end of the 13th period, when the LSB (D0) capacitor is
tested, D0 and all the previous results are shifted to the out-
put registers and drivers. The capacitors are reconnected to
the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by T
data), the output is updated.
D
Clock
The CA3310 can operate either from its internal clock or
from one externally supplied. The CLK pin functions either
as the clock output or input. All converter functions are syn-
chronous with the rising edge of the clock signal.
The DRDY (Data Ready) status output goes high (specified
by t DRDY) after the start of clock period 1, and returns
D1
low (specified by t DRDY) after the start of clock period 2.
D2
DRDY may also be asynchronously reset by a low on DRST
(to be discussed later).
Figure 16 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
wiring capacitance should be kept to a minimum.
If the output data is to be latched externally by the DRDY
signal, the trailing edge of DRDY should be used: there is no
guaranteed set-up time to the leading edge.
The 10 output data bits are available in parallel on three-
state bus driver outputs. When low, the OEM input enables
the most significant byte (D2 through D9) while the OEL
INTERNAL
ENABLE
OPTIONAL
EXTERNAL
CLOCK
INTERNAL
CLOCK
input enables the two least significant bits (D0, D1). t
and
EN
specify the output enable and disable times, respec-
t
DIS
tively. See Figure 2.
CLK
When the STRT input is used to initiate conversions,
operation is slightly different depending on whether an
internal or external clock is used.
OPTIONAL
CLOCK
ADJUST
100K
R
EXT
Figure 3 illustrates operation with an internal clock. If the
50K
18pF
STRT signal is removed (at least t STRT) before clock
R
FIGURE 16. CLOCK CIRCUITRY
period 1, and is not reapplied during that period, the clock
6-15
CA3310, CA3310A
will shut off after entering period 2. The input will continue to Accuracy Specifications
track the DRDY output will remain high during this time.
The CA3310 accepts an analog input between the values of
10
V
- and V
+, and quantizes it into one of 2 or 1024
A low signal applied to STRT (at least t STRT wide) can
W
now initiate a new conversion. The STRT signal (after a
REF
REF
output codes. Each code should exist as the input is varied
1
through a range of /
1024
X (V
+ - V -), referred to as
REF
delay of t
DRDY) will cause the DRDY flag to drop, and
REF
D3
1 LSB of input voltage. A differential Iinearity error, illustrated
in Figure 17, occurs if an output code occurs over other than
the ideal (1 LSB) input range. Note that as long as the error
does not reach -1 LSB, the converter will not miss any codes.
(after a delay of t CLK) cause the clock to restart.
D
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
The input will continue to track until the end of period 3, the
same as when free-running.
UNIFORM
TRANSFER
CURVE
Figure 4 illustrates the same operation as above, but with an
external clock. If STRT is removed (at least t STRT) before
R
A
B
clock period 1, and not reapplied during that period, the
clock will continue to cycle in period 2. A low signal applied
to STRT will drop the DRDY flag as before, and with the first
OUTPUT
C
positive-going clock edge that meets the t
time, the converter will continue with clock period 3.
STRT set-up
SU
CODE
The DRDY flag output, as described previously, goes active
at the start of period 1, and drops at the start of period 2 or
upon a new STRT command, whichever is later. It may also
be controlled with the DRST (Data Ready Reset) input.
Figure 5 depicts this operation.
ACTUAL
TRANSFER
CURVE
A = IDEAL 1 LSB STEP
B-A = + DIFFERENTIAL LINEARITY ERROR
A-C = - DIFFERENTIAL LINEARITY ERROR
DRST must be removed (at least t DRST) before the start
R
of period 1 to allow DRDY to go high. A low level on DRST
INPUT VOLTAGE
(at least t DRST wide) will (after a delay of t DRDY) drop
W
D4
FIGURE 17. DIFFERENTIAL LINEARITY ERROR
DRDY.
Analog Input
The CA3310 output should change from a code of 000 to
16
001 at an input voltage of (V
- +1 LSB). It should also
The analog input pin is a predominantly capacitive load that
changes between the track and hold periods of a conversion
cycle. During hold, clock period 4 through 13, the input
loading is leakage and stray capacitance, typically less than
0.1µA and 20pF.
16
REF
to 3FF
change from a code of 3FE
at an input of
16
16
(V
+ -1 LSB). Any differences between the actual and
REF
expected input voltages that cause these transitions are the
offset and gain errors, respectively. Figure 18 illustrates
these errors.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have low
enough impedance to dissipate the charge by the end of the
tracking period. The amount of charge is dependent on supply
and input voltages. Figure 8 shows typical peak input currents
for various supply and input voltages, while Figure 9 shows
typical average input currents. The average current is also pro-
portional to clock frequency, and should be scaled accordingly.
As the input voltage is increased linearly from the point that
causes the 000 to 001 transition to the point that causes
16 16
the 3FE to 3FF transition, the output code should also
16 16
increase linearly. Any deviation from this input-to-output cor-
respondence is integral linearity error, illustrated in Figure 19.
Note that the integral linearity is referenced to a straight line
drawn through the actual end points, not the ideal end
points. For absolute accuracy to be equal to the integral lin-
earity, the gain and offset would have to be adjusted to ideal.
During tracking, the input appears as approximately a 300pF
capacitor in series with 330Ω, for a 100ns time constant. A
1
1
full-scale input swing would settle to / LSB ( /
) in 7RC
Offset and Gain Adjustments
2
2048
time constants. Doing continuous conversions with a 1MHz
clock provides 3µs of tracking time, so up to 1kΩ of external
source impedance (400ns time constant) would allow proper
settling of a step input.
The V
REF
+ and V - pins, references for the two ends of
REF
the analog input range, are the only means of doing offset or
gain adjustments. In a typical system, the V - might be
REF
returned to a clean ground, and offset adjustment done on
an input amplifier. V + would then be adjusted for gain.
If the clock was slower, or the converter was not restarted
immediately (causing a longer sample lime), a higher source
impedance could be used.
REF
- could be raised from ground to adjust offset or to accom-
V
REF
modate an input source that can’t drive down to ground. There
The CA3310s low-input time constant also allows good are current pulses that occur, however, during the successive
tracking of dynamic input waveforms. The sampling rate with approximation part of a conversion cycle, as the charge-balanc-
a 1MHz clock is approximately 80kHz. A Nyquist rate ing capacitors are switched between V
- and V
+. For
+ should be well bypassed.
REF
REF
(f
/2) input sine wave of 40kHz would have negligible that reason, V
SAMPLE REF
- and V
REF
attenuation and a phase lag of only 1.5 degrees. Figure 10 shows peak and average V
+ current.
REF
6-16
CA3310, CA3310A
3FF
3FE
EXPECTED
TRANSFER
CURVE
OFFSET
ERROR
GAIN
ERROR
002
001
000
ACTUAL
TRANSFER
CURVE
1
1024
2
1024
1022
1024
1023
1024
0
1
INPUT VOLTAGE AS A FRACTION OF (V
REF
+ - V
-)
REF
FIGURE 18. GAIN AND OFFSET ERROR
3FF
3FE
ACTUAL
TRANSFER
CURVE
IDEAL
TRANSFER
CURVE
OUTPUT
CODE
(HEX)
INTEGRAL
LINEARITY
ERROR
001
000
OFFSET POINT
GAIN POINT
INPUT VOLTAGE
FIGURE 19. NORMALIZED GAIN, OFFSET, INTEGRAL AND DIFFERENTIAL LINEARITY ERRORS vs REFERENCE VOLTAGE
6-17
CA3310, CA3310A
Other Accuracy Effects
Linearity, offset, and gain errors are dependent on the
Application Circuits
Differential Input A/D System
magnitude of the full-scale input range, V + - V -.
REF
REF
As the CA3310 accepts a unipolar positive-analog input, the
accommodation of other ranges requires additional circuitry.
The input capacitance and the input energy also force using
a low-impedance source for all but slow speed use. Figure
20 shows the CA3310 with a reference, input amplifier, and
input-scaling resistors for several input ranges.
Figure 11 shows how these errors vary with full-scale range.
The clocking speed is a second factor that affects conversion
accuracy. Figure 12 shows the typical variation of linearity,
offset, and gain errors versus clocking speed.
Gain and offset drift due to temperature are kept very low by
means of auto-balancing the comparator. The specifications
show typical offset and gain dependency on temperature.
The ICL7663S regulator was chosen as the reference, as it
can deliver less than 0.25V input-to-output (dropout) voltage
and uses very little power. As high a reference as possible is
generally desirable, resulting in the best linearity and
rejection of noise at the CA3310.
There is also very little linearity change with temperature, only
that caused by the slight slowing of CMOS with increasing
o
temperature. At 85 C, for instance, the lLE and DLE would be
o
typically those for a 20% faster clock than at 25 C.
The tantalum capacitor sources the V
current spikes
REF
during a conversion cycle. This relieves the response and
peak current requirements of the reference.
Power Supplies and Grounding
V
(+) and V (GND) are the digital supply pins: they
SS
DD
The CA3140 operational amplifier provides good slewing
capability for high bandwidth input signals and can quickly
operate all internal logic and the output drivers. Because the
output drivers can cause fast current spikes in the V and
DD
should have a low impedance path to digital
settle the energy that the CA3310 outputs at its V terminal.
lN
V
lines, V
SS
ground and V
SS
It can also drive close to the negative supply rail.
should be well bypassed.
DD
If system supply sequencing or an unknown input voltage is
likely to cause the operational amplifier to drive above the
Except for V +, which is a substrate connection to V , all
DD
DD
pins have protection diodes connected to V
and V
:
DD
SS
V
supply, a diode clamp can be added from pin 8 of the
DD
operational amplifier to the V
input transients above V
or below V will get steered to
DD
SS
supply. The minus drive
DD
the digital supplies. Current on these pins must be limited by
external means to the values specified under maximum
ratings.
current is low enough not to require protection.
With a 2MHz clock (~150kHz sampling), Nyquist criteria would
give a maximum input bandwidth of 75kHz. The resistor values
chosen are low enough to not seriously degrade system band-
width (an operational amplifier settling) at that clock frequency.
If A/D clock frequency and bandwidth requirements are lower,
the resistor values (and input impedance) can be made
correspondingly higher.
The V + and V - terminals supply the charge-balancing
AA AA
comparator only. Because the comparator is autobalanced
between conversions, it has good low frequency supply
rejection. It does not reject well at high frequencies, how-
ever: V - should be returned to a clean analog ground, and
AA
V
+ should be RC decoupled from the digital supply.
AA
There is approximately 50Ω of substrate impedance
between V and V +. This can be used, for example, as
The A/D system would generally be calibrated by tying V - to
lN
1
ground and applying a voltage to V + that is 0.5 LSB ( /
IN 2048
DD
AA
of full-scale range) above ground. The operational amplifier
offset should be adjusted for an output code dithering between
part of a low-pass RC filter to attenuate switching supply
noise. A 10pF capacitor from V + to ground would
AA
attenuate 30kHz noise by approximately 40dB. Note that
000 and 001 for unipolar use, or 100 and 101 for bipo-
16 16 16 16
lar use. The gain would then be adjusted by applying a voltage
that is 1.5 LSB below the positive full scale input, and adjusting
back-to-back diodes should be placed from V
to V + to
DD
AA
handle supply to capacitor turn-on or turn-off current
spikes.
the reference for an output dithering between 3FE and
16
3FF
16
.
Figure 16 shows V + supply rejection versus frequency.
AA
Note that R1 through R5 should be very well matched, as
they affect the common-mode rejection of the A/D system.
Also, if R2 and R3 are not matched, the offset adjust of the
operational amplifier may not have enough adjustment range
in bipolar systems.
Note that the frequency to be rejected scales with the clock:
the 100Hz rejection with a 100kHz clock would be roughly
equivalent to the 1kHz rejection with a 1MHz clock.
The supply current for the CA3310 is dependent on clock
frequency, supply voltage, and temperature. Figure 14
shows the typical current versus frequency and voltage,
while Figure 15 shows it versus temperature and voltage.
Note that if stopped in auto-balance, the supply current is
typically somewhat higher than if free-running. See
Specifications.
The common-mode input range of the system is set by the
supply voltage available to the operational amplifier. The
range that can be applied to the V - terminal can be
IN
calculated by:
R4
R5
------- + 1
V
- for the most negative,
R4
IN
R4
-------
------- + 1
R5
(V + -2.5V) - (
)V
+ for the most positive.
REF
IN
R5
6-18
CA3310, CA3310A
Single +5V Supply
end as it goes positive. Ten cycles later, the conversion will
be complete, and DRDY will go active.
If only a single +5V supply is available, an ICL7660 can be
used to provide approximately +8V and -4V to the opera-
tional amplifier. Figure 20 shows this approach. Note that the
converter and associated capacitors should be grounded to
the digital supply. The 1kΩ in series with each supply at the
operational amplifier isolates digital and analog grounds.
Operating and Handling Considerations
HANDLING
All inputs and outputs of Intersil CMOS devices have a
network for electrostatic protection during handling. Recom-
mended handling practices for CMOS devices are described
in lCAN-6526, “Guide to Better Handling and Operation of
CMOS Integrated Circuits”.
+5V
10Ω
+
IN914
+
8
D
OPERATING
2
+
+8V
-4V
Operating Voltage
+
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause
ICL7660S
4
5
D
V
- V to exceed the absolute maximum rating.
DD
SS
+
3
ALL CAPACITORS - 10µF, 10V
Input Signals
D
D
D = DIGITAL GROUND
To prevent damage to the input protection circuit, input
Digital Sample and Hold
signals should never be greater than V
than V
SS
+0.3V nor less
-0.3V. Input currents must not exceed 20mA even
DD
With a minimum of external logic, the CA3310 can be made
to wait at the verge of ending a sample. A start pulse will then,
after the internal aperture delay, capture the input and finish
the conversion cycle. Figure 21 illustrates this application.
when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused Input terminals must be connected to either V or
The CA3310 is connected as if to free run. The Data Ready
signal is shifted through a CD74HC175, and at the low-going
clock edge just before the sample would end, is used to hold
the clock low.
DD
V
, whichever is appropriate.
SS
Output Short Circuits
The same signal, active high, is available to indicate the
CA3310 is ready to convert. A low pulse to reset the
CD74HC175 will now release the clock, and the sample will
Shorting of outputs to V
devices by exceeding the maximum device dissipation.
or V
may damage CMOS
SS
DD
CA3310/A
+5V
V
V
DRST
STRT
+5V
DD
D
+
D
AA
D0 - D9
DATA TO SYSTEM
A
A
FULL SCALE
REFERENCE
V
+
-
OEL
OEM
OUTPUT ENABLES
REF
ANALOG
INPUT
V
DRDY
DATA READY
IN
V
V
REF
-
R
EXT
INPUT BUFFED
AS REQUIRED
AA
CLK
V
A
IN914
SS
READY TO
CONVERT
1/16
CD74HCO4E
D
D0
Q0
D1
Q1
D2
Q2
Q2
DD
V
+5V
CP
CD74HC175E
GND
KEEP CAPACITANCE AT R
AS LOW AS POSSIBLE
D = DIGITAL GROUND
A = ANALOG GROUND
/CLK NODE
EXT
D
D3
Q0
Q1
Q3
Q3
MR
START
CONVERT
D
NC
FIGURE 20. DIGITAL TRACK-AND-HOLD BLOCK DIAGRAM
6-19
CA3310, CA3310A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FAX: (321) 724-7240
6-20
相关型号：
CA3310M96
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO24
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