CDP1823D [INTERSIL]
128-Word x 8-Bit LSI Static RAM; 128字×8位LSI静态RAM
| 型号： | CDP1823D |
| 厂家： | 
Intersil |
| 描述： | 128-Word x 8-Bit LSI Static RAM |
| 文件： | 总7页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1823,
CDP1823C
128-Word x 8-Bit
LSI Static RAM
March 1997
Features
Description
• Fast Access Time
The CDP1823 and CDP1823C are 128-word by 8-bit CMOS
SOS static random-access memories. These memories are
compatible with general-purpose microprocessors. The two
memories are functionally identical. They differ in that the
CDP1823 has a recommended operating voltage range of
4V to 10.5V, and the CDP1823C has a recommended oper-
ating voltage range of 4V to 6.5V.
- V
- V
= 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns
= 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
DD
DD
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory
System Expansion
The CDP1823 memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip-
select inputs are provided to simplify memory-system expan-
sion. In order to enable the CDP1823, the chip-select inputs
CS2, CS3 and CS5 require a low input signal, and the chip-
select inputs CS1 and CS4 require a high input signal.
Ordering Information
PKG.
PACKAGE TEMP. RANGE NO.
5V
10V
o
o
CDP1823CE
CDP1823CD
CDP1823CDX
CDP1823E PDIP
CDP1823D SBDIP
-40 C to +85 C E24.6
o
o
-40 C to +85 C D24.6
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
-
Burn-In
D24.6
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or t
(access time) after address changes.
AA
Pinout
CDP1823, CDP1823C
(PDIP, SBDIP)
TOP VIEW
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CS1
1
2
3
4
5
6
7
8
9
24
V
DD
23 MA0
22 MA1
21 MA2
20 MA3
19 MA4
18 MA5
17 MA6
16 MWR
15 MRD
14 CS5
13 CS4
CS2 10
CS3 11
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1198.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-24
CDP1823, CDP1823C
OPERATIONAL MODES
FUNCTION
MRD
0
MWR
CS1
1
CS2
0
CS3
0
CS4
1
CS5
0
BUS TERMINAL STATE
Storage State of Addressed Word
Input High-Impedance
High Impedance
Read
Write
X
0
1
1
0
0
1
0
Stand-By (Active)
Not Selected
1
1
1
0
0
1
0
X
X
X
X
X
X
0
X
X
X
X
High Impedance
X
X
1
X
X
X
High Impedance
X
X
X
1
X
X
High Impedance
X
X
X
X
0
X
High Impedance
X
X
X
X
X
1
High Impedance
Logic 1 = High, Logic 0 = Low, X = Don’t Care
6-25
CDP1823, CDP1823C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1823C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Maximum Storage Temperature Range (T
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
60
60
N/A
17
SS
o
o
) . . .-65 C to +150 C
STG
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V Maximum Junction Temperature
DD
o
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (T )
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
o
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 300 C
A
o
o
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
LIMITS
CDP1823D
CDP1823CD
MAX
6.5
PARAMETER
Supply Voltage Range
Recommended Input Voltage Range
MIN
MAX
MIN
UNITS
4
10.5
4
V
V
V
V
V
V
DD
SS
DD
SS
o
o
Static Electrical Specifications At T = -40 C to +85 C, Except as Noted:
A
CONDITIONS
LIMITS
CDP1823
(NOTE 1)
CDP1823C
V
V
V
DD
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
(V)
MIN
TYP
MAX
500
1000
-
MIN
TYP
MAX
UNITS
µA
µA
mA
mA
mA
mA
V
Quiescent Device
Current
I
-
5
-
-
-
-
-
-
500
DD
-
10
5
-
-
-
Output Low (Sink)
Current
I
0.4
2
4
9
-2
-4.4
0
0
5
10
-
2
4
-
-
OL
0.5
10
5
4.5
-
-
-
Output High (Source)
Current
I
4.6
-1
-
-1
-2
-
-
-
OH
9.5
10
5
-2.2
-
-
Output Voltage
Low-Level
V
-
-
0.1
0.1
-
-
0
-
0.1
-
OL
-
10
5
-
-
V
Output Voltage
High-Level
V
-
4.9
4.9
5
-
-
V
OH
-
10
5
9.9
-
-
-
V
Input Low Voltage
Input High Voltage
Input Leakage Current
V
0.5, 4.5
0.5, 9.5
0.5, 9.5
0.5, 9.5
-
-
1.5
3
-
-
1.5
-
V
IL
IH
IN
-
10
5
-
-
-
V
V
-
3.5
7
-
-
-
3.5
-
-
V
-
10
5
-
-
-
-
-
-
-
-
-
-
-
-
-
V
I
Any
Input
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
±5
±10
8
-
±5
-
µA
µA
mA
mA
µA
µA
pF
pF
10
5
-
-
-
Operating Current
(Note 2)
I
-
-
4
8
-
4
-
8
DD1
OUT
-
0, 5
0, 10
-
10
5
-
16
±5
±10
7.5
15
-
Three-State Output
Leakage Current
I
-
-
± 5
-
10
-
-
-
-
Input Capacitance
Output Capacitance
NOTES:
C
-
5
10
5
10
7.5
15
IN
C
-
-
-
-
OUT
o
1. Typical values are for T = +25 C and nominal V
A
.
DD
2. Outputs open circuited; Cycle time = 1µs.
6-26
CDP1823, CDP1823C
o
Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, C = 100pF
A
DD
R
F
L
LIMITS
CDP1823
CDP1823C
(NOTE 2) (NOTE 1)
V
(NOTE 2) (NOTE 1)
DD
PARAMETER
SYMBOL
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Read Cycle (See Figure 1)
Access Time From Address
Change
t
5
10
5
-
-
275
150
150
100
150
100
50
450
250
250
150
250
150
75
-
-
275
450
ns
ns
ns
ns
ns
ns
ns
ns
AA
-
150
-
-
250
-
Access Time From Chip
Select
t
-
-
DOA
10
5
-
-
MRD to Output Active
Data Hold Time After Read
NOTES:
t
-
-
150
-
250
-
AM
10
5
-
-
t
25
15
25
-
50
-
75
-
DOH
10
25
40
o
1. Typical values are at T = 25 C and nominal voltage.
A
2. Time required by a limit device to allow for the indicated function.
+
t
AA
ADDRESS
MRD
t
AM
CS2, CS3, CS5
t
DOA
CS1, CS4
t
DOH
90%
10%
VALID DATA
DATA OUT
HIGH IMPEDANCE
NOTE:
1. MWR is high during read operation. Timing measurement reference is 0.5 V
.
DD
FIGURE 1. READ CYCLE TIMING DIAGRAM
6-27
CDP1823, CDP1823C
o
Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, C = 100pF
A
DD
R
F
L
LIMITS
CDP1823
(NOTE 2) (NOTE 1)
CDP1823C
(NOTE 2) (NOTE 1)
V
DD
PARAMETER
Write Cycle (See Figure 2)
Write Recovery
SYMBOL
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t
t
5
10
5
75
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR
WC
-
400
-
Write Cycle
400
225
200
100
125
75
10
5
Write Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time From MWR
NOTES:
t
200
-
WRW
10
5
t
125
-
AS
DS
DH
10
5
t
100
75
100
-
10
5
t
75
75
-
10
50
o
1. Typical values are at T = 25 C and nominal voltage.
A
2. Time required by a limit device to allow for the indicated function.
t
WC
t
AS
ADDRESS
CS1, CS4
t
WR
CS2, CS3, CS5
MWR
t
WRW
t
t
DH
DS
BUS 0-7
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
6-28
CDP1823, CDP1823C
o
Data Retention Specifications At T = -40 to +85 C, see Figure 3
A
LIMITS
TEST
CONDITIONS
CDP1823
CDP1823C
V
V
(NOTE 1)
(NOTE 1)
DR
DD
PARAMETER
(V)
(V)
MIN
-
TYP
MAX
MIN
TYP
MAX
UNITS
V
Minimum Data Retention Voltage,
Data Retention Quiescent Current,
V
-
-
1.5
2
-
1.5
2
DR
I
2
-
-
-
30
-
100
-
600
-
30
-
100
µA
ns
DD
Chip Deselect to Data Retention Time
5
600
300
600
300
1
-
-
-
-
-
-
-
-
-
-
t
-
10
5
-
-
ns
CDR
RC
Recovery to Normal Operation
Time
-
-
600
-
-
ns
t
-
10
5
-
-
ns
V
to V
Rise and Fall Time
t , t
R F
2
-
1
-
µs
DD
DR
NOTE:
o
Typical values are for T = 25 C and nominal V
.
DD
A
DATA RETENTION
MODE
V
DD
0.95 V
0.95 V
DD
DD
V
DR
t
t
t
t
CDR
F
R
RC
C
S1
V
V
IH
IH
V
IL
V
IL
FIGURE 3. LOW V
DATA RETENTION TIMING WAVEFORMS
DD
MA0
MA1
MA2
16 x 8 x 8
STORAGE
ARRAY
BUFFER
AND
DECODER
MA3
MA4
MA5
MA6
BUFFER
DECODER
MRD
MWR
CONTROL
CS1
CS2
CS3
CS4
BUS 0-7
CS5
FIGURE 4. FUNCTIONAL DIAGRAM
6-29
CDP1823, CDP1823C
CPU/ROM SYSTEM
ADDRESS
RAM INTERFACE
RAM SYSTEM
MA0 - MA7
MA0- MA7
MA0 - MA6
TPA
TPA
MRD
MRD
MWR
MRD
MWR
CPU
CDP1802
ROM
CDP1833
RAM
CDP1823
CE0
BUS0 - BUS7
CS
BUS0 - BUS7
BUS0 - BUS7
DATA
FIGURE 5. CDP1823 (128 x 8) MINIMUM SYSTEM (128 x 8)
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6-30
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