CDP1853 [INTERSIL]
N-Bit 1 of 8 Decoder; N位的8解码器1
| 型号： | CDP1853 |
| 厂家： | 
Intersil |
| 描述： | N-Bit 1 of 8 Decoder |
| 文件： | 总6页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1853,
CDP1853C
March 1997
N-Bit 1 of 8 Decoder
Features
Description
The CDP1853 and CDP1853C are 1 of 8 decoders designed for
use in general purpose microprocessor systems. These
devices, which are functionally identical, are specifically
designed for use as gated N-bit decoders and interface directly
with the 1800-series microprocessors without additional compo-
nents. The CDP1853 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1853C has a recommended
operating voltage range of 4V to 6.5V.
• Provides Direct Control of Up to 7 Input and 7 Output
Devices
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
PKG.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low tran-
sition) to the trailing edge of CLOCK B (high-to-low transition).
All outputs will be low when the device is not selected (CE = 0)
and during conditions of CLOCK A and CLOCK B as shown in
Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and
CLOCK B are connected to an 1800-series microprocessor out-
puts N0, N1, N2, TPA, and TPB respectively, when used to
decode I/O commands as shown in Figure 5. The CHIP
ENABLE (CE) input provides the capability for multiple levels of
decoding as shown in Figure 6.
PACKAGE TEMP. RANGE
5V
-40 C to +85 C CDP1853CE CDP1853E E16.3
CDP1853CEX E16.3
-40 C to +85 C CDP1853CD CDP1853D D16.3
CDP1853CDX D16.3
10V
NO.
o
o
PDIP
Burn-In
SBDIP
Burn-In
-
o
o
-
The CDP1853 can also be used as a general 1 of 8 decoder for
I/O and memory system applications as shown in Figure 4.
The CDP1853 and CDP1853C are supplied in hermetic 16-lead
dual-in-line ceramic (D suffix) and plastic (E suffix) packages.
TRUTH TABLE
Pinout
CDP1853 Functional Diagram
16 LEAD DIP
TOP VIEW
CE
1
CL A
CL B
EN
4
OUT 0
0
0
1
1
X
0
1
0
1
X
Qn-1†
2
5
6
N0
N1
N2
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
CLK A 1
N0 2
16 VDD
1
1
0
1
0
15 CLK B
14 N2
7
3
1 OF 8
DECODER
1
N1 3
12
11
10
9
OUT 0 4
OUT 1 5
OUT 2 6
OUT 3 7
13 CE
1
14
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
0
EN
13
CE
1
N2
0
N1
0
N0
EN
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
2
0
0
1
0
0
0
0
0
0
3
0
0
0
1
0
0
0
0
0
4
0
0
0
0
1
0
0
0
0
5
0
0
0
0
0
1
0
0
0
6
0
0
0
0
0
0
1
0
0
7
0
0
0
0
0
0
0
1
0
VSS
8
0
1
0
1
0
1
0
1
X
Qn
0
0
1
CLOCK
A
(TPA)
0
1
1
0
1
1
1
0
1
15
CLOCK
B
(TPB)
1
0
1
1
1
1
1
1
1
FIGURE 1.
X
X
0
1 = High level, 0 = Low level, X = Don’t care
† Qn-1 = Enable remains in previous state.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1189.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-35
CDP1853, CDP1853C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(All voltage values referenced to V terminal)
CDP1853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V +0.5V
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
SS
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
85
85
N/A
22
Operating Temperature Range (T )
A
o
o
DD
Ceramic Packages (D Suffix Types) . . . . . . . . . .-55 C to +125 C
Plastic Packages (E Suffix Types) . . . . . . . . . . . . .-40 C to +85 C
o
o
o
o
Storage Temperature Range (T
) . . . . . . . . . . . .-65 C to +150 C
STG
o
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265 C
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Static Electrical Specifications At T = -40 to +85 C, Unless Otherwise Specified
A
CONDITIONS
LIMITS
CDP1853
CDP1853C
V
V
V
DD
(NOTE1)
(NOTE1)
O
IN
PARAMETER
Quiescent Device
(V)
(V)
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
µA
µA
mA
mA
mA
mA
V
I
-
-
5
-
1
10
3.2
5.2
-2.3
-5.2
0
10
100
-
-
5
50
L
Current
-
-
10
5
-
-
-
-
Output Low Drive (Sink)
Current
I
0.4
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
1.6
1.6
3.2
-
OL
0.5
10
5
2.6
-
-
-
-
Output High Drive
(Source) Current
I
4.6
-1.15
-
-1.15
-2.3
-
OH
9.5
10
5
-2.6
-
-
-
0
-
-
0.1
-
Output Voltage Low Level
(Note 2)
V
-
-
0.1
0.1
-
-
OL
-
-
10
5
-
0
-
V
Output Voltage High Level
Input Low Voltage
V
4.9
5
4.9
5
-
-
V
OH
-
10
5
9.9
10
-
-
-
-
V
V
0.5, 4.5
1, 9
0.5, 4.5
1, 9
-
1.5
3
-
-
1.5
-
V
IL
IH
IN
-
10
5
-
3.5
7
-
-
-
-
V
Input High Voltage
V
-
-
-
3.5
-
-
V
-
10
5
-
-
-
-
-
-
-
-
-
-
-
V
Input Leakage Current
I
Any
Input
0, 5
0, 10
0, 5
0, 10
-
-
±1
±1
100
300
7.5
15
-
±1
-
µA
µA
µA
µA
pF
pF
10
5
-
-
-
Operating Current
(Note 3)
I
0, 5
-
50
150
5
50
-
100
-
DD1
0, 10
10
-
-
Input Capacitance
Output Capacitance
NOTES:
C
-
-
-
5
10
7.5
15
IN
C
-
-
-
10
OUT
o
1. Typical values are for T = +25 C and nominal voltage.
A
2. I = I = 1µA
OL
OH
3. Operating current measured in a CDP1802 system at 2MHz with outputs floating.
Spec Number
4-36
CDP1853, CDP1853C
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
LIMITS
CDP1853
CDP1853C
PARAMETER
Supply Voltage Range
Recommended Input Voltage Range
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
V
V
V
V
DD
SS
DD
SS
o
Dynamic Electrical Specifications At T = -40 to +85 C, V = ±5%, V = 0.7V , V = 0.3V , t , t = 20ns, C = 100pF,
A
DD
IH
DD IL
DD
R
F
L
Unless Otherwise Specified
LIMITS
CDP1853
TYP
CDP1853C
TYP
PARAMETER
V
(V)
MIN
MAX
MIN
MAX
UNITS
DD
Propagation Delay Time:
CE to Output
t
t
5
-
-
-
-
-
-
-
-
175
90
275
150
350
200
300
150
275
150
-
-
-
-
-
-
-
-
175
275
ns
ns
ns
ns
ns
ns
ns
ns
EOH,
EOL
10
5
-
225
-
-
350
-
N to Output
t
225
120
200
100
175
90
NOH,
t
NOL
10
5
Clock A to Output
Clock B to Output
t
200
-
300
-
AO
BO
10
5
t
175
-
275
-
10
Minimum Pulse Widths:
Clock A
ns
t
t
5
10
5
-
-
-
-
50
25
50
25
75
50
75
50
-
-
-
-
50
-
75
-
ns
ns
ns
ns
CACA
Clock B
NOTES:
50
-
75
-
CBCB
10
1. Maximum limits of minimum characteristics are the values above which all devices function.
o
2. Typical values are for T = +25 C and nominal voltages.
A
4-37
CDP1853, CDP1853C
Timing Diagrams
tEO
tEO
tNO
tNO
CE
N
OUTPUT
OUTPUT
FIGURE 2A. CE TO OUTPUT (0-7) DELAY TIME
FIGURE 2B. N LINES TO OUTPUT (0-7) DELAY TIME
tCBCB
tCACA
tAO
tBO
CLOCK A
OUTPUT
CLOCK B
OUTPUT
FIGURE 2C. CLOCK A TO OUTPUT (0-7) DELAY TIME
FIGURE 2D. CLOCK B TO OUTPUT (0-7) DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
TPA
TPB
CE
A
N0
B
N1
C
CHIP ENABLE
VDD
N2
CE
EN
(NOTE 1)
CLOCK B
CLOCK A
OUTPUT
NOTE 1. OUTPUT ENABLED WHEN EN = HIGH
INTERNAL SIGNAL SHOWN FOR
REFERENCE ONLY (SEE FIGURE 1)
FIGURE 3. TIMING DIAGRAM
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
4-38
CDP1853, CDP1853C
CDP1800 SERIES
N0 N1 N2 TPB MRD
TPA
TPB
VDD
CLOCK A CLOCK B
CDP1853
CE N0 N1 N2
0
1
2-6
7
READ VIA
6F INSTRUCTION
CS1
CS2
CS1
CS2
CDP1852
OUTPUT
PORT 7
CDP1852
LOAD VIA 67
INPUT
DATA
DATA
INSTRUCTION
PORT 7
SR
DATA AVAILABLE
STROBE
MODE
MODE
TPB
VDD
CLOCK
5 CDP1852 INPUT AND OUTPUT PORTS
READ VIA
69 INSTRUCTION
CS2
CS1
CS1
CS2
CDP1852
CDP1852
LOAD VIA 61
OUTPUT
PORT 1
INPUT
DATA
INSTRUCTION
PORT 1
SR
AVAILABLE
STROBE
MODE
MODE
TPB
VDD
CLOCK
7 INPUT PORTS
7 OUTPUT PORTS
FIGURE 5. N-BIT DECODER IN A ONE-LEVEL I/O SYSTEM
CDP1800 SERIES
TPA TPB
NOTE: SYSTEM SHOWN WILL SELECT
UP TO 56 INPUT AND 48 OUTPUT
PORTS. WITH ADDITIONAL DECODING
THE TOTAL NUMBER OF INPUT
AND OUTPUT PORTS CAN BE
FURTHER EXPANDED.
NO, N1, N2
MRD BUS
DATA BUS
TPA
CL CSI
CS2
CDP1853
DECODED
“61” INSTRUCTION
I
INTERCONNECTED
AS IN FIGURE 4
CDP1852
CLOCK A
CLOCK B
I/O
7 INPUT
6 OUTPUT
CE
CDP1853
“62-6F”
NO, N1, N2
PORTS
INST
CLOCK A
CLOCK B
I/O
7 INPUT
6 OUTPUT
CE
CDP1853
“62-6F”
NO, N1, N2
PORTS
INST
SECTIONS 3-7
CLOCK A
CLOCK B
I/O
7 INPUT
6 OUTPUT
CE
CDP1853
“62-6F”
NO, N1, N2
PORTS
INST
FIGURE 6. TWO-LEVEL I/O USING CDP1853 AND CDP1852
4-39
CDP1853, CDP1853C
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-40
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