CDP1855_1_技术文档

CDP1855,

TM

CDP1855C

8-Bit Programmable

Multiply/Divide Unit

March 1997

Features

Description

• Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply

^{or 64}÷ 32-Bit Divide

The CDP1855 and CDP1855C are CMOS 8-bit multi-

ply/divide units which can be used to greatly increase the

capabilities of 8-bit microprocessors. They perform multiply

and divide operations on unsigned, binary operators. In

general, microprocessors do not contain multiply or divide

instructions and even efficiently coded multiply or divide

subroutines require considerable memory and execution

time. These multiply/divide units directly interface to the

CDP1800-series microprocessors via the N-lines and can

easily be configured to fit in either the memory or I/O space

of other 8-bit microprocessors.

^{• 8-Bit by 8-Bit Multiply or 16}÷ 8-Bit Divide in 5.6µs at

5V or 2.8µs at 10V

• Direct Interface to CDP1800-Series Microprocessors

• Easy Interface to Other 8-Bit Microprocessors

• Significantly Increases Throughput of Microprocessor

Used for Arithmetic Calculations

Ordering Information

The multiple/divide unit is based on a method of multiplying

by add and shift right operations and dividing by subtract and

shift left operations. The device is structured to permit cas-

cading identical units to handle operands up to 32 bits.

PKG.

NO.

PACKAGE TEMP. RANGE

5V

-40 C to +85 C CDP1855CE CDP1855E E28.6

CDP1855CEX E28.6

-40 C to +85 C CDP1855CD CDP1855D D28.6

CDP1855CDX D28.6

10V

o

PDIP

Burn-In

SBDIP

Burn-In

The CDP1855 and CDP1855C are functionally identical.

They differ in that the CDP1855 has a recommended

operating voltage range of 4V to 10.5V, and the CDP1855C,

a recommended operating voltage range of 4V to 6.5V.

-

o

-

The CDP1855 and CDP1855C types are supplied in a 28

lead hermetic dual-in-line ceramic package (D suffix) and in

a 28 lead dual-in-line plastic package (E suffix). The

CDP1855C is also available in chip form (H suffix).

Pinout

Circuit Configuration

28 LEAD DIP

TOP VIEW

+V

CLEAR

XTAL

CLEAR

CE

CLEAR

CTL

1

2

3

4

5

6

7

8

9

28 V

DD

CLK

RA0

RA1

RA2

STB

CE

C1

27 CN0

26 CN1

25 CI

N0

N1

CN0

CN1

C.O./O.F.

N2

Y

Z

24

23

Y

L

R

TPB

MRD

Z

L

R

RD/WE

CDP1855

SHIFT

CLK

22 BUS 7

21 BUS 6

CDP1802

Y

L

STB

20

BUS 5

Z

R

RD/WE 10

RA2 11

19 BUS 4

18 BUS 3

17 BUS 2

16 BUS 1

15 BUS 0

CTL

C0

EF

RA1 12

RA0 13

Y

R

V

14

Z

L

SS

BUS

FIGURE 1. MDU ADDRESSED AS I/O DEVICE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1053.2

^{1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas}1^Inc.

CDP1855, CDP1855C

Absolute Maximum Ratings

Thermal Information

o

DC Supply Voltage Range, (V

)

Thermal Resistance (Typical)

θ

( C/W)

θ

( C/W)

DD

JA

JC

(All voltage values referenced to V terminal)

CDP1855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +11V

CDP1855C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V

DD

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

SS

PDIP Package . . . . . . . . . . . . . . . . . . .

SBDIP Package. . . . . . . . . . . . . . . . . .

Device Dissipation Per Output Transistor

55

50

N/A

12

+0.5V

For T = Full Package-Temperature Range

A

(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

o

Operating Temperature Range (T ) . . . . . . . . . . . . .-40 C to +85 C

A

o

Storage Temperature Range (T

) . . . . . . . . . . . .-65 C to +150 C

STg

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

o

Static Electrical Specifications At T = -40 to +85 C, V ±10%, Unless Otherwise Specified

A

DD

CONDITIONS

LIMITS

CDP1855

CDP1855C

V

DD

(NOTE1)

O

IN

PARAMETER

Quiescent Device

(V)

0, 5

0, 10

0, 5

0, 10

0, 5

0, 10

0, 5

0, 10

0, 5

0, 10

-

(V)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

µA

mA

V

I

-

5

-

0.01

50

200

-

0.02

200

DD

Current

-

10

5

-

1

3.2

5.2

-2.3

-5.2

0

-

Output Low Drive (Sink)

Current

I

0.4

1.6

3.2

-

OL

0.5

10

5

2.6

-

Output High Drive

(Source) Current

I

4.6

-1.15

-

-1.15

-2.3

OH

9.5

10

5

-2.6

-

0

-

Output Voltage Low Level

(Note 2)

V

-

0.1

-

0.1

-

OL

-

10

5

-

0

-

V

Output Voltage High Level

(Note 2)

V

-

4.9

5

4.9

5

-

V

OH

-

10

5

9.9

10

-

V

Input Low Voltage

Input High Voltage

Input Leakage Current

V

0.5, 4.5

-

1.5

3

-

1.5

-

V

IL

IH

IN

0.5, 9.5

-

10

5

-

V

0.5, 4.5

-

3.5

7

-

3.5

-

V

0.5, 9.5

-

10

5

-

V

I

-

0, 5

0, 10

0, 5

0, 10

0, 5

0, 10

-

±1

±10

-

±1

-

µA

mA

pF

-

10

5

-

Three-State Output

Leakage Current

I

0, 5

-

±1

-

OUT

0, 10

10

5

-

Operating Current

(Note 3)

I

-

1.5

6

1.5

-

3

DD1

10

-

12

7.5

15

-

Input Capacitance

Output Capacitance

NOTES:

C

-

5

10

7.5

15

IN

C

-

10

OUT

o

1. Typical values are for T = +25 C and nominal V

.

DD

A

2. I = I

OL

= 1µA

OH

3. Operating current is measured at 3.2MHz with open outputs.

2

CDP1855, CDP1855C

Recommended Operating Conditions At T = Full package temperature range. For maximum reliability, operating conditions

A

should be selected so that operation is always within the following ranges:

LIMITS

CDP1855

MAX

10.5

CDP1855C

V

(V)

DD

PARAMETER

DC Operating Voltage Range

MIN

MAX

UNITS

V

-

4

6.5

Input Voltage Range

-

V

SS

DD

SS

DD

Maximum Clock Input Frequency

5

3.2

6.4

-

3.2

-

MHz

µs

10

5

-

Minimum 8 x 8 Multiply (16 ÷ 8 Divide) Time

5.6

2.8

5.6

-

10

-

µs

3

CDP1855, CDP1855C

CE

1

RA2 RA1 RA0

11 12 13

REGISTER

SELECT LOGIC

SELECT CONTROL

SELECT Z

SELECT STATUS

SELECT Y

SELECT X

X REGISTER

X SEQUENCE

COUNTER

LOAD

RESET

OUT

8

CLOCK

8

C.I.

25

ADD/

SHIFT

GENERATOR

CTL.

3

4

SUBTRACT

CN1

26

8

CHIP

NO.

C.O./O.F.

STATUS

REG

CN0

27

C.O.

8

Y SEQUENCE

COUNTER

Y

L

5

Y REGISTER

SHIFT

Y

R

24

RESET

OUT

LOAD RESET

8

Z SEQUENCE

COUNTER

Z

L

6

Z REGISTER

SHIFT

Z

R

23

LOAD RESET

RESET

OUT

LOAD

BUS BUS BUS BUS BUS BUS BUS BUS

7

6

5

4

3

2

1

0

22 21 20 19 18 17 16

15

9

STB

2

7

10

14

28

V

SS

CLEAR SHIFT

RD/WE

DD

FIGURE 2. BLOCK DIAGRAM OF CDP1855 AND CDP1855C

Functional Description

The CDP1855 is a multiply-divide unit (MDU) designed to be are loaded with the operands prior to an operation and

compatible with CDP1800 series microprocessor systems. It contain the results at the completion. In addition, the control

can, in fact, be interfaced to most 8-bit microprocessors (see register must be loaded to initiate a multiply or divide. There

Figure 5). The CDP1855 performs binary multiply or divide is also a status register which contains an overflow flag as

operations as directed by the microprocessor. It can do a shown in the “CONTROL REGISTER BIT ASSIGNMENT

16N-bit by 8N-bit divide yielding a 8N-bit result plus and 8N- TABLE”. The register address lines (RA0-RA1) are used to

bit remainder. The multiply is an 8N-bit by 8N-bit operation select the appropriate register for loading or reading. The

with a 16N-bit result. The “N” represent the number of RD/WE and STB lines are used in conjunction with the RA

cascaded CDP1855's and can be 1, 2, 3 or 4. All operations lines to determine the exact MDU response (See

require 8N + 1 shift pulses (See “DELAY NEEDED WITH “CONTROL TRUTH TABLE”).

AND WITHOUT PRESCALER”).

When multiple MDU's are cascaded, the loading of each reg-

The CDP1855 contains three registers, X, Y, and Z, which ister is done sequentially. For example, the first selection of

4

CDP1855, CDP1855C

register X for loading loads the most significant CDP1855, 2. Divide Operation

the second loads the next significant, and so on. Registers

For the divide operation, the divisor is loaded in the X

are also read out sequentially. This is accomplished by inter-

nal counters on each MDU which are decremented by STB

during each register selection. When the counter matches

the chip number (CN1, CN0 lines), the device is selected.

These counters must be cleared with a clear on pin 2 or with

bit 6 in the control word (See “CONTROL REGISTER BIT

ASSIGNMENT TABLE”) in order to start each sequence of

accesses with the most significant device.

register. The dividend is loaded in the Y and Z registers with

the more significant half in the Y register and the less signifi-

cant half in the Z register. These registers may be loaded in

any order, and after loading is completed, a control word is

loaded to specify a divide operation and the number of

MDU's and also to reset the sequence counters and Y or Z

register and select the clock option if desired. Clearing the

sequence counters with bit 6 will set the MDU's up for read-

The CDP1855 has a built in clock prescaler which can be ing the results.

selected via bit 7 in the control register. The prescaler may

The X register will be unaltered by the operation. The

be necessary in cascaded systems operating at high

frequencies or in systems where a suitable clock frequency

is not readily available. Without the prescaler select, the shift

frequency is equal to the clock input frequency. With the

prescaler selected, the rate depends on the number of

MDU's as defined by bits 4 and 5 of the control word (See

“CONTROL REGISTER BIT ASSIGNMENT TABLE”).

quotient will be in the Z register while the remainder will be in

the Y register. An overflow will be indicated by the C.O./O.F.

of the most significant MDU and can also be determined by

reading the status byte.

While the CDP1855 is specified to perform 16 by 8-bit

divides, if the quotient of a divide operation exceeds the size

of the Z register(s) (8N-bits - where N is the number of

cascaded CDP1855's) the overflow bit in the Status Register

will be set. Neither the quotient in Z nor the remainder in Y

will represent a valid answer. This will always be the result of

a division performed when the divisor (X) is equal to or less

than the most significant 8N-bits of the dividend (Y).

1. For one MDU, the clock frequency is divided by 2.

2. For two MDU's the clock frequency is divided by 4.

3. For 3 or 4 MDU's, the clock frequency is divided by 8.

Operation

The MDU can still be used for such computations if the

divide is done in two steps. The dividend is split into two

parts-the more significant 8N-bits and the less significant 8N-

bits-and a divide done on each part. Each step yields an 8N-

bit result for a total quotient of 16N-bits.

1. Initialization and Controls

The CDP1855 must be cleared by a low on pin 2 during

power-on which prevents bus contention problems at the Y ,

L

Y

and Z , Z terminals and also resets the sequence

R

L R

counters and the shift pulse generator.

The first step consists of dividing the more significant 8N-

bits by the divisor. This is done by clearing the Y register(s),

loading the Z register(s) with the more significant 8N-bits of

the dividend, and loading the X register(s) with the divisor. A

division is performed and the resultant value in Z represents

the more significant 8N-bits of the final quotient. The Z regis-

ter(s) value must be unloaded and saved by the processor.

Prior to loading any other registers the control register must

be loaded to specify the number of MDU's being used (See

“CONTROL REGISTER BIT ASSIGNMENT TABLE”).

Once the number of devices has been specified and the

sequence counters cleared with a clear pulse or bit 6 of the

control word, the X, Y, and Z registers can be loaded as

defined in the “CONTROL TRUTH TABLE”. All bytes of the X

register can be loaded, then all bytes of the Y, and then all

bytes of the Z, or they can be loaded randomly. Successive

loads to a given register will always proceed sequentially

from the most significant byte to the least significant byte, as

previously described. Resetting the sequence counters

select the most significant MDU. In a four MDU system,

loading all MDU's results in the sequence counter pointing to

the first MDU again. In all other configurations (1, 2, or 3

MDU's), the sequence counter must be reset prior to each

series of register reads or writes.

5

CDP1855, CDP1855C

A second division is performed using the remainder from the

Z

of the least significant CDP1855 MDU. This signal is

R

first division (in Y) as the more significant 8N-bits of the divi- used to indicate whether the registers are to be operated on

dend and the less significant half of the original dividend or only shifted.

loaded into the Z register. The divisor in X remains unaltered

C.O./O.F. - Carry Out/Over Flow (Output):

and is, by definition, larger than the remainder from the first

division which is in Y. The resulting value in Z becomes the

less significant 8N-bits of the final quotient and the value in Y

is, as usual, the remainder.

This is a three-state output pin. It is the CDP1855 Carry Out

signal and is connected to Cl (CARRY-IN) of the next more

significant CDP1855 MDU, except for on the most significant

MDU. On that MDU it is an overflow indicator and is enabled

when chip enables is true. A low on this pin indicates that an

overflow has occurred. The overflow signal is latched each

time the control register is loaded, but is only meaningful

after a divide command.

Extending this technique to more steps allows division of any

size number by an 8N-bit divisor.

Note that division by zero is never permitted and must be

tested for and handled in software.

The following example illustrates the use of this algorithm.

Y , Y - Y-Left, Y-Right:

L

R

Example:

These are three-state bi-directional pins for data transfer

between the Y registers of cascaded CDP1855 MDU's. The

Assume three MDU's capable of a by 24-bit division. The

problem is to divide 00F273, 491C06H by 0003B4H.

Y

pin is an output and Y is an input during a multiply and

R

L

the reverse is true at all other times. The Y pin must be

L

Step 1: 000000

,

00F273

Z(MS)

491C06

Z(LS)

/

0003B4

=

000041 R=0001BF

Z1 Y1

78C936 R=00000E

Z2 Y2

connected to the Y pin of the next more significant MDU.

R

Y

Step 2: 0001BF

Y1

X

0003B4

X

An exception is that the Y pin of the most significant

L

/

=

CDP1855 MDU must be connected to the Z pin of the least

R

significant MDU and to the CTL pins of all MDU's. Also the

Result: 000041

Z1

78C936

Z2

R=00000E

Y2

Y

pin of the least significant MDU is tied to the Z pin of the

R

L

most significant MDU.

The Z register can simply be reset using bit 2 of the control

word and another divide can be done in order to further

divide the remainder.

Z , Z - Z-Left, Z-Right:

L

R

These are three-state bi-directional pins for data transfers

between the “Z” registers of cascaded MDU's. The Z pin is

R

3. Multiply Operation

an output and Z is an input during a multiply and the

L

reverse is true at all other times. The Z pin must be tied to

L

For a multiply operation the two numbers to be multiplied are

loaded in the X and Z registers. The result is in the Y and Z

register with Y being the more significant half and Z the less

significant half. The X register will be unchanged after the

operation is completed.

the Y pin of the next more significant MDU. An exception is

R

that the Z in of the most significant MDU must be con-

L

nected to the Y pin of the least significant MDU. Also, the

R

Z

pin of the least significant MDU is tied to the Y of the

R

L

most significant MDU.

The original contents of the Y register are added to the

product of X and Z. Bit 3 of the control word will reset

register Y to 0 if desired.

Shift - Shift Clock:

This is a three-state bi-directional pin. It is an output on the

most significant MDU. And an input on all other MDU's. It

provides the MDU system timing pulses. All SHIFT pins must

be connected together for cascaded operation. A maximum

of the 8N +1 shifts are required for an operation where "N"

equals the number of MDU devices that are cascaded.

Functional Description of

CDP1855 Terminals

CE - Chip Enable (Input):

A high on this pin enables the CDP1855 MDU to respond to

the select lines. All cascaded MDU's must be enabled

together. CE also controls the three-state C.O./O.F., output

of the most significant MDU.

CLK - Clock (Input):

This pin should be grounded on all but the most significant

MDU. There is an optional reduction of clock frequency

available on this pin if so desired, controlled by bit 7 of the

control byte.

Clear (Input):

The CDP1855 MDU(s) must be cleared upon power-on with

a low-on this pin. The clear signal resets the sequence

counters, the shift pulse generator, and bits 0 and 1 of the

control register.

STB - Strobe (Input):

When RD/WE is low, data is latched from bus lines on the

falling edge of this signal. It may be asynchronous to the

clock. Strobe also increments the selected register's

sequence counter during reads and writes. TPB would be

used in CDP1800 systems.

CTL - Control (Input):

This is an input pin. All CTL pins must be wired together and

to the Y of the most significant CDP1855 MDU and to the

L

6

CDP1855, CDP1855C

RD/WE - Read/Write Enable (Input):

Y - Y-Right:

R

This signal defines whether the selected register is to be See Pin 5.

read from or written to. In 1800 systems use MRD if MDU's

Cl- Carry In (Input):

are addressed as I/O devices, MWR is used if MDU's are

addressed as memory devices.

This is an input for the carry from the next less significant

MDU. On the least significant MDU it must be high (V ) on

DD

all others it must be connected to the CO pin of the next less

RA2, RA1, RA0 - Register Address (Input):

These input signals define which register is to be read from significant MDU.

or written to. It can be seen in the “CONTROL TRUTH

CN1, CN0 - Chip Number (Input):

TABLE” that RA2 can be used as a chip enable. It is identical

to the CE pin, except only CE controls the three-state

C.O./O.F. on the most significant MDU. In 1800 systems use

N lines if MDU's are used as I/O devices, use address lines

or function of address lines if MDU's are used as memory

devices.

These two input pins are wired high or low to indicate the

MDU position in the cascaded chain. Both are high for the

most significant MDU regardless of how many CDP1855

MDU's are used. Then CN1 = high and CN0 = low for the

next MDU and so forth.

Bus 0 - Bus 7 - Bus Lines:

V

- Ground:

SS

Three-state bi-directional bus for direct interface with

CDP1800 series and other 8-bit microprocessors.

Power supply line.

V

- V+:

DD

Z

- Z-Right:

R

Power supply line.

See Pin 6.

CONTROL TRUTH TABLE

INPUTS (NOTE 1)

RA2

(N2)

RA1

(N1)

RA0

(N0)

RD/WE

(MRD)

STB

(TPB)

CE

RESPONSE

No Action (Bus Floats)

0

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

1

0

X

1

X

No Action (Bus Floats)

X to Bus

1

Increment Sequence

Counter When STB

and RD = 1

1

Z to Bus

1

Y to Bus

1

Status to Bus

1

Load X from Bus

Load Z from Bus

Load Y from Bus

Load Control Register

No Action (Bus Floats)

Increment Sequence

Counter

1

0

NOTE:

1. ( ) = 1800 System Signals. 1 = High Level, 0 = Low Level, X = High or Low Level.

7

CDP1855, CDP1855C

CONTROL REGISTER BIT ASSIGNMENT TABLE

BUS 7

BUS 6

BUS 5

BUS 4

BUS 3

BUS 2

BUS 1

BUS 0

B1

0

B0

0

OPERATION SELECT

No Operation

Multiply

REGISTER

RESET

0

1

0

Divide

1

Illegal State

B2 = 1, RESET Z REGISTER

B3 = 1, RESET Y REGISTER

B5

1

B4

1

NO. OF MDU’s

One MDU

1

0

Two MDU’s

Three MDU’s

Four MDU’s

0

1

0

NO. OF MDU’s

SHIFT RATE

Clock ÷ 2

Clock ÷ 4

Clock ÷ 8

1

2

3

4

B6 = 1, RESET SEQUENCE COUNTER

B7 = 1, SELECT SHIFT RATE OPTIONS:

B7 = 0, SHIFT = CLOCK FREQUENCY RATE

STATUS REGISTER

STATUS BYTE

BIT

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OUTPUT

O.F.

NOTES:

1. O.F. = 1 if overflow (only valid after a divide has been done)

2. Bits 1 - 7 are read as 0 always.

DELAY NEEDED WITH AND WITHOUT PRESCALER

8N + 1 Shifts/Operation at 1 Clock Cycle/Shift

N = Number of MDU’s, S = Shift Rate

WITHOUT PRESCALER

WITH PRESCALER

(NOTE 1)

MACHINECYCLES

NEEDED

(NOTE 1)

MACHINE CYCLES

NEEDED

SHIFTS = 8N +1

NEEDED

SHIFTS = S (8N +1)

NEEDED

NO. OF MDU’s

SHIFT RATE

1

2

3

4

9

2 (1 NOP)

3 (1 NOP)

4 (2 NOPs)

18

68

3 (1 NOP)

9 (3 NOPs)

25 (9 NOPs)

33 (11 NOPs)

2

4

8

17

25

33

200

264

NOTE:

1. NOP instruction is shown for machine cycles needed (3/NOP). Other instructions may be used.

8

CDP1855, CDP1855C

CDP1855 Interfacing Schemes

V

CC

14

28 27 26 25

V

CN0 CN1 CI

SS

DD

24

6

Y

R

Z

L

3

CTL

5

CDP1855

MDU

Y

L

23

Z

R

22

21

20

19

18

17

16

15

BUS 7

BUS 6

BUS 5

BUS 4

BUS 3

+V

DD

CLEAR

CLOCK

DATA BUS

XTAL

MA0

MA1

RA0

RA1

CI

DATA

BUS

CN0

2

8

CLEAR

CLK

CN1

HIGH

ADDRESS

LATCH

BUS 2

BUS 1

BUS 0

RA2

MAX

10

9

RD/WE

STB

CDP1802

CDP1855

Y

L

TPA

RA2 RA1 RA0 CE

MWR

RE/WE

Z

R

11 12 13

1

CE

CTL

A8

MRD

TPB

A9

IO/M

WR

STB

CO

Y

R

EF

Z

L

BUS

RD

1/4 CD4011

CLK (OUT)

RESET OUT

1/4 CD4011

FIGURE 3. REQUIRED CONNECTION FOR MEMORY MAPPED

ADDRESSING OF THE MDU

FIGURE 4. INTERFACING THE CDP1855 TO AN 8085 MICRO-

PROCESSOR AS AN I/O DEVICE

Programming Example for Multiplication

For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C by

16

723C09

:

16

MEMORY

LOCATION

OP

CODE

LINE

NO.

ASSEMBLY LANGUAGE

0000

0002

0003

0005

0006

0008

000A

000C

000E

0010

F830;

0001

0002

0003

0004

0005

0006

0007

0008

0009

0010

0011

0012

0013

0014

0015

0016

LDI 030H

PLO R2

A2;

. . LOAD 30 INTO R2.0

F800;

LDI 00H

B2;

PHI R2

. . LOAD 00 INTO R2.1 (R2=0030)

. . LOAD CONTROL REGISTERS

. . SPECIFYING THREE MDU’s

. . RESET THE Y REGISTER AND

. . SEQUENCE COUNTER

. . LOAD MSB OF X REGISTER

. . WITH 20

6758;

OUT 7; DC 058H

;

6420;

OUT 4; DC 020H

OUT 4; DC 01FH

OUT 4; DC 07CH

OUT 5; DC 072H

;

641F;

. . LOAD NEXT MSB OF X REG

. . WITH 1F

;

647C;

. . LOAD LSB OF X REGISTER

. . WITH 7C

;

6572;

;

. . LOAD MSB OF Z REGISTER

. . WITH 72

9

CDP1855, CDP1855C

Programming Example for Multiplication

For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C by

16

723C09 : (Continued)

16

MEMORY

LOCATION

OP

CODE

LINE

NO.

ASSEMBLY LANGUAGE

. . LOAD NEXT MSB OF Z REG

. . WITH 3C

0010

0012

0014

0016

653C;

0017

0018

0019

0020

0021

0022

0023

0024

0025

OUT 5; DC 030H

OUT 5; DC 09H

OUT 7; DC 059H

;

6509;

. . LOAD LSB OF Z REGISTER

. . WITH 09

;

6759;

. . LOAD CONTROL REGISTERS

. . RESETTING Y REGISTERS

. . AND SEQUENCE COUNTERS

. . AND STARTING MULTIPLY

. . OPERATION

;

DELAY FOR MULTIPLY TO FINISH

0016

0017

0019

001B

001D

001F

0021

0022

0024

0000

E2;

0026

0027

SEX R2

6E60;

INP 6; IRX

. . MSB OF RESULTS IS STORED

. . AT LOCATION 0030

;

0028

6E60;

0029

INP 6; IRX

INP 5; IRX

INP 5

6E60;

0030

6D60;

0031

6D60;

0032

6D;

0033

. . COMPLETE LOADING RESULT

. . INTO MEMORY LOCATIONS

. . 0030 TO 0035

;

0034

;

0035

;

0036

. . RESULTS = 0E558DBA2B5C

3022;

;

0037 STOP

0038

BR STOP

END

BEFORE MULTIPLY

The result of 201F7C x 723C09 is 0E558DBA2B5C =

16 16

15760612797276 . It will be stored in memory as follows:

10

MDU1

20

MDU2

1F

MDU3

7C

LOC

0030

31

BYTE

0E

REGISTER X

REGISTER Y

REGISTER Z

00

72

3C

09

55

AFTER MULTIPLY

32

8D

MDU1

20

MDU2

1F

MDU3

7C

33

BA

2B

REGISTER X

REGISTER Y

REGISTER Z

34

0E

55

8D

35

5C

BA

2B

5C

10

CDP1855, CDP1855C

Programming Example for Division

MEMORY

LOCATION

OP

CODE

LINE

NO.

ASSEMBLY LANGUAGE

0000

0004

0008

000C

000F

0011

0014

0016

0019

001C

001F

0021

0024

0027

0028

0000

;

0001

0002

0003

0004

0005

0006

0007

0008

0009

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

0030

0031

0032

0033

0034

0035

0036

0037

0038

. . Program example for a 16-bit by 8-bit divide using 1 CDP1855 MDU

. . Gives a 16-bit answer with 8-bit remainder

;

68C22000;

RLDI R2, 2000H

RLDI R3, 3000H

RLDI R4, 4000H

. . Answer is stored at 2000 hex

. . Register 2 points to it

;

68C33000;

. . Dividend is stored at 3000 hex

. . Register 3 points to it

;

68C44000;

. . Divisor is stored at 4000 hex

. . Register 4 points to it

;

E067F0;

SEX R4; OUT 7; DC OF0H

. . Write to the control register to use

. . clock/2; 1MDU; reset sequence

. . counter; and no operation

;

E464;

SEX R4; OUT 4

. . Load the divisor into the X register

;

E06600;

SEX R0; OUT 6; DC 0

SEX R3; OUT 5

. . Load 0 into the Y register

E365;

. . Load the most significant 8 bits of

. . the dividend into the Z register

;

E067F2;

SEX R0; OUT 7; DC 0F2H

SEX R2; INP 5; IRX

. . Do the first divide, also resets the

. . sequence counter

;

E26D60;

. . Read and store the most significant

. . 8 bits of the answer at 2000 hex

;

E067F0;

SEX R0; OUT 7; DC 0F0H

SEX R3; OUT 5

. . Reset the sequence counter

;

E365;

. . Load the 8 least significant 8 bits

. . of the original dividend into the Z

. . register

;

E067F2;

SEX R0; OUT 7; DC 0F2H

SEX R2; INP 5; IRX

INP 6

. . Do the second division

;

E26D60;

. . Read and store the least significant

. . 8 bits of the answer at 2001 hex

. . Read and store the remainder at 2002

. . hex

;

6E;

;

11

CDP1855, CDP1855C

For the divide operation (Figure 5), the formula is:

Y Y Y Z Z Z

Y Y Y

3 2 1

X X X

3 2 1

3

2

1

3

2

1

------------------------------------------- = Z Z Z + ---------------------

3

2

1

X X X

3

2

1

EF1

DATA BUS

BUS

8

MRD

TPB

TO

CPU

CLEAR

N2

N1

N0

8

V

DD

BUS RD/ STB CLR

WE

CN1

CN0

RA0

RA1

RA2

CN0

RA0

RA1

RA2

CN0

RA0

RA1

RA2

CLOCK

CLK

SHIFT

V

DD

Y

Z

Y

Z

Y

Z

L

R

L

R

L

R

CDP1855

Z

L

R

L

O.F.

CE

C.I.

CTL

C.O.

CE

C.I.

CTL

C.O.

CE

C.I.

CTL

V

DD

OR

I/O SELECT

MOST SIGNIFICANT

LEAST SIGNIFICANT

FIGURE 5. CASCADING THREE MDU’s (CDP1855) IN AN 1800 SYSTEM WITH MDU’s BEING ACCESSED AS I/O PORTS IN

PROGRAMMING EXAMPLE

CLOCK

EF1

DATA BUS

BUS

MRD

TPB

CLEAR

N2

N1

N0

V

DD

BUS RD/ STB CLR

WE

CN1

CN0

RA0

RA1

RA2

CN0

RA0

RA1

RA2

CN0

RA0

RA1

RA2

CN0

RA0

RA1

RA2

CLK

SHIFT

V

DD

Y

Z

Y

Z

Y

Z

Y

Z

L

R

L

R

L

R

L

R

CDP1855

Z

L

R

L

R

O.F.

CE

C.I.

CTL

C.O.

CE

C.I.

CTL

C.O.

CE

C.I.

CTL

C.O.

CE

C.I.

CTL

MOST SIGNIFICANT

LEAST SIGNIFICANT

FIGURE 6. CASCADING FOUR MDU’s (CDP1855)

12

CDP1855, CDP1855C

o

Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, V = 0.7V , V = 0.3V

,

A

DD

R

F

IH

DD IL

DD

C

= 100pF (See Figure 7)

L

LIMITS

CDP1855

CDP1855C

(NOTE 1)

V

(NOTE 2)

DD

PARAMETER

(V)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

OPERATION TIMING

Maximum Clock Frequency

(Note 3)

5

10

5

3.2

4

-

3.2

4

-

MHz

ns

6.4

8

-

1.6

-

Maximum Shift Frequency

(1 Device) (Note 4)

1.6

2

-

2

-

10

5

3.2

-

4

-

100

-

Minimum Clock Width

Minimum Clock Period

t

100

50

150

75

-

150

CLK0

CLK1

10

5

-

312

-

ns

t

-

250

125

200

100

50

312

156

300

150

67

-

250

-

ns

CLK

10

5

-

ns

Clock to Shift Propagation

Delay

t

-

200

-

300

-

ns

CSH

10

5

-

ns

Minimum C.I. to Shift Setup

t

-

50

-

67

-

ns

SU

10

5

-

25

33

-

ns

C.O. from Shift Propagation

Delay

t

-

450

225

50

600

300

75

-

450

-

600

-

ns

PLH

PHL

10

5

-

ns

Minimum C.I. from Shift Hold

t

-

50

-

75

-

ns

H

10

5

-

25

40

-

ns

Minimum Register Input

Setup

t

-

-20

-10

400

200

50

10

-

-20

-

10

-

ns

SU

10

5

-

10

-

ns

Register after Shift Delay

t

-

600

300

100

50

-

400

-

600

-

ns

PLH

PHL

10

5

-

ns

Minimum Register after Shift

Hold

t

-

50

-

100

-

ns

H

10

5

-

25

-

ns

C.O. from C.I. Propagation

Delay

t

-

100

50

150

75

-

100

-

150

-

ns

PLH

PHL

10

5

-

ns

Register from C.I.

Propagation Delay

t

-

80

120

60

-

80

-

120

-

ns

PLH

PHL

10

-

40

-

ns

NOTES:

1. Maximum limits of minimum characteristics are the values above which all devices function.

o

2. Typical values are for T = 25 C and nominal voltages.

A

3. Clock frequency and pulse width are given for systems using the internal clock option of the CDP1855. Clock frequency equals shift

frequency for systems not using the internal clock option.

4. Shift period for cascading of devices is increased by an amount equal to the C.I. to C.O. Propagation Delay for each device added.

13

CDP1855, CDP1855C

o

Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, V = 0.7V , V = 0.3V

,

A

DD

R

F

IH

DD IL

DD

C

= 100pF (See Figure 8)

L

LIMITS

CDP1855

CDP1855C

(NOTE 1)

V

(NOTE 2)

DD

PARAMETER

(V)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

WRITE CYCLE

Minimum Clear Pulse Width

Minimum Write Pulse Width

Minimum Data-In-Setup

Minimum Data-In-Hold

t

5

10

5

-

50

25

75

40

225

115

0

-

50

-

75

-

ns

CLR

t

150

75

150

-

225

-

WW

10

5

t

-75

-40

50

-75

-

0

DSU

10

5

0

-

t

75

40

75

40

75

40

50

-

75

-

DH

10

5

25

Minimum Address to Write

Setup

t

50

-

75

-

ASU

10

5

25

Minimum Address after

Write Hold

t

50

-

75

-

AH

10

25

NOTES:

1. Maximum limits of minimum characteristics are the values above which all devices function.

o

2. Typical values are for T = 25 C and nominal voltages.

A

o

Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, V = 0.7V , V = 0.3V

,

A

DD

R

F

IH

DD IL

DD

C = 100pF (See Figure 9)

L

LIMITS

CDP1855

CDP1855C

(NOTE 1)

V

(NOTE 2)

DD

PARAMETER

(V)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

READ CYCLE

CE to Data Out Active

t

5

10

5

-

200

100

300

150

300

150

75

300

150

450

225

450

225

115

225

115

300

150

300

150

-

200

300

ns

CDO

-

300

-

450

-

CE to Data Access

t

-

CA

AA

10

5

-

Address to Data Access

Data Out Hold after CE

Data Out Hold after Read

Read to Data Out Active

Read to Data Access

t

-

300

-

450

-

10

5

-

t

50

25

50

25

-

50

-

150

-

225

-

DOH

RDO

10

5

150

75

50

-

150

-

225

-

10

5

200

100

200

100

-

200

-

300

-

10

5

-

t

-

200

-

300

-

RA

10

-

14

CDP1855, CDP1855C

o

Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, t , t = 20ns, V = 0.7V , V = 0.3V

,

A

DD

R

F

IH

DD IL

DD

C

= 100pF (See Figure 9) (Continued)

L

LIMITS

CDP1855

CDP1855C

(NOTE 1)

V

(NOTE 2)

DD

PARAMETER

(V)

MIN

50

25

-

TYP

MAX

300

150

225

115

MIN

TYP

MAX

300

-

UNITS

ns

Strobe to Data Access

t

5

200

100

150

75

50

-

200

SA

10

5

-

150

-

ns

Minimum Strobe Width

t

-

225

-

ns

SW

10

-

ns

NOTES:

1. Maximum limits of minimum characteristics are the values above which all devices function.

o

2. Typical values are for T = 25 C and nominal voltages.

A

Timing Diagrams

t

CLOCK

CLK

1

2

9

t

CLK 1

t

CLK 0

SHIFT

1

2

9

(PRESCALER OFF)

t

CSH

t

, t

PLH PHL

C.O., Y , Y , Z , Z OUT

L

R

L

R

t

H

SU

C

, Y , Y , Z , Z IN

L R L R

IN

FIGURE 7. OPERATION TIMING DIAGRAM

t

CLR

CLEAR

CE

RD/WE

STB

* t

WW

* WRITE IS OVERLAP OF CE = 1, RD/WE = 0, AND STB = 1.

D

IN

t

DSU

ASU

t

DH

RA0-2

t

AH

FIGURE 8. WRITE TIMING DIAGRAM

15

CDP1855, CDP1855C

Timing Diagrams (Continued)

CE

ADVANCE

SEQUENCE COUNTER

RD/WE

STB

t

SW

t

DOH

RA0-2

t

AA

t

DOH

SA

D

OUT

t

RDO

CDO

t

RA

CA

FIGURE 9. READ TIMING DIAGRAM

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

16


型号：	CDP1855_1
厂家：	Intersil
描述：	8-Bit Programmable Multiply/Divide Unit 8位可编程乘法/除法单元
文件：	总16页 (文件大小：191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDP1855_1 [INTERSIL]

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