CDP1878CD [INTERSIL]
CMOS Dual Counter-Timer; CMOS双反定时器
| 型号： | CDP1878CD |
| 厂家： | 
Intersil |
| 描述： | CMOS Dual Counter-Timer |
| 文件： | 总13页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1878C
CMOS Dual Counter-Timer
March 1997
Features
Description
• Compatible with General Purpose and CDP1800
Series Microprocessor Systems
The CDP1878C is a dual counter-timer consisting of two 16-
bit programmable down counters that are independently
controlled by separate control registers. The value in the reg-
isters determine the mode of operation and control func-
tions. Counters and registers are directly addressable in
memory space by any general industry type microproces-
sors, in addition to input/output mapping with the CDP1800
series microprocessors.
• Two 16-Bit Down Counters and Two 8-Bit Control
Registers
• 5 Modes Including a Versatile Variable-Duty Cycle
Mode
• Programmable Gate-Level Select
Each counter-timer can be configured in five modes with the
additional flexibility of gate-level control. The control regis-
ters in addition to mode formatting, allow software start and
stop, interrupt enable, and an optional read control that
allows a stable readout from the counters. Each counter-
timer has software control of a common interrupt output with
an interrupt status register indicating which counter-timer
has timed out.
• Two-Complemented Output Pins for Each Counter-
Timer
• Software-Controlled Interrupt Output
• Addressable in Memory Space or CDP1800-Series I/O
Space
Ordering Information
In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.
PART
NUMBER
CDP1878CE
CDP1878CD
TEMP. RANGE
PACKAGE
PKG. NO.
E28.6
N28.6
This type is supplied in 28-lead dual-in-line ceramic pack-
ages (D suffix), and 28-lead dual-in-line plastic packages (E
suffix).
o
o
-40 C to +85 C PDIP
o
o
-40 C to +85 C SBDIP
Pinout
CDP1878C
(DIP)
TOP VIEW
TABLE 1. MODE DESCRIPTION
MODE
FUNCTION
APPLICATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INT
TAO
TAO
TAG
TACL
RD
V
DD
1 Timeout
Outputs change when clock
decrements counter to “0”
Event counter
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TBO
TBO
TBG
TBCL
3
4
2 Timeout
Strobe
One clockwide output pulse
when clock decrements
counter to “0”
Trigger pulse
5
6
7
IO/MEM
TPB/WR
TPA
3 Gate-Con-
trolled One
Shot
Outputs change when clock
decrements counter to “0”.
Retriggerable
Time-delay
generation
8
9
10
11
12
13
14
CS
4 Rate Generator Repetitive clockwide output
pulse
Time-base
generator
A0
A1
5 Variable-Duty Repetitive output with
Cycle
Motor control
A2
programmed duty cycle
V
RESET
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1341.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-91
CDP1878C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply-Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1878C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
SS
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
55
50
N/A
12
DD
T = Full Package Temperature Range
A
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T )
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
A
o
o
o
o
o
o
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
STG
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
PARAMETER
DC Operating Voltage Range
Input Voltage Range
SYMBOL
MIN
MAX
UNITS
V
4
6.5
V
V
V
SS
-
DD
5
Maximum Clock Input Rise or Fall Time
Minimum Clock Pulse Width
Maximum Clock Input Frequency
t , t
µs
R
F
t
, t
WL WH
200
DC
-
ns
f
1
MHz
CL
o
o
Static Electrical Specifications At T = -40 C to +85 C, V ± 5% Except as noted:
A
DD
CONDITIONS
LIMITS
V
V
V
DD
(NOTE 1)
O
IN
PARAMETER
Quiescent Device Current
Output Low Drive (Sink) Current
Output High Drive (Source) Current
Output Voltage Low-Level (Note 2)
Output Voltage High-Level (Note 2)
Input Low Voltage
SYMBOL
(V)
(V)
0, 5
0, 5
0, 5
0, 5
0, 5
-
(V)
5
5
5
5
5
5
5
5
5
-
MIN
TYP
MAX
200
-
UNITS
I
-
-
0.02
3.2
-2.3
0
µA
mA
mA
V
DD
I
0.4
1.6
OL
I
4.6
-1.15
-
OH
V
-
-
0.1
-
OL
V
-
4.9
5
V
OH
V
0.5, 4.5
-
-
1.5
-
V
IL
IH
IN
Input High Voltage
V
0.5, 9.5
-
3.5
-
V
Input Leakage Current
I
Any Input
0, 5
0, 5
-
-
-
-
-
-
±1
3
µA
mA
pF
pF
Operating Current (Note 3)
Input Capacitance
I
-
-
-
1.5
5
DD1
C
7.5
15
IN
Output Capacitance
C
-
-
10
OUT
NOTES:
1. Typical values are for T = +25 C and nominal V
o
.
DD
A
2. I = I
OL
= 1µA
OH
3. Operating current measured at 200kHz for V
imum speed of 3.2MHz).
= 5V, with open outputs (worst-case frequencies for CDP1802A system operating at max-
DD
4-92
CDP1878C
Functional Diagram
JAM
REGISTER A
RESET
RD
GATE A
TAO
TAO
CONTROL REGISTER A
AND MODE CONTROL
TPB/WR
IO/MEM
TPA
I-O
CONTROL
AND
COUNTER A
CLOCK A
CS
LOGIC
A2
A1
A0
HOLDING
REGISTER A
V
DD
V
INT AND
STATUS REGISTER
SS
INT
8-BIT
EXTERNAL
BUS
DATA
BUS
DRIVERS
JAM
REGISTER B
GATE B
TBO
TBO
CONTROL REGISTER B
AND MODE CONTROL
COUNTER B
CLOCK B
HOLDING
REGISTER B
FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS
TERMINAL
- V
USAGE
TERMINAL
TAO, TAO
TBO, TBO
TPA
USAGE
V
Power
Data to and from device
TPB/WR, RD Directional Control Signals
Complemented outputs of Timer A
Complemented outputs of Timer B
DD
SS
DB0-DB7
Used with CDP1800-series processors, tied high
otherwise
A0, A1, A2
Addresses that select counters or registers
CS
INT
Active high input that enables device
Low when counter is “0”
TACL, TBCL Clocks used to decrement counters
TAG, TBG
Gate inputs that control counters
RESET
When active, TAO, TBO are low, TAO, TBO are
high. Interrupt status register is cleared.
IO/MEM
Tied high in CDP1800 input/output mode, other-
wise tied low
4-93
CDP1878C
REGISTER TRUTH TABLE
ACTIVE
ADDRESS
A2
1
1
0
0
1
1
1
0
0
1
1
1
0
0
A1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
A0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
TPB/WR
RD
REGISTER COUNTER
Write Counter A MSB
Read Counter A MSB
Write Counter A LSB
Read Counter A LSB
Control Register A
X
X
X
X
X
X
Write Counter B MSB
Read Counter B MSB
Write Counter B LSB
Read Counter B LSB
Control Register B
X
X
X
X
X
X
Interrupt Status Register
Not Used
Not Used
Programming Model
BUS 7
BUS 7
CONTROL REGISTER
WRITE ONLY
BUS 0
BUS 0
CONTROL REGISTER
WRITE ONLY
HOLDING REGISTER LSB
READ ONLY
JAM REGISTER LSB
WRITE ONLY
HOLDING REGISTER LSB
READ ONLY
JAM REGISTER LSB
WRITE ONLY
HOLDING REGISTER MSB
JAM REGISTER MSB
HOLDING REGISTER MSB
JAM REGISTER MSB
COUNTER A REGISTERS
COUNTER B REGISTERS
BUS 7
BUS 0
X
X
0
0
0
0
0
0
READ ONLY
TIMER A
TIMER B
INTERRUPT STATUS REGISTER
4-94
CDP1878C
(most significant and least significant byte in any order), and
Functional DescriptIon
then the control register be accessed and loaded with the
control word. The trailing edge of the TPB/WR pulse will latch
the control word into the control register. The trailing edge of
the first clock to occur with gate valid will cause the counter to
be jammed with its initial value. The counter will decrement on
the trailing edge of succeeding clocks as long as the gate is
valid, until it reaches zero. The output levels will then change,
and if enabled, the interrupt output will become active and the
appropriate timer bit will be set in the interrupt status register.
The interrupt output and the interrupt status register can be
cleared (to their inactive state) by addressing the control reg-
ister with the TPB/WR line active For example, if counter A
times out, control register A must be accessed to reset the
interrupt output high and reset the timer A bit in the status reg-
ister low. Timer B bit in the status register will be unaffected.
The dual counter-timer consists of two programmable 16-bit
down counters, separately addressable and controlled by
two independent 8-bit control registers. The word in the con-
trol register determines the mode and type of operation that
the counter-timer performs. Writing to or reading from a
counter or register is enabled by selective addressing during
a write or read cycle. The data is placed on the data bus by
the microprocessor during the write cycle or read from the
counter during the read cycle. Data to and from the counters
and to the control registers is in binary format.
Each counter-timer consists of three parts. The first is the
counter itself, a 16-bit down counter that is decremented on
the trailing edge of the clock input. The second is the jam
register that receives the data when the counter is written to.
The word in the control register determines when the jam
register value is placed into the counter. The third part is the
Read Operation
holding register that places the counter value on the data Each counter has a holding register that is continuously
bus when the counter is read.
being updated by the counter and is accessed when the
counter is addressed during read cycles. Counter reads are
accomplished by halting the holding register and then read-
ing it, or by reading the holding register directly. If the holding
register is read directly, data will appear on the bus if the
counters are addressed with the RD line active. However, if
the clock decrements the counter between the two read
operations (most and least significant byte), an inaccurate
value will be read. To preclude this from happening, writing a
“1” into bit 6 of the control register and then addressing and
reading the counter will result in a stable reading. This oper-
ation prevents the holding register from being updated by the
counter and does not affect the counter’s operation.
When the counter has decremented to zero, three events
occur. The first involves the common interrupt output pin that,
if enabled, becomes active low. The second is the setting of a
bit in the interrupt status register. This register can be read to
determine which counter-timer has timed out. The third event
is the logic change of the complemented output pins.
In addition to the clock input used to decrement the counter, a
gate input is available to enable or initiate operation. The
counter-timers are independent and can have different mode
operations.
Write Operation
The interrupt status register is read by addressing either
control register with the RD line active. A “1” in bit 7 indicates
Timer A has timed out and a “1” in bit 6 indicates Timer B
has timed out. Bits 0-5 are zeros.
The counters and registers are separately addressable and
are programmed via the data bus when the chip is selected
with the TPB/WR pin active. Normal sequencing requires that
the counter jam register be loaded first with the required value
Control Register
7
6
5
4
3
2
1
0
JAM ENABLE
1 = ENABLE
0 = DISABLE
MODE SELECT
001 = MODE 1
010 = MODE 2
†011 = MODE 3
100 = MODE 4
101 = MODE 5
†PLUS BIT 7 = 0
GATE LEVEL SELECT
1 = POSITIVE (HIGH)
0 = NEGATIVE (LOW)
HOLDING REGISTER CONTROL
1 = FREEZE HOLDING REGISTER
0 = UPDATE CONTINUOUSLY
INTERRUPT ENABLE
1 = ENABLE
0 = DISABLE
START/STOP CONTROL
1 = START COUNTER
0 = STOP COUNTER
Bits 0, 1 and 2
BIT 7 BIT 2 BIT 1 BIT 0
Mode Selects - See Mode Timing Diagrams (Figures 1, 2, 3,
4, and 5).
Mode 1 - Timeout
-
-
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
Mode 2 - Timeout Strobe
Mode 3 - Gate Controlled One Shot
Mode 4 - Rate Generator
Mode 5 - Variable-Duty Cycle
Note: When selecting a mode, the timer outputs TAO and TBO
are set low, and TAO and TBO are set high. If bits 0, 1 and 2
are all zero’s when the control register is loaded, no mode is
selected, and the counter-timer outputs are unaffected. Issuing
mode 6 will cause an indeterminate condition of the counter,
issuing mode 7 is equivalent to issuing mode 5.
0
-
-
No Mode selected. Counter outputs
unaffected
-
4-95
CDP1878C
Bit 3 - Gate Level Select - All modes require an enabling sig- tion will hold a stable value in the hold register for subse-
nal on the gate to allow counter operation. This enabling sig- quent read operations. Rewriting a “1” into bit 6 will cause an
nal is either a level or a pulse (edge). Positive gate level or update in the holding register on the next trailing clock edge.
edge enabling is selected by writing a “1” into this bit and If this location contains a “0”, the holding register will be
negative (low) enabling is selected when bit 3 is “0”.
updated continuously by the value in the counter.
Bit 4 - Interrupt Enable - Setting this bit to “1” enables the Bit 7 - Jam Enable - When this bit is set to “1 “during a write
INT output, and setting it to “0” disables it. When reset, the to the control register, the 16-bit value in the jam register will
INT output is at a high level. If the interrupt enable bit in the be available to the counter; TAO and TBO are reset low and
control register is enabled and the counter decrements to TAO and TBO are set high. On the trailing edge of the first
zero, the INT output will go low and will not return high until input clock signal with the gate valid this value will be latched
the counter-timer is reset or the selected control register is in the counter, the counter outputs TAO and TBO will be set
written to. Example: If timer B times out, control register B high and the TAO and TBO will be reset low. Setting bit 7 to
must be accessed to reset the INT output high. If the inter- “0” will leave the counter value unaffected. This location
rupt enable bit is set to “0”, the counter’s timeout will have no should be set to “0” any time a write to the control register
effect on the lNT output.
must be performed without changing the present counter
value. If the value in the jam register has not been changed,
writing a “1” into bit 7 of the control register with zeros in bits
0,1, and 2 (mode select) will reload the counter with the old
value and leave the mode unchanged. If the value in the jam
register is changed, then the next write to the control register
(with bit 7 a “1”) must include a valid mode select (i.e., at
least 1 of the bits 0,1, or 2 must be a ”1”).
In mode 5, the variable-duty cycle mode, the lNT pin will
become active low when the MSB in the counter has decre-
mented to zero.
Bit 5 - Start/Stop Control - This bit controls the clock input to
the counter and must be set to “1” to enable it. Writing a “0”
into this location will halt operation of the counter. Operation
will not resume until the bit is set to “1”.
In mode 3, the hardware start is enabled by writing a “0” into
bit 7. If a “1” is written to bit 7, the timeout will start immedi-
ately and mode 3 will resemble mode 1.
Bit 6 - Holding Register Control - Since the counter may be
decrementing during a read cycle, writing a “1” into this loca-
Mode Descriptions
MODE
Timeout
CONTROL REGISTER
GATE CONTROL
Selectable High or Low
Level Enables Operation
1
X X X X X 0 0 1
BUS 7 BUS 0
Mode 1
After the count is loaded into the jam register and the control interrupt output is set low. Writing to the counter while it is
register is written to with the jam-enable bit high on the trail- decrementing has no effect on the counter value unless the
ing edge of the first clock after the gate is valid, TXO goes control register is subsequently written to with the jam-
high and TXO goes low. The input clock decrements the enable bit high. After timeout the counter remains at FFFF
counter as long as the gate remains valid. When it reaches unless reloaded.
zero TXO goes low and TXO goes high, and if enabled, the
COUNTER VALUE
5
4
3
2
1
1
0
CLOCK
5
4
3
2
1
1
0
FFFF
WR CONTROL
REGISTER
STALL COUNTER
GATE
TXO
INT
LOAD COUNT = 5
FIGURE 1. TIMEOUT (MODE 1) TIMING WAVEFORMS
4-96
CDP1878C
MODE
CONTROL REGISTER
GATE CONTROL
Timeout Strobe
Selectable High or Low
Level Enables Operation
2
X X X X X 0 1 0
BUS 7
BUS 0
Mode 2
Operation of this mode is the same as mode 1, except the to the condition of TXO high and TXO low, and the counter is
outputs will change for one clock period only and then return reloaded
COUNTER VALUE
3
2
2
1
1
0
0
3
3
3
3
2
2
1
1
0
CLOCK
3
SEE NOTE
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 2. TIMEOUT STROBE (MODE 2) TIMING WAVEFORMS
NOTE: Write to control register with mode selects = 0
MODE
CONTROL REGISTER
GATE CONTROL
Gate Controlled One-Shot
Selectable Positive or
Negative Going Edge
Initiates Operation
3
0
X X X X 0 1 1
BUS 7 BUS 0
Mode 3
After the jam register is loaded with the required value, the gerable: While the counter is decrementing, a gate edge or
gate edge will initiate this mode. TXO will be set high, and write to the control register with the jam-enable bit high, will
TXO will be set low. The clock will decrement the counter. load the counter with the jam register value and restart the
When zero is reached, TXO will go low and TXO will be high, one-shot operation.
and the interrupt output will be set low. The counter is retrig-
3
2
1
0
3
3
2
COUNTER VALUE
CLOCK
3
2
1
0
3
3
2
1
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 3. GATE CONTROLLED ONE-SHOT (MODE 3) TIMING WAVEFORMS
4-97
CDP1878C
MODE
CONTROL REGISTER
GATE CONTROL
Rate Generator
Selectable High or Low
Level Enables Operation
4
X X X X X 1 0 0
BUS 7
BUS 0
Mode 4
A repetitive clock-wide output pulse will be output, with the not affect the counter’s operation until the present timeout
time between pulses equal to the counter’s value, (trailing has concluded, unless the control register is written to with
edge to leading edge). This model is software started with a the jam-enable bit high. If the gate input (TAG or TBG) is
write to the control register if the gate level is valid. If the used to start this mode, the first cycle following the gate
counter is written to while decrementing, the new value will going true is indeterminate.
COUNTER VALUE
CLOCK
3
2
1
0
3
3
2
1
0
3
N
3
2
1
0
2
1
0
3
N
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 4. RATE GENERATORS (MODE 4) TIMING WAVEFORMS
MODE
CONTROL REGISTER
GATE CONTROL
Variable Duty Cycle
Selectable High or Low
Level Enables Operation
5
X X X X X 1 0 1
BUS 7
BUS 0
Mode 5
After the mode is initiated, the outputs will remain at one with a duty cycle directly controlled by the value in the
level until the clock decrements the least significant byte of counter. The output period will be equal to LSB+MSB+2.
the counter to N+1. The outputs will then change level and
The interrupt output will become active after the MSB is
the counter decrements the most significant byte to N+1.
loaded into the counter and decrements to zero.
The process will then repeat, resulting in a repetitive output
2
1
0
1
0
2
1
0
1
COUNTER VALUE
CLOCK
2
1
0
1
0
2
1
0
1
WR CONTROL
REGISTER
GATE
TXO
INT
LSB
MSB
LSB
LOAD COUNT LSB = 2 AND MSB = 1
FIGURE 5. VARIABLE-DUTY CYCLE (MODE 5) TIMING WAVEFORMS
NOTE: In order to avoid unwanted starts when selecting mode 3 or 4, the gate signal must be set to the opposite level that will be pro-
grammed.
4-98
CDP1878C
Setting the Control Register
Function Pin Description
The following will illustrate a counter write and subsequent
reads that places stable, accurate values on the data bus
from the counter-timer.
DB7 - DB0 - 8-bit bidirectional bus used to transfer binary
information between the microprocessor and the dual
counter-timer.
The counter is addressed and the required values are
loaded with a write operation. The control register is
addressed next and loaded with B9H.
V
, V - Power and ground for device.
DD SS
A0, A1, and A2 - Addresses used to select counters or reg-
isters.
TPB/WR, RD - Directional signals that determine whether
data will be placed on the bus from a counter or the interrupt
status register (RD active) (memory mapped), or data on the
bus will be placed into a counter or control register (TPB/WR
active). The following connections are required between the
microprocessor and the counter-timer in the CDP1800-
series input/output mapping mode.
BUS 7
BUS 0
1
0
1
1
1
0
0
1
CONTROL
REGISTER = B9H
MODE 1 SELECTED
POSITIVE GATE ENABLING
REQUIRED
LOAD COUNTER
WITH JAM REGISTER
MICROPROCESSOR
COUNTER-TIMER
RD
INTERRUPT OUTPUT
ENABLED
MRD
TPB
TPB/WR
HOLDING REGISTER
CONTINUOUSLY
UPDATED BY COUNTER
TPA
TPA
COUNTER START
N Lines
Address Lines
and IO/MEM to V
DD
FIGURE 6.
During an output instruction, data from the memory is
strobed into the counter-timer during TPB when RD is active,
and latched on TPB’s trailing edge. Data is read from the
counter-timer when RD is not active between the trailing
edges of TPA and TPB. See Figures 11, 12, and 13.
The counter will now decrement with each input clock pulse
while the gate is valid. Assuming the counter has not decre-
mented to zero and its value is to be read without affecting
the counter’s operation, a write to the control register is per-
formed. 78H is loaded into the control register.
TACL, TBCL - Clocks used to decrement the counter.
TAG, TBG - Gate inputs used to control counter.
TAO, TAO - Complemented outputs of Timer A.
TBO, TBO - Complemented outputs of Timer B.
BUS 7
BUS 0
INT - Common interrupt output. Active when counter decre-
0
1
1
1
1
0
0
0
ments to zero.
CONTROL
REGISTER = 78H
RESET - Active low signal that resets counter outputs (TAO,
TBO low, TAO, TBO high). The interrupt output is set high
and the status register is cleared.
COUNTER VALUE
UNAFFECTED
UNCHANGED
COUNTER OUTPUTS
UNAFFECTED
IO/MEM - Tied high in CDP1800-series input/output mode,
otherwise tied low.
FREEZE HOLDING
REGISTER
TPA - Tied to TPA of the CDP1800-series microprocessors.
During memory mapping, it is used to latch the high order
address bit for the chip select. In the CDP1800 input/output
mode, it is used to gate the N lines. When the counter-timer
is used with other microprocessors, or when the high order
address of the CDP1800-series microprocessors is exter-
FIGURE 7.
nally latched, it is connected to V
.
DD
The counter is addressed and read operations are per-
formed.
CS - An active high signal that enables the device.
4-99
CDP1878C
CLOCK XTAL
TACL, TBCL
RESET
TPB/WR
RD
TAG
TBG
TAO
TAO
TBO
TBO
GATE
INPUTS
CLEAR
MWR
MRD
TPA
TPA
MAO
MA1
A0
A1
TIMER
OUTPUTS
ADDRESS
LINES
MA2
A2
MA7
CS
V
IO/MEM
INT
SS
INT
COUNTER - TIMER
DB0 - DB7
MEMORY
CDP1802
DATA BUS
FIGURE 8. TYPICAL CDP1802 MEMORY-MAPPED SYSTEM
LATCH HIGH-ORDER
ADDRESS FOR CS
LOW BYTE
TPA
HIGH BYTE
ADDRESS
TPB/WR
DATA LATCHED
DATA FROM CPU
TO COUNTER-TIMER
VALID DATA
FIGURE 9. CDP1800-SERIES MEMORY-MAPPING WRITE CYCLE TIMING WAVEFORMS
TPA
ADDRESS
RD
HIGH BYTE
LOW BYTE
OUTPUT DRIVERS
ENABLED
DISABLED
DATA FROM
COUNTER-TIMER
TO CPU
VALID DATA
FIGURE 10. CDP1800-SERIES MEMORY-MAPPING READ CYCLE TIMING WAVEFORMS
4-100
CDP1878C
CLOCK XTAL
TACL, TBCL
RESET
TPA
TAG
TBG
TAO
TAO
TBO
TBO
GATE
INPUTS
CLEAR
TPA
MRD
TPB
N0
RD
TPB/WR
A0
N1
A1
TIMER
OUTPUTS
ADDRESS
LINES
N2
A2
CS
V
IO/MEM
INT
DD
INT
COUNTER - TIMER
DB0 - DB7
MEMORY
CDP1802
DATA BUS
FIGURE 11. TYPICAL CDP1802 INPUT/OUTPUT-MAPPED SYSTEM
TPA
RD
N LINES
DATA LATCHED
TPB/WR
DATA FROM MEMORY
TO COUNTER-TIMER
VALID DATA
FIGURE 12. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION
OUTPUT DRIVERS ENABLED
TPA
RD
OUTPUT DRIVERS
DISABLED
TPB/WR
N LINES
DATA FROM
COUNTER-TIMER
TO MEMORY
VALID DATA
FIGURE 13. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION
4-101
CDP1878C
o
Dynamic Electrical Specifications at T = -40 to +85 C, V = 5V ± 5%, Input t , t = 10ns, C = 50pF and 1 TTL Load
A
DD
R
F
L
(NOTE 1)
(NOTE 2)
PARAMETER
READ CYCLE TIMES (See Figure 14)
Data Access from Address
Read Pulse Width
SYMBOL
MIN
TYP
MAX
UNITS
t
-
400
-
350
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
DA
RD
DR
RH
DH
t
t
t
t
-
Data Access from Read
Address Hold after Read
Output Hold after Read
Chip Select Setup to TPA
NOTES:
250
0
-
-
-
50
50
t
CS
1. Time required be a limit device to allow for the indicated function.
o
2. Typical values are for T = 25 C and nominal V
A
.
DD
TPA
t
CS
t
RH
ADDRESS/CHIP SELECT
t
RD
READ
DATA TO CPU
t
DR
t
t
DA
DH
FIGURE 14. READ CYCLE TIMING WAVEFORMS
4-102
CDP1878C
o
Dynamic Electrical Specifications at T = -40 to +85 C, V = 5V ± 5%, Input t , t = 10ns, C = 50pF and 1 TTL Load
A
DD
R
F
L
(NOTE 1)
(NOTE 2)
PARAMETER
WRITE CYCLE TIMES (See Figure 15)
Address Setup to Write
Write Pulse Width
SYMBOL
MIN
TYP
MAX
UNITS
t
150
150
200
50
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
AS
t
WR
Data Setup to Write
t
DS
AH
WH
Address Hold after Write
Data Hold after Write
Chip Select Setup to TPA
NOTES:
t
t
50
t
50
CS
1. Time required by a limit device to allow for the indicated function.
o
2. Typical values are for T = 25 C and nominal V
A
.
DD
TPA
t
CS
t
AH
ADDRESS/CHIP SELECT
t
t
WR
AS
WRITE
DATA TO COUNTER-TIMER
t
t
WH
DS
FIGURE 15. WRITE CYCLE TIMING WAVEFORMS
C
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4-103
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