CDP68HC68W1E [INTERSIL]
CMOS Serial Digital Pulse Width Modulator; CMOS串行数字脉宽调制器
| 型号： | CDP68HC68W1E |
| 厂家： | 
Intersil |
| 描述： | CMOS Serial Digital Pulse Width Modulator |
| 文件： | 总9页 (文件大小：46K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP68HC68W1
CMOS Serial Digital Pulse Width Modulator
March 1998
Features
Description
• Programmable Frequency and Duty Cycle Output
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
• Serial Bus Input; Compatible with Motorola/Intersil
SPI Bus, Simple Shift-Register Type Interface
• 8 Lead PDIP Package
• Schmitt Trigger Clock Input
o
o
• 4V to 6V Operation, -40 C to 85 C Temperature Range
• 8MHz Clock Input Frequency
Pinout
V pin rises above 0.75V. The CDP68HC68W1 is supplied in
an 8 lead PDIP package (E suffix).
T
CDP68HC68W1
(PDIP)
TOP VIEW
Ordering Information
CLK
CS
1
2
3
4
8
7
6
5
V
DD
TEMP. RANGE
PKG.
NO.
o
PWM
SCK
PART NUMBER
( C)
PACKAGE
V
T
CDP68HC68W1E
-40 to 85
8 Ld PDIP
E8.3
V
DATA
SS
Block Diagram
PWM
INPUT CLK
MODULATOR
LOGIC
CLK
8 - STAGE RIPPLE
COUNTER
8 - STAGE RIPPLE
COUNTER
RESET
LOAD
PULSE - WIDTH
DATA REGISTER
FREQUENCY
DATA REGISTER
LOAD
DATA
8 - STAGE SHIFT
REGISTER
8 - STAGE SHIFT
REGISTER
CONTROL REGISTER
2 - STAGE SHIFT
LOAD
V
T
V
T
COMPARATOR
SCK
8
16
24
5 - STAGE 24 - STATE
COMPARATOR
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number 1919.3
1
CDP68HC68W1
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage Range, (V ) . . . . . . . . . . . . . . . . -0.5V to +7V
DD
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
(Voltage Referenced to V Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
SS
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . 100mW
99
+0.5V
DD
o
o
Maximum Storage Temperature Range (T
) . . . .-65 C to 150 C
STG
o
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 265 C
At Distance 1/16 ±1/32 in. (1.59 ± 0.79mm)
From Case for 10s Max
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
A
T = Full Package Temperature Range (All Package Types)
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
o
o
CDP68HC68W1, V
= 5V ±10%, V = 0V, T = -40 C to 85 C
SS
DD
A
DC Operating Voltage Range
Input Voltage Range (Except V Pin)
-
4
-
-
-
-
-
-
-
-
-
-
6
V
V
V
0.7•V
DD
V
+0.3V
T
IH
DD
V
-0.3
0.3•V
V
IL
IT
DD
V
Pin Output Voltage Threshold
V
0.4
0.15•V
V
T
DD
Device Current in “Power Down” Mode, Clock Disabled
I
-
-
1
0.4
-
µA
V
PD
Low Level Output Voltage (I = 1.6mA)
OL
V
OL
High Level Output Voltage (I
Input Leakage Current
= -1.6mA)
V
V - 0.4V
DD
V
OH
OH
I
-
-
-
±1
1
µA
mA
pF
IN
Operating Device Current (f
Clock Input Capacitance
= 1MHz)
o
I
OPER
CLK
C
10
IN
(V = 0V, f
IN
= 1MHz, T = 25 C)
CLK
A
Control Timing
PARAMETER
SYMBOL
MIN
MAX
UNITS
o
o
CDP68HC68W1, V
Clock Frequency
Cycle Time
= 5V ±10%, V = 0V, T = -40 C to 85 C
SS
DD
A
F
DC
-
8.0
-
MHz
ns
CLK
t
CYC
Clock to PWM Out
Clock High Time
Clock Low Time
t
-
125
-
ns
PWMO
t
50
50
-
ns
CLKH
t
-
ns
CLKL
Rise Time (20% V
to 70% V
)
t
R
100
100
ns
DD
DD
Fall Time (70% V
DD
to 20% V
)
t
-
ns
DD
F
2
CDP68HC68W1
SPI Interface Timing
PARAMETER
SYMBOL
MIN
MAX
UNITS
o
o
CDP68HC68W1, V
= 5V ±10%, V = 0V, T = -40 C to 85 C
SS
DD
A
Serial Clock Frequency
Cycle Time
f
DC
480
240
-
2.1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
t
-
SCYC
Enable Lead Time
t
-
ELD
ELG
Enable Lag Time
t
200
Serial Clock (SCK) High Time
Serial Clock (SCK) Low Time
Data Setup Time
t
190
190
100
100
-
-
SH
t
-
-
SL
t
DSU
DHD
Data Hold Time
t
-
Fall Time (70% V
DD
to 20% V , C = 200pF)
DD
t
100
100
L
SCKF
Rise Time (20% V
to 70% V , C = 200pF)
t
-
DD
DD
L
SCKR
t
t
CLKH
CYC
t
R
t
F
CLK
t
CLKL
t
PWMO
t
PWMO
PWM
FIGURE 1. PWM TIMING
t
SCYC
CS
(INPUT)
t
t
ELD
ELG
t
SCKF
SCK
(INPUT)
t
SH
t
t
SL
SCKR
DATA
(INPUT)
MSB
LSB
t
DHD
t
DSU
FIGURE 2. SERIAL PERIPHERAL INTERFACE TIMING
3
CDP68HC68W1
CHIP SELECT
(CS)
CONTROL WORD
FREQUENCY WORD
MSB
7
LSB MSB
SERIAL CLK
(SCK)
6
5
4
3
2
1
0
7
6
5
4
3
CURVES
CONTINUED
IMMEDIATELY
BELOW
DATA
DON’T DON’T DON’T DON’T DON’T DON’T PWR CLOCK BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
CARE CARE CARE CARE CARE CARE COUNT DIVIDE = 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
CLK = 0
PWM-OUT = 0
(CS)
SCK
FREQUENCY WORD
PULSE WIDTH (PWM) WORD
LSB MSB
LSB
2
1
0
7
6
5
4
3
2
1
0
DATA
BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
= 1 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 1
CURVES
CONTINUED
BELOW
CLK
PWM-OUT
INPUT
CLOCK (CLK)
CLK
OUTPUT
(PWM)
PWM
OUT
TOTAL OUTPUT PERIOD =
5 X (INPUT CLOCK PERIOD)
FIGURE 3. CDP68HC68W1 INTERFACE TIMING SPECIFICATIONS (CONTINUED)
4
CDP68HC68W1
Introduction
Functional Description
The digital pulse width modular (DPWM) divides down a
clock signal supplied via the CLK input as specified by the
control, frequency, and pulse width data registers. The
resultant output signal, with altered frequency and duty
cycle, appears at the output of the device on the PWM pin.
Serial Port
Data are entered into the three DPWM registers serially
through the DATA pin, accompanied by a clock signal applied
to the SCK. The user can supply these serial data via shift
register(s) or a microcontroller’s serial port, such as the SPI
port available on most CDP68HC05 microcontrollers. Micro-
controller I/O lines can also be used to simulate a serial port.
Functional Pin Description
V
and V
SS
Data are written serially, most significant bit first, in 8, 16 or
24-bit increments. Data are sampled and shifted into the
PWMs shift register on each rising edge of the SCK. The
serial clock should remain low when inactive. Therefore,
when using a 68HC05 microcontroller’s SPI port to provide
data, program the microcontroller’s SPI control register bits
CPOL, CPHA to 0, 0.
DD
These pins are used to supply power and establish logic lev-
els within the PWM. V is a positive voltage with respect to
DD
V
(ground).
SS
CLK
The CLK pin is an input only pin where the clock signal to be
altered by the PWM circuitry is supplied. This is the source
of the PWM output. This input frequency can be internally
divided by either one or two, depending on the state of the
CD bit in the control register.
The CDP68HC68W1 latches data words after device
deselection. Therefore, CS must go high (inactive) following
each write to the W1.
Power-Up Initialization
CS
Upon V
DD
power up, the output of the PWM chip will remain
at a low level (logic zero) until:
The CS pin is the chip select input to the PWM’s SPI inter-
face. A high-to-low (1 to 0) transition selects the chip. A low-
to-high (0 to 1) transition deselects the chip and transfers
data from the shift registers to the data registers.
1. The chip is selected (CS pin pulled low).
2. 24-bit of information are shifted in.
3. The chip is deselected (CS pin pulled high).
VT
The 24-bits of necessary information pertain to the loading
of the PWM 8-bit registers, in the following order:
The VT pin is the input to the voltage threshold comparator
on the PWM. An analog voltage greater than 0.75V (at V
= 5V) on this pin will immediately cause the PWM output to
1. Control register
DD
2. Frequency register
3. Pulse width register
go to logic “0”. This will be the status until the V input is
T
returned to a voltage below 0.4V, the W1 is deselected, and
then one or more of the data registers is written to.
See section entitled Pulse Width Modulator Data Regis-
ters for a description of each register. Once initialized, the
specified PWM output signal will appear until the device is
An analog voltage on this pin less than 0.75V (at V
= 5V)
DD
will allow the device to operate as specified by the values in
the registers.
reprogrammed or the voltage on the V pin rises above the
T
specified threshold. Reprogramming the device will update
the PWM output after the end of the present output clock
period.
DATA
Data input at this pin is clocked into the shift register (i.e.,
latched) on the rising edge of the serial clock (SCK), most
significant bits first.
Reprogramming Shortcuts
After the device has been fully programmed upon power up,
it is only necessary to input 8 bits of information to alter the
output pulse width, or 16 bits to alter the output frequency.
SCK
The SCK pin is the serial clock input to the PWM’s SPI inter-
face. A rising edge on this pin will shift data available at the
(DATA) pin into the shift register.
Altering the Pulse Width: The pulse width may be
changed by selecting the chip, inputting 8 bits, and dese-
lecting the chip. By deselecting the chip, data from the first
8-bit shift register are latched into the pulse width register
(PWM register). The frequency and control registers
remain unchanged. The updated PWM information will
appear at the output only after the end of the previous total
output period.
PWM
This pin provides the resultant output frequency and pulse
width. After V
power up, the output on this pin will remain
DD
a logic “0”, until the chip is selected, 24 bits of information
clocked in, and the chip deselected.
Altering the Frequency: The frequency can be changed by
selecting the chip, inputting 16 bits (frequency information
followed by pulse width information), and deselected the
5
CDP68HC68W1
chip. Deselection will transfer 16 bits of data from the shift Byte 3: Pulse Width Data Register
register into the frequency register and PW register. The
7
6
5
4
3
2
1
0
updated frequency and PW information will appear at the
PWM output pin only after the end of the previous total
output period.
Pulse Width Data Register
B7-B0
This register contains the value that will
determine the pulse width or duty cycle (high
duration) of the output PWM waveform.
Altering the Control Word: Changing the clock divider
and/or power control bit in the CDPHC68W1 control register
requires full 24-bit programming, as described under Power
Up Initialization.
PW = (N+1) (CD+1)
Pulse Width Modulator Data Registers
PW = Pulse width out as measured in number of
input CLK periods.
Byte 1: Control Register
CD = Value of clock divider bit in control register.
N = Value in PW register.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PC
CD
For a case of n (binary value in PW register)
equal to 3 and CD (clock divider) = 0 (divide-by-
1), the output will be 4 input clock periods of a
high level followed by the remaining clocks of the
total period which will be a low level.
B7-B2
Unused; “don’t care”.
B2, PC
Power Control Bit. If this bit is a “0”, the chip will
remain in the active state. If the bit is set to a “1”,
internal clocking and the voltage comparator
(VT) circuit and voltage reference will be
disabled. Thus the chip will enter a low current
drain mode. The chip may only reenter the
active mode by clearing this bit and clocking in a
full 24 bits of information.
Assuming the frequency register contains a
value of 5, the resultant PWM output would be
high for 4 CLK periods, low for 2.
Using the CDP68HC68W1
B0, CD
Clock Divider Bit. If this bit is a “0”, the chip will
set internal clocking (CLK) at a divide-by-one
rate with respect to the (CLK). If this bit is set to
“1”, the internal clocking will be set to divide-by-2
state.
Programming the CDP68HC68W1
1. Select chip
2. Write to control register
3. Write to frequency register
4. Write to pulse width register
5. Deselect chip
Byte 2: Frequency Data Register
7
6
5
4
3
2
1
0
NEXT - TO then alter the pulse width
PWM Frequency Register
1. Select chip
2. Write to pulse width register*
3. Deselect chip
B7-B0
This register contains the value that will deter-
mine the output frequency or total period by:
OR - To then alter the frequency (and possibly PW):
F
IN
F
= ------------------------------------------
OUT
(N + 1)(CD + 1)
1. Select chip
2. Write to frequency register*
3. Write to pulse width register*
4. Deselect chip
F
F
= resultant PWM output frequency
OUT
= the frequency of input CLK
IN
NOTE: All writes use 8-bit words
n = value in frequency register
CD = value of clock divider bit in control register.
Example
when CD = 0,
For a case of n (binary value in frequency
register) equal to 5, CD (clock divider) = 0
(divide-by-1), the PWM output will be a fre-
quency 1/6 that of the input clock (CLK). Like-
wise, the output clock period will be equal to 6
input CLK periods.
When CD=0, frequency register = 4, pulse width register = 1;
output = high for 2 input CLK periods, low for 3;
1. Select chip
2. Then write (most significant bit first) to the control, the fre-
quency, and pulse width registers (control = 00, frequency =
04, PW = 1)
6
CDP68HC68W1
3. Deselect the chip
New pulse width out begins and PWM goes high when CS is
raised after last SCK pulse (assuming no previous time-out).
PWM then toggles on falling CLK edges.
INPCLK
(04 + 1)(0 + 1)
INPCLK
-----------------------
5
Frequency = ------------------------------------- =
Resulting output waveform: Control = 00 = Divide-by-1,
frequency = 4;
PW = 1: (1 + 1) (0 + 1) = 2 CLKs high time.
CDP68HC68W1 Application Example
The following example was written for a system which has and the Pulse Width Data Register. The frequency and pulse
the CDP68HC68W1 connected to the SPI bus of a width are then modified. Finally the pulse width is modified
CDP68HC05C8B microcontroller. The program sets the W1 without changing the frequency. The program was assem-
to run a divide by 200 frequency with a duty cycle of 30% by bled using the Intersil HASM 3.0 assembler.
writing to the Control Register, the Frequency Data Register,
INTERSIL Corporation (c)1990 - 1997
68HC05 Assembler Version 3.0.2
Filename:
Source Created: 01/08/98, 10:36 am
01/08/98, 10:36 am
***********************************************************************
W1.LST
Assembled:
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
* File:
*
*
*
W1.S
Example W1 routines - sets W1 to a divide by
200 output with 30% duty cycle
* Date:
Thursday, January 8, 1998
***********************************************************************
***********************************************************************
*
***********************************************************************
Partial Map of CDP68HC05C8B Hardware Registers
0000
0000
0001
0002
0003
0004
0005
0006
0007
000A
Section Registers, $0000
PortA
PortB
PortC
PortD
DDRA
DDRB
DDRC
_Free1 ds
SPCR
SPE
ds
ds
ds
ds
ds
ds
ds
1
1
1
1
1
1
1
3
1
6
4
1
7
1
;Port A
;Port B
;Port C
;Port D
;Port A Data Direction Register
;Port B DDR
;Port C DDR
;three unused locations
;SPI Control Register
;SPI Enable bit
;SPI Master Mode bit
;SPI Status Register
;SPI Flag bit for ANDs, CMPs, etc.
;SPI Data Register
ds
00023 $0006 =
00024 $0004 =
00025
00026 $0007 =
00027
6
4
equ
equ
ds
equ
ds
MSTR
SPSR
SPIF
SPDR
000B
7
000C
00028
00029
00030
00031
***********************************************************************
CDP68HC68W1 Constants
***********************************************************************
*
00032
00033 $0000 =
00034 $0002 =
00035 $0001 =
00036
0
2
1
W1
W1_PC
W1_CD
equ
equ
equ
0
2
1
;W1 is connected to bit 0 of Port A
;Power Control: 1 = power down
;Clock Divider: 1 = divide by 2
00037
00038
00039
***********************************************************************
* Main Routines
00040
***********************************************************************
00041
00042
00043
0100
Section Code, $0100
00044* [6] 0100 AD37
00045
jsr
Set200_30
Init_W1
;turn on PA0
00046 [5] 0102 1100
00047* [6] 0104 AD28
00048
bclr
jsr
W1,PortA
Set_SPI_Mode
;select W1 (CE is active low)
;Setup the 68HC05 SPI control
;to talk to the W1
00049
00050
******* Set Up Control, Frequency, and Pulse Width
00051
00052
SendCommands
00053 [2] 0106 A601
lda
#W1_CD
;set divide by two clock on W1
7
CDP68HC68W1
00054* [6] 0108 AD29
00055 [2] 010A A663
00056* [6] 010C AD25
00057 [2] 010E A61D
jsr
lda
jsr
lda
jsr
SPI_xmit
#99
SPI_xmit
#29
SPI_xmit
;set frequency to divide by 2000
;set pulse width to 30% duty cycle
00058* [6] 0110 AD21
00059
00060
DeselectW1_1
bset
00061 [5] 0112 1000
W1,PortA
;deselect the W1 which loads registers
; with values transmitted
00062
00063
00064
00065
00066
00067
;
;
;
;
Here the CDP68HC05C8B would generally
attend to other processing issues
00068
00069
******* Modify Frequency and Pulse Width
00070
00071 [5] 0114 1100
00072* [6] 0116 AD16
00073
bclr
jsr
W1,PortA
Set_SPI_Mode
;select W1 (CE is active low)
;Setup the CDP68HC05 SPI Control....
;to talk to the W1
00074
SendCommands2
00075 [2] 0118 A631
00076* [6] 011A AD17
00077 [2] 011C A609
00078* [6] 011E AD13
lda
jsr
lda
jsr
#49
SPI_xmit
#9
;set frequency to divide by 100 (the
;divide by 2 is still in effect)
;set pulse width to 20% duty cycle
SPI_xmit
00079
00080
DeselectW1_2
bset
00081 [5] 0120 1000
W1,PortA
;deselect the W1 which loads registers
00082
00083
;
00084
00085
00086
;
;
;
Here the CDP68HC05C8B would again
attend to other processing issues
00087
00088
******* Modify Pulse Width
00089
00090 [5] 0122 1100
00091* [6] 0124 AD08
00092
bclr
jsr
W1,PortA
Set_SPI_Mode
;select W1 (CE is active low)
;Setup the 68HC05 SPI control...
;to talk to the W1
00093
SendCommands3
00094 [2] 0126 A611
00095* [6] 0128 AD09
lda
jsr
#17
SPI_xmit
;set pulse width to 38% duty cycle
00096
00097
DeselectW1_3
bset
00098 [5] 012A 1000
W1,PortA
*
;deselect the W1 which loads registers
;with values transmitted
00099
00100
Finish
bra
00101 [3] 012C 20FE
;loop forever
00102
00103
00104
00105
00106
***********************************************************************
Common Subroutines
***********************************************************************
*
00107
00108
00109
012E
Section Subroutines, *
Set_SPI_Mode
00110 [2] 012E A650
00111 [4] 0130 B70A
00112 [6] 0132 81
00113
lda
sta
rts
#(2!SPE+2!MSTR) ;Enable SPI as a Master with....
SPCR
;CPHA=CPOL=0,
SPI_Xmit
00114 [4] 0133 B70C
00115
sta
SPI_wait
SPDR
;send A to SPI device
00116 [5] 0135 0F0BFD
00117 [6] 0138 81
00118
brclr
rts
SPIF,SPSR,SPI_wait
;wait until transmit complete
00119
Init_W1
00120 [5] 0139 1000
00121 [5] 013B 1004
bset
bset
W1,PortA
W1,DDRA
;disable the W1 (CE is active low)
;by activating PA0 as a high
8
CDP68HC68W1
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A1
A
D1
e
D
5
C
eC
B
eB
D1
E
5
0.010 (0.25)
C
B
S
M
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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