CDP68HCL05C16BN [RENESAS]

IC,MICROCONTROLLER,8-BIT,6805 CPU,CMOS,LDCC,44PIN,PLASTIC;
CDP68HCL05C16BN
型号: CDP68HCL05C16BN
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

IC,MICROCONTROLLER,8-BIT,6805 CPU,CMOS,LDCC,44PIN,PLASTIC

时钟 微控制器 外围集成电路
文件: 总67页 (文件大小:347K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CDP68HC05C16B,  
CDP68HCL05C16B,  
CDP68HSC05C16B  
S E M I C O N D U C T O R  
June 1997  
8-Bit Enhanced Microcontroller Series  
Features  
Description  
HARDWARE  
The CDP68HC05C16B HCMOS Microcomputer is a new  
member of the CDP68HC05 family of low-cost single chip  
microcomputers. It is an enhanced version of the  
CDP68HC05C8B. Enhancements include a larger RAM and  
ROM sizes (352 bytes of RAM, 15,936 bytes of ROM), key-  
board scanning logic, a high current output pin, an advanced  
watchdog (COP) timer, a low power oscillator that can "wake  
up" the CPU from STOP mode and fixed tone outputs. This  
8-bit microcomputer unit (MCU) also contains an on-chip  
oscillator, CPU, 31 bidirectional I/O pins, two serial interface  
systems, and 16 bit capture/compare timer. The fully static  
design allows operation at frequencies down to DC, further  
reducing its already low-power consumption.  
• 8-Bit HCMOS Microcontroller  
• Extended Version of MC68HC05C9A Family  
- Pin for Pin Compatible  
• Power-Saving Stop, Wait and Data Retention Modes  
• Fully Static Operation  
• On-Chip Memory  
- 352 Bytes RAM  
- 15,936 Bytes ROM  
• Keyboard Scanning Logic  
• Watchdog Timer (COP) and Clock Monitor  
• Low Power Wake Up Oscillator  
• 31 Bidirectional I/O Lines  
The CDP68HCL05C16B MCU is a low-power version of the  
CDP68HC05C16B. It contains all the features of the  
CDP68HC05C16B with additional features of lower power  
consumption in the RUN, WAIT and STOP modes; and low  
voltage operation down to 2.4V.  
- 1 High Current Output for LED Drive (PC7)  
• Bidirectional RESET pin  
• Internal 16-Bit Timer  
• Serial Communications Interface (SCI) System  
• Serial Peripheral Interface (SPI) System  
The CDP68HSC05C16B MCU is a high-speed version of  
the CDP68HC05C16B. It also contains all the features of  
the CDP68HC05C16B with the additional capability of  
higher frequency operation at 8.0MHz.  
• Fixed Frequency Tone/Simple PWM Outputs (Mask  
Programmable)  
• Self-Check Mode  
Table Of Contents  
• External, Timer, SCI, and SPI Interrupts  
• Master Reset and Power-On Reset  
• On-Chip Oscillator with RC or Crystal Mask Options  
• CDP68HC05C16B  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4  
Characterization Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Electrical and Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 6  
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Software Programmable Options . . . . . . . . . . . . . . . . . . . . . . . 28  
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Resets, Interrupts and Low Power Modes . . . . . . . . . . . . . . . . 32  
Hardware/Power-On Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
COP/Clock Monitor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
Wake Up Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Serial Communications Interface (SCI). . . . . . . . . . . . . . . . . . . 44  
Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . 51  
Port A Tone and Simple PWM Circuitry . . . . . . . . . . . . . . . . . . 57  
Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . 57  
Package Outline Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
I/O, Control, Status and Data Register Definitions. . . . . . . . . . 66  
Ordering Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
- 4.2MHz Oscillator (2.1MHz Internal Bus Frequency)  
at 5V; 2.0MHz (1.0MHz Internal Bus) at 3.0V  
- Single 3.0V to 6.0V Supply (1.5V Data Retention  
Mode)  
• CDP68HCL05C16B  
- Lower Supply Current, I  
DD  
Modes at 5.5V, 2.5V and 1.8V  
- Single 1.8V to 6.0V Supply (1.5V Data Retention Mode)  
• CDP68HSC05C16B  
in RUN, WAIT and STOP  
- 8.0MHz Oscillator (4.0MHz Internal Bus Frequency)  
- Single 2.4V to 6.0V Supply (1.5V Data Retention Mode)  
SOFTWARE  
• Complete 68HC05 Instruction Set  
• Efficient Use of Program Space  
• Memory Mapped I/O  
• Versatile Interrupt Handling  
• True Bit Manipulation  
• Addressing Modes with Indexed Addressing for  
Accessing Tables  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 4249  
Copyright © Harris Corporation 1997  
1
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Data Format Options  
Ordering Information  
The ROM data can be submitted in various formats. The fol-  
lowing list summarizes the principal formats which Harris will  
accept. The list is in order of preference, with S-Record for-  
matted data files being the preferred format.  
PART NUMBER  
CDP68HC05C16BE  
CDP68HC05C16BN  
CDP68HC05C16BQ  
CDP68HC05C16BSE  
CDP68HC05C16BD  
CDP68HC05C16BH  
CDP68HCL05C16BE  
CDP68HCL05C16BN  
CDP68HCL05C16BQ  
CDP68HCL05C16BSE  
CDP68HCL05C16BD  
CDP68HCL05C16BH  
CDP68HSC05C16BE  
CDP68HSC05C16BN  
CDP68HSC05C16BQ  
CDP68HSC05C16BSE  
CDP68HSC05C16BD  
CDP68HSC05C16BH  
PACKAGE  
PKG. NO.  
E40.6  
40 Ld PDIP  
44 Ld PLCC  
44 Ld MQFP  
42 Ld SPDIP  
40 Ld SBDIP  
Chip  
N44.65  
Q44.10x10  
E42.6C  
D40.6  
• S-Record Formatted Hex Data File via modem upload  
• S-Record Formatted Hex Data File on floppy disk  
• S-Record Formatted Hex Data File via e-mail  
• 6805 Assembly Language Source File on floppy disk  
• Contents of a 27XX type EPROM/EEPROM  
Regardless of the medium used to transfer the data, con-  
tents of all of the User ROM regions of the memory map of  
the particular microcontroller should be specified. This  
includes any Page 0 User ROM and User Reset/Interrupt  
Vectors. Data should not be specified for the Self Check  
ROM space of a device. All unused locations should either  
not be specified (S-Record and source files) or specified as  
$00 (EPROM/EEPROM).  
40 Ld PDIP  
44 Ld PLCC  
44 Ld MQFP  
42 Ld SPDIP  
40 Ld SBDIP  
Chip  
E40.6  
N44.65  
Q44.10x10  
E42.6C  
D40.6  
Procedure for Submitting Data  
When submitting data via a physical medium such as a  
floppy disk or EPROM, the “Ordering Information Sheet” at  
the end of this document must be completed and submitted  
with the data.  
40 Ld PDIP  
44 Ld PLCC  
44 Ld MQFP  
42 Ld SPDIP  
40 Ld SBDIP  
Chip  
E40.6  
N44.65  
Q44.10x10  
E42.6C  
D40.6  
When utilizing the Harris Customer Pattern Retrieval System  
(modem upload) the customer will be prompted for the same  
information as that specified on the “Ordering Information  
Sheet”.  
If the data is submitted via e-mail, the message should  
include the same information as that specified on the “Order-  
ing Information Sheet”.  
NOTE: Pin number references throughout this specification refer to  
the 40 lead DIP. See pinouts for cross reference.  
Harris Customer Pattern Retrieval System  
ROM Ordering Information  
To access the Harris Customer Pattern Retrieval System,  
you must first obtain an account ID and password from your  
Harris sales representative. The system is accessed by dial-  
ing 1-908-685-6541. It is presently set to run with baud rates  
up to 2400 baud, with 8 data bits, 1 stop bit, and no parity bit.  
The data transfer is done using text mode Kermit transfers.  
The CDP68HC05C16B family of microcontrollers contains  
mask programmed ROMs. The contents of these ROMs are  
personalized to meet a customer’s code requirements during  
manufacturing of the ICs. The code is programmed via pho-  
tomasking techniques. Semiconductor manufacturing is a  
batch process, and all microcontrollers manufactured in a  
given lot (a batch) will contain identical ROM code.  
Check the Harris Corporate internet site, www.harris.com,  
for the latest information on the Harris Customer Pattern  
Retrieval System.  
Harris generates a customer’s ROM mask from an ASCII  
representation of the desired ROM contents together with  
other specific information. The following pages contain  
sheets which can be used to provide the required informa-  
tion when ordering a masked ROM microcontroller.  
2
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Standard Pinouts  
CDP68HC05C16B, CDP68HCL05C16B  
CDP68HC05C16B, CDP68HCL05C16B  
CDP68HSC05C16B  
(PLCC)  
CDP68HSC05C16B  
(SBDIP, PDIP)  
TOP VIEW  
TOP VIEW  
RESET  
IRQ  
1
2
3
4
5
6
7
8
9
40 V  
DD  
39 OSC1  
38 OSC2  
37 TCAP  
36 PD7  
NC  
6
5
4
3
2
1 44 43 42 41 40  
PA7  
PA6  
PA5  
PA4  
PA3  
PA2  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
PA5  
PA4  
PA3  
PA2  
PA1  
PA0  
PB0  
PB1  
PB2  
PB3  
NC  
NC  
8
TCMP  
9
PD5/SS  
PD4/SCK  
PD3/MOSI  
PD2/MISO  
PD1/TDO  
PD0/RDI  
PC0  
35 TCMP  
34 PD5/SS  
33 PD4/SCK  
32 PD3/MOSI  
31 PD2/MISO  
30 PD1/TDO  
29 PD0/RDI  
28 PC0  
10  
11  
12  
13  
14  
15  
16  
17  
PA1 10  
PA0 11  
PB0 12  
PB1 13  
PB2 14  
PB3 15  
PB4 16  
PB5 17  
PB6 18  
PB7 19  
PC1  
PC2  
18 19  
27 28  
20 21 22 23 24 25 26  
27 PC1  
26 PC2  
25 PC3  
24 PC4  
Note: For compatibility with CDP68HC05C4B/C8B  
devices in 44-pin PLCC, tie pins 17 and 18  
together and tie pins 39 and 40 together.  
23 PC5  
22 PC6  
V
20  
21 PC7  
SS  
CDP68HC05C16B, CDP68HCL05C16B  
CDP68HSC05C16B  
(SPDIP)  
CDP68HC05C16B, CDP68HCL05C16B  
CDP68HSC05C16B  
(MQFP)  
TOP VIEW  
TOP VIEW  
RESET  
IRQ  
1
2
3
4
5
6
7
8
9
42 V  
DD  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
OSC1  
OSC2  
TCAP  
PD7  
NC  
PA7  
PA6  
PA5  
PA4  
PA3  
PA2  
44 43 42 41 40 39 38 37 36 35 34  
1
2
3
4
5
6
7
8
9
TCMP  
PA6  
PA5  
PA4  
PA3  
PA2  
PA1  
PA0  
PB0  
PB1  
PB2  
PB3  
33  
32  
31  
30  
29  
PD5/SS  
PD4/SCK  
PD3/MOSI  
PD2/MISO  
PD1/TDO  
PD0/RDI  
PC0  
TCMP  
PD5/SS  
PD4/SCK  
PD3/MOSI  
PD2/MISO  
PD1/TDO  
PD0/RDI  
PC0  
28  
27  
26  
25  
24  
23  
PA1 10  
PA0 11  
PB0 12  
PB1 13  
PB2 14  
PB3 15  
NC 16  
PC1  
10  
11  
PC2  
PC3  
PC1  
12 13 14 15 16 17 18 19 20 21 22  
PC2  
NC  
PC3  
17  
18  
19  
20  
21  
PB4  
PB5  
PB6  
PB7  
PC4  
PC5  
PC6  
PC7  
V
SS  
3
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Microcomputer Block Diagram  
OSC1  
39  
OSC2  
38  
35  
COP SYSTEM  
CLOCK MONITOR  
WAKE UP OSCILLATOR  
16 BIT  
TIMER SYSTEM  
TCMP  
TCAP  
OSCILLATOR  
37  
÷ 2  
INTERNAL  
PROCESSOR  
CLOCK  
1
2
RESET  
IRQ  
TONE GEN  
11  
10  
9
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
PA7  
BAUD RATE  
GENERATOR  
ACCUMULATOR  
29  
8
8
8
5
6
6
A
X
PORT A  
I/O  
LINES  
CPU  
CONTROL  
PD0 (RDI)  
SCI  
30  
7
PD1 (TDO)  
INDEX  
REGISTER  
6
31  
32  
PD2 (MISO)  
PD3 (MOSI)  
PD4 (SCK)  
PD5 (SS)  
5
CONDITION CODE  
REGISTER  
4
SPI  
CC  
S
33  
CPU  
34  
STACK  
POINTER  
12  
13  
14  
15  
16  
17  
18  
19  
PB0  
PB1  
PB2  
PB3  
PB4  
PB5  
PB6  
PB7  
36  
PROGRAM COUNTER  
PD7  
HIGH  
PCH  
ALU  
PORT B  
I/O  
LINES  
PROGRAM  
COUNTER LOW PCL  
28  
27  
26  
25  
8
PC0  
PC1  
PC2  
PORT C  
I/O  
LINES  
DATA  
DIR  
PORT  
C
15,936 x 8 ROM  
352 x 8  
STATIC RAM  
PC3  
PC4  
PC5  
PC6  
PC7  
24  
23  
22  
21  
REG  
REG  
240 x 8  
SELF-CHECK  
ROM  
Power Considerations  
o
The average chip-junction temperature, T , in C can be  
J
obtained from:  
PINS  
R
R
C
1
2
V
= 4.5V  
DD  
T = T + (P • θ )  
JA  
(EQ. 1)  
J
A
D
PA0-7, PB0-7, PC0-7, PD7  
PD0-5  
3.26k  
1.9kΩ  
2.38kΩ  
2.26kΩ  
50pF  
o
Where:  
T
= Ambient Temperature, C  
A
θ
= Package Thermal Resistance,  
Junction-to-Ambient, C/W  
200pF  
JA  
o
V
= 3.0V  
DD  
P
= P  
+ P  
D
INT  
I/O  
P
P
= I  
CC  
x V , Watts - Chip Internal Power  
CC  
INT  
I/O  
PA0-7, PB0-7, PC0-7, PD7  
PD0-5  
10.19k6.32kΩ  
50pF  
= Power Dissipation on Input and Output  
Pins - User Determined  
6kΩ  
6kΩ  
200pF  
For most applications P << P  
I/O  
and can be neglected.  
INT  
An approximate relationship between P and T (if P is  
I/O  
D
J
V
DD  
neglected) is:  
o
P
= K ÷ (T + 273 C)  
(EQ. 2)  
D
J
R
2
1
Solving Equation 1 and Equation 2 for K gives:  
TEST  
POINT  
o
K = P • (T + 273 C) + θ • P 2  
(EQ. 3)  
R
C
D
A
JA  
D
Where K is a constant pertaining to the particular part. K can  
be determined from Equation 3 by measuring P (at equilib-  
D
rium) for a known T . Using this value of K the values of P  
A
D
EQUIVALENT TEST LOAD  
and T can be obtained by solving Equation 1 and Equation 2  
J
iteratively for any value of T .  
A
4
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
120.0  
V
= 5.0V  
V
= 2.0V  
-5.0  
DD  
DD  
100.0  
80.0  
60.0  
40.0  
20.0  
V
= 4.5V  
DD  
-10.0  
-15.0  
-20.0  
-25.0  
-30.0  
V
= 3.3V  
DD  
V
= 3.3V  
DD  
V
= 4.5V  
V
= 2.0V  
3.0  
DD  
DD  
V
= 5.0V  
DD  
0
1.0  
2.0  
4.0  
5.0  
6.0  
0
-6.0  
-5.0  
-4.0  
-3.0  
-2.0  
-1.0  
(V)  
DD  
V
, OUTPUT VOLTAGE (V)  
V
, OUTPUT VOLTAGE REFERENCED TO V  
O
O
FIGURE 1B. TYPICAL PC7 PORT OUTPUT N-CHANNEL SINK  
FIGURE 1A. TYPICAL PC7 PORT OUTPUT P-CHANNEL SOURCE  
o
CURRENT FOR V  
= 2V, 3.3V, 4.5V AND 5V AT  
CURRENT FOR V = 2V, 3.3V, 4.5V AND 5V AT 25 C  
DD  
DD  
o
25 C  
30.0  
25.0  
20.0  
15.0  
10.0  
5.0  
V
= 2.0V  
DD  
V
= 5.0V  
-2.0  
DD  
V
= 4.5V  
V
= 3.3V  
DD  
DD  
-4.0  
-6.0  
V
= 4.5V  
DD  
-8.0  
V
= 3.3V  
DD  
V
= 5.0V  
DD  
-10.0  
-12.0  
V
= 2.0V  
3.0  
DD  
0
1.0  
2.0  
4.0  
5.0  
6.0  
0
-6.0  
-5.0  
-4.0  
-3.0  
-2.0  
-1.0  
V
, OUTPUT VOLTAGE (V)  
O
V
, OUTPUT VOLTAGE REFERENCED TO V  
(V)  
DD  
O
FIGURE 1D. TYPICAL PORT OUTPUT N-CHANNEL SINK  
FIGURE 1C. TYPICAL PORT OUTPUT P-CHANNEL SOURCE  
CURRENT FOR V  
= 2V, 3.3V, 4.5V AND 5V AT  
DD  
CURRENT FOR V  
= 2V, 3.3V, 4.5V AND 5V AT  
DD  
o
o
25 C  
25 C  
12.0  
10.0  
8.0  
20.0  
16.0  
12.0  
8.0  
o
V
= 2V, T = 25 C  
DD  
6.0  
4.0  
4.0  
2.0  
2.0  
o
V
= 5V, T = 25 C  
DD  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
0
4
8
12  
16  
20  
V
, OPERATING VOLTAGE (V)  
f
, CRYSTAL OSCILLATOR FREQUENCY (MHz)  
DD  
osc  
FIGURE 1E. TYPICAL CRYSTAL OSCILLATOR OPERATING  
FIGURE 1F. TYPICAL SUPPLY CURRENT vs OPERATING  
o
FREQUENCIES vs OPERATING VOLTAGE, V  
AT  
FREQUENCY AT 25 C  
DD  
o
25 C  
5
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Absolute Maximum Ratings  
Thermal Information  
o
o
Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Thermal Resistance (Typical, Note 1)  
DD  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
Input Voltage, V . . . . . . . . . . . . . . . . . . . V - 0.3V to V  
+ 0.3V  
+ 0.3V  
SPDIP Package. . . . . . . . . . . . . . . . . .  
PDIP Package . . . . . . . . . . . . . . . . . . .  
PLCC Package . . . . . . . . . . . . . . . . . .  
MQFP Package . . . . . . . . . . . . . . . . . .  
SBDIP Package. . . . . . . . . . . . . . . . . .  
55  
55  
45  
70  
60  
N/A  
N/A  
N/A  
N/A  
IN SS  
DD  
Self-Check Mode (IRQ Pin Only), V . V - 0.3V to 2 x V  
IN  
SS  
DD  
Current Drain Per Pin Excluding V  
and V , I. . . . . . . . . . 25mA  
DD  
SS  
Operating Conditions  
18  
o
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175 C  
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V  
o
o
o
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to 125 C  
o
o
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
CDP68HC05C16B . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
o
o
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C  
CDP68HCL05C16B . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C  
o
o
(PLCC, MQFP - Lead Tips Only)  
CDP68HSC05C16B . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C  
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
DC Electrical Specifications HC Product Type  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
o
o
CDP68HC05C16B V  
= 5V ±10%, V = 0V, T = -40 C to 85 C (Note 2)  
DD  
SS  
A
Output Voltage  
V
I
< 10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD7, PD0  
V
I
I
I
= -0.8mA  
= -1.6mA  
= -5.0mA  
V
V
V
- 0.8  
- 0.8  
- 0.8  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
V
I
I
= 1.6mA  
-
-
-
0.4  
0.4  
V
V
V
OL  
LOAD  
PC7  
V
= 10.0mA  
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-  
5, PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
o
o
Data Retention Mode  
V
T = 0 C to 70 C  
A
1.5  
-
-
-
-
V
RM  
o
Wake Up Timer Oscillator Frequency  
f
T
= 25 C  
13  
kHz  
RCO  
A
Supply Current (f  
Run (Note 6)  
= 4.2MHz)  
OSC  
I
I
I
-
3.5  
1.0  
1.0  
2.0  
7.0  
10.0  
-
5.25  
3.25  
20  
mA  
mA  
µA  
µA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 5, 6, 7, 9)  
STOP (Notes 7, 8)  
-
o
T
T
T
T
= 25 C  
-
A
A
A
A
o
o
= 0 C to 70 C  
-
-
40  
o
o
= -40 C to 85 C  
50  
o
STOP with Wake Up Timer Enabled  
I
= 25 C  
-
-
DD  
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without Pullups), PC0-7, PD0-5, PD7  
I
-10  
+10  
IL  
Pullup Current PB0-7 (with Pullups, Note 10)  
Input Current, IRQ, TCAP, OSC1  
I
60  
-1  
-
140  
300  
+1  
12  
8
µA  
µA  
pF  
pF  
IN  
I
-
-
-
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
OUT  
C
-
IN  
6
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications  
HC Product Type (Continued)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
o
o
CDP68HC05C16B V  
= 3.3V ±10%, V = 0V, T = -40 C to 85 C  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.2mA  
= -0.4mA  
= -1.5mA  
V
V
V
- 0.3  
- 0.3  
- 0.3  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, TCMP, PD7  
V
I
I
= 0.4mA  
= 6.0mA  
-
-
-
0.3  
0.3  
V
V
V
OL  
LOAD  
PC7  
V
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-  
5, PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
o
o
Data Retention Mode  
V
T = 0 C to 70 C  
A
1.5  
-
-
-
-
V
RM  
o
Wake Up Timer Oscillator Frequency  
f
T
= 25 C  
13  
kHz  
RCO  
A
Supply Current (f  
Run (Note 6)  
= 2.0MHz)  
OSC  
I
I
I
-
1
1.6  
0.9  
8
mA  
mA  
µA  
µA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 5, 6, 7, 9)  
STOP (Notes 7, 9)  
-
0.5  
o
T = 25 C  
A
-
1
o
o
T = 0 C to 70 C  
-
-
-
16  
20  
-
A
o
o
T = -40 C to 85 C  
A
-
10.0  
-
o
STOP with Wake Up Timer Enabled  
I
T
= 25 C  
-
DD  
A
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without Pullups), PC0-7, PD0-5, PD7  
I
-10  
+10  
IL  
Pullup Current PB0-7 (with Pullups, Note 10)  
Input Current - IRQ, TCAP, OSC1  
I
25  
-1  
-
65  
-
140  
+1  
12  
8
µA  
µA  
pF  
pF  
IN  
I
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
-
OUT  
C
-
-
IN  
NOTES:  
2. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that  
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For  
proper operation it is recommended that V and V  
be constrained to the range V <(V or V  
)<V . Reliability of operation is  
IN OUT  
SS IN OUT  
DD  
enhanced if unused inputs except OSC2 are connected to an appropriate logic voltage level (e.g., either V or V ).  
SS DD  
3. All values shown reflect average measurement.  
o
4. Typical values at midpoint of voltage range, 25 C only.  
5. Wait I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.  
DD  
6. Run (Operating) I , Wait I : Measured using external square-wave clock source, all inputs 0.2V from rail, no DC loads, less than 50pF  
DD DD  
on all outputs, C = 20pF on OSC2.  
L
7. Wait, Stop I : All ports configured as inputs, V = 0.2V, V = V -0.2V.  
DD  
DD  
IL  
IH  
8. Stop I  
9. Wait I  
measured with OSC1 = V  
.
DD  
DD  
SS  
is affected linearly by the OSC2 capacitance.  
10. Input pullup current measured with V = 0.2V.  
IL  
7
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Control Timing HC Product Type  
PARAMETER  
= 5V ±10%, V = 0V, T = -40 C to 85 C  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HC05C16B V  
DD  
SS  
A
Frequency Of Operation  
Crystal Option  
f
f
-
4.2  
4.2  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
+ 2)  
External Clock (f  
f
f
-
DC  
480  
-
2.1  
2.1  
-
MHz  
MHz  
ns  
OSC  
OP  
OP  
+ 2)  
OSC  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
t
RL  
CYC  
Timer  
Resolution (Note 12)  
t
4
125  
-
-
-
-
-
-
RES  
CYC  
ns  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
, t  
TH TL  
t
(Note 13)  
125  
t
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 11)  
90  
t
ILIL  
, t  
CYC  
ns  
t
OH OL  
o
o
CDP68HC05C16B V  
= 3.3V ±10%, V = 0V, T = -40 C to 85 C  
SS  
DD  
A
Frequency Of Operation  
Crystal Option  
f
f
-
2.0  
2.0  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
+ 2)  
External Clock (f  
f
f
-
DC  
1000  
-
1.0  
1.0  
-
MHz  
MHz  
ns  
OSC  
OP  
OP  
+ 2)  
OSC  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
t
RL  
CYC  
Timer  
Resolution (Note 12)  
t
4
-
-
-
-
-
-
RES  
CYC  
ns  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
, t  
250  
TH TL  
t
(Note 13)  
250  
t
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 11)  
200  
t
ILIL  
, t  
CYC  
ns  
t
OH OL  
NOTES:  
11. The minimum period t  
ILIL  
should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t .  
CYC  
12. Since a 2-bit prescaler in the timer must count four internal cycles (t  
), this is the limiting minimum factor in determining the timer resolution.  
should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24  
CYC  
13. The minimum period t  
TLTL  
t
.
CYC  
8
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HC Product Type  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HC05C16B V  
= 5V ±10%, V = 0V, T = -40 C to 85 C Unless Otherwise Specified  
DD  
SS  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
2.1  
f
(Note 16)  
MHz  
OP(M)  
OP  
Slave  
f
OP(S)  
1
2
3
4
5
6
7
Cycle Time  
Master  
t
2.0  
-
-
t
CYC(M)  
CYC  
ns  
Slave  
t
480  
CYC(S)  
Enable Lead Time  
Master  
t
(Note 14)  
240  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 14)  
720  
-
-
-
LAG(M)  
Slave  
t
ns  
LAG(S)  
Clock (SCK) High Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
Data Setup Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
Data Hold Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
8
9
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
120  
240  
ns  
ns  
A
Disable Time (Hold Time to High Impedance State)  
Slave  
t
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
t
V(M)  
CYC(M)  
Slave (After Enable Edge) (Note 15)  
t
240  
ns  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
DD  
= 20% to 70%, C = 200pF)  
L
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
r(S)  
Fall Time (V  
DD  
= 20% to 70%, C = 200pF)  
L
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
f(S)  
o
o
CDP68HC05C16B V  
= 3.3V ±10%, V = 0V, T = -40 C to 85 C Unless Otherwise Specified  
SS  
DD  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
1.0  
f
OP  
(Note 16)  
OP(M)  
Slave  
f
OP(S)  
MHz  
9
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HC Product Type (Continued)  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
1
Cycle Time  
Master  
t
2.0  
1.0  
-
-
t
CYC  
CYC(M)  
Slave  
t
µs  
CYC(S)  
2
3
4
5
6
7
Enable Lead Time  
Master  
t
(Note 14)  
500  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 14)  
1.5  
-
-
-
LAG(M)  
Slave  
t
µs  
LAG(S)  
Clock (SCK) High Time  
Master  
t
720  
400  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
720  
400  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
Data Setup Time (Inputs)  
Master  
t
200  
200  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
Data Hold Time (Inputs)  
Master  
t
200  
200  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
8
9
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
250  
500  
ns  
ns  
A
Disable Time (Hold Time to High Impedance State)  
Slave  
t
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
t
V(M)  
CYC(M)  
Slave (After Enable Edge) (Note 15)  
t
500  
ns  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
DD  
= 20% to 70%, C = 200pF)  
L
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
200  
2.0  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
r(S)  
Fall Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
200  
2.0  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
f(S)  
NOTES:  
14. Signal Production depends on software.  
15. Assumes 200pF load on all SPI leads.  
16. Note that the units this specification uses is f  
(internal operating frequency), not MHz! In the master mode the SPI bus is capable of  
OP  
running at one-half of the devices’s internal operating frequency, therefore 5V: 1.05MHz and 3.3V: 0.05MHz maximum.  
10  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications HCL Product Type  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
o
o
CDP68HCL05C16B V  
= 5V ±10%, V = 0V, T = 0 C to 70 C (Note 17)  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.8mA  
= -1.6mA  
= -5.0mA  
V
V
V
- 0.8  
- 0.8  
- 0.8  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
V
I
I
= 1.6mA  
-
-
-
0.4  
0.4  
V
V
V
OL  
LOAD  
PC7  
V
= 10.0mA  
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
o
o
Data Retention Mode  
V
T
T
= 0 C to 70 C  
1.5  
-
-
-
-
V
RM  
A
A
o
Wake Up Timer Oscillator Frequency  
f
= 25 C  
13  
kHz  
RCO  
Supply Current (f  
OSC  
= 4.2MHz)  
Run (Note 20)  
I
I
I
-
3.5  
1.6  
1
4.25  
2.25  
15  
mA  
mA  
µA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 19, 20, 21, 23)  
STOP (Notes 21, 22)  
-
o
T
T
T
= 25 C  
-
-
A
A
A
o
o
= 0 C to 70 C  
-
25  
o
STOP with Wake Up Timer Enabled  
I
= 25 C  
-
10.0  
-
-
DD  
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without pullups), PC0-7, PD0-5, PD7  
I
-10  
+10  
IL  
Pullup Current PB0-7 (with pullups, Note 24)  
Input Current - IRQ, TCAP, OSC1  
I
60  
-1  
140  
-
300  
+1  
µA  
µA  
IN  
I
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
-
-
-
-
12  
8
pF  
pF  
OUT  
C
IN  
o
o
CDP68HCL05C16B V  
= 2.5V - 3.6V, V = 0V, T = 0 C to 70 C  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.2mA  
= -0.4mA  
= -1.5mA  
V
V
V
- 0.3  
- 0.3  
- 0.3  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
11  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications HCL Product Type (Continued)  
PARAMETER  
Output Low Voltage  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
PC7  
V
V
I
I
= 0.4mA  
= 5.0mA  
-
-
-
-
0.3  
0.3  
V
V
V
OL  
LOAD  
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
V
DD  
IH  
DD  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
o
o
Data Retention Mode  
V
T
T
= 0 C to 70 C  
1.5  
-
-
-
-
V
RM  
A
A
o
Wake Up Timer Oscillator Frequency  
f
= 25 C  
13  
kHz  
RCO  
Supply Current (f  
OSC  
= 2MHz)  
Run (Note 20)  
I
I
I
-
-
-
-
-
1.0  
0.7  
1.0  
-
1.4  
1.0  
5.0  
10  
-
mA  
mA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 19, 20, 21, 23)  
STOP (Notes 21, 22)  
o
T
T
T
= 25 C  
A
A
A
o
o
= 0 C to 70 C  
o
STOP with Wake Up Timer Enabled  
I
= 25 C  
10.0  
DD  
Supply Current (f  
OSC  
= 1MHz)  
Run (Note 20)  
I
I
I
-
500  
300  
1.0  
-
750  
500  
5.0  
10  
µA  
µA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 19, 20, 21, 23)  
STOP (Notes 21, 22)  
-
-
o
T
T
= 25 C  
A
A
o
o
= 0 C to 70 C  
-
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without Pullups), PC0-7, PD0-5, PD7  
I
-10  
-
+10  
IL  
Pullup Current PB0-7 (with Pullups, Note 24)  
Input Current - IRQ, TCAP, OSC1  
I
20  
-1  
55  
-
120  
-1  
µA  
µA  
IN  
I
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
-
-
-
-
12  
8
pF  
pF  
OUT  
C
IN  
o
o
CDP68HCL05C16B V  
= 1.8V - 2.4V, V = 0V, T = 0 C to 70 C (Note 17)  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.1mA  
= -0.2mA  
= -0.75mA  
V
V
V
- 0.3  
- 0.3  
- 0.3  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
V
I
I
= 0.2mA  
= 2.0mA  
-
-
-
0.3  
0.3  
V
V
V
OL  
LOAD  
PC7  
V
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
12  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications HCL Product Type (Continued)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
o
o
Data Retention Mode  
V
T
T
= 0 C to 70 C  
1.5  
-
-
-
-
V
RM  
A
A
o
Wake Up Timer Oscillator Frequency  
f
= 25 C  
13  
kHz  
RCO  
Supply Current (f  
OSC  
= 1MHz)  
Run (Note 20)  
I
I
I
-
300  
250  
1.0  
-
600  
400  
2.0  
5.0  
-
µA  
µA  
µA  
µA  
µA  
µA  
DD  
DD  
DD  
WAIT (Notes 19, 20, 21, 23)  
STOP (Notes 21, 22)  
-
o
T
T
T
= 25 C  
-
-
A
A
A
o
o
= 0 C to 70 C  
o
STOP with Wake Up Timer Enabled  
I
= 25 C  
-
10.0  
-
DD  
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without Pullups), PC0-7, PD0-5, PD7  
I
-10  
+10  
IL  
Pullup Current PB0-7 (with Pullups, Note 24)  
Input Current - IRQ, TCAP, OSC1  
I
20  
-1  
45  
-
75  
+1  
µA  
µA  
IN  
I
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
-
-
-
-
12  
8
pF  
pF  
OUT  
C
IN  
NOTES:  
17. All values shown reflect average measurement.  
o
18. Typical values at midpoint of voltage range, 25 C only.  
19. Wait I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.  
DD  
20. Run (Operating) I , Wait I : Measured using external square-wave clock source, all inputs 0.2V from rail, no DC loads, less than 50pF  
DD DD  
on all outputs, C = 20pF on OSC2.  
L
21. Wait, Stop I : All ports configured as inputs, V = 0.2V, V = V - 0.2V.  
DD  
DD  
IL  
IH  
22. Stop I  
23. Wait I  
measured with OSC1 = V  
.
DD  
SS  
is affected linearly by the OSC2 capacitance.  
DD  
24. Input pullup current measured with V = 0.2V.  
IL  
Control Timing HCL Product Type  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HCL05C16B V  
= 5V 10%, V = 0V, T = 0 C to 70 C  
DD  
SS  
A
Frequency Of Operation  
Crystal Option  
f
f
-
4.2  
4.2  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
+ 2)  
f
f
-
DC  
480  
-
2.1  
2.1  
-
MHz  
MHz  
ns  
OSC  
OP  
External Clock (f  
OSC  
+ 2)  
OP  
Cycle Time (See Figure 11)  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
t
CYC  
t
100  
100  
-
ms  
OXOV  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
-
ms  
ILCH  
t
1.5  
t
CYC  
RL  
13  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Control Timing HCL Product Type (Continued)  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
Timer  
Resolution (Note 26)  
t
4
125  
-
-
-
-
-
-
t
t
t
RES  
CYC  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
t
, t  
TH TL  
ns  
t
(Note 27)  
125  
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 25)  
90  
ILIL  
CYC  
ns  
OSC1 Pulse Width  
CDP68HCL05C16B V  
t
, t  
OH OL  
o
= 2.4V to 3.6V, V = 0V, T = 0 C to 70 C (V = 3.6)  
DC  
o
DD  
SS  
A
Frequency Of Operation  
Crystal Option  
f
f
-
2.0  
2.0  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
+ 2)  
f
f
-
DC  
1000  
-
1.0  
1.0  
-
MHz  
MHz  
ns  
OSC  
OP  
External Clock (f  
OSC  
+ 2)  
OP  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
t
RL  
CYC  
Timer  
Resolution (Note 26)  
t
4.0  
250  
-
-
-
-
-
-
RES  
CYC  
ns  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
, t  
TH TL  
t
(Note 27)  
250  
t
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 25)  
200  
t
ILIL  
CYC  
ns  
t
, t  
OH OL  
o
o
CDP68HCL05C16B  
V
= 2.4V to 3.6V, V = 0V, T = 0 C to 70 C (V  
SS  
= 2.4)  
DC  
DD  
A
Frequency Of Operation  
Crystal Option  
f
-
1.0  
1.0  
MHz  
MHz  
OSC  
External Clock Option  
f
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
+ 2)  
f
f
-
DC  
2000  
-
0.5  
0.5  
-
MHz  
MHz  
ns  
OSC  
OP  
External Clock (f  
OSC  
+ 2)  
OP  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
CYC  
RL  
14  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Control Timing HCL Product Type (Continued)  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
Timer  
Resolution (Note 26)  
t
4.0  
500  
-
-
-
-
-
-
t
t
t
RES  
CYC  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
, t  
TH TL  
ns  
t
(Note 27)  
500  
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 25)  
400  
ILIL  
CYC  
ns  
t
, t  
OH OL  
NOTES:  
25. The minimum period t  
should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t  
.
ILIL  
CYC  
, this is the limiting minimum factor in determining the timer resolution.  
26. Since a 2-bit prescaler in the timer must count four internal cycles (t  
CYC)  
should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24  
27. The minimum period t  
TLTL  
t
.
CYC  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HCL Product Type  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HCL05C16B V  
= 5V ±10%, V = 0V, T = 0 C to 70 C Unless Otherwise Specified  
DD  
SS  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
2.1  
f
OP  
(Note 30)  
OP(M)  
Slave  
f
OP(S)  
MHz  
1
2
3
4
5
6
7
Cycle Time  
Master  
t
2.0  
-
-
t
CYC(M)  
CYC  
Slave  
t
480  
ns  
CYC(S)  
Enable Lead Time  
Master  
t
(Note 28)  
240  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 28)  
720  
-
-
-
LAG(M)  
Slave  
t
ns  
LAG(S)  
Clock (SCK) High Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
Data Setup Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
Data Hold Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
15  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HCL Product Type (Continued)  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
120  
UNITS  
ns  
8
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
A
9
Disable Time (Hold Time to High Impedance State)  
Slave  
t
240  
ns  
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
V(M)  
CYC(M)  
ns  
Slave (After Enable Edge) (Note 29)  
t
240  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
t
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
r(S)  
Fall Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
f(S)  
o
o
CDP68HCL05C16B V  
DD  
= 2.5V - 3.6V , V = 0V, T = 0 C to 70 C Unless Otherwise Specified  
DC SS  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
2.1  
f
OP  
(Note 30)  
OP(M)  
Slave  
f
OP(S)  
MHz  
1
2
3
4
5
6
Cycle Time  
Master  
t
2.0  
-
-
t
CYC(M)  
CYC  
Slave  
t
480  
ns  
CYC(S)  
Enable Lead Time  
Master  
t
(Note 28)  
240  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 28)  
720  
-
-
-
LAG(M)  
Slave  
t
ns  
LAG(S)  
Clock (SCK) High Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
Data Setup Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
16  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HCL Product Type (Continued)  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
7
Data Hold Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
8
9
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
120  
240  
ns  
ns  
A
Disable Time (Hold Time to High Impedance State)  
Slave  
t
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
V(M)  
CYC(M)  
ns  
Slave (After Enable Edge) (Note 29)  
t
240  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
t
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
r(S)  
Fall Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
f(S)  
NOTES:  
28. Signal Production depends on software.  
29. Assumes 200pF load on all SPI pins.  
30. Note that the units this specification uses is f  
(internal operating frequency), not MHz! In the master mode the SPI bus is capable of  
OP  
running at one-half of the devices’s internal operating frequency, therefore 5V: 1.05MHz maximum.  
DC Electrical Specifications HSC Product Type  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
o
o
CDP68HSC05C16B V  
= 5V ±10%, V = 0V, T = 0 C to 85 C (Notes 31, 32)  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.8mA  
= -1.6mA  
= -5.0mA  
V
V
V
- 0.8  
- 0.8  
- 0.8  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
V
I
I
= 1.6mA  
-
-
-
0.4  
0.4  
V
V
V
OL  
LOAD  
PC7  
V
= 10.0mA  
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-  
5, PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
DD  
V
IL  
SS  
-
17  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications HSC Product Type (Continued)  
PARAMETER  
Data Retention Mode  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
o
o
V
T
= 0 C to 70 C  
1.5  
-
-
V
RM  
A
Supply Current (f  
OSC  
= 8.0MHz)  
Run (Note 34)  
I
I
I
-
7
11  
6.5  
20  
40  
50  
-
mA  
mA  
µA  
DD  
DD  
DD  
WAIT (Notes 33, 34, 35, 37)  
STOP (Notes 35, 36)  
-
2
o
T
T
T
T
T
= 25 C  
-
1
A
A
A
A
A
o
o
= 0 C to 70 C  
-
-
-
µA  
o
o
= -40 C to 85 C  
-
-
µA  
o
STOP with Wake Up Timer Enabled  
Wake Up Timer Oscillator Frequency  
I
= 25 C  
10.0  
13  
-
µA  
DD  
o
f
= 25 C  
-
-
kHz  
µA  
RCO  
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without pullups), PC0-7, PD0-5, PD7  
I
-10  
+10  
IL  
Pullup Current PB0-7 (with pullups)  
Input Current - IRQ, TCAP, OSC1  
I
I
60  
-1  
-
140  
300  
+1  
12  
8
µA  
µA  
pF  
pF  
IN  
-
-
-
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
OUT  
C
-
IN  
o
o
CDP68HSC05C16B V  
= 2.4V - 3.6V, V = 0V, T = 0 C to 85 C, Unless Otherwise Specified  
DD  
SS  
A
Output Voltage  
V
I
10µA  
LOAD  
-
-
-
0.1  
-
V
V
OL  
V
V
- 0.1  
OH  
DD  
Output High Voltage  
PA0-7, PB0-7, PC0-6, TCMP, PD0, PD7  
V
I
I
I
= -0.2mA  
= -0.4mA  
= -1.5mA  
V
V
V
- 0.3  
- 0.3  
- 0.3  
-
-
-
-
-
-
V
V
V
OH  
LOAD  
LOAD  
LOAD  
DD  
DD  
DD  
PD1-5  
PC7  
V
OH  
V
OH  
Output Low Voltage  
PA0-7, PB0-7, PC0-6, PD0-5, PD7, TCMP  
V
I
I
= 0.4mA  
= 6.0mA  
-
-
-
0.3  
0.3  
V
V
V
OL  
LOAD  
PC7  
V
-
OL  
LOAD  
Input High Voltage, PA0-7, PB0-7, PC0-7, PD0-  
5, PD7, TCAP, IRQ, RESET, OSC1  
V
0.7 x V  
DD  
V
DD  
IH  
-
Input Low Voltage, PA0-7, PB0-7, PC0-7, PD0-5,  
PD7, TCAP, IRQ, RESET, OSC1  
V
V
0.2 x V  
V
V
IL  
SS  
-
DD  
o
o
Data Retention Mode  
V
T
= 0 C to 70 C  
1.5  
-
-
RM  
A
Supply Current (f  
OSC  
= 4.0MHz)  
Run (Note 34)  
I
I
I
-
-
-
-
-
-
-
2.5  
4
2
mA  
mA  
µA  
DD  
DD  
DD  
WAIT (Notes 33, 34, 35, 37)  
STOP (Notes 35, 36)  
1
1
o
T
T
T
T
T
= 25 C  
8
A
A
A
A
A
o
o
= 0 C to 70 C  
-
16  
20  
-
µA  
o
o
= -40 C to 85 C  
-
µA  
o
STOP with Wake Up Timer Enabled  
Wake Up Timer Oscillator Frequency  
I
= 25 C  
10.0  
13  
µA  
DD  
o
f
= 25 C  
-
kHz  
RCO  
18  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
DC Electrical Specifications HSC Product Type (Continued)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
I/O Ports Hi-Z Leakage Current - RESET, PA0-7,  
PB0-7 (without Pullups), PC0-7, PD0-5, PD7  
I
-10  
-
+10  
µA  
IL  
Pullup Current PB0-7 (with Pullups)  
Input Current - IRQ, TCAP, OSC1  
I
I
25  
-
65  
-
140  
±1  
12  
8
µA  
µA  
pF  
pF  
IN  
IN  
Capacitance Ports (As Input or Output)  
RESET, IRQ, TCAP, OSC1, PD0-5, PD7  
C
-
-
OUT  
C
-
-
IN  
NOTES:  
31. All values shown reflect average measurement.  
o
32. Typical values at midpoint of voltage range, 25 C only.  
33. Wait I : Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.  
DD  
34. Run (Operating) I , Wait I : Measured using external square-wave clock source, all inputs 0.2V from rail, no DC loads, less than 50pF  
DD DD  
on all outputs, C = 20pF on OSC2.  
L
35. Wait, Stop I : All ports configured as inputs, V = 0.2V, V = V - 0.2V.  
DD  
DD  
IL  
IH  
36. Stop I  
37. Wait I  
measured with OSC1 = V  
.
DD  
DD  
SS  
is affected linearly by the OSC2 capacitance.  
Control Timing HSC Product Type  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HSC05C16B V  
DD  
= 5V ±10%, V = 0V, T = 0 C to 85 C, Unless Otherwise Specified  
SS  
A
Frequency Of Operation  
Crystal Option  
f
f
-
8.2  
8.2  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
Internal Operating Frequency  
Crystal (f  
OSC  
+ 2)  
f
f
-
DC  
250  
-
4.1  
4.1  
-
MHz  
MHz  
ns  
OP  
External Clock (f  
OSC  
+ 2)  
OP  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
t
RL  
CYC  
Timer  
Resolution (Note 39)  
t
4
64  
-
-
-
-
-
-
RES  
, t  
CYC  
ns  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
TH TL  
t
(Note 40)  
64  
t
t
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 38)  
50  
ILIL  
, t  
CYC  
ns  
t
OH OL  
o
o
CDP68HSC05C16B V  
DD  
= 2.4V - 3.6V, V = 0V, T = 0 C to 85 C, Unless Otherwise Specified  
SS  
A
Frequency Of Operation  
Crystal Option  
f
f
-
4.2  
4.2  
MHz  
MHz  
OSC  
External Clock Option  
DC  
OSC  
19  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Control Timing HSC Product Type (Continued)  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
Internal Operating Frequency  
Crystal (f + 2)  
f
f
-
DC  
1000  
-
2.1  
2.1  
-
MHz  
MHz  
ns  
OSC  
External Clock (f  
OP  
+ 2)  
OSC  
OP  
Cycle Time (See Figure 11)  
t
CYC  
Crystal Oscillator Start Up Time for AT-cut Crystal (See Figure 11)  
Stop Recovery Start Up Time (AT-cut Crystal Oscillator) (See Figure 2)  
RESET Pulse Width (See Figure 11)  
t
100  
100  
-
ms  
OXOV  
t
-
ms  
ILCH  
t
1.5  
t
t
RL  
CYC  
Timer  
Resolution (Note 39)  
t
4
125  
-
-
-
-
-
-
RES  
, t  
CYC  
ns  
Input Capture Pulse Width (See Figure 3)  
Input Capture Pulse Period (See Figure 3)  
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 15)  
Interrupt Pulse Period (See Figure 15)  
OSC1 Pulse Width  
t
TH TL  
t
(Note 40)  
125  
t
t
TLTL  
CYC  
ns  
t
ILIH  
t
(Note 38)  
90  
ILIL  
, t  
CYC  
ns  
t
OH OL  
NOTES:  
38. The minimum period t  
ILIL  
should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t .  
CYC  
39. Since a 2-bit prescaler in the timer must count four internal cycles (t  
), this is the limiting minimum factor in determining the timer resolution.  
CYC  
40. The minimum period t  
TLTL  
should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24  
t
.
CYC  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HSC Product Type  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
o
o
CDP68HSC05C16B V  
= 5V ±10%, V = 0V, T = 0 C to 85 C Unless Otherwise Specified  
DD  
SS  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
4.1  
f
(Note 43)  
MHz  
OP(M)  
OP  
Slave  
f
OP(S)  
1
2
3
4
5
Cycle Time  
Master  
t
2.0  
-
-
t
CYC(M)  
CYC  
Slave  
t
244  
ns  
CYC(S)  
Enable Lead Time  
Master  
t
(Note 41)  
122  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 41)  
366  
-
-
-
LAG(M)  
Slave  
t
ns  
LAG(S)  
Clock (SCK) High Time  
Master  
t
166  
93  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
166  
93  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
20  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HSC Product Type (Continued)  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
6
Data Setup Time (Inputs)  
Master  
t
49  
49  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
7
Data Hold Time (Inputs)  
Master  
t
49  
49  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
8
9
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
61  
ns  
ns  
A
Disable Time (Hold Time to High Impedance State)  
Slave  
t
122  
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
V(M)  
CYC(M)  
ns  
Slave (After Enable Edge) (Note 42)  
t
122  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
t
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
50  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
1.0  
µs  
r(S)  
Fall Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
50  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
1.0  
µs  
f(S)  
o
o
CDP68HSC05C16B V  
DD  
= 2.4V to 3.6V, V = 0V, T = 0 C to 85 C Unless Otherwise Specified  
SS  
A
Operating Frequency  
Master  
f
DC  
DC  
0.5  
2.1  
f
(Note 43)  
MHz  
OP(M)  
OP  
Slave  
f
OP(S)  
1
2
3
4
5
6
Cycle Time  
Master  
t
2.0  
-
-
t
CYC(M)  
CYC  
Slave  
t
480  
ns  
CYC(S)  
Enable Lead Time  
Master  
t
(Note 41)  
240  
-
-
-
LEAD(M)  
Slave  
t
ns  
LEAD(S)  
Enable Lag Time  
Master  
t
(Note 41)  
720  
-
-
-
LAG(M)  
Slave  
t
ns  
LAG(S)  
Clock (SCK) High Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKH)M  
Slave  
t
W(SCKH)S  
Clock (SCK) Low Time  
Master  
t
340  
190  
-
-
ns  
ns  
W(SCKL)M  
Slave  
t
W(SCKL)S  
Data Setup Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
SU(M)  
Slave  
t
SU(S)  
21  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Interface (SPI) Timing (See Figure 4) HSC Product Type (Continued)  
LEAD  
PARAMETER  
SYMBOL  
MIN  
MAX  
UNITS  
7
Data Hold Time (Inputs)  
Master  
t
100  
100  
-
-
ns  
ns  
H(M)  
Slave  
t
H(S)  
8
9
Access Time (Time to Data Active from High Impedance State)  
Slave  
t
0
-
120  
240  
ns  
ns  
A
Disable Time (Hold Time to High Impedance State)  
Slave  
t
DIS  
10  
Data Valid Time  
Master (Before Capture Edge)  
t
0.25  
-
-
t
V(M)  
CYC(M)  
ns  
Slave (After Enable Edge) (Note 42)  
t
240  
V(S)  
11  
12  
13  
Data Hold Time (Outputs)  
Master (After Capture Edge)  
t
0.25  
0
-
-
t
HO(M)  
CYC(M)  
ns  
Slave (After Enable Edge)  
t
HO(S)  
Rise Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
r(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
r(S)  
Fall Time (V  
= 20% to 70%, C = 200pF)  
L
DD  
SPI Outputs (SCK, MOSI, MISO)  
t
-
-
100  
2.0  
ns  
f(M)  
SPI Inputs (SCK, MOSI, MISO, SS)  
t
µs  
f(S)  
NOTES:  
41. Signal Production depends on software.  
42. Assumes 200pF load on all SPI pins.  
43. Note that the units this specification uses is f  
(internal operating frequency), not MHz! In the master mode the SPI bus is capable of  
OP  
running at one-half of the devices’s internal operating frequency, therefore 5V: 2.0MHz and 2.4V to 3.6V: 500kHz maximum.  
Waveforms  
OSC1  
(NOTE 44)  
t
RL  
RESET  
t
ILIH  
IRQ  
(NOTE 45)  
t
4064 t  
CYC  
ILCH  
IRQ  
(NOTE 46)  
INTERNAL  
CLOCK  
INTERNAL  
ADDRESS  
BUS  
3FFE  
3FFE  
3FFE 3FFE 3FFE  
RESET OR INTERRUPT  
VECTOR FETCH  
NOTES:  
44. Represents the internal gating of the OSC1 pin.  
45. IRQ pin edge-sensitive mask option.  
46. IRQ pin level and edge-sensitive mask option.  
FIGURE 2. STOP RECOVERY TIMING DIAGRAM  
22  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Waveforms (Continued)  
t
t
t
TL  
TLTL  
TH  
EXTERNAL  
(TCAP PIN 37)  
FIGURE 3. TIMER RELATIONSHIPS  
HELD HIGH ON MASTER  
SS (INPUT)  
(13)  
(12)  
(12)  
(5)  
SCK (CPOL = 1)  
(OUTPUT)  
(4)  
(1)  
(13)  
SCK (CPOL = 0)  
(OUTPUT)  
(4)  
(5)  
D7I  
D6I  
D0I  
MISO (INPUT)  
(7)  
D7O  
(11)  
(6)  
D6O  
D0O  
MOSI (OUTPUT)  
(10)  
FIGURE 4A. SPI MASTER TIMING CPHA = 0  
HELD HIGH ON MASTER  
SS (INPUT)  
(13)  
(12)  
(5)  
SCK (CPOL = 0)  
(OUTPUT)  
(1)  
(12)  
(4)  
(5)  
(13)  
SCK (CPOL = 1)  
(OUTPUT)  
(4)  
D7I  
D6I  
D0I  
MISO (INPUT)  
(7)  
D7O  
(11)  
(6)  
D6O  
D0O  
MOSI (OUTPUT)  
(10)  
NOTE: MEASUREMENT POINTS ARE V , V , V AND V  
OL OH IL IH  
FIGURE 4B. SPI MASTER TIMING CPHA = 1  
23  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Waveforms (Continued)  
SS (INPUT)  
(12)  
(13)  
(13)  
(12)  
(5)  
SCK (CPOL = 1)  
(INPUT)  
(4)  
(5)  
(1)  
(3)  
(2)  
SCK (CPOL = 0)  
(INPUT)  
(4)  
D7I  
D6I  
D0I  
MISO (OUTPUT)  
MOSI (INPUT)  
(8)  
(6)  
(7)  
D7O  
(11)  
D6O  
D0O  
(10)  
FIGURE 4C. SPI SLAVE TIMING CPHA = 0  
SS (INPUT)  
(13)  
(12)  
(12)  
(5)  
(4)  
SCK (CPOL = 1)  
(INPUT)  
(2)  
(4)  
(3)  
(1)  
(13)  
SCK (CPOL = 0)  
(INPUT)  
LAST  
BIT  
(5)  
TRANSMITTED  
HIGH  
Z
MISO (OUTPUT)  
MOSI (INPUT)  
D7O  
D7I  
D6O  
D6I  
D0O  
(8)  
(9)  
(10)  
(11)  
D0I  
(6)  
(7)  
FIGURE 4D. SPI SLAVE TIMING CPHA = 1  
24  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
The following sections provide a description of the functional Crystal  
pins, Input/Output programming, software programmable  
options, memory, CPU registers and self check mode for the  
Harris CDP68HC05C16B microcontroller. See pages 2 and  
67 for ordering information.  
The circuit shown in Figure 5B is recommended when using a  
crystal. The internal oscillator is designed to interface with an  
AT-cut parallel resonant quartz-crystal resonator in the fre-  
quency range specified for f  
in Control Timing. Use of an  
OSC  
external CMOS oscillator is recommended when crystals out-  
side the specified ranges are to be used. The crystal and com-  
ponents should be mounted as close as possible to the input  
pins to minimize output distortion and start up stabilization time.  
Functional Pin Description  
V
and V  
SS  
DD  
Power is supplied to the MCU using these two pins. V  
is  
DD  
Refer to DC Electrical Specifications for V  
specifications.  
power and V is ground.  
DD  
SS  
Ceramic Resonator  
IRQ (Maskable Interrupt Request)  
A ceramic resonator may be used in place of the crystal in  
cost-sensitive applications. The circuit in Figure 5B is recom-  
mended when using a ceramic resonator. Figure 5A lists the  
recommended capacitance and feedback resistance values.  
The manufacturer of the particular ceramic resonator being  
considered should be consulted for specific information.  
IRQ is an external maskable interrupt which can force the MCU  
into an interrupt service routine. The IRQ pin on the C16B has  
a software programmable option which provides two different  
choices of interrupt triggering sensitivity. The options that can  
be chosen are: 1.) Negative edge-sensitive triggering only, or  
2.) Both negative edge-sensitive and level-sensitive triggering.  
The IRQ options are chosen by either setting or clearing the  
IRQ bit in the OPTION register (See Software Programmable  
Options for details). In the latter case, either type of input to the  
IRQ pin will produce the interrupt. The MCU completes the cur-  
rent instruction before it responds to the interrupt request.  
RC  
If the RC oscillator option is selected, then a resistor is con-  
nected to the oscillator pins as shown in Figure 5D.  
External Clock  
When the IRQ pin goes low for at least one t  
, a logic one is  
ILIH  
An external clock should be applied to the OSC1 input with  
the OSC2 input not connected, as shown in Figure 5E. An  
external clock may be used with either the RC or crystal  
latched internally to signify an interrupt has been requested.  
When the MCU completes its current instruction, the interrupt  
latch is tested. If the interrupt latch contains a logic one, and the  
interrupt mask bit (I bit) in the condition code register is clear,  
the MCU then begins the interrupt sequence.  
oscillator option. The t  
or t specifications do not  
OXOV  
ILCH  
apply when using an external clock input. The equivalent  
specification of the external clock source should be used in  
If the option is selected to include level-sensitive triggering,  
lieu of t  
or t  
.
ILCH  
OXOV  
then the IRQ input requires an external resistor to V  
for  
DD  
PA0 - PA7  
“wire-OR” operation. See INTERRUPTS for more detail con-  
cerning interrupts.  
These eight I/O lines comprise port A. The state of any pin is  
software programmable and all port A lines are configured  
as inputs during power-on or reset. Port A pins PA7 - PA4  
are mask programmable to provide fixed tone/simple PWM  
outputs. The port A data register (PORTA) is at location  
$0000 and the port A data direction register (DDRA) is at  
location $0004. Refer to Input/Output Programming para-  
graph for a detailed description of I/O programming.  
RESET  
The RESET input is not required for start up but can be used  
to reset the MCU internal state and provide an orderly soft-  
ware start up procedure. Refer to RESETS for a detailed  
description.  
TCAP  
PB0 - PB7  
The TCAP input controls the input capture feature for the on-  
chip programmable timer system. Refer to Input Capture  
Register for additional information.  
These eight lines comprise port B. The state of any pin is  
software programmable and all port B lines are configured  
as inputs during power-on or reset. Each of the port B pins  
has a mask programmable interrupt and pullup option. This  
makes port B ideal for keyboard scanning. The port B data  
register (PORTB) is at location $0001 and the port B data  
direction register (DDRB) is at location $0005. Refer to  
TCMP  
The TCMP pin (35) provides an output for the output com-  
pare feature of the on-chip timer system. Refer to Output  
Compare Register for additional information.  
Input/Output Programming paragraph for  
a detailed  
OSC1, OSC2  
description of I/O programming.  
The CDP68HC05C16B family of MCUs can be configured to  
accept either a crystal input or an RC network to control the  
internal oscillator. The internal clocks are derived by a  
PC0 - PC7  
These eight lines comprise port C. The state of any pin is soft-  
ware programmable and all port C lines are configured as  
inputs during power-on reset. PC7 has a high current sink and  
source output stage. The port C data register (PORTC) is at  
location $0002 and the port C data direction register (DDRC)  
is at location $0006. Refer to Input/Output Programming  
paragraph for a detailed description of I/O programming.  
divide-by-two of the internal oscillator frequency (f  
).  
OSC  
25  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
CRYSTAL  
CERAMIC RESONATOR  
2MHz  
400  
5
4MHz  
75  
UNITS  
2MHz - 4MHz  
UNITS  
R
C
C
C
C
R
R
C
C
C
C
R
(Typical)  
10  
40  
SMAX  
S
0
1
7
pF  
pF  
0
0.008  
0.012  
15 - 30  
15 - 25  
10  
pF  
4.3  
pF  
1
15 - 40  
15 - 30  
10  
pF  
30  
pF  
OSC1  
OSC2  
P
OSC1  
OSC2  
P
pF  
30  
pF  
MΩ  
K
1 - 10  
1250  
MΩ  
-
Q
30  
40  
Q
FIGURE 5A. CRYSTAL/CERAMIC RESONATOR PARAMETERS  
L
C
R
1
MCU  
S
OSC2  
38  
OSC1  
39  
OSC1  
OSC2  
38  
R
P
39  
C
0
C
C
OSC2  
38  
39  
OSC1  
FIGURE 5C. EQUIVALENT CRYSTAL CIRCUIT  
FIGURE 5B. CRYSTAL OSCILLATOR CONNECTIONS  
MCU  
MCU  
OSC1  
39  
OSC2  
38  
OSC1  
39  
OSC2  
38  
R
UNCONNECTED  
EXTERNAL CLOCK  
FIGURE 5D. RC OSCILLATOR CONNECTIONS  
FIGURE 5E. EXTERNAL CLOCK SOURCE CONNECTIONS  
PD0 - PD5, PD7  
TABLE 1. I/O PIN FUNCTIONS  
These seven lines comprise port D. The state of each port  
pin is software programmable and all Port D pins are config-  
ured as inputs during reset. Two of the CDP68HC05C16B’s  
subblocks make use of the pins on this port. Four of the  
lines, PD2/MISO, PD3/MOSI, PD4/SCK, and PD5/SS, are  
used for the serial peripheral interface (SPI). Two of these  
lines, PD0/RDI and PD1/TD0, are used for the serial com-  
munications interface (SCI). Both the SCI and the SPI sys-  
tems are disabled during power-on or reset configuring all  
pins as inputs. The port D data register (PORTD) is at loca-  
tion $0003 and the Port D data direction register (DDRD) is  
located at $0007. Refer to Input/Output Programming for a  
detailed description of I/O programming.  
(NOTE)  
R/W  
DDRn BIT  
I/O PIN FUNCTION  
0
0
The I/O pin is in input mode. Data is  
written into the output data latch.  
0
1
Data is written into the output data latch  
and output to the I/O pin.  
1
1
0
1
The state of the I/O pin is read.  
The I/O pin is in an output mode. The  
output data latch is read.  
NOTE: R/W is an internal signal.  
The data direction registers are capable of being written to  
or read by the processor. Refer to Figure 6 and Table 1. Any  
port A, port B, port C, or port D pin is configured as an out-  
put if its corresponding DDRn bit is set to a logic one. When  
Input/Output Programming  
Bidirectional Parallel Ports A, B, C and D  
configured as an output, the pin will be driven to V  
if the  
DD  
Each I/O pin of ports A, B, C and D can be programmed as  
an input or an output under software control. Each port has  
an data register (PORTn) and an associated data direction  
register (DDRn). All registers are 8 bits wide except for the  
port D data and data direction which are 7 bits wide. The  
direction of the pins is determined by the state of the corre-  
sponding bit in the DDRn.  
associated PORTn bit is a 1 and it will be driven to V if the  
SS  
associated PORTn bit is a 0. During the programmed output  
state, a read of the data register actually reads the value of  
the output data latch and not the I/O pin (see Figure 6A). At  
power-on or reset, all DDR bits are cleared, which config-  
ures all port A, B, C, and D pins as inputs.  
26  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Port A4 - A7 Tone/Simple PWM Output Option  
V
In addition to being a standard bidirectional port, four bits of  
Port A (PA4 - PA7) have a mask option to connect an internal  
“tone” signal to the output (see Figure 6D). When the option is  
selected a fixed frequency will appear on the output pin when-  
ever the appropriate PORTA and DDRA bits are set. A second  
mask option disables the output NMOS device allowing wire-  
ORing of the pins to produce various duty cycle outputs creat-  
ing a simple PWM (see Figure 6D). Refer to Port A Tone and  
Simple PWM Circuitry for a detailed explanation.  
DD  
MASK OPTION 1  
TONE  
V
DD  
PORT DATA  
P
PORT DRR  
V
PAD  
DD  
MASK OPTION 2  
N
DATA  
DIR REG  
BIT  
INTERNAL LOGIC  
OUTPUT  
FIGURE 6D. PORT A7 - A4 TONE OUTPUT MASK OPTION  
Port B Interrupts and Pullups  
I/O  
PIN  
LATCHED  
OUTPUT  
DATA BIT  
In addition to being a standard bidirectional port, each bit of  
Port B has a mask option to connect a pullup device to the  
I/O pad and to simultaneously feed the input to the internal  
interrupt logic. When the mask option is not selected, each  
Port B pin behaves as a standard bidirectional port pin.  
INPUT REG BIT  
INPUT I/O  
FIGURE 6A. TYPICAL PARALLEL PORT I/O CIRCUITRY  
When the mask option is selected, a pullup PMOS device  
7
6
5
4
3
2
1
0
with an impedance of approximately 20kis connected  
TYPICAL  
PORT DATA  
DIRECTION  
REGISTER  
between the pad and V  
(see Pullup Current, I , in the  
DD  
IN  
DDR 7 DDR 6 DDR 5 DDR 4 DDR 3 DDR 2 DDR 1 DDR 0  
DC Electrical Specifications tables for more details) and the  
input signal is inverted and internally ORed with the IRQ  
signal (refer to Figure 6E).  
(Note 47)  
TYPICAL  
PORT DATA  
REGISTER  
V
V
DD  
DD  
P
MASK OPTION  
DDRB BIT n  
PIN  
P7  
P6  
P5  
P4  
P3  
P2  
P1  
P0  
PBn  
NOTE:  
47. DDR6 not available on port D.  
PORT CIRCUITRY  
FIGURE 6C  
FIGURE 6B. TYPICAL PARALLEL PORT I/O CIRCUITRY  
TO INTERNAL  
INTERRUPT  
OTHER PORT B INPUTS  
IRQ  
V
DD  
PORT DATA  
PORT DRR  
P (NOTE 48)  
N (NOTE 48)  
FIGURE 6E. PORT B INTERRUPT AND PULLUP MASK OPTION  
PAD  
The interrupt behavior of any port B pin which has the pul-  
lup/interrupt mask option activated is identical to the results  
one would achieve by externally ORing (active low) the  
signal with the IRQ signal.  
INTERNAL LOGIC  
NOTE: The BIH and BIL instructions apply to the output of the logic  
OR of the Port B IRQ, IRQ pin and Wake Up Timer IRQ signals and  
can not be used to test the IRQ pin exclusively.  
NOTES:  
48. Denotes devices are enhancement type.  
49. Input Protection and Latch-up protection not shown.  
If the IRQ bit in the OPTION register is clear (the external  
interrupt will sense only edges, see Software Programma-  
ble Options, External Interrupts and Figure 15 for details)  
when any one of the interrupt sources (port B inputs or IRQ)  
goes low an interrupt will be generated. A second interrupt  
will not be generated until all of the interrupt lines go high  
and one or more again goes low.  
FIGURE 6C. TYPICAL PARALLEL PORT I/O CIRCUITRY  
27  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
If the IRQ bit in the OPTION register is set (the external  
Software Programmable Options  
interrupt will sense both level and edges, see Software Pro-  
grammable Options, External Interrupts and Figure 15 for  
details) when any one of the interrupt sources (port B inputs  
or IRQ) goes low an interrupt will be generated. Interrupts will  
continue to be generated until all of the interrupt lines go high.  
The CDP68HC05C16B has several software programmable  
options that are controlled by the Option register (OR),  
located at memory address $3FDF. The Option register con-  
tains control bits for the following options:  
• Memory mapping of shared RAM/ROM areas from $20 to  
$4F and from $100 to $17F  
The pullup device and the interrupt function are disabled when  
the associated DDRB bit is set high. When its DDRB bit is a 1,  
each port B pin acts as a normal output regardless of whether • Edge triggered only or edge and level-triggered external  
or not the pullup/interrupt mask option has been selected. Thus  
the DDRB bit can be used as an interrupt enable for the inter-  
ruptible port B pins. Care should be taken when re-enabling a  
port B interrupt to avoid false interrupts. False interrupts can be  
avoided by first driving the PORTB bit high before clearing the  
DDRB bit. Further note, that all DDRB bits are cleared by reset,  
thus enabling port B interrupts (no interrupt will be recognized  
until execution of the first CLI instruction following reset).  
interrupt (IRQ or any port B pin configured as an interrupt)  
This register must be configured by the user software and all  
bits except for the IRQ bit can be read or written any time the  
CPU is operational.  
7
6
5
0
4
0
3
0
2
0
1
0
0
RAM0 RAM1  
IRQ  
$3FDF  
B7, RAM0 RAM0 is the Random Access Memory Control  
Bit 0. This bit is used to control which memory  
type (RAM/user ROM) is mapped between $20  
and $4F. If RAM0=0, then the ROM is selected.  
If RAM0=1 then the RAM is selected.  
Bidirectional I/O Port C  
Port C is an 8-bit general purpose bidirectional input/output  
ports located at $0002. The data direction register for port C  
is located at $0006. The contents of the port C data register  
are indeterminate at initial power up and must be initialized  
by user software. Reset does not affect the data register  
itself, but does however clear the data direction register  
(DDRC), setting the port to input. Bit 7 of port C (PC7) is a  
high current sink and source output. Refer to the DC Electrical  
Specifications table for details.  
B6, RAM1 RAM1 is the Random Access Memory Control  
Bit 1. This bit is used to control which memory  
type (RAM/user ROM) is mapped between $100  
and $17F. If RAM1=0, then the ROM is selected.  
If RAM1=1 then the RAM is selected.  
B5-B2, B0 Not implemented, always read as 0.  
Bidirectional I/O Port D  
B1, IRQ  
The IRQ edge level bit is used to select what  
type of signal will trigger an external interrupt. If  
this bit is set (1) then the edge and level interrupt  
option is selected. If this bit is clear (0), the edge  
only option is selected. This bit is set by reset  
but can be cleared by software. This bit can only  
be written once.  
Port D is a 7-bit bidirectional port located at $0003 with a  
data direction register (DDRD) located at $0007. Four of it’s  
pins are with the SPI subsystem and two more are shared  
with the SCI subsystem. Refer to Serial Communications  
Interface and Serial Peripheral Interface for more detailed  
information. When these systems are disabled the port D  
lines serve as general purpose bidirectional port lines. Dur-  
ing power-on reset or external reset both the SPI and SCI  
modules are disabled and all of the bits in DDRD are  
cleared, setting port D as an input port. When reading Port  
D, bit 6 returns the state of the TCMP pin. This bit is read  
only and can not be used to set the TCMP high or low. There  
is no DDR associated with bit 6. Bits being used for the serial  
ports should not be used as general I/O as they do not return  
valid data.  
NOTE: It is recommended that all unused inputs, except OSC2, and  
I/O ports (configured as outputs) be tied to an appropriate logic level  
(e.g. either V  
or V ).  
SS  
DD  
28  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
$0000  
0000  
0000  
PORT A DATA REGISTER  
PORT B DATA REGISTER  
$00  
$01  
$02  
$03  
$04  
$05  
$06  
$07  
$08  
$09  
$0A  
$0B  
$0C  
$0D  
$0E  
$0F  
$10  
$11  
$12  
$13  
$14  
$15  
$16  
$17  
$18  
$19  
$1A  
$1B  
$1C  
$1D  
$1E  
$1F  
PORTS  
8 BYTES  
I/O  
32 BYTES  
PORT C DATA REGISTER  
PORT D DATA REGISTER  
UNUSED  
2 BYTES  
$001F  
$0020  
0031  
0032  
SERIAL  
PERIPHERAL  
INTERFACE  
3 BYTES  
PORT A DATA DIRECTION REGISTER  
PORT B DATA DIRECTION REGISTER  
PORT C DATA DIRECTION REGISTER  
PORT D DATA DIRECTION REGISTER  
UNUSED  
USER  
ROM  
RAM  
48 BYTES  
48 BYTES  
RAM0=0  
RAM0=1  
$004F  
$0050  
0079  
0080  
SERIAL  
COMMUNICATIONS  
INTERFACE  
5 BYTES  
UNUSED  
TIMER  
10 BYTES  
SPI CONTROL REGISTER  
RAM  
176 BYTES  
SPI STATUS REGISTER  
WAKE UP TIMER  
SPI DATA I/O REGISTER  
COP TIMER  
2 BYTES  
$00BF  
$00C0  
0191  
0192  
SCI BAUD RATE REGISTER  
SCI CONTROL REGISTER 1  
SCI CONTROL REGISTER 2  
SCI STATUS REGISTER  
STACK  
64 BYTES  
RESERVED  
0031  
$00FF  
$0100  
0255  
0256  
USER  
ROM  
RAM  
128 BYTES  
128 BYTES  
SCI DATA REGISTER  
$3FF0  
$3FF1  
$3FF2  
$3FF3  
$3FF4  
$3FF5  
$3FF6  
$3FF7  
$3FF8  
$3FF9  
$3FFA  
$3FFB  
$3FFC  
$3FFD  
$3FFE  
$3FFF  
UNUSED  
UNUSED  
UNUSED  
RAM1=0  
RAM1=1  
TIMER CONTROL REGISTER  
TIMER STATUS REGISTER  
INPUT CAPTURE HIGH REGISTER  
INPUT CAPTURE LOW REGISTER  
OUTPUT COMPARE HIGH REGISTER  
OUTPUT COMPARE LOW REGISTER  
COUNTER HIGH REGISTER  
COUNTER LOW REGISTER  
ALTERNATE COUNTER HIGH REGISTER  
ALTERNATE COUNTER LOW REGISTER  
WAKE UP TIMER CONTROL REGISTER  
COP RESET REGISTER  
0383  
0384  
$017F  
$0180  
UNUSED  
SPI HIGH VECTOR  
USER  
ROM  
15,744 BYTES  
SPI LOW VECTOR  
SCI HIGH VECTOR  
SCI LOW VECTOR  
TIMER HIGH VECTOR  
16127  
16128  
$3EFF  
$3F00  
TIMER LOW VECTOR  
IRQ/PORTB HIGH VECTOR  
IRQ/PORTB LOW VECTOR  
SWI HIGH VECTOR  
SELF CHECK  
ROM AND  
VECTORS  
OPTION REGISTER  
16351  
$3FDF  
16367  
16368  
COP CONTROL REGISTER  
RESERVED  
$3FEF  
$3FF0  
SWI LOW VECTOR  
USER  
VECTORS  
16 BYTES  
RESET HIGH VECTOR  
RESET LOW VECTOR  
$3FFF  
16383  
FIGURE 7. ADDRESS MAP FOR CDP68HC05C16B, CDP68HCL05C16B AND CDP68HSC05C16B  
7
7
0
0
0
0
0
A
X
ACCUMULATOR  
STACK  
0
7
INDEX REGISTER  
PROGRAM COUNTER  
STACK POINTER  
CONDITION CODE REG  
ACCUMULATOR (A)  
1
1
0
1
13  
13  
PC  
INDEX REGISTER (X)  
7
0
PROGRAM COUNTER HIGH  
0
0
0
0
0
1
1
SP  
0
4
CC  
N
PROGRAM COUNTER LOW  
H
I
Z
C
CONDITION CODE REG  
UNSTACK  
CARRY/BORROW  
ZERO  
NEGATIVE  
INTERRUPT MASK  
HALF CARRY  
NOTE: Since the Stack Pointer decrements during pushes, the PCL  
is stacked first, followed by PCH, etc. Pulling from the stack is in the  
reverse order.  
FIGURE 9. STACKING ORDER  
FIGURE 8. PROGRAMMING MODEL  
29  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
to the six least significant register bits to produce an address  
Memory  
within the range of $00FF to $00CO. The stack area of RAM  
is used to store the return address on subroutine calls and  
the machine state during interrupts. During external or  
power-on reset, and during a reset stack pointer (RSP)  
instruction, the stack pointer is set to its upper limit ($00FF).  
Nested interrupt and/or subroutines may use up to 64 (deci-  
mal) locations. When the 64 locations are exceeded, the  
stack pointer wraps around and points to its upper limit  
($00FF), thus, losing the previously stored information. A  
subroutine call occupies two RAM bytes on the stack, while  
an interrupt uses five RAM bytes.  
As demonstrated in Figure 7, the CDP68HC05C16B,  
CDP68HCL05C16B and CDP68HSC05C16B MCUs are  
capable of addressing 16384 bytes of memory and I/O  
registers with their program counter. The first 256 bytes of  
memory (page zero) include 28 bytes of I/O features such as  
data ports, the port DDRs, timer, serial peripheral interface  
(SPI), and serial communication interface (SCI); 48 bytes of  
user ROM (RAM0=0) or RAM (RAM0=1) and 176 bytes of  
RAM. Notice that between the address locations of $20 and  
$4F there is both RAM and ROM in the same locations. Both  
of these memories exist simultaneously and can be switched  
between while the MCU is running. When the CPU accesses  
Condition Code Register (CC)  
any location between $20 and $4F, the memory that will be The condition code register is a 5-bit register which indicates  
accessed depends on the state of the RAM0 bit in the the results of the instruction just executed as well as the  
OPTION register ($3FDF). If RAM0=0, then the ROM will be state of the processor. These bits can be individually tested  
accessed. If RAM0=1, then the RAM will be accessed. This by a program and specified action taken as a result of their  
same setup applies to the next 128 locations ($100 to $17F), state. Each bit is explained in the following paragraphs.  
except that now RAM1 controls the memory switching, not  
RAM0. Switching to the ROM area in either section will not alter  
Half Carry Bit (H)  
The H bit is set to a one when a carry occurs between bits 3  
and 4 of the ALU during an ADD or ADC instruction. The H  
bit is useful in binary coded decimal subroutines.  
the contents of the RAM in these locations. See Software  
Programmable Options for more information. The next 15,744  
bytes complete the user ROM. The self-check ROM (239 bytes)  
and self-check vectors (16 bytes) are contained in memory  
locations $3F00 through $3FEF. The OPTION register is  
located in this area at location $3FDF. The 16 highest address  
bytes contain the user defined reset and interrupt vectors. Four  
bytes of the lowest 32 memory locations are unused and the  
176 bytes of user RAM between locations $50 and $FF include  
up to 64 bytes for the stack. Since most programs use only a  
small part of the allocated stack locations for interrupts and/or  
subroutine stacking purposes, the unused bytes are usable for  
program data storage.  
Interrupt Mask Bit (I)  
When the I bit is set, all interrupts are disabled. Clearing this  
bit enables the interrupts. If an external interrupt occurs  
while the I bit is set, the interrupt is latched and processed  
after the I bit is next cleared; therefore, no interrupts are lost  
because of the I bit being set. An internal interrupt can be  
lost if it is cleared while the I bit is set (refer to Programmable  
Timer, Serial Communications Interface, and Serial Periph-  
eral Interface Sections for more information).  
Negative (N)  
CPU REGISTERS  
When set, this bit indicates that the result of the last arith-  
metic, logical, or data manipulation is negative (bit 7 in the  
result is a logic one).  
The CPU contains five registers, as shown in the program-  
ming model of Figure 8. The interrupt stacking order is  
shown in Figure 9.  
Zero (Z)  
Accumulator (A)  
When set, this bit indicates that the result of the last arith-  
metic, logical, or data manipulation is zero.  
The accumulator is an 8-bit general purpose register used to  
hold operands, results of the arithmetic calculations, and  
data manipulations.  
Carry/Borrow (C)  
Indicates that a carry or borrow out of the arithmetic logic  
unit (ALU) occurred during the last arithmetic operation. This  
bit is also affected during bit test and branch instructions,  
shifts, and rotates.  
Index Register (X)  
The X register is an 8-bit register which is used during the  
indexed modes of addressing. It provides an 8-bit value  
which is used to create an effective address. The index reg-  
ister is also used for data manipulations with the read-mod-  
ify-write type of instructions and as a temporary storage  
register when not performing addressing operations.  
Self Check  
The self-check capability of the CDP68HC05C16B MCU pro-  
vides an internal check to determine if the device is functional.  
Self-check is performed using the circuit shown in the sche-  
matic diagram of Figure 10. As shown in the diagram, port C  
pins PC0 - PC3 are monitored (light emitting diodes are  
shown but other devices could be used) for the self-check  
results. The self-check mode is entered by applying a 9V input  
(through a 4.7kresistor) to the IRQ pin (2) and 5V input  
(through a 10kresistor) to the TCAP pin (37) and then  
depressing the reset switch to execute a reset. After reset, the  
Program Counter (PC)  
The program counter is a 14-bit register that contains the  
address of the next instruction to be executed by the processor.  
Stack Pointer (SP)  
The stack pointer is a 14-bit register containing the address  
of the next free locations on the push-down/pop-up stack.  
When accessing memory, the most significant bits are per-  
manently configured to 00000011. These bits are appended  
30  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
RESET  
RESET  
1
1.0µF  
10K  
4.7K  
IRQ  
2
3
+9V  
V
NC  
40  
39  
+5V  
+5V  
DD  
20pF  
20pF  
OSC1  
10K  
TCAP  
37  
10M  
4MHz  
+5V  
PA7  
PA6  
PA5  
PA4  
PA3  
PA2  
PA1  
38  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
4
5
PD7  
TCMP  
PD5/SS  
PD4/SCK  
PD3/MOSI  
PD2/MISO  
PD1/TDO  
PD0/RDI  
PC0  
6
7
10K  
1M  
8
9
10  
PA0  
11  
4.7K  
4.7K  
+5V  
PB0  
PB1  
PB2  
PB3  
PB4  
PB5  
PB6  
PB7  
12  
13  
14  
15  
16  
17  
18  
19  
4.7K  
PC1  
PC2  
4.7K  
PC3  
PC4  
PC5  
PC6  
PC7  
V
SS  
20  
FIGURE 10. SELF-CHECK CIRCUIT SCHEMATIC DIAGRAM  
TABLE 2. SELF-CHECK RESULTS  
following seven tests are performed automatically:  
PC3  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
PC2  
ON  
PC1  
ON  
PC0  
REMARKS  
I/O - Functionally exercises ports A, B and C  
RAM - Counter test for each RAM byte  
ON Bad I/O  
OFF Bad RAM  
ON Bad Timer  
OFF Bad SCI  
ON Bad ROM  
OFF Bad SPI  
Timer - Tracks counter register and checks OCF flags  
ON  
ON  
SCI - Transmission Test; checks for RDRF, TDRE,  
TC, and FE flags  
ON  
OFF  
OFF  
ON  
ROM - Exclusive OR with odd ones parity result  
ON  
SPI - Transmission test with check for SPIF,  
WCOL, and MODF flags  
OFF  
OFF  
Interrupts - Tests external, timer, SCI, and SPI interrupts  
ON  
Self-check results (using the LEDs as monitors) are shown in  
Table 2. The following subroutines are available to user pro-  
grams and do not require any external hardware.  
Flashing  
All Others  
Good Device  
Bad Device, Bad Port C, etc.  
NOTE: ON implies LED on, port = 0; OFF implies LED off, port = 1.  
TIMER TEST SUBROUTINE  
This subroutine returns with the Z bit cleared if any error is  
detected; otherwise, the Z bit is set. This subroutine is called  
at location $3F8C. The output compare register is first set to  
the current timer state. Because the timer is free running and  
has only a divide-by-four prescaler, each timer count cannot  
be tested. The test tracks the counter until the timer wraps  
around, triggering the output compare flag in the timer status  
register. RAM locations $0050 and $0051 are overwritten.  
Upon return to the user’s program, X = 40. If the test passed,  
A = 0.  
ROM CHECKSUM SUBROUTINE  
This subroutine returns with the Z bit cleared if any error is  
detected; otherwise, the Z bit is set. This subroutine is called  
at location $3FB5 with RAM location $0053 equal to $01 and  
A = 0. A short routine is set up and executed in RAM to com-  
pute a checksum of the entire ROM pattern. Upon return to  
the user’s program, X = 0. If the test passed, A = 0. RAM  
locations $0050 through $0053 are overwritten.  
31  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
V
DD  
OSC1  
(NOTE 51)  
4064  
tOXOV tCYC  
tCYC  
INTERNAL  
PROCESSOR  
CLOCK (NOTE 50)  
INTERNAL  
ADDRESS BUS  
(NOTE 50)  
NEW  
PC  
NEW  
PC  
3FFE  
3FFE  
3FFE  
3FFE  
PCH  
3FFF  
PCL  
3FFE  
3FFF  
INTERNAL  
DATA BUS  
(NOTE 52)  
OP  
CODE  
NEW  
PCH  
NEW  
PCL  
OP  
CODE  
tRL  
RESET  
(NOTE 52)  
NOTES:  
50. Internal signal and bus information is not available externally.  
51. OSC1 is not meant to represent frequency. It is only meant to represent time.  
52. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.  
FIGURE 11. POWER-ON RESET AND RESET  
RESETS  
Resets, Interrupts, and Low Power Modes  
The MCU has two reset modes: an active low external reset  
pin (RESET) and a power-on reset function; refer to Figure 11.  
TABLE 3. RESET ACTION ON INTERNAL CIRCUIT  
POWER-  
RESET  
PIN  
ON  
RESET  
RESET Pin  
CONDITION  
The RESET input pin is used to reset the MCU to provide an  
orderly software start up procedure. When using the external  
reset mode, the RESET pin must stay low for a minimum of  
one and one half t  
Schmitt Trigger as part of its input to improve noise immunity.  
The RESET pin of the CDP68HC05C16B is a bidirectional pin  
Timer Prescaler reset to zero state  
Timer counter configured to $FFFC  
Timer output compare (TCMP) bit reset to zero  
X
X
X
X
X
X
X
X
. The RESET pin contains an internal  
CYC  
All timer interrupt enable bits cleared (ICIE,  
OCIE, and TOIE) to disable timer interrupts.  
The OLVL timer bit is also cleared by reset.  
in that the MCU will drive the pin low during the 4064 t  
CYC  
after a power-on reset and for 4 t  
CYC  
reset is issued (from a COP time-out or clock monitor reset).  
All other times the pin is configured as an input.  
every time an internal  
All data direction registers cleared to zero  
(input)  
X
X
X
Reset COP control register and timer  
Clear COP Reset Flag (COPF)  
Reset Wake Up Timer Register  
Configure stack pointer to $00FF  
X
X
X
X
X
Power-On Reset  
The power-on reset occurs when a positive transition is  
X
X
X
detected on V . The power-on reset is used strictly for  
DD  
power turn-on conditions and should not be used to detect  
any drops in the power supply voltage. There is no provision  
for a power-down reset. The power-on circuitry provides for a  
Force internal address bus to restart vector  
(See Table 4)  
Set I bit in condition code register to a logic one  
Clear STOP latch  
X
X
X
X
X
X
X
X
X
X
4064 t  
delay from the time that the oscillator becomes  
CYC  
active. If the external RESET pin is low at the end of the  
4064 t time out, the processor remains in the reset con-  
Clear external interrupt latch  
Clear WAIT latch  
CYC  
dition until RESET goes high.  
Table 3 shows the actions of the two resets on internal cir-  
cuits, but not necessarily in order of occurrence (X indicates  
that the condition occurs for the particular reset).  
Disable SCI (serial control bits TE = 0 and  
RE = 0). Other SCI bits cleared by reset  
include: TIE, TCIE, RIE, ILIE, RWU, SBK,  
RDRF, IDLE, OR, NF, and FE.  
COP Watchdog Timer Reset  
Disable SPI (serial output enable control bit  
SPE = 0). Other SPI bits cleared by reset  
include: SPIE, MSTR, SPIF WCOL, and  
MODF.  
X
X
The CDP68HC05C16B contains an advanced version of the  
watchdog timer found in the CDP68HC05C4B and C8B families.  
The main purpose of this system is to guard against program  
runaway failures. The COP is a free-running resettable timer that  
will reset the MCU any time that it overflows (this is referred to as  
a time out). The COP reset will re-initialize the MCU just as if a  
hardware RESET has occurred. To keep the COP timer from  
resetting the MCU, the software must periodically reset it. A block  
diagram of the COP system is shown in Figure 12.  
Set serial status bits TDRE and TC  
X
X
X
X
Clear all serial interrupt enable bits (SPIE,  
TIE and TCIE)  
Place SPI system in slave mode (MSTR = 0)  
Clear SCI prescaler rate control bits  
X
X
X
X
32  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
B3, CME The Clock Monitor Enable bit turns on and off  
INTERNAL  
.
13  
.
CM1  
CM0  
2
CPU  
the clock monitor function of the COP system.  
When this bit is set (1) the clock monitor is on,  
and when it is clear (0) the clock monitor is off.  
This bit is readable at any time, but it may be  
written only once. This bit is cleared by reset.  
CLOCK  
15  
17  
2
2
19  
COP  
2
2
B2, COPE The Computer Operating Properly system Enable  
bit controls the operation of the COP system. Like  
the CME bit, this bit is readable at any time but  
may be written only once. As a part of the COP  
enable sequence, all three COP control bits  
(COPE, CM1 and CM0) must be written in the  
same write. When the COPE bit is set the COP  
system is on and when it is clear the COP system  
is off. This bit is cleared by reset.  
21  
.
.
.
.
.
.
.
2
.4  
COPRST  
.
2
.
2
.2  
.2  
.
2
.
FIGURE 12. COP BLOCK DIAGRAM  
The COP timer system consists of two registers: the COP  
reset register, COPRST, located at $1D, and the COP  
control register, COPCR, located at $1E.  
COP Reset Register (COPRST)  
B1, CM1 CM1 is used in along with CM0 to establish the  
COP and Wake Up Timer time out period. This  
bit is readable at any time. COPE, CM1 and  
CM0 must be written together and can be writ-  
ten only once after reset. See Table 4 for time  
out configurations.  
The COP reset register, located at $1D, is a write-only regis-  
ter that is used to reset the COP system before it times out.  
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
$1D  
B0, CM0 CM0 is used in along with CM1 to establish the  
COP and Wake Up Timer time out period. This  
bit is readable at any time. COPE, CM1 and  
CM0 must be written together and can be writ-  
ten only once after reset. See Table 4 for time  
out configurations.  
To reset the COP timer, a specific sequence of writes must  
be made to the COPRST register. This sequence is:  
• Write $55 to the COP reset register  
• Write $AA to the COP reset register  
Both of these write operations must occur in the order listed,  
but they do not need to be simultaneous. Any number of  
operations may be executed between the two writes, but  
both must occur before the COP times out. If the COP does  
time out, a system reset will occur and the MCU will start  
executing instructions as if coming out of a hardware reset.  
Reading this register does not return valid data.  
COP Operation in Special Modes  
If the COP system is enabled it will continue to function nor-  
mally even when the MCU goes into WAIT mode. Since all of  
the internal timers for the CPU still run under WAIT mode,  
the COP will generate a reset if the software does not peri-  
odically exit wait mode to reset the COP timer. If the MCU  
goes into STOP mode, however, all internal clocks (with the  
COP Control Register (COPCR)  
The COP system in the CDP68HC05C16B is controlled by exception of the Wake Up Timer RC oscillator) stop. Since  
the COP control register, located at $1E. The COPCR the COP timer is driven by the internal CPU clock, the COP  
register has the following functions:  
• Enables clock monitor functions  
• Enables COP functions  
will not time out. The timer will be reset when STOP mode is  
entered. If either a reset or IRQ is used to exit STOP mode  
the COP timer will be reset after a 4064 cycle delay. If a  
STOP instruction is inadvertently executed the COP timer  
will not provide a reset. For this condition software must  
relay on the Clock Monitor Reset.  
• Selects time out duration of the COP and flags the follow-  
ing conditions:  
• A COP timeout  
Clock Monitor Reset  
• A clock monitor reset  
The clock monitor system that is a part of the COP system is  
designed to reset the MCU if the internal CPU clock stops for  
any reason, including execution of the STOP instruction.  
When the CME bit the COP control register is set, the sys-  
tem monitors the CPU clock. If a clock is not detected within  
a certain time period, typically 5 to 100µs depending on pro-  
cessing parameters, a system reset is generated in the  
same way as if the COP timed out. The reset signal is issued  
to the external system through the RESET pin for four bus  
cycles if the clock is slow or until the clock recovers in the  
case where it is absent. If the MCU executes a STOP  
instruction while the Clock Monitor system is enabled, the  
7
0
6
0
5
0
4
3
2
1
0
COPF CME COPE CM1  
CM0  
$1E  
B7-B5  
Not implemented, always read as 0.  
B4, COPF The Computer Operation Properly Flag is used  
as an indicator that either a COP of clock moni-  
tor reset has occurred. If the COPF flag is set  
(1), then the MCU has reset itself due a COP  
time out. If the flag is clear (0), no COP reset  
has occurred. This bit is unaffected by reset and  
is cleared by reading the COPF register.  
33  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
TABLE 4. WAKE UP TIMER/COP TIMEOUT CONFIGURATIONS  
BITS IN COPCR  
COP SYSTEM TIMEOUT PERIODS (Note 53)  
WAKE UP TIMER SYSTEM TIMEOUT PERIODS (Note 54)  
10  
15  
f
/ 2  
TIMEOUT PERIOD TIMEOUT PERIOD  
= 2.0MHz = 4.0MHz  
f
/ 2  
rco  
TIMEOUT PERIOD TIMEOUT PERIOD  
= 10kHz = 20kHz  
op  
CM1  
CM0  
DIVIDE BY  
f
f
DIVIDE BY  
f
f
rco  
osc  
osc  
rco  
102.4ms  
0
0
1
0
1
1
4
32.77ms  
131.07ms  
524.29ms  
2.097s  
16.38ms  
65.54ms  
1
4
51.2ms  
204.8ms  
819.2ms  
3.277s  
0
409.6ms  
1.638s  
6.554s  
1
1
16  
64  
262.14m38s  
1.048s  
16  
64  
NOTES:  
14  
53. COP time-out periods have a tolerance of -0ms to +(2 /f )ms.  
osc  
54. The timeout period of the Wake Up Timer is dependent on the frequency of the RC oscillator, f . f varies with temperature and supply  
rco rco  
voltage. See Figure 17 for more details.  
TABLE 5. VECTOR ADDRESS FOR INTERRUPTS AND RESET  
REGISTER  
FLAG NAME  
INTERRUPTS  
Reset (External)  
CPU INTERRUPT  
VECTOR ADDRESS  
N/A  
N/A  
RESET  
$3FFE - $3FFF  
COPCR  
COPCR  
COPF  
COPF  
COP Time Out Reset  
Clock Monitor Reset  
N/A  
N/A  
Software  
SWI  
IRQ  
$3FFC - $3FFD  
$3FFA - $3FFB  
N/A  
WUTCR  
N/A  
WUTF  
External (IRQ or Port B)  
Wake Up Timer  
Timer Status  
ICF  
OCF  
TOF  
Input Capture  
Timer  
SCI  
$3FF8 - $3FF9  
$3FF6 - $3FF7  
Output Compare  
Timer Overflow  
SCI Status  
TDRE  
TC  
Transmit Buffer Empty  
Transmit Complete  
Receiver Buffer Full  
Idle Line Detect  
Overrun  
RDRF  
IDLE  
OR  
SPI Status  
SPIF  
Transfer Complete  
Mode Fault  
SPI  
$3FF4 - $3FF5  
MODF  
Clock Monitor will generate a CPU reset followed by a 4064 interrupt from occurring but does not inhibit the flag from  
cycle delay for oscillator stabilization. The bidirectional reset being set. Reset clears all enable bits to preclude interrupts  
pin will be held low for the entire 4064 cycles.  
during the reset procedure  
.
INTERRUPTS  
The general sequence for clearing an interrupt is a software  
sequence of first accessing the status register while the  
interrupt flag is set, followed by a read or write of an associ-  
ated register. When any of these interrupts occur, and if the  
enable bit is a logic one, normal processing is suspended at  
the end of the current instruction execution. Interrupts cause  
the processor registers to be saved on the stack (see  
Figure 9) and the interrupt mask (I bit) set to prevent addi-  
tional interrupts. The appropriate interrupt vector then points  
to the starting address of the interrupt service routine (refer  
to Figure 7 for vector location). Upon completion of the inter-  
rupt service routine, the RTI instruction (which is normally a  
part of the service routine) causes the register contents to  
be recovered from the stack followed by a return to normal  
processing. The stack order is shown in Figure 9. The inter-  
rupt mask bit (I bit) will be cleared if and only if the corre-  
sponding bit stored in the stack is zero.  
Systems often require that normal processing be interrupted  
so that some external event may be serviced. The  
CDP68HC05C16B may be interrupted by one of five differ-  
ent methods: either one of four maskable hardware inter-  
rupts (IRQ, SPI, SCI, or Timer) and one non-maskable  
software interrupt (SWI). The IRQ interrupt can be gener-  
ated from one of three sources: A low level or transition on  
the IRQ pin, a low level or transition on a Port B pin (if  
selected via a mask option), or a time out of the Wake Up  
Timer while the device is in STOP mode (See Figure 15A).  
Interrupts such as Timer, SPI, and SCI have several flags  
which will cause the interrupt. Generally, interrupt flags are  
located in read-only status registers, whereas their equiva-  
lent enable bits are located in associated control registers.  
The interrupt flags and enable bits are never contained in the  
same register. If the enable bit is a logic zero it blocks the  
34  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
FROMRESET  
IS  
I BIT  
SET?  
Y
N
IRQ  
EXTERNAL  
INTERRUPT  
CLEAR IRQ  
REQUEST  
LATCH  
Y
Y
N
STACK  
PC, X, A, CC  
TIMER  
INTERNAL  
INTERRUPT  
N
SET  
I BIT  
SCI  
EXTERNAL  
INTERRUPT  
Y
Y
LOAD PC FROM  
IRQ: $3FFA - $3FFB  
TIMER: $3FF8 - $3FF8  
SCI: $3FF6 - $3FF7  
SPI: $3FF4 - $3FF5  
N
SPI  
INTERNAL  
INTERRUPT  
COMPLETE  
INTERRUPT  
N
ROUTINE AND  
EXECUTE RTI  
EXECUTE  
INSTRUCTION  
FETCH NEXT  
INSTRUCTION  
FIGURE 13. HARDWARE INTERRUPT FLOW DIAGRAM  
STOP  
WAIT  
OSCILLATOR ACTIVE  
TIMER, SCI, AND SPI  
CLOCKS ACTIVE  
STOP OSCILLATOR  
AND ALL CLOCKS  
CLEAR I BIT AND WUTF  
PROCESSOR CLOCKS STOPPED  
N
N
RESET  
Y
RESET  
N
EXTERNAL  
INTERRUPT  
IRQ  
Y
EXTERNAL OR  
WAKE UP TIMER  
IRQ  
N
TIMER  
INTERRUPT  
Y
Y
Y
N
TURN ON OSCILLATOR  
WAIT FOR TIME  
DELAY TO STABILIZE  
RESTART  
PROCESSOR CLOCK  
SCI  
Y
INTERRUPT  
(1) FETCH RESET VECTOR OR  
(2) SERVICE INTERRUPT  
A. STACK  
(1) FETCH RESET VECTOR OR  
(2) SERVICE INTERRUPT  
A. STACK  
N
N
SPI  
B. SET I BIT  
C. VECTOR TO INTERRUPT  
ROUTINE  
B. SET I BIT  
C. VECTOR TO INTERRUPT  
ROUTINE  
INTERRUPT  
Y
FIGURE 14. STOP/WAIT FLOW DIAGRAM  
35  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
A table listing vector addresses for all interrupts including Software Interrupt (SWI)  
reset, in the MCU is provided in Table 5.  
The software interrupt is an executable instruction. The  
Hardware Controlled Interrupt Sequence  
action of the SWI instruction is similar to the hardware inter-  
rupts. The SWI is executed regardless of the state of the  
interrupt mask (I bit) in the condition code register. The inter-  
rupt service routine address is specified by the contents of  
memory location $3FFC and $3FFD.  
The following three functions (RESET, STOP, and WAIT) are  
not in the strictest sense an interrupt; however, they are  
acted upon in a similar manner. Flowcharts for hardware  
interrupts are shown in Figure 13, and for STOP and WAIT  
are provided in Figure 14. A discussion is provided below.  
External Interrupts (IRQ, Port B, Wake Up Timer)  
(a) A low input on the RESET input pin, a power-on, or a  
COP timeout causes the program to vector to its starting  
address which is specified by the contents of memory  
locations $3FFE and $3FFF. The I bit in the condition  
code register is also set. Much of the MCU is configured  
to a known state during this type of reset as previously  
described in RESETS paragraph.  
If the interrupt mask (I bit) of the condition code register has  
been cleared and the external interrupt pin (IRQ) has gone  
low, then the external interrupt is recognized. When the inter-  
rupt is recognized, the current state of the CPU is pushed  
onto the stack and I bit is set. This masks further interrupts  
until the present one is serviced. The interrupt service routine  
address is specified by the contents of memory location  
(b) STOP - The STOP instruction causes the oscillator to be $3FFA and $3FFB. Either a level-sensitive and negative edge-  
turned off and the processor to “sleep” until an external sensitive trigger, or a negative edge-sensitive only trigger are  
interrupt (IRQ) or reset occurs.  
available as a mask option. Figure 15 shows both a functional  
and mode timing diagram for the interrupt line. The timing dia-  
gram shows two different treatments of the interrupt line (IRQ)  
to the processor. The first method shows single pulses on the  
interrupt line spaced far enough apart to be serviced. The  
minimum time between pulses is a function of the number of  
cycles required to execute the interrupt service routine plus 21  
cycles. Once a pulse occurs, the next pulse should not occur  
until the MCU software has exited the routine (an RTI occurs).  
The second configuration shows several interrupt lines “wire-  
ORed” to form the interrupts at the processor. Thus, if after  
servicing one interrupt the interrupt line remains low, then the  
next interrupt is recognized.  
IRQ BIT, $3FDF  
V
DD  
EXTERNAL  
INTERRUPT  
REQUEST  
D
Q
Q
C
I BIT (CC)  
INTERRUPT  
PIN  
R
POWER-ON RESET  
EXTERNAL RESET  
PORT B  
IRQ PIN  
WAKE UP TIMER  
EXTERNAL INTERRUPT  
BEING SERVICED  
NOTE: The internal interrupt latch is cleared in the first part of the  
service routine; therefore, one (and only one) external interrupt pulse  
(READ OF VECTORS)  
FIGURE 15A. EXTERNAL INTERRUPT FUNCTION DIAGRAM  
could be latched during t  
cleared.  
and serviced as soon as the I bit is  
ILIL  
IRQ  
NOTE: The BIH and BIL instructions apply to the output of the logic  
OR of the Port B IRQ, IRQ pin and Wake Up Timer IRQ signals and  
can not be used to test the IRQ pin exclusively.  
t
ILIH  
t
ILIL  
IRQ1  
IRQn  
Timer Interrupt  
t
ILIH  
There are three different timer interrupt flags that will cause a  
timer interrupt whenever they are set and enabled. These three  
interrupt flags are found in the three most significant bits of the  
timer status register (TSR, location $13) and all three will vector  
to the same interrupt service routine ($3FF8 - $3FF9).  
NORMALLY  
USED WITH  
WIRE - ORed  
CONNECTION  
IRQ  
(MCU)  
All interrupt flags have corresponding enable bits (ICIE, OCIE,  
and TOIE) in the timer control register (TCR, location $12).  
Reset clears all enable bits, thus preventing an interrupt from  
occurring during the reset time period. The actual processor  
interrupt is generated only if the I bit in the condition code regis-  
ter is also cleared. When the interrupt is recognized, the current  
machine state is pushed onto the stack and I bit is set. This  
masks further interrupts until the present one is serviced. The  
interrupt service routine address is specified by the contents of  
memory location $3FF8 and $3FF9. The general sequence for  
clearing an interrupt is a software sequence of accessing the  
status register while the flag is set, followed by a read or write of  
an associated register. Refer to Programmable Timer for addi-  
tional information about the timer circuitry.  
NOTES:  
55. Edge-Sensitive Trigger Condition - The minimum pulse width (t  
I-  
= 3V). The period  
) is either 125ns (V  
LIH  
= 5V) or 250ns (V  
DD  
should be less than the number of t  
DD  
cycles it takes to ex-  
t
ILIL  
CYC  
CYC  
ecute the interrupt service routine plus 21 t  
cycles.  
56. Level-Sensitive Trigger Condition - If after servicing an interrupt  
the IRQ remains low, then the next interrupt is recognized.  
FIGURE 15B. EXTERNAL INTERRUPT MODE DIAGRAM  
(c) WAIT - The WAIT instruction causes all processor clocks  
to stop, but leaves the Timer, SCI, and SPI clocks run-  
ning. This “rest” state of the processor can be cleared by  
reset, an external interrupt (IRQ), Timer interrupt, SPI  
interrupt, or SCI interrupt.  
36  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Communications Interface (SCI) Interrupts  
WAKE UP TIMER  
An interrupt in the serial communications interface (SCI) occurs The Wake Up Timer of the CDP68HC05C16B is a counter  
o
when one of the interrupt flag bits in the serial communications driven by a low power (10µA typical at 25 C) RC oscillator  
status register is set, provided the I bit in the condition code reg- that can be used to “wake up” the CPU from STOP mode at  
ister is clear and the enable bit in the serial communications certain intervals. This oscillator for this circuit is completely  
control register 2 (locations $0F) is enabled. When the interrupt independent from the main CPU oscillator and therefore is  
is recognized, the current state of the machine is pushed onto unaffected by STOP mode. The Wake Up Timer is a mask  
the stack and the I bit in the condition code register is set. This programmable option that, if selected, is controlled by the  
masks further interrupts until the present one is serviced. The WUTE bit in the Wake Up Timer Control Register (WUTCR,  
SCI interrupt causes the program counter to vector to memory $1C) and by the CM1 and CM0 bits in the COP control regis-  
location $3FF6 and $3FF7 which contains the starting address ter (A diagram of the COPCR register along with bit assign-  
of the interrupt service routine. Software in the serial interrupt ments is shown in the COP Watchdog Timer Interrupt  
service routine must determine the priority and cause of the section). The flag bit for the system, WUTF, is located in the  
SCI interrupt by examining the interrupt flags and the status bits WUTCR. Wake Up Timer can be enabled or disabled at any  
located in the serial communications status register (location time by setting or clearing the WUTE bit. A block diagram of  
$10). The general sequence for clearing an interrupt is a soft- the Wake Up Timer is shown in Figure 16.  
ware sequence of accessing the serial communications status  
register while the flag is set followed by a read or write of an  
Wake Up Timer Control Register (WUTCR)  
The Wake Up Timer Register, WUTCR, is located at $1C. It  
contains two bits that control the operation of the Wake Up  
Timer.  
associated register. Refer to Serial Communications Inter-  
face for a description of the SCI system and its interrupts.  
Serial Peripheral Interface (SPI) Interrupts  
7
0
6
0
5
0
4
0
3
0
2
0
1
0
An interrupt in the serial peripheral interface (SPI) occurs when  
one of the interrupt flag bits in the serial peripheral status regis-  
ter (location $0B) is set, provided the I bit in the condition code  
register is clear and the enable bit in the serial peripheral con-  
trol register (location $0A) is enabled. When the interrupt is rec-  
ognized, the current state of the machine is pushed onto the  
stack and the I bit in the condition code register is set. This  
masks further interrupts until the present one is serviced. The  
SPI interrupt causes the program counter to vector to memory  
location $3FF4 and $3FF5 which contain the starting address  
of the interrupt service routine. Software in the serial peripheral  
interrupt service routine must determine the priority and cause  
of the SPI interrupt by examining the interrupt flag bits located  
in the SPI status register. The general sequence for clearing an  
interrupt is a software sequence of accessing the status regis-  
ter while the flag is set, followed by a read or write of an associ-  
ated register. Refer to Serial Communications Interface for a  
description of the SPI system and its interrupts.  
WUTF WUTE  
$1C  
B7-B2  
Not implemented, always read as 0.  
B1, WUTF The Wake Up Timer Flag is a read only bit that is  
set whenever the Wake Up Timer circuitry has  
timed out and brought the MCU out of STOP  
mode. This bit is cleared by resetting the MCU,  
reading the WUTCR register or entering STOP  
mode. As long as this flag is set the Wake Up  
Timer will hold the internal IRQ signal low.  
B0, WUTE The Wake Up Timer Enable bit is used to control  
the on chip Wake Up Timer. If this bit is set (and  
the Wake Up Timer mask option is selected) the  
Wake Up Timer is enabled when the MCU  
enters STOP mode. If this bit is clear the timer is  
disabled. This bit is cleared by reset and may be  
read and written at any time.  
LOW POWER MODES  
STOP Instruction  
RC  
.
8
2
.
CM1  
CM0  
OSCILLATOR  
The STOP instruction places the MCU in its lowest power con-  
sumption mode. In the STOP mode the main internal oscillator  
is turned off, causing all internal processing to be halted; refer  
to Figure 14. During the STOP mode, the I bit in the condition  
code register is cleared to enable external interrupts, the WUTF  
bit in the COP control register is cleared and the Wake Up/COP  
timer is reset. All other registers and memory remain unal-  
tered and all input/output lines remain unchanged. This contin-  
ues until the Wake Up Timer times out, an external interrupt  
(IRQ) or reset is sensed. When this happens, the internal oscil-  
lator is turned back on. If the source of the wake up is either an  
external interrupt (on the IRQ pin or from Port B interrupt) or a  
Wake Up Timer time-out, the program counter will vector mem-  
ory locations $3FFA and $3FFB. If the wake up source is an  
external reset, the program counter will vector to locations  
$3FFE and $3FFF. These memory locations ($3FFA, $3FFB  
and $3FFE, $3FFF) contain the starting address of the interrupt  
or reset service routines, respectively.  
10  
12  
2
2
IRQ  
WUTF  
14  
2
2
16  
.
.
.
.
.
.
.
.4  
.2  
.2  
.2  
.2  
.2  
.2  
STOP  
FIGURE 16. WAKE UP TIMER BLOCK DIAGRAM  
When the Wake Up Timer mask option is selected and the  
the WUTE bit in the WUTCR is set, the Wake Up Timer sys-  
tem will be enabled when the MCU enters STOP mode.  
When a STOP instruction is executed, the Wake Up Timer  
counter is cleared and the low power RC oscillator is pow-  
ered on (the RC oscillator stabilizes within one cycle so no  
start up delay is necessary). When the counter overflows,  
37  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
the WUTF bit is set and an IRQ is generated, thus bringing The time-out period of the Wake Up Timer is controlled by  
the MCU out of STOP mode. The MCU will react to the the frequency of the RC oscillator and by the state of the  
Wake Up Timer IRQ in the same way as if an external inter- CM0 and CM1 bits in the COPCR register. The frequency of  
rupt was generated, i.e., the MCU will vector to $3FFA and the RC oscillator is dependent on the supply voltage, V  
,
CC  
$3FFB. Software can distinguish the Wake Up Timer IRQ and the temperature of the chip. Figure 17 shows the fre-  
from an external IRQ by checking the WUTF bit. If the Wake quency output of the oscillator, f , for different values of  
rco  
Up Timer option is selected, it is important that the IRQ ser- voltage and temperature. Table 4 shows different timeout  
vice routine software read the WUTCR register to clear the configurations for the Wake Up Timer as set by the CM1 and  
WUTF bit. As long as the WUTF flag is set, the Wake Up CM0 bits in the COPCR. It is important to remember that the  
Timer system will hold the internal IRQ signal low. This will CM0 and CM1 bits control the timeout periods of both the  
cause the MCU to either continuously generate IRQ inter- Wake Up Timer AND the COP timer. Since the CM0 and  
rupts (if the IRQ sensitivity is set to EDGE/LEVEL) or mask CM1 bits are writable only once after reset, the user must  
all IRQ requests (if IRQ sensitivity is set to EDGE only). If consider both the desired COP and Wake Up Timer timeout  
the Wake Up Timer mask option is not selected the WUTF periods when setting these bits. Also, since the COP enable  
will never affect the IRQ circuitry of the device. The WUTF bit bit, COPE, is also a write once only bit, it must be set during  
is cleared when the WUTCR register is read, when the MCU the same write as the CM1 and CM0 bits. In contrast, the  
enters STOP mode, or if the device is reset. The MCU can Wake Up Timer enable bit, WUTE, is writable at any time. If  
be brought out of STOP mode before the Wake Up TImer the user is not using the COP, the CM1 and CM0 bits only  
times out by either an external RESET or IRQ.  
affect the Wake Up Timer. These bits are, however, still writ-  
able only once. Finally, due to the 68HC05 architecture, a bit  
set or bit clear instruction (BSET or BCLR) to any bit in the  
COPCR will cause the CPU to write an entire byte to the reg-  
ister, causing all write-once only bits to become read-only.  
The initial write to the COPCR should always be a full byte  
write (i.e., STA $1E).  
o
25 C  
30  
25  
20  
15  
10  
5
o
85 C  
WAIT Instruction  
The WAIT instruction places the MCU in a low power con-  
sumption mode, but the WAIT mode consumes somewhat  
more power than the STOP mode. In the WAIT mode, the  
internal clock remains active, and all CPU processing is  
stopped; however, the COP timer, programmable timer,  
serial peripheral interface, and serial communications inter-  
face systems remain active. Refer to Figure 14. During the  
WAIT mode, the I bit in the condition code register is cleared  
to enable all interrupts. All other registers and memory  
remain unaltered and all parallel input/output lines remain  
unchanged. This continues until any interrupt or reset is  
sensed. At this time the program counter vectors to the  
memory location ($1FF4 through $1FFF) which contains the  
starting address of the interrupt or reset service routine.  
0
1
2
3
4
5
6
V
, SUPPLY VOLTAGE (V)  
CC  
FIGURE 17. RC OSCILLATOR VOLTAGE/FREQUENCY CURVE  
DATA RETENTION MODE  
The contents of RAM and CPU registers are retained at sup-  
ply voltages as low as 1.5V. This is referred to as the DATA  
RETENTION mode, where the data is held, but the device is  
not guaranteed to operate.  
38  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
MCU INTERNAL BUS  
INTERNAL  
8-BIT  
BUFFER  
PROCESSOR  
CLOCK  
HIGH  
BYTE BYTE  
LOW  
HIGH  
BYTE  
HIGH LOW  
BYTE BYTE  
LOW  
BYTE  
÷4  
16 - BIT FREE  
RUNNING  
COUNTER  
INPUT  
CAPTURE  
REGISTER  
OUTPUT  
COMPARE  
REGISTER  
$16  
$17  
$18  
$19  
$14  
$15  
COUNTER  
ALTERNATE  
REGISTER  
$1A  
$1B  
OUTPUT  
COMPARE  
CIRCUIT  
OVERFLOW  
DETECT  
CIRCUIT  
EDGE  
DETECT  
CIRCUIT  
D
Q
CLK  
C
OUTPUT  
LEVEL REG.  
TIMER  
STATUS  
REG.  
$13  
ICF OCF TOF  
ICIE OCIE TOIE IEDG OLVL  
RESET  
TIMER  
CONTROL  
REG.  
OUTPUT EDGE  
LEVEL INPUT  
(TCMP (TCAP  
PIN 35) PIN 37)  
INTERRUPT  
CIRCUIT  
$12  
FIGURE 18. PROGRAMMABLE TIMER BLOCK DIAGRAM  
Programmable Timer  
INTRODUCTION  
Output Compare High Register location $16,  
Output Compare Low Register location $17,  
Counter High Register location $18,  
The programmable timer, which is preceded by a fixed  
divide-by-four prescaler, can be used for many purposes,  
including input waveform measurements while simulta-  
neously generating an output waveform. Pulse widths can  
vary from several microseconds to many seconds. A block  
diagram of the timer is shown in Figure 18 and timing dia-  
grams are shown in Figures 19 through 22.  
Counter Low Register location $19,  
Alternate Counter High Register location $1A, and  
Alternate Counter Low Register location $1B.  
COUNTER  
The key element in the programmable timer is a 16-bit free run-  
ning counter, or counter register, preceded by a prescaler which  
divides the internal processor clock by four. The prescaler gives  
the timer a resolution of 2.0ms if the internal processor clock is  
2.0MHz. The counter is clocked to increasing values during the  
low portion of the internal processor clock. Software can read  
the counter at any time without affecting its value.  
Because the timer has a 16-bit architecture, each specific  
functional segment (capability) is represented by two regis-  
ters. These registers contain the high and low byte of that  
functional segment. Generally, accessing the low byte of a  
specific timer function allows full control of that function;  
however, an access of the high byte inhibits that specific  
timer function until the low byte is also accessed  
The double byte free running counter can be read from either of  
two locations $18 - $19 (called counter register at this location),  
or $1A - $1B (counter alternate register at this location). A read  
of only the least significant byte (LSB) of the free running  
NOTE: The I bit in the condition code register should be set while ma-  
nipulating both the high and low byte register of a specific timer function  
to ensure that an interrupt does not occur. This prevents interrupts from  
occurring between the time that the high and low bytes are accessed.  
The programmable timer capabilities are provided by using counter ($19, $1B) retrieves the current count value. If a read of  
the following ten addressable 8-bit registers (note the high the free running counter first addresses the most significant  
and low represent the significance of the byte). A description byte ($18, $1A) the least significant byte is transferred to a  
of each register is provided below.  
buffer. This buffer value remains fixed after the first most signifi-  
cant byte “read” even if the user reads the most significant byte  
several times. This buffer is accessed when reading the LSB of  
the free running counter or counter alternate register ($19,  
$1B), if the most significant byte is read, the least significant  
byte must also be read in order to complete the sequence.  
Timer Control Register (TCR) locations $12,  
Timer Status Register (TSR) location $13,  
Input Capture High Register location $14,  
Input Capture Low Register location $15,  
39  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
INTERNAL PROCESSOR CLOCK  
(INTERNAL RESET)  
T00  
T01  
INTERNAL TIMER CLOCKS  
T10  
T11  
COUNTER (16 - BIT)  
$FFFC  
$FFFD  
$FFFE  
$FFFF  
RESET (EXTERNAL OR END OF POR)  
NOTE:  
57. The Counter Register and the Timer Control Register are the only ones affected by RESET.  
FIGURE 19. TIMER STATE DIAGRAM FOR RESET  
INTERNAL PROCESSOR  
CLOCK  
T00  
T01  
INTERNAL TIMER  
CLOCKS  
T10  
T11  
COUNTER (16 - BIT)  
INPUT EDGE  
$FFEB  
$FFEC  
$FFED  
$FFEE  
$FFEF  
(SEE NOTE)  
INTERNAL CAPTURE LATCH  
INPUT CAPTURE REGISTER  
$????  
$FFED  
INPUT CAPTURE FLAG  
NOTE:  
58. If the input edge occurs in the shaded area from one timer state T10 to the next, the input capture flag is set during the next T11.  
FIGURE 20. TIMER STATE DIAGRAM FOR INPUT CAPTURE  
40  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
INTERNAL PROCESSOR CLOCK  
T00  
T01  
INTERNAL TIMER  
T10  
T11  
COUNTER (16 - BIT)  
COMPARE REGISTER  
$FFEB  
$FFEC  
$FFED  
$FFEE  
$FFED  
$FFEF  
(NOTE 59)  
CPU WRITES $FFED  
(NOTE 60)  
COMPARE REGISTER  
LATCH  
OUTPUT COMPARE  
FLAG (OCF) AND  
TCMP (PIN 35)  
(NOTE 61)  
NOTES:  
59. The CPU write to the Compare Register may take place at any time, but a compare only occurs at timer state T01. Thus a 4 cycle differ-  
ence may exist between the write to the Compare Register and the actual compare.  
60. Internal compare takes place during timer state T01.  
61. OCF is set at the timer state T11 which follows the comparison match ($FFED in this example).  
FIGURE 21. TIMER STATE DIAGRAM FOR OUTPUT COMPARE  
INTERNAL PROCESSOR CLOCK  
T00  
T01  
INTERNAL TIMER  
T10  
T11  
COUNTER (16 - BIT)  
$FFFE  
$FFFF  
$0000  
$0001  
$0002  
TIMER OVERFLOW  
FLAG (TOF)  
NOTE:  
62. The TOF bit is set at timer state T11 (transition of the counter from $FFFF to $0000). It is cleared by a read of the Timer Status Register  
during the internal processor clock high time followed by a read of the Counter Low Register.  
FIGURE 22. TIMER STATE DIAGRAM FOR TIMER OVERFLOW  
41  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
The free running counter is configured to $FFFC during The advantage of this procedure is to prevent the OCF bit  
reset and is always a read-only register. During a power-on- from being set between the time it is read and the write to  
reset (POR) or a CAP Reset, the counter is also configured the output compare register. A software example is shown  
to $FFFC and begins running after the oscillator start up below.  
delay. Because the free running counter is 16 bits preceded  
B716  
B613  
BF17  
STA  
LDA  
STX  
OCMPHI;  
TSTAT;  
INHIBIT OUTPUT COMPARE  
ARM OCF BIT IF SET  
by a fixed divide-by-four prescaler, the value in the free run-  
ning counter repeats every 262,144 MPU internal processor  
clock cycles. When the counter rolls over from $FFFF to  
$0000, the timer overflow flag (TOF) bit is set. An interrupt  
can also be enabled when counter roll-over occurs by setting  
its interrupt enable bit (TOIE).  
OCMPLO;  
READY FOR NEXT COMPARE  
The state of the TCMP output pin can be read internally as  
bit 6 of Port D. This location is read only, so the TCMP output  
can not be set by a write to the Port D data register. Also,  
there is no data direction bit in the Port D DDR register ($07)  
to be set for the TCMP; this pin is always an output.  
OUTPUT COMPARE REGISTER  
The output compare register is a 16-bit register, which is made  
up of two 8-bit registers at locations $16 (most significant byte)  
and $17 (least significant byte). The output compare register  
can be used for several purposes such as, controlling an output  
waveform or indicating when a period of time has elapsed. The  
output compare register is unique in that all bits are readable  
and writable and are not altered by the timer hardware. Reset  
does not affect the contents of this register and if the compare  
function is not utilized, the two bytes of the output compare reg-  
ister can be used as storage locations. The contents of the out-  
put compare register are compared with the contents of the free  
running counter once during every four internal processor  
clocks. If a match is found, the corresponding output compare  
flag (OCF) bit is set and the corresponding output level (OLVL)  
bit is clocked (by the output compare circuit pulse) to an output  
level register. The values in the output compare register and the  
output level bit should be changed after each successful com-  
parison in order to control an output waveform or establish a  
INPUT CAPTURE REGISTER  
The two 8-bit registers which make up the 16-bit input cap-  
ture register are read-only and are used to latch the value of  
the free running counter after a defined transition is sensed  
by the corresponding input capture edge detector. The level  
transition which triggers the counter transfer is defined by  
the corresponding input edge bit (IEDG). Reset does not  
affect the contents of the input capture register.  
The result obtained by an input capture will be one more  
than the value of the free running counter on the rising edge  
of the internal processor clock preceding the external transi-  
tion (refer to timing diagram shown in Figure 20). This delay  
is required for internal synchronization. Resolution is  
affected by the prescaler allowing the timer to only increment  
every four internal processor clock cycles.  
new elapsed timeout. An interrupt can also accompany a suc- After a read of the most significant byte of the input capture  
cessful output compare provided the corresponding interrupt register ($14), counter transfer is inhibited until the least sig-  
enable bit, OCIE, is set.  
nificant byte ($15) of the input capture register is also read.  
This characteristic forces the minimum pulse period attain-  
able to be determined by the time used in the capture soft-  
ware routine and its interaction with the main program. The  
free running counter increments every four internal proces-  
sor clock cycles due to the prescaler.  
After a processor write cycle to the output compare register  
containing the most significant byte ($16), the output compare  
function is inhibited until the least significant byte ($17) is also  
written. The user must write both bytes (locations) if the most  
significant byte is written first. A write made only to the least  
significant byte ($17) will not inhibit the compare function. The A read of the least significant byte ($15) of the input capture  
free running counter is updated every four internal processor register does not inhibit the free running counter transfer.  
clock cycles due to the internal prescaler. The minimum time Again, minimum pulse periods are ones which allow soft-  
required to update the output compare register is a function of ware to read the least significant byte ($15) and perform  
the software program rather than the internal hardware.  
needed operations. There is no conflict between the read of  
the input capture register and the free running counter trans-  
fer since they occur on opposite edges of the internal pro-  
cessor clock.  
A processor write may be made to either byte of the output  
compare register without affecting the other byte. The output  
level (OLVL) bit is clocked to the output level register regard-  
less of whether the output compare flag (OCF) is set or clear.  
TIMER CONTROL REGISTER (TCR)  
The timer control register (TCR, location $12) is an 8-bit  
read/write register which contains five control bits. Three of  
these bits control interrupts associated with each of the  
three flag bits found in the timer status register (discussed  
below). The other two bits control: 1) which edge is signifi-  
cant to the capture edge detector (i.e., negative or positive),  
and 2) the next value to be clocked to the output level regis-  
Because neither the output compare flag (OCF bit) or output  
compare register is affected by reset, care must be exer-  
cised when initializing the output compare function with soft-  
ware. The following procedure is recommended:  
1. Write the high byte of the output compare register to inhibit  
further compares until the low byte is written.  
2. Read the timer status register to arm the OCF if it is ter in response to a successful output compare. The timer  
already set.  
control register and the free running counter are the only  
sections of the timer affected by reset. The TCMP pin is  
forced low during external reset and stays low until a valid  
compare changes it to a high. The timer control register is  
3. Write the output compare register low byte to enable the  
output compare function with the flag clear.  
42  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
illustrated below followed be a definition of each bit. The The timer status register is illustrated below followed by a  
grayed out areas denote bits that are not used in this register definition of each bit. Refer to timing diagrams shown in Fig-  
and are always read as zero.  
ures 19, 20, and 21 for timing relationship to the timer status  
register bits.  
7
6
5
4
0
3
0
2
0
1
0
7
6
5
4
0
3
0
2
0
1
0
0
0
ICIE OCIE TOIE  
IEDG OLVL $12  
ICF OCF TOF  
$13  
B7, ICIE  
If the input capture interrupt enable (ICIE) bit is  
set, a timer interrupt is enabled when the ICF  
status flag (in the timer status register) is set. If  
the ICIE bit is clear, the interrupt is inhibited. The  
ICIE bit is cleared by reset.  
B7, ICF  
The input capture flag (ICF) is set when a proper  
edge has been sensed by the input capture  
edge detector. It is cleared by a processor  
access of the timer status register (with ICF set)  
followed by accessing the low byte ($15) of the  
input capture register. Reset does not affect the  
input compare flag.  
B6, OCIE If the output compare interrupt enable (OCIE) bit  
is set, a timer interrupt is enabled whenever the  
OCF status flag is set. If the OCIE bit is clear,  
the interrupt is inhibited. The OCIE bit is cleared  
by reset.  
B6, OCF The output compare flag (OCF) is set when the  
output compare register contents match the  
contents of the free running counter. The OCF is  
cleared by accessing the timer status register  
(with OCF set) and then accessing the low byte  
($17) of the output compare register. Reset does  
not affect the output compare flag.  
B5, TOIE If the timer overflow interrupt enable (TOIE) bit is  
set, a timer interrupt is enabled whenever the  
TOF status flag (in the timer status register) is  
set. If the TOIE bit is clear, the interrupt is inhib-  
ited. The TOIE bit is cleared by reset.  
B5, TOF  
The timer overflow flag (TOF) bit is set by a tran-  
sition of the free running counter from $FFFF to  
$0000. It is cleared by accessing the timer sta-  
tus register (with TOF set) followed by an access  
of the free running counter least significant byte  
($19). Reset does not affect the TOF bit.  
B4-B2  
Not implemented, always read as 0.  
B1, IEDG The value of the input edge (IEDG) bit determines  
which level transition on pin 37 will trigger a free  
running counter transfer to the input capture regis-  
ter. Reset does not affect the IEDG bit.  
0 = negative edge  
B4-B0  
Not implemented, always read as 0.  
1 = positive edge  
Accessing the timer status register satisfies the first condi-  
tion required to clear any status bits which happen to be set  
during the access. The only remaining step is to provide an  
access of the register which is associated with the status  
bit. Typically, this presents no problem for the input capture  
and output compare functions.  
B0, OLVL The value of the output level (OLVL) bit is  
clocked into the output level register by the next  
successful output compare and will appear at  
pin 35. This bit and the output level register are  
cleared by reset.  
0 = low output  
1 = high output  
A problem can occur when using the timer overflow func-  
tion and reading the free running counter at random times  
to measure an elapsed time. Without incorporating the  
proper precautions into software, the timer overflow flag  
could unintentionally be cleared if: 1) the timer status reg-  
ister is read or written when TOF is set, and 2) the least  
significant byte of the free running counter is read but not  
for the purpose of servicing the flag. The counter alternate  
register at address $1A and $1B contains the same value  
as the free running counter (at address $18 and $19);  
therefore, this alternate register can be read at any time  
without affecting the timer overflow flag in the timer status  
register.  
TIMER STATUS REGISTER (TSR)  
The timer status register (TSR) is an 8-bit register of which  
the three most significant bits contain read-only status  
information. These three bits indicate the following:  
1. A proper transition has taken place at pin 37 with an ac-  
companying transfer of the free running counter contents  
to the input capture register,  
2. A match has been found between the free running counter  
and the output compare register, and  
During STOP and WAIT instructions, the programmable  
timer functions as follows: during the wait mode, the timer  
continues to operate normally and may generate an inter-  
rupt to trigger the CPU out of the wait state; during the stop  
mode, the timer holds at its current state, retaining all data,  
and resumes operation from this point when an external  
interrupt is received.  
3. A free running counter transition from $FFFF to $0000 has  
been sensed (timer overflow).  
43  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Communications Interface (SCI)  
CONTROL BIT ‘M’  
SELECTS 8 OR 9  
BIT DATA  
INTRODUCTION  
A full-duplex asynchronous serial communications interface  
(SCI) is provided with a standard NRZ format and a variety  
of baud rates. The SCI transmitter and receiver are function-  
ally independent, but use the same data format and bit rate.  
The serial data format is standard mark/space (NRZ) which  
provides one start bit, eight or nine data bits, and one stop  
bit. “Baud” and “bit rate” are used synonymously in the fol-  
lowing description.  
0
1
2
3
4
5
6
7
8
0
IDLE LINE  
S
T
A
R
T
S
T
O
P
S
T
A
R
T
NOTE: Stop bit is always high  
FIGURE 23. DATA FORMAT  
SCI Two Wire System Features  
• Standard NRZ (mark/space) format  
WAKE-UP FEATURE  
• Advanced error detection method includes noise detection  
for noise duration of up to 1/16 bit time.  
In a typical multiprocessor configuration, the software protocol  
will usually identify the addressee(s) at the beginning of the  
message. In order to permit uninterested MPUs to ignore the  
remainder of the message, a wake-up feature is included  
whereby all further SCI receiver flag (and interrupt) process-  
ing can be inhibited until its data line returns to the idle state.  
An SCI receiver is re-enabled by an idle string of at least ten  
(or eleven) consecutive ones. Software for the transmitter  
must provide for the required idle string between consecutive  
messages and prevent it from occurring within messages.  
• Full-duplex operation (simultaneous transmit and receive)  
• Software programmable for one of 32 different baud rates  
• Software selectable word length (eight or nine bit words)  
• Separate transmitter and receiver enable bits.  
• SCI may be interrupt driven  
• Four separate enable bits available for interrupt control  
SCI Receiver Features  
• Receiver wake-up function (idle or address bit)  
• Idle line detect  
• Framing error detect  
• Noise detect  
The user is allowed a second method of providing the wake-  
up feature in lieu of the idle string discussed above. This  
method allows the user to insert a logic one in the most sig-  
nificant bit of the transmit data word which needs to be  
received by all “sleeping” processors.  
• Overrun detect  
• Receiver data register full flag  
RECEIVE DATA IN  
SCI Transmitter Features  
Transmit data register empty flag  
Transmit complete flag  
• Break send  
Receive data in is the serial data which is presented from the  
input pin via the SCI to the internal data bus. While waiting  
for a start bit, the receiver samples the input at a rate which  
is 16 times higher than the set baud rate. This 16 times  
higher-than-baud rate is referred to as the RT rate in Figures  
24 and 25, and as the receiver clock in Figure 29. When the  
input (idle) line is detected low, it is tested for three more  
sample times (referred to as the start edge verification sam-  
ples in Figure 24). If at least two of these three verification  
samples detect a logic low, a valid start bit is assumed to  
have been detected (by a logic low following the three start  
qualifiers) as shown in Figure 24; however, if in two or more  
of the verification samples a logic high is detected, the line is  
assumed to be idle. (A noise flag is set if one of the three  
verification sample detects a logic high, thus a valid start bit  
could be assumed and a noise flag still set.) The receiver  
clock generator is controlled by the baud rate register (see  
Figures 28 and 29; however, the serial communications  
interface is synchronized by the start bit (independent of the  
transmitter).  
Any SCI two-wired system requires receive data in (RDI) and  
transmit data out (TDO).  
NOTE: Unlike the SPI port pins, the SCI output pin (TDO) does NOT  
require that the associated DDRD1 be set. This pin will be forced to  
an output state when the SCI is enabled.  
DATA FORMAT  
Receive data in (RDI) or transmit data out (TDO) is the serial  
data which is presented between the internal data bus and  
the output pin (TDO), and between the input pin (RDI) and  
the internal data bus. Data format is as shown for the NRZ in  
Figure 23 and must meet the following criteria:  
1. A high level indicates a logic one and a low level indicates  
a logic zero.  
2. The idle line is in a high (logic one) state prior to transmis-  
sion/reception of a message.  
Once a valid start bit is detected, the start bit, each data bit,  
and the stop bit are sampled three times at RT intervals of  
8RT, 9RT, and 10RT (1RT is the position where the bit is  
expected to start as shown in Figure 25. The value of the bit is  
determined by voting logic which takes the value of the major-  
ity of samples (two or three out of three). A noise flag is set  
when all three samples on a valid start bit or a data bit or the  
stop bit do not agree.  
3. A start bit (logic zero) is transmitted/received indicating the  
start of a message.  
4. The data is transmitted and received least-significant-bit first.  
5. A stop bit (high in the tenth or eleventh bit position) indi-  
cates the byte is complete.  
6. A break is defined as the transmission or reception of a low  
(logic zero) for some multiple of the data format.  
44  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
16x INTERNAL SAMPLING CLOCK  
1
R
T
2
R
T
3
R
T
4
R
T
5
R
T
6
R
T
7
R
T
8
R
T
RT CLOCK EDGES (FOR ALL THREE EXAMPLES)  
RD11  
START  
1
1
1
1
1
1
1
1
1
1
0
0
0
0
START  
QUALIFIERS  
START EDGE VERIFICATION SAMPLES  
NOISE  
IDLE  
RD12  
RD13  
START  
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
IDLE  
NOISE  
START  
0
1
0
1
1
FIGURE 24. EXAMPLES OF START BIT SAMPLING TECHNIQUE  
START BIT DETECTION FOLLOWING A FRAMING ERROR  
PREVIOUS BIT  
RDI  
PRESENT BIT  
SAMPLES  
NEXT BIT  
V
V
V
If there has been a framing error without detection of a break  
(10 zeros for 8-bit format or 11 zeros for 9-bit format), the circuit  
continues to operate as if there actually were a stop bit and the  
start edge will be placed artificially. The last bit received in the  
data shift register is inverted to a logic one, and the three logic  
one start qualifiers (shown in Figure 24) are forced into the  
sample shift register during the interval when detection of a  
start bit is anticipated (see Figure 26); therefore the start bit will  
be accepted no sooner than it is anticipated.  
16  
R
T
1
R
T
8
R
T
9
R
T
10  
R
T
16  
R
T
1
R
T
FIGURE 25. DATA FORMAT  
EXPECTED  
STOP  
ARTIFICIAL  
EDGE  
DATA  
RECEIVE  
DATA IN  
START BIT  
If the receiver detects that a break (RDRF = 1, FE = 1,  
receiver data register = $00) produced the framing error, the  
start bit will not be artificially induced and the receiver must  
actually receive a logic one bit before start. See Figure 27.  
DATA  
DATA SAMPLES  
FIGURE 26A. CASE 1, RECEIVE LINE LOW DURING  
ARTIFICIAL EDGE  
REGISTERS  
There are five different registers used in the serial communi-  
cations interface (SCI) and the internal configuration of these  
registers is discussed in the following paragraphs. A block  
diagram of the SCI system is shown in Figure 28.  
EXPECTED  
STOP  
START EDGE  
DATA  
RECEIVE  
DATA IN  
START BIT  
Serial Communications Data Register (SCDAT)  
DATA  
DATA SAMPLES  
7
6
5
4
3
2
1
0
FIGURE 26B. CASE 2, RECEIVE LINE HIGH DURING  
EXPECTED START EDGE  
Serial Communications Data Register  
$11  
FIGURE 26. SCI ARTIFICIAL START FOLLOWING A FRAMING  
ERROR  
The serial communications data register performs two  
functions in the serial communications interface; i.e. it acts  
as the receive data register when it is read and as the  
transmit data register when it is written. Figure 28 shows  
the register as two separate registers, namely: the receive  
data register (RDR) and the transmit data register (TDR).  
As shown in Figure 28, the TDR (transmit data register)  
provides the parallel interface from the internal data bus to  
the transmit shift register and the receive data register  
(RDR) provides the interface from the receive shift register  
to the internal data bus.  
EXPECTED  
STOP  
DETECTED AS  
VALID START EDGE  
BREAK  
START BIT  
RECEIVE  
DATA IN  
START START EDGE  
QUALI- VERIFICATION  
DATA SAMPLES  
FIER  
SAMPLER  
FIGURE 27. SCI START BIT FOLLOWING A BREAK  
45  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
SCI INTERRUPT  
INTERNAL BUS  
$0F  
SCCR2  
TRANSMIT  
DATA  
REGISTER  
RECEIVE  
DATA  
REGISTER  
(SEE  
NOTE)  
(SEE  
TIE  
$11  
$11  
NOTE)  
TCIE  
RIE  
TDO  
(PD1,  
PIN 30)  
ILIE  
TE  
TRANSMIT  
DATA  
SHIFT  
RECEIVE  
DATA  
SHIFT  
RE  
SBK  
RWU  
REGISTER  
REGISTER  
RDI  
(PD0,  
PIN 29)  
2
SCSR  
$10  
FE  
NF  
OR  
IDLE RDRF TC  
TDRE  
WAKE  
UP  
UNIT  
7
SBK  
TE  
TRANSMIT  
CONTROL  
FLAG  
CONTROL  
RECEIVE  
CONTROL  
INTERNAL  
PROCESSOR  
CLOCK  
RATE GENERATOR  
BAUD  
RATE  
REGISTER  
$0D  
-
-
SCP1  
-
SCR2 SCR1 SCR0  
SCP0  
$0E  
SCCR1  
R8  
T8  
-
M
WAKE  
-
-
-
NOTE: The serial communications data register (SCDAT) is controlled by the internal R/W signal it is the transmit data register when written  
and receive data register when read.  
FIGURE 28. SERIAL COMMUNICATIONS INTERFACE BLOCK DIAGRAM  
When SCDAT is written, it becomes the transmit data regis- Serial Communications Control Register 1 (SCCR1)  
ter and contains the next byte of data to be transmitted. The  
7
6
5
0
4
3
2
0
1
0
0
transmit data register, also represented above, is a write-  
only register containing the next byte of data to be applied to  
the transmit shift register from the internal data bus. As long  
as the transmitter is enabled, data stored in the serial com-  
munications data register is transferred to the transmit shift  
register (after the current byte in the shift register has been  
transmitted). The transfer from the SCDAT to the transmit  
shift register is synchronized with the bit rate clock (from the  
transmit control) as shown in Figure 28. All data is transmit-  
ted least-significant-bit first.  
R8  
T8  
M
WAKE  
0
$0E  
The serial communications control register 1 (SCCR1) pro-  
vides the control bits which: 1) determine the word length  
(either 8 or 9 bits), and 2) selects the method used for the  
wake-up feature. Bits 6 and 7 provide a location for storing  
the ninth bit for longer bytes.  
B7, R8  
If the M bit is a one, then this bit provides a stor-  
age location for the ninth bit in the receive data  
byte. Reset does not affect this bit.  
46  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
B6, T8  
If the M bit is one, then this bit provides a stor- B4, ILIE  
age locations for the ninth bit in the transmit data  
byte. Reset does not affect this bit.  
When the idle line interrupt enable bit is set, the  
SCI interrupt occurs provided IDLE is set (see  
Figure 28). When ILIE is clear, the IDLE interrupt  
is disabled. Reset clears the ILIE bit.  
B5, B2-B0 Not implemented, always read as 0.  
B3, TE  
When the transmit enable bit is set, the transmit  
shift register output is applied to the TDO line.  
Depending on the state of control bit M in serial  
communications control register 1, a preamble of  
10(M = 0) or 11(M = 1) consecutive ones is trans-  
mitted when software sets the TE bit from a  
cleared state. If a transmission is in progress, and  
TE is written to a zero, then the transmitter will wait  
until after the present byte has been transmitted  
before placing the TDO pin in the idle high-imped-  
ance state. If the TE pin has been written to a zero  
and then set to a one before the current byte is  
transmitted, the transmitter will wait until that byte  
is transmitted and will then initiate transmission of  
a new preamble. After the preamble is transmitted,  
and provided the TDRE bit is set (no new data to  
transmit), the line remains idle (driven high while  
TE = 1); otherwise, normal transmission occurs.  
This function allows the user to “neatly” terminate  
a transmission sequence. After loading the last  
byte in the serial communications data register  
and receiving the interrupt from TDRE, indicating  
the data has been transferred into the shift register,  
the user should clear TE. The last byte will then be  
transmitted and the line will go idle (high imped-  
ance). Reset clears the TE bit.  
B4, M The option of the word length is selected by the  
configuration of this bit and is shown below.  
Reset does not affect this bit. 0 = 1 start bit, 8  
data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1  
stop bit  
B3, WAKE This bit allows the user to select the method for  
receiver “wake up”. If the WAKE bit is a logic zero,  
an idle line condition will “wake up” the receiver. If  
the WAKE bit is set to a logic one, the system  
acknowledges an address bit (most significant  
bit). The address bit is dependent on both the  
WAKE bit and the M bit level (table shown below).  
(Additionally, the receiver does not use the wake-  
up feature unless the RWU control bit in serial  
communications control register 2 is set as dis-  
cussed below.) Reset does not affect this bit.  
WAKE  
M
METHOD OF RECEIVER “WAKE-UP”  
0
X
Detection of an idle line allows the next  
data byte received to cause the receive  
data register to fill and produce an  
RDRF flag.  
1
1
0
1
Detection of a received one in the  
eighth data bit allows an RDRF flag and  
associated error flags.  
Detection of a received one in the ninth  
data bit allows an RDRF flag and asso-  
ciated error flags.  
B2, RE  
When the receive enable bit is set, the receiver  
is enabled. When RE is clear, the receiver is dis-  
abled and all of the status bit associated with the  
receiver (RDRF, IDLE, OR, NF, and FE) are  
inhibited. Reset clears the RE bit.  
Serial Communications Control Register 2 (SCCR2)  
7
6
5
4
3
2
1
0
B1, RWU When the receiver wake-up bit is set, it enables  
the “wake up” function. The type of “wake up”  
mode for the receiver is determined by the  
WAKE bit discussed above (in the SCCR1).  
When the RWU bit is set, no status flags will be  
set. Flags which were set previously will not be  
cleared when RWU is set. If the WAKE bit is  
cleared, RWU is cleared after receiving 10(M = 0)  
or 11(M = 1) consecutive ones. Under these condi-  
tions, RWU cannot be set if the line is idle. If the  
WAKE bit is set, RWU is cleared after receiving an  
address bit. The RDRF flag will then be set and  
the address byte will be stored in the receiver data  
register. Reset clears the RWU bit.  
TIE TCIE RIE  
ILIE  
TE  
RE RWU SBK $0F  
The serial communications control register 2 (SCCR2) pro-  
vides the control bits which: individually enable/disable the  
transmitter or receiver, enable the system interrupts, and  
provide the wake-up enable bit and a “send break code” bit.  
Each of these bits is described below. (The individual flags  
are discussed in the Serial Communications Status Reg-  
ister Section.)  
B7, TIE  
When the transmit interrupt enable bit is set, the  
SCI interrupt occurs provided TDRE is set (see  
Figure 28). When TIE is clear, the TDRE interrupt  
is disabled. Reset clears the TIE bit.  
B6, TCIE When the transmission complete interrupt B0, SBK  
enable bit is set, the SCI interrupt occurs pro-  
vided TC is set (see Figure 28). When TCIE is  
clear, the TC interrupt is disabled. Reset clears  
the TCIE bit.  
When the send break bit is set the transmitter  
sends zeros in some number equal to a multiple of  
the data format bits. If the SBK bit is toggled set  
and clear, the transmitter sends 10(M = 0) or 11(M  
= 1) zeros and then reverts to idle or sending data.  
The actual number of zeros sent when SBK is tog-  
gled depends on the data format set by the M bit in  
the serial communications control register 1; there-  
fore, the break code will be synchronous with  
respect to the data stream. At the completion of  
B5, RIE  
When the receive interrupt enable bit is set, the  
SCI interrupt occurs provided OR is set or  
RDRF is set (see Figure 28). When RIE is clear,  
the OR and RDRF interrupts are disabled. Reset  
clears the RIE bit.  
47  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
the break code, the transmitter sends at least one  
high bit to guarantee recognition of a valid start bit.  
Reset clears the SBK bit.  
the serial communications status register (with  
IDLE set) followed by a read of the serial commu-  
nications data register. The IDLE bit will not be set  
again until after an RDRF has been set; i.e., a new  
idle line occurs. The IDLE bit is not set by an idle  
line when the receiver “wakes up” from the wake-  
up mode. Reset clears the IDLE bit.  
Serial Communications Status Register (SCSR)  
7
6
5
4
3
2
1
0
0
TDRE TC RDRF IDLE OR  
NF  
FE  
$10  
B3, OR  
When the overrun error bit is set the next byte is  
ready to be transferred from the receive shift  
register to the serial communications data regis-  
ter when it is already full (RDRF bit is set). Data  
transfer is then inhibited until the RDRF bit is  
cleared. Data in the serial communications data  
register is valid in this case, but additional data  
received during an overrun condition (including  
the byte causing the overrun) will be lost. The  
OR bit is cleared when the serial communica-  
tions status register is accessed (with OR set),  
followed by a read of the serial communications  
data register. Reset clears the OR bit.  
The serial communications status register (SCSR) provides  
inputs to the interrupt logic circuits for generation of the SCI  
system interrupt. In addition, a noise flag bit and a framing  
error bit are also contained in the SCSR.  
B7, TDRE The transmit data register empty bit is set to indi-  
cate that the contents of the serial communications  
data register have been transferred to the transmit  
serial shift register. If the TDRE bit is clear, it indi-  
cates that the transfer has not yet occurred and a  
write to the serial communications data register  
will overwrite the previous value. The TDRE bit is  
cleared by accessing the serial communications  
status register (with TDRE set), followed by writing  
to the serial communication data register. Data can  
not be transmitted unless the serial communica-  
tions status register is accessed before writing to  
the serial communications data register to clear  
the TDRE flag bit. Reset sets the TDRE bit.  
B2, NF  
The noise flag bit is set if there is noise on a “valid”  
start bit or if there is noise on any of the data bits or  
if there is noise on the stop bit. It is not set by noise  
on the idle line nor by invalid (false) start bits. If  
there is noise, the NF bit is not set until the RDRF  
flag is set. Each data bit is sampled three times as  
described above in RECEIVE DATA IN and shown  
in Figure 25. The NF bit represents the status of  
the byte in the serial communications data register.  
For the byte being received (shifted in) there will  
also be a “working” noise flag the value of which  
will be transferred to the NF bit when the serial  
data is loaded into the serial communications data  
register. The NF bit does not generate an interrupt  
because the RDRF bit gets set with NF and can be  
used to generate the interrupt. The NF bit is  
cleared when the serial communications status  
register is accessed (with NF set), followed by a  
read of the serial communications data register.  
Reset clears the NF bit.  
B6, TC  
The transmit complete bit is set at the end of a  
data frame, preamble, or break condition if:  
1.TE = 1, TDRE = 1, and no pending data, pream-  
ble, or break is to be transmitted; or  
2.TE = 0, and the data, preamble, or break (in the  
transmit shift register) has been transmitted.  
The TC bit is a status flag which indicates that one  
of the above conditions has occurred. The TC bit is  
cleared by accessing the serial communications  
status register (with TC set), followed by writing to  
the serial communications data register. It does  
not inhibit the transmitter function in any way.  
Reset sets the TC bit.  
B1, FE  
The framing error bit is set when the byte bound-  
aries in the bit stream are not synchronized with  
the receiver bit counter (generated by a “lost” stop  
bit). The byte is transferred to the serial communi-  
cations data register and the RDRF bit is set. The  
FE bit does not generate an interrupt because the  
RDRF bit is set at the same time as FE and can be  
used to generate the interrupt. Note that if the byte  
received causes a framing error and it will also  
cause an overrun if transferred to the serial com-  
munications data register, then the overrun bit will  
be set, but not the framing error bit, and the byte  
will not be transferred to the serial communications  
data register. The FE bit is cleared when the serial  
communications status register is accessed (with  
FE set) followed by a read of the serial communi-  
cations data register. Reset clears the FE bit.  
B5, RDRF When the receive data register full bit is set, it indi-  
cates that the receiver serial shift register is trans-  
ferred to the serial communications data register. If  
multiple errors are detected in any one received  
word, the NF, FE, and RDRF bits will be affected  
as appropriate during the same clock cycle. The  
RDRF bit is cleared when the serial communica-  
tions status register is accessed (with RDRF set)  
followed by a read of the serial communications  
data register. Reset clears the RDRF bit.  
B4, IDLE When the idle line detect bit is set, it indicates that  
a receiver idle line is detected (receipt of a mini-  
mum number of ones to constitute the number of  
bits in the byte format). The minimum number of  
ones needed will be 10(M = 0) or 11(M = 1). This  
allows a receiver that is not in the wake-up mode  
to detect the end of a message, detect the pream-  
ble of a new message, or to resynchronize with the  
transmitter. The IDLE bit is cleared by accessing  
48  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
B0  
Not implemented, always read as 0.  
PRESCALER OUTPUT  
SCR2  
SCR1  
SCR0  
DIVIDE BY  
Baud Rate Register  
7
0
6
0
5
4
3
0
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
SCP1 SCP0  
SCR2 SCR1 SCR0 $0D  
The baud rate register provides the means for selecting dif-  
ferent baud rates which may be used as the rate control for  
the transmitter and receiver. The SCP0 - SCP1 bits function  
as a prescaler for the SCR0 - SCR2 bits. Together, these five  
bits provide multiple, baud rate combinations for a given  
crystal frequency.  
4
8
16  
32  
64  
128  
B7-B6, B3 Not implemented, always read as 0.  
B5, SCP1 The SCP1 bit along with the SCP0 bit in the  
baud rate register are used as a prescaler to  
increase the range of standard baud rates con-  
trolled by the SCR0 - SCR2 bits. A table of the  
prescaler internal processor clock division ver-  
sus bit levels is provided below. This bit is  
cleared by reset (divide-by-one).  
The diagram of Figure 25 and Tables 6 and 7 illustrate the  
divided chain used to obtain the baud rate clock (transmit  
clock). Note that there is a fixed rate divide-by-16 between the  
receive clock (RT) and the transmit clock (Tx). The actual  
divider chain is controlled by the combined SCP0 - SCP1 and  
SCR0 - SCR2 bits in the baud rate register as illustrated. All  
divided frequencies shown in the first table represent the final  
transmit clock (the actual baud rate) resulting from the internal  
processor clock division shown in the “divide-by” column only  
(prescaler division only). The second table illustrates how the  
prescaler output can be further divided by action of the SCI  
select bits (SCR0 - SCR2). For example, assume that a  
9600Hz baud rate is required with a 2.4576MHz external crys-  
tal. In this case the prescaler bits (SCP0 - SCP1) could be con-  
figured as a divide-by-one or a divide-by-four. If a divide-by-four  
prescaler is used, then the SCR0 - SCR2 bits must be config-  
ured as a divide-by-two. This results in a divide-by-128 of the  
internal processor clock to produce a 9600Hz baud rate clock.  
Using the same crystal, the 9600 baud rate can be obtained  
with a prescaler divide-by-one and the SCR0 - SCR2 bits con-  
figured for a divide-by-eight.  
B4, SCP0 The SCP0 bit along with the SCP1 bit in the  
baud rate register are used as a prescaler to  
increase the range of standard baud rates con-  
trolled by the SCR0 - SCR2 bits. A table of the  
prescaler internal processor clock division ver-  
sus bit levels is provided below. This bit is  
cleared by reset (divide-by-one).  
INTERNAL PROCESSOR  
SCP1  
SCP0  
CLOCK DIVIDE BY  
0
0
1
1
0
1
0
1
1
3
4
13  
The crystal frequency is internally divided-by-two to gener-  
ate the internal processor clock.  
B2, SCR2 The SCR2 bit, along with SCR1 and SCR0,  
used to select the baud rates of both the trans-  
mitter and receiver. A table of baud rates versus  
bit levels is shown below. This bit is not affected  
by reset.  
SCI  
TRANSMIT  
CLOCK (Tx)  
B1, SCR1 The SCR1 bit, along with SCR2 and SCR0,  
used to select the baud rates of both the trans-  
mitter and receiver. A table of baud rates versus  
bit levels is shown below. This bit is not affected  
by reset.  
÷16  
OSCILLATOR  
FREQUENCY  
SCR0 - SCR2  
SCI SELECT  
RATE  
SCP0 - SCP1  
PRESCALER  
CONTROL  
÷N  
SCI  
RECEIVE  
B0, SCR0 The SCR0 bit, along with SCR2 and SCR1,  
used to select the baud rates of both the trans-  
mitter and receiver. A table of baud rates versus  
bit levels is shown below. This bit is not affected  
by reset.  
÷2  
CLOCK (RT)  
CONTROL  
÷M  
FIGURE 29. RATE GENERATOR DIVISION  
49  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
CDP68HC05C16B SLAVE 0  
MISO  
MOSI  
SCK  
SS  
MISO MOSI SCK SS  
V
DD  
CDP68HC05C16B  
MASTER  
0
1
PORT  
2
3
MISO MOSI SCK SS  
CDP68HC05C4B SLAVE 3  
MISO MOSI SCK SS  
CDP68HC05C8B SLAVE 2  
MISO MOSI SCK SS  
CDP68HC05C16B SLAVE 1  
FIGURE 30. MASTER-SLAVE SYSTEM CONFIGURATION (SINGLE MASTER, FOUR SLAVES)  
TABLE 6. PRESCALER HIGHEST BAUD RATE FREQUENCY OUTPUT  
SCP BIT  
CRYSTAL FREQUENCY MHz  
(NOTE 63)  
CLOCK  
(NOTE 64)  
1
0
0
1
0
1
DIVIDED BY  
8.0  
4.194304  
131.072kHz  
43.691kHz  
32.768kHz  
10.082kHz  
4.0  
2.4576  
2.0  
1.8432  
57.60kHz  
19.20kHz  
14.40kHz  
4430Hz  
0
1
3
250.000kHz  
83.332kHz  
62.500kHz  
19.200kHz  
125.000kHz  
41.666kHz  
31.250kHz  
9600Hz  
76.80kHz  
25.60kHz  
19.20kHz  
5.907kHz  
62.50kHz  
20.833kHz  
15.625kHz  
4800Hz  
0
1
1
4
13  
NOTES:  
63. The clock in the “CLOCK DIVIDED BY” column is the internal processor clock.  
64. CDP68HSC05C16B types.  
65. The divided frequencies shown in Table 6 represent baud rates which are the highest transmit baud rate (Tx) that can be obtained by a  
specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing a further division using  
the SCI rate select bits as shown below for some representative prescaler outputs.  
TABLE 7. TRANSMIT BAUD RATE OUTPUT FOR A GIVEN PRESCALER  
SCR BITS  
REPRESENTATIVE HIGHEST PRESCALER BAUD RATE OUTPUT  
(NOTE 66)  
250.000kHz 131.072kHz 32.768kHz  
131.072kHz 32.768kHz  
125.000kHz 65.536kHz 16.384kHz  
PORT A  
TONE  
OUTPUT  
DIVIDE  
BY  
2
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
76.80kHz  
76.80kHz  
38.40kHz  
19.20kHz  
9600Hz  
4800Hz  
2400Hz  
1200Hz  
600Hz  
19.20kHz  
19.20kHz  
9600Hz  
4800Hz  
2400Hz  
1200Hz  
600Hz  
9600Hz  
9600Hz  
4800Hz  
2400Hz  
1200Hz  
600Hz  
300Hz  
150Hz  
75Hz  
0
-
-
1
2
-
0
0
4
62.500kHz 32.678kHz  
31.250kHz 16.384kHz  
8.192kHz  
4.096kHz  
2.048kHz  
1.024kHz  
512Hz  
0
PA7  
PA6  
PA5  
PA4  
-
8
1
16  
32  
64  
128  
15.625kHz  
7.813kHz  
3.906kHz  
1.953kHz  
8.192kHz  
4.096kHz  
2.048kHz  
1.024kHz  
1
1
1
300Hz  
256Hz  
150Hz  
NOTES:  
66. CDP68HSC05C16B types.  
67. Table 7 illustrates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the prescaler output  
frequency. The five examples are only representative samples. In all cases, the baud rates shown are transmit baud rates (transmit clock)  
and the receiver clock is 16 times higher in frequency than the actual baud rate.  
50  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
• Write Collision Flag Protection  
Serial Peripheral Interface (SPI)  
• Master-Master Mode Fault Protection Capability  
INTRODUCTION AND FEATURES  
Introduction  
SIGNAL DESCRIPTION  
The serial peripheral interface (SPI) is an interface built into The four basic signals (MOSI, MISO, SCK, SS) discussed  
the MCU which allows several MCUs, or one MCU plus above are described in the following paragraphs. Each sig-  
peripheral devices, to be interconnected within a single “black nal function is described for both the master and slave mode.  
box” or on the same printed circuit board. In a serial peripheral  
interface (SPI), separate wires (signals) are required for data  
and clock. In the SPI format, the clock is not included in the  
NOTE: When the SPI system is enabled, any I/O pin that is used  
by the SPI as an input is forced to be an input, regardless of the  
state of the corresponding data direction register bit. However,  
data stream and must be furnished as a separate signal. An  
SPI system may be configured as one containing one master  
MCU and several slave MCUs, or in a system in which an  
MCU is capable of being either a master or a slave.  
any I/O pin that is used as an SPI output MUST have its corre-  
sponding data direction register bit set. If the DDR bit is not set,  
the pin is disconnected from the SPI logic and can be used as a  
general purpose input.  
Master Out Slave In (MOSI)  
Figure 30 illustrates a typical multi-computer system configu-  
ration. Figure 30 represents a system of five different MCUs  
in which there are one master and four slave (0, 1, 2, 3). In  
this system four basic line (signals) are required for the  
MOSI (master out slave in), MISO (master in slave out), SCK  
serial clock, and SS (slave select) lines.  
The MOSI pin is configured as a data output in a master  
(mode) device and as a data input in a slave (mode) device.  
In this manner data is transferred serially from a master to a  
slave on this line; most significant bit first, least significant bit  
last. The timing diagrams of Figure 31 summarize the SPI  
timing and show the relationship between data and clock  
(SCK). As shown in Figure 31, four possible timing relation-  
ships may be chosen by using control bits CPOL and CPHA.  
The master device always allows data to be applied on the  
MOSI line a half-cycle before the clock edge (SCK) in order  
for the slave device to latch the data.  
Features  
• Full Duplex, Three-Wire Synchronous Transfers  
• Master or Slave Operation  
• Master Bit Frequency  
- 1.05MHz Maximum (CDP68HC05C16B and  
CDP68HCL05C16B)  
NOTE: Both the slave device(s) and a master device must be pro-  
grammed to similar timing modes for proper data transfer.  
- 2.0MHz Maximum (CDP68HSC05C16B)  
• Slave Bit Frequency  
When the master device transmits data to a second (slave)  
device via the MOSI line, the slave device responds by send-  
ing data to the master device via the MISO line. This implies  
full duplex transmission with both data out and data in syn-  
chronized with the same clock signal (one which is provided  
by the master device). Thus, the byte transmitted is replaced  
by the byte received and eliminates the need for separate  
transmit-empty and receiver-full status bits. A single status bit  
(SPIF) is used to signify that the I/O operation is complete.  
- 2.1MHz Maximum (CDP68HC05C16B and  
CDP68HCL05C16B)  
- 4.0MHz Maximum (CDP68HSC05C16B)  
• Four Programmable Master Bit Rates  
• Programmable Clock Polarity and Phase  
• End of Transmission Interrupt Flag  
SS  
SS  
SCK  
SCK  
(CPOL = 0, CPHA = 0)  
(CPOL = 0, CPHA = 1)  
SCK  
SCK  
(CPOL = 1, CPHA = 0)  
(CPOL = 1, CPHA = 1)  
MISO/  
MOSI  
MSB  
6
5
4
3
2
1
LSB  
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)  
FIGURE 31. DATA CLOCK TIMING DIAGRAM  
51  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Configuration of the MOSI pin is a function of the MSTR bit controlled by the CPOL and CPHA bits in the SPCR. In slave  
in the serial peripheral control register (SPCR, location $0A). devices, SPR0, SPR1 have no effect on the operation of the  
When a device is operating as a master, the MOSI pin is an SPI. Timing is shown in Figure 31.  
output because the program in firmware sets the MSTR bit  
to a logic one.  
Slave Select (SS)  
The slave select (SS) pin is a fixed input, which receives an  
active low signal to enable slave device(s) to transfer data. A  
Master In Slave Out (MISO)  
The MISO pin is configured as an input in a master (mode) high level SS signal forces the MISO line to the high-imped-  
device and as an output in a slave (mode) device. In this ance state. Also, SCK and MOSI are ignored by a slave  
manner data is transferred serially from a slave to a master device when its SS signal is high. The SS signal must be  
on this line; most significant bit first, least significant bit last. driven low prior to the first SCK and must remain low  
The MISO pin of a slave device is placed in the high-imped- throughout a transfer. The SS input on a Master must be  
ance state if it is not selected by the master; i.e., its SS pin is held high at all times (see description of MODF under Serial  
a logic one. The timing diagram of Figure 31 shows the rela- Peripheral Status Register for more details).  
tionship between data and clock (SCK). As shown in Figure  
As shown in Figure 31, with CPHA = 0, the first bit of data  
31, four possible timing relationships may be chosen by  
must be applied to the MISO line prior to the first transition of  
using control bits CPOL and CPHA. The master device  
the SCK. In this case, SS going low is used to provide the  
always allows data to be applied on the MOSI line a half-  
first clock edge of a transfer. A device is prevented from writ-  
cycle before the clock edge (SCK) in order for the slave  
ing to its SPI data register while SS is low and CPHA = 0  
device to latch the data.  
(see description of WCOL under Serial Peripheral Status  
Register for more details). These facts require that SS go  
high between SPI data transfers whenever CPHA = 0.  
NOTE: The slave device(s) and a master device must be pro-  
grammed to similar timing modes for proper data transfer.  
When the master device transmits data to a slave device via  
When CPHA = 1, the SS of a slave can be held low through-  
the MOSI line, the slave device responds by sending data to  
out a series of SPI transfers and in a single slave system can  
the master device via the MISO line. This implies full duplex  
even be permanently wired low.  
transmission with both data out and data in synchronized  
When a device is a master, it constantly monitors its SS sig-  
nal input for a logic low. The master device will become a  
slave device any time its SS signal input is detected low. This  
ensures that there is only one master controlling the SS line  
for a particular system. When the SS line is detected low, it  
clears the MSTR control bit (serial peripheral control regis-  
ter, location $0A). Also, control bit SPE in the serial periph-  
eral control register is cleared which causes the serial  
peripheral interface (SPI) to be disabled. The MODF flag bit  
in the serial peripheral status register (location $0B) is also  
set to indicate to the master device that another device is  
attempting to become a master. Two devices attempting to  
be outputs are normally the result of a software error; how-  
ever, a system could be configured which would contain a  
default master which would automatically “take over” and  
restart the system.  
with the same clock signal (one which is provided by the  
master device). Thus, the byte transmitted is replaced by the  
byte received and eliminates the need for separate transmit-  
empty and receiver-full status bits. A single status bit (SPIF)  
in the serial peripheral status register (SPSR, location $0B)  
is used to signify that the I/O operation is complete.  
In the master device, the MSTR control bit in the serial  
peripheral control register (SPCR, location $0A) is set to a  
logic one (by the program) to allow the master device to  
receive data on its MISO pin. In the slave device, its MISO  
pin is enable by the logic level of the SS pin; i.e., if SS = 1  
then the MISO pin is placed in the high-impedance state,  
whereas, if SS = 0 the MISO pin is an output for the slave  
device.  
Serial Clock (SCK)  
The serial clock is used to synchronize the movement of FUNCTIONAL DESCRIPTION  
data both in and out of the device through its MOSI and  
A block diagram of the serial peripheral interface (SPI) is  
MISO pins. The master and slave devices are capable of  
exchanging a data byte of information during a sequence of  
eight clock pulses. The SCK is generated by the master  
device, is an input on all slave devices, and synchronizes  
master/slave data transfers. The type of clock and its rela-  
tionship to data are controlled by the CPOL and CPHA bits  
in the Serial Peripheral Control Register (SPCR, location  
$0A) discussed below. Refer to Figure 30 for timing.  
shown in Figure 32. In a master configuration, the master  
start logic receives an input from the CPU (in the form of a  
write to the SPI rate generator) and originates the system  
clock (SCK) based on the internal processor clock. This  
clock is also used internally to control the state controller as  
well as the 8-bit shift register. As a master device, data is  
parallel loaded into the 8-bit shift register (from the internal  
bus) during a write cycle, data is applied serially from a slave  
device via the MISO pin to the 8-bit shift register. After the  
8-bit shift register is loaded, its data is parallel transferred to  
the read buffer and then is made available to the internal  
data bus during a CPU read cycle.  
The master device generates the SCK through a circuit  
driven by the internal processor clock. Two bits (SPR0 and  
SPR1) in the SPCR of the master device select the clock  
rate. The master device uses the SCK to latch incoming  
slave device data on the MISO line and shifts out data to the  
slave device on the MOSI line. Both master and slave  
devices must be operated in the same timing mode as  
In a slave configuration, the slave start logic receives a logic  
low (from a master device) at the SS pin and a system clock  
input (from the same master device) at the SCK pin. Thus, the  
52  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
SEE NOTES  
INTERNAL  
PROCESSOR  
CLOCK  
33  
SCK  
32  
MOSI  
31  
MISO  
READ  
RATE  
GENERATOR  
MASTER  
START LOGIC  
8
INTERNAL  
DATA BUS  
(LOAD)  
(FULL)  
READ BUFFER  
34  
SS  
SPIF  
(END TX)  
8
$0C  
SLAVE  
START LOGIC  
8-BIT SHIFT  
REGISTER  
8
(SEE NOTES)  
2
WRITE  
CONTROL  
BITS  
SPCR  
$0A  
3
7
STATE  
CONTROLLER  
SPSR  
$0B  
FLAGS  
NOTES:  
68. The SS, SCK, MOSI and MISO are external pins which provide the following functions:  
69. MOSI - Provides serial output to slave unit(s) when device is configured as a master. Receives serial input from master unit when device  
is configured as a slave unit.  
70. MISO - Receives serial input from slave unit(s) when device is configured as a master. Provides serial output to master when device is  
configured as a slave unit.  
71. SCK - Provides system clock when device is configured as a master unit. Receives system clock when device is configured as a slave unit.  
72. SS - Provides a logic low to select device for a transfer with a master device.  
FIGURE 32. SERIAL PERIPHERAL INTERFACE BLOCK DIAGRAM  
slave is synchronized with the master. Data from the master is REGISTERS  
received serially at the slave MOSI pin and loads the 8-bit shift  
There are three register in the serial parallel interface which  
register. After the 8-bit shift register is loaded, its data is paral-  
provide control, status, and data storage functions. These  
lel transferred to the read buffer and then is made available to  
registers which include the serial peripheral control register  
the internal data bus during a CPU read cycle. During a write  
(SPCR, location $0A), serial peripheral status register  
cycle, data is parallel loaded into the 8-bit shift register from  
(SPSR, location $0B), and serial peripheral data I/O register  
the internal data bus and then shifted out serially to the MISO  
(SPDR, location $0C) are described below.  
pin for application to the master device. Figure 33 illustrates  
Serial Peripheral Control Register (SPCR)  
the MOSI, MISO, and SCK master-slave interconnections.  
Note that in Figure 33 the master SS pin is tied to a logic high  
and the slave SS pin is a logic low. Figure 30 provides a larger  
system connection for these same pins. Note that in Figure  
30, all SS pins are connected to a port pin of a master/slave  
device. In this case any of the devices can be a slave.  
7
6
5
4
3
2
1
0
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 $0A  
The serial peripheral control register bits are defined as  
follows:  
MASTER  
SLAVE  
B7, SPIE When the serial peripheral interrupt enable is  
high, it allows the occurrence of a processor  
interrupt, and forces the proper vector to be  
loaded into the program counter if the serial  
peripheral status register flag bit (SPIF and/or  
MODE) is set to a logic one. It does not inhibit  
the setting of a status bit. The SPIE bit is cleared  
by reset.  
MISO  
MOSI  
SCK  
MISO  
MOSI  
SCK  
8-BIT SHIFT  
REGISTER  
8-BIT SHIFT  
REGISTER  
SPI  
CLOCK  
GENERATOR  
SS  
+5V  
SS  
0V  
B6, SPE  
When the serial peripheral output enable control  
bit is set, all output drive is applied to the exter-  
nal pins and the system is enabled. When the  
FIGURE 33. SERIAL PERIPHERIAL INTERFACE MASTER-SLAVE  
INTERCONNECTION  
53  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
SPE bit is set, it enables the SPI system by con- B1, SPR1 These two serial peripheral rate bits select one  
necting it to the external pins thus allowing it to  
B0, SPR0 of four baud rates to used as SCK if the device is  
interface with the external SPI bus. The pins that  
a master; however they have no effect in the  
are defined as output depend on which mode  
slave mode. The slave device is capable of shift-  
(master or slave) the device is in. Because the  
ing data in and out at a maximum rate which is  
SPE bit is cleared by reset, the SPI system is  
equal to the CPU clock. A rate table is given  
not connected to the external pins upon reset.  
below for the generation of the SCK from the  
B5, DWOM The Port D Wire-Or Mode bit controls the output  
drivers for all of the Port D pins. When this bit is  
set the high side output drivers for all of the Port  
D pins are turned off and the outputs can be  
wire-ORed together. When this bit is clear the  
outputs are standard push-pull CMOS outputs.  
master. The SPR1 and SPR0 bits are not  
affected by reset.  
Serial Peripheral Status Register (SPSR)  
7
6
5
0
4
3
0
2
0
1
0
0
0
SPIF WCOL  
MODF  
$0B  
B4, MSTR The master bit determines whether the device is  
a master or a slave. If the MSTR bit is a logic  
zero it indicates a slave device and a logic one  
denotes a master device. If the master mode is  
selected, the function of the SCK pin changes  
from an input to an output and the function of the  
MISO and MOSI pins are reversed. This allows  
the user to wire device pins MISO to MISO, and  
MOSI to MOSI, and SCK to SCK without inci-  
dent. The MSTR bit is cleared by reset; there-  
fore, the device is always placed in the slave  
mode during reset.  
The status flags which generate a serial peripheral interface  
(SPI) interrupt may be blocked by the SPIE control bit in the  
serial peripheral control register. The WCOL bit does not  
cause an interrupt. The serial peripheral status register bits  
are defined as follows:  
B7, SPIF The serial peripheral data transfer flag bit noti-  
fies the user that a data transfer between the  
device and an external device has been com-  
pleted. With the completion of the data transfer,  
SPIF is set, and if SPIE is set, a serial peripheral  
interrupt (SPI) is generated. During the clock  
cycle that SPIF is being set, a copy of the  
received data byte in the shift register is moved  
to a buffer. When the data register is read, it is  
the buffer that is read. During an overrun condi-  
tion, when the master device has sent several  
bytes of data and the slave device has not  
responded to the first SPIF, only the first byte  
sent is contained in the receiver buffer and all  
other bytes are lost.  
B3, CPOL The clock polarity bit controls the normal or  
steady state value of the clock when data is not  
being transferred. The CPOL bit affects both the  
master and slave modes. It must be used in con-  
junction with the clock phase control bit (CPHA)  
to produce the wanted clock-data relationship  
between a master and a slave device. When the  
CPOL bit is a logic zero, it produces a steady  
state low value at the SCK pin of the master  
device. If the CPOL bit is a logic one, a high value  
is produced at the SCK pin of the master device  
when data is not being transferred. The CPOL bit  
is not affected by reset. Refer to Figure 31.  
The transfer of data is initiated by the master  
device writing its serial peripheral data register.  
Clearing the SPIF bit is accomplished by a soft-  
ware sequence of accessing the serial periph-  
eral status register while SPIF is set and  
followed by a write to or a read of the serial  
peripheral data register. While SPIF is set, all  
writes to the serial peripheral data register are  
inhibited until the serial peripheral status register  
is read. This occurs in the master device. In the  
slave device, SPIF can be cleared (using a simi-  
lar sequence) during a second transmission;  
however, it must be cleared before the second  
SPIF in order to prevent an overrun condition.  
The SPIF bit is cleared by reset.  
B2, CPHA The clock phase bit controls the relationship  
between the data on the MISO and MOSI pins  
and the clock produced or received at the SCK  
pin. This control has effect in both the master and  
slave modes. It must be used in conjunction with  
the clock polarity control bit (CPOL) to produce  
the wanted clock-data relation. The CPHA bit in  
general selects the clock edge which captures  
data and allows it to change states. It has its  
greatest impact on the first bit transmitted (MSB)  
in that it does or does not allow a clock transition  
before the first data capture edge. The CPHA bit  
is not affected by reset. Refer to Figure 31.  
B6, WCOL The function of the write collision status bit is to  
notify the user that an attempt was made to write  
the serial peripheral data register while a data  
transfer was taking place with an external  
device. The transfer continues uninterrupted;  
therefore, a write will be unsuccessful. A “read  
collision” will never occur since the received  
data byte is placed in a buffer in which access is  
always synchronous with the MCU operation. If  
INTERNAL PROCESSOR  
SPR1  
SPR0  
CLOCK DIVIDE BY  
0
0
1
1
0
1
0
1
2
4
16  
32  
54  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
a “write collision” occurs, WCOL is set but no  
SPI interrupt is generated. The WCOL bit is a  
status flag only.  
sion mode, a master device might hold a slave  
device SS pin low during a transfer of several  
bytes of data without a problem.  
Clearing the WCOL bit is accomplished by a  
software sequence of accessing the serial  
peripheral status register while WCOL is set, fol-  
lowed by 1) a read of the serial peripheral data  
register prior to the SPIF bit being set, or 2) a  
read or write of the serial peripheral data regis-  
ter after the SPIF bit is set. A write to the serial  
peripheral data register (SPDR) prior to the  
SPIF bit being set, will result in generation of  
another WCOL status flag. Both the SPIF and  
WCOL bits will be cleared in the same  
sequence. If a second transfer has started while  
trying to clear (the previously set) SPIF and  
WCOL bits with a clearing sequence containing  
a write to the serial peripheral data register, only  
the SPIF bit will be cleared.  
A special case of WCOL occurs in the slave  
device. This happens when the master device  
starts a transfer sequence (an edge on SCK for  
CPHA = 1; or an active SS transition for CPHA =  
0) at the same time the slave device CPU is writ-  
ing to its serial peripheral interface data register.  
In this case it is assumed that the data byte writ-  
ten (in the slave device serial peripheral  
interface) is lost and the contents of the slave  
device read buffer becomes the byte that is  
transferred. Because the master device receives  
back the last byte transmitted, the master device  
can detect that a fatal WCOL occurred.  
Since the slave device is operating asynchro-  
nously with the master device, the WCOL bit  
may be used as an indicator of a collision occur-  
rence. This helps alleviate the user from a strict  
real-time programming effort. The WCOL bit is  
cleared by reset.  
A collision of a write to the serial peripheral data  
register while an external data transfer is taking  
place can occur in both the master mode and  
the slave mode, although with proper program-  
ming the master device should have sufficient  
information to preclude this collision.  
B5, B3-B0 Not implemented, always read as 0.  
B4, MODF The function of the mode fault flag is defined for  
the master mode (device). If the device is a  
slave device the MODF bit will be prevented  
from toggling from a logic zero to a logic one;  
however, this does not prevent the device from  
being in the slave mode with the MODF bit set.  
The MODF bit is normally a logic zero and is set  
only when the master device has its SS pin  
pulled low. Toggling the MODF bit to a logic one  
affects the internal serial peripheral interface  
(SPI) system in the following ways:  
Collision in the master device is defined as a  
write of the serial peripheral data register while  
the internal rate clock (SCK) is in the process of  
transfer. The signal on the SS pin is always high  
on the master device.  
A collision in a slave device is defined in two  
separate modes. One problem arises in a slave  
device when the CPHA control bit is a logic zero.  
When CPHA is a logic zero, data is latched with  
the occurrence of the first clock transition. The  
slave device does not have any way of knowing  
when that transition will occur; therefore, the  
slave device collision occurs when it attempts to  
write the serial peripheral data register after its  
SS pin has been pulled low. The SS pin of the  
slave device freezes the data in its serial periph-  
eral data register and does not allow it to be  
altered if the CPHA bit is a logic zero. The mas-  
ter device must raise the SS pin of the slave  
device high between each byte it transfers to the  
slave device.  
1. MODF is set and SPI interrupt is generated if  
SPIE = 1.  
2. The SPE bit is forced to a logic zero. This  
blocks all output drive from the device, dis-  
ables the SPI system.  
3. The MSTR bit is forced to a logic zero, thus  
forcing the device into the slave mode.  
Clearing the MODF is accomplished by a soft-  
ware sequence of accessing the serial periph-  
eral status register while MODF is set followed  
by a write to the serial peripheral control regis-  
ter. Control bit SPE and MSTR may be restored  
to their original set state during this cleared  
sequence or after the MODF bit has been  
cleared. Hardware does not allow the user to set  
the SPE and MSTR bit while MODF is a logic  
one unless it is during the proper clearing  
sequence. The MODF flag bit indicates that  
there might have been a multi-master conflict for  
system control and allows a proper exit from  
system operation to a reset or default system  
state. The MODF bit is cleared by reset.  
The second collision mode is defined for the  
state of the CPHA control bit being a logic one.  
With the CPHA bit set, the slave device will be  
receiving a clock (SCK) edge prior to the latch of  
the first data transfer. This first clock edge will  
freeze the data in the slave device I/O register  
and allow the MSB onto the external MISO pin  
of the slave device. The SS pin low state  
enables the slave device but the drive onto the  
MISO pin does not take place until the first data  
transfer clock edge. The WCOL bit will only be  
set if the I/O register is accessed while a transfer  
is taking place. By definition of the second colli-  
55  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Serial Peripheral Data I/O Register (SPDR)  
SERIAL PERIPHERAL INTERFACE (SPI)  
SYSTEM CONSIDERATIONS  
7
6
5
4
3
2
1
0
There are two types of SPI systems; single master system  
and multi-master systems. Figure 30 illustrates a single mas-  
ter system and a discussion of both is provided below.  
Serial Peripheral Data I/O Register  
$0C  
The serial peripheral data I/O register is used to transmit and  
receive data on the serial bus. Only a write to this register  
will initiate transmission/reception of another byte and this  
will only occur in the master device. A slave device writing to  
its data I/O register will not initiate a transmission. At the  
completion of transmitting a byte of data, the SPIF status bit  
is set in both the master and slave devices. A write or read of  
the serial peripheral data I/O register, after accessing the  
serial peripheral status register with SPIF set, will clear SPIF.  
Figure 31 illustrates how a typical single master system may  
be configured, using a CDP68HC05 family device as the mas-  
ter and four CDP68HC05 family devices as slaves. As shown,  
the MOSI, MISO, and SCK pins are all wired to equivalent  
pins on each of the five devices. The master device generates  
the SCK clock, the slave devices all receive it. Since the  
CDP68HC05 master device is the bus master, it internally  
controls the function of its MOSI and MISO lines, thus writing  
data to the slave devices on the MOSI and reading data from  
the slave devices on the MISO lines. The master device  
selects the individual slave devices by using four pins of a par-  
allel port to control the four SS pins of the slave devices. A  
slave device is selected when the master device pulls its SS  
pin low. The SS pins are pulled high during reset since the  
master device ports will be forced to be inputs at that time,  
thus disabling the slave devices. Note that the slave devices  
do not have to be enabled in a mutually exclusive fashion  
except to prevent bus contention on the MISO line. For exam-  
ple, three slave devices, enabled for a transfer, are permissi-  
ble if only one has the capability of being read by the master.  
An example of this is a write to several display drivers to clear  
a display with a single I/O operation. To ensure that proper  
data transmission is occurring between the master device and  
a slave device, the master device may have the slave device  
respond with a previously received data byte (this data byte  
could be inverted or at least be a byte that is different from the  
last one sent by the master device). The master device will  
always receive the previous byte back from the slave device if  
all MISO and MOSI lines are connected and the slave has not  
written its data I/O register. Other transmission security meth-  
ods might be defined using ports for handshake lines or data  
bytes with command fields.  
During the clock cycle that the SPIF bit is being set, a copy  
of the received data byte in the shift register is being moved  
to a buffer. When the user reads the serial peripheral data  
I/O register, the buffer is actually being read. During an  
overrun condition, when the master device has sent several  
bytes of data and the slave device has not internally  
responded to clear the first SPIF, only the first byte is con-  
tained in the receive buffer of the slave device; all others  
are lost. The user may read the buffer at any time. The first  
SPIF must be cleared by the time a second transfer of data  
from the shift register to the read buffer is initiated or an  
overrun condition will exist.  
A write to the serial peripheral data I/O register is not buff-  
ered and places data directly into the shift register for trans-  
mission.  
The ability to access the serial peripheral data I/O register is  
limited when a transmission is taking place. It is important to  
read the discussion defining the WCOL and SPIF status bit to  
understand the limits on using the serial peripheral data I/O  
register.  
A multi-master system may also be configured by the user. An  
exchange of master control could be implemented using a  
handshake method through the I/O ports or by an exchange  
of code messages through the serial peripheral interface sys-  
tem. The major device control that plays a part in this system  
is the MSTR bit in the serial peripheral control register and the  
MODF bit in the serial peripheral status register.  
56  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
resistor), setting DDRA7-DDRA4=1 and PA7, PA5 and PA4=1  
Port A Tone and Simple PWM Circuitry  
and PA6=0. The number in parentheses beside the port desig-  
nations in the diagram is the duty cycle of the associated output  
signal. The port A tone output options are not available on the  
MC68CH05C9A MCUs. When designing CDP68HC05C16B  
systems which must maintain backward compatibility with the  
MC68CH05C9A, avoid use of the port A tone options.  
INTRODUCTION  
When the Tone output mask option is selected on PA7-PA4  
a fixed frequency will appear on the output pin whenever  
the appropriate DDRA and PORTA bits are set to 1. Each  
of the port pins A4 - A7 provides a different frequency. The  
frequency is dependent on the oscillator input frequency  
and on the values selected for SCP1 and SCP0 in the SCI  
Baud Rate Register (see Table 7). An example of frequen-  
cies generated with a 4MHz oscillator and SCP1=SCP0=1  
is shown in Figure 34.  
Effects of STOP and WAIT Modes on the  
Timer and Serial Systems  
STOP MODE  
TABLE 8. PORT A TONES WITH 4MHz OSCILLATOR  
When the processor executes the STOP instruction, the  
internal oscillator is turned off. This halts all internal CPU  
processing including the operation of the programmable  
timer, serial communications interface, serial peripheral  
interface, and COP. The only way for the MCU to “wake up”  
from the stop mode is by receipt of an external interrupt  
(IRQ = 0) or by a hardware reset (logic low on RESET pin  
or a power-on reset).  
FREQUENCY WITH  
FREQUENCY DIVISOR OF  
SCP1=SCP0=1 IN SCI  
PIN  
PA4  
PA5  
PA6  
PA7  
BAUD RATE PRE-SCALE BAUD RATE REGISTER  
Divide By 64  
Divide By 32  
Divide By 16  
Divide By 8  
150Hz  
300Hz  
600Hz  
1200Hz  
Timer During Stop Mode  
NOTE: Frequency is dependent on the Baud Rate Prescaler value  
set in the Baud Rate Register. See Serial Communications Interface  
(SCI) for details on the Baud Rate Register  
When the MCU enters the stop mode, the timer counter  
stops counting (the internal processor is stopped) and  
remains at that particular count value until the stop mode is  
exited by an interrupt (if exited by reset the counter is forced  
to $FFFC). If the stop mode is exited by an external low on  
the IRQ pin, then the counter resumes from its stopped  
value as if nothing had happened. If at least one valid input  
capture edge occurs at the TCAP pin while in the stop mode,  
the input capture detect circuitry is armed. This action does  
not set any timer flags or “wake up” the MCU, but when the  
MCU does “wake up” there will be an active input capture  
flag (and data) from that first valid edge which occurred dur-  
ing the stop mode. If the stop mode is exited by an external  
reset (logic low on RESET pin), then no such input capture  
flag or data action takes place even if there was a valid input  
capture edge (at the TCAP pin) during the MCU stop mode.  
Even when the tone output mask option is selected the PA7-  
PA4 pins still function as CMOS inputs when the appropriate  
bits in DDRA are set to 0. No signal will appear on the port pin  
when the that pin is configured as an input. When a tone pin is  
in the output mode (i.e. for pin PAx, DDRAx is set to “1”) writing  
a 1 to the respective PA7-PA4 bit in the PORTA register enables  
the frequency to appear on the pin output. Writing a 0 to this  
location disconnects this signal from the pin output. When the  
bits of PORTA are in output mode (DDRAx=1) reading the port  
reads the state of the PORTA bit in register location $00, not the  
tone signal. The open drain mask option (see Figure 6D) allows  
wire ORing of the pins to produce various duty cycle outputs  
creating a simple PWM. An example of this is shown as the last  
waveform in Figure 34. In this case the signal shown is the  
result of wire-ORing all four pins together (with a pull-down  
16 TIME SLOTS  
PA7 (50%)  
PA6 (25%)  
PA5 (12.5%)  
PA4 (6.25%)  
PA7+PA5+PA4 (68.75%)  
FIGURE 34. PORT A TONE GENERATOR/SIMPLE PWM OUTPUT WAVEFORMS  
57  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
SCI During Stop Mode  
WAIT MODE  
When the MCU enters the stop mode, the baud rate generator When the MCU enters the wait mode, the CPU clock is  
which drives the receiver and transmitter is shut down. This halted. All CPU action is suspended; however, the timer,  
essentially stops all SCI activity. The receiver is unable to SCI, SPI, and COP systems remain active. In fact, any inter-  
receive and transmitter is unable to transmit. If the STOP rupt from the timer, SCI, SPI, or IRQ pin or a reset from the  
instruction is executed during a transmitter transfer, that trans- COP or RESET pin will cause the processor to exit the wait  
fer is halted. When the stop mode is exited, that particular mode. Since the timer and serial systems operate as they do  
transmission resumes (if the exit is the result of a low input to in the normal “run” mode, only a general discussion of the  
the IRQ pin). Since the previous transmission resumes after wait mode is provided below.  
an IRQ interrupt stop mode exit, the user should ensure that  
The wait mode power consumption depends on how many  
the SCI transmitter is in the idle state when the STOP instruc-  
systems are active. The power consumption will be highest  
tion is executed. If the receiver is receiving data when the  
when all the systems (timer, TCMP, SCI, and SPI) are active.  
STOP instruction is executed, received data sampling is  
The power consumption will be the least when the SCI and  
stopped (baud rate generator stops) and the rest of the data is  
SPI systems are disabled (timer operation cannot be dis-  
lost. For the above reasons, all SCI transactions should be in  
abled in the wait mode). If a non-reset exit from the wait  
the idle state when the STOP instruction is executed.  
mode is performed (i.e., timer overflow interrupt exit), the  
SPI During Stop Mode  
state of the remaining systems will be unchanged. If a reset  
exit from the wait mode is performed all the systems revert to  
the disabled reset state. See the previous discussion of  
COP.  
When the MCU enters the stop mode, the baud rate generator  
which drives the SPI shuts down. This essentially stops all  
master mode SPI operation, thus the master SPI is unable to  
transmit or receive any data. If the STOP instruction is exe-  
cuted during an SPI transfer, that transfer is halted until the  
MCU exits the stop mode (provided it is an exit resulting from  
a logic low on the IRQ pin). If the stop mode is exited by a  
reset, then the appropriate control/status bits are cleared and  
the SPI is disabled. If the device is in the slave mode when the  
STOP instruction is executed, the slave SPI will still operate. It  
can still accept data and clock information in addition to trans-  
mitting its own data back to a master device.  
At the end of a possible transmission with a slave SPI in the  
stop mode, no flags are set until a logic low IRQ input  
results in an MCU “wake up”. Caution should be observed  
when operating the SPI (as a slave) during the stop mode  
because none of the protection circuitry (write collision,  
mode fault, etc.) is active.  
It should also be noted that when the MCU enters the stop  
mode all enabled output drivers (TDO, TCMP, MISO, MOSI,  
and SCK ports) remain active and any sourcing currents  
from these outputs will be part of the total supply current  
required by the device.  
58  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Dual-In-Line Plastic Packages (PDIP)  
E40.6 (JEDEC MS-011-AC ISSUE B)  
N
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INCHES  
MILLIMETERS  
INDEX  
AREA  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.250  
-
MIN  
-
MAX  
6.35  
-
NOTES  
-B-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.125  
0.014  
0.030  
0.008  
1.980  
0.005  
0.600  
0.485  
0.39  
3.18  
0.356  
0.77  
0.204  
4
D
E
0.195  
0.022  
0.070  
0.015  
2.095  
-
4.95  
0.558  
1.77  
0.381  
-
BASE  
PLANE  
A2  
A
-C-  
-
SEATING  
PLANE  
B1  
C
8
L
C
L
-
D1  
B1  
eA  
A1  
A
D1  
e
D
50.3  
53.2  
5
C
eC  
B
D1  
E
0.13  
15.24  
12.32  
-
5
eB  
0.010 (0.25)  
C
B
S
M
0.625  
0.580  
15.87  
14.73  
6
E1  
e
5
NOTES:  
0.100 BSC  
0.600 BSC  
2.54 BSC  
15.24 BSC  
-
1. Controlling Dimensions: INCH. In case of conflict between  
English and Metric dimensions, the inch dimensions control.  
e
e
6
A
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
-
0.700  
0.200  
-
17.78  
5.08  
7
B
3. Symbols are defined in the “MO Series Symbol List” in Section  
2.2 of Publication No. 95.  
L
0.115  
2.93  
4
9
N
40  
40  
4. Dimensions A, A1 and L are measured with the package seated  
in JEDEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or protru-  
sions. Mold flash or protrusions shall not exceed 0.010 inch  
(0.25mm).  
e
6. E and  
pendicular to datum  
7. e and e are measured at the lead tips with the leads uncon-  
are measured with the leads constrained to be per-  
A
-C-  
.
B
C
strained. e must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions.  
Dambar protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,  
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch  
(0.76 - 1.14mm).  
59  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Shrink Dual-In-Line Plastic Packages (SPDIP)  
E42.6B-S  
N
42 LEAD SHRINK DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INCHES MILLIMETERS  
INDEX  
AREA  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.190  
-
MIN  
4.50  
MAX  
5.00  
-
NOTES  
A
0.178  
0.020  
2
A1  
B
0.50  
2
D
0.016  
0.023  
0.041  
0.013  
1.503  
0.523  
0.40  
0.60  
1.405  
0.35  
38.20  
13.30  
-
BASE  
PLANE  
A
B1  
C
0.030  
0.75  
-
SEATING  
PLANE  
0.008  
0.20  
-
L
C
L
D
1.485  
37.70  
12.90  
1.778 BSC  
15.24 BSC  
3.00  
3
eA  
A1  
e
B1  
E1  
e
0.508  
3
C
α
B
0.070 BSC  
0.600 BSC  
0.119  
-
e
4
A
L
-
-
2
N
42  
42  
5
o
o
o
o
NOTES:  
0
15  
0
15  
-
α
1. Controlling Dimensions: MILLIMETER. In case of conflict be-  
tween English and Metric dimensions, the metric dimensions  
control.  
Rev. 0 2/96  
2. Dimensions A, A1 and L are measured with the package seated  
in JEDEC seating plane gauge GS-3.  
3. D and E1 dimensions do not include mold flash or protrusions.  
e
4.  
is measured with the leads constrained to be perpendicular  
A
to base plane.  
5. N is the maximum number of terminal positions.  
60  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Plastic Leaded Chip Carrier Packages (PLCC)  
0.042 (1.07)  
0.048 (1.22)  
N44.65 (JEDEC MS-018AC ISSUE A)  
0.042 (1.07)  
0.056 (1.42)  
0.004 (0.10)  
C
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE  
PIN (1) IDENTIFIER  
0.025 (0.64)  
0.045 (1.14)  
0.050 (1.27) TP  
INCHES  
MIN  
MILLIMETERS  
R
C
L
SYMBOL  
MAX  
0.180  
0.120  
0.695  
0.656  
0.319  
0.695  
0.656  
0.319  
MIN  
4.20  
MAX  
4.57  
NOTES  
A
A1  
D
0.165  
0.090  
0.685  
0.650  
0.291  
0.685  
0.650  
0.291  
-
2.29  
3.04  
-
D2/E2  
17.40  
16.51  
7.40  
17.65  
16.66  
8.10  
-
C
L
D1  
D2  
E
3
E1  
E
4, 5  
D2/E2  
17.40  
16.51  
7.40  
17.65  
16.66  
8.10  
-
VIEW “A”  
E1  
E2  
N
3
4, 5  
6
0.020 (0.51)  
MIN  
44  
44  
D1  
D
A1  
A
Rev. 1 3/95  
SEATING  
PLANE  
0.020 (0.51) MAX  
3 PLCS  
-C-  
0.026 (0.66)  
0.032 (0.81)  
0.013 (0.33)  
0.021 (0.53)  
0.025 (0.64)  
MIN  
0.045 (1.14)  
MIN  
VIEW “A” TYP.  
NOTES:  
1. Controlling dimension: INCH. Converted millimeter dimensions  
are not necessarily exact.  
2. Dimensions and tolerancing per ANSI Y14.5M-1982.  
3. Dimensions D1 and E1 do not include mold protrusions. Allow-  
able mold protrusion is 0.010 inch (0.25mm) per side.  
-C-  
4. To be measured at seating plane  
contact point.  
5. Centerline to be determined where center leads exit plastic body.  
6. “N” is the number of terminal positions.  
61  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)  
D
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)  
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE  
D1  
-D-  
INCHES  
MIN  
MILLIMETERS  
SYMBOL  
MAX  
0.093  
0.010  
0.083  
0.018  
0.016  
0.530  
0.398  
0.530  
0.398  
0.037  
MIN  
-
MAX  
2.35  
NOTES  
A
A1  
A2  
B
-
-
0.004  
0.077  
0.012  
0.012  
0.510  
0.390  
0.510  
0.390  
0.026  
0.10  
1.95  
0.30  
0.30  
12.95  
9.90  
12.95  
9.90  
0.65  
0.25  
-
2.10  
-
-B-  
-A-  
0.45  
6
E
E1  
B1  
D
0.40  
-
13.45  
10.10  
13.45  
10.10  
0.95  
3
D1  
E
4, 5  
3
E1  
L
4, 5  
e
-
N
44  
0.032 BSC  
44  
0.80 BSC  
7
PIN 1  
e
-
SEATING  
PLANE  
Rev. 1 1/94  
-H-  
A
NOTES:  
0.10  
0.004  
1. Controlling dimension: MILLIMETER. Converted inch  
dimensions are not necessarily exact.  
-C-  
o
o
5 -16  
2. All dimensions and tolerances per ANSI Y14.5M-1982.  
3. Dimensions D and E to be determined at seating plane  
4. Dimensions D1 and E1 to be determined at datum plane  
0.40  
0.016  
0.20  
0.008  
MIN  
D
A-B  
M
C
S
S
-C-  
-H-  
.
.
o
0
MIN  
B
A2  
o
A1  
5. Dimensions D1 and E1 do not include mold protrusion.  
Allowable protrusion is 0.25mm (0.010 inch) per side.  
B1  
o
o
0 -7  
6. Dimension B does not include dambar protrusion. Allowable  
dambar protrusion shall be 0.08mm (0.003 inch) total.  
0.13/0.17  
0.005/0.007  
o
5 -16  
L
7. “N” is the number of terminal positions.  
BASE METAL  
WITH PLATING  
0.13/0.23  
0.005/0.009  
62  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)  
D40.6 MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C)  
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE  
c1 LEAD FINISH  
-A-  
-D-  
E
INCHES MILLIMETERS  
MIN  
BASE  
METAL  
(c)  
SYMBOL  
MAX  
0.225  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
2.096  
0.620  
MIN  
-
MAX  
5.72  
NOTES  
A
b
-
-
b1  
M
M
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
0.66  
2
-B-  
(b)  
b1  
b2  
b3  
c
0.58  
3
SECTION A-A  
S
S
S
D
bbb  
C
A - B  
1.65  
-
D
1.14  
4
BASE  
PLANE  
S2  
Q
0.46  
2
A
-C-  
SEATING  
PLANE  
c1  
D
0.38  
3
L
53.24  
15.75  
4
S1  
b2  
eA  
A A  
E
0.510  
12.95  
4
e
0.100 BSC  
2.54 BSC  
-
e
eA/2  
C A - B  
b
C A - B  
c
eA  
eA/2  
L
0.600 BSC  
0.300 BSC  
15.24 BSC  
7.62 BSC  
-
ccc  
D
aaa  
D
S S  
M
S
S
M
-
NOTES:  
0.125  
0.200  
3.18  
5.08  
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.005  
0.070  
0.38  
0.13  
0.13  
1.78  
5
S1  
S2  
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
o
o
o
o
90  
105  
90  
105  
-
aaa  
bbb  
ccc  
M
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
2
8
N
40  
40  
Rev. 0 4/94  
5. Dimension Q shall be measured from the seating plane to the  
base plane.  
6. Measure dimension S1 at all four corners.  
7. Measure dimension S2 from the top of the ceramic body to the  
nearest metallization or lead.  
8. N is the maximum number of terminal positions.  
9. Braze fillets shall be concave.  
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
11. Controlling dimension: INCH.  
63  
INSTRUCTION SET OPCODE MAP  
BIT  
MANIPULATION BRANCH  
READ/MODIFY/WRITE  
CONTROL  
REGISTER/MEMORY  
BTB  
BSC  
REL  
DIR  
3
INH  
INH  
IX1  
IX  
7
INH  
INH  
IMM  
A
DIR  
B
EXT  
IX2  
IX1  
IX  
F
HI  
HI  
0
1
2
4
5
6
8
9
C
D
E
LOW  
0
LOW  
0
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0  
BSET0  
BCLR0  
BSET1  
BCLR1  
BSET2  
BCLR2  
BSET3  
BRA  
BRN  
BHI  
NEG  
NEGA  
NEGX  
NEG  
NEG  
RTI  
SUB  
CMP  
SBC  
CPX  
AND  
BIT  
SUB  
CMP  
SBC  
CPX  
AND  
BIT  
SUB  
SUB  
CMP  
SBC  
CPX  
AND  
BIT  
SUB  
SUB  
CMP  
SBC  
CPX  
AND  
BIT  
3
3
3
3
3
BTB  
2
2
2
2
2
BSC  
2
2
2
2
2
REL  
2
DIR  
1
INH  
1
INH  
2
IX1  
1
IX  
1
1
INH  
6
2
2
2
2
2
IMM  
2
2
2
2
2
DIR  
3
3
3
3
3
3
EXT  
3
3
3
3
3
IX2  
5
2
2
2
2
2
IX1  
4
1
1
1
1
1
IX  
3
CDP68H0516B,DP68HL0516B,DP68HS0516B  
5
5
3
2
4
BRCLR0  
BTB  
RTS  
CMP  
SBC  
CPX  
AND  
BIT  
CMP  
SBC  
CPX  
AND  
BIT  
1
2
3
4
5
1
2
3
4
5
BSC  
REL  
INH  
IMM  
DIR  
3
EXT  
IX2  
5
IX1  
4
IX  
3
5
5
3
11  
2
4
BRSET1  
BTB  
MUL  
COMA  
LSRA  
BSC  
REL  
1
1
1
INH  
3
IMM  
DIR  
3
EXT  
IX2  
5
IX1  
4
IX  
3
5
5
3
5
3
6
5
10  
INH  
2
4
BRCLR1  
BTB  
BLS  
BCC  
BCS  
BNE  
COM  
LSR  
COMX  
LSRX  
COM  
LSR  
COM  
SWI  
BSC  
REL  
2
2
DIR  
5
INH  
3
1
1
INH  
3
2
2
IX1  
6
1
1
IX  
1
IMM  
DIR  
3
EXT  
IX2  
5
IX1  
4
IX  
3
5
5
3
2
4
5
LSR  
BRSET2  
BTB  
BSC  
REL  
DIR  
INH  
INH  
IX1  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
IX  
5
5
3
2
3
4
5
4
3
BRCLR2  
BTB  
3
3
2
2
BSC  
2
2
REL  
2
2
IMM  
2
2
DIR  
3
3
3
EXT  
3
3
IX2  
5
2
2
IX1  
4
1
1
IX  
3
5
5
3
5
2
4
3
3
6
5
BRSET3  
BTB  
ROR  
LDA  
LDA  
LDA  
LDA  
LDA  
LDA  
6
6
RORA  
ASRA  
LSLA  
RORX  
ASRX  
LSLX  
ROR  
ASR  
LSL  
ROR  
ASR  
LSL  
BSC  
REL  
2
DIR  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
1
1
1
1
INH  
3
1
1
1
1
INH  
3
2
2
2
2
IX1  
6
1
1
1
1
IX  
5
5
5
3
5
2
4
5
6
5
4
BRCLR3  
BTB  
BCLR3  
BSET4  
BCLR4  
BEQ  
BHCC  
BHCS  
ASR  
LSL  
TAX  
CLC  
SEC  
STA  
EOR  
ADC  
STA  
EOR  
ADC  
STA  
EOR  
ADC  
STA  
EOR  
ADC  
STA  
EOR  
ADC  
7
8
7
8
3
3
3
2
2
2
BSC  
2
2
2
REL  
2
2
2
DIR  
5
INH  
3
INH  
3
IX1  
6
IX  
5
1
1
1
INH  
2
2
2
2
DIR  
3
3
3
EXT  
3
3
3
IX2  
5
2
2
2
IX1  
4
1
1
1
IX  
3
5
5
3
2
4
BRSET4  
BTB  
EOR  
ADC  
BSC  
REL  
DIR  
5
INH  
3
INH  
3
IX1  
6
IX  
5
INH  
2
2
2
IMM  
DIR  
3
EXT  
IX2  
5
IX1  
4
IX  
3
5
5
3
2
4
BRCLR4  
BTB  
ROL  
ROLA  
ROLX  
ROL  
ROL  
9
9
BSC  
REL  
DIR  
INH  
INH  
IX1  
IX  
INH  
IMM  
DIR  
IX2  
IX1  
IX  
3
3
EXT  
5
5
3
5
3
3
6
5
2
2
3
4
5
4
3
BRSET5  
BTB  
BSET5  
BCLR5  
BSET6  
BCLR6  
BSET7  
BCLR7  
BPL  
BMI  
BMC  
BMS  
BIL  
DEC  
DECA  
DECX  
DEC  
DEC  
CLI  
SEI  
ORA  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
A
B
C
D
E
F
A
B
C
D
E
F
3
3
3
3
3
3
2
2
2
2
2
2
BSC  
2
2
2
2
2
2
REL  
2
DIR  
1
INH  
1
INH  
2
IX1  
1
IX  
1
1
1
1
INH  
2
2
2
IMM  
2
2
2
2
2
2
DIR  
3
EXT  
3
3
3
3
IX2  
5
2
2
2
2
2
2
IX1  
4
1
1
1
1
1
1
IX  
3
5
5
3
2
4
BRCLR5  
BTB  
ADD  
BSC  
REL  
INH  
2
IMM  
DIR  
2
3
EXT  
IX2  
4
IX1  
3
IX  
2
5
5
3
5
3
3
6
5
3
BRSET6  
BTB  
INC  
TST  
INCA  
TSTA  
INCX  
TSTX  
INC  
TST  
INC  
TST  
RSP  
BSC  
REL  
2
2
DIR  
4
1
1
INH  
3
1
1
INH  
3
2
2
IX1  
5
1
1
IX  
4
INH  
2
DIR  
5
3
3
3
3
EXT  
IX2  
7
IX1  
6
IX  
5
5
5
3
6
6
BRCLR6  
BTB  
NOP  
BSR  
LDX  
BSC  
REL  
DIR  
INH  
INH  
IX1  
IX  
INH  
2
2
REL  
DIR  
3
EXT  
IX2  
5
IX1  
4
IX  
3
5
5
3
2
2
4
BRSET7  
BTB  
STOP  
WAIT  
BSC  
REL  
1
1
INH  
2
IMM  
DIR  
4
EXT  
3
IX2  
6
IX1  
5
IX  
4
5
5
3
5
3
3
6
5
2
5
BRCLR7  
BTB  
BIH  
CLR  
CLRA  
CLRX  
CLR  
CLR  
TXA  
BSC  
REL  
2
DIR  
1
INH  
1
INH  
2
IX1  
1
IX  
INH  
1
INH  
DIR  
EXT  
3
3
IX2  
IX1  
IX  
INH = Inherent  
IMM = Immediate  
DIR = Direct  
REL = Relative  
BSC = Bit Set/Clear  
BTB = Bit Test and Branch  
IX = Indexed, No Offset  
IX1 = Indexed, 8-Bit Offset  
IX2 = Indexed, 16-Bit Offset  
HI  
0
MSB of Opcode  
Number of Cycles  
LOW  
0
5
BRSET0 Instruction Mnemonic  
LSB of Opcode  
EXT = Extended  
BTB Number of Bytes/Addressing Mode  
HARRIS CDP68HC05 FAMILY OF MICROCONTROLLERS  
HARRIS PART  
NUMBER  
ROM  
(BYTES)  
RAM  
(BYTES)  
SERIAL  
PORTS  
HSC  
HCL  
TIMER  
I/O  
COP  
VERSION VERSION  
COMMENTS  
PACKAGE  
CDP68HC05C4  
4160  
176  
16 bit;  
1IC, 1OC  
SCI, SPI  
24 i/o,  
7 i  
No  
Yes  
Yes  
Yes  
Yes  
8x8 Unsigned Multiply,  
RC or Crystal Oscillator  
40PDIP, 44PLCC,  
44PQFP, 42SDIP  
CDP68HC05C4B  
4160  
176  
16 bit;  
1IC, 1OC  
SCI, SPI  
24 i/o,  
7 i  
Yes  
8x8 Unsigned Multiply, RC or Crystal Oscillator, 40PDIP, 44PLCC,  
Tone Generator, Keypad Scan Interface, 8 KBI, 44PQFP, 42SDIP  
Mask Option Pull-Ups, STOP Disable,  
CDP68H0516B,DP68HL0516B,DP68HS0516B  
High Current Pin (20mA sink)  
CDP68HC05C8  
CDP68HC05C8B  
7744  
7744  
176  
176  
16 bit;  
1IC, 1OC  
SCI, SPI  
SCI, SPI  
24 i/o,  
7 i  
No  
Yes  
Yes  
Yes  
Yes  
8x8 Unsigned Multiply,  
RC or Crystal Oscillator  
40PDIP, 44PLCC,  
44PQFP, 42SDIP  
16 bit;  
1IC, 1OC  
24 i/o,  
7 i  
Yes  
8x8 Unsigned Multiply, RC or Crystal Oscillator 40PDIP, 44PLCC,  
Tone Generator, Keypad Scan Interface, 8 KPI, 44PQFP, 42SDIP  
Mask Option Pull-Ups, Wake Up Timer,  
High Current Pin (20mA sink)  
CDP68HC05C16B  
CDP68HC05J3  
15936  
2352  
352  
128  
16 bit;  
1IC, 1OC  
SCI, SPI  
None  
31 i/o  
12 i/o  
Yes,  
CM  
Yes  
Yes  
Yes  
Yes  
8x8 Unsigned Multiply, RC or Crystal Oscillator 40PDIP, 44PLCC,  
Tone Generator, Keypad Scan Interface, 8 KPI, 44PQFP, 42SDIP  
Mask Option Pull-Ups, Wake Up Timer,  
High Current Pin (20mA sink)  
16 bit;  
1IC, 1OC  
No  
8x8 Unsigned Multiply, RC or Crystal Oscillator 20PDIP, 20SOIC  
Keypad Scan Interface, 8 KPI,  
External Timer Oscillator,  
Oscillator Start Up Delay  
CDP68HC05J4B  
CDP68HC05JC2  
CDP68HC05P4B  
CDP6805E2  
4160  
4160  
4160  
None  
None  
176  
176  
176  
112  
112  
16 bit;  
1IC, 1OC  
None  
SPI, J1850  
SIOP  
14 i/o  
13 i/o  
Yes  
Yes  
Yes  
No  
Yes  
No  
Yes  
No  
8x8 Unsigned Multiply, RC or Crystal Oscillator, 20PDIP, 20SOIC,  
Keypad San Interface, STOP Disable,  
2 High Current Pins (15mA)  
28PDIP, 28SOIC  
16 bit;  
1IC, 1OC  
8x8 Unsigned Multiply, RC or Crystal Oscillator, 28PDIP, 28SOIC  
Analog Comparator, 10MHz Operation,  
Slow Clock Detect  
16 bit;  
1IC, 1OC  
20 i/o,  
1 i  
Yes  
No  
Yes  
No  
8x8 Unsigned Multiply, RC or Crystal Oscillator, 28PDIP, 28SOIC,  
Keypad San Interface, 8 KPI, Wake Up Timer  
2 High Current Pins (15mA)  
20SOIC  
8 bit,  
7 bit  
prescaler  
None  
13 i/o  
13 i/o  
8k External Address Space  
5MHz Operation  
40PDIP, 44PLCC  
CDP6805E3  
8 bit,  
7 bit  
None  
No  
No  
No  
64k External Address Space  
5MHz Operation  
40PDIP, 44PLCC  
prescaler  
CM=Clock Monitor  
IC= Input Capture  
i=Input Only Port  
i/o=Bidirectional Port  
KPI=Keypad Interrupt  
OC=Output Compare  
J1850=SAE J1850 Serial Communications Interface SIOP=Simple Serial I/O Port  
SCI=Serial Communications Interface  
SPI=Serial Peripheral Interface  
HSC Versions: High Speed Versions, Max f = 8MHz  
HCL Versions: Low Power Versions, Typical Run Power = 1.2mW  
osc  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Bit 7  
I/O  
4
Bit 6  
I/O  
5
Bit 5  
I/O  
6
Bit 4  
I/O  
7
Bit 3  
I/O  
Bit 2  
I/O  
Bit 1  
I/O  
Bit 0  
I/O  
$0000  
$0001  
$0002  
$0003  
PORT A  
Pin Numbers  
Pin Name  
PORT B  
*
*
*
*
8
9
10  
11  
PA7/TONE7 PA6/TONE6 PA5/TONE5 PA4/TONE4  
PA3  
I/O  
PA2  
I/O  
PA1  
I/O  
PA0  
I/O  
I/O  
19  
I/O  
18  
PB6  
I/O  
22  
PC6  
-
I/O  
17  
I/O  
16  
15  
14  
13  
12  
Pin Numbers  
Pin Name  
PORT C  
PB7  
I/O  
PB5  
I/O  
PB4  
I/O  
PB3  
I/O  
PB2  
I/O  
PB1  
I/O  
PB0  
I/O  
21  
23  
24  
25  
26  
27  
28  
Pin Numbers  
Pin Name  
PORT D  
PC7  
I/O  
PC5  
I/O  
PC4  
I/O  
PC3  
I/O  
PC2  
I/O  
PC1  
I/O  
PC0  
I/O  
36  
-
34  
33  
32  
31  
30  
29  
Pin Numbers  
Pin Name  
PD7  
-
PD5/SS  
PD4/SCK  
PD3/MOSI  
PD2/MISO  
PD1/TDO  
PD0/RDI  
$0004  
$0005  
$0006  
$0007  
$0008  
$0009  
$000A  
$000B  
$000C  
$000D  
$000E  
$000F  
$0010  
$0011  
$0012  
$0013  
$0014  
$0015  
$0016  
$0017  
$0018  
$0019  
$001A  
$001B  
$001C  
$001D  
$001E  
$001F  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
DDRA  
DDRB  
DDRC  
DDRD  
UNUSED  
UNUSED  
MSTR  
MODF  
SPIE  
SPIF  
SPE  
DWOM  
0
CPOL  
0
CPHA  
0
SPR1  
0
SPR0  
0
SPCR  
SPSR  
WCOL  
SPI DATA REGISTER  
SPDR  
0
R8  
0
T8  
SCP1  
SCP2  
M
0
WAKE  
TE  
SCR2  
SCR1  
SCR0  
BAUD  
0000  
0
0
0
0
0
0
0
SCCR1  
SCCR2  
SCSR  
TIE  
TCIE  
TC  
RIE  
ILIE  
IDLE  
RE  
NF  
RWU  
FE  
SBK  
0
TDRE  
RDRF  
OR  
SCI DATA REGISTER  
SCDR  
ICIE  
ICF  
OCIE  
OCF  
TOIE  
TOF  
0
0
0
0
0
0
IEDG  
0
OLVL  
0
TCR  
TSR  
Bit 15  
Bit 7  
Bit 15  
Bit 7  
Bit 15  
Bit 7  
Bit 15  
Bit 7  
0
Bit 8  
Bit 0  
Bit 8  
Bit 0  
Bit 8  
Bit 0  
Bit 8  
Bit 0  
WUTE  
Bit 0  
CM0  
CAPHI  
CAPLO  
CMPHI  
CMPLO  
CNTHI  
CNTLO  
ALTHI  
ALTLO  
WUTCR  
COPRST  
COPCR  
RESERVED  
0
Bit 6  
0
0
Bit 5  
0
0
0
0
WUTF  
Bit 1  
Bit 7  
0
Bit 4  
COPF  
Bit 3  
CME  
Bit 2  
COPE  
CM1  
RESERVED  
FIGURE 34. I/O, CONTROL, STATUS, AND DATA REGISTER DEFINITIONS  
0
= UNUSED LOCATION  
* 40 Pin DIP Package Only. For other pinouts, see Page 3.  
66  
CDP68HC05C16B, CDP68HCL05C16B, CDP68HSC05C16B  
Ordering Information Sheet  
A. Device Type (select one):  
CDP68HC05C16B  
CDP68HSC05C16B  
CDP68HCL05C16B  
Chip (H)  
B. Package Type (select one):  
40 Ld Dual-In-Line Plastic (E)  
44 Ld MQFP (Q)  
44 Ld PLCC (N)  
42 Ld Shrink Dual-In-Line (SE)  
Production Packaging  
Bulk (Tubes, sticks or trays)  
Tape and Reel  
C. Select the following microcomputer options. A manufacturing mask will be generated from this information.  
Refer to data sheet or data book instructions for submitting data for ROM patterns.  
Internal Oscillator (select one)  
Wake Up Timer  
Crystal/Ceramic Resonator  
Enabled  
Resistor  
Disabled  
Port B Interrupt/Pullup Options (select all that apply - unselected indicates no interrupt and no pullup)  
PB7 Interrupt and Pullup  
PB6 Interrupt and Pullup  
PB5 Interrupt and Pullup  
PB4 Interrupt and Pullup  
PB3 Interrupt and Pullup  
PB2 Interrupt and Pullup  
PB1 Interrupt and Pullup  
PB0 Interrupt and Pullup  
Port A Tone Options (select all that apply - unselected indicates normal port function)  
PA7 Tone Output  
PA5 Tone Output  
PA7 Open Drain Tone Output  
PA6 Tone Output  
PA5 Open Drain Tone Output  
PA4 Tone Output  
PA6 Open Drain Tone Output  
PA4 Open Drain Tone Output  
D. Customer Company ____________________________________________________________________________  
Address _____________________________________________________________________________________  
City _________________________________________________________________________________________  
Phone ( ____ ) ___________________________________________  
Extension ________________________  
Contact Person _______________________________________________________________________________  
Customer Part Number _________________________________________________________________________  
E. Pattern Media (S-Record Formatted File Should Be Used - Unspecified locations are filled with 0’s)  
1
1
Floppy Disk:  
3 / ”  
5 / ”  
MODEM Upload:  
S-Record Filename _________________  
2
4
Medium if other than above _____________________________________________________________________  
Signature _________________________________________________ Title ______________________________  
Date _____________________________  
67  

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