CG80C286-20 [INTERSIL]

High Performance Microprocessor with Memory Management and Protection; 高性能微处理器与内存管理和保护


型号：	CG80C286-20
厂家：	Intersil
描述：	High Performance Microprocessor with Memory Management and Protection 高性能微处理器与内存管理和保护微处理器
文件：	总13页 (文件大小：501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

80C286/883

High Performance Microprocessor with Memory

Management and Protection

March 1997

Features

Description

• This Circuit is Processed in Accordance to MIL-STD- The Intersil 80C286/883 is a static CMOS version of the

883 and is Fully Conformant Under the Provisions of NMOS 80286 microprocessor. The 80C286/883 is an

Paragraph 1.2.1.

advanced, high-performance microprocessor with specially

optimized capabilities for multiple user and multi-tasking sys-

tems. The 80C286/883 has built-in memory protection that

supports operating system and task isolation as well as pro-

gram and data privacy within tasks. The 80C286/883

includes memory management capabilities that map 230

• Compatible with NMOS 80286/883

• Static CMOS Design for Low Power Operation

- ICCSB = 5mA Maximum

- ICCOP = 185mA Maximum (80C286-10/883)

- ICCOP = 220mA Maximum (80C286-12/883)

(one gigabyte) of virtual address space per task into 2

bytes (16 megabytes) of physical memory.

• Large Address Space

The 80C286/883 is upwardly compatible with 80C86 and

80C88 software (the 80C286/883 instruction set is a super-

set of the 80C86/80C88 instruction set). Using the 80C286/

883 real address mode, the 80C286/883 is object code com-

patible with existing 80C86 and 80C88 software. In pro-

tected virtual address mode, the 80C286/883 is source code

compatible with 80C86 and 80C88 software but may require

upgrading to use virtual address as supported by the

80C286/883’s integrated memory management and protec-

tion mechanism. Both modes operate at full 80C286/883

performance and execute a superset of the 80C86 and

80C88 instructions.

- 16 Megabytes Physical

- 1 Gigabyte Virtual per Task

• Integrated Memory Management, Four-Level Memory

Protection and Support for Virtual Memory and

Operating Systems

• Two 80C86 Upward Compatible Operating Modes

- 80C286/883 Real Address Mode

- Protected Virtual Address Mode

• Compatible with 80287 Numeric Data Co-Processor

The 80C286/883 provides special operations to support the

efficient implementation and execution of operating systems.

For example, one instruction can end execution of one task,

save its state, switch to a new task, load its state, and start

execution of the new task. The segment-not-present excep-

tion and restartable instructions.

Ordering Information

PACKAGE

TEMP. RANGE

10MHz

12.5MHz

CG80C286-12

IG80C286-12

16MHz

20MHz

25MHz

PKG. NO.

G68.B

68 Pin PGA

0^oC to +70^oC

CG80C286-16

CG80C286-20

-40^oC to +85^oC IG80C286-10

G68.B

-55^oC to +125^oC MG80C286-10/883 MG80C286-12/883

5962-9067801MXC 5962-9067802MXC

G68.B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

FN2948.1

128

80C286/883

Pinout

68 LEAD PGA, COMPONENT PAD VIEW

As viewed from underside of the component when mounted on the board.

35 37 39 41

34 36 38 40 42

32 33

43 45 47 49 51

ERROR

44 46 48 50 53 52

BUSY

55 54

57 56

59 58

61 60

63 62

65 64

67 66

CLK

RESET

INTR

NMI

30 31

28 29

PEREQ

READY

HLDA

M/IO

26 27

24 25

22 23

HOLD

20 21

A11

A13

A10

A12

COD/INTA

LOCK

18 19 16 14 12

17 15 13 11

PIN 1 INDICATOR

P.C. BOARD VIEW

As viewed from the component side of the P.C. board.

51 49 47 45 43

41 39 37 35

42 40 38 36 34

33 32

NC ERROR

52 53 50 48 46 44

BUSY

INTR

54 55

56 57

58 59

60 61

62 63

64 65

66 67

CLK

31 30

NMI

RESET A3

29 28

PEREQ

READY

HLDA

M/IO

27 26

25 24

HOLD

COD/INTA

LOCK

23 22

21 20

A10

A12

A11

A13

12 14 16 19 18

11 13 15 17

PIN 1 INDICATOR

129

80C286/883

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage Applied. . . . . . GND -1.0V to V_CC+1.0V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65^oC to +150^oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175^oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300^oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical)

PGA Package . . . . . . . . . . . . . . . . . . . . .

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates

θ_JA

θ_JC

35^oC/W

6^oC/W

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ_JAis measured with the component mounted on an evaluation PC board in free air.

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . . -55^oC to +125^oC

System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)

System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)

Input RISE and FALL Time (From 0.8V to 2.0V

80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)

TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

GROUP A

SUB-

GROUPS

LIMITS

MAX

PARAMETER

Input LOW Voltage

SYMBOL

V_IL

CONDITIONS

V_CC= 4.5V

TEMPERATURE

-55^oC ≤ T_A≤ +125^oC

MIN

-0.5

2.0

UNITS

1, 2, 3

0.8

Input HIGH Voltage

CLK Input LOW Voltage

CLK Input HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

V_IH

V_CC= 5.5V

V_CC+0.5

V_ILC

V_IHC

V_OL

V_CC= 4.5V

-0.5

3.6

1.0

V_CC= 5.5V

V_CC+0.5

I_OL= 2.0mA, V_CC= 4.5V

I_OH= -2.0mA, V_CC= 4.5V

I_OH= -100µA, V_CC= 4.5V

0.4

V_OH

3.0

V_CC-0.4

-10

Input Leakage Current

I_I

V_IN= GND or V_CC

V_CC= 5.5V,

1, 2, 3

-55^oC ≤ T_A≤ +125^oC

µA

Pins 29, 31, 57, 59, 61,

63-64

Input Sustaining Current

LOW

I_BHL

I_BHH

I_SH

V_CC= 4.5V and 5.5V,

1, 2, 3

-55^oC ≤ T_A≤ +125^oC

-50

-30

200

-400

-500

µA

V_IN= 1.0V, Note 1

Input Sustaining Current

HIGH

V_CC= 4.5V and 5.5V,

V_IN= 3.0V, Note 2

Input Sustaining Current

on BUSY and ERROR

Pins

V_CC= 4.5V and 5.5V

V_IN= GND, Note 5

Output Leakage Current

I_O

V_O= GND or V_CC

V_CC= 5.5V,

1, 2, 3

-55^oC ≤ T_A≤ +125^oC

-10

µA

Pins 1, 7-8, 10-28, 32-34

Active Power Supply

Current

I_CCOP

80C286-10/883, Note 4

80C286-12/883, Note 4

V_CC= 5.5V, Note 3

1, 2, 3

-55^oC ≤ T_A≤ +125^oC

185

220

Standby Power

Supply Current

I_CCSB

NOTES:

2. I_BHLshould be measured after lowering V_INto GND and then raising to 1.0V on the following pins: 36-51, 66, 67.

3. I_BHHshould be measured after raising V_INto V_CCand then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.

4. I_CCSBshould be tested with the clock stopped in phase two of the processor clock cycle. V_IN= V_CCor GND, V_CC= 5.5V, outputs unloaded.

5. I_CCOPmeasured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. V_IN= 2.4V or 0.4V, V_CC= 5.5V, outputs unloaded.

6. I_SHshould be measured after raising V_INto V_CCand then lowering to 0V on pins 53 and 54.

130

80C286/883

TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device

Guaranteed and 100% Tested.

80C286/883

10MHz

12.5MHz

GROUP A

PARAMETER

System Clock

SYMBOL

CONDITIONS

SUBGROUPS

TEMPERATURE

MIN MAX MIN MAX UNITS

_CC= 4.5V and 5.5V

9, 10, 11

-55^oC ≤ T_A≤ +125^oC

(CLK) Period

System Clock

(CLK) Low Time

V_CC= 4.5V and 5.5V

at 1.0V

-55^oC ≤T_A≤ +125^oC

-55^oC ≤ T_A≤ +125^oC

System Clock (CLK)

High Time

V_CC= 4.5V and 5.5V

at 3.6V

Asynchronous Inputs

SETUP Time

(Note 1)

_CC= 4.5V

and 5.5V

Asynchronous Inputs

HOLD Time

_CC= 4.5V

9, 10, 11

-55^oC ≤ T_A≤ +125^oC

and 5.5V

(Note 1)

RESET SETUP Time

RESET HOLD Time

_CC= 4.5V

9, 10, 11

-55^oC ≤ T_A≤ +125^oC

-55^oC ≤T_A≤ +125^oC

-55^oC ≤ T_A≤ +125^oC

and 5.5V

V_CC= 4.5V

and 5.5V

Read Data

SETUP Time

V_CC= 4.5V

and 5.5V

Read Data

HOLD Time

V_CC= 4.5V

and 5.5V

READY SETUP Time

READY HOLD Time

12A

V_CC= 4.5V

and 5.5V

V_CC= 4.5V

and 5.5V

Status/PEACKActive

Delay, (Note 4)

V_CC= 4.5V and

5.5V, C_L= 100pF

I_L= |2mA|

Status/PEACK

Inactive Delay

(Note 3)

12B

_CC= 4.5V and

9, 10, 11

-55^oC ≤ T_A≤ +125^oC

5.5V, C_L= 100pF

I_L= |2mA|

Address Valid

Delay (Note 2)

V_CC= 4.5V and

5.5V, C_L= 100pF

I_L= |2mA|

Write Data

V_CC= 4.5V and

Valid Delay, (Note 2)

5.5V, C_L= 100pF

I_L= |2mA|

131

80C286/883

TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device

Guaranteed and 100% Tested.

80C286/883

10MHz

MIN MAX MIN MAX UNITS

47 25 ns

12.5MHz

GROUP A

SUBGROUPS

PARAMETER

SYMBOL

CONDITIONS

TEMPERATURE

HLDA Valid Delay

(Note 5)

V_CC= 4.5V and

5.5V, C_L= 100pF

IL = |2mA|

9, 10, 11

-55^oC ≤ T_A≤ +125^oC

NOTES:

1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure

recognition at a specific CLK edge.

2. Delay from 1.0V on the CLK to 0.8V or 2.0V.

3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).

4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).

5. Delay from 1.0V on the CLK to 2.0V.

TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS

80C286/883

10MHz

12.5MHz

MIN MAX

PARAMETER

CLK Input Capacitance

Other Input Capacitance

I/O Capacitance

SYMBOL CONDITIONS

NOTES

TEMPERATURE

T_A= +25^oC

MIN

MAX

UNITS

C_CLK

C_IN

C_I/O

FREQ = 1MHz

FREQ = 1MH

T_A= +25^oC

Address/Status/Data

Float Delay

1, 3, 4, 5

-55^oC ≤ T_A≤ +125^oC

Address Valid to Status

SETUP Time

I_L= | 2.0mA|

1, 2, 5

-55^oC ≤ T_A≤ +125^oC

NOTES:

1. Output Load: C_L= 100pF.

2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching

2.0V.

3. Delay from 1.0V on the CLK to Float (no current drive) condition.

4. I_L= -6mA (V_OHto Float), I_L= 8mA (V_OLto Float).

5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-

acterized upon initial design and after major process and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS

Initial Test

METHOD

100%/5004

100%

SUBGROUPS

Interim Test

PDA

1, 7, 9

Final Test

100%

2, 3, 8A, 8B, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 7, 9

Group A

Group C & D

Samples/5005

132

80C286/883

AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is

Implied.

82C284 Timing

10MHz

12.5MHz

MIN

SYMBOL

PARAMETER

MIN

MAX

UNIT

TEST CONDITION

TIMING REQUIREMENTS

SRDY/SRDYEN Setup Time

SRDY/SRDYEN Hold Time

ARDY/ARDYEN Setup Time

ARDY/ARDYEN Hold Time

(Note 1)

TIMING RESPONSES

19 PCLK Delay

C_L= 75pF, I_OL= 5mA,

I_OH= -1mA

NOTE:

1. These times are given for testing purposes to ensure a predetermined action.

82C288 Timing

10MHz

12.5MHz

MIN MAX

SYMBOL

PARAMETER

MIN

MAX

UNIT

TEST CONDITION

TIMING REQUIREMENTS

CMDLY Setup Time

CMDLY Hold Time

TIMING RESPONSES

ALE Active Delay

ALE Inactive Delay

DT/R Read Active Delay

DEN Read Active Delay

C_L= 150pF

I_OL= 16mA Max

I_OH= -1mA Max

DEN Read Inactive Delay

DT/R Read Inactive Delay

DEN Write Active Delay

DEN Write Inactive Delay

Command Active Delay from CLK

Command Inactive Delay from CLK

C_L= 300pF

I_OL= 32mA Max

133

80C286/883

AC Specifications

4.0V

3.6V

CLK INPUT

0.45V

1.0V

4.0V

3.6V

CLK INPUT

1.0V

0.45V

2.4V

t_SETUP

t_HOLD

2.0V

0.8V

2.0V

OTHER

DEVICE

INPUT

0.8V

0.4V

t_DELAY(MAX)

t_DELAY(MIN)

2.0V

0.8V

DEVICE

OUTPUT

NOTE:

1. For AC testing, input rise and fall times are driven at 1ns per volt.

FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT

134

80C286/883

135

80C286/883

Waveforms

READ CYCLE

ILLUSTRATED WITH ZERO

WAIT STATES

WRITE CYCLE

ILLUSTRATED WITH ONE

WAIT STATE

READ

(T_IOR T_S)

T_I

T_S

T_C

T_S

T_C

BUS CYCLE TYPE

V_OH

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

CLK

12A

12B

V_OL

S1 • S0

₂₃- A₀

M/IO,

VALID ADDRESS

VALID IF T_S

COD INTA

VALID CONTROL

BHE, LOCK

VALID WRITE DATA

D₁₅- D₀

VALID READ DATA

READY

SRDY +

SRDYEN

ARDY +

ARDYEN

PCLK

ALF

CMDLY

MWTC

(SEE NOTE 1)

MRDC

DT/R

DEN

NOTES:

1. The modified timing is due to the CMDLY signal being active.

2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.

FIGURE 2. MAJOR CYCLE TIMING

136

80C286/883

Waveforms (Continued)

BUS CYCLE TYPE

V_CH

T_X

φ2

φ1

φ2

φ1

CLK

V_CL

(SEE NOTE 1)

PCLK

(SEE NOTE 1)

RESET

T_X

φ2

V_CH

φ1

φ2

INTR, NMI

HOLD, PEREQ

(SEE NOTE 2)

CLK

V_CL

(SEE NOTE 1)

RESET

ERROR, BUSY

(SEE NOTE 2)

NOTES:

1. PCLK indicates which processor cycle phase will occur on the

next CLK. PCLK may not indicate the correct phase until the first

cycle is performed.

NOTE:

1. When RESET meets the setup time shown, the next CLK will

2. These inputs are asynchronous. The setup and hold times shown

assure recognition for testing purposes.

start or repeat φ1 of a processor cycle.

FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-

QUENT PROCESSOR CYCLE PHASE

FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL

TIMING

137

80C286/883

Waveforms (Continued)

T_H

T_HOR T_I

φ1

T_I

T_H

BUS CYCLE TYPE

V_CH

φ1

φ2

φ1

φ2

φ1

φ2

CLK

V_CL

HILDA

(SEE NOTE 4)

(NOTE 3)

12A

IF T_S

(SEE NOTE 3)

S1 • S0

12B

PEACK

IF NPX TRANSFER

(SEE NOTE 1)

BHE, LOCK

A₂₃- A₀,

(SEE NOTE 5)

VALID

M/IO,

COD/INTA

(SEE NOTE 2)

(SEE NOTE 6)

₁₅- D₀

PCLK

VALID IF WRITE

NOTES:

1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.

2. The data bus will be driven as shown if the last cycle before T_Iin the diagram was a write T_C.

3. The 80C286/883 puts its status pins in a high impedance logic one state during T_H.

4. For HOLD request set up to HLDA, refer to Figure 8.

5. BHE and LOCK are driven at this time but will not become valid until T_S.

6. The data bus will remain in a high impedance state if a read cycle is performed.

FIGURE 5. EXITING AND ENTERING HOLD

138

80C286/883

Waveforms (Continued)

BUS CYCLE TYPE

T_I

T_S

T_C

T_S

T_C

T_I

V_CH

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

CLK

V_CL

I/0 READ IF PROC. EXT. TO MEMORY

MEMORY READ IF MEMORY TO PROC. EXT

MEMORY WRITE IF PROC. EXT. TO MEMORY

I/O WRITE IF MEMORY TO PROC. EXT.

S1 • S0

CLK

MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O

PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER

A₂₃-A₀

M/IO,

COD INTA

I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER

MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER

12A

12B

PEACK

(SEE NOTE 1)

(SEE NOTE 2)

PEREQ

NOTES:

1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation

will be either a memory read at operand address or I/O read at port address 00FA(H).

2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x

- 12A_MAX-(4)_MIN

(4)

The actual, configuration dependent, maximum time is: 3 x

- 12A_MAX

+N x 2 x ⁽¹⁾. N is the number of extra T_Cstates added

MIN

to either the first or second bus operation of the processor extension data operand transfer sequence.

FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY

BUS CYCLE TYPE

T_X

T_I

V_CH

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

CLK

V_CL

(SEE NOTE 2)

(SEE NOTE 1)

RESET

AT LEAST

16 CLK PERIODS

12B

S1 • S0

PEACK

UNKNOWN

A₂₃- A₀

BHE

UNKNOWN

M/IO

COD/INTA

LOCK

UNKNOWN

(SEE NOTE 3)

DATA

HILDA

UNKNOWN

NOTES:

1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.

2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.

3. The data bus is only guaranteed to be in a high impedance state at the time shown.

FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET

BUS HOLD

BUS HOLD ACKNOWLEDGE

WRITE CYCLE

ACKNOWLEDGE

BUS CYCLE TYPE

CLK

T_HT_HT_H

T_S

T_C

T_I

T_H

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

139

(SEE NOTE 5)

80C286/883

Die Characteristics

DIE DIMENSIONS:

GLASSIVATION:

286 x 283 x 19 ±1mils

Type: Nitrox

Thickness: 10kÅ

METALLIZATION:

Type: Si-Al

WORST CASE CURRENT DENSITY: 2 X 10 A/cm

Thickness: 8kÅ

LEAD TEMPERATURE: (10s Soldering): ≤ 300 C

Metallization Mask Layout

80C286/883

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Spec Number

140

CG80C286-20 [INTERSIL]

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