D2-45057-QR [INTERSIL]
Intelligent Digital Amplifier PWM Controller and Audio Processor; 智能数字放大器PWM控制器和音频处理器型号: | D2-45057-QR |
厂家: | Intersil |
描述: | Intelligent Digital Amplifier PWM Controller and Audio Processor |
文件: | 总31页 (文件大小:412K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Intelligent Digital Amplifier PWM Controller and
Audio Processor
D2-45057, D2-45157
Features
• All Digital Class-D Amplifier and Controller with
Integrated Digital Signal Processing (DSP)
The D2-45057 and D2-45157 devices are complete
System-on-Chip (SoC) Class-D digital audio amplifiers.
Combining high performance integrated Power Stages
along with an optimized Audio Processor feature set and
PWM Controller, these devices offer a complete,
powerful, and very cost effective audio solution for high
volume and cost-critical products.
• Four Integrated Power Stages Supporting
- 2 Channels, Bridged
- 4 Channels, Half-Bridge
- 2 Channels, Half-Bridge, plus 1 Channel Bridged
• Output Power (Bridged)
- 25W (8Ω, <1% THD); 30W (8Ω, <10% THD)
This 4th generation Digital Audio Engine (DAE-4P)™
device combines extensive integrated Digital Signal
Processor (DSP) audio processing with amplifier control,
for a complete audio solution. Its ease of integration into
the existing system processor provides complete support
for all system product and amplifier functions.
• Fully Programmable Digital Signal Processing (DSP)
- Up to 5 Programmable Audio Signal Path Channels
- Programmable Equalizers, Filters, Mixers, Limiters
• Includes D2Audio™ SoundSuite™ and
The four configurable Power Stages operate as four
separate Half-Bridge outputs, as two Full-Bridge outputs,
or in combinations of Half-Bridge plus Full-Bridge,
providing flexible loudspeaker drive solutions. Separate
PWM outputs provide additional combinations to drive
headphone, or line level stereo and subwoofer outputs.
SRS WOW/HD™ Audio Enhancement Algorithms
2
• I S and S/PDIF™ Digital Audio Inputs
• Asynchronous Sample Rate Converters;
Sample Rates from 32kHz up to 192kHz
• Wide 9V to 26V Power Stage HV Supply Range, plus
Internally-Generated Gate Drive Supply
• Temperature and Undervoltage Monitoring
and Individual Channel Protection
Related Literature
• DAE-4/DAE-4P Register API Specification
• DAE-4P Evaluation Kit Guides
Applications
• PC/Multimedia Speakers
• Digital TV Audio Systems
• Portable Device Docking Stations
• Powered Speaker Systems
Typical System Implementation
Amplifier Output 1
Output
Digital
I2S
Audio
Amplifier Output 2
SoC
System
Controller(s)
Filter
24 Bit
Digital
Signal
2 Channel
Sample
Rate
Amplifier
Output
MOSFETS
Interface
5 Channel
PWM
Engine
Amplifier Output 3
Amplifier Output 4
Output
Filter
I2C
I2C
Processor
Converter
Control
PWM
Output
Drive
PWM
Output
Subwoofer
Optical/
Coax IN
S/PDIF
Buffer
Filter
Line Out
D2Audio®
Audio Canvas™
Processing
3rd Party
S/PDIF
Digital I/O
Interface
D2Audio®
SoundSuite™
ENHANCEMENTS
(SRS WOW/HD®)
PWM
PWM
Output
Filter
Stereo
Line Out
OR
Optical/
Coax OUT
S/PDIF
Buffer
Output
Filter
(Optional)
Headphone
Out
D2-45x57-QR
DAE-4P™ Intelligent Digital Power Amplifier and Audio Processor
(Optional)
SYSTEM APPLICATION IMPLEMENTING 2X FULL-BRIDGE LOUDSPEAKER OUTPUTS PLUS 3 LINE-LEVEL OUTPUTS
July 29, 2010
FN6785.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
D2-45057, D2-45157
Ordering Information
PART
AUDIO PROCESSING
NUMBER
(Notes 3, 4)
PART
MARKING
FEATURE SET SUPPORT
(Note 1)
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
D2-45057-QR
D2-45057-QR D2Audio™ SoundSuite™
-10 to +85 68 Ld QFN
L68.10x10C
L68.10x10C
D2-45057-QR-T (Note 2) D2-45057-QR D2Audio™ SoundSuite™
-10 to +85 68 Ld QFN
(1k pcs.) Tape and Reel
D2-45157-QR
D2-45157-QR SRS WOW/HD™
-10 to +85 68 Ld QFN
L68.10x10C
L68.10x10C
D2-45157-QR-T (Note 2) D2-45157-QR SRS WOW/HD™
-10 to +85 68 Ld QFN
(1k pcs.) Tape and Reel
NOTES:
1. The D2-45057, D2-45157 support audio processing algorithms for the D2Audio™ SoundSuite™, and SRS WOW/HD™ audio
enhancement features. Algorithm support of these enhancements is device-dependent. Refer to specific part number for
desired feature support.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for D2-45057, D2-45157. For more information on
MSL please see techbrief TB363.
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D2-45057, D2-45157
Table of Contents
Ordering Information ........................................ 2
Absolute Maximum Ratings ............................... 4
Thermal Information ......................................... 4
Recommended Operating Conditions................. 4
Electrical Specifications..................................... 4
Performance Specifications ............................... 6
Serial Audio Interface Port Timing .................... 6
Control and Operation..................................... 19
Control Register Summary............................... 19
2
I C 2-Wire Control Interface ............................ 19
Reading and Writing Control Registers............... 19
Control Interface Address Spaces ..................... 20
Storing Parameters to EEPROM......................... 20
Serial Peripheral Interface (SPI) ....................... 20
Reset and Device Initialization.......................... 20
Boot Modes.................................................... 21
Power Supply Requirements ........................... 21
2
Two-Wire (I C) Interface Port Timing............... 7
High-Side Gate Drive Voltage........................... 21
Power Supply Synchronization.......................... 21
Power Sequence Requirements......................... 22
REG5V .......................................................... 22
SPI™ Master Mode Interface Port Timing .......... 8
SPI™ Slave Mode Interface Port Timing ............ 8
Pin Configuration............................................... 9
Pin and Control Block Functions...................... 22
Pin Description................................................ 10
I/O Control Pins ............................................. 22
nPDN Input Pin .............................................. 22
nERROR[0-3] Output Pins................................ 22
IREF Pin........................................................ 22
Configuration Assignment Pin Differences .......... 22
OCFG0, OCFG1 Input Pins................................ 23
nERROR/CFG0 and PSSYNC/CFG1 Pins .............. 23
Temperature Monitoring .................................. 23
Typical Performance Characteristics................ 14
Test Considerations.........................................14
Full-Bridge Typical Performance Curves..............14
Half-Bridge Typical Performance Curves .............15
Functional Description..................................... 17
Overview .......................................................17
Audio Enhancement Features............................17
Serial Audio Digital Input .................................17
S/PDIF Digital Audio I/O ..................................17
Sample Rate Converter....................................18
DSP...............................................................18
Clock and PLL.................................................18
Timers...........................................................18
Configuration Setting...................................... 24
Protection ....................................................... 26
Error Reporting .............................................. 26
Short-Circuit and Overcurrent Sensing .............. 26
Protection Monitoring and Control..................... 26
Thermal Protection and Monitors....................... 26
Graceful Overcurrent and Short Circuit .............. 27
Power Supply Voltage Monitoring...................... 27
Audio Outputs ................................................. 18
Output Power Stages.......................................18
Output Options ...............................................19
PWM Audio Outputs.........................................19
Audio Processing............................................. 27
Audio Processing Signal Flow Blocks.................. 27
Revision History.............................................. 30
Products.......................................................... 30
Package Outline Drawing ................................ 31
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D2-45057, D2-45157
Absolute Maximum Ratings
Thermal Information
Supply Voltage
Thermal Resistance (Typical)
θ
JA (°C/W) θJC (°C/W)
25
HVDD[A:D], VDDHV. . . . . . . . . . . . . . . . -0.3V to +28.0V
RVDD, PWMVDD . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . .-0.3V to RVDD +0.3V
XTALI. . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . .±10mA
68 Ld QFN Package (Notes 5, 6) . .
1
Maximum Storage Temperature . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
High Voltage Supply Voltage,
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . .9.0V to 26.5V
Digital I/O Supply Voltage, PWMVDD. . . . . . . . . . . . . . 3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . 1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . 1.8V
Minimum Load Impedance (HVDD[A:D] ≤24.0V), Z . . . . 4Ω
L
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications T = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
A
±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at
147.456MHz with typical audio data traffic.
TEST
PARAMETER
Digital Input High Logic Level (Note 8)
Digital Input Low Logic Level (Note 8)
High Level Output Drive Voltage
CONDITIONS
SYMBOL
MIN
TYP
MAX UNIT
V
2
-
-
-
-
0.8
-
V
V
V
IH
V
-
IL
V
RVDD - 0.4
OH
(I
at -Pin Drive Strength Current)
OUT
Low Level Output Drive Voltage
(I at +Pin Drive Strength Current)
V
-
-
0.4
V
OL
OUT
High Level Input Drive Voltage XTALI Pin
Low Level Input Drive Voltage XTALI Pin
Input Leakage Current (Note 9)
Input Capacitance
V
0.7
-
-
PLLVDD
V
V
IHX
V
-
-
-
-
0.3
±10
-
ILX
I
-
µA
pF
pF
IN
Cin
9
9
Output Capacitance
All Outputs Except
OUT[A:D]
Cout
-
OUT[A:D]
-
-
-
190
10
-
-
-
pF
ns
nRESET Pulse Width
t
RST
Internal Pull-Up Resistance to PWMVDD
(for nERROR0-3, OCFG, nPDN)
-
100
kΩ
Digital I/O Supply Pin Voltage, Current
Core Supply Pins
RVDD
and
PWMVDD
3
-
3.3
10
3.6
V
Active Current
-
-
mA
mA
V
Power-Down Current
-
0.01
1.8
300
6
CVDD
1.7
-
1.9
-
Active Current
mA
mA
Power-Down Current
(Note 10)
-
-
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D2-45057, D2-45157
Electrical Specifications T = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
A
±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at
147.456MHz with typical audio data traffic. (Continued)
TEST
PARAMETER
Analog Supply Pins (PLL)
CONDITIONS
SYMBOL
MIN
TYP
1.8
10
MAX UNIT
PLLVDD
1.7
1.9
V
Active Current
-
-
-
-
mA
mA
Power-Down Current
(Note 10)
5
CRYSTAL OSCILLATOR
Crystal Frequency (Fundamental Mode Crystal)
Duty Cycle
Xo
Dt
20
40
-
24.576
25
60
20
MHz
%
-
Start-up Time (Start-up Time is Oscillator Enabled
(with Valid Supply) to Stable Oscillation)
t
5
ms
START
PLL
VCO Frequency
F
240
-
294.912
3
300
-
MHz
ms
VCO
PLL Lock Time from any Input Change
1.8V POWER-ON RESET
Reset Enabled Voltage Level
POR Minimum Output Pulse Width
1.8V BROWNOUT DETECTION
Detect Level
V
0.95
-
1.1
5
1.3
-
V
EN
t
µs
DIS
1.4
1.5
100
20
1.7
V
Pulse Width Rejection
t
-
-
-
-
ns
ns
BOD1
Minimum Output Pulse Width
3.3V (PWMVDD) BROWNOUT DETECTION
Detect Level
t
O1
2.5
2.7
100
20
2.9
V
Pulse Width Rejection
t
-
-
-
-
ns
ns
BOD3
Minimum Output Pulse Width
t
O3
GATE DRIVE INTERNAL +5V BROWN-OUT DETECTION
Gate Drive Supply Undervoltage Threshold
-
-
-
4.5
200
50
-
-
-
V
Gate Drive Supply Undervoltage Threshold Hysteresis
mV
ns
Gate Drive Supply Undervoltage Threshold Glitch
Rejection
PROTECTION DETECT
High Voltage (+VDDHV) Undervoltage Protection
Overcurrent Trip Threshold
-
-
-
-
-
-
-
7
4
9
-
-
-
-
-
-
V
A
Overcurrent De-glitch
2.5
8
ns
A
Short-Circuit Current Limit (Peak)
Overcurrent Response Time
20
140
30
ns
°C
°C
Thermal Shut-Down (Power Stages)
Thermal Shut-Down Hysteresis (Power Stages)
NOTES:
8. All input pins except XTALI.
9. Input leakage applies to all pins except XTALO.
10. Power-down is with device in reset and clocks stopped.
FN6785.0
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D2-45057, D2-45157
Performance Specifications T = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%,
A
RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz,
core running at 147.456MHz with typical audio data traffic.
PARAMETER
(Maximum, MOSFETs @ +25°C)
Mismatch
SYMBOL
MIN
TYP
200
1
MAX
UNIT
mΩ
%
r
r
r
-
-
-
-
-
-
-
-
-
-
DS(ON)
DS(ON)
DS(ON)
PWM Switching Rate
384
1.4
1.4
kHz
ms
nPDN Input Off Delay
t
PDNOFF
nPDN Input On Delay
t
ms
PDNON
POWER OUTPUT
<1% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
<10% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
<1% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
<10% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
THD+N
P
P
P
P
-
-
-
-
25
30
7
-
-
-
-
W
W
W
W
OUT
OUT
OUT
OUT
9
Load = 8Ω, Power = 25W, Bridged, 1kHz
Load = 8Ω, Power = 1W, Bridged, 1kHz
SNR
THD+N
SNR
-
-
-
-
0.3
0.05
110
90
-
-
-
-
%
%
dB
%
Efficiency (Power Stage, Load = 8Ω)
Serial Audio Interface Port Timing T = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%,
A
RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core
running at 147.456MHz with typical audio data traffic.
SYMBOL
t SCLK
DESCRIPTION
SCLK Frequency - (SCLK)
MIN
-
TYP
MAX
UNIT
MHz
ns
-
-
-
-
-
-
12.5
c
t SCLK
SCLK Pulse Width (high and low) - (SCLK)
LRCKR Setup to SCLK Rising - (LRCK)
LRCKR Hold from SCLK Rising - (LRCK)
SDIN Setup to SCLK Rising - (SDIN)
SDIN Hold from SCLK Rising - (SDIN)
40
20
20
20
20
-
-
-
-
-
w
t LRCLK
ns
s
t LRCLK
ns
h
t SDI
ns
s
t SDI
ns
h
tcSCLK
twSCLK
SCLK
thLRCLK
LRCK
twSCLK
tsLRCLK
tsSDI
SDIN
thSDI
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
FN6785.0
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D2-45057, D2-45157
2
Two-Wire (I C) Interface Port Timing T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
A
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
-
MAX
UNIT
kHz
µs
f
SCL Frequency
100
SCL
t
Bus Free Time Between Transmissions
SCL Clock Low
4.7
4.7
4.0
4.7
4.0
-
-
-
-
-
buf
t
SCLx
µs
wlow
t
SCLx
SCL Clock High
µs
whigh
t STA
Setup Time For a (Repeated) Start
Start Condition Hold Time
µs
s
t STA
µs
h
t SDAx
SDA Hold From SCL Falling (Note 11)
SDA Setup Time to SCL Rising
SDA Output Delay Time From SCL Falling
Rise Time of Both SDA and SCL (Note 12)
Fall Time of Both SDA and SCL (Note 12)
Setup Time For a Stop Condition
1 (typical)
sys clk
ns
h
t SDAx
250
-
3.5
1
s
t SDAx
-
-
µs
d
t
µs
r
t
-
300
-
ns
f
t STO
4.7
µs
s
NOTES:
11. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
12. Limits established by characterization and not production tested.
twhighSCLx
tr
tf
twlowSCLx
SCLx
tsSTA
thSDAx
tsSTO
tsSDAx
tbuf
SDAx
(INPUT)
thSTAx
SDAx
(OUTPUT)
tdSDAx
2
FIGURE 2. I C INTERFACE TIMING
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D2-45057, D2-45157
SPI™ Master Mode Interface Port Timing T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
A
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MOSI Valid From Clock Edge
MIN
-
MAX
UNIT
ns
t
t
8
V
S
H
MISO Setup to Clock Edge
MISO Hold From Clock Edge
nSS Minimum Width
10
-
ns
t
1 system clock + 2ns
3 system clocks + 2ns
t
WI
SPI™ Slave Mode Interface Port Timing T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
A
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MISO Valid From Clock Edge
MIN
MAX
UNIT
t
t
3 system clocks + 2ns
-
V
S
H
MOSI Setup to Clock Edge
MOSI Hold From Clock Edge
nSS Minimum Width
10
ns
t
1 system clock + 2ns
3 system clocks + 2ns
t
WI
SCK(CPHA = 1, CPOL = 0)
SCK(CPHA = 0, CPOL = 0)
tV
tV
MOSI
tH
tS
MISO(CPHA = 0)
nSS
tWI
FIGURE 3. SPI TIMING
FN6785.0
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D2-45057, D2-45157
Pin Configuration
D2-45057, D2-45157
(68 LD QFN)
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
nRESET
TEMPCOM/TIO0
SDA
1
2
3
4
5
6
7
8
9
51 OUTA
50 HSBSA
49 HSBSB
48 OUTB
47 HGNDB
46 HVDDB
45 REG5V
44 VDDHV
43 IREF
SCL
SCLK
SDIN
LRCK
MCLK
CVDD
CGND 10
RGND 11
42 DNC
41 SUBOUT
40 HVDDC
39 HGNDC
38 OUTC
RVDD 12
TEMPREF/SCK 13
nMUTE/TIO1 14
VOL1/MISO 15
TEMP1/MOSI 16
SPDIFRX 17
37 HSBSC
36 HSBSD
35 OUTD
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
FN6785.0
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D2-45057, D2-45157
Pin Description
PIN
NAME
PIN (Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
1
nRESET
I
3.3
Active low reset input with hysteresis. Low level activates system level reset, initializing all
internal logic and program operations. System latches boot mode selection on the IRQ input
pins on the rising edge.
2
3
4
TEMPCOM/ I/O
TIO0
3.3
3.3
3.3
Board temperature monitor common I/O pin. When operating as output, provides 16mA
drive strength.
SDA
I/O
Two-Wire Serial data port, open drain driver with 8mA drive strength. Bidirectional signal
used by both the master and slave controllers for data transport. Pin floats on reset.
SCL
I/O
Two-Wire Serial clock port, open drain driver with 8mA drive strength. Bidirectional signal
is used by both the master and slave controllers for clock signaling. Pin floats on reset.
2
5
6
7
8
SCLK
SDIN
LRCK
MCLK
I
I
3.3
3.3
3.3
3.3
I S Serial Audio Bit Clock (SCLK) Input. Input has hysteresis.
2
I S Serial Audio Data (SDIN) Input. Input has hysteresis.
2
I
I S Serial Audio Left/Right (LRCK) Input. Input has hysteresis.
2
O
I S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset.
Output is an 8mA driver.
9
CVDD
CGND
RGND
RVDD
P
3.3
3.3
3.3
3.3
Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.
Core ground.
10
11
12
GND
GND
P
Digital pad ring ground. Internally connected to PWMGND.
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. There are 2 of these pins and both are required to be
connected. Internally connected to PWMVDD.
13 TEMPREF/ I/O
SCK
3.3
Reference pin for temperature monitor and SPI clock. At de-assertion of device reset, pin
operates as SPI clock with 8mA drive strength. Upon internal D2-45057, D2-45157 firmware
execution, pin becomes temperature monitor reference.
14
15
nMUTE/
TIO1
O
3.3
3.3
Mute signal output. Low active: mute condition drives pin low. Output is a 16mA driver.
Initializes as input on reset, then becomes output upon internal firmware execution.
VOL1/
MISO
I/O
Volume control pulse input and SPI master- input/slave-output data signal. At de-assertion
of device reset, pin operates as SPI master input or slave output. (When operating as
output, provides 4mA drive strength.) Then upon internal D2-45057, D2-45157 firmware
execution, pin becomes input for monitoring up/down phase pulses from volume control.
(1 of 2 volume input pins.)
16
TEMP1/
MOSI
I/O
3.3
Board temperature monitor pin, and SPI master-output/slave-input data signal. At de-
assertion of device reset, pin operates as SPI master output or slave input. (When operating
as output, provides 4mA drive strength.) Then upon internal D2-45057, D2-45157 firmware
execution, pin becomes input for monitoring board temperature.
17 SPDIFRX
I
3.3
3.3
S/PDIF Digital audio data input
18
SPDIFTX
O
S/PDIF Digital audio data output This pin is the S/PDIF audio output and drives a 8mA, 3.3V
stereo output up to 192kHz. Pin floats on reset.
19
20
TEST
IRQA
I
I
3.3
3.3
Hardware test mode control. For factory use only. Must be tied low.
Interrupt request port A. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low
logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle.
21
IRQB
I
3.3
Interrupt request port B. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low
logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle.
22
23
RGND
RVDD
GND
P
3.3
3.3
Digital pad ring ground. Internally connected to PWMGND.
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. There are 2 of these pins and both are required to be
connected. Internally connected to PWMVDD.
FN6785.0
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10
D2-45057, D2-45157
Pin Description(Continued)
PIN
NAME
PIN (Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
24 nERROR/
CFG0
I/O
3.3
Output configuration selection input, and nERROR output. Upon device reset, pin operates
as input, using application-installed pull-up or pull-down connection to pin to specify one of
4 amplifier configurations. Upon internal D2-45057, D2-45157 firmware execution, pin
becomes output, providing active-low output drive when amplifier protection monitoring
detects an error condition. When operating as output, provides 4mA drive strength. (Note:
This pin may also be referenced as “PSCURR” on some reference designs. Function is
identical regardless of name.)
25 PSSYNC/
CFG1
I/O
3.3
Output configuration selection input, and power supply sync output. Upon device reset, pin
operates as input, using application-installed pull-up or pull-down connection to pin to
specify one of 4 amplifier configurations. Upon internal D2-45057, D2-45157 firmware
execution, pin becomes output, providing synchronizing signal to on-board power supply
circuits. When operating as output, provides 4mA drive strength. Note: This pin may also
be referenced as “PSTEMP” on some reference designs. Function is identical regardless of
name.
26 PROTECT0 I/O
27 PROTECT1 I/O
28 PROTECT2 I/O
3.3
3.3
3.3
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
29 nERROR0
30 nERROR1
31 nERROR2
32 nERROR3
O
O
O
O
P
3.3
3.3
3.3
3.3
HV
Overcurrent protection output, channel A output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
Overcurrent protection output, channel B output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
Overcurrent protection output, channel C output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
Overcurrent protection output, channel D output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
33
34
HVDDD
HGNDD
Output stage D high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
GND
HV
Output stage D high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
35
36
37
38
39
OUTD
HSBSD
HSBSC
OUTC
O
HV
HV
HV
HV
HV
PWM power amplifier output, channel D.
I
I
High-side boot strap input, output channel D. Capacitor couples to OUTD amplifier output.
High-side boot strap input, output channel C. Capacitor couples to OUTC amplifier output.
PWM power amplifier output, channel C.
O
HGNDC
GND
Output stage C high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
40
HVDDC
P
HV
Output stage C high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
41
42
SUBOUT
DNC
O
-
3.3
-
“Subwoofer” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output to subwoofer.
Do not connect to this pin.
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D2-45057, D2-45157
Pin Description(Continued)
PIN
NAME
PIN (Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
43
44
45
46
47
IREF
I
-
+HV
5
Overcurrent reference analog input. Used in setting the overcurrent error detect externally-
set threshold. The pin needs to be connected to a 100kΩ resistor to ground to set the
overcurrent threshold according to the specified limits.
VDDHV
REG5V
HVDDB
HGNDB
P
High Voltage internal driver supply power. All of the HVDD[A:D] pins and the VDDHV pin
connect to the system “HV” power source. The internal +5V supply regulators also operate
from this VDDHV input.
P
5V internal regulator filter connect. A +5V supply is internally generated from the voltage
source provided at the VDD pin. REG5V is used for external connection of a decoupling
capacitor.
P
HV
HV
Output stage B high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
GND
Output stage B high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
48
49
50
51
52
OUTB
HSBSB
HSBSA
OUTA
O
HV
HV
HV
HV
HV
PWM power amplifier output, channel B.
I
I
High-side boot strap input, output channel B. Capacitor couples to OUTB amplifier output.
High-side boot strap input, output channel A. Capacitor couples to OUTA amplifier output.
PWM power amplifier output, channel A.
O
HGNDA
GND
Output stage A high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
53
54
HVDDA
nPDN
P
I
HV
Output stage A high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
3.3
Power-down and mute input. Active low. When this input is low, all 4 outputs become
inactive and their output stages float, and their output is muted. Internal logic and other
references remain active during this power-down state.
55
56
57
LINER
LINEL
O
O
I
3.3
3.3
3.3
“Right” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
“Left” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
OCFG1
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
58
OCFG0
I
3.3
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
59 PWMGND
60 PWMVDD
P
P
3.3
3.3
PWM output pin ground. Internally connected to RGND.
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally
connected to RVDD.
61
PLLGND
P
1.8
PLL Analog ground. Should be tied to low voltage ground (CGND, RGND) through single
point connection to isolate ground noise on board and minimizing affecting of PLL.
62
63
XTALI
P
P
1.8
1.8
Crystal oscillator analog input port.
XTALO
Crystal oscillator analog output port. (This output drives the crystal and XTALO does not
have a drive strength specification.)
64
PLLVDD
P
1.8
PLL Analog power, 1.8V.
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D2-45057, D2-45157
Pin Description(Continued)
PIN
NAME
PIN (Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
65
VOL0/
nSS
I/O
3.3
Volume control pulse input and SPI slave select. At de-assertion of device reset, pin operates
as SPI slave select input. Then upon internal D2-45057, D2-45157 firmware execution, pin
becomes input for monitoring up/down phase pulses from volume control. (1 of 2 volume
input pins.)
66
67
CGND
CVDD
P
P
1.8
1.8
3.3
Core ground
Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.
68 nRSTOUT
O
Active low open drain output, with 16mA drive strength. Pin drives low from RVDD 3.3V
brownout detector, PWMVDD 3.3V brownout detector, or 1.8V brownout detector going
active. This output should be used to initiate a system reset to the nRESET pin upon
brownout event detection.
NOTES:
13. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix, such as nRESET.
14. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be
tied together, CGND pins to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) Also, CGND
and RGND are to be tied together on board, and RGND and PWMGND pins are internally connected and are to be tied together
on the board.
15. Thermal pad is internally connected to all 4 HGND ground pins (HGNDA, HGNDB, HGNDC, HGNDD). Any connection to the
thermal pad must be made to the common ground for these 4 ground pins.
FN6785.0
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13
D2-45057, D2-45157
Typical Performance Characteristics
Test Considerations
• Typical performance measurements are made using an Audio Precision™ 2700 Series audio analyzer.
• Precision power resistors are used for the 8Ω loudspeaker loads
• Measurements are done using a +HV supply of +24.0VDC.
Full-Bridge Typical Performance Curves
10.00
5.00
1.000
0.500
P = 25W
HVDD = 24.0V,
8Ω LOAD, 1kHz
P = 14W
2.00
1.00
0.50
0.200
0.100
0.050
P = 7W
0.20
0.020
0.010
0.005
P = 1W
0.10
0.05
HVDD = 24.0V, 8Ω LOAD,
0.02
0.01
0.002
0.001
AT 1W, 7W, 14W, 25W POWER OUT
50 100 200 500 1k 2k
FREQUENCY (Hz)
20
5k 10k 20k
0.06 0.1 0.2
0.5
1
2
5
10
20
50
POWER (W)
FIGURE 4. THD vs POWER, FULL-BRIDGE
FIGURE 5. THD vs FREQUENCY, FULL-BRIDGE
6
5
-50
HVDD = 24.0V,
8Ω LOAD, 3.5W
HVDD = 24.0V, 8Ω LOAD,
AT 1kHz, REFERENCE TO 30W
-55
-60
4
-65
3
-70
2
-75
1
-80
-0
-1
-2
-3
-4
-85
-90
-95
-100
-105
-110
< -115dB, UN-WEIGHTED
-5
-6
-115
-120
30 50 100 200
500 1k
2k
5k 10k
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0
dBFS
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE, FULL-BRIDGE
FIGURE 7. NOISE FLOOR, FULL-BRIDGE
FN6785.0
July 29, 2010
14
D2-45057, D2-45157
Half-Bridge Typical Performance Curves
1.000
0.500
10.00
5.00
HVDD = 24.0V,
8Ω LOAD, 1kHz
0.200
0.100
0.050
2.00
1.00
0.50
0.020
0.010
0.005
0.20
0.10
0.05
HVDD = 24.0V, 8Ω LOAD,
2.4W POWER OUT
0.002
0.001
0.02
20
50
100 200
500
1k
2k
5k
10k 20k
0.06
0.1
0.2
0.5
1
2
5
10
20
FREQUENCY (Hz)
POWER (W)
FIGURE 8. THD vs POWER, HALF-BRIDGE
FIGURE 9. THD vs FREQUENCY, HALF-BRIDGE
12
10
8
-30
HVDD = 24.0V,
8Ω LOAD, 1W
-35
-40
NOISE FLOOR @ 1kHz, +24V RAIL,
SPDIF INPUT, 8Ω LOAD, UNITY DSP GAIN
-45
-50
6
-55
DC RESPONSE WITHOUT
DC BLOCKING CAPACITOR
-60
4
-65
2
-70
-75
-0
-2
-4
-6
-8
-10
-12
-80
-85
-90
< -110dB, UN-WEIGHTED
-95
-100
-105
-110
-115
-120
-125
AC RESPONSE DUE TO LOUDSPEAKER
DC BLOCKING CAPACITOR
20
50 100 200
500 1k
FREQUENCY (Hz)
2k
5k 10k 20k
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0
dBFS
FIGURE 10. FREQUENCY RESPONSE, HALF-BRIDGE
FIGURE 11. NOISE FLOOR, HALF-BRIDGE
FN6785.0
July 29, 2010
15
HSBSA (50)
HVDDA (53)
SCLK (5)
SDIN (6)
D2-45057, D2-45157
DAE-4P™
OUTPUT STAGE A
INPUT SELECTION
TONE CONTROLS
5-BAND EQS
SERIAL AUDIO
INTERFACE PORT
(I2S DATA TYPE
RECEIVER)
LRCK (7)
MCLK (8)
OUTA (51)
HGNDA (52)
SAMPLE RATE
CONVERTERS
SPDIFRX (17)
SPDIFTX (18)
S/PDIF
DIGITAL AUDIO
RECEIVER,
nERROR0 (29)
HSBSB (49)
5 CHANNEL PULSE WIDTH
MODULATOR ENGINE
MIXERS
SPEAKER EQS
TRANSMITTER
OUTPUT STAGE B
HVDDB (46)
LINEAR INTERPOLATOR
PWM CORRECTION
NOISE SHAPER
COMPRESSOR/LIMITERS
ROUTERS
nRESET (1)
nRSTOUT (68)
TEST (19)
OUTB (48)
CONTROL,
INITIALIZATION
HIGH/LOW-PASS CROSS-
OVERS
HGNDB (47)
nERROR1 (30)
HSBSC (37)
HVDDC (40)
ENHANCEMENT
AUDIO PROCESSING ALGORITHMS
(PART-NUMBER DEPENDENT)
IRQA (20)
OUTPUT STAGE C
3-BAND EQS
VOLUME CONTROLS
LOUDNESS
IRQB (21)
D2AUDIO SOUNDSUITE™
SRS WOW/HD®
SDA (3)
SCL (4)
2-WIRE
QUANTIZER
(I2C-COMPATIBLE)
OUTC (38)
HGNDC (39)
nERROR2 (31)
HSBSD (36)
HVDDD (33)
TEMPREF/SCK (13)
TEMP1/MOSI (16)
VOL1/MISO (15)
VOL0/nSS (65)
PWM OUTPUT DRIVE
24-BIT FIXED-POINT DIGITAL SIGNAL
PROCESSOR
SPI INTERFACE,
SYSTEM I/O
OUTPUT STAGE D
WITH 56-BIT MAC
(SIGNAL PROCESSING AND
CONFIGURATION BLOCKS DEFINED BY
DEVICE
COMPRESSOR/LIMITERS
CHANNEL ATTENUATORS
ROM FIRMWARE)
OUTD (35)
PSSYNC/CFG1 (25)
nERROR/CFG0 (24)
FIRMWARE
(ROM)
CONFIGURATION,
SYSTEM I/O
HGNDD (34)
nERROR3 (32)
PROTECT0 (26)
PROTECT1 (27)
PROTECT2 (28)
LINEL (56)
LINER (55)
SUBOUT (41)
PROTECTION
INPUTS
TIMERS,
I/O
LINE PWM OUTPUTS
PLL
POWER SUPPLY
AMPLIFIER CONFIGURATION & CONTROL
2
2
2
2
FIGURE 12. D2-45057, D2-45157 FUNCTIONAL BLOCK DIAGRAM
D2-45057, D2-45157
The audio path includes a stereo Sample Rate Converter
(SRC), five independent audio processing channels, plus
device-specific audio enhancement algorithms.
Functional Description
Overview
The D2-45057, D2-45157 device, shown in Figure 12, is
an integrated System-on-Chip (SoC) audio processor and
Class D digital audio amplifier. It includes digital audio
input selection, signal routing, complete audio
Programmable parameter settings for audio processing
include volume control, path routing and mixing,
high/low pass filtering, multi-band equalizers,
compressors, and loudness. These parameters can be
adjusted using the D2Audio™ Audio Canvas™ software,
or can be set by a system/amplifier microcontroller
through the D2-45057, D2-45157 device’s control
interface.
processing, PWM controllers, amplifier and protection
2
control, and integrated power stages. Stereo I S and
2
S/PDIF Digital input support, plus I C and 2-wire SPI
control interfaces provide integration compatibility with
existing system architectures and solutions.
Audio Enhancement Features
The four configurable power stages can operate as four
separate Half-Bridge outputs, as two Full-Bridge outputs,
or in combinations of Half-Bridge plus Full-Bridge
outputs. Separate PWM outputs provide additional
combinations to drive headphone, or line-level stereo
and subwoofer outputs. These application-dependent
configurations provide for driving Stereo (2.0) Speaker,
2.1 Speaker, and Stereo (2.2) Bi-Amp Speaker solutions,
as well as providing Stereo Line outputs, Headphone
outputs, or Subwoofer line outputs.
The D2-45057, D2-45157 devices include the D2Audio
SoundSuite™ or SRS WOW/HD™ audio enhancement
algorithms. These device-specific functions are
integrated within the firmware as part of the standard
audio processing signal flow, and are supported per
device as:
• D2Audio SoundSuite™ (WideSound™, DeepBass™,
Audio Align™, and ClearVoice™) Audio Processing
- Included in the D2-45057 device
Audio output implementations are defined by
configuration mode select pins, providing four
combinations of powered and line amplifier outputs as
shown in Table 1. The five independent audio processing
paths feed a PWM engine, where its five PWM channels
are mapped to the configuration-selected power stages
and line outputs.
• SRS WOW/HD™
- Included in the D2-45157 device
Each of these enhancements utilizes its own algorithms,
where choice of enhancement is specified by device part
number. The D2-45057 includes only D2Audio
SoundSuite™ support, and the D2-45157 includes only
SRS WOW/HD™ support. These enhancements also
have their own unique set of programmable parameters
to control operation.
TABLE 1. OUTPUT CONFIGURATION MODES
CONFIG
MODE
NAME
FUNCTION
Serial Audio Digital Input
0
2.0 L/R • Powered Left and Right Outputs
4-Quadrant
The D2-45057, D2-45157 devices include one Serial
Audio Interface (SAI) port accommodating two digital
audio input channels. This SAI port operates in slave
With 4-Quadrant, Full Bridge Drivers.
• No Line-Level Outputs
2
mode only, supports the I S digital audio industry
1
2
2.0 L/R • Powered Left and Right Outputs
standard, and can carry up to 24-bit Linear PCM audio
words.
+
With 2-Quadrant, Full Bridge Drivers.
L/R/Sub
Line
• Stereo Left + Right Line-Level
Outputs.
The digital audio input from the SAI input port routes
directly through the Sample Rate Converters (SRC).
• Subwoofer Line-Level Output
2
Either the I S digital input, or the S/PDIF Digital input
2.1
L/R/Sub
+
• Two Half Bridge Drivers for Powered
Left and Right Outputs.
may be selected as the audio path source.
S/PDIF Digital Audio I/O
• 2-Quadrant, Full Bridge Driver for
Powered Subwoofer Output.
L/R Line
The D2-45057, D2-45157 contains one IEC60958
compliant S/PDIF Digital receiver input and one
IEC60958 compatible S/PDIF Digital transmitter.
• Two (Stereo Left + Right)
Line-Level Outputs.
The S/PDIF Digital receiver input includes an input
transition detector, digital PLL clock recovery, and a
decoder to separate the audio data. The receiver meets
the jitter tolerance specified in IEC60958-4.
• Crossover Filtering Included Within
Audio Path Signal Flow.
3
2.2
Bi-Amp
• Four Half Bridge Drivers for Powered
Bi-Amp Left + Right Outputs.
The S/PDIF Digital transmitter complies with the
consumer applications defined in IEC60958-3. The
transmitter supports 24-bit audio data, but does not
support user data and channel status.
• Crossover Filtering Included Within
Audio Path Signal Flow.
FN6785.0
July 29, 2010
17
D2-45057, D2-45157
Compressed digital formats are not decoded within the
Timers
D2-45057, D2-45157 devices. But a bit-exact
pass-through mode is supported from the SPDIFRX input
to the SPDIFTX output, allowing for designs that require
IEC61937-compliant original compressed audio input
bitstream be made available at the product’s S/PDIF
Digital output.
There are two independent timers used for device and
system control. One timer is used for internal references
for chip-specific operations. The other is used for the
system/board temperature sensing control algorithm.
There are two I/O pins (TIO0 and TIO1) associated with
the timers. Their pin functions are defined by the device
firmware. Only TIO0 is actually used in relationship to its
timer, Timer 0, and operates the timing-related I/O
functions of the temperature monitoring algorithm.
Timer 1 is used for internal functions of the device. Its
pin (TIO1) is not used for this timing operation and is
defined by device firmware as the nMUTE input pin.
Sample Rate Converter
The D2-45057, D2-45157 devices contain a 2-channel
asynchronous sample rate converter (SRC) within the
audio input signal flow path. This SRC is used to convert
audio data input sampled at one input sample rate, to a
fixed 48kHz output sample rate, aligning asynchronous
input audio streams to a single rate for system
processing.
Audio Outputs
Audio outputs are provided through four output power
stages, configurable for driving loudspeakers. Three
additional PWM outputs are also available for driving
line-level audio outputs. Combinations of outputs and
their audio processing channel assignment is defined by
the device’s configuration mode settings.
Audio data presented to the SRC can be from either the
SAI or S/PDIF Digital input sources, with an input sample
rate from 16kHz to 192kHz. In addition to converting the
input sample rate to the output sample rate, input clock
jitter and sampling jitter is attenuated by the SRC,
further enhancing audio quality.
Output Power Stages
DSP
The devices include four independent output stages
(Figure 13) that are each implemented using a high-side
(to positive HVDD supply) and a low-side (to HV supply
ground) FET pair. Drivers and overcurrent monitoring are
included in each of these four output stages. Depending
on the selected configuration mode, these four stages
can be used independently as single half-bridge outputs,
or as pairs for full-bridge outputs.
A 24-bit fixed-point Digital Signal Processor (DSP)
controls the majority of audio processing and system
control functions within the D2-45057, D2-45157
devices.
Audio path signal routing, programmable-parameter
processing blocks, and control logic are defined within
the device’s internal firmware. Signal flows through the
device are buffered and processed through hardware
specific-function blocks, such as the Sample Rate
Converter. Internal device registers allow full integration
of DSP control with the internal ROM-based firmware, as
well as providing for external control of audio processing
parameters.
Audio processing PWM channel outputs are routed to the
inputs of the four output stages based on the OCFG0 and
OCFG1, and nERROR/CFG0 and PSSYNC/CFG1
configuration settings. Each output stage includes its own
high-side and low-side current sensing that feeds to
internal monitor logic as well as providing its nERROR
output connection. Temperature and undervoltage
monitoring also provides status and input to device
protection control.
Clock and PLL
Clock is generated on-chip, using a fundamental-mode
crystal connected across the XTALI and XTALO pins.
XTALO is an output, but is designed only to drive the
crystal, and not connect to any other circuit. XTALI is an
input, connecting to the other side of the crystal.
HSBSA
(+)
HVDD
HIGH
SIDE
FET
HIGH-SIDE
PWM DRIVE
The clock generation contains a low jitter PLL to ensure
low noise PWM output, and a precise master clock source
for sample rate conversion and the audio processing data
paths. The internal PLL’s VCO clock operates at 12x the
crystal frequency (12 x 24.576MHz) and provides
complete device and system timing reference. It is used
throughout the device, including clock generators for
brown-out detection, system and power-on reset, DSP,
S/PDIF Digital transmitter, and PWM engine timing.
OUT
LOW
SIDE
FET
LOW SIDE
PWM DRIVE
(GND)
HGND
nERROR
OVERCURRENT
Clock and PLL hardware functions are controlled by
internal device firmware. They are not programmable
and are optimized for device and system operation.
FIGURE 13. OUTPUT STAGE
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D2-45057, D2-45157
Output Options
Reading and Writing Control Registers
The D2-45057, D2-45157 devices provide four
configuration options for the power stage outputs. The
power stage configuration is selected by strapping the
OCFG0 and OCFG1 pins high or low. These defined
configurations include:
All reads or writes to registers (shown in Figures 14 and
15) begin with a Start Condition, followed by the Device
Address byte, three Register Address bytes, three Data
bytes and a Stop Condition.
2
Register writes through the I C interface are initiated by
• 2 Channels of Full Bridge, 4-Quadrant Outputs,
• 2 Channels of Full Bridge, 2-Quadrant Outputs
• 4 Channels of Half-Bridge Outputs
setting the read/write bit that is within the device
address byte. Write sequence shown in Figure 14 is
described in Table 2.
2
• 2 Channels Half-Bridge, Plus 1 Channel Full Bridge
TABLE 2. I C WRITE SEQUENCE
BYTE
NAME
DESCRIPTION
Audio processing routing and control supporting the
output stage configurations is defined by the logical high
or low strapping of the nERROR/CFG0 and PSSYNC/CFG1
pins. Audio path definition, audio path output routing,
and output stage configurations are automatically set to
one of the four available modes, based on these
configuration settings.
0
Device Address
Device Address, With R/W
bit set
1
2
3
4
5
6
Register Address [23:16] Upper 8 bits of address
Register Address [15:8]
Register Address [7:0]
Data[23:16]
Middle 8 bits of address
Lower 8 bits of address
Upper 8 bits of write data
Middle 8 bits of write data
Lower 8 bits of write data
PWM Audio Outputs
Three PWM outputs provide audio for up to three
line-level outputs. Audio processing channel assignment
is mapped to these PWM outputs, based on the device’s
available configuration settings.
Data[15:8]
Data[7:0]
All reads to registers, shown in Figure 15, require two
steps. First, the master must send a dummy write which
consist of sending a Start, followed by the device address
with the write bit set, and three register address bytes.
Then, the master must send a repeated Start, following
with the device address with the read/write bit set to
read, and then read the next three data bytes. The
master must Acknowledge (ACK) the first two read bytes
and send a Not Acknowledge (NACK) on the third byte
received and a Stop condition to complete the
Using only a simple passive filter, the PWM outputs will
drive line-level outputs at a nominal 1V
addition of active filter configurations, these can also
. With
RMS
drive headphone outputs, or 2V or higher line
rms
outputs. (Alternately, these PWM outputs could also be
used to drive powered outputs, using additional power
stages on the system design.)
Control and Operation
Control Register Summary
transaction. The device's control interface acknowledges
each byte by pulling SDA low on the bit immediately
following each write byte. The read sequence shown in
Figure 15 is described in Table 3.
The control interface provides access to the registers
used for audio processing blocks and signal flow
2
parameters. Audio input selection (I S input or S/PDIF
receiver input) and all programmable data elements used
in the audio processing paths are controlled through
these register parameters, and each parameter is
defined with its specific register address. Programming
details, register identification, and parameter calculations
are provided in the DAE-4/DAE-4P Register API
Specification document.
2
TABLE 3. I C READ SEQUENCE
BYTE
NAME
DESCRIPTION
0
Device Address
Device Address, With Write
bit set
1
2
3
4
Register Address [23:16] Upper 8 bits of address
2
Register Address [15:8]
Register Address [7:0]
Device Address
Middle 8 bits of address
Lower 8 bits of address
I C 2-Wire Control Interface
The D2-45057, D2-45157 device includes a 2-Wire I C
2
compatible interface for communicating with an external
controller. This interface is usable through either an
external microcontroller bus, or for communication to
EEPROMs, or other compatible peripheral chips.
Device Address, With Read
bit set
5
6
7
Data[23:16]
Data[15:8]
Data[7:0]
Upper 8 bits of write data
Middle 8 bits of write data
Lower 8 bits of write data
2
The I C interface supports normal and fast mode
operation and is multi-master capable. In a D2-45057,
2
D2-45157 system application, it operates as an I C slave
device, where the system controller operates as the
2
I C master.
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D2-45057, D2-45157
ACK
ACK
ACK
DEVICE-ADDR
REGISTER [23:16]
REGISTER [15:8]
REGISTER [7:0]
START
R/W
ACK
ACK
ACK
ACK
Write Sequence
REGISTER [7:0]
DATA [23:16]
DATA [15:8]
DATA [7:0]
STOP
2
FIGURE 14. I C WRITE SEQUENCE OPERATION
Step 1
ACK
ACK
ACK
ACK
DEVICE-ADDR
REGISTER [23:16]
REGISTER [15:8]
REGISTER [7:0]
REPEAT
START
START
R/W
MASTER
ACK
MASTER
ACK
ACK
ACK
NACK
Read Sequence
DEVICE-ADDR
DATA [23:16]
DATA [15:8]
DATA [7:0]
REPEAT
START
R/W
STOP
Step 2
2
FIGURE 15. I C READ SEQUENCE OPERATION
(TEMPREF/SCK, TEMP1/MOSI, VOL1/MISO,
VOL0/nSS) function as an SPI input port for external
boot loading operation.
Control Interface Address Spaces
2
Registers are accessed through the I C control interface,
2
using the I C channel address of 0xB2. This establishes
2
the device or product under control through I C
communication as the D2-45057, D2-45157.
• As soon as the boot-up process is completed and the
device begins executing its firmware program, these
pins are no longer used for SPI functions, and are
reassigned by the firmware for use as
Registers and memory spaces are defined within the
D2-45057, D2-45157 for specific internal operation and
control. The highest-order byte of the register address
(bits 23:16) determines the internal address space used
for control read or write access, and the remaining 16
bits (bits 15:0) describe the actual address within that
space.
dedicated-function I/O for amplifier operation.
Refer to multiple-purpose pins descriptions in Table 5 for
more description of these pin functions.
Reset and Device Initialization
The D2-45057, D2-45157 devices must be reset to
initialize and begin proper operation. A system reset is
initiated by applying a low level to the nRESET input
pin. External hardware circuitry or a controller within
the amplifier system design must provide this reset
signal and connect to the nRESET input to initiate the
reset process. Device initialization then begins after the
nRESET pin is released from its low-active state.
Programmable settings for the audio processing blocks
are internally mapped to the address space defined with
the highest order bits all zero. (For example, 0x00nnnn,
where nnnn is the address location within this address
space.)
Storing Parameters to EEPROM
The D2-45057, D2-45157 device has the ability to store
parameters data to an EEPROM. If an EEPROM is installed
in the application, the programmable parameter data can
be saved in this EEPROM. This stored data can then be
recalled upon reset or power-up.
The chip contains power rail sensors and brownout
detectors on the 3.3V RVDD and PWMVDD power
supplies, and the 1.8V CVDD power supply. A loss or
droop of power from these supplies will trigger their
brownout detectors which will assert the nRSTOUT
output pin, driving it low. The nRSTOUT pin should
connect to the nRESET input through hardware on the
amplifier design, to ensure a proper reset occurs if the
power supply voltages drop below their design
specifications.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an alternate serial
input port that provides an interface for loading
parameter data from an optional EEPROM or Flash device
during boot-up operation.
The four SPI interface pins are all shared functions:
At the de-assertion of nRESET, the chip will read the
status of the boot mode selection pins (IRQA and IRQB)
and begin the boot process, determined by the boot
• Following a reset condition and while the device is
initiating the boot-up process, these four SPI pins
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D2-45057, D2-45157
mode that is defined by these pins’ logic state. These
Power Supply Requirements
device pins are strapped either high or low on the
system’s design (PCB), and it is the state of these pins
that is latched into, and defines boot mode operation.
The device requires operating power for these voltages:
• PWMVDD and RVDD:
- 3.3V DC Supply Voltage.
- RVDD operates interface and I/O logic.
Boot Modes
The D2-45057, D2-45157 devices contain embedded
firmware to operate the part and run the amplifier
system. Parameter information that is used by the
programmable settings can be written to the device after
it is operational and running. However, parameter data
can also be read at boot time, allowing saved parameter
settings to be used, or allowing amplifier function to be
set through a system microcontroller interface. The
device is designed to boot in one of four possible boot
modes, allowing control and data to be provided through
these boot sources:
- PWMVDD is the same voltage, and is used for the
PWM outputs and output stage drive.
• CVDD and PLLVDD
- 1.8V DC Supply Voltage
- CVDD operates the internal processor and DSP core.
- PLLVDD also operates at the internal processor
voltage levels, but is provided through a separate
connection to allow isolation and bypassing for
noise and performance improvements.
2
• “High Voltage” (HVDD[A:D], and VDDHV)
• I C Slave (to external Microcontroller)
- HVDDA, HVDDB, HVDDC, and HVDDD are the
“High Voltage” supplies used for operating each of
the four output power stages.
- VDDHV is used as the source for the on-chip +5V
regulator that is used for the output stage drivers.
2
• I C EEPROM
• Internal Device ROM Only
• SPI Slave
The specific boot mode is selected based on the state of
the IRQB and IRQA input pins at the time of reset
de-assertion. Boot modes and their functions are shown
in Table 4. (Note: “Boot Mode” describes the “mode” of
device initialization with respect to the source of
parameter data or start-up control settings. This is not to
be confused with “Output Mode” or audio processing
“Configuration Mode” settings that define
- Individual power (HVDD[A:D]) and their
corresponding ground (HGND[A:D]) pins are
included for each of the four power stage outputs,
providing channel isolation and low impedance
source connections to each of the outputs. All the
HVDD[A:D]/VDDHV pins connect to the same
voltage source.
High-Side Gate Drive Voltage
amplifier-specific functions.)
An on-chip bootstrap circuit provides the gate drive
voltage used by each output stage. A pin is included for
each output channel (HSBS[A:D]) for connection of a
capacitor (nominal, 0.22µF/50V) from this pin to that
channel’s PWM output.
TABLE 4. BOOT MODE SETTINGS
BOOT IRQB IRQA MASTER/
MODE PIN PIN
SLAVE
DESCRIPTION
2
2
0
0
0
I C Slave Operates as I C slave, boot
at address 0x88. An external
Drivers for high-side FETs on the output stages require a
voltage above the supply used for powering that FET. The
charge pumping action of the driving PWM to this driver
produces this “bootstrap” voltage, and uses this capacitor
to filter and hold this gate drive voltage. This enables
amplifier operation without need of connection to an
additional power supply voltage.
2
2-wire I C master provides
the boot code.
2
1
0
1
I C Master Operates as 2-wire master;
loads boot code from ROM on
2
I C port.
2
3
1
1
0
1
-
Internal ROM Boot/Operation
Power Supply Synchronization
SPI Slave SPI slave. External SPI
master provides boot code.
The the PSSYNC/CFG1 pin provides a power supply
synchronization signal for switching power supplies.
Firmware configures this pin to the frequency and duty
cycle needed by the system switching regulator. This
synchronization allows switching supplies used with the
device to operate without generating in-band audio
interference signals that could be possible if the switching
power supply is not locked to the amplifier switching.
The device initializes as defined by its boot mode. But it
gets its configuration and parameter data from the host
device. This host device can be either an external
controller, or from an EEPROM. If a system uses both an
external controller and an EEPROM, the EEPROM will load
first, and during this time, the controller must remain off
2
the I C bus until after the reading sequence from
This PSSYNC/CFG1 pin is a shared pin. (Refer to multiple-
purpose pins descriptions in Table 5 on page 24.) During
device reset and initialization, it operates as one of two
configuration input pins, where its high or low logic state
is used to set the amplifier configuration mode. After
EEPROM has completed.
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D2-45057, D2-45157
completion of reset and when the device firmware begins
operating, this pin becomes the PSSYNC output.
nPDN Input Pin
The nPDN pin is a control input that is used to
power-down the outputs. When this input is pulled low,
all audio outputs turn off and become inactive, internal
PWM drive to output stages is turned off, and all output
stages float. Internal logic and other references remain
active during this power-down state. Asserting nPDN also
causes all four nERROR[0:3] outputs to pull (active) low.
Power Sequence Requirements
Voltage sensors and brownout detectors monitor supply
voltages to the device. The logic and built-in protection of
this voltage monitoring prevents operation until all
supply voltages are within their specified limits. However,
during application of power, the CVDD and RVDD
(including PWMVDD) voltages should be brought up
together to avoid high current transients that could fold
back a power supply regulator.
Each of the four output stages incorporate their own
latching overcurrent hardware shutdown logic, in
addition to the separate protection events that occur
through firmware control from an overcurrent condition.
Firmware protection control will perform other steps to
clear this hardware latched shutdown, although asserting
nPDN will also reset the hardware-latched state.
During application of power to the system and while the
CVDD voltage (nominal +1.8V) is below its minimum
specified limit, the RVDD and PWMVDD supplies (nominal
+3.3V) must not exceed the voltage that is present at
CVDD. (i.e., if V
< minimum-specified, then
.) After CVDD has
The nPDN pin is active low, and inactive when at logic
high level. In normal operation, it is held high with
pull-up to the RVDD supply.
CVDD
V
must be < V
CVDD
RVDD/PWMVDD
reached its minimum limit, RVDD/PWMVDD can then
continue to increase to its normal design (3.3V) value.
(PLLVDD may be brought up separately.)
nERROR[0-3] Output Pins
Each of the four output stages includes a two-level
overload and overcurrent monitor. An overcurrent or
overload condition asserts the nERROR output for that
channel.
Best practice would be for all supplies to feed from
regulators using a common power source. Typically this
can be achieved by using a single low-voltage supply
power source and regulating the 3.3V and 1.8V supplies
from that source. Also, as noted in the pin specifications
of this document, all voltages of the same names must
be tied together at the board level.
Also, an undervoltage condition for the voltages used by
the output stages (HVDD[A:D]/VDDHV, REG5V,
PWMVDD), or assertion of nPDN, will cause all four
nERROR outputs to assert.
REG5V
The nERROR pins are open drain, active-low, and can be
wire-or connected together. Depending on the output
mode configuration where more than one output stage
may be used for an audio channel, nERROR pins
associated with that audio channel are connected
together to provide monitoring status.
The output stage internal drivers require their own
+5VDC supply voltage. An on-chip regulator operates
from the VDDHV voltage to produce this +5V voltage.
The REG5V pin is used for external capacitor connection
to filter this regulated voltage. A 1.0µF and 0.1µF
capacitor should be connected to this pin, and the
connection should be made as close as practical to the
pin. This internal +5V is used only by the output stage
drivers. No other connection is to be made to this pin.
In applications where multiple power stage outputs are
defined for an audio channel, the nERROR pins for these
power stages would be tied together, and also tied to the
PROTECT input pin associated with that audio channel.
Refer to Table 6 on page 25, that shows these
Pin and Control Block Functions
I/O Control Pins
connections for the different configuration modes.
IREF Pin
Several device pins are used as specific-function inputs
and outputs to control amplifier and device operation.
These pins are implemented within the device hardware
as general purpose inputs/outputs. However, their
operation is not programmable, and their specific
function is totally defined by the D2-45057, D2-45157
internal firmware. Functions of these pins are defined in
the pin definition list, and additional detail is included
within the descriptions of the functional blocks where
these pins are used.
The IREF pin is used to set the overcurrent and overload
monitoring threshold. The design requires a 100kΩ
resistor to connect from this pin to ground.
Configuration Assignment Pin Differences
There are two pairs of pins used for configuration
assignments. Both pin pairs are used for the assignment,
and their settings must both match their requirements
for the configuration mode. These pin pairs are:
• OCFG0, OCFG1: define the output stage topology
and operation of the output configuration.
Some pins are multiple-purpose, where their functions
are defined accordingly by the operational state (e.g.,
reset, initializing, booting, running) of the D2-45057,
D2-45157 device. These multiple-purpose pins and their
descriptions and uses are described in more detail in
Table 5 on page 24.
• nERROR/CFG0, PSSYNC/CFG1: define the audio
processing and amplifier control supporting the
output configuration.
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D2-45057, D2-45157
OCFG0, OCFG1 Input Pins
Temperature Monitoring
These two pins define the configuration of the four output
stages. They are logic level input pins, and are connected
to logic high (PWMVDD) or logic ground (PWMGND) to
establish which of the four output configurations is used
in the design. Refer to “Pin Description” starting on
page 10 for additional reference and definition.
The TEMPREF/SCK, TEMP1/MOSI, and TEMPCOM/TIO0
pins are used in a firmware-controlled algorithm to
monitor temperature. These pins share other functions
(refer to multiple-purpose pins descriptions in Table 5 on
page 24) and during firmware execution, operate as
inputs and outputs for this measurement algorithm.
Figure 16 shows the circuit for this temperature
measurement implementation.
nERROR/CFG0 and PSSYNC/CFG1 Pins
These pins define the amplifier configuration mode that
the firmware uses in operating the amplifier. In addition
to the OCFG0 and OCFG1 pins that set operation of the
output stages, these nERROR/CFG0 and PSSYNC/CFG1
pins also establish audio signal processing path
assignments and set up monitoring and protection for
the configuration mode. The configuration pin logic levels
are assigned by pull-up or pull-down resistors installed
on that application.
100k
TEMP1/MOSI
49.9k
TEMPREF/SCK
10
TEMPCOM/TIO0
0.1µF
The configuration defined by these pins is assigned when
the D2-45057, D2-45157 device exits its reset state,
when at that time, the logic status of these
PSSYNC/CFG1 and nERROR/CFG0 pins are latched into
internal device registers. These are shared-function pins,
and after firmware begins executing, their functions are
reassigned as outputs. Refer to Table 5 on page 24 for
further description on these pins and their shared
functions.
FIGURE 16. TEMPERATURE MONITOR CIRCUIT
A NTC (Negative Temperature Coefficient) 100kΩ resistor
connects to the TEMP1/MOSI pin, and using the resistor’s
temperature/resistance correlation, the firmware
monitors temperature of the NTC resistor. The internal
device timing functions associated with the TIO0 pin
provide calibration that correlates to system clock. A
49.9kΩ resistor connects to the TEMPREF/SCK pin and is
used as a constant non-temperature-dependent
reference for this algorithm.
The firmware algorithm is internal to the D2-45057,
D2-45157 device. Status from this temperature monitor
is used for the temperature protection functions of the
device and its application. There are no adjustments or
parameters for changing settings.
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D2-45057, D2-45157
TABLE 5. MULTI-FUNCTION I/O CONTROL PIN ASSIGNMENT AND OPERATION
PIN STATE DURING
INITIALIZATION
PIN STATE DURING OPERATION
PIN
NAME
I/O
FUNCTION
I/O FUNCTION
CONNECTION REFERENCE
TEMPREF/ Output SPI Cock Output.
SCK
Input Temperature Monitor
Reference. Used for
Temperature Monitoring
Algorithm.
Typical connection is to 49.9kΩ
resistor as temperature monitor
reference. Available for SPI connect
if SPI is used in application.
VOL1/
MISO
Input SPI Master Input or Slave
or Output. Function (Master or
Output Slave) determined by nSS
input state.
Input Volume Control Phase-B
input. Used for Monitoring
Rotary-Encoder Volume
Control.
Typical connection to +3.3V with
10kΩ pull-up resistors, and to 2-bit
volume control encoder.
TEMP1/ Output SPI Master Output or Slave
MOSI or Input. Function (Master or
I/O
Temperature monitor
reference I/O pin. Used for
Temperature Monitoring
Algorithm.
Typical connection is to 100kΩ NTC
resistor as temperature monitor
reference. Available for SPI connect
if SPI is used in application.
Input Slave) determined by nSS
input state.
nERROR/ Input (CFG0) Configuration Mode
Output Active-Low Output Amplifier Connects to +3.3V or to ground with
CFG0
Input Select. Uses pull-up or
pull-down to set logic input
level, to define one of 4
amplifier configurations.
Protection and Monitoring
Status Indication.
10 kΩ resistor, to select logic high or
low for setting configuration. Also
connects to input of monitor or
indicator circuit to provide status.
(Referenced as “PSTEMP” on some
reference designs.)
PSSYNC/
CFG1
Input (CFG1) Configuration Mode
Input Select. Uses pull-up or
pull-down to set logic input
level, to define one of 4
Output Sync Output for
Connects to +3.3V or to ground with
10kΩ resistor, to select logic high or
low for setting configuration. Also
connects to clock sync input of
on-board switching regulator.
(Referenced as “PSCURR” on some
reference designs.)
Synchronizing On-Board
Power Supply regulator.
amplifier configurations.
VOL0/
nSS
Input SPI Slave Select.
Input Volume Control Phase-A
input. Used for monitoring
rotary-encoder volume
control.
Typical connection to +3.3V with
10kΩ pull-up resistors, and to 2-bit
volume control encoder.
These four pins are connected to either a high (+3.3V)
level or low (ground = 0) level. Connection should be
through a 10kΩ resistor, and not directly to supply or
ground.
Configuration Setting
The configuration mode is assigned through two pairs of
pin settings. When the D2-45057, D2-45157 device exits
its reset state, the logic status of the PSSYNC/CFG1 and
nERROR/CFG0 pins is latched into internal device
registers. During this initialization time, these pins
operate as logic inputs. After completion of the
initialization and the internal firmware begins executing,
these pins are re-assigned as outputs for their shared
functions, and the internal latched logic state that defines
the configuration mode remains until the device is
powered down or reset again. The OCFG0 and OCFG1 pin
status is not latched; those pins are to remain in their
pull-up or pull-down state.
Table 6 shows the audio processing channel
assignment, audio content, and output assignments for
each of the four configuration modes.
• Both pairs of configuration setting pins (OCFG0,
OCFG1) and (PSSYNC/CFG1, nERROR/CFG0) must be
used and both must be set to the same configuration
mode.
In modes 2 and 3, the filtering for high and low pass
crossovers is applied to the audio signal flow path,
enabling the appropriate high or low pass content to be
properly filtered for the PWM output channels.
Selection of one of the four configuration modes is
defined by strapping the configuration pins high or low:
• OCFG0 and OCFG1, to define the output power stage
configuration;
• and nERROR/CFG0 and PSSYNC/CFG1 pins to define
the amplifier and channel configuration
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D2-45057, D2-45157
TABLE 6. CONFIGURATION MODE AND CHANNEL ASSIGNMENTS
OUTPUT
CFG PINS MODE PINS
CONFIG
POWER STAGE
OUTPUTS
PWM LINE
OUTPUTS
nERROR[0:3] to
PROTECT[0:2]
“00” 2-Channel
4-Quad
0
0
1
0
1
0
0
0
1
0
1
0
1
2
L
Left
nERROR0
+nERROR1
to PROT0
SPKR Full Bridge
Full Bridge
(3-Level)
R
SPKR
Right
Full Bridge
nERROR2
+nERROR3
to PROT1
3
4
5
1
PROTECT2 Unused
(tie high)
“01” 2-Channel
L
Left
nERROR0
+nERROR1
to PROT0
2-Quad
Full Bridge
+
L Line
+
R Line
+
Sub Line
SPKR Full Bridge
2
R
SPKR
Right
Full Bridge
nERROR2
+nERROR3
to PROT1
3
4
5
1
L Line
R Line
Sub
PROTECT2 Unused
(tie high)
Left
Right
Sub
“10” 2-Channel
Half Bridge
+
L
Left
SPKR HB
1-Channel
Full Bridge
for Sub,+
L Line,
2
R
SPKR
Right
HB
-
+
R Line
3
4
5
L Line
R Line
Sub
Left
Right
Ch 5 Sub
Full Bridge
nERROR2
+nERROR3
to PROT2
“11” 4-Channel
Half Bridge
2.2
1
1
1
1
1
L
HF
Left
HF
SPKR (HB)
Bi-Amp
2
3
4
5
L
LF
SPKR
Left
LF
(HB)
R
HF
SPKR
Right
HF
(HB)
R
LF
SPKR
Right
LF
(HB)
NOTE: LF = Low Frequency, HF = High Frequency for Bi-Amp Config; HB = Half-Bridge
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D2-45057, D2-45157
Short-Circuit and Overcurrent Sensing
Protection
Each PWM output FET includes a dual-threshold
overcurrent sensor. Multiple functions occur depending
on detection of overcurrent conditions:
The D2-45057, D2-45157 device includes multiple
protection mechanisms. Output overload and overcurrent
status for each output power stage provides two levels of
monitoring. Temperature monitoring provides two levels
of temperature status. On-chip undervoltage detection is
included for all supply voltages.
• The lower threshold is used to monitor fault
conditions such as shorts or overloads on the
loudspeaker outputs.
Several strategies are provided in the D2-45057,
D2-45157 to prevent damage from the high voltages,
currents, and temperatures present in class-D amplifiers.
This protection is also effective against user-induced
faults such as clipping, output overload, or output shorts,
including both shorted outputs or short-to-ground faults.
Protection includes events such as:
• The higher threshold monitors fault conditions of the
PWM output pin.
• The nERROR output asserts for the channel detecting
the fault.
• For the lower level threshold, nERROR remains
asserted only through the duration of the
overcurrent event.
• Output Overcurrent
• For the higher level threshold, the output is shut
down, and its nERROR output is asserted, and these
remain latched until the controller acknowledges the
fault event by turning off the channel’s PWM drive.
(When shutdown, the PWM output pin floats.)
• Output Short Circuit
• Over-Temperature
• Power Supply Brown-Out
• Shoot-Through Overcurrent
Certain levels of protection are managed using on-chip
hardware. Other protection is integrated into device
firmware, and involves actions to:
Hysteresis is built into the overcurrent detectors to
suppress PWM switching transient events.
Protection Monitoring and Control
• Shut down the outputs for a short circuit,
over-temperature, or undervoltage event.
These overcurrent detectors generate either a pulse or
latched logic level (depending on low or high threshold)
upon detection of high current. Detector status is
presented to the nERROR[0:3] pins.
• Shut down the device if power supply sensors detect
voltages dropping below their design thresholds.
• Providing both indication, and device shutdown if
needed for overload and overcurrent monitors
detection. Dual threshold monitors provide two
levels of high current conditions.
The PROTECT[0:2] pins are used as protection inputs to
the firmware. Firmware action based on these pins’
status depends on the selected output mode
configuration. The nERROR[0:3] output pins and the
PROTECT[0:2] input pins are connected together based
on the particular system and output mode configuration,
as shown in Table 6 on page 25.
• Chip temperature monitoring provides dual threshold
status of high temperature conditions, providing
both indication, and device shutdown if needed.
Error Reporting
Thermal Protection and Monitors
Internal monitoring of system and device operation uses
an I/O pin (nERROR/CFG1) as an output to signal an
external system controller of a channel shutdown error
condition. This output may be used to turn on a simple
indicator.
An temperature sensing provides two thresholds of
temperature monitoring.
If the device reaches the lower threshold, a warning
indication is generated, and triggers one level of thermal
protection management.
The error output is also used to signal an external
On-chip hardware thermal protection shuts down the
device upon a high-threshold temperature condition. If
the device reaches the higher threshold, on-chip
hardware latches and shuts down all four output stages.
It also drives all four nERROR0-3 outputs low (active)
providing this shut-down status to the firmware through
their connected PROTECT0-2 inputs.
2
microcontroller that the I C bus may be busy. When the
2
error output is low during system initialization, the I C
bus is busy as a master device.
This error output is active low and only becomes used as
an error reporting output after the device firmware has
initialized and began running. This same pin is shared as
an input. (Refer to Table 5 on page 24 for further
description on shared-function pins.) During a reset
condition, this pin operates as an input, and is one of two
input pins that are used to define the configuration
mode. A resistor pull-up or pull-down on this pin
establishes this mode input configuration state. After
completion of the initialization sequence, these resistors
do not affect the error output operation.
FN6785.0
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D2-45057, D2-45157
processing blocks are shown in Figure 17. This
architecture includes audio processing functions of:
Graceful Overcurrent and Short Circuit
Hard faults from overcurrent or short circuit conditions
shut down the outputs. High-threshold over-temperature
also causes a shut down. For lower-threshold event
detections, graceful protection is provided for each
output. Specific operation depends on type and severity
of the detected event, but action taken is to reduce
conditions that would contribute to the event, without
the severity of a complete shut-down as in a high-limit
fault condition.
• Input Selection
• Mixers
• Input Compressors and Output Limiters
• Tone Controls
• 5-Band and 3-Band Parametric Equalizers
• Router
Overcurrent monitoring status is presented to the
PROTECT0-2 inputs, from per-output detector status that
drives the nERROR0-3 outputs. Overcurrent detection
algorithms in firmware monitor these peak level
• High/Low-Pass Crossover Filters
• Volume and Output Level Controls
• Loudness Contour
detections, and upon detection of an overload condition,
automatically reduce PWM gain. This Automatic Gain
Control (AGC) action aids to prevent clipping of audio
output, as well as avoiding related excessive-level
conditions. The AGC algorithm operation functions
through a stepped-changing of PWM gain reduction,
corresponding to characteristics and time-event
detection of overloads. At the lower (non shut-down)
high-temperature threshold, the AGC function also acts to
attenuate the outputs to attempt to reduce temperature.
Enhancement audio processing is also used. Depending
on which device, (D2-45057 or D2-45157) either the
D2Audio SoundSuite™ or SRS WOW/HD™ algorithms
are included.
Audio Processing Signal Flow Blocks
INPUT SELECTION
The Input Select register specifies the audio inputs that
are assigned to the audio processing input path. Either
2
the I S or S/PDIF Digital inputs are available.
Output level gain and level change effects from this AGC
function are similar to operation from a compressor.
However, unlike a compressor where characteristics are
determined by input levels, the PWM AGC operation is
controlled through detection of near-overload output
levels or from high temperature detection.
MIXERS
An input mixer provides a two-input, two-output mixing
and routing path. Either input can be mixed at adjustable
gain into either or both of the two outputs. Default
setting is 0 dB through each channel, with full cut-off for
non-through channels. Attenuation is continuously
variable with the programmable parameters.
Power Supply Voltage Monitoring
Undervoltage sensors and brownout detectors monitor all
supply voltages to the device. The logic and built-in
protection of this voltage monitoring prevents operation
until all supply voltages are within their specified limits.
Also, if any of these monitored voltages drop below their
threshold, the device shuts down its outputs and asserts
all four of the nERROR outputs.
A stereo mixer provides a path from the two input
channels. This typically is used to provide a mix of both
stereo input channels for crossover processing and
becoming the source for the subwoofer channel. Gains
for both input channels are adjustable to feed the single
stereo mixer output.
TONE CONTROLS
Audio Processing
The audio processing, signal flow, and system definition
is defined by the D2-45057, D2-45157 device internal
ROM firmware, and executed by the DSP. This firmware
defines the audio flow architecture, which includes the
audio processing blocks. Each of these blocks are
programmable, allowing for adjustment of their
A tone control block is included in both of the two input
channels. Each of the filters (bass or treble) is
implemented with a first-order (6dB/octave) roll-off,
using programmable corner frequency and a boost or
attenuating gain. The signal flow processing
automatically provides a smooth transition between tone
control changes.
audio-controlling parameters. The signal flow and audio
FN6785.0
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27
Input Select
S/PDIF
Licensed
Audio
Processing
Algorithm
S/PDIF
Digital Input
1
2
3
4
5
Compressor 1
Compressor 2
Tone 1
Tone 2
5 Band EQ 1
5 Band EQ 2
Speaker EQ 1
Speaker EQ 2
2x2
Mixer
SRC
I2S
2
4x4
Router
DIGITAL
Digital Input
*(See Note)
* NOTE: Device-dependent licensed audio processing algorithm supporting
D2Audio SoundSuite™, or SRS WOW/HD®. Refer to device ordering
information for part number specifying each algorithm.
2x1
Mixer
Crossovers
1
Output A
Output B
Output C
Output D
HP 1
LP 1
LP 2
LP 3
LP 4
LP 5
3 Band EQ 1
3 Band EQ 1
3 Band EQ 1
3 Band EQ 1
Loudness 1
Loudness 2
Loudness 3
Loudness 4
Loudness 5
Limiter 1
Limiter 2
Limiter 3
Limiter 4
Limiter 5
Volume 1
Volume 2
2
3
4
5
HP 2
HP 3
HP 4
HP 5
PWM
Channel
Driver
Master
Volume
Control
Volume 3
Mapping
Volume 4
Volume 5
Configuration Settings
Output stage channel assignment and amplifier topology is programmed with
configuration pin settings. Four output modes are available with combinations
of 4- and 2-quadrant full bridge, and half bridge operation for outputs A-D.
Line and subwoofer output channel assignment is also established by output
mode configuration settings.
Left Line Out
Right Line Out
Sub Line Out
FIGURE 17. D2-45057, D2-45157 AUDIO SIGNAL FLOW
D2-45057, D2-45157
COMPRESSORS AND LIMITERS
LOUDNESS CONTOUR
Two individual input compressors are included in the
input audio path, one for each of the two input channels.
Five output limiters are also included in the five output
path channels. The Compressor and Limiter blocks
operate identically, and their parameter settings allow
independent control of the audio signals. Typically, the
input path blocks are programmed to provide a
compression function, and the output path blocks are
programmed to limit output signal levels. But each can
be programmed as needed. Each Compressor/Limiter
has configurable Compression Ratio, Threshold, Attack
and Release Time, as well as Makeup Gain.
An individual software-controlled Loudness Contour is
included for each of the 5 amplifier output channels. The
Loudness Contour curve is customized to allow for
dynamically and automatically enhancing the frequency
response of the audio program material relative to the
Master Volume Level setting. The Loudness Contour
models the frequency response correction as defined by
the Fletcher/Munson audio response curve. It provides
for amplitude or volume changes to those signals to
which the ear does not respond equally at very low
listening levels.
SOUNDSUITE™ PROCESSING
MULTI-BAND EQUALIZERS
The D2Audio SoundSuite™ audio processing provides a
full set of enhancements to audio that greatly add to the
quality and listening experience of sound in wide scopes
of consumer devices. The D2Audio SoundSuite™
algorithms use psycho-acoustic processing that create a
rich-sounding environment from small speakers, and
synthesizes the sound and quality equivalent to more
complex systems. It is especially suited to consumer
products that include televisions, docking stations, and
mini hi-fi stereo products.
Three sets of Multi-Band Parametric Equalizers are
included in the audio signal processing path. Each band
of the equalizers provides for independent gain,
frequency, and Q-factor programming.
A 5-Band Equalizer and a Speaker Equalizers (SEQ) are
included in both of the two input channels. Four 3-Band
Equalizers are also located in the four output channels.
STEREO ROUTER
A 4x4 stereo router is used to assign any one of the 4
input channel paths to each of the 4 output paths. The
router performs path assignment only. It does not have
provision for gain or signal level adjustment.
SoundSuite Processing Includes:
®
• D2Audio WideSound™
- An advanced Two-Channel Image Field
Enhancement
HIGH/LOW-PASS CROSSOVER FILTERS
®
• D2Audio DeepBass™
High-Pass and Low-Pass filter blocks are provided for
each of the 5 output channels downstream of the Router
and Stereo Mixer. These provide a flexible Crossover
function for all the output channels, including provision
for defining the subwoofer channel’s frequency response.
- A sophisticated bass enhancement using
psycho-acoustics and Dynamic Filtering
®
• D2Audio AudioAlign™
- Sound Positioning and Alignment to the Video
Display
The High and Low Pass blocks operate together, and are
implemented as a total of 4 cascaded elements, with 2
each of the elements allocated for High Pass, and the
other 2 elements allocated for Low Pass functionality.
Complete flexibility allows each element to be optionally
defined for either High or Low Pass. Each element is
selectable for a slope of 6, 12, 18, or 24dB, or may be or
bypassed. Three filter types of Butterworth, Bessel, or
Linkwitz-Riley implementations can also be chosen.
®
• D2Audio ClearVoice™
- Enhancement of Vocal Clarity
The D2Audio SoundSuite™ algorithms are completely
included within the D2-41051 DAE-4 devices.
MASTER VOLUME CONTROL
A software-controlled Master Volume control is used to
adjust the global volume for all 5 output channels.
Master Volume operates a continuously adjustable
attenuator, from unity gain, down to -100dB and cutoff.
Each of the 5 output channels have their own dedicated
output level adjustments, providing individual channel
gain or attenuation after the output limiter stages.
Settings provide output level adjustment from +12dB to
-100dB.
FN6785.0
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29
D2-45057, D2-45157
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
7/29/10
FN6785.0
Initial Release to web
Products
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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: D2-45057, D2-45157
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FN6785.0
July 29, 2010
30
D2-45057, D2-45157
Package Outline Drawing
L68.10x10C
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 04/09
A
10.00
B
4 X 8.00
6
68
52
PIN #1
INDEX AREA
51
1
6
PIN 1
INDEX AREA
EXPOSED
PAD
7.70
10.00
64 X 0.50
(4X)
0.15
68 X 0.25
68 X 0.55 ±0.10
TOP VIEW
BOTTOM VIEW
PACKAGE OUTLINE
SEE DETAIL “X”
1.00 MAX
C
C
0.10
64 X 0.50
68 X 0.25
MIN 0.00
MAX 0.05
0.08
C
SEATING PLANE
7.70
10.00
SIDE VIEW
68 X 0.20
68 X 0.55
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.23mm and 0.28mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6785.0
July 29, 2010
31
相关型号:
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