D2-74383-LR_技术文档

DATASHEET

D2-6 Family Audio SOC

Intelligent Digital Amplifier and Sound Processor

FN7838

Rev.4.00

Mar. 19, 2019

The D2-6 family (D2-71083, D2-74083, D2-71583, D2-74583,

and D2-74383) digital audio processor devices are complete

System-on Chip (SoC) audio processor and Class-D amplifier

controllers. Integrated DSP processing and configurable audio

processing algorithms provide an extremely flexible platform

for feature rich and cost-effective quality audio solutions which

benefit from the addition of Class-D amplifiers and DSP audio

processing, meeting demands of consumer electronics

applications.

Features

• Advanced D2-6 family digital audio processor IC

- Pin compatible and function/feature compatible with the

D2 Audio DSP D2-3 family device

• Total System on Chip (SoC)

- All digital Class-D amplifier controller

- Full 5.1/7.1/9.1-channel amplifier platform support

• Enhanced audio processing decoders

The 12 integrated digital PWM controllers can be used in a

variety of multi-channel audio system configurations, supporting

powered as well as line outputs. Fully protected amplifier control

provides efficient and clean Class-D power output support.

®

- Dolby Digital/AC3

®

- Dolby Pro Logic IIx

- AAC LC™

®

The D2-6 device family supports full audio decoding for

formats including Dolby® Digital, Dolby® Pro Logic IIx, AAC

LC™, DTS® Digital Surround, and Dolby® Digital Plus. The

D2-6 family is pin-compatible and function/feature compatible

with the D2-3 family devices, enabling additional decoding

capability to existing designs, or providing cost optimization to

lower-featured systems not requiring the additional audio

processing and decode capability.

- DTS Digital Surround

®

- Dolby Digital Plus

• D2 Audio DSP sound enhancement algorithm and

virtualization

• Expanded on-chip memory capacity

• Integrated DSP processing

- 12 channels of Digital Signal Processing (DSP) including

equalizers, filters, mixers and other common audio

processing blocks

Applications

• Audio Video Receiver (AVR)

- Fully configurable and routable audio signal paths

• Multi-channel surround soundbar

• Home Theater in a Box (HTiB)

• Flexible audio input and output configurations

• Embedded 8-channel sample rate converter

- Sample rates from 32kHz up to 192kHz

• Multi-channel Multi-Media (MM) systems

• Installed steerable audio arrays

• Bluetooth/WiFi voice-enabled speaker systems

• Automotive trunk/amplified solutions

• Real-time amplifier control and monitoring

- Supports bridged, half-bridged, and Bridge-Tied Load

(BTL) topologies, using discrete or integrated power

stages from 10W to over 500W

Related Literature

For a full list of related documents, visit our website:

- Complete fault protection with automatic recovery

• D2-71083, D2-74083, D2-71583, D2-74583, D2-74383 device pages

D2-6 Digital Audio Processor

S/PDIF

Digital I/O

Interface

2x S/PDIF Digital Input

8-Channel

Sample

Rate

24-Bit Digital

Signal Processor PWM Engine

12-Channel

S/PDIF Digital Output

A/Vsync I/O

PWM

Output

Drive

PWM Outputs

Protection I/O

Converter

Digital

Audio

Interface

2

I S Digital Audio Input

DSD

Decimator

Engine

2

I S Digital Audio Output

Audio Processing Decoders

•D2 Audio DSP

•Dolby® Digital/AC3,

•Dolby Pro Logic IIx

•AAC LC™

•DTS® Digital Surround

•Dolby® Digital Plus

4x Serial

Audio

Interface

2

SAI [0:3] I S/TDM

Digital Audio Input

Amplifier

Protection

Test,

Timer, PLL

HD Audio

Interface

HD Audio Interface

Stereo Analog Input

Control Ports

Power Supply

and Control

Stereo

ADC

SPI

GPIO

2-Wire

(I C Compliant)

2

FIGURE 1. BLOCK DIAGRAM

FN7838 Rev.4.00

Mar. 19, 2019

Page 1 of 33

D2-6 Family Audio SOC

Ordering Information

PART NUMBER

PART

AUDIO PROCESSING

TEMP.

PACKAGE

PKG.

(Notes 2, 3)

MARKING

FEATURE SET SUPPORT (Note 1) RANGE (°C) (RoHS COMPLIANT)

DWG. #

D2-71083-LR

D2-74083-LR

D2-71583-LR

D2-74583-LR

D2-74383-LR

D2-71083-LR Refer to Table 1

D2-74083-LR Refer to Table 1

D2-71583-LR Refer to Table 1

D2-74583-LR Refer to Table 1

D2-74383-LR Refer to Table 1

D2-71683-LR Refer to Table 1

-10 to +85 128 Ld LQFP

Q128.14x14

D2-71683-LR

(No longer available,

recommended replacement: D2-71583-LR)

NOTES:

1. The D2-6 devices support multiple audio processing algorithms and decoders, and support is device-dependent. Refer to Table 1 for the supported

features for each device part number.

2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the D2-71083, D2-74083, D2-71583, D2-74583, D2-74383 product information pages. For more information

about MSL, see TB363.

FN7838 Rev.4.00

Mar. 19, 2019

Page 2 of 33

D2-6 Family Audio SOC

D2-6 Family Device Feature Set Offering

The D2-6 family has specific part numbers to specify the features and algorithms supported in the device. These part numbers and

their supported features are shown in Table 1.

TABLE 1. D2-6 DEVICE PART NUMBERS AND FEATURES

ALGORITHM SUPPORT

(Note 4)

DSP CLOCK AND MEMORY

(Note 5)

PART NUMBER

D2-71083-LR

FEATURES

2

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 147MHz DSP Clock

Algorithm Audio Processing 24k X and Y Memory Capacities

32k P Memory Capacity

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs

Embedded 8-Channel Sample Rate Converter

2

D2-74083-LR

D2-71583-LR

D2-74583-LR

D2-74383-LR

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 160MHz DSP Clock

Algorithm Audio Processing 40k X and Y Memory Capacities

56k P Memory Capacity

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs

Embedded 8-Channel Sample Rate Converter

2

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 147MHz DSP Clock

Dolby® Digital/AC3 Decoder 24k X and Y Memory Capacities

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs Dolby® Pro Logic IIx

Embedded 8-Channel Sample Rate Converter

32k P Memory Capacity

DTS® Digital Surround Decoder

2

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 160MHz DSP Clock

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs Dolby® Pro Logic IIx

Embedded 8-Channel Sample Rate Converter

Dolby® Digital/AC3 Decoder

40k X and Y Memory Capacities

56k P Memory Capacity

DTS® Digital Surround Decoder

2

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 160MHz DSP Clock

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs Dolby® Digital Plus

Algorithm

40k X and Y Memory Capacities

56k P Memory Capacity

Embedded 8-Channel Sample Rate Converter

Dolby® Pro Logic IIx

DTS® Digital Surround Decoder

2

D2-71683-LR (No longer

available, recommended

8-Channels Audio of I S Digital Inputs

D2 Audio DSP Sound Enhancement 147MHz DSP Clock

Dolby® Digital/AC3 Decoder 24k X and Y Memory Capacities

32k P Memory Capacity

2 S/PDIF Digital Inputs

replacement: D2-71583-LR) 8 Audio Processing Channels with PWM Outputs Dolby® Pro Logic IIx Surround

Embedded 8-Channel Sample Rate Converter

DTS® Digital Surround Decoder

AAC LC™ Decoder

NOTES:

4. D2 Audio DSP Sound Enhancements are included with all D2-6 family devices with no additional licensing or royalties required. The D2-71583-LR and

D2-74583-LR devices include Dolby Digital and DTS Digital Surround support and third part licenses are required. The D2-74383-LR device includes

Dolby Digital Plus and DTS Digital Surround support and third party licenses are required. Dolby Pro Logic IIx support is an optional feature that can

be added to the D2-71583-LR, D2-74583-LR, and D2-74383-LR products. Additional third part licensing is required for Dolby Pro Logic IIx.

5. 147MHz DSP clock speed represents an actual DSP clock of 147.456MHz, and 160MHz DSP clock speed represents an actual DSP clock of

159.744MHz, when using a crystal frequency of 24.576MHz.

FN7838 Rev.4.00

Mar. 19, 2019

Page 3 of 33

D2-6 Family Audio SOC

Table of Contents

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

D2-6 Family Device Feature Set Offering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Audio Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

Two-Wire (I C) Interface Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SPI™ Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Target Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Application Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System Features and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Audio Processing Signal Flow Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

HD Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sample Rate Converters (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clocks And PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Hardware I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Amplifier Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Booting and Boot Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Audio Processing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Firmware Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Input Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Master Volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Channel Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Tone Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Excursion Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Upward Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

High/Low-Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Routers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Loudness Contour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Audio Processing Enhancements and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Sound Enhancement Algorithm Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimer for Dolby Technology License Required Notice:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimer for DTS (SRS) Technology License Required Notice: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FN7838 Rev.4.00

Mar. 19, 2019

Page 4 of 33

D2-6 Family Audio SOC

Absolute Maximum Ratings (Note 8)

Thermal Information

Supply Voltage

Thermal Resistance (Typical)

128 Ld LQFP Package (Notes 6, 7) . . . . . .

Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

JA (°C/W) JC (°C/W)

40 6.5

RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V

CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V

Input Voltage

Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to RVDD +0.3V

XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V

Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

Recommended Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C

Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V

Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V

Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6.  is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.

JA

7. For  , the “case temp” location is taken at the package top center.

JC

8. Absolute Maximum parameters are not tested in production.

Electrical Specifications

T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages

A

referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are

measured in full power down configuration.

TEST

MIN

MAX

PARAMETER

Digital Input High Logic Level (Note 9)

SYMBOL

CONDITIONS

(Note 12)

TYP

-

(Note 12)

UNIT

V

RVDD = 3.3V

(Scales with

RVDD)

2.0

-

IH

Digital Input Low Logic Level (Note 9)

V

RVDD = 3.3V

(Scales with

RVDD)

-

0.8

V

IL

High Level Output Drive Voltage

V

RVDD - 0.4

-

V

OH

(I

OUT

at - Pin Drive Strength Current, see “Pin Descriptions” on page 11)

Low Level Output Drive Voltage

(I at + Pin Drive Strength Current, see “Pin Descriptions” on page 11)

V

0.4

OL

OUT

High Level Input Drive Voltage XTALI Pin

Low Level Input Drive Voltage XTALI Pin

Input Leakage Current (Note 10)

Input Capacitance

VIHX

VILX

0.7

-

PLLVDD

V

-

0.3

I

-

±10

µA

pF

V

IN

C

-

9

-

IN

High Level Output Drive Voltage OSCOUT Pin

Low Level Output Drive Voltage OSCOUT Pin

Output Capacitance

VOHO

VOLO

PLLVDD - 0.3

-

0.3

V

C

-

9

-

pF

ns

V

OUT

nRESET Pulse Width

t

-

10

3.3

15

<1

1.8

450

15

1.8

25

10

3.3

12

-

RST

Typical Digital and PWM I/O Pad Ring Supply

(Voltage)

(Current, Active)

R

/

3.0

3.6

VDD

PWM

VDD

-

mA

V

(Current, Power-down)

-

Typical Core Supply

(Voltage) CVDD

(Current, Active)

(Current, Power-down)

(Voltage) PLLVDD

1.7

1.9

-

mA

V

-

Typical PLL Analog Supply

Typical ADC Analog Supply

1.7

1.9

(Current, Active)

-

mA

V

(Current, Power-down)

-

3.0

-

3.6

-

(Voltage) ADCVDD

(Current, Active, Power-Down)

mA

FN7838 Rev.4.00

Mar. 19, 2019

Page 5 of 33

D2-6 Family Audio SOC

Electrical Specifications

T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages

A

referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are

measured in full power down configuration. (Continued)

TEST

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

(Note 12)

TYP

(Note 12)

UNIT

MHz

CRYSTAL OSCILLATOR

Crystal Frequency (Fundamental Mode Crystal)

Xo

Dt

20

24.576

24.822

(24.576 + 1%)

Duty Cycle

40

-

60

20

%

Start-Up Time (Start-Up Time is Oscillator Enabled

(with Valid Supply) to Stable Oscillation)

t

5

ms

START

PLL

VCO Frequency

Input Reference Frequency

F

80.00

20

294.912

-

297.86

MHz

VCO

F

24.822

IN

(24.576 + 1%)

Feedback Dividers (Integer)

PLL Lock Time from any Input Change

1.8V POWER-ON RESET

4

-

12

2

15

-

ms

Reset Enabled Voltage Level

POR Pulse Width Rejection

V

-

1.1

1.4

V

EN

t

150

500

µs

REJ

(Note 13)

POR Minimum Output Pulse Width

1.8V BROWNOUT DETECTION

Detect Level

t

-

5

-

µs

DIS

1.4

-

1.5

100

-

1.6

V

Pulse Width Rejection

Minimum Output Pulse Width

3.3V BROWNOUT DETECTION

Detect Level

t

-

ns

BOD1

t

20

O1

2.5

-

2.7

100

-

2.9

V

Pulse Width Rejection

Minimum Output Pulse Width

ADC PERFORMANCE SPECIFICATIONS

ADCREF DC Level

t

-

ns

BOD3

t

20

O3

V

I

= 0

REF

1.3

1.4

-

1.5

±20

-

V

REF

ADCREF Load Current

ADCREF Source Impedance

Analog Input Level

I

-

µA

kΩ

V

REF

R

14

-

REF

V

- 0.6

V

+ 0.6

REF

AIN

REF

Dynamic Range

-

94

-80

0.1

-80

-70

-

dB

THD+N

-

Gain Mismatch

Crosstalk

Power Supply Rejection

NOTES:

9. All input pins except XTALI.

10. Input leakage applies to all pins except XTALO.

11. Power-down is with device in reset and clocks stopped.

12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

13. Limits established by characterization and are not production tested.

FN7838 Rev.4.00

Mar. 19, 2019

Page 6 of 33

D2-6 Family Audio SOC

Serial Audio Interface Port Timing (Figure 2) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All

A

grounds at 0.0V. All voltages referenced to ground.

MIN

MAX

SYMBOL

tc

DESCRIPTION

SCKRx Frequency - SCKR0, SCKR1

(Note 12)

TYP

(Note 12)

UNIT

MHz

ns

12.5

SCLK

tw

SCKRx Pulse Width (High and Low) - SCKR0, SCKR1

LRCKRx Set-Up to SCLK Rising - LRCKR0, LRCKR1

LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1

SDINx Set-Up to SCLK Rising - SDIN0, SDIN1

SDINx Hold from SCLK Rising - SDIN0, SDIN1

SDOUTx Delay from SCLK Falling

40

20

SCLK

LRCLK

ts

ns

th

ns

ts

ns

SDI

th

ns

t

20

ns

dSDO

t SCLK

w

c

SCKRx

t LRCLK

t

SCLK

h

w

LRCLKRx

t LRCLK

t SDI

s

SDINx

t SDI

t SDO

h

d

SDOUTx

FIGURE 2. SERIAL AUDIO INTERFACE PORT TIMING

FN7838 Rev.4.00

Mar. 19, 2019

Page 7 of 33

D2-6 Family Audio SOC

2

Two-Wire (I C) Interface Port Timing (Figure 3) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All

A

grounds at 0.0V. All voltages referenced to ground.

MIN

TYPICAL

MAX

SYMBOL

DESCRIPTION

(Note 12)

UNIT

kHz

µs

f

SCL Frequency

100

SCL

t

Bus Free Time Between Transmissions

SCL Clock Low

4.7

4.0

4.7

4.0

buf

tw

µs

lowSCLx

tw

SCL Clock High

µs

highSCLx

ts

STA

Set-Up Time For a (Repeated) Start

Start Condition Hold Time

µs

th

STA

µs

th

SDA Hold From SCL Falling (Note 14)

SDA Set-Up Time to SCL Rising

SDA Output Delay Time From SCL Falling (Note 15)

Rise Time of Both SDA and SCL (Note 15)

Fall Time of Both SDA and SCL (Note 15)

Set-Up Time for a Stop Condition

1

µs

SDAx

ts

250

ns

td

3.5

1

µs

t

µs

r

f

t

300

ns

ts

4.7

µs

STO

NOTES:

14. Data is clocked in as valid on next XTALI rising edge after SCL goes low.

15. Limits established by characterization and not production tested.

t

SCLx

whigh

t

R

F

t

SCLx

wlow

SCLx

t STA

s

t SDAx

t STO

h

s

t

tsSDAx

BUF

SDAx (INPUT)

t STAx

h

SDAx (OUTPUT)

t SDAx

d

2

FIGURE 3. I C INTERFACE TIMING

FN7838 Rev.4.00

Mar. 19, 2019

Page 8 of 33

D2-6 Family Audio SOC

SPI™ Interface Port Timing (Figure 4) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V.

A

All voltages referenced to ground.

MIN

MAX

SYMBOL

DESCRIPTION

(Note 12)

UNIT

SPI MASTER MODE TIMING

t

MOSI Valid From Clock Edge

MISO Set-Up to Clock Edge

MISO Hold From Clock Edge

nSS Minimum Width

-

8

ns

V

S

H

t

10

-

t

1 system clock + 2ns

3 system clocks + 2ns

t

WI

SPI SLAVE MODE TIMING

t

MISO Valid From Clock Edge

MOSI Set-Up to Clock Edge

MOSI Hold From Clock Edge

nSS Minimum Width

3 system clocks + 2ns

-

V

S

H

10

ns

t

1 system clock + 2ns

3 system clocks + 2ns

t

WI

SCK (CPHA = 1, CPOL = 0

SCK (CPHA = 0, CPOL = 0

t

V

MOSI

t

H

t

S

MISO (CPHA = 0

nSS

t

WI

FIGURE 4. SPI TIMING

FN7838 Rev.4.00

Mar. 19, 2019

Page 9 of 33

D2-6 Family Audio SOC

Pin Configuration

128 LD LQFP

TOP VIEW

1

SC20

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

PWMVDD

PWM0

2

SRD2

3

SC21

PWM1

4

SCK2

PWM2

5

STD2

PWM3

6

SC22

PWMGND

PWMVDD

PWM4

7

MCLK

8

SCK3

9

STD3

PWM5

10

SC32

PWM6

11

SC30

PWM7

12

SC31

PWMGND

PWMVDD

PWM8

13

SRD3

14

STD0

15

SCK0

PWM9

16

CVDD

PWM10

PWM11

PWM12

PWM13

PWMGND

PWMVDD

PWM14

PWM15

PWM16

PWM17

PWMGND

CVDD

17

CVDD

18

CGND

19

CGND

20

RGND

21

RVDD

22

SRD0

23

SC00

24

SC01

25

SC02

26

SCK

27

TIO1

28

MISO

CGND

29

MOSI

RGND

30

GPIO7

RVDD

31

GPIO3

GPIO1

32

GPIO2

PROTECT2

FN7838 Rev.4.00

Mar. 19, 2019

Page 10 of 33

D2-6 Family Audio SOC

Pin Descriptions

NAME

(Note 16) TYPE

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

1

DESCRIPTION

2

SC20

SRD2

SC21

SCK2

STD2

SC22

MCLK

I/O

O

3.3

8

4

Serial Audio Interface 2, I S0 SCLK

2

Serial Audio Interface 2, I S0 SDIN

2

3

8

Serial Audio Interface 2, I S0 LRCK

2

4

8

Serial Audio Interface 2, I S1 SCLK

2

5

8

Serial Audio Interface 2, I S1 SDIN

2

6

4

Serial Audio Interface 2, I S1 LRCK

2

7

16

I S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset and

is enabled by firmware assignment.

2

8

SCK3

STD3

SC32

SC30

SC31

SRD3

STD0

SCK0

CVDD

I/O

P

3.3

8

4

8

Serial Audio Interface 3, I S3 SCLK

2

9

Serial Audio Interface 3, I S3 SDIN

2

10

11

12

13

14

15

Serial Audio Interface 3, I S3 LRCK

2

Serial Audio Interface 3, I S2 SCLK

2

Serial Audio Interface 3, I S2 LRCK

2

Serial Audio Interface 3, I S2 SDIN

2

Serial Audio Interface 0, I S SDAT0

2

Serial Audio Interface 0, I S LRCK0

16, 17,

48, 49,

70, 114

Core power, 1.8V

18, 19,

50, 51,

69, 113

CGND

P

3.3

Core ground

20

21

RGND

RVDD

P

3.3

Digital pad ring ground. Internally connected to PWMGND.

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

22

23

24

25

26

27

SRD0

SC00

SC01

SC02

SCK

I/O

3.3

4

8

Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.

2

8

Serial Audio Interface 0, I S SDAT1

2

8

Serial Audio Interface 0, I S LRCK1

4

SPI clock I/O with hysteresis input.

TIO1

16

Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

28

29

30

MISO

MOSI

I/O

3.3

4

SPI master input, slave output data signal.

SPI master output, slave input data signal.

GPIO7

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

31

32

33

GPIO3

GPIO2

GPIO4

I/O

3.3

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

FN7838 Rev.4.00

Mar. 19, 2019

Page 11 of 33

D2-6 Family Audio SOC

Pin Descriptions(Continued)

NAME

(Note 16) TYPE

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

34

DESCRIPTION

GPIO5

GPIO6

SDA1

SCL1

I/O

3.3

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

35

36

37

38

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

8 - OD

4

Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers for

data transport.

Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave controllers

for clock signaling.

PROTECT9 I/O

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

39

40

41

SPDIFRX1

SPDIFRX0

SPDIFTX

I

3.3

-

S/PDIF Digital audio data input 1

S/PDIF Digital audio data input 0

O

4

S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon

firmware, driving stereo output up to 192kHz.)

42

43

TEST

IRQA

I

3.3

-

Factory test use only. Must be tied low.

Interrupt request port A, Boot mode select. One of four IRQ pins. Connects to logic high (3.3V) or

to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

44

45

46

47

IRQB

IRQC

IRQD

TIO2

I

3.3

-

Interrupt request port B, Boot mode select. One of four IRQ pins. Connects to logic high (3.3V) or

to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

I

Interrupt request port C, Boot mode select. One of four IRQ pins. Connects to logic high (3.3V) or

to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

-

Interrupt request port D, Boot mode select. One of four IRQ pins. Connects to logic high (3.3V) or

to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

I/O

16

Timer I/O port 2. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

52

53

RGND

RVDD

P

3.3

-

Digital pad ring ground. Internally connected to PWMGND.

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

54

55

56

PUMPHI

PUMPLO

PSSYNC

I/O

3.3

16

Assignable I/O. Function and operation defined by firmware.

Synchronizing output signal to switching power supply. (Operates under specification of firmware

and resets to high impedance inactive state when not used.)

57

58

59

60

PSTEMP

PSCURR

I/O

3.3

4

Assignable I/O. Function and operation defined by firmware.

PWM synchronization port. (Function and operation is defined by firmware.)

PWMSYNC I/O

PROTECT3 I/O

16

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

61

62

PROTECT4 I/O

PROTECT5 I/O

3.3

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

FN7838 Rev.4.00

Mar. 19, 2019

Page 12 of 33

D2-6 Family Audio SOC

Pin Descriptions(Continued)

NAME

(Note 16) TYPE

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

63

DESCRIPTION

PROTECT6 I/O

PROTECT7 I/O

PROTECT2 I/O

3.3

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

64

65

66

67

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

GPIO1

RVDD

I/O

P

16

-

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

68

71

72

RGND

PWMGND

PWM17

P

3.3

-

Digital pad ring ground. Internally connected to PWMGND.

PWM output pin ground. Internally connected to RGND.

-

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

73

74

75

76

PWM16

PWM15

PWM14

PWMVDD

I/O

P

3.3

8 or 16

-

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

77

78

PWMGND

PWM13

P

3.3

-

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

79

80

81

82

83

84

PWM12

PWM11

PWM10

PWM9

I/O

P

3.3

8 or 16

-

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM8

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWMVDD

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

85

86

PWMGND

PWM7

P

3.3

-

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

87

88

89

PWM6

PWM5

PWM4

I/O

3.3

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

FN7838 Rev.4.00

Mar. 19, 2019

Page 13 of 33

D2-6 Family Audio SOC

Pin Descriptions(Continued)

NAME

(Note 16) TYPE

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

90

DESCRIPTION

PWMVDD

P

3.3

-

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

91

92

PWMGND

PWM3

P

3.3

-

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

93

94

95

96

97

PWM2

PWM1

I/O

P

3.3

1.8

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM0

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWMVDD

OSCOUT

-

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

P

Analog oscillator output to slave D2-71x83 devices. OSCOUT drives a buffered version of the

crystal oscillator signal from the XTALI pin.

98

99

PLLAGND

PLLTESTB

PLLTESTA

XTALI

P

O

P

1.8

-

PLL Analog ground

Factory test use only. Must be tied low.

100

101

Crystal oscillator analog input port. An external clock source would be driven into the this port. In

multi-D2-71x83 systems, the OSCOUT from the master D2-71x83 would drive the XTALI pin.

102

XTALO

P

1.8

-

Crystal oscillator analog output port. When using an external clock source, this pin must be open.

XTALO does not have a drive strength specification.

103

104

105

106

107

108

109

110

111

PLLAVDD

ADCVDD

AIN1

P

I

1.8

3.3

-

PLL Analog power, 1.8V

Analog power for internal ADC, 3.3V

Analog input 1 to internal ADC

ADCREF

AIN0

O

I

Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.

Analog input 0 to internal ADC

ADCGND

nTRST

nSS

P

I

Analog ground for internal ADC

-

4

-

Factory test only. Must be tied high at all times.

SPI slave select I/O.

I/O

P

RVDD

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

112

115

116

117

118

119

120

121

RGND

SC12

P

3.3

-

Digital pad ring ground. Internally connected to PWMGND.

Serial Audio Interface 1, LRCK

I/O

O

8

SC11

8

Serial Audio Interface 1, SDAT3

SC10

8

Serial Audio Interface 1, data (Assignment by firmware control.)

Serial Audio Interface 1, SDAT2

STD1

8

SCK1

8

4

Serial Audio Interface 1, SCK

SRD1

nRSTOUT

Serial Audio Interface 1, data (Assignment by firmware control.)

16 - OD

Active low open drain reset output. Pin drives low from POR generator, 3.3V brown out detector

going active, or from 1.8V brown out detector going active. This output should be used to initiate

a system reset to the nRESET pin upon brownout event detection.

FN7838 Rev.4.00

Mar. 19, 2019

Page 14 of 33

D2-6 Family Audio SOC

Pin Descriptions(Continued)

NAME

(Note 16) TYPE

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

DESCRIPTION

122

nRESET

I

3.3

-

Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all

internal logic and program operations. System latches boot mode selection of the IRQ input pins

on the rising edge.

123

124

TIO0

I/O

3.3

16

4

Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

PROTECT1 I/O

PROTECT0 I/O

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

125

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

126

GPIO0

SDA0

SCL0

I/O

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

127

8 - OD

Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers for

data transport.

128

Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave controllers

for clock signaling.

NOTES:

16. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix.

17. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins

to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and

PWMGND pins are also internally connected and are to be tied together.

FN7838 Rev.4.00

Mar. 19, 2019

Page 15 of 33

D2-6 Family Audio SOC

System Features and Support

The D2-6 enables multiple solutions consisting of a class-D

amplifier system built around internal audio processing

functional blocks. Features include:

Introduction

The D6 family of ICs provide the core functionality, amplifier

control, and complete audio signal processing for D2 Audio’s

Class-D amplifier solutions. A variety of reference designs from

Renesas D2 Audio DSP include specific signal flows designed for

their applications, supporting today’s design features. Support is

also provided for future planned features, with little or no

additional hardware or logic to enable new features. The signal

flow, digital audio I/O, and amplifier hardware control support is

handled completely by the D2-6 family firmware.

• Flexible audio input and output configurations

2

- Four independent asynchronous I S digital inputs

- Support of 8 audio channels of HDMI

- HD Audio (HDA)

- Direct Stream Digital™ (DSD) input support

- Integrated high-performance stereo ADC

The products are targeted at high-volume Home Theater in a Box

(HTiB), Multimedia, Soundbar, and similar solutions, where rich

features and cost-effective quality audio are required to meeting

demands of current consumer electronics markets.

- Dual multiplexed S/PDIF™ digital audio inputs

(Linear IEC-61958 PCM or compressed IEC-61937 audio)

- S/PDIF Digital Audio PCM Output

- Line-level Outputs (Left, Right, Subwoofer) using passive or

active output filter stages

The D2-6 family devices are completely pin-compatible with the

D2-3 family family devices, allowing full flexibility for function vs

cost trade-off, providing cost-effective solutions for applications

of varying end-user features and capabilities.

• Flexible DSP clock speed and DSP memory capacity options

- 147.456MHz DSP clock speed devices, with 24k X and Y

memory and 32k P memory capacity

Target Performance

Typical systems built around the D2-6 family support

performances that includes or exceeds:

- 159.744MHz DSP clock speed devices, with 24k X and Y

memory and 32k P memory capacity

• Real-time amplifier control and monitoring

• >110 dB SNR/dynamic range system support

• <0.06% THD+N at full scale at 1kHz

- Supports bridged, half-bridged, and Bridge-Tied Load (BTL)

topologies, using discrete or integrated power stages from 10W

to over 500W

• 20Hz to 20kHz audio frequency response

• Scalable amplifier power control capability

- Graceful protection and recovery

- Complete fault protection with automatic recovery

2

• Serial control interface using I C, HDA, SPI, or SCI

• Discrete component and integrated power stages using

full-bridge, half-bridge, and BTL output topologies

• Decoding of Compressed audio formats, including

®

- Dolby Digital/AC3

• Encrypted code loads and unique decryption for each IC part

number

®

- Dolby Pro Logic IIx

- AAC™ LC

• Support for all standard audio data delivery formats and

protocols employed in the target markets

®

- DTS Digital Surround

®

- Dolby Digital Plus

2

• The delivery formats include: I S, left-justified, Time-Division

• Audio enhancement feature support

Multiplexed (TDM), S/PDIF, DSD, HDA, 2-channel analog

- D2 Audio DSP Sound Enhancement Algorithm audio

processing enhancement

Application Markets

The powerful DSP coupled with flexible peripherals and excellent

signal processing hardware results in a chip for solutions that

cover many markets. All are characterized by the need for

complex signal processing and high audio channel count. Typical

applications include a wide variety of cost sensitive but

feature-demanding performance such as in:

• Multimedia speaker solutions

• Multi-driver (Bi-Amp, Tri-Amp) speaker arrays

• Home theater systems with compressed audio decoder

• Soundbar system solutions

• Set-top box solutions

• Low-cost virtualized stereo, 5.1, 7.1, and 9.1 AVR systems

• Bluetooth/WiFi voice-enabled speaker systems

• Aftermarket/OEM automotive amplifiers

FN7838 Rev.4.00

Mar. 19, 2019

Page 17 of 33

D2-6 Family Audio SOC

Audio Processing Signal Flow Support

Audio Input

The D2-6 family series of ICs support a wide variety of signal

flows and audio processing options that are fully programmable

and are completely defined by the system firmware and system

architecture.

Multiple versions of the D2-6 family IC-based reference designs

support a wide range of market applications and each of these

market applications has a variety of potential audio sources such

as:

The firmware provided for the D2-6 family is application-specific

and includes its own specific signal flow and associated

performance level. Much of the signal flow is also hardware

dependent and that hardware integrates with the full system

architecture that is defined within that system’s programmed

firmware. Each firmware design includes a specific set of control

tool support, including the D2 Audio DSP customization GUI

software and system design data.

• Mono and stereo analog inputs

2

• Serial audio, I S and Time Division Multiplexed (TDM) Single

Line “Network” mode

• HD-audio interface (UAA-Class Driver Capable)

• Stereo and multichannel DSD

• S/PDIF digital (IEC60958-compliant and IEC61937-compliant)

SERIAL AUDIO INPUT

Additional design-specific reference documentation is included

within each firmware application design, that includes

platform-specific signal flows, control registers, and descriptions

of advanced processing features.

Because most systems incorporate some mix of digital and analog

inputs, the D2-6 family offers a very flexible digital audio peripheral

interface. The D2-6 family features four independent Serial Audio

Interface (SAI) ports. All SAI ports support both master or slave

clocking and can support sample rates from 32kHz to 192kHz.

The various system support capabilities include:

• Flexible system configuration with 8 audio input and audio

processing channels, with up to 12 audio output PWM

channels, supporting differential or single-end PWM outputs

with up to 18 PWM output pins.

2

Each SAI port supports the digital audio industry I S standard, which

supports carrying up to 24-bit Linear PCM audio words per subframe

®

IEC60958, or compressed digital audio (Dolby Digital, AAC, DTS ,

MPEG, etc.) packing per the IEC61937 specification. The SAI port

also supports left-justified formatted linear PCM or compressed

digital audio. Each SAI port supports time division multiplexing

(TDM) capability (also known as “Network mode”) with up to 32

words per frame.

• Audio processing for up to 4 simultaneous stereo

asynchronous digital audio inputs from a variety of sources

2

(HDA, I S, HDMI, DSD, S/PDIF Digital)

• Multiple D2-6 family devices may be cascaded to support

higher channel count designs.

SAI Ports 2 and 3 (the 3rd and 4th ports) have multiplexed inputs

to provide a standard input signal flow for the ADC, DSD, and

HDA audio interfaces. All serial audio input data streams go

through an SAI interface, which simplifies the data flow

configuration.

Functional Description

The D2-6 family of ICs, integrated into D2 Audio DSP offerings of

reference design platforms support present and future design

features with little or no additional hardware or logic to enable

new features.

2

SAI data formats are shown in Figure 6. For I S format, the left

channel data is read when LRCK is low. For the left-justified

format, the left channel data is read when LRCK is high. Either

format requires data to be valid on the rising edge of SCLK and

sent MSB-first on SDIN with 32 bits of data per channel. Each set

of digital inputs runs asynchronously to the others and may

accept different sample rates and formats.

Left Channel

LRCLKx

SCLKx

Right Channel

Serial

Data

-1

-2

-1

-2

-3

+3

+2

+1

LSB

+3

+2

+1

LSB

-3

MSB

I²S Format

Right Channel

LRCLKx

SCLKx

Left Channel

Serial

Data

-1

-2

-1

-2

-4

+3

+2

+1

LSB

-3

+3

+2

+1

LSB

-3

MSB

-4

MSB

-1

Left-Justified

FIGURE 6. SAI PORT SUPPORTED DATA FORMATS FOR DELIVERY OF LINEAR PCM OR COMPRESSED AUDIO DATA

FN7838 Rev.4.00

Mar. 19, 2019

Page 18 of 33

D2-6 Family Audio SOC

S/PDIF RECEIVER

ADC INPUT

The D2-6 family contains two input pins internally multiplexed

into one IEC60958 compliant S/PDIF Digital receiver. The

receiver input pins are 3.3V CMOS input level compatible,

requiring external circuitry to condition the serial input. The

receiver contains an input transition detector, digital PLL clock

recovery, and a decoder to separate audio, channel status, and

user data. Only the first 24-channel status bits are supported.

The receiver constantly monitors the incoming data stream to

detect the IEC61937-1 packet headers, and if found, captures

the Pc and Pd data words into registers. The receiver meets the

jitter tolerance specified in IEC60958-4.

The D2-6 family contains a high-performance Analog-to-Digital

Converter (ADC) that connects to input analog sources with a

minimum of interface circuitry. At a bandwidth of 20kHz at

nominal voltage and temperature, the ADC input of the D2-6

family provides a typical THD+N (unweighted) value of -81dB and

an SNR/dynamic range of 94dB.

The ADC master clock can be supplied from either the low jitter

PLL of the D2-6 family, or from the HD audio interface. When the

PLL provides the ADC master clock, the ADC operates

synchronous to the DSP processing, which minimizes noise

pickup. When operated from the HD audio clock system, the ADC

decimator output is synchronous to the HDA frame rate,

eliminating the need for sample rate conversion to the HDA

frame rate. Figure 7 shows the ADC decimator frequency

response over full bandwidth and passband, and Figure 8 shows

the ADC performance with full scale input processed through the

SRC to a 48kHz sample rate.

S/PDIF is a commonly used interface for receiving compressed

(IEC61937-compliant) and stereo PCM (IEC60958-compliant)

audio data. This interface also supports receipt of compressed

audio data that is not compliant with the IEC61937 specification,

but instead meets the IEC60958 specification.

0.020

0

24 BITS

SPEC

24 BITS

SPEC

0.015

0.010

0.005

0

50

-0.005

-0.010

-0.015

-0.020

100

150

0

0.5

1.0

1.5

2.0

2.5

3.0

4

0

0.5

1.0

1.5

2.0

2.5

3.0

6

x10

FREQUENCY (Hz)

x10

FIGURE 7. ADC DECIMATOR FREQUENCY RESPONSE (256 TAPS DECIMATE BY 32)

0

fs = 6.144MHz

Ch0 INPUT = 1kHz AT 1V

P-P

THD + N = -81dB SNR = 94dB

-20

-40

-60

-80

-100

-120

-140

0

5k

10k

15k

20k

FREQUENCY (Hz)

FIGURE 8. ADC PERFORMANCE AT FULL SCALE INPUT

FN7838 Rev.4.00

Mar. 19, 2019

Page 19 of 33

D2-6 Family Audio SOC

The DSD input processing clusters the DSD data into channel

pairs. This allows a flexible channel count of 2, 4, or all 6 DSD

data streams to be handled. Using 4-channel DSD frees the SAI 3

port for other uses. Similarly, using only 2-channel DSD frees the

second SAI 2 port and the SAI 3 port for other uses.

DSD

The HDMI specification (version 1.2 and later) used in TV systems

supports streaming DSD encoded audio over HDMI. To support

this, the system can receive and process up to six DSD audio

streams. The DSD interface supports both standard and

phase-modulated data formats. A high-quality 16x decimator

engine converts all of the DSD data streams into 24-bit PCM

words with an FS of 176.4kHz using a 128-tap FIR filter. The DSD

decimation filter has a cutoff frequency of 50kHz and is

optimized for passband flatness.

The D2-6 family of ICs also offers digital audio format conversion

2

support for DSD stereo format input to S/PDIF or I S format

output, as well as DSD multichannel format input to multiple I S

2

format output. This high-quality digital audio format conversion

path also offers the ability to reduce clock jitter in the audio

system introduced by certain transmission paths such as HDMI.

SAI Ports 2 and 3 support DSD format inputs. When the DSD

interface is enabled, all the pins of SAI 2 and the SC21 pin of

SAI3 become the DSD input signals. The six channels of DSD

audio are merged into three I S PCM streams at a 176.4kHz

sample rate. These I S streams are routed into both receivers on

SAI 2 and the first receiver of SAI 3. The data is then passed to

the Sample Rate Converter (SRC). The SRC rate-locks to the DSD

input clock and attenuates any jitter in the DSD input stream.

This technique also enables consumer products to output a

downsampled and/or downmixed (if necessary) digital audio

output for audio that may not otherwise be made available to the

consumer in the original higher-bandwidth format due to certain

consumer electronic/content protection licensing restrictions.

2

The graphs in Figure 9 show the DSD decimation filter frequency

response at two different frequency zoom levels.

0.020

0

24 BITS

SPEC

24 BITS

SPEC

0.015

0.010

0.005

0

-50

-100

-150

-0.005

-0.010

-0.015

-0.020

0

2

4

6

8

10

12

14

x10

0

0.5

1.0

1.5

2.0

2.5

3.0

4

5

FREQUENCY (Hz)

x 10

FREQUENCY (Hz)

FIGURE 9. DSD DECIMATOR FREQUENCY RESPONSE (128 TAPS DECIMATE BY 16)

FN7838 Rev.4.00

Mar. 19, 2019

Page 20 of 33

D2-6 Family Audio SOC

SERIAL AUDIO OUTPUT

Audio Output

The D2-6 family IC-based systems support outputting a bit-exact

pass-through of a compressed audio bitstream, or a decoded,

down-mixed (Lt/Rt or Lo/Ro) and downsampled 2-channel Linear

PCM audio bitstream using a specified SAI port, or S/PDIF digital

transmitter. In addition, depending on the firmware functionality,

it is possible for unused SAI (Serial Audio Interfaces) to also

support I S output as well, in either slave or master mode. The

output audio sample rate is determined by the firmware and can

vary from 32kHz up to 192kHz.

PWM AUDIO AMPLIFIER OUTPUT

The D2-6 family supports multiple PWM output topologies, which

enables system designs to use an output stage, which meets the

cost and performance requirements of the particular application.

Twelve PWM channels are mapped to 18 PWM output pins by the

programmed firmware. The PWM output pins are 3.3V CMOS

levels with either 8mA or 16mA drive capability.

2

Output topologies supported include:

• Half-bridge, N+N or N+P

HD Audio

• Full-bridge, N+N or N+P using 2-level modulation, 2 or

4-quadrant control

HDA INTERFACE

The HD audio interface also provides a control interface. This

control interface uses the HD audio GPI, GPO, and GPIO 8-bit

ports to provide a message passing facility between the D2-6

family and the PC.

LINE LEVEL OUTPUT

In addition to amplified outputs, the D2-6 family IC also supports

line-level outputs that generate a nominal 1V

simple passive filter.

output using a

RMS

The D2-6 family fully supports Windows® Hardware Quality Labs

(WHQL™)-certification as, it is a UAA-Compliant Secondary HD

Audio CODEC. The devices may be used either as the primary

HDA CODEC, or as the second HDA CODEC in the system.

Headphone outputs or line-level outputs that require a 2V

RMS

higher output level) are also supported, using an active filter to

accomplish the signal level needs.

(or

Features supported are:

S/PDIF TRANSMITTER

• Message passing to other devices located on the motherboard

(for example, HP jack detection and reporting)

The D2-6 family contains one IEC60958 compatible S/PDIF

Digital transmitter. The transmitter complies with the consumer

applications defined in IEC60958-3. The transmitter supports

24-bit audio data, 24-bit user data, and 30-bit channel status

data.

• Amplifier firmware download

• Amplifier code load during system boot

• Amplifier control protocol (D2 Audio DSP customization GUI

support)

A bit-exact pass-through mode from the selected SPDIFRX[1:0]

input is also supported. This simplifies system designs that

require that the IEC61937-compliant original compressed audio

bitstream be made available at the back panel of the product, as

well as giving the user the capability to select a decoded (and

downmixed, if necessary) IEC60958-compliant stereo or mono

linear PCM output for digital audio recording/playback

capabilities.

HD AUDIO PLAY

The D2-6 family provides for direct connection of a PC’s HD Audio

(HDA) Controller to the device. In this configuration, the

D2-6 family functions as an HDA CODEC with powered

(amplified) outputs.

Supported features include:

The D2-6 family optional firmware offers digital audio format

• 2, 4, 6, or 8 amplified or PWM DAC channels

• Audio sample rates 48kHz, 96kHz, and 192kHz

• Data widths of 16-bit, 20-bit, and 24-bit

• Independent channel gain control

2

conversion support for I S digital format input to S/PDIF digital

2

format output, as well as S/PDIF digital format input to I S

digital format output, for all digital audio Linear PCM

(non-compressed) audio sources. This functionality is not

available for compressed audio inputs, unless the compressed

audio data is first decoded by the internal DSP, and if necessary,

downmixed to two channels.

The HDA interface uses five of the six pins of the SAI 3 port. The

HDA interface captures the audio streams and converts them

2

into one to four I S data streams, depending on the number of

This format conversion path offers the ability to reduce the clock

jitter on the output due to the fact that both inputs (when in this

mode) pass through the professional-grade Sample-Rate Converters

(SRC). This approach also enables consumer products to output a

downsampled digital audio output for audio that may not otherwise

be made available to the consumer in the original higher-bandwidth

format due to certain consumer electronic/content protection

licensing restrictions.

2

channels used. These I S stereo streams are routed through

SAI 3 and SAI 4 and then on to the sample rate converter. The

SRC will rate lock to the HDA stream and remove any jitter while

converting the data to the output sample rate.

FN7838 Rev.4.00

Mar. 19, 2019

Page 21 of 33

D2-6 Family Audio SOC

HD AUDIO FUNCTIONS AND FUNCTION TYPES

TABLE 2.

NODE ID

01

FUNCTION

Audio Function Group

FUNCTION TYPE

Function Group

Stereo DAC

CONNECTIONS

Parent of all other nodes, also holds GPIO functions

To Front L/R mixer

Front L/R DAC

02

Center/LFE DAC

Stereo DAC

03

To Center/LFE mixer

Surround L/R DAC

Stereo DAC

04

To Surround L/R mixer

Side Surround L/R DAC

Front L/R Mixer

Stereo DAC

05

To side surround mixer

Sum/Mixer Node

Pin Complex

06

To front L/R pin

Center/LFE Mixer

07

To center/LFE pin

Surround L/R Mixer

Side Surround L/R Mixer

Front L/R Output Pin

Center/LFE Output Pin

Surround L/R Output Pin

Side Surround L/R Output Pin

08

To surround L/R pin

09

To side surround L/R pin

0A

To system per configuration default register

Pin Complex

0B

Pin Complex

0C

Pin Complex

0D

HD AUDIO VERBS SUPPORTED

TABLE 3.

WIDGET NID

VERB FUNCTION

Converter Format

GET CODE

SET CODE

01

02 - 05

Y

06 - 09

0A - 0D

Y

A

B

2

3

4

5

Gain/Mute

Processing Coefficient

Coefficient Index

Get Parameter

Connection Select

Get Connection List

Processing

C

D

F00

F01

F02

F03

F04

F05

F06

F07

F08

F09

F0A

F0C

F0D

F0F

F10 - F1A

F1C

F20

F24

Y

701

SDI Select

704

705

Power State

Channel/Stream ID

Pin Widget

Y

706

Y

707

Y

Unsolicited Response

Pin Sense

708

709

Beep

70A

EAPD/BTL

70C

Digital Converter

Volume Knob

GPI

70D - 70E

70F

710 - 71A

71C - 71F

720 - 723

724

Y

Config Default

Subsystem ID

Stripe

Y

Reset

7FF

FN7838 Rev.4.00

Mar. 19, 2019

Page 22 of 33

D2-6 Family Audio SOC

HD AUDIO WIDGET REQUIRED PARAMETERS

TABLE 4. VERB ID - 0xF00; PARAMETERS 0x9 - 0xD

WIDGET CAP.

PID 0x9

PCM SIZE RATE

FORMAT

PIN CAP.

PID 0xC

INPUT AMP CAP.

PID 0xD

NODE ID

01

FUNCTION

Function

DAC

PID 0xA

PID 0xB

Y

02

Y

03

DAC

04

DAC

05

DAC

06

Mixer

Y

07

08

09

0A

Y

0B

0C

0D

TABLE 5. VERB ID - 0xF00; PARAMETERS 0xE - 0x13

CONNECT LIST

OUTPUT AMP

CAP.

LENGTH

POWER STATES

PROCESS CAP.

VOLUME KNOB

PID 0x13

NODE ID

01

FUNCTION

Function

DAC

PID 0xE

PID 0xF

Y

PID 0x10

PID 0x12

02

03

DAC

04

DAC

05

DAC

06

Mixer

Y

07

08

09

0A

0B

0C

0D

FN7838 Rev.4.00

Mar. 19, 2019

Page 23 of 33

D2-6 Family Audio SOC

HD AUDIO SYSTEM TOPOLOGY

Front L/R

Mixer

(Gain Control)

Front L/R

Pin Complex

(Mute Control)

Front L/R

DAC

NID 02

NID 06

NID 0A

Center / LFE

Mixer

(Gain Control)

Center / LFE

Pin Complex

(Mute Control)

Center / LFE

DAC

NID 03

NID 07

NID 0B

HDA Link

Interface

Surround L/R

Mixer

(Gain Control)

Surround L/R

Pin Complex

(Mute Control)

Surround L/R

DAC

NID 04

NID 08

NID 0C

Side Surr L/R

Mixer

(Gain Control)

Side Surr L/R

Pin Complex

(Mute Control)

Side Surr L/R

DAC

NID 05

NID 09

NID 0D

FIGURE 10. HD AUDIO SYSTEM TOPOLOGY

ADC, sample rate conversion, and the audio data paths. The

serial audio interfaces can function as either a master or a slave.

Sample Rate Converters (SRC)

The D2-6 family ICs support internal asynchronous sample rate

conversion to align input audio streams to a single rate

compatible with the DSP processing rate and PWM switch rate.

D2-6 device family has four independent rate estimators,

allowing up to four asynchronous stereo inputs (eight channels)

to be sample rate converted and processed simultaneously. The

sample rate converter has a measured SNR that exceeds 140dB

and a THD+N that exceeds -125dB.

The PLL block contains the following components:

• Low noise crystal oscillator

• Low jitter PLL clock multiplier

• Power-on reset generator

• Brown out detectors on the CVDD and RVDD supplies

• System reset generation logic

DSP

• Clock generators for the DSP, S/PDIF transmitter, ADC, and

MCLK output pin

The majority of the D2-6 family audio processing functions as

well as system control occur within the DSP core. The core is a

24-bit fixed-point digital signal processor, tightly integrated with

its own DMA, interrupt control, memory, and control interfaces.

Software configurable processing blocks and signal routings are

implemented within the DSP, allowing a wide range of

The PLL block is completely managed by the system firmware.

The system clock is provided by the crystal oscillator block, using

either a fundamental mode crystal or a clock input to the XTALI

pin. If the clock input is used, it must be a 1.8V signal level. The

input signal on the XTALI pin is analog buffered and driven onto

the OSCOUT pin for use in driving the XTALI input of other D2-6

family controllers.

functionality and system implementations through the

programmed definitions that are read into memory upon device

initialization. Signal flows through the device are buffered and

processed through hardware specific-function blocks (such as

the sample rate converter) and allow considerable overall signal

processing capability through interface to the DSP.

The PLL uses the signal on the XTALI pin as the reference clock.

The reference clock frequency is multiplied by an integer

multiple of 4 to 15 to get the PLL output clock. The PLL output is

used to time the PWM outputs and to generate the DSP clock.

During system start-up, before the PLL has been configured and

locked, the PLL is bypassed and the system operates at XTALI

speed.

Clocks And PLL

The clock generation contains a low jitter PLL critical for low

noise PWM output and a precise master clock source for the

FN7838 Rev.4.00

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D2-6 Family Audio SOC

The power-on reset circuit senses the rise of the PLLVDD supply.

When the supply reaches the sense threshold, the power-on reset

pulse is generated. If the PLLVDD supply droops below the sense

threshold, the reset pulse occurs when the supply rises above the

threshold. The power-on reset signal drives the nRSTOUT output

pin low.

POWER SUPPLY SYNCHRONIZATION

The PSSYNC pin provides a power supply synchronization signal

for switching power supplies. Firmware configures PSSYNC to the

frequency and duty cycle needed by the system switching

regulator. The proper configuration eliminates audio output tones

generated if the switching power supply is not locked to the

amplifier switching.

The two power supply brown out detectors monitor the CVDD and

PWMVDD power rails. If the power rail droops below the

threshold, the brown out detector activates and drives the

nRSTOUT output pin low.

POWER SUPPLY ANTI-PUMP

The D2-6 family supports designs to correct for power supply

pumping that occurs in half-bridge output stage topologies. The

PUMPHI and PUMPLO pins provide a differential PWM signal pair

that drive an anti-pump correction stage. The dead time and duty

cycle are adjustable to eliminate the power supply DC offset.

The system reset generation logic is activated by a low level on

the nRESET input pin or by the power-on reset sensor pulse. Upon

de-assertion of nRESET a sequential counter ensures sufficient

time and clock cycle count for the internal synchronous logic to

reset.

Amplifier Protection

Multiple D2-6 family ICs are capable of running on a common

timebase. Multiple D2-6 family ICs synchronize themselves onto

a single crystal oscillator so that all ICs run at identical

frequencies.

The D2-6 family supports individual PWM channel protection

through individual protection input pins. These PROTECT pins are

primarily intended for protecting the PWM powered output

stages. The protection inputs are activated by either a pulse or

level driven into the pin. Firmware configures the input

DSP CLOCK SPEED AND MEMORY CAPACITY SUPPORT

processing logic to properly interpret the input signal as rising

edge triggered, falling edge triggered, high level, or low level.

The D2-6 family devices are offered in part number-specific

devices that support multiple DSP clock speeds and memory

capacity. Depending on the device part number, the D2-6

operates up to clock rates of 147.456MHz or 159.744MHz, and

offers memory capacity of 24k/24k/32k or 40k/40k, 56k of

X/Y/P memory space.

The protection input signal is generated by specialized sensing

circuits. There are several kinds of sensing circuits for detecting

current, temperature, or voltage. A powered PWM output stage or

a power supply pump driver typically uses an overcurrent sensor.

This sensor detects power FET current, load current, or both.

These circuits are unique to the specific power stage design, and

may be embedded inside an integrated power stage.

Temperature and voltage sensing are accomplished in a variety

of ways and usually create a DC level representing a fault

condition.

The higher speed and larger memory devices support designs

requiring higher processing capacity, while the lower speed

devices provide cost optimization to systems not requiring the

additional audio processing and decode capability.

Refer to “D2-6 Family Device Feature Set Offering” on page 3 for

the device part numbers and definitions of clock speed and

memory capacity.

The D2-6 family designs incorporate a variety of protection

strategies to prevent damage from the high voltages, currents,

and temperatures present in class-D amplifier designs. This

protection is also effective against user-induced faults, such as

clipping, output overload, or output shorts, including both shorted

outputs or short-to-ground faults.

Hardware I/O Functions

The D2-6 family provides programmable I/O pins used for

various hardware functions of the system design. Pin functions

are defined by the product firmware, and may be different from

one design to another.

The D2-92xx IC works in conjunction with specific surrounding

parts to provide continuous system monitoring for destructive

events. These events include:

GENERAL-PURPOSE (GPIO) I/O PINS,

• Output overcurrent

Eight dedicated General Purpose I/O (GPIO) pins are available for

system use. These are controlled only by the D2-6 device family

firmware.

• Output short-circuit

• Over-temperature (thermal event)

• Power supply brown out

• Shoot-through overcurrent

TIMERS

A timer block consisting of three separate general purpose

timers provides programmed control of event or count down

timing functions. The timer functions are controlled through the

firmware, where these timers can operate as timed pulse

generators, as pulse-width modulators, or as event counters to

capture an event or to measure the width or period of a

connected signal. These timers are connected to the three timer

pins (TIO[0:2]), which are also assignable as I/O by firmware.

Protection features and their details are firmware application

dependent.

Firmware functions running on the D2-6 family can be assigned

to observe the temperature at critical points in the hardware and

automatically respond to excessive temperature. Depending on

the specific implementation, this response can be as simple as

turning on an optional fan to reduce temperature, or managing

the audio signal to reduce power consumption.

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D2-6 Family Audio SOC

GRACEFUL OVERCURRENT AND SHORT-CIRCUIT

Booting and Boot Modes

Overcurrent sensing requires a current sensor in the power

device to be protected, usually a powered PWM output. The

typical sensor creates a pulse that is active when the current

exceeds a specified threshold.

CODE INITIALIZATION AND BOOT MODES

The D2-6 family includes a fully-programmable DSP with internal

boot ROM. The boot ROM’s primary function is to download a

second-stage boot image from one of several possible peripheral

sources:

The D2-6 family ICs observe the overcurrent protection inputs

and provide graceful protection for the output stage. The

hardware is configured to provide immediate current reduction,

cycle-by-cycle output clipping, output signal control, and output

stage deactivation depending on the severity and duration of

high current events. The combination of hardware features and

firmware monitoring allows the system to differentiate between

an overcurrent situation or a more serious short-circuit condition.

2

• I C interface EEPROM

2

• I C interface slave

• SPI ROM

• SPI interface slave

• HDA bus

THERMAL PROTECTION

The specific boot mode is selected based on the state of the

IRQD, IRQC, IRQB, and IRQA pins at the time of reset

de-assertion. The boot ROM code has been designed to handle

both encrypted and non-encrypted boot images from any of the

above storage locations. Boot modes are shown in Table 6 on

page 27.

The D2-6 family ICs can connect to an optional low-cost thermal

sensing circuit and monitor temperatures in the system.

Firmware monitoring can record the system temperature and

provide system responses including enabling a fan and

managing the audio output signal.

The system requires external firmware to boot the internal DSP.

Internal ROM within the D2-6 family initiates the boot process to

read the boot records and firmware, to load into the internal D2-6

family memory.

Device Operation

RESET AND INITIALIZATION

The D2-6 family ICs must be reset after power up to begin proper

operation, and in normal system hardware configurations, the

reset occurs automatically using the reset hardware circuitry. The

chips contain power rail sensors, brown out detectors, on the 3.3V

and 1.8V power supplies. These brown out sensors asserts and

hold an internal power-on reset, which disables the device until the

power supplies are at a safe level for the DSP to start. These same

brownout sensors detect a power supply voltage droop while the

system is active and provide a safe amplifier shutdown.

There are multiple boot modes provided on the D2-6 devices, as

shown in Table 6. The mode is selected by a hardware pull-up or

pull-down connection to each of the four boot mode (IRQ[D:A])

pins. (Modes not listed are reserved.) Boot sources include:

2

• I C EEPROM

• SPI EEPROM or SPI flash

2

• I C slave (to external microcontroller)

• SPI slave (to external microcontroller)

POWER SEQUENCING

• Asynchronous UART (RS-232 for PC Communication mode as

well as D2-6 family Device to Device Communication mode)

The CVDD and RVDD (including PWMVDD) supplies should be

brought up together to avoid high current transients that could

fold back a power supply regulator. The ADCVDD and PLLVDD

may be brought up separately. Best practice would be for all

supplies to feed from regulators with a common power source.

Typically this can be achieved by using a single 5V power source

and regulating the 3.3V and 1.8V supplies from that 5V source.

• HD audio bus

2

• Combo mode with I C EEPROM or SPI

RESET

The D2-6 family ICs have one reset input: the nRESET pin. The

nRESET input pin (active low, non-reset high) is effectively a

power-on system reset. All internal state logic, except internal

test hardware, is initialized by nRESET. While reset is active the

system is held in the reset condition. The reset condition is

defined as all internal reset signals being active, the crystal

oscillator is running, and the PLL disabled.

At the de-assertion of nRESET, the chip captures the boot mode

selection and begins the boot process.

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D2-6 Family Audio SOC

TABLE 6. BOOT MODES

INTERFACE

SPEED

MODE

IRQ[D:A]

0000

M/S

S

XTALI RANGE

N/A

DESCRIPTION

USAGE

System

2

0

1

per Master

I C port 1 slave boot at address 88

2

0001

M

24.576 MHz

400kb/s

Combo Master - ROM on I C port 0 or SPI

(See Note 18)

2

0010

M

24.576MHz

1.53MHz

ROM on SPI (EE or FLASH)

System

(Copy of Mode 1 for pin compatibility)

3

7

B

0011

0111

1011

S

N/A

per Master

384kb/s

SPI slave boot

System

Multi-IC

System

24.576MHz

24.576 MHz

Fast asynchronous SCI boot

9600 b/s

Asynchronous SCI interface boot (RS232

Compatible)

C

1100

M

24.576MHz

1.53MHz

(See Note 18)

HDA enabled, Combo Master - ROM on SPI (EE or

FLASH)

System

D

E

F

1101

1110

1111

M

24.576MHz

24.576 MHz

400kb/s

per Master

400Kb/s

Copy of mode C for pin compatibility

HDA boot

System

2-wire ROM on GPIO port (SCL= GPIO1,SDA = GPIO0)

System/

Failsafe

NOTE:

18. For the “per Master” and “N/A” entries above, there is a maximum transfer rate that is a fraction of XTALI speed. This maximum transfer rate is

peripheral port specific.

APPLICATION FIRMWARE LOAD

MULTI-CONTROLLER IC COMMUNICATION

The application firmware is loaded either by the boot code or by a

multi-step process. Direct boot code loading occurs when the

selected boot mode successfully finds a boot image on the

expected peripheral interface and the image is successfully

loaded in memory. A multi-step boot is one in which the boot

code loads a program that manages the system boot.

The D2-6 family ICs are capable of communicating and

synchronizing data and control information across multiple D2-6

family ICs. This communication is to facilitate matrix mixing of all

input channels in a system and to allow precise phase alignment

of the output audio. Systems designs are capable of achieving

outputs phase aligned to within 1/2 sample at 192kHz. One

D2-6 family IC acts as the timing master, so all other D2-6 family

ICs must then operate as timing slaves. The setting of each of the

D2-6 family ICs is system-configuration specific and is detailed in

the specific RDP documentation.

Control Interfaces

2

I C 2-WIRE INTERFACE

2

The D2-6 family ICs have two separate I C 2-wire compatible

AUDIO SYNCHRONIZATION

ports. One is typically used for the external microcontroller

interface, and the other for D2-6 family IC communication to

Multiple D2-6 family ICs can be connected together and

synchronized for controlling events to meet phase alignment

requirements.

2

EEPROMs, or other compatible peripheral chips. Both I C

interfaces are multi-master capable.

2

Registers are accessed through the I C control interface.

Control Protocols provide for an external device communication

with the D2-6 family firmware while the amplifier is running. The

D2-6 family firmware has a peripheral device driver that

establishes communication with the external controller device.

The D2-6 family is always a slave. Communication can occur

2

Because the I C bus has multiple slaves, the desired I C target

device must be addressed. The specific I C channel control

2

address is defined within the firmware that is loaded into the

D2-6 family at boot and initialization time. Typical addresses

used in various reference designs use the address of 0xB2, but

the actual address should be confirmed based on the firmware

design being used in the application.

2

through the HDA, I C, and SPI ports. However control is provided

2

through only the I C, and HDA ports, and control through the SPI

port is not supported.

SERIAL PERIPHERAL INTERFACE (SPI™)

CONTROL REGISTER SUMMARY

The Serial Peripheral Interface (SPI) is an alternate serial

interface to the I C interfaces. As a master, this interface

supports port extenders, EEPROMs, Flash, and various control

interfaces for more complex chips. As a slave, this provides an

alternate method for customers to communicate with the

system.

The control register interface provides a mechanism for an

external controller to manipulate the amplifier signal flow, and

provides access to the internal registers.

2

Each system design has its own firmware-dependent register

Application Programming Interface (API) and its own unique

signal flow. The control register definitions, bit fields, and data

format for each register are specified in that firmware API.

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D2-6 Family Audio SOC

by the device address with the write bit set, and three register

address bytes. Next, the master must send a repeated Start,

following with the device address with the read/write bit set to

read, and then read the next three data bytes. The master must

Acknowledge (ACK) the first two read bytes and send a Not

Acknowledge (NACK) on the third byte received and a Stop

condition to complete the transaction. The device's control

interface acknowledges each byte by pulling SDA low on the bit

immediately following each write byte. The device read function,

READING AND WRITING CONTROL REGISTERS

Registers and memory spaces are defined within the D2-6 family

firmware for specific internal operation and control. In typical

reference designs, the highest-order byte of the register address

(Bits 23:16) determines the internal address space used for

control read or write access, and the remaining 16 bits (Bits

15:0) describe the actual address within that space. Refer to the

descriptions of the actual reference design firmware being used

in the application for specific definitions.

2

as shown in Figure 12, executes the following 11 steps as the I C

All reads or writes to registers (shown in Figures 11 and 12)

begin with a Start Condition, followed by the Device Address byte,

three Register Address bytes, three Data bytes, and a Stop

Condition.

bus master:

2

1. I C START command

2

2. Transmit device I C address with W

3. Transmit mode byte

2

Register writes through the I C interface are initiated by setting

4. Transmit upper memory address byte

5. Transmit lower memory address byte

6. Repeat START command

the read/write bit that is within the device address byte. The

device write function as, shown in Figure 11, executes the

following nine steps as the I C bus master:

2

1. I C START command

7. Transmit device I C address with R

2

2. Transmit device I C address with W

8. Receive data upper byte

9. Receive data middle byte

10. Receive data lower byte

3. Transmit mode byte

4. Transmit upper memory address byte

5. Transmit lower memory address byte

6. Transmit data upper byte

2

11. I C STOP command or NACK

7. Transmit data middle byte

8. Transmit data lower byte

2

9. I C STOP command

All reads to registers require two steps. First, the master must

send a dummy write, which consists of sending a Start, followed

ACK

DEVICE-ADDR

REGISTER [23:16]

REGISTER [15:8]

REGISTER [7:0]

START

R/W

ACK

Write Sequence

REGISTER [7:0]

DATA [23:16]

DATA [15:8]

DATA [7:0]

STOP

2

FIGURE 11. I C WRITE SEQUENCE OPERATION

Step 1

ACK

DEVICE-ADDR

REGISTER [23:16]

REGISTER [15:8]

REGISTER [7:0]

REPEAT

START

R/W

MASTER

ACK

MASTER

ACK

NACK

Read Sequence

DEVICE-ADDR

DATA [23:16]

DATA [15:8]

DATA [7:0]

REPEAT

START

R/W

STOP

Step 2

2

FIGURE 12. I C READ SEQUENCE OPERATION

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D2-6 Family Audio SOC

Input Source Selection

A source selection register specifies the action of a signal

multiplexer, which implements a simple switching function. The

selected input is routed to the block output unaltered. All

non-selected inputs are ignored. Selections typically include I S

inputs, S/PDIF Digital inputs, HD Audio inputs, and ADC inputs.

Audio Processing Functions

Each system design has its own firmware-dependent signal flow.

This signal flow may be generic, or specifically designed for a

particular amplifier application and consists of input elements

connected to various signal processing blocks, routing the audio

data to an output element. The input elements consist of chip

2

peripherals used for audio input (I S input, S/PDIF Digital

Master Volume

2

receiver, and ADC). The output elements include the chip I S

output, S/PDIF Digital transmitter, and PWM outputs.

A master volume function alters the level on all channels

simultaneously by applying the same gain/attenuation function

to each. A single parameter controls all channels.

Typical audio processing blocks include gain stages, mixers, tone

controls, compressors, limiters, equalizers, routers, loudness

contour, crossover filters, delays, as well as audio enhancement

features provided within the specific application firmware.

Channel Attenuation

A channel attenuation function alters the level of a single

channel. A single parameter is provided for each channel.

The input and output elements are configured by the firmware

application and the scope of I/O selection is generally specific to

the hardware of the particular application.

Equalization

An equalization processing block consists of a single input and

output, and is characterized by how many frequency bands are

supported. Typical equalizers have 3-bands or 5-bands, although

multiple combinations are directly supported. Each frequency

band has three parameters - the center frequency, the filter Q,

and the filter gain.

The signal processing blocks contain one or more parameters

that define the signal transfer characteristic of the block and a

mechanism for choosing the source and destination data

locations. The signal flow is created by connecting together the

signal processing blocks in the proper order to achieve the

overall system audio processing function.

Tone Control

Firmware Functions

Tone control provide simple bass and treble processing to the

audio signal. Each tone processing block includes two first-order

(6dB/octave) shelving filters, one each for bass and treble. Filters

include programmable corner frequency and gain settings.

D2-6 family ICs contain a DSP supporting powerful audio

processing algorithms. Some of the standard audio algorithms

that are typically supported in all firmware loads. Other

algorithms are specific system design and firmware load

dependent.

Excursion Control

Additional features support multiple system capabilities such as:

Excursion processing provides dynamic control of the subwoofer

response. Three audio processing control adjustments are

provided for frequency settings, and three adjustments are

provided for Q parameter settings.

• Automatic power-on amplifier calibration

• Parameter control and status reporting

• Integrated power supply control and clock synchronization

• Automatic power supply high-voltage rail anti-pump control

Mixer

Mixer configuration blocks have multiple input channels and as

many output channels as required by the system implementation.

The mixer has an input gain parameter for each input to every

mixing node. (for example, an 8-input mixer with 12 outputs

incorporates a total of 96 independent gain adjustment

parameters). The minimum gain parameter value is infinite

attenuation, or mute.

• Automatic negative rail generation and bring-up control (for

select half-bridge designs where a ± rail is not already

supplied)

• Automatic cycle-by-cycle temperature sensing and system

response

• Automatic cycle-by-cycle current sensing and system response

• Input audio signal sensing and pop-free power-on/off using D2

Audio DSP’s patented “Green Mode” algorithm with adjustable

threshold

Mixers

An input mixer provides a two-input, two-output mixing and

routing path. All inputs can be mixed at adjustable gain into any

combination of outputs. Programmable settings are continuously

adjustable from unity (0 dB) gain, through full cut-off.

• Dynamic adjustment of efficiency vs. distortion vs. output

power level using D2 Audio DSP’s patented “DynaTiming”

algorithm

• AM radio interference avoidance mode allows for dynamic

switching of PWM engines when system microcontroller is in

AM Radio model

Compressor/Limiter

The compressor/limiter processor is used to gracefully limit the

dynamic range of the audio signal. This is useful to prevent the

amplifier from clipping or to limit the amplifier output power.

Each compressor/limiter has configurable compression ratio,

threshold, attack and release time, as well as makeup gain.

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D2-6 Family Audio SOC

Upward Compressor

Audio Processing Enhancements and

Decoding

Depending on the device part number and design-specific

firmware definitions, the D2-6 family devices support a variety of

processing, decoding, virtualization, and pre/post processing

feature sets, as well as options for DSP clock speed and memory

capacity. Features and processing support are shown in

“D2-6 Family Device Feature Set Offering” on page 3.

Upward compressors provide audio compression and limiting

functions but also provide an increase of signal level to inputs

below the threshold setting. Upward compressors have

configurable expansion ratio, threshold, attack and release time,

as well as makeup gain. Controls are supported for global

settings, gate adjustment, and for low-level expansion.

Upward compressors support two inputs. One input receives the

audio that is processed by the compressor and passed to its

output. A separate side chain input is the reference input for the

processing algorithms.

Sound Enhancement Algorithm Processing

The D2 Audio DSP Sound enhancement algorithm audio

processing provides a full set of enhancements to audio that

greatly add to the quality and listening experience of sound in

wide scopes of consumer devices. The D2 Audio DSP Sound

Enhancement Algorithms use psycho-acoustic processing that

create a rich-sounding environment from small speakers, and

synthesizes the sound and quality equivalent to more complex

systems. It is especially suited to consumer products that include

televisions, docking stations, and mini hi-fi stereo products.

Delay

A delay block simply adds delay to the audio signal. A single

delay parameter is used.

Crossover

Low-pass and high-pass filter blocks add frequency filtering to

the audio paths, providing appropriate signal processing for

speaker crossover functionality, including bi-amplified solutions,

and subwoofer low-pass filtering.

The D2-6 family includes enhanced sound enhancement

algorithm processing that includes:

• 2 Channel stereo spatialization

High/Low-Pass Filters

• Bass Enhancement

High-Pass and Low-Pass filter blocks are provided for each of the

five output channels downstream of the router and stereo mixer.

These provide a flexible crossover function for all the output

channels, including provision for defining the subwoofer

channel’s frequency response.

• Content/configuration EQ presets

• Improved vocal clarity

• Automatic room audio setup/equalization/optimization

• Automatic loudspeaker setup/equalization/correction

Filters are implemented as cascaded elements, with elements

allocated for high-pass as well as for low-pass functionality, with

complete flexibility of assignment. Pre-defined filter types

including Butterworth, Bessel, and Linkwitz-Riley

The D2 Audio DSP sound enhancement algorithms are

completely included within the D2-6 family devices.

implementations are also provided.

Routers

Routers provide individual audio path selection to any one of

available input channels. The router performs path assignment

only. It does not have a provision for gain or signal level

adjustment.

Loudness Contour

Loudness contour provides adjustment to allow for dynamically

and automatically enhancing the frequency response of the

audio program material relative to the master volume Level

setting. The loudness contour models the frequency response

correction as defined by the Fletcher/Munson audio response

curve. It provides for amplitude or volume changes to those

signals to which the ear does not respond equally at very low

listening levels.

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D2-6 Family Audio SOC

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please go to web to make sure you have the latest revision.

DATE

REVISION

FN7838.4

CHANGE

Mar 19, 2019

Changed the title from: D2-7xx83 to: D2-6 Family Audio SOC

Added Related Literature section.

Updated Applications and Features sections on page 1.

Updated Figure 1.

Updated Ordering Information table by removing retired parts and adding D2-74383-LR.

Changed throughout: “D2Audio™” to “D2 Audio DSP”; “DAE-3” to “D2-3 Family”; “DAE-6” and “D2-7xx83” to “D2-

6 Family”; “Digital Audio Engine” to “Digital Audio Processor”; “SoundSuite” to “Sound Enhancement Algorithm”;

removed “DTS®Studio Sound II”

Page 3, table 1:

- Added “DTS® Digital Surround Decoder” to the algorithm support column on page 3 for D2-74383-LR part.

- Added a note for “algorithm support” column.

Figure 5 on page 16, changed “D2AudioTM SoundSuite” to “D2 Sound Enhancement Algorithm”; for the lower

block about Post-processing, changed the text to the following: “Post-Processing (D2 Sound Enhancement

Algorithms for tone and equalization control)

Changed Audio Enhancement Features bullet points on page 30.

Removed Mark Levinson MightyCat™ Processing section.

Updated Application Markets section.

Removed About Intersil section on page 31

Updated to Renesas disclaimer and moved to end of datasheet.

Apr 28, 2016

FN7838.3

Updated the Ordering Information table on page 2.

Updated Table 1 on page 3 Algorithm Support column for D2-71583-LR, D2-74583-LR and D2-71683-LR.

Replaced the Products section with the About Intersil section.

Added Dolby and DTS disclaimers.

Sept 20, 2011

Jun 23, 2011

FN7838.2

FN7838.1

Revise/add available device part numbers and related descriptions.

Initial release.

Disclaimer for Dolby Technology License Required Notice:

Renesas may distribute Dolby™ technology separately from its D2 Audio DSP integrated circuits. Dolby™ technology would be

embedded in firmware to be loaded onto and executed by Dolby™ enabled D2 Audio DSP integrated circuits. Supply of this

implementation of Dolby technology does not convey a license nor imply a right under any patent or any other industrial or intellectual

property right of Dolby Laboratories to use this implementation in any finished end-user or ready-to-use final product. It is hereby

notified that a license for such use is required from Dolby Laboratories. In some cases the Dolby™ technology may include at least one

Dolby™ Pro Logic™ decoder. The party receiving this implementation must be licensed for at least one of the three Dolby Laboratories

Licensing Corporation (“Dolby”) technologies contained in this implementation. If the party receiving this implementation is not a

Licensee for all three of the Dolby technologies contained in this implementation then the party may only use the unlicensed

technology(ies) contained on the implementation for internal testing and evaluation purposes.

Disclaimer for DTS (SRS) Technology License Required Notice:

NOTICE OF LICENSE REQUIREMENT: Supply of this implementation of DTS technology to DTS Product Licensees directly or through a

distributor does not incur a royalty payment or convey a license, exhaust DTS’ rights in the implementation, or imply a right under any

patent or any other industrial or intellectual property right of DTS to use, offer for sale, sell, or import such implementation in any

finished end-user or ready-to-use final product. A license from and royalty payment to DTS is required prior to and for such use.

FN7838 Rev.4.00

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D2-6 Family Audio SOC

For the most recent package outline drawing, see Q128.14x14.

Package Outline Drawing

Q128.14x14

128 LEAD LOW PLASTIC QUAD FLATPACK

PACKAGE .4 MM PITCH (LQFP)

4X

0.2 Y T-U Z

D

MILLIMETERS

PIN 1

97

Z

128

SYMBOL

MIN

-

NOM

MAX

1.60

0.15

1.45

0.23

0.19

0.20

0.16

NOTES

A

A1

A2

b

-

1

96

0.05

1.35

0.13

0.09

-

1.40

-

0.16

4

b1

c

-

U

T

c1

D

-

16 BSC

14 BSC

16 BSC

14 BSC

0.60

-

E

E1

-

D1

E

3

-

E1

L

3

0.45

0.75

-

65

32

L1

R1

R2

S

1.00 REF

-

0.08

0.20

0°

-

0.20

-

33

64

-

D1

-

0.2 H T-U Z

4X

0

3.5°

7°

-

01

02

03

N

0°

-

11°

12°

13°

-

DETAIL

0.080 Y

F

12°

-

H

Y

128

-

e

0.40 BSC

-

Rev. 1 7/11

NOTES:

128X b

1. Dimensions are in millimeters. Dimensions in ( ) for

Reference Only.

e

124X

SEATING PLANE

0.07 Y T-U

M

b1

2. Dimensions and tolerances per AMSEY14.5M-1994.

3. Dimensions D1 and E1 are excluding mold protrusion.

Allowable protrusion is 0.25 per side. Dimensions D1

and E1 are exclusive of mold mismatch and deter-

mined by datum plane H.

c1

c

0.05

b

PLATING

02

4. Dimension b does not include dambar protrusion.

Allowable dambar protrusion shall not cause the lead

width to exceed the maximum b dimension by more

than 0.08mm. Dambar cannot be located at the lower

radius or the foot. Minimum space between protrusion

and an adjacent lead is 0.07 mm.

01

R1

A2

A

R2

03

0

A1

S

L

(L1)

0.25 GAUGE

PLANE

DETAIL

F

FN7838 Rev.4.00

Mar. 19, 2019

Page 32 of 33

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型号：	D2-74383-LR
厂家：	RENESAS TECHNOLOGY CORP
描述：	Intelligent Digital Amplifier and Sound Processor 外围集成电路
文件：	总33页 (文件大小：1288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

D2-74383-LR [RENESAS]

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