EL2019CN [INTERSIL]
Fast, High Voltage Comparator with Master Slave Flip-Flop; 快速，高电压比较器与主从触发器
| 型号： | EL2019CN |
| 厂家： | 
Intersil |
| 描述： | Fast, High Voltage Comparator with Master Slave Flip-Flop |
| 文件： | 总12页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL2019
®
December 1995, Rev. G
FN7025
Fast, High Voltage Comparator with
Master Slave Flip-Flop
Features
• Comparator cannot oscillate
The EL2019 offers a new feature
previously unavailable in a comparator
before—a master/slave edge triggered
• Fast response—5ns data to clock setup, 20ns clock to
output
• Wide input differential voltage range—24V on ±15V
supplies
flip-flop. The comparator output will only change output state
after a positive going clock edge is applied. Thus the output
can't feed back to the input and cause oscillation.
Manufactured with Elantec's proprietary Complementary
Bipolar process, this device uses fast PNP and NPN
transistors in the signal path. A unique circuit design gives
the inputs the ability to handle large common mode and
differential mode signals, yet retain high speed and excellent
accuracy. Careful design of the front end insures speed and
accuracy when operating with a mix of small and large
signals. The three-state output stage is designed to be TTL
compatible for any power supply combination, yet it draws a
constant current and does not generate current glitches.
When the output is disabled, the supply current consumption
drops by 50%, but the input stage and master slave flip-flop
remain active.
• Wide input common mode voltage range—±12V
• Precision input stage—V
OS
= 1.5mV
• Low input bias current—100nA
• Low input offset current—30nA
• ±4.5V to ±18V supplies
• Three-State TTL compatible output
• No supply current glitch during switching
• 103dB voltage gain (Low input uncertainty ≈ 30µV)
• 50% power reduction in shut-down mode
• Input and flip-flop remain active in shutdown mode
Ordering Information
Applications
PART NUMBER TEMP. RANGE
PACKAGE
PKG. NO.
• Analog to digital converters
• ATE pin receiver
EL2019CN
-40°C to +85°C
8-Pin PDIP
MDP0006
• Zero crossing detector
• Window detector
Pinout
EL2019
(8-PIN PDIP)
TOP VIEW
• “Go/no-go” detector
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
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Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL2019
Absolute Maximum Ratings (T = 25°C)
A
V
V
V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V
Input Voltage+V to -V
Differential Input Voltage . . . . Limited only by Power Supplies
Input Current (Pins 1, 2 or 3). . . . . . . . . . . . . . . . . . . . ±10mA
Input Current (Pins 5 or 6). . . . . . . . . . . . . . . . . . . . . . . ±5mA
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . .1.25W
I
I
T
T
T
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Continuous Output Current. . . . . . . . . . . . . . . . . . . . . . 25mA
Operating Temperature Range . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature. . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . .-65°C to +150°C
S
OP
O
IN
IN
S
S
A
I
I
IN
INS
J
ST
P
D
The maximum power dissipation depends on package type, ambient
temperature and heat sinking. See the Typical Performance curves for more
details.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
V = ±15V, unless otherwise specified
S
LIMITS
TYP
PARAMETER
DESCRIPTION
Input Offset Voltage
TEMP
MIN
MAX
6
UNITS
mV
mV
nA
V
25°C
1.5
OS
V
= 0V, V Transition Point
O
CM
T
T
T
, T
8
MIN MAX
I
I
Input Bias Current
= 0V, Pin 2 or 3
25°C
±100
30
±400
±600
150
250
B
V
CM
, T
nA
MIN MAX
Input Offset Current
= 0V
25°C
nA
OS
V
CM
, T
nA
MIN MAX
CMRR
PSRR
Common Mode Rejection
Ratio (Note 1)
25°C
25°C
25°C
75
75
90
95
dB
Power Supply Rejection
Ratio (Note 2)
dB
V
Common Mode Input
Range
±12
±12
±13
V
CM
T
T
T
, T
V
MIN MAX
V
V
Input Uncertainty Range
Output Voltage Logic Low
30
µV/RMS
UNCER
OL
25°C
-0.05
-0.1
0.15
0.4
0.4
V
V
I
= 8mA and I = 0mA)
OL
OL
, T
MIN MAX
V
Output Voltage Logic High
OH
V
V
V
V
V
= ±15V
= ±15V
= ±5V
= ±5V
= ±5V
S
S
S
S
S
25°C
3.5
3.5
2.4
2.4
2.4
4.0
4.65
4.65
V
V
V
V
V
, T
MIN MAX
25°C
T
MIN
T
MAX
V
V
V
Range, Disabled,
ODIS1
ODIS2
OUT
= -1mA
I
OL
25°C
4.65
4.65
V
V
V
V
V
V
V
= ±15V
= ±15V
= ±5V
S
S
S
T
, T
MIN MAX
25°C
All
3.65
-1
V
Range, Disabled,
-0.3
OUT
= +1mA
I
OL
V
= ±5V to +15V
S
2
EL2019
DC Electrical Specifications
V
= ±15V, unless otherwise specified (Continued)
S
LIMITS
TYP
PARAMETER
DESCRIPTION
Clock or CS Inputs
TEMP
MIN
2
MAX
UNITS
V
V
25°C
INH
Logic High Input Voltage
T
T
, T
2
V
MIN MAX
I
Clock or CS Inputs
Logic Input Current
25°C
±200
±300
µA
IN
, T
±300
µA
MIN MAX
V
= 0V and V = 5V
IN
IN
V
Clock or CS Inputs
Logic Low Input Voltage
25°C
0.8
0.8
13
14
6
V
INL
T
T
T
T
T
, T
V
MIN MAX
I
I
I
I
Positive Supply
Current Enabled
25°C
8.8
4.9
mA
mA
mA
mA
mA
mA
mA
mA
S+EN
S+DIS
S-EN
S-DIS
, T
MIN MAX
Positive Supply
Current Disabled
25°C
, T
7
MIN MAX
Negative Supply
Current Enabled
25°C
14.5
6.4
17
18
8.0
8.0
, T
MIN MAX
Negative Supply
Current Disabled
25°C
, T
MIN MAX
NOTES:
1. V
= +12V to -12V
CM
2. V = ±5V to ±15V
S
AC Electrical Specifications
V
= ±15V, T = 25°C
A
S
LIMITS
PARAMETER
DESCRIPTION
MIN
TYP
12
-3
MAX
UNITS
ns
T
T
T
T
T
T
Setup Time 5mV Overdrive
Hold Time
20
0
S
ns
H
Clock to Output Delay
20
7
25
ns
OPOUT
OPMIN
EN
Minimum Clock Width
ns
Output Three-State Enable Delay
Output Three-State Disable Delay
40
150
70
ns
300
ns
DIS
3
EL2019
Typical AC Performance Curves
Delay Time vs
Input Overdrive
Delay Time vs
Supply Voltage
Clock to Output Delay
vs Load Capacitor
Delay Time vs
Temperature
Enabled/Disabled Times
vs Temperature
Minimum Clock Width
vs Temperature
4
EL2019
Typical AC Performance Curves (Continued)
Input Bias Current vs
Differential Input Voltage
Input Bias Current
vs Temperature
Input Bias Current vs
Common Mode Voltage
V
/V Transfer Characteristics
I
O
Supply Current
vs Temperature
Supply Current
vs Supply Voltage
5
EL2019
Typical AC Performance Curves (Continued)
V
vs Positive
OH
V
vs Temperature
Supply Voltage
OUT
8-Pin Plastic DIP
Maximum Power Dissipation
vs Ambient Temperature
V
vs Positive
OH
Supply Voltage
Clock to Output Delay vs
Clock Time Constant
Set-up Time vs
Clock Time Constant
PSRR vs
Clock Time Constant
Hold Time vs
Clock Time Constant
Relative V
Shift vs
Clock Time Constant
OS
6
EL2019
Timing Diagram
Note: Since the hold time is
negative the input is a don't care at
the clock time. This ensures that
clock noise will not affect the
measurement.
Block Diagram
Function Table
INTERNAL Q
(TIME N)
INPUTS (TIME N-1)
NOTES
OUTPUT (TIME N)
+IN
-IN
CS
CLK
+
-
-
L
L
H
L
Normal Comparator Operation
With “D” Flip-Flop
H
L
+
+
-
-
+
H
H
H
L
Normal Comparator Operation
With “D” Flip-Flop; Power Down Mode
High Z
High Z
X
X
X
X
X
X
L
L
L
H
L
Qn-1
Qn-1
Qn-1
Data Retained in Flip-Flop
Data Retained in Flip-Flop
Data Retained in Flip-Flop
Qn-1
Qn-1
Qn-1
X
X
X
X
X
X
H
H
H
L
Qn-1
Qn-1
Qn-1
Data Retained in Flip-Flop,
Output Power Down Mode
Data Retained in Flip-Flop,
Output Power Down Mode
Data Retained in Flip-Flop,
Output Power Down Mode
High Z
High Z
High Z
H
latch remain active. This extremely fast and accurate device
is built with the proprietary Elantec Complementary Bipolar
Process, which is immune to power sequencing and latch up
problems.
Application Hints
Device Overview
The EL2019 is the first comparator of its kind. It is capable of
24V differential signals, yet has excellent accuracy, linearity
and voltage gain. The EL2019 has an internal master/slave
flip-flop between the input and output. It even has a three-
state output feature that reduces the power supply currents
50% when the output is disabled, yet the input stage and
Power Supplies
The EL2019 will work with ±5V to ±18V supplies or any
combination between (Example +12V and -5V). The
supplies should be well bypassed with good high frequency
7
EL2019
capacitors (0.01µF monolithic ceramic recommended) within
1/4 inch of the power supply pins. Good ground plane
construction techniques improve stability, and the pin from
pin 1 to ground should be short.
shifts, reduce PSRR, and cause the device to operate
incorrectly at low temperatures and low supply voltages. A
good method to control the clock edge rate is to place a
resistor in series and a capacitor to ground in parallel with
the clock input. Generally, any time constant 10ns or greater
will suffice.
Front End
The EL2019 uses schottky diodes to make a “bullet proof”
front end with very low input bias currents, even if the two
inputs are tied to very large differential voltages (±24V).
Elantec tests the EL2019 with a nominal 20ns time constant,
using a series 330Ω resistor and 61pF of capacitance to
ground (including strays). All clocks are generated by
Schottky TTL and have a 0.25V to 3.5V swing.
The large common mode range (±12V minimum) and
differential voltage handling ability (±24V min.) of the device
make it useful in ATE applications without the need for an
input attenuator with its associated delay.
Output Stage
The output stage of the EL2019 is a pair of complementary
emitter followers operating as a linear amplifier. This makes
the output stage of the EL2019 glitch free, and improves
accuracy and stability when operating with small signals.
Recovery from Large Overdrives
Timing accuracy is excellent for all signals within the
common mode range of the device (±12V with ±15V supply).
When the common mode range is exceeded the input stage
will saturate, input bias currents increase and it may take as
much as 200ns for the device to recover to normal operation
after the inputs are returned to the common mode range. If
signals greater than the common mode range of the device
are anticipated, the inputs should be diode clamped to
remain within the common mode range of the device, or the
supply voltage be raised to encompass the input signal in the
common mode range.
Three-State Output, Power Saving Feature
The EL2019 has an output stage which can be put into a
high impedance “three-state” mode. When it is in this mode,
the input stage and latch remain active, yet the device
dissipates only 50% of the power used when the output is
active. This has advantages in large ATE systems where
there may be 1000 comparators, but only 10% are in use at
any one time.
The EL2019 will work properly with the chip select input
(pin 5) floating, however, good R.F. technique would be to
ground this input if it is not used.
Input Slew Rate
All comparators have input slew rate limitations. The EL2019
operates normally with any input slew rate up to 300V/µs.
Input signal slew rates over 300V/µs induce offset voltages
of 5mV to 20mV. This induced offset voltage settles out in
about 20ns, 20 times faster than previous high voltage
comparators. This shows up as an increased set-up time.
Due to the power saving feature and linear output stage, the
EL2019 does not have a standard TTL three-state output
stage. As such one must be careful when using the three-
state feature with devices other than other EL2018’s or
EL2019’s. When operating from ±15V supplies the three-
state feature is compatible with all TTL families, however
CMOS families may conflict on high outputs. Since the
output stage of the EL2019 turns on faster than it turns off, a
50Ω to 100Ω resistor in series with the output will limit fault
currents between devices with minimum impact on logic
drive capability.
Master Slave Flip-Flop
The built-in Master/Slave Flip-Flop only allows the output to
change when a positive edge is received on the clock input.
This feature has some major benefits to the user. First, the
device cannot oscillate due to feedback from the output to
the inputs. Second, the device must make a decision when it
receives a clock input, and the difference between deciding
on a “0” or a “1” is limited only by the input circuit noise, both
internal and external to the EL2019. With low impedance
sources and a good layout this uncertainty can be less than
30µV/RMS. Since a 30µV change on the input can cause a
4V change on the output this works out to an effective gain of
103dB, more than adequate for a 16-bit analog to digital
converter.
The hold time of the EL2019 is worst case 0ns, and typically
-3ns. This means that the analog signal is sampled typically
3ns before the clock time and, worst case, concurrent with
the clock.
The EL2019 is sensitive to a large clock edge rates. More
than a 500V/µs edge rate at the clock input will induce V
OS
8
EL2019
Typical Applications
USING THE POWER DOWN/
THREE-STATE FEATURE
(V Range +12V to -12V with V = ±15V)
IN
S
A WIDE INPUT RANGE WINDOW COMPARATOR
The EL2019 makes an excellent comparator in most analog
to digital converters, due to its high gain and fast response.
Most 2504 based A to D designs can be modified to use the
EL2019 simply by using an inverted clock to the EL2019 as
shown below. This results in improved performance due to
less jitter of the transition voltages.
Burn-In Circuit
PIN NUMBERS ARE FOR DIP PACKAGES. ALL PACKAGES USE THE SAME SCHEMATIC.
9
EL2019
Equivalent Schematic
10
EL2019
EL2019 Macromodel
* Connections:
+input
*
|
-input
*
*
*
*
*
*
|
|
|
|
|
|
|
|
|
|
|
+V
|
|
|
|
|
-V
|
|
|
|
Cpin
|
|
|
CS
|
|
output
|
|
.subckt M2019
*
2
3
8
4
6
5
7
* Input Stage
*
i1 8 10 700µA
r1 13 4 1K
r2 14 4 1K
q1 8 3 11 qn
q2 8 2 12 qn
q3 13 11 10 qp
q4 14 12 10 qp
i2 11 4 200µA
i3 12 4 200µA
*
* 2nd Stage & Flip Flop
*
*i4 8 24 700µA
i4 8 24 1mA
q9 22 6 24 qp
q10 18 17 24 qp
v1 17 0 2.5V
q5 15 14 22 qp
q6 16 13 22 qp
r3 15 4 1K
r4 16 4 1K
q7 16 15 18 qp
q8 15 16 18 qp
i5 8 40 500µA
q11 41 17 40 qp
q12 42 6 40 qp
q13 43 16 41 qp
q14 44 15 41 qp
q15 44 43 42 qp
q16 43 44 42 qp
r5 43 4 1K
r6 44 4 1K
*
* Output Stage
*
i7 8 35 2mA
s1 35 20 5 0 sw
d2 35 8 ds
i6 26 34 5mA
s2 34 4 5 0 sw
d3 34 26 ds
q19 8 20 21 qn 2
q20 4 19 7 qp 2
r8 21 7 60
r7 20 19 4K
q17 19 44 26 qn 5
q18 0 43 26 qn 5
11
EL2019
q22 20 20 30 qn 5
q23 19 19 30 qn 8
d1 0 19 ds
q21 0 17 19 qp
*
* Power Supply Current
*
ips 8 4 4mA
*
* Models
*
.model qn npn (is=2e-15 bf=400 tf=0.05nS cje=0.3pF cjc=0.2pF ccs=0.2pF)
.model qp pnp (is=0.6e-15 bf=60 tf=0.3nS cje=0.5pF cjc=0.5pF ccs=0.4pF)
.model ds d(is=2e-12 tt=0.05nS eg=0.62V vj=0.58)
.model sw vswitch (von=0.4V voff=2.5V)
.ends
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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