EL4544_07_技术文档

EL4544

®

Data Sheet

April 3, 2007

FN7362.3

Triple 16x5 Differential Crosspoint Switch

Capable of Operation in Single-Ended or

Differential Input Modes

Features

• Serial programming of switch array

• Parallel or serial modes

The EL4544 is a high bandwidth 16-channel differential RGB

to 5-channel RGB single-ended RGB-HV video crosspoint

switch with embedded sync extraction. Four 16-channel

input muxes, each capable of receiving a complete RGB

video signal, and five output muxes, each capable of

“seeing” any one of the four RGB inputs. Additionally, the

fifth input mux has an overlay “screen on screen” function

that can be displayed in conjunction with any of the stacked

RGB inputs.

• High Z output disable

• Drives 150Ω loads

• 60MHz 0.1dB gain flatness

• -3dB bandwidth of 300MHz

• Crosstalk rejection: 75dB @ 100MHz

• Channels settle to 5% within 10ns after overlay switching

• 356 pin BGA packaging

The EL4544 has a fast disable feature to reduce power

consumption. The device also provides a presence of signal

indicator by looking for syncs on a designated channel.

• Pb-free plus anneal available (RoHS compliant)

Applications

Ordering Information

• Video switching

PART

PKG.

NUMBER

MARKING

PACKAGE

DWG. #

EL4544IGZ EL4544IGZ 356 Pin (27x27mm) BGA V356.27x27

(Note) (Pb-Free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL4544

Pinout

EL4544

(356 PIN BGA)

TOP VIEW

20

19

18

17

16

15

14

13

12

11

10

9

Vp

Vm BpF BpE BpD BpC BpB BpA Bp9 Bp8 Bp7 Bp6 Bp5 Bp4 Bp3 Bp2 Bp1 Bp0 Vm

Vp

Vm Vm BnF BnE BnD BnC BnB BnA Bn9 Bn8 Bn7 Bn6 Bn5 Bn4 Bn3 Bn2 Bn1 Bn0 Vm Vm

RpF RnF TMon1 Vm Vm Vm Vm Vm Vm Vp Vm Vm Vm Vm Vm Vm Vm TMon2 GnF GpF

RpE RnE Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm GnE GpE

RpD RnD Vm Vm

RpC RnC Vm Vm

RpB RnB Vm Vm

RpA RnA Vm Vm

Rp9 Rn9 Vm Vm

Vm Vm GnD GpD

Vm Vm GnC GpC

Vm Vm GnB GpB

Vm Vm GnA GpA

Vm Vm Gn9 Gp9

Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm

Rp8 Rn8 Vp

Vm

Vp Gn8 Gp8

Rp7 Rn7 Vm Vm

Rp6 Rn6 Vm Vm

Rp5 Rn5 Vm Vm

Rp4 Rn4 Vm Vm

Vm Vm Gn7 Gp7

Vm Vm Gn6 Gp6

Vm Vm Gn5 Gp5

Vm Vm Gn4 Gp4

8

7

6

Rp3 Rn3 R^AZ

GAZ

NC

Vdp Chip Gn2 Gp2

Vm Vm Vm Vm Vm Vm Vm Vm Vm sDo sEn Reset Gn1 Gp1

Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm sDi sClk Vp Gn0 Gp0

NC Gn3 Gp3

5

Rp2 Rn2 Trans RefOL

4

Rp1 Rn1 Cal

Rp0 Rn0 Vp

ROL

Ovl

GOL

BOL

BAZ

3

2

VpS Hs

Vs VmS VpD Hd

Vd VmD VpC Hc

Vc VmC VpB Hb

Vb VmB VpA Ha

Va VmA

Ba RefA

1

Rs

A

Gs

B

Bs RefS Rd

Gd

F

Bd RefD Rc

Gc

K

Bc RefC Rb

Gb

P

Bb RefB Ra

Ga

V

C

D

E

G

H

J

L

M

N

R

T

U

W

Y

= EMPTY LOCATION (UNPOPULATED)

= BALLGRID

FN7362.3

April 3, 2007

2

EL4544

Pin Descriptions

PIN NAME

SOLDER BALL

DESCRIPTION

EQUIVALENT CIRCUIT

Rp0

A3

Red plus input 0

V

P

1.75kΩ

+

–

V

≅ 1.5V

REF

V

M

CIRCUIT 1

Rn0

Rp1

Rn1

Rp2

Rn2

Rp3

Rn3

Rp4

Rn4

Rp5

Rn5

Rp6

Rn6

Rp7

Rn7

Vm

B3

A4

Red minus input 0

Red plus input 1

Red minus input 1

Red plus input 2

Red minus input 2

Red plus input 3

Red minus input 3

Red plus input 4

Red minus input 4

Red plus input 5

Red minus input 5

Red plus input 6

Red minus input 6

Red plus input 7

Red minus input 7

Analog minus supply

Analog plus supply

Red plus input 8

Red minus input 8

Red plus input 9

Red minus input 9

Red plus input 10

Red minus input 10

Red plus input 11

Red minus input 11

Red plus input 12

Red minus input 12

Red plus input 13

Red minus input 13

Red plus input 14

Red minus input 14

Red plus input 15

Red minus input 15

Reference Circuit 1

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

MultipleBalls

C11

A11

B11

A12

B12

A13

B13

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

Vp

Reference Circuit 1

Rp8

Rn8

Rp9

Rn9

RpA

RnA

RpB

RnB

RpC

RnC

RpD

RnD

RpE

RnE

RpF

RnF

FN7362.3

April 3, 2007

3

EL4544

Pin Descriptions (Continued)

PIN NAME

SOLDER BALL

DESCRIPTION

EQUIVALENT CIRCUIT

TMon1

C18

Thermal Monitor 1 has diodes to measure die temperature

V

P

V

M

CIRCUIT 6

Vp

A20

MultipleBalls

C19

Analog plus supply

Analog minus supply

Blue minus input 15

Blue plus input 15

Blue minus input 14

Blue plus input 14

Blue minus input 13

Blue plus input 13

Blue minus input 12

Blue plus input 12

Blue minus input 11

Blue plus input 11

Blue minus input 10

Blue plus input 10

Blue minus input 9

Blue plus input 9

Vm

BnF

BpF

BnE

BpE

BnD

BpD

BnC

BpC

BnB

BpB

BnA

BpA

Bn9

Bp9

Bn8

Bp8

Vp

Reference Circuit 1

C20

D19

D20

E19

E20

F19

F20

G19

G20

H19

H20

J19

J20

K19

Blue minus input 8

Blue plus input 8

K20

K18

Analog plus supply

Analog minus supply

Blue minus input 7

Blue plus input 7

Vm

MultipleBalls

L19

Bn7

Bp7

Bn6

Bp6

Bn5

Bp5

Bn4

Bp4

Bn3

Bp3

Bn2

Bp2

Bn1

Reference Circuit 1

L20

M19

M20

N19

Blue minus input 6

Blue plus input 6

Blue minus input 5

Blue plus input 5

N20

P19

Blue minus input 4

Blue plus input 4

P20

R19

Blue minus input 3

Blue plus input 3

R20

T19

Blue minus input 2

Blue plus input 2

T20

U19

Blue minus input 1

FN7362.3

April 3, 2007

4

EL4544

Pin Descriptions (Continued)

PIN NAME

SOLDER BALL

U20

V19

V20

Vm

DESCRIPTION

EQUIVALENT CIRCUIT

Reference Circuit 1

Bp1

Blue plus input 1

Blue minus input 0

Blue plus input 0

Analog minus supply

Analog plus supply

Bn0

Reference Circuit 1

Bp0

Reference Circuit 1

Vm

Vp

Y20

V18

W18

Y18

W17

Y17

W16

Y16

W15

Y15

W14

Y14

W13

Y13

W12

Y12

W11

Y11

TMon2

GnF

GpF

GnE

GpE

GnD

GpD

GnC

GpC

GnB

GpB

GnA

GpA

Gn9

Gp9

Gn8

Gp8

Vp

Thermal Monitor 2 has diodes to measure die temperature

Green minus input 15

Green plus input 15

Green minus input 14

Green plus input 14

Green minus input 13

Green plus input 13

Green minus input 12

Green plus input 12

Green minus input 11

Green plus input 11

Green minus input 10

Green plus input 10

Green minus input 9

Green plus input 9

Reference Circuit 6

Reference Circuit 1

Green minus input 8

Green plus input 8

V11

Analog plus supply

Vm

MultipleBalls

W10

Y10

W9

Analog minus supply

Green minus input 7

Green plus input 7

Gn7

Gp7

Gn6

Gp6

Gn5

Gp5

Gn4

Gp4

Gn3

Gp3

Gn2

Gp2

Gn1

Gp1

Gn0

Gp0

Reference Circuit 1

Green minus input 6

Green plus input 6

Y9

W8

Green minus input 5

Green plus input 5

Y8

W7

Green minus input 4

Green plus input 4

Y7

W6

Green minus input 3

Green plus input 3

Y6

W5

Green minus input 2

Green plus input 2

Y5

W4

Green minus input 1

Green plus input 1

Y4

W3

Green minus input 0

Green plus input 0

Y3

FN7362.3

April 3, 2007

5

EL4544

Pin Descriptions (Continued)

PIN NAME

SOLDER BALL

DESCRIPTION

EQUIVALENT CIRCUIT

Vm

V3

V5

Analog minus supply

Analog plus supply

Vp

Chip

Chip enable (active low): when "HI" disables all analog except

references; all analog or digital video outputs are in a high

impedance state; all registers hold their data but remain

programmable since the serial interface is left active

V

DP

V

M

CIRCUIT 4

Vdp

U5

V4

Digital logic power supply: nominally at 3V

Reset

Reset (active low): clears all registers in interface and calibration Reference Circuit 4

sections; this causes the chip to standby with all outputs in a high

impedance state

sEn

U4

Serial bus enable (active low): enables the serial bus when "LO"; Reference Circuit 4

latches the current value when transitioning to "HI"

Vp

Vm

V3

Analog plus supply

Analog minus supply

MultipleBalls

sClk

sDo

sDi

U3

T4

T3

Serial bus clock

Reference Circuit 4

Serial bus data output

Serial bus data input

V

DP

V

M

CIRCUIT 5

RefA

VmA

Y1

Y2

Output stage reference level (input) A

Reference Circuit 6

RGB video output stages' minus supply A

V

P

35kΩ

V

M

CIRCUIT 7

Ba

W1

Blue output A

V

P

V

M

CIRCUIT 2

FN7362.3

April 3, 2007

6

EL4544

Pin Descriptions (Continued)

PIN NAME

SOLDER BALL

DESCRIPTION

EQUIVALENT CIRCUIT

Reference Circuit 5

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 7

Reference Circuit 6

Reference Circuit 7

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 7

Reference Circuit 6

Reference Circuit 7

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 7

Reference Circuit 6

Reference Circuit 7

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 7

Reference Circuit 6

Reference Circuit 7

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 5

Reference Circuit 2

Reference Circuit 7

Reference Circuit 6

Va

W2

V1

V2

U1

U2

T1

T2

R1

R2

P1

P2

N1

N2

M1

M2

L1

Vertical sync output A

Ga

Green output A

Ha

Horizontal sync output A

Red output A

Ra

VpA

RefB

VmB

Bb

RGB video output stages' plus supply A

Output stage reference level (input) B

RGB video output stages' minus supply B

Blue output B

Vb

Vertical sync output B

Gb

Green output B

Hb

Horizontal sync output B

Rb

Red output B

VpB

RefC

VmC

Bc

RGB video output stages' plus supply B

Output stage reference level (input) C

RGB video output stages' minus supply C

Blue output C

Vc

L2

Vertical sync output C

Gc

K1

K2

J1

Green output C

Hc

Horizontal sync output C

Rc

Red output C

VpC

RefD

VmD

Bd

J2

RGB video output stages' plus supply C

Output stage reference level (input) D

RGB video output stages' minus supply D

Blue output D

H1

H2

G1

G2

F1

F2

E1

E2

D1

D2

C1

C2

B1

B2

A1

A2

E3

E4

D4

Vd

Vertical sync output D

Gd

Green output D

Hd

Horizontal sync output D

Rd

Red output D

VpD

RefS

VmS

Bs

RGB video output stages' plus supply D

Output stage reference level (input) S

RGB video output stages' minus supply S

Blue output S

Vs

Vertical sync output S

Gs

Green output S

Hs

Horizontal sync output S

Rs

Red output S

VpS

BOL

GOL

ROL

RGB video output stages' plus supply S

Blue overlay input for output group S

Green overlay input for output group S

Red overlay input for output group S

FN7362.3

April 3, 2007

7

EL4544

Pin Descriptions (Continued)

PIN NAME

RefOL

Vm

SOLDER BALL

DESCRIPTION

EQUIVALENT CIRCUIT

D5

MultipleBalls

F4

Overlay inputs' reference level for output group S

Analog minus supply

Reference Circuit 6

BAZ

Blue auto-zero internal calibration level monitor for output group S

V

P

200Ω

V

M

CIRCUIT 3

GAZ

D6

Green auto-zero internal calibration level monitor for output group Reference Circuit 3

S

Vp

RAZ

Vdp

Ovl

C3

Analog plus supply

C6

Red auto zero internal calibration level monitor for output group S Reference Circuit 3

Digital logic power supply: nominally at 3V

U5

D3

Digital input to select whether overlay is active for output group S Reference Circuit 4

Cal

C4

C5

Digital input to calibrate S output group

Digital input to select a transparent overlay for output group S

Analog plus supply

Reference Circuit 4

Trans

Vp

C3

Vm

MultipleBalls

A19

Analog minus supply

Vm

Analog minus supply

Vm

B19, B20, C7, C8, C9, C10,

C12, C13, C14, C15, C16, C17,

D7, D8, D9, D10, D11, D12,

D13, D14, D15, D16, D17, D18,

E17, E18, F3, F6, F7, F8, F9,

F10, F11, F12, F13, F14, F15,

F17, F18, G3, G4, G6, G7, G8,

G9, G10, G11, G12, G13, G14,

G15, G17, G18, H3, H4, H6, H7,

H8, H9, H10, H11, H12, H13,

H14, H15, H17, H18, J3, J4, J6,

J7, J8, J9, J10, J11, J12, J13,

J14, J15, J17, J18, K3, K4, K6,

K7, K8, K9, K10, K11, K12, K13,

K14, K15, K17, L3, L4, L6, L7,

L8, L9, L10, L11, L12, L13, L14,

L15, L17, L18, M3, M4, M6, M7,

M8, M9, M10, M11, M12, M13,

M14, M15, M17, M18, N3, N4,

N6, N7, N8, N9, N10, N11, N12,

N13, N14, N15, N17, N18, P3,

P4, P6, P7, P8, P9, P10, P11,

P12, P13, P14, P15, P17, P18,

R3, R4, R6, R7, R8, R9, R10,

R11, R12, R13, R1, R15, R17,

R18, T17, T18, U7, U8, U9, U10,

U11, U12, U13, U14, U15, U16,

U17, U18, V7, V8, V9, V10, V12,

V13, V14, V15, V16, V17, W19,

W20, Y19

N/C

U6, V6

Not connected; may be grounded

FN7362.3

April 3, 2007

8

EL4544

Absolute Maximum Ratings (T = +25°C)

A

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C

Recommended Operating Temperature . . . . . . . . . .-40°C to +85°C

SA

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

S

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V

SD

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

Electrical Specifications

V

= 5V, V = 3.3V, Gain = 2, R = 150Ω, C = 2.7pF, T = +25°C.

SA

SD

L

A

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

SUPPLY CHARACTERISTICS

V

Recommended Analog Supply Voltage

Recommended Digital Supply Voltage

Digital Supply Current

4.75

2.4

5.0

3.3

3

5.25

3.6

10

V

SA

SD

V

I

mA

dB

SD

SA

Analog Supply Current

Enabled - no load, all amplifiers enabled

Disabled

685

33

790

50

PSRR

Power Supply Rejection Ratio

4.75V to 5.25V

40

CHARACTERISTICS OF DIFFERENTIAL INPUTS

CMRR Input Common Mode Rejection Ratio

0V to 1.5V

45

66

dB

A

Gain Accuracy for A, B, C, D, S Channels Range of Deviation from gain of 2 (excluding

overlay)

1.85

2.0

2.15

V

Input Referred Voltage Noise

Input Referred Offset Voltage

A

= +2

40

0

nV/√Hz

N

V

Includes muxes and output amps; A, B, C, D

channels

-80

-10

80

12

mV

OS

S channel in auto-calibration mode

5

mV

V

Maximum Recommended Input Range

Input Capacitance

V

SA

IN

C

R

2

pF

Ω

IN

Input Resistance, Single-ended

Input Biasing Voltage

1100

1.49

1320

1.53

1550

1.57

IN

V

INSET

OVERLAY INPUT CHARACTERISTICS

Input Referred Offset Voltage

OVERLAY SWITCHING CHARACTERISTICS

V

S channel overlay inputs at A = 2

V

-10

5

12

mV

ns

OS

P

Pixel Mux Aperture of Uncertainty

Gain Accuracy for S Channel

5% setting for max signal charge

S channel overlay input

10

APERTURE

A

V

OUTPUT CHARACTERISTICS

Output

Impedance

Enabled

Disabled

100

10

mΩ

MΩ

V

Maximum Recommended Output Range

Output Current

0

3.3

OUT

I

Short-circuit (5Ω)

60

mA

OUT

FN7362.3

April 3, 2007

9

EL4544

Electrical Specifications

V

= 5V, V = 3.3V, Gain = 2, R = 150Ω, C = 2.7pF, T = +25°C. (Continued)

SA

SD

L

A

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

AC PERFORMANCE

SR

Slew Rate

2V

P-P

symmetrical, R = 150Ω, A = 2,

800

V/µs

L

V

guaranteed by design

BW

-3dB Bandwidth

-3dB, 200mV , load of 150Ω

300

60

MHz

ns

P-P

0.1dB Bandwidth

1% Settling Time

0.1dB, 200mV , load of 150Ω

P-P

Settling Time

Crosstalk

2V step, load of 150Ω

10

O

Hostile Crosstalk Between any 2

Channels

100MHz

-70

dB

Worst Case Hostile Crosstalk One

Channel Affected by all Other Channels

Running the Same Signal

100MHz

-50

dB

FN7362.3

April 3, 2007

10

EL4544

I/O Block Diagram of Video Signals

R0

OUTPUT GAIN

SELECTION

INPUT GAIN

SELECTION

16x2:1

MUX

4x5 XPOINT MUX

Ai

Bi

Ci

Di

Ax

Bx

Cx

R

G

B

R

G

B

Ai

2

R15

R0

OutA =

(Ra, Ga, Ba + Ha, Va)

2

G15

H

V

H

V

L

SYNC

B15

16x2:1

MUX

R

G

B

R

G

B

Bi

2

R15

R0

OutB =

(Rb, Gb, Bb + Hb, Vb)

G15

H

V

H

V

L

SYNC

B15

16x2:1

MUX

R

G

B

R

G

B

Ci

2

R15

R0

OutC =

(Rc, Gc, Bc + Hc, Vc)

G15

H

V

H

V

L

B15

16x2:1

MUX

Dx

R

G

B

R

G

B

TRANSPARENT

Di

2

OVERLAY

CALIBRATE/HOLD

2:1 PIXEL MUX

R15

OutD =

(Rd, Gd, Bd + Hd, Vd)

Ro

Go

G15

H

V

H

L

2

Rso

Gso

Bso

B15

V

Bo

Rs

Sx

Rs

Gs

Bs

Hs

Vs

Gs

Bs

NOTES:

1. Each output group is a 5 element vector

(R, G, B + H, V)

OutS = (Rs, Gs, Bs, Hs, Vs)

2. Each input group is a 3 element vector

(R, G, B)

L

Hs

Vs

3. All outputs drive back terminated 75Ω cable

L

OutSO = (Rso, Gso, Bs, Hs, Vs)

SDI (SERIAL DATA INPUT)

SCLK (SERIAL CLOCK)

SDO (SERIAL DATA OUTPUT)

CONTROL REGISTERS

SEN (SERIAL CLOCK ENABLE/LATCH)

RESET (CLEARS ALL REGISTERS)

WHEN HI, DATA IS CLOCKED IN, WHEN ↓ LO, DATA IS LATCHED TO ENABLE SELECTION

FN7362.3

April 3, 2007

11

EL4544

I/O Block Diagram of Video Signals with Power Supplies and References

R0

16x2:1

MUX

4x5 XPOINT MUX

VpA

Ai

Bi

Ci

Di

Ax

Bx

Cx

R

G

B

R

G

B

Ai

2

R15

R0

OutA =

(Ra, Ga, Ba + Ha, Va)

G15

H

V

H

V

L

SYNC

B15

RefB

VmA

VpB

16x2:1

MUX

R

G

B

R

G

B

Bi

2

R15

R0

OutB =

(Rb, Gb, Bb + Hb, Vb)

G15

H

V

H

V

L

B15

RefB

VmB

VpC

16x2:1

MUX

R

G

B

R

G

B

Ci

2

R15

R0

OutC =

(Rc, Gc, Bc + Hc, Vc)

G15

H

V

H

V

L

B15

RefC

VmC

VpD

16x2:1

MUX

Dx

R

G

B

R

G

B

Di

2

TRANSPARENT

OVERLAY

CALIBRATE/HOLD

VpS

R15

OutD =

(Rd, Gd, Bd + Hd, Vd)

Ro

Go

G15

H

V

H

V

L

B15

2

Rso

Gso

Bso

RefD

VmD

Bo

Rs

Sx

Rs

Gs

Bs

Hs

Vs

NOTES:

Gs

Bs

1. Each output group is a 5 element vector

(R, G, B + H, V)

RefS

VmS

OutS = (Rs, Gs, Bs, Hs, Vs)

2. Each input group is a 3 element vector

(R, G, B)

2:1 PIXEL MUX

L

Hs

Vs

3. All outputs drive back terminated 75Ω cable

L

OutSO = (Rso, Gso, Bs, Hs, Vs)

SDI (SERIAL DATA INPUT)

SCLK (SERIAL CLOCK)

SDO (SERIAL DATA OUTPUT)

CONTROL REGISTERS

SEN (SERIAL CLOCK ENABLE/LATCH)

RESET (CLEARS ALL REGISTERS)

WHEN HI, DATA IS CLOCKED IN, WHEN ↓ LO, DATA IS LATCHED TO ENABLE SELECTION

FN7362.3

April 3, 2007

12

EL4544

Serial Bus Interface Architecture

1-SHOT PULSE

GENERATOR

LOAD

SEN

4 BIT

SELECTOR

L

F3

F2

F1

F0

0

L

C

L

R

S

O

A

D

0

d

0

3

2

1

L

m3 m2 m1 m0

m

L

O

A

D

C

L

R

S

m

L

M3 M2 M1 M0

d

0

3

2

1

L

3

L

2

L

1

L

0

03

02

01

00

F

L

O

A

D

C

L

R

S

F

03

02

01

00

b3 b2 b1 b0

d

RESET

ADDRESS

DATA

SDO

Q

D

A

D

0

SDI

3

2

1

0

3

2

1

8 BIT SHIFT REGISTER

SCLK

SEN

RESET

CLEAR

NOTE: The selector has 16 outputs, connected to 16 AND gates, connected to 16 4-bit latches.

Rising edge of SEN triggers the load one-shot.

FN7362.3

April 3, 2007

13

EL4544

Serial Bus Interface Timing Diagram

t(SEN)

IDLE

WRITE TO REGISTER OF EL4544 (ADDRESS = XXXX)

SEN

t(SCLK)HI

t(SCLK)LO

(1/F)*SCLK

SCLK

SDI

8

td(SEN)

MSB

LSB

MSB

LSB

A

D

0

3

2

1

0

3

2

1

td(SCLK)

START

t(SDI)

SETUP

t(SDI)

HOLD

CURRENT (m) REGISTER

ADDRESS (4 BITS)

CURRENT (m) INPUT

DATA (4 BITS)

MSB

LSB

MSB

LSB

D

A

D

0

3

2

1

0

3

2

1

PREVIOUS... (m-2) PREVIOUS (m-1) ADDRESS (4 BITS)

ADDRESS

PREVIOUS (m-1) DATA (4 BITS)

NOTE: Readback of the serial bus register can be done as follows: After SEN is taken low, latching data, and before

writing the next word, the data in the register can be read back by clocking out 8 bits before writing in the next word.

FN7362.3

April 3, 2007

14

EL4544

Serial Bus Interface Control Table

HEX

ADDRESS

DATA

ADDRESS

CODE

FUNCTION

A3

0

A2

0

A1

0

A0

0

D3

S3

D2

S2

D1

S1

D0

S0

0

1

2

3

4

5

Ai Input Mux: Select Input of Input Mux Ai

Bi Input Mux: Select Input of Input Mux Bi

Ci Input Mux: Select Input of Input Mux Ci

Di Input Mux: Select Input of Input Mux Di

Enable Any of the 4 Input Muxes: Di/Ci/Bi/Ai

0

1

S3

S2

S1

S0

0

1

0

S3

S2

S1

S0

0

1

S3

S2

S1

S0

0

1

0

EnDi

TiS3

EnCi

TiS2

EnBi

TiS1

EnAi

TiS0

Ti Input Test Mux: Select Which Input Group is

0

1

0

1

Connected to Input Test Mux

6

7

8

Enable Test Muxes: Input and Output

0

1

0

1

0

1

0

EnTi

ToS2

ToS1

ToS0

Enable Sync Detectors for Di/Ci/Bi/Ai

EnDSync EnCSync EnBSync EnASync

Ax Crosspoint Mux: Enable/Gain =

2or1/Select Input (2Bits)

En

A =2/

V

not1

S1

S0

9

A

B

C

Bx Crosspoint Mux: Enable/Gain = 2or1/

Select Input (2Bits)

1

0

1

0

1

0

1

0

1

0

A =2/

V

not1

Cx Crosspoint Mux: Enable/Gain = 2or1/

Select Input (2Bits)

A =2/

V

not1

Dx Crosspoint Mux: Enable/Gain = 2or1/

Select Input (2Bits)

A =2/

V

not1

Sx Crosspoint Mux: Enable/Gain = 2or1/

A =2/

V

Select Input (2Bits)

not1

D

E

Sync, Overlay, and Calibration Modes

1

0

1

0

X

Trans

Toggle

AvBi=2

Autocal

AvDi=2

Gain for: Di/Ci/Bi/Ai

Set to HI for gain of 2

Set to LO for gain of 1

AvDi=2

AvCi=2

F

No Operation

1

2

1

3

1

4

X

5

X

6

X

7

X

8

Order bits are loaded

FN7362.3

April 3, 2007

15

EL4544

Typical Performance Curves

DIFFERENTIAL

INPUTS

DIFFERENTIAL

INPUTS

C =10pF

L

R =1kΩ

L

R =150Ω

C =0pF

L

C =6.8pF

L

A =2

V

R =500Ω

L

C =4.7pF

L

C =2.7pF

L

R =300Ω

L

C =0pF

L

R =150Ω

L

FIGURE 1. FREQUENCY FOR VARIOUS R

FIGURE 2. FREQUENCY FOR VARIOUS C

LOAD

5

DIFFERENTIAL

DIFFERENTIAL INPUTS

INPUTS

A IN=1

A OUT=1

V

OUTPUT CHANNELS=R, B, G

V

A IN=1

V

3

1

3

1

BLUE

RED

A OUT=1

V

-1

-3

-5

-1

-3

-5

GREEN

INPUTS 0-15

OUT Ax

TYPICAL

100k

1M

10M

FREQUENCY (Hz)

100M

1G

100k

1M

10M

FREQUENCY (Hz)

100M

500M

FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS INPUT

CHANNELS

FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS OUTPUT

COLOR CHANNELS

5

A IN=1

V

A IN=1

V

A OUT=1

V

A OUT=1

V

3

1

3

1

-1

-3

-5

-1

-3

-5

INPUTS 0-15

OUT Ax

TYPICAL

INPUTS 0-15

OUT Ax

TYPICAL

100k

1M

10M

FREQUENCY (Hz)

100M

1G

100k

1M

10M

FREQUENCY (Hz)

100M

500M

FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS NON

INVERTING INPUTS

FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS INVERTING

INPUTS

FN7362.3

April 3, 2007

16

EL4544

Typical Performance Curves (Continued)

5

3

5

INVERTING INPUTS

NON-INVERTING INPUTS

3

1

A IN=1, A OUT=2

V V

-1

-3

V

-1

-3

A IN=2, A OUT=2

V V

V

A IN=1, A OUT=1

V V

V

A IN=2, A OUT=1

V V

V

-5

100k

-5

100k

1M

10M

FREQUENCY (Hz)

100M

1G

1M

10M

FREQUENCY (Hz)

100M

1G

FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS GAINS

FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS GAINS

5

3

ALL OUTPUT MUXes

ENABLED OR DISABLED

NO EFFECT

3

A IN=2, A OUT=1

V

1

-1

-3

-5

1

-1

-3

A IN=1, A OUT=1

V

A IN=1, A OUT=2

V

(-0.1dB 180MHz)

A IN=2, A OUT=2

V

(-0.1dB 150MHz)

-5

100k

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS GAIN

COMBINATIONS

FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS INPUT MUX

LOADING

5

A IN=1

V

Sx OUTPUT CHANNEL

A OUT=1

V

IN OVERLAY MODE

3

1

3

GPO

1

GAIN=1

GNO

-1

-3

-5

-1

-3

GAIN=2

-5

100k

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 11. GAIN vs FREQUENCY DIFFERENTIAL INPUT

COMPARISON

FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS GAINS

FN7362.3

April 3, 2007

17

EL4544

Typical Performance Curves (Continued)

5

3

INPUT=OVERLAY

OUTPUT=Sx

Sx OUTPUT CHANNEL

IN OVERLAY MODE

A IN=2

A IN=1

V

3

1

AUTO CAL DISABLED

-3dB 390MHz

AUTO CAL DISABLED

-3dB 322MHz

1

-1

-3

-5

-1

-3

-5

AUTO CAL ENABLED

-3dB 192MHz

100k

1M

10M

100M

1G

100k

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 13. GAIN vs FREQUENCY FOR Sx CHANNEL

FUNCTIONS

FIGURE 14. GAIN vs FREQUENCY FOR Sx CHANNEL

FUNCTIONS

5

INPUT=OVERLAY

OUTPUT=Sx

AUTO CAL=DISABLED

AUTO CAL=ENABLED

3

A IN=2

V

A IN=2

V

3dB=390MHz

3dB 176MHz

1

-1

-3

1

-1

-3

A IN=A OUT=1

V V

V

3dB 322MHz

3dB 162MHz

-5

100k

-5

100k

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS GAINS

FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS GAINS

7

-30

A TOTAL=4

V

V =VARIOUS

A

4.43V

V =3.0V

D

EF

5

3

-50

-70

4.45V

4.47V

4.5V

4.55V

4.6V

R

OUT=1.5V

A IN=2

V

4.7V

5V

1

-90

-1

-3

-110

-130

4.42V

100k

1M

10M

FREQUENCY (Hz)

100M

500M

100k

1M

10M

100M

500M

FREQUENCY (Hz)

FIGURE 17. PEAKING FOR VARIOUS POWER SUPPLY

SETTINGS

FIGURE 18. INPUT TO OUTPUT ISOLATION (DISABLED)

FN7362.3

April 3, 2007

18

EL4544

Typical Performance Curves (Continued)

-30

-50

A IN=2

INPUT SIGNAL

-20dBm

Ax IN

Bx LISTEN

BROADCAST

V

A TOTAL=4

V

-50

-70

A IN=2

V

Ax IN

Bx LISTEN

Ax ON Bx ON

-70

A IN=1

V

Ax IN

Bx LISTEN

Ax Cx Dx ON

-90

Ax IN

Bx LISTEN

ALL OTHERS OFF

-110

-130

-110

-130

100k

1M

10M

FREQUENCY (Hz)

100M

500M

100k

1M

10M

FREQUENCY (Hz)

100M

500M

FIGURE 19. CROSSTALK FOR VARIOUS GAINS

FIGURE 20. CROSSTALK FOR VARIOUS BROADCAST MODES

25

15

5

25

15

5

-5

-15

-25

100k

-25

100k

1M

10M

100M

500M

1M

10M

100M

500M

FREQUENCY (Hz)

FIGURE 21. GROUP DELAY FOR OUTPUT

CHANNELS A, B, C, D, S

FIGURE 22. GROUP DELAY FOR OVERLAY MODE

10

300

A IN=2

V

A IN=2

V

-10

-30

-50

-70

-90

200

150

100

50

0

10k

100k

1M

10M

100M

500M

100k

1M

10M

100M

FREQUENCY (Hz)

FIGURE 23. CMRR

FIGURE 24. OUTPUT IMPEDANCE

FN7362.3

April 3, 2007

19

EL4544

Typical Performance Curves (Continued)

700

600

500

400

300

200

100

0

10k

1K

A IN=2

V

100

10

100

1K

10k

100k

1M

10M

100M

3

3.5

4

4.5

5

5.5

6

6.5

7

FREQUENCY (Hz)

SUPPLY VOLTAGE (VD) VOLTS

FIGURE 26. SLEW RATE vs SUPPLY (VD)

FIGURE 25. VOLTAGE NOISE vs FREQUENCY

A IN=1

V

GPO

A OUT=1

OUTPUT

INPUT

A IN=1

V

A OUT=1

V

GNO

TIME (10ns/DIV)

FIGURE 27. SMALL SIGNAL NEGATIVE PULSE RESPONSE

FIGURE 28. SMALL SIGNAL POSITIVE PULSE RESPONSE

OUTPUT

INPUT

A IN=1

V

GNO

V

INPUT

A OUT=1

V

GPO

TIME (10ns/DIV)

FIGURE 29. LARGE SIGNAL NEGATIVE PULSE RESPONSE

FIGURE 30. LARGE SIGNAL POSITIVE PULSE RESPONSE

FN7362.3

April 3, 2007

20

EL4544

Typical Performance Curves (Continued)

ENABLE PULSE

(STEP)

20ns

940ns

ENABLE PULSE

(STEP)

GATED OUTPUT

SIGNAL

GATED OUTPUT

SIGNAL

TIME (1.0µs/DIV)

TIME (1ns/DIV)

FIGURE 31. ENABLE TIME

FIGURE 32. DISABLE TIME

600

500

400

300

200

100

0

400

350

300

250

200

150

100

OUTPUT MUXES 1 - 5

ENABLED

INPUT MUXES 1 - 4

ENABLED

50

Va=5.0V Vd=3.0V Ref^OL=1.5V

Va=5.0V Vd=3.0V RefOL=1.5V

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

NUMBER OF MUXES ENABLED 1 -5 (OUTPUT MUXES)

5 - 9 (INPUT MUXES)

NUMBER OF OUTPUT MUXES ENABLED

FIGURE 33. POWER SUPPLY CURRENT AS FUNCTION OF

OUTPUT MUXES ENABLED - ALL INPUT MUXES

DISABLED

FIGURE 34. POWER SUPPLY CURRENT AS FUNCTION OF

INPUT AND OUTPUT MUXES ENABLED

600

550

500

450

400

300

250

200

150

100

50

350

Va=5.0V Vd=3.0V RefOL=1.5V

0

300

1

1.5

2

2.5

3

3.5

4

0

1

2

3

4

NUMBER OF INPUT MUXES ENABLED

FIGURE 35. POWER SUPPLY CURRENT AS FUNCTION OF

INPUT MUXES ENABLED - ALL OUTPUT MUXES

ENABLED

FIGURE 36. POWER SUPPLY CURRENT AS FUNCTION OF

INPUT MUXES ENABLED - ALL OUTPUT MUXES

DISABLED

FN7362.3

April 3, 2007

21

EL4544

Typical Performance Curves (Continued)

120

100

500

450

400

350

300

250

200

150

100

50

80

60

40

20

0

MAIN VOLTAGE SUPPLY (Va)

Vd=3.0V Ref^OL=1.5V

0

2

2.5

3

3.5

4

4.5

5

5.5

0

0.5

1

1.5

2

2.5

3

SUPPLY VOLTAGE (V)

DIGITAL SUPPLY VOLTAGE (V)

FIGURE 37. ANALOG CURRENT vs DIGITAL SUPPLY

VOLTAGE

FIGURE 38. SUPPLY CURRENT VERSUS SUPPLY VOLTAGE

BASE LINE IDLE - ALL INPUTS AND OUTPUTS

DISABLED

40

35

40

A TOTAL=4

V

35

30

25

20

15

10

5

A TOTAL=4

V

A IN=2

V

30

25

20

15

10

5

A IN=2

V

A IN=1

V

A IN=1

V

0

1.0

10.0

100.0

1.0

10.0

FREQUENCY (MHz)

100.0

FREQUENCY (MHz)

FIGURE 39. THIRD-ORDER INTERCEPT POINT vs

FREQUENCY GREEN CHANNEL

FIGURE 40. THIRD-ORDER INTERCEPT POINT vs

FREQUENCY BLUE CHANNEL

0

40

A TOTAL=4

V

IP3= 36.2

A TOTAL=4

-10

-20

f1=10MHz

V

35

30

25

20

15

10

5

f2=10.004MHz

f1

f2

A IN=2

V

-30

-40

A IN=1

V

-50

-60

2f1-f2

2f2-f1

-70

-80

-90

-100

-110

0

9.995 9.997 9.999 10.001 10.003 10.005 10.007 10.009

1.0

10.0

FREQUENCY (MHz)

100.0

FREQUENCY (MHz)

FIGURE 41. THIRD-ORDER INTERCEPT POINT vs

FREQUENCY RED CHANNEL

FIGURE 42. IP3 A TOTAL = 4 BLUE CHANNEL

V

FN7362.3

April 3, 2007

22

EL4544

Typical Performance Curves (Continued)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

A IN=2

f1=10MHz

f2=10.004MHz

A IN=1

V

IP3=33.9

V

IP3 = 24.5

-10

-20

f1=10MHz

f2=10.004MHz

f1

-30

f1

f2

-40

-50

-60

-70

2f2-f1

2f1-f2

2f2-f1

-80

2f1-f2

-90

-100

-110

9.995 9.997 9.999 10.001 10.003 10.005 10.007 10.009

FREQUENCY (MHz)

FIGURE 44. IP3 A IN = 1 BLUE CHANNEL

V

FIGURE 43. IP3 A IN = 2 BLUE CHANNEL

V

groups has an independent reference pin (RefA, RefB,

RefC, RefD, and RefS) that allows the user to program the

reference level that corresponds to a zero voltage differential

input.

Functional Overview

Overall Functionality

The EL4544 is a video crosspoint switch that has 16 (RGB

differential) input channels (with H and V sync embedded in

their common-modes) which connect via an internal

crosspoint mux to 5 (RGB + HV) single-ended output

channels. The 5th output group has enhanced features that

include: a pixel-by-pixel overlay mux and auto-calibrated

offset cancellation. All analog and digital outputs have a

high-impedance state, allowing several EL4544 to share the

same output connections.

Analog and Digital Video Outputs

All analog outputs (A, B, C, D, and S) have a signal range

from 0V to 3.5V and are capable of driving the 150Ω load

presented by a terminated video cable. The H and V sync

outputs and all other digital I/O are compatible with 3V

operation; their signal swings are determined by connecting

the digital supply pin Vdp to a 3V source.

How to Configure the Analog Video Outputs to

Swing to 0V

16 RGB Differential Video Inputs with Encoded

Sync

The RGB analog outputs of the A, B, C, D, and S output

groups are all capable of a range of swing that reaches the

negative supply pin Vm = 0V. However, since the EL4544

has no internal supply connections, its single-ended outputs

run out of bandwidth, slew rate, and linearity below 0.5V. If

accurate wide band performance below 0.5V is required,

add external pulldown resistors between each analog output

and an external -5V supply.

For each of the 16 RGB groups of differential video inputs,

horizontal and vertical sync are encoded as a combination of

the common modes for each RGB group. Each of these

differential input pins has a single-ended signal range that

spans the entire 0V to 5V supply range. The embedded sync

signals are provided by the EL4543 Triple Differential

Twisted Pair Driver IC.

Overall Analog Signal Flow

This will keep the output stage biased. Values between 3kΩ

to 1kΩ are suggested. The lower the selected resistance, the

wider the bandwidth will be at 0V, but lower external

resistance will increase overall IC power dissipation

significantly since these resistors are loading their respective

output stages.

There are four independent internal input multiplexors

represented as Ai, Bi, Ci, and Di in the block diagram and

serial bus interface control table (hexa-decimal addresses

0h, 1h, 2h, 3h). These muxes convert the selected RGB

differential input signal to single-ended RGB and extract H

and V sync. The five output crosspoint multiplexors

represented as Ax, Bx, Cx, Dx, and Sx, can independently

select from the four internal (RGBHV) signal groups Ai, Bi,

Ci, and Di by programming the hexadecimal serial bus

addresses 8h, 9h, Ah, Bh, and Ch. There are five RGBHV

single-ended output signal groups labelled A, B, C, D, and S

which buffer signals from the corresponding crosspoint

outputs Ax, Bx, Cx, Dx, and Sx. Each of these output

Operating the S Output Group Near Ground

The S output group has one additional consideration to

cover configurations where the output signals and the output

reference pin RefS are operated below 0.5V. Under these

circumstances, each of the three auto-zero monitoring pins

RAZ, GAZ, and BAZ, require an external 10kΩ resistor

FN7362.3

April 3, 2007

23

EL4544

connecting each to an external -5V supply. This keeps the

auto-zero circuitry active all the way down to ground.

calibration. If Toggle mode is inactive, the user must

individually calibrate both the overlay and non-overlay

("thru") output states by selecting the between them and

running calibration separately for both of the input

conditions. Changing the input selections by re-

Switchable Video Output Group Has Overlay

Capability and Offset Cancellation

The S group of output signals have an overlay switch that

allows single-ended inputs ROL, GOL, and BOL, to be

inserted on a pixel-by-pixel basis. The pin RefOL allows the

user to program the overlay input (reference) level that

produces an output voltage equal to the output reference pin

RefS. The S group of video outputs has an Auto-Calibration

mode which can null out offsets through the entire selected

signal path from its inputs to its outputs. (It is usually

triggered during the front or back porch of video when the

input signal is known to be at Black Level.)

programming the crosspoint to another input path or by

changing the overlay mode (transparent/opaque), requires

refreshing of this calibration. Ideally, the calibration is

refreshed once per line of video. The drift during a line of

video is negligible. (On the lab bench, using manual control,

a drift rate on the order of 0.2mV/sec will be observed.)

Toggle Mode Automatically Supervises the

Calibration Cycles

The purpose of Toggle mode is to automatically alternate

between calibrating the overlay and calibrating the "thru"

paths to the S Output group. The Toggle mode assumes that

overlays never exist outside of the video screen (that overlay

only occurs during active video). When using the Toggle

mode, the overlay function must be inactive during and

around sync. When Toggle mode is active and the overlay

switch is disabled, the EL4544 will automatically toggle

between "thru" and overlay selections for alternate pulsing of

the calibrate signal. Thus, every alternate calibrate pulse will

override the selected "thru" state of the overlay switch,

perform an auto-zero function, and then return the overlay

switch back to its original "thru" position. This is true if the

programming Bit D1 in Register D (labelled Toggle) of the

Serial Interface is programmed to a logical "1". Whenever

the IC is reset by momentarily pulling the Reset pin "LO", the

Toggle mode is initialized such that the first path calibrated is

the overlay path. The next calibration cycle will automatically

calibrate the "thru" path.

Transparent vs Opaque Overlays

The overlay input for the S group is directly selected by the

Overlay control pin Ovl. Two types of overlay are possible.

The simplest overlay alternates between the dedicated

overlay input and the "thru" input (that has been selected by

the cross-point multiplexor). The "transparent" overlay mode

is different from the standard overlay mode in that it presents

the average of the overlay input and the "thru" input signal

during overlay. The transparent mode is selected either by

driving the Trans pin low or by programming bit D2 in

Register D of the Serial Interface to a logical "1".

Serial Interface Control of the Auto-Calibration

Feature

Programming bit D0 in Register D of the Serial Interface to a

logical "1" activates the "Auto-Calibration" Mode which

allows offsets from all inputs to the S group to be nulled-out

via a calibration sequence. The programming Bit D1 in

Register D of the Serial Interface is called Toggle. It allows

for two modes of auto-calibration. If Toggle is programmed to

a logical "0", Toggle mode is inactive. The auto-calibration

cycle must be executed separately for both input groups (the

overlay and the through signal groups).

Incorrect Use of the Toggle Mode

If the overlay is selected during auto-calibration with the

Toggle mode active, the "thru" path will never be calibrated.

Only the overlay gets calibrated in this configuration.

Integrated Die Temperature Probes

What Happens During an Auto-Calibration Cycle

Thermal monitoring pins TMon1 and TMon2 allow the user

to effectively monitor the die temperature by lightly forward

biasing internal diodes and measuring their forward voltage

drop. Since these diodes will have a -2mV/°C tempco, they

can be an effective means of evaluating the thermal

management of the user's application board and may even

be configured to provide a thermally-triggered shutdown. To

implement this feature, pull either of these pins below the

negative supply with precision current source of 10µA to

100µA. Measure the forward drop at room temperature with

the chip disabled. During operation, every 1°C rise in

temperature will produce a 2mV drop in the forward voltage.

The auto-calibration (auto-zero) feature only applies to the S

group of outputs. An auto-calibration cycle works as follows

for either the overlay input or a selected "thru" input from the

cross-point: During any time when the input signal is known

to be at a "zero-level" ("zero-level" is a differential-zero input

signal for any of the 16-RGB differential inputs or when the

pin voltages to the overlay inputs ROL = GOL = BOL are all

equal to RefOL), setting the calibration pin Cal to a logical

"LO" activates the sample phase of auto-calibration and

forces the analog outputs to be equal to the reference

voltage of pin RefS. When pin Cal is brought back to a

logical "HI", the calibration is held until the next calibration

cycle, and the S group will accurately convey the video

signal with low offsets. A small hold-step (≤1mV) can be

observed whenever the calibration signal is released. Each

subsequent activation of the sampling phase refreshes the

Some Tips on the Most Effective Programming of

the EL4544

The video inputs present a 1.75kΩ single ended and a 3.5kΩ

differential load to an incoming video signal. Since this load

FN7362.3

April 3, 2007

24

EL4544

is in parallel with the external termination network, it has a

consistent effect on the system gain. To maintain this

consistency, it is inadvisable to program more than one input

stage (Ai, Bi, Ci, or Di) to "look" at any given video input

(RGB0, RGB1, …, RGBF) since each activated input stage

puts an additional parallel load of 3.5kΩ onto the selected

input. When programming the serial interface this is simply

expressed as: Avoid programming the same value into the

four data registers (for Ai, Bi, Ci, and Di) at hex addresses

0H, 1H, 2H, and 3H. They should all have unique values.

This is important since if any inputs are selected more than

once, their gains will mismatch an input that has only been

selected once.

The EL4544 decodes the common-mode signals into H and

V syncs as follows: Horizontal Sync is TRUE when the

Blue_Common_Mode voltage is greater than the

Average_of_Red_and_Green_Common_Mode voltage.

Vertical Sync is TRUE when the

Average_of_Red_and_Blue_Common_Mode voltage is

greater than the Green_Common_Mode voltage. The sync

comparators have an internal symmetrical hysteresis that is

less than ±50mV. Timing skews between comparators under

all conditions are less than one pixel. The comparators have

an input common mode that allows for operation at least 1V

from the negative supplies and at least 1.5V from the

positive supplies.

If one wishes to broadcast the same signal to multiple output

channels, this can easily be accomplished without violating

the advice of the previous paragraph. Select the input that

needs to be broadcast using any one of the four input

selectors (Ai, Bi, Ci, or Di), then have any of up to five of the

output stages (Ax, Bx, Cx, Dx, Sx) point to the input stage

that is pointing to the desired input signal. These are

selected using hex 8H, 9H, AH, BH, and CH. Now the

EL4544 is broadcasting a single video source to multiple

outputs without excessively loading down the selected input.

Logic Levels for Serial Interface and Control Logic

TABLE 2. INPUT LOGIC THRESHOLD (+5V SUPPLY)

V

, max

0.8V

2V

LO

V

, min

HI

Sync Decoding of EL4544

The EL4544 is designed to receive and decode Horizontal

and Vertical Sync signals that have been encoded as

common-mode signals of the Red, Green, and Blue Video

inputs. The EL4543 provides this encoding as shown in

Table 1.

TABLE 1. SYNC SIGNAL ENCODING

COMMON COMMON COMMON

MODE A

(RED)

MODE B

(GREEN)

MODE C

(BLUE)

H

V

Low

High

Low

High

3.0

2.5

2.0

2.5

2.0

3.0

2.0

2.5

2.0

2.5

3.0

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7362.3

April 3, 2007

25


型号：	EL4544_07
厂家：	Intersil
描述：	Triple 16x5 Differential Crosspoint Switch Capable of Operation in Single-Ended or Differential Input Modes 工作在单端或差分输入模式三重16x5差分交叉点开关，能够开关
文件：	总26页 (文件大小：783K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EL4544_07 [INTERSIL]

相关型号：

EL4544_0712

EL4581

EL4581C

EL4581CN

EL4581CN

EL4581CS

EL4581CS

EL4581CS-T13

EL4581CSZ

EL4581_08

EL4581_10

EL4583