EL5174IS-T7 [INTERSIL]
550MHz Differential Twisted-Pair Drivers; 550MHz的差分双绞线驱动器
| 型号： | EL5174IS-T7 |
| 厂家： | 
Intersil |
| 描述： | 550MHz Differential Twisted-Pair Drivers |
| 文件： | 总15页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5174, EL5374
®
Data Sheet
August 8, 2005
FN7313.5
550MHz Differential Twisted-Pair Drivers
Features
The EL5174 and EL5374 are single and triple high
bandwidth amplifiers with an output in differential form. They
are primarily targeted for applications such as driving
twisted-pair lines in component video applications. The
inputs can be in either single-ended or differential form but
the outputs are always in differential form.
• Fully differential inputs, outputs, and feedback
• Differential input range ±2.3V
• 550MHz 3dB bandwidth
• 1100V/µs slew rate
• Low distortion at 5MHz
On the EL5174 and EL5374, two feedback inputs provide
the user with the ability to set the gain of each device (stable
at minimum gain of one). For a fixed gain of two, please see
EL5173 and EL5373.
• Single 5V or dual ±5V supplies
• 60mA maximum output current
• Low power - 12.5mA per channel
• Pb-free plus anneal available (RoHS compliant)
The output common mode level for each channel is set by
the associated REF pin, which have a -3dB bandwidth of
over 110MHz. Generally, these pins are grounded but can be
tied to any voltage reference.
Applications
• Twisted-pair driver
All outputs are short circuit protected to withstand temporary
overload condition.
• Differential line driver
• VGA over twisted-pair
The EL5174 is available in an 8-pin SO package and
EL5374 is available in a 28-pin QSOP package. All specified
for operation over the full -40°C to +85°C temperature range.
• ADSL/HDSL driver
• Single ended to differential amplification
• Transmission of analog signals in a noisy environment
Pinouts
EL5174
EL5374
(28-PIN QSOP)
TOP VIEW
(8-PIN SO)
TOP VIEW
FBP
IN+
1
2
3
4
8
7
6
5
OUT+
VS-
NC
INP1
INN1
1
2
3
28 OUT1
27 FBP1
26 FBN1
25 OUT1B
24 VSP
+
-
+
-
REF
FBN
VS+
OUT-
REF1 4
NC
INP2
INN2
REF2
NC
5
6
7
8
9
23 VSN
22 OUT2
21 FBP2
20 FBN2
19 OUT2B
18 OUT3
17 FBP3
16 FBN3
15 OUT3B
+
-
INP3 10
INN3 11
REF3 12
NC 13
+
-
EN 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003 - 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
EL5174, EL5374
Ordering Information
TAPE &
REEL
TAPE &
REEL
PART NUMBER
EL5174IS
PACKAGE
8-Pin SO
8-Pin SO
8-Pin SO
PKG. DWG. #
PART NUMBER
EL5374IU
PACKAGE
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
PKG. DWG. #
MDP0040
MDP0040
MDP0040
MDP0040
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
-
7”
13”
-
EL5174IS-T7
EL5174IS-T13
EL5374IU-T7
EL5374IU-T13
EL5174ISZ
(See Note)
8-Pin SO
(Pb-Free)
EL5374IUZ
(See Note)
28-Pin QSOP
(Pb-Free)
EL5174ISZ-T7
(See Note)
8-Pin SO
(Pb-free)
7”
MDP0027
MDP0027
EL5374IUZ-T7
(See Note)
28-Pin QSOP
(Pb-Free)
7”
MDP0040
MDP0040
EL5174ISZ-T13
(See Note)
8-Pin SO
(Pb-free)
13”
EL5374IUZ-T13
(See Note)
28-Pin QSOP
(Pb-Free)
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7313.5
2
August 8, 2005
EL5174, EL5374
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, unless otherwise
S
S
A
IN
LD
F
G
LD
specified .
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
= 1, C = 2.7pF
LD
550
130
20
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
V
A
= 2, R = 500, C = 2.7pF
LD
V
F
A
= 10, R = 500, C = 2.7pF
LD
V
F
BW
SR
±0.1dB Bandwidth
A
= 1, C = 2.7pF
LD
120
1100
850
10
V
Slew Rate (EL5174)
Slew Rate (EL5374)
Settling Time to 0.1%
V
V
V
= 3V , 20% to 80%
P-P
800
600
OUT
OUT
OUT
= 3V , 20% to 80%
P-P
T
T
= 2V
P-P
STL
Output Overdrive Recovery Time
Gain Bandwidth Product
20
ns
OVR
GBWP
200
110
134
70
MHz
MHz
V/µs
V/µs
nV/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
%
V
V
V
V
BW (-3dB)
SR+
V
V
V
-3dB Bandwidth
Slew Rate - Rise
Slew Rate - Fall
A =1, C = 2.7pF
V LD
REF
REF
REF
N
REF
REF
REF
V
V
= 2V , 20% to 80%
P-P
OUT
OUT
SR-
= 2V , 20% to 80%
P-P
Input Voltage Noise
at 10kHz
at 10kHz
21
I
Input Current Noise
2.7
-95
-94
-88
-87
0.06
0.13
90
N
HD2
Second Harmonic Distortion
V
V
V
V
= 2V , 5MHz
P-P
OUT
OUT
OUT
OUT
= 2V , 20MHz
P-P
HD3
Third Harmonic Distortion
= 2V , 5MHz
P-P
= 2V , 20MHz
P-P
dG
Differential Gain at 3.58MHz
R
R
= 300Ω, A =2
V
LD
LD
dθ
Differential Phase at 3.58MHz
Channel Separation - for EL5374 only
= 300Ω, A =2
°
V
e
at f = 1MHz
dB
S
INPUT CHARACTERISTICS
Input Referred Offset Voltage
V
(EL5174)
(EL5374)
±1.4
±2.2
-14
2.3
±25
±25
-7
mV
mV
µA
µA
kΩ
pF
V
OS
I
I
Input Bias Current (V +, V -)
-30
0.5
IN
REF
IN
IN
Input Bias Current (V
)
4
REF
R
C
Differential Input Resistance
150
1
IN
IN
Differential Input Capacitance
Differential Mode Input Range
Common Mode Positive Input Range at
DMIR
±2.1
±2.3
3.4
±2.5
CMIR+
V
V
+, V -
IN IN
CMIR-
Common Mode Negative Input Range at
+, V
-4.3
V
V
-
IN
IN
FN7313.5
3
August 8, 2005
EL5174, EL5374
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, unless otherwise
S
S
A
IN
LD
F
G
LD
specified (Continued).
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
+
Positive Reference Input Voltage Range
(EL5374)
V
V
+ = V - = 0V
IN
3.4
3.7
V
REFIN
IN
-
Negative Reference Input Voltage Range
(EL5374)
+ = V - = 0V
IN
-3.3
-3
V
REFIN
IN
Output Offset Relative to V
(EL5374)
REF
±50
78
±100
mV
dB
REFOS
CMRR
Input Common Mode Rejection Ratio
(EL5374)
V
= ±2.5V
65
IN
Gain
Gain Accuracy
V
V
= 1V (EL5174)
= 1V (EL5374)
0.980
0.978
0.995
0.993
1.010
1.008
V
V
IN
IN
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
R
R
R
= 500Ω to GND (EL5174)
= 500Ω to GND (EL5374)
±3.4
±3.8
±60
130
V
V
OUT
L
L
L
±3.6
±50
I
(Max)
OUT
Maximum Output Current
Output Impedance
= 10Ω, V + = ±3.2V
IN
±100
mA
mΩ
R
OUT
SUPPLY
V
Supply Operating Range
V + to V -
4.75
10
11
14
10
V
SUPPLY
S
S
I
I
Power Supply Current - Per Channel
12.5
1.7
mA
µA
S(ON)
+
-
Positive Power Supply Current - Disabled EN pin tied to 4.8V
(EL5374)
S(OFF)
S(OFF)
I
Negative Power Supply Current -
Disabled (EL5374)
-200
60
-120
75
µA
dB
PSRR
Power Supply Rejection Ratio
V from ±4.5V to ±5.5V
S
ENABLE (EL5374 ONLY)
t
t
Enable Time
130
1.2
ns
µs
V
EN
DS
Disable Time
V
V
EN Pin Voltage for Power-Up
EN Pin Voltage for Shut-Down
EN Pin Input Current High
EN Pin Input Current Low
V + -1.5
S
IH
V + -0.5
S
V
IL
I
I
At V
At V
= 5V
= 0V
123
-8
130
µA
µA
IH-EN
IL-EN
EN
EN
-10
Pin Descriptions
EL5174
EL5374
17, 21, 27
2, 6, 10
3, 7, 11
16, 20, 26
15, 19, 25
24
PIN NAME
PIN FUNCTION
1
2
3
4
5
6
7
8
FBP1, 2, 3
INP1, 2, 3
INN1, 2, 3
FBN1, 2, 3
Feedback from non-inverting outputs
Non-inverting inputs
Inverting inputs, note that on EL5174, this pin is also the REF pin
Feedback from inverting outputs
Inverting outputs
OUT1B, 2B, 3B
VSP
Positive supply
23
VSN
Negative supply
18, 22, 28
1, 5, 9, 13
4, 8, 12
14
OUT1, 2, 3
NC
Non-inverting outputs
No connect; grounded for best crosstalk performance
Reference inputs, sets common-mode output voltage
ENABLE
REF1, 2, 3
EN
FN7313.5
4
August 8, 2005
Connection Diagrams
EL5174
R
F1
C
L1
5pF
-5V
0Ω
OUT
FBP
INP
1
2
3
4
OUT 8
VSN 7
IN+
R
LD
1kΩ
R
G
REF
FBN
REF
VSP 6
R
R
S1
S1
OUTB
OUTB 5
50Ω
50Ω
C
R
L2
5pF
F2
+5V
0Ω
EL5374
+5V
1
2
3
4
5
6
7
8
9
NC
OUT1 28
R
F
INP1
INN1
REF1
INP1
INN1
REF1
NC
FBP1 27
FBN1 26
OUT1B 25
VSP 24
0Ω
R
LD1
1kΩ
R
G
R
F
0Ω
INP2
INN2
REF2
INP2
INN2
REF2
NC
VSN 23
OUT2 22
R
F
R
LD2
1kΩ
FBP2
FBN2
21
20
19
18
17
16
0Ω
R
G
R
F
INP3
INN3
REF3
0Ω
INP3
INN3
REF3
NC
OUT2B
OUT3
FBP3
10
11
12
13
R
F
0Ω
R
G
R
LD3
1kΩ
R
R
R
R
R
R
R
R
R
R
F
SP1
50Ω
SN1
50Ω
SR1
50Ω
SP2
50Ω
SN2
50Ω
SR2
50Ω
SP3
SN3
SR3
FBN3
50Ω
50Ω
50Ω
0Ω
14 EN
OUT3B 15
C
C
C
C
C
C
L1
5pF
L1B
5pF
L2
5pF
L2B
5pF
L3
5pF
L3B
5pF
-5V
ENABLE
EL5174, EL5374
Typical Performance Curves
A
= 1, R = 1kΩ, C = 2.7pF
LD LD
R
= 1kΩ, C = 2.7pF
LD
V
LD
4
3
4
3
2
2
V
= 200mV
OP-P
1
1
A
= 1
V
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= 2
V
V
= 1V
OP-P
A
= 5
V
A
= 10
V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
A
= 1, C = 2.7pF
LD
A
= 1, R = 1kΩ
V
V
LD
10
4
3
C
= 50pF
LD
8
6
C
= 23pF
LD
C
= 34pF
2
LD
R
= 1kΩ
LD
4
1
2
0
0
-1
-2
-3
-4
-5
-6
R
= 500Ω
C
= 9pF
LD
LD
-2
-4
-6
-8
-10
C
= 2.7pF
LD
R
= 200Ω
LD
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs C
FIGURE 4. FREQUENCY RESPONSE vs R
LD
LD
A
= 2, R = 1kΩ, C = 2.7pF
A
= 2, C = 2.7pF, R = 750Ω
LD
V
LD
LD
V
F
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
= 1kΩ
F
R
= 1kΩ
LD
R
= 500Ω
R
= 500Ω
F
LD
R
= 200Ω
F
R
= 200Ω
LD
1M
10M
FREQUENCY (Hz)
100M
400M
1M
10M
FREQUENCY (Hz)
100M
400M
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs R
LD
FN7313.5
August 8, 2005
6
EL5174, EL5374
Typical Performance Curves (Continued)
5
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
3
2
1
PSRR-
0
-1
-2
-3
-4
-5
PSRR+
10M
100K
1M
10M
100M
1M
FREQUENCY (Hz)
10K
100K
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE - V
FIGURE 8. PSRR vs FREQUENCY
REF
100
1K
100
10
80
60
40
20
0
E
N
I
N
-20
1K
1
10
1M
10M
100
1K
10K
100K
10M
10K
100K
100M
1G
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY
FIGURE 10. VOLTAGE AND CURRENT NOISE vs FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
10
1
CH1 <=> CH2, CH2 <=> CH3
CH1 <=> CH3
100M
0.1
10K
100K
1M
10M
100M
10M
100K
1M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. CHANNEL ISOLATION (EL5374 ONLY)
FIGURE 12. OUTPUT IMPEDANCE vs FREQUENCY
FN7313.5
August 8, 2005
7
EL5174, EL5374
Typical Performance Curves (Continued)
V
= ±5V, A = 1, R = 1kΩ
LD
S
V
V
= ±5V, A = 2, R = 1kΩ
LD
S
V
-40
-50
-40
-50
-60
-70
-80
-90
HD3 (f = 5MHz)
-60
HD3 (f = 20MHz)
HD3 (f = 20MHz)
-70
-80
-90
HD2 (f = 20MHz)
4.5 5
HD2 (f = 5MHz)
HD2 (f = 5MHz)
-100
-100
1
1.5
2
2.5
V
3
3.5
(V)
4
1
2
3
4
5
6
7
8
9
10
V
(V)
OP-P, DM
OP-P, DM
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 14. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
V
= ±5V, A = 1, V
= 1V
OP-P, DM
V
= ±5V, A = 2, V
= 2V
S
V
S
V
OP-P, DM
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD3 (f = 20MHz)
HD3 (f = 5MHz)
HD2 (f = 2
0MHz)
HD2 (f = 5MHz)
200 300 400 500 600 700 800 900 1000
(Ω)
100 200 300 400 500 600 700 800 900 1000
(Ω)
R
R
LD
LD
FIGURE 15. HARMONIC DISTORTION vs R
LD
FIGURE 16. HARMONIC DISTORTION vs R
LD
V
= ±5V, R = 1kΩ, V
= 1V for A = 1,
OP-P, DM V
S
LD
V
= 2V for A = 2
OP-P, DM
V
-40
-50
HD3 (A = 2)
V
-60
-70
50mV/DIV
-80
-90
-100
0
10
20
30
40
50
60
10ns/DIV
FREQUENCY (MHz)
FIGURE 17. HARMONIC DISTORTION vs FREQUENCY
FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE
FN7313.5
August 8, 2005
8
EL5174, EL5374
Typical Performance Curves (Continued)
M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
0.5V/DIV
CH2
10ns/DIV
400ns/DIV
FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 20. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
1.2
1.010W
1
0.8
0.6
0.4
0.2
0
QSOP28
=99°C/W
θ
JA
CH1
CH2
625mW
SO8
=160°C/W
θ
JA
0
25
50
75 85 100
125
150
400ns/DIV
AMBIENT TEMPERATURE (°C)
FIGURE 21. DISABLED RESPONSE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1
1.266W
QSOP28
θ
=79°C/W
909mW
JA
0.8
0.6
0.4
0.2
0
SO8
=110°C/W
θ
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7313.5
9
August 8, 2005
EL5174, EL5374
Simplified Schematic
V +
S
R
R
3
4
R
R
2
1
R
R
7
8
IN+
IN-
FBP
FBN
V
V
B1
OUT+
R
R
CD
CD
REF
10
R
R
9
OUT-
B2
C
C
C
C
R
R
6
5
V -
S
Differential and Common Mode Gain Settings
Description of Operation and Application
Information
Product Description
For EL5174, since the I - pin and REF pin are bounded
N
together as the REF pin in an 8-pin package, the signal at
the REF pin is part of the common mode signal and also part
of the differential mode signal. For the true balance
The EL5174 and EL5374 are wide bandwidth, low power
and single/differential ended to differential output amplifiers.
The EL5174 is a single channel differential amplifier. Since
differential outputs, the REF pin must be tired to the same
bias level as the I + pin. For a ±5V supply, just tire the REF
N
the I - pin and REF pin are tired together internally, the
pin to GND if the I + pin is biased at 0V with a 50Ω or 75Ω
N
N
EL5174 can be used as a single ended to differential
converter. The EL5374 is a triple channel differential
termination resistor. For a single supply application, if the
I + is biased to half of the rail, the REF pin should be biased
N
amplifier. The EL5374 have a separate I - pin and REF pin
to half of the rail also.
N
for each channel. It can be used as single/differential ended
to differential converter. The EL5174 and EL5374 are
internally compensated for closed loop gain of +1 of greater.
Connected in gain of 1 and driving a 1kΩ differential load,
the EL5174 and EL5374 have a -3dB bandwidth of 550MHz.
Driving a 200Ω differential load at gain of 2, the bandwidth is
about 130MHz. The EL5374 is available with a power down
feature to reduce the power while the amplifier is disabled.
The gain setting for EL5174 is:
R
+ R
F2
F1
---------------------------
V
= V + × 1 +
ODM
IN
R
G
2R
F
----------
V
V
= V + = 1 +
ODM
OCM
IN
R
G
= V
= 0V
REF
Input, Output, and Supply Voltage Range
The EL5174 and EL5374 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.4V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is from -2.3V to +2.3V. The input
voltage range at the REF pin is from -3.3V to 3.7V. If the
input common mode or differential mode signal is outside the
above-specified ranges, it will cause the output signal
distorted.
Where:
V
= 0V
REF
R
= R = R
F2
F1
F
EL5374 have a separate I - pin and REF pin. It can be used
N
as a single/differential ended to differential converter. The
voltage applied at REF pin can set the output common mode
voltage and the gain is one.
The output of the EL5174 and EL5374 can swing from -3.8V
to +3.8V at 1kΩ differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
FN7313.5
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August 8, 2005
EL5174, EL5374
The gain setting for EL5374 is:
Driving Capacitive Loads and Cables
The EL5174 and EL5374 can drive 23pF differential
R
+ R
F2
F1
capacitor in parallel with 1kΩ differential load with less than
5dB of peaking at gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5Ω to
50Ω) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If
the gain setting is greater than 1, the gain resistor R can
then be chosen to make up for any gain loss which may be
created by the additional series resistor at the output.
---------------------------
V
= (V + – V -) × 1 +
ODM
IN
IN
R
G
2R
F
----------
V
V
= (V + – V -) × 1 +
ODM
OCM
IN
IN
R
G
= V
REF
G
Where:
= R = R
R
F1
F2
F
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
R
F1
FBP
V
+
V
V
+
-
IN
O
O
I +
N
R
G
V
-
IN
I -
N
V
REF
FBN
REF
Disable/Power-Down (for EL5374 only)
The EL5374 can be disabled and placed its outputs in a high
impedance state. The turn off time is about 1.2µs and the
turn on time is about 130ns. When disabled, the amplifier's
R
F2
FIGURE 24.
supply current is reduced to 1.7µA for I + and 120µA for I -
S
S
typically, thereby effectively eliminating the power
Choice of Feedback Resistor and Gain Bandwidth
Product
consumption. The amplifier's power down can be controlled
by standard CMOS signal levels at the EN pin. The applied
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
logic signal is relative to V + pin. Letting the EN pin float or
S
applying a signal that is less than 1.5V below V + will enable
S
the amplifier. The amplifier will be disabled when the signal
at EN pin is above V + - 0.5V.
S
Output Drive Capability
The EL5174 and EL5374 have internal short circuit
protection. Its typical short circuit current is ±60mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Therefore, R has some maximum value that should not be
F
exceeded for optimum performance. If a large value of R
F
must be used, a small capacitor in the few Pico farad range
in parallel with R can help to reduce the ringing and
F
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5174 and EL5374 depends on the
load and the feedback network. R and R appear in
F
G
Power Dissipation
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
With the high output drive capability of the EL5174 and
EL5374. It is possible to exceed the 135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
Consequently, R also has a minimum value that should not
F
be exceeded for optimum bandwidth performance. For gain
of +1, R = 0 is optimum. For the gains other than +1,
F
optimum response is obtained with R between 500Ω to
F
1kΩ.
The EL5174 and EL5374 have a gain bandwidth product of
200MHz for R = 1kΩ. For gains ≥5, its bandwidth can be
LD
The maximum power dissipation allowed in a package is
determined according to:
predicted by the following equation:
Gain × BW = 200MHz
T
– T
AMAX
JMAX
--------------------------------------------
PD
=
MAX
Θ
JA
FN7313.5
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August 8, 2005
EL5174, EL5374
Where:
Power Supply Bypassing and Printed Circuit
Board Layout
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
T
AMAX
θ
= Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
normal single supply operation, where the V - pin is
S
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V +
S
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
∆V
O
-----------
PD = i × V × I
+ V
S
×
S
SMAX
R
LD
be used. In this case, the V - pin becomes the negative
S
supply rail.
Where:
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
V = Total supply voltage
S
I
= Maximum quiescent supply current per channel
SMAX
∆V = Maximum differential output voltage of the
O
application
R
= Differential load resistance
LD
I
= Load current
LOAD
i = Number of channels
By setting the two PD
equations equal to each other, we
MAX
can solve the output current and R to avoid the device
LD
overheat.
Typical Applications
R
F
FBP
IN+
IN-
50
50
TWISTED PAIR
IN+
R
R
G
T
EL5174/
EL5374
EL5175/
EL5375
V
O
REF
IN-
Z
= 100Ω
O
FBN
REF
R
F
R
FR
R
GR
FIGURE 25. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
FN7313.5
12
August 8, 2005
EL5174, EL5374
R
F
GAIN
(dB)
FBP
I +
V
V
+
-
O
N
R
75
T
R
R
G
GC
I -
N
C
REF
FBN
L
O
f
f
H
FREQUENCY
R
L
F
2R
1
G
F
------------------------
≅
f
f
----------
DC Gain = 1 +
L
2πR
C
C
R
G
1
GC
2R
----------------------------
≅
F
H
2πR
C
C
--------------------------
||
(HF)Gain = 1 +
R
R
G
GC
FIGURE 26. TRANSMIT EQUALIZER
FN7313.5
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August 8, 2005
EL5174, EL5374
SO Package Outline Drawing
FN7313.5
14
August 8, 2005
EL5174, EL5374
QSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7313.5
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August 8, 2005
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