EL5176IYZ-T13 [INTERSIL]
250MHz Differential Twisted-Pair Driver; 为250MHz差分双绞线驱动器
| 型号： | EL5176IYZ-T13 |
| 厂家： | 
Intersil |
| 描述： | 250MHz Differential Twisted-Pair Driver |
| 文件： | 总11页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5176
®
Data Sheet
August 3, 2005
FN7343.2
250MHz Differential Twisted-Pair Driver
Features
The EL5176 is a high bandwidth amplifier with an output in
differential form. It is primarily targeted for applications such
as driving twisted-pair lines or any application where
common mode injection is likely to occur. The input signal
can be in either single-ended or differential form but the
output is always in differential form.
• Fully differential inputs, outputs, and feedback
• Differential input range ±2.3V
• 250MHz 3dB bandwidth
• 800V/µs slew rate
• Low distortion at 20MHz
On the EL5176, two feedback inputs provide the user with
the ability to set the device gain (stable at minimum gain of
one).
• Single 5V or dual ±5V supplies
• 40mA maximum output current
• Low power - 8mA typical supply current
• Pb-Free plus anneal available (RoHS compliant)
The output common mode level is set by the reference pin
(REF), which has a -3dB bandwidth of over 50MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
Applications
• Twisted-pair drivers
Both outputs (OUT+, OUT-) are short circuit protected to
withstand temporary overload condition.
• Differential line drivers
The EL5176 is available in the 10-pin MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
• VGA over twisted-pair
• ADSL/HDSL drivers
• Single ended to differential amplification
• Transmission of analog signals in a noisy environment
See also EL5171 (EL5176 in 8-pin MSOP.)
Ordering Information
Pinout
PART
NUMBER
PACKAGE
10-Pin MSOP
10-Pin MSOP
10-Pin MSOP
TAPE & REEL PKG. DWG. #
EL5176
(10-PIN MSOP)
TOP VIEW
EL5176IY
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5176IY-T7
EL5176IY-T13
FBP
IN+
1
2
3
4
5
10 OUT+
EL5176IYZ
(See Note)
10-Pin MSOP
(Pb-free)
9
8
7
6
VS-
+
-
REF
IN-
VS+
EN
EL5176IYZ-T7
(See Note)
10-Pin MSOP
(Pb-free)
7”
MDP0043
MDP0043
EL5176IYZ-T13 10-Pin MSOP
(See Note) (Pb-free)
13”
FBN
OUT-
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5176
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
LD
F
G
LD
Specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
= 1, C = 2.7pF
LD
250
60
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
V
A
A
A
V
V
V
= 2, R = 500, C = 2.7pF
LD
V
F
= 10, R = 500, C = 2.7pF
10
V
F
LD
BW
SR
±0.1dB Bandwidth
Slew Rate - Rise
Slew Rate - Fall
= 1, C = 2.7pF
50
V
LD
= 3V , 20% to 80%
P-P
600
540
800
700
10
1000
1000
OUT
OUT
OUT
= 3V , 20% to 80%
P-P
T
T
Settling Time to 0.1%
= 2V
P-P
STL
Output Overdrive Recovery Time
Gain Bandwidth Product
20
ns
OVR
GBWP
100
50
MHz
MHz
V/µs
V/µs
nV/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
%
V
V
V
V
BW (-3dB) V
-3dB Bandwidth
Slew Rate - Rise
Slew Rate - Fall
A
V
V
=1, C = 2.7pF
LD
REF
REF
REF
N
REF
REF
REF
V
SR+
SR-
V
V
= 2V , 20% to 80%
P-P
90
OUT
OUT
= 2V , 20% to 80%
P-P
50
Input Voltage Noise
at 10kHz
at 10kHz
26
I
Input Current Noise
2
N
HD2
Second Harmonic Distortion
V
V
V
V
= 2V , 5MHz
P-P
-94
-94
-77
-75
0.1
0.5
OUT
OUT
OUT
OUT
= 2V , 20MHz
P-P
HD3
Third Harmonic Distortion
= 2V , 5MHz
P-P
= 2V , 20MHz
P-P
dG
Differential Gain at 3.58MHz
Differential Phase at 3.58MHz
R
= 300Ω, A = 2
L
L
V
dθ
R
= 300Ω, A = 2
°
V
INPUT CHARACTERISTICS
Input Referred Offset Voltage
V
±1.5
-6
±25
-3
mV
µA
µA
kΩ
pF
V
OS
I
I
Input Bias Current (V +, V -)
-14
0.5
IN
REF
IN
IN
Input Bias Current (V
)
1.3
300
1
4
REF
R
C
Differential Input Resistance
Differential Input Capacitance
Differential Mode Input Range
IN
IN
DMIR
±2.1
3.1
±2.3
3.4
-4.5
3.8
-3.3
±60
±2.5
-4.2
CMIR+
CMIR-
Common Mode Positive Input Range at V +, V
IN
-
V
IN
Common Mode Negative Input Range at V +, V
IN
-
V
IN
V
V
V
+
-
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
V
V
+ = V - = 0V
IN
3.5
V
REFIN
REFIN
IN
+ = V - = 0V
IN
-3
V
IN
Output Offset Relative to V
±100
mV
REFOS
REF
FN7343.2
2
August 3, 2005
EL5176
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
LD
F
G
LD
Specified (Continued)
PARAMETER
CMRR
DESCRIPTION
CONDITIONS
= ±2.5V
MIN
65
TYP
82
MAX
UNIT
dB
Input Common Mode Rejection Ratio
Gain Accuracy
V
V
IN
IN
Gain
= 1
0.981
0.996
1.011
V
OUTPUT CHARACTERISTICS
V
Positive Output Swing
R
= 500Ω to GND
3.6
35
3.9
-3.8
50
V
V
OUT
L
Negative Output Swing
-3.5
-30
I
(Max)
Maximum Source Output Current
Maximum Sink Output Current
R
= 10Ω,
mA
mA
OUT
L
V
V
V
+ = 1.1V,
- = -1.1V,
IN
IN
REF
-40
= 0
R
Output Impedance
130
mΩ
OUT
SUPPLY
V
Supply Operating Range
V + to V -
4.75
6.8
11
8.2
120
V
SUPPLY
S
S
I
I
I
Power Supply Current - Per Channel
7.5
80
mA
µA
µA
dB
S(ON)
+
-
Positive Power Supply Current - Disabled
Negative Power Supply Current - Disabled
Power Supply Rejection Ratio
EN pin tied to 4.8V
S(OFF)
S(OFF)
-200
70
-120
84
PSRR
ENABLE
V from ±4.5V to ±5.5V
S
t
t
Enable Time
215
ns
µs
V
EN
DS
Disable Time
0.95
V
EN Pin Voltage for Power-Up
V + -
S
IH
1.5
V
EN Pin Voltage for Shut-Down
V + -
S
V
IL
0.5
I
I
EN Pin Input Current High
EN Pin Input Current Low
At V
At V
= 5V
= 0V
40
60
µA
µA
IH-EN
IL-EN
EN
EN
-6
-2.5
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
2
FBP
IN+
Non-inverting feedback input; resistor R must be connected from this pin to V
F1
OUT
Non-inverting input
3
REF
IN-
Output common-mode control; the common-mode voltage of V
will follow the voltage on this pin
OUT
4
Inverting input
5
FBN
OUT-
EN
Inverting feedback input; resistor R must be connected from this pin to V
F2
OUT
6
Inverting output
7
Enabled when this pin is floating or the applied voltage ≤ V + -1.5
S
8
VS+
VS-
Positive supply
9
Negative supply
Non-inverting output
10
OUT+
FN7343.2
3
August 3, 2005
EL5176
Connection Diagram
R
F1
0Ω
VREF
R
S3
50Ω
1
2
3
4
5
FBP
IN+
OUT+ 10
OUT+
INP
VS-
VS+
EN
9
8
7
6
-5V
R
S1
50Ω
R
LD
1kΩ
R
OPEN
G
REF
IN-
+5V
INN-
EN
R
S2
50Ω
FBN
OUT-
OUT-
R
F2
0Ω
Typical Performance Curves
A
= 1, R = 1kΩ, C = 2.7pF
LD LD
R
= 1kΩ, C = 2.7pF
LD LD
V
4
3
4
3
2
2
1
1
0
0
V
= 200mV
OP-P
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= 1
V
A = 2
V
A
= 5
V
V
= 1V
P-P
OP-P
A
= 10
V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
A
= 1, C = 2.7pF
LD
V
A
= 1, R = 1kΩ
LD
V
4
3
5
4
C
= 56pF
LD
2
C
= 34pF
LD
3
1
2
C
= 23pF
LD
R
= 1kΩ
LD
0
1
R
= 500Ω
-1
-2
-3
-4
-5
-6
LD
0
-1
-2
-3
-4
-5
C
= 9pF
LD
C
R
= 200Ω
LD
= 2.7pF
LD
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs R
FIGURE 4. FREQUENCY RESPONSE vs C
LD
LD
FN7343.2
August 3, 2005
4
EL5176
Typical Performance Curves (Continued)
A
= 2, R = 1kΩ, C = 2.7pF
LD
A
= 2, R = 1kΩ, C = 2.7pF
LD LD
V
F
V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
= 1kΩ
F
R
= 1kΩ
LD
R
= 500Ω
F
R
= 500Ω
LD
R
= 200Ω
F
R
= 200Ω
LD
1M
10M
100M
400M
1M
10M
FREQUENCY (Hz)
100M
400M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs R
LD
100
5
4
3
2
10
1
1
0
-1
-2
-3
-4
-5
0.1
10K
100K
1M
10M
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 7. FREQUENCY RESPONSE - V
REF
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
90
80
70
60
50
40
30
20
10
0
PSRR-
PSRR+
10M
100K
1M
100M
1G
100K
FREQUENCY (Hz)
1K
10K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 10. CMRR vs FREQUENCY
FIGURE 9. PSRR vs FREQUENCY
FN7343.2
August 3, 2005
5
EL5176
Typical Performance Curves (Continued)
V
= ±5V, A = 1, R = 1kΩ
S
V
LD
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
1K
100
E
N
10
I
N
1
10
1
1.5
2
2.5
3
3.5
(V)
4
4.5
5
10K
FREQUENCY (Hz)
100
1K
100K
1M
10M
V
OP-P, DM
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 11. VOLTAGE AND CURRENT NOISE vs FREQUENCY
V
= ±5V, A = 1, R = 1kΩ
S
V
LD
V
= ±5V, A = 1, V
= 1V
OP-P, DM
S
V
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD3 (f = 5MHz)
1
2
3
4
5
6
7
8
9
10
100 200 300 400 500 600 700 800 900 1000
V
(V)
OP-P, DM
R
(Ω)
LD
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 14. HARMONIC DISTORTION vs R
LD
V
V
= ±5V, R = 1kΩ, V
= 1V for A = 1,
OP-P, DM V
V
= ±5V, A = 2, V
V
= 2V
OP-P, DM
S
LD
S
= 2V for A = 2
V
OP-P, DM
-40
-50
-40
-50
HD3 (A = 1)
HD3 (f = 20MHz)
V
HD3 (f = 5MHz)
-60
-60
-70
-70
-80
-80
HD2 (f = 5MHz)
-90
-90
-100
-100
0
10
20
30
40
50
60
200 300
400 500 600 700
(Ω)
800 900 1000
FREQUENCY (MHz)
R
LD
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FIGURE 15. HARMONIC DISTORTION vs R
LD
FN7343.2
August 3, 2005
6
EL5176
Typical Performance Curves (Continued)
0.5V/DIV
50mV/DIV
10ns/DIV
10ns/DIV
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
CH2
CH1
CH2
200ns/DIV
100ns/DIV
FIGURE 20. DISABLED RESPONSE
FIGURE 19. ENABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
CONDUCTIVITY TEST BOARD
0.6
0.9
0.5
870mW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
486mW
MSOP8/10
MSOP8/10
0.4
θ
=115°C/W
JA
θ
=206°C/W
JA
0.3
0.2
0.1
0
0
25
50
75 85 100
125
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7343.2
August 3, 2005
7
EL5176
Simplified Schematic
V +
S
R
R
3
4
R
R
2
1
R
R
7
8
IN+
IN-
FBP
FBN
V
V
B1
OUT+
R
R
CD
CD
REF
10
R
R
9
OUT-
B2
C
C
C
C
R
R
6
5
V -
S
The gain setting for EL5176 is:
Description of Operation and Application
Information
Product Description
The EL5176 is a wide bandwidth, low power and
single/differential ended to differential output amplifier. It can
be used as single/differential ended to differential converter.
The EL5176 is internally compensated for closed loop gain
of +1 of greater. Connected in gain of 1 and driving a 1kΩ
differential load, the EL5176 has a -3dB bandwidth of
250MHz. Driving a 200Ω differential load at gain of 2, the
bandwidth is about 30MHz. The EL5176 is available with a
power down feature to reduce the power while the amplifier
is disabled.
R
+ R
F2
F1
V
= V + × 1 + ---------------------------
IN
R
ODM
G
2R
F
V
V
= (V + – V -) × 1 + ----------
ODM
OCM
IN
IN
R
G
= V
REF
Where:
• R = R = R
F1 F2
F
R
F1
Input, Output, and Supply Voltage Range
FBP
IN+
V
+
V
V
+
-
IN
O
The EL5176 has been designed to operate with a single
supply voltage of 5V to 10V or a split supplies with its total
voltage from 5V to 10V. The amplifier has an input common
mode voltage range from -4.5V to 3.4V for ±5V supply. The
differential mode input range (DMIR) between the two inputs
is from -2.3V to +2.3V. The input voltage range at the REF
pin is from -3.3V to 3.8V. If the input common mode or
differential mode signal is outside the above-specified
ranges, it will cause the output signal distorted.
R
G
V
-
IN
IN-
V
REF
FBN
REF
O
R
F2
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth
Product
The output of the EL5176 can swing from -3.8V to +3.9V at
1kΩ differential load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced.
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Differential and Common Mode Gain Settings
The voltage applied at REF pin can set the output common
mode voltage and the gain is one. The differential gain is set
by the R and R network.
F
G
Therefore, R has some maximum value that should not be
F
exceeded for optimum performance. If a large value of R
F
must be used, a small capacitor in the few Pico farad range
FN7343.2
8
August 3, 2005
EL5176
in parallel with R can help to reduce the ringing and
F
peaking at the expense of reducing the bandwidth.
±40mA. This limit is set by the design of the internal metal
interconnect.
The bandwidth of the EL5176 depends on the load and the
Power Dissipation
feedback network. R and R appear in parallel with the
F
G
With the high output drive capability of the EL5176. It is
possible to exceed the 135°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, R also has a
F
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, R = 0 is optimum.
F
For the gains other than +1, optimum response is obtained
with R between 500Ω to 1kΩ.
F
The EL5176 has a gain bandwidth product of 100MHz for
The maximum power dissipation allowed in a package is
determined according to:
R
= 1kΩ. For gains ≥5, its bandwidth can be predicted by
LD
the following equation:
T
– T
AMAX
JMAX
PD
= --------------------------------------------
Gain × BW = 100MHz
MAX
Θ
JA
Driving Capacitive Loads and Cables
Where:
The EL5176 can drive 50pF differential capacitor in parallel
with 1kΩ differential load with less than 5dB of peaking at
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• θ = Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
than 1, the gain resistor R can then be chosen to make up
G
for any gain loss which may be created by the additional
series resistor at the output.
∆V
O
PD = V × I
+ V × -----------
S
SMAX
S
R
LD
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Where:
• V = Total supply voltage
S
• I
= Maximum quiescent supply current per channel
SMAX
• ∆V = Maximum differential output voltage of the
application
O
• R = Differential load resistance
LD
Disable/Power-Down
The EL5176 can be disabled and placed its outputs in a high
impedance state. The turn off time is about 0.95µs and the
turn on time is about 215ns. When disabled, the amplifier's
• I
= Load current
LOAD
By setting the two PD
equations equal to each other, we
MAX
can solve the output current and R to avoid the device
LD
supply current is reduced to 1.7µA for I + and 120µA for I -
S
S
overheat.
typically, thereby effectively eliminating the power
consumption. The amplifier's power down can be controlled
by standard CMOS signal levels at the ENABLE pin. The
Power Supply Bypassing and Printed Circuit
Board Layout
applied logic signal is relative to V + pin. Letting the EN pin
S
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
float or applying a signal that is less than 1.5V below V + will
S
enable the amplifier. The amplifier will be disabled when the
signal at EN pin is above V + - 0.5V.
S
normal single supply operation, where the V - pin is
S
Output Drive Capability
connected to the ground plane, a single 4.7µF tantalum
The EL5176 has internal short circuit protection. Its typical
short circuit current is ±40mA for EL5176. If the output is
shorted indefinitely, the power dissipation could easily
increase such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
capacitor in parallel with a 0.1µF ceramic capacitor from V +
S
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V - pin becomes the negative
S
supply rail.
FN7343.2
August 3, 2005
9
EL5176
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
R
F
FBP
IN+
IN-
50
50
TWISTED PAIR
IN+
R
R
G
T
EL5176
EL5172
V
O
REF
IN-
Z
= 100Ω
O
FBN
REF
R
F
R
FR
R
GR
FIGURE 24. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
R
F
Gain
(dB)
FBP
I +
V
V
+
-
O
N
R
75
T
R
R
G
GC
I -
N
C
REF
FBN
L
O
f
f
H
frequency
R
L
F
2R
1
F
f
≅ ------------------------
2πR C
DC Gain = 1 + ----------
L
R
G
G
C
1
2R
f
≅ ----------------------------
2πR C
F
H
(HF)Gain = 1 + --------------------------
GC
C
||
R
R
GC
G
FIGURE 25. TRANSMIT EQUALIZER
FN7343.2
August 3, 2005
10
EL5176
MSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7343.2
11
August 3, 2005
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