EL5210 [INTERSIL]
30MHz Rail-to-Rail Input-Output Op Amps; 30MHz的轨至轨输入输出运算放大器
| 型号： | EL5210 |
| 厂家： | 
Intersil |
| 描述： | 30MHz Rail-to-Rail Input-Output Op Amps |
| 文件： | 总13页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5210, EL5410
®
Data Sheet
May 6, 2005
FN7185.2
30MHz Rail-to-Rail Input-Output Op Amps
Features
The EL5210 and EL5410 are low power, high voltage rail-to-
rail input-output amplifiers. The EL5210 contains two
amplifiers in one package and the EL5410 contains four
amplifiers. Operating on supplies ranging from 5V to 15V,
while consuming only 2.5mA per amplifier, the EL5410 and
EL5210 have a bandwidth of 30MHz (-3dB). They also
provide common mode input ability beyond the supply rails,
as well as rail-to-rail output capability. This enables these
amplifiers to offer maximum dynamic range at any supply
voltage.
• 30MHz -3dB bandwidth
• Supply voltage = 4.5V to 16.5V
• Low supply current (per amplifier) = 2.5mA
• High slew rate = 33V/µs
• Unity-gain stable
• Beyond the rails input capability
• Rail-to-rail output swing
• Available in both standard and space-saving fine pitch
packages
The EL5410 and EL5210 also feature fast slewing and
settling times, as well as a high output drive capability of
30mA (sink and source). These features make these
amplifiers ideal for high speed filtering and signal
conditioning application. Other applications include battery
power, portable devices, and anywhere low power
consumption is important.
• Pb-Free available (RoHS compliant)
Applications
• Driver for A-to-D Converters
• Data Acquisition
The EL5410 is available in a space-saving 14-Pin TSSOP
package, as well as the industry-standard 14-Pin SOIC. The
EL5210 is available in the 8-Pin MSOP and 8-Pin SOIC
packages. Both feature a standard operational amplifier pin
out. These amplifiers operate over a temperature range of
-40°C to +85°C.
• Video Processing
• Audio Processing
• Active Filters
• Test Equipment
• Battery Powered Applications
• Portable Equipment
Pinouts
EL5210
(8-PIN MSOP, SOIC)
TOP VIEW
EL5410
(14-PIN TSSOP, SOIC)
TOP VIEW
VOUTA
VINA-
VOUTD
VIND-
1
2
3
4
5
6
7
14
13
12
VOUTA
VINA-
VINA+
VS-
1
2
3
4
8
7
6
5
VS+
-
-
VINA+
VIND+
+
+
-
VOUTB
VINB-
VINB+
+
VS+
11 VS-
-
+
VINB+
VINC+
10
9
+
-
+
-
VINB-
VINC-
VOUTB
VOUTC
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5210, EL5410
Ordering Information
PART NUMBER
PACKAGE TAPE & REEL PKG. DWG. #
EL5210CS
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
-
7”
13”
-
MDP0027
EL5210CS-T7
EL5210CS-T13
MDP0027
MDP0027
MDP0027
EL5210CSZ
(See Note)
8-Pin SOIC
(Pb-free)
EL5210CSZ-T7
(See Note)
8-Pin SOIC
(Pb-free)
7”
MDP0027
MDP0027
EL5210CSZ-T13
(See Note)
8-Pin SOIC
(Pb-free)
13”
EL5210CY
8-Pin MSOP
8-Pin MSOP
8-Pin MSOP
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5210CY-T7
EL5210CY-T13
EL5210CYZ
(See Note)
8-Pin MSOP
(Pb-free)
EL5210CYZ-T7
(See Note)
8-Pin MSOP
(Pb-free)
7”
MDP0043
MDP0043
EL5210CYZ-T13
(See Note)
8-Pin MSOP
(Pb-free)
13”
EL5410CS
14-Pin SOIC
14-Pin SOIC
14-Pin SOIC
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
EL5410CS-T7
EL5410CS-T13
EL5410CSZ
(See Note)
14-Pin SOIC
(Pb-free)
EL5410CSZ-T7
(See Note)
14-Pin SOIC
(Pb-free)
7”
MDP0027
MDP0027
EL5410CSZ-T13 14-Pin SOIC
13”
(See Note)
(Pb-free)
EL5410CR
14-Pin TSSOP
14-Pin TSSOP
14-Pin TSSOP
-
7”
13”
-
MDP0044
MDP0044
MDP0044
MDP0044
EL5410CR-T7
EL5410CR-T13
EL5410CRZ
(See Note)
14-Pin TSSOP
(Pb-free)
EL5410CRZ-T7
(See Note)
14-Pin TSSOP
(Pb-free)
7”
MDP0044
MDP0044
EL5410CRZ-T13 14-Pin TSSOP
(See Note) (Pb-free)
13”
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7185.2
2
May 6, 2005
EL5210, EL5410
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 1kΩ and C = 12pF to 0V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 0V
= 0V
3
7
2
1
2
15
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 1)
Input Bias Current
OS
I
60
B
R
Input Impedance
GΩ
pF
IN
IN
C
Input Capacitance
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-5.5
50
+5.5
-4.8
V
CMRR
for V from -5.5V to 5.5V
IN
70
80
dB
A
-4.5V ≤ V
≤ 4.5V
OUT
65
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
Output Current
I = -5mA
-4.9
4.9
V
V
OL
L
I = 5mA
4.8
60
OH
L
I
I
±120
±30
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Amplifier)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from ±2.25V to ±7.75V
80
dB
S
I
No Load
2.5
3.75
mA
S
-4.0V ≤ V
≤ 4.0V, 20% to 80%
33
140
30
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V Step
S
V
O
BW
-3dB Bandwidth
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
20
50
CS
Channel Separation
Differential Gain (Note 3)
Differential Phase (Note 3)
f = 5MHz
110
0.12
0.17
dB
%
d
d
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
F
G
OUT
OUT
R
= R = 1kΩ and V
°
G
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
3. NTSC signal generator used
FN7185.2
3
May 6, 2005
EL5210, EL5410
Electrical Specifications V + = 5V, V - = 0V, R = 1kΩ and C = 12pF to 2.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 2.5V
= 2.5V
3
7
2
1
2
15
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 1)
Input Bias Current
OS
I
60
B
R
Input Impedance
GΩ
pF
IN
IN
C
Input Capacitance
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
45
+5.5
200
V
CMRR
for V from -0.5V to 5.5V
IN
66
80
dB
A
0.5V ≤ V
≤ 4.5V
OUT
65
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
Output Current
I = -5mA
100
4.9
mV
V
OL
L
I = 5mA
4.8
60
OH
L
I
I
±120
±30
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Amplifier)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from 4.5V to 15.5V
80
dB
S
I
No Load
2.5
3.75
mA
S
1V ≤ V
≤ 4V, 20% o 80%
33
140
30
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V Step
S
V
O
BW
-3dB Bandwidth
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
20
50
CS
Channel Separation
Differential Gain (Note 3)
Differential Phase (Note 3)
f = 5MHz
110
0.30
0.66
dB
%
d
d
R
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
F
G
OUT
= R = 1kΩ and V
°
G
OUT
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
3. NTSC signal generator used
FN7185.2
4
May 6, 2005
EL5210, EL5410
Electrical Specifications V + = 15V, V - = 0V, R = 1kΩ and C = 12pF to 7.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 7.5V
= 7.5V
3
7
2
1
2
15
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 1)
Input Bias Current
OS
I
60
B
R
C
Input Impedance
GΩ
pF
IN
IN
Input Capacitance
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
53
+15.5
350
V
CMRR
for V from -0.5V to 15.5V
IN
72
80
dB
A
0.5V ≤ V
≤ 14.5V
OUT
65
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
Output Current
I = -7.5mA
170
14.83
±120
±30
mV
V
OL
L
I = 7.5mA
14.65
OH
L
I
I
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Amplifier)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
V
is moved from 4.5V to 15.5V
60
80
dB
S
I
No Load
2.5
3.75
mA
S
1V ≤ V
≤ 14V, 20% o 80%
33
140
30
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V Step
S
V
O
BW
-3dB Bandwidth
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
20
50
CS
Channel Separation
Differential Gain (Note 3)
Differential Phase (Note 3)
f = 5MHz
110
0.10
0.11
dB
%
d
d
R
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
G
OUT
OUT
= R = 1kΩ and V
°
F
G
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
3. NTSC signal generator used
FN7185.2
5
May 6, 2005
EL5210, EL5410
Typical Performance Curves
EL5410 Input Offset Voltage Drift
EL5410 Input Offset Voltage Distribution
500
25
20
15
10
5
V
=±5V
S
Typical
Production
Distortion
Typical
Production
Distortion
V
T
=±5V
=25°C
S
A
400
300
200
100
0
0
Input Offset Voltage Drift, TCV
OS
(µV/°C)
Input Offset Voltage (mV)
Input Offset Voltage vs Temperature
Input Bias Current vs Temperature
0.008
0.004
0
5
4
3
2
1
0
V
=±5V
S
-0.004
-0.008
-0.012
-50
-10
30
70
110
150
-50
-10
30
70
110
150
Temperature (°C)
Temperature (°C)
Output Low Voltage vs Temperature
Output High Voltage vs Temperature
-4.85
-4.87
-4.89
-4.91
-4.93
-4.95
4.96
4.95
4.94
4.93
4.92
4.91
V
=±5V
=5mA
V
I
=±5V
S
S
I
=5mA
OUT
OUT
-50
-10
30
70
110
150
-50
-10
30
70
110
150
Temperature (°C)
Temperature (°C)
FN7185.2
May 6, 2005
6
EL5210, EL5410
Typical Performance Curves (Continued)
Open-Loop Gain vs Temperature
90
Slew Rate vs Temperature
33.85
33.80
33.75
33.70
33.65
33.60
33.55
V
=±5V
S
V
=±5V
S
L
85
80
75
70
R =1kΩ
-40
0
40
80
120
160
150
10
-50
-10
30
70
110
150
Temperature (°C)
Temperature (°C)
EL5410 Supply Current per Amplifier vs Supply Voltage
EL5410 Supply Current per Amplifier vs Temperature
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
2.7
2.65
2.6
T
=25°C
A
V
=±5V
S
2.55
2.5
2.45
2.4
-50
-10
30
70
110
4
8
12
16
20
Supply Voltage (V)
Temperature (°C)
Differential Gain and Phase
Harmonic Distortion vs V
OP-P
0.25
0.15
0.05
-0.05
-30
-40
-50
-60
-70
-80
V
A
=±5V
S
=2
V
V
A
=±5V
=1
S
V
R =1kΩ
L
HD3
R =1k
L
IN
F
= 1MHz
0
100
200
HD2
0.20
0.10
0
-0.10
0
100
IRE
200
0
2
4
6
8
V
(V)
OP-P
FN7185.2
7
May 6, 2005
EL5210, EL5410
Typical Performance Curves (Continued)
Open Loop Gain and Phase vs Frequency
140
Frequency Response for Various R
L
250
150
50
5
3
Phase
10kΩ
1kΩ
100
60
1
0
560Ω
-50
20
-1
Gain
A
V
=1
=±5V
V
S
V
=±5V T =25°C
A
L
L
S
-150
-20
-3
-5
150Ω
C =12pF
R =1kΩ to GND
C =12pF to GND
L
-250
-60
10
100
1k
10k
100k
1M
10M
100M
1M
100M
100k
10M
Frequency (Hz)
Frequency (Hz)
Frequency Response for Various C
Closed Loop Output Impedance vs Frequency
L
20
10
200
160
120
80
100pF
A
=1
=±5V
=25°C
V
1000pF
V
S
A
T
47pF
10pF
0
-10
-20
-30
R =1kΩ
L
A
V
=1
=±5V
V
S
40
0
10k
100k
1M
10M
30M
1M
100M
100k
10M
Frequency (Hz)
Frequency (Hz)
Maximum Output Swing vs Frequency
CMRR vs Frequency
80
70
60
50
40
30
10
8
6
V
T
A
=±5V
=25°C
S
A
4
=1
V
R =1kΩ
C =12pF
Distortion <1%
L
L
V
T
=±5V
=25°C
S
A
2
0
10
100
1k
10k
100k
1M
10M 30M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
FN7185.2
May 6, 2005
8
EL5210, EL5410
Typical Performance Curves (Continued)
Input Voltage Noise Spectral Density vs Frequency
PSRR vs Frequency
80
1000
100
PSRR+
PSRR-
60
40
10
1
V
T
=±5V
=25°C
S
A
20
0
1k
10k
100k
1M
100
1k
10k
100k
1M
10M
100M
100
10M
Frequency (Hz)
Frequency (Hz)
Total Harmonic Distortion + Noise vs Frequency
Channel Separation vs Frequency Response
-60
-80
0.010
0.008
0.006
0.004
0.002
0
Dual measured Channel A to B
Quad measured Channel A to D or B to C
Other combinations yield improved rejection
-100
-120
-140
-160
V
=±5V
S
V
=±5V
S
L
R =1kΩ
A
V
L
V
R =1kΩ
A
V
=1
=1
V
=0.5V
IN
RMS
=110mV
IN
RMS
1k
10k
100k
1M
10M 30M
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Small-Signal Overshoot vs Load Capacitance
Settling Time vs Step Size
5
100
80
60
40
20
0
V =±5V
S
V
A
=±5V
S
4
3
A =1
=1
V
V
R =1k
R =1kΩ
L
L
0.1%
C =12pF
V
T
=±50mV
=25°C
L
A
IN
T
=25°C
2
A
1
0
-1
-2
-3
-4
-5
0.1%
210
70
90
110
130
150
170
190
230
10
100
1000
Load Capacitance (pF)
Settling Time (ns)
FN7185.2
9
May 6, 2005
EL5210, EL5410
Typical Performance Curves (Continued)
Large Signal Transient Response
Small Signal Transient Response
50mV
1V
200ns
100ns
V
T
A
=±5V
=25°C
S
A
=1
V
R =1kΩ
C =12pF
L
L
V
T
A
=±5V
=25°C
S
A
=1
V
R =1kΩ
C =12pF
L
L
Pin Des criptions
EL5210
EL5410
NAME
FUNCTION
Amplifier A Output
EQUIVALENT CIRCUIT
1
1
V
OUTA
V
+
S
V
-
S
GND
Circuit 1
2
2
V
-
Amplifier A Inverting Input
INA
V
+
S
V
-
S
Circuit 2
3
8
5
6
7
3
4
V
+
Amplifier A Non-Inverting Input
Positive Power Supply
(Reference Circuit 2)
INA
V +
S
5
V
+
Amplifier B Non-Inverting Input
Amplifier B Inverting Input
Amplifier B Output
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
(Reference Circuit 1)
(Reference Circuit 2)
(Reference Circuit 2)
INB
6
V
-
INB
7
V
V
OUTB
OUTC
8
Amplifier C Output
9
V
-
Amplifier C Inverting Input
Amplifier C Non-Inverting Input
Negative Power Supply
Amplifier D Non-Inverting Input
Amplifier D Inverting Input
Amplifier D Output
INC
10
11
12
13
14
V
+
INC
4
V -
S
V
+
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
IND
V
-
IND
V
OUTD
FN7185.2
10
May 6, 2005
EL5210, EL5410
output continuous current never exceeds ±30mA. This limit
is set by the design of the internal metal interconnects.
Applications Information
Product Des cription
Output Phas e Revers al
The EL5210 and EL5410 voltage feedback amplifiers are
fabricated using a high voltage CMOS process. They exhibit
Rail-to-Rail input and output capability, are unity gain stable
and have low power consumption (2.5mA per amplifier).
These features make the EL5210 and EL5410 ideal for a
wide range of general-purpose applications. Connected in
voltage follower mode and driving a load of 1kΩ and 12pF,
the EL5210 and EL5410 have a -3dB bandwidth of 30MHz
while maintaining a 33V/µS slew rate. The EL5210 is a dual
amplifier while the EL5410 is a quad amplifier.
The EL5210 and EL5410 are immune to phase reversal as
long as the input voltage is limited from V - -0.5V to V +
S
S
+0.5V. Figure 2 shows a photo of the output of the device
with the input voltage driven beyond the supply rails.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diodes placed in the input stage of the device
begin to conduct and overvoltage damage could occur.
Operating Voltage, Input, and Output
1V
10µs
The EL5210 and EL5410 are specified with a single nominal
supply voltage from 5V to 15V or a split supply with its total
range from 5V to 15V. Correct operation is guaranteed for a
supply range of 4.5V to 16.5V. Most EL5210 and EL5410
specifications are stable over both the full supply range and
operating temperatures of -40°C to +85°C. Parameter
variations with operating voltage and/or temperature are
shown in the typical performance curves.
V
T
A
V
=±2.5V
=25°C
S
A
=1
V
=6V
IN
P-P
The input common-mode voltage range of the EL5210 and
EL5410 extends 500mV beyond the supply rails. The output
swings of the EL5210 and EL5410 typically extend to within
100mV of positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage range even closer to the supply rails. Figure 1
shows the input and output waveforms for the device in the
unity-gain configuration. Operation is from ±5V supply with a
1V
FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dis s ipation
With the high-output drive capability of the EL5210 and
EL5410 amplifiers, it is possible to exceed the 125°C
'absolute-maximum junction temperature' under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.
1kΩ load connected to GND. The input is a 10V
sinusoid.
P-P
The output voltage is approximately
9.8V
.
P-P
5V
10µs
The maximum power dissipation allowed in a package is
determined according to:
T
– T
AMAX
V
T
A
V
=±5V
=25°C
S
A
JMAX
P
= --------------------------------------------
DMAX
Θ
=1
V
JA
=10V
IN
P-P
Where:
T
T
= Maximum Junction Temperature
= Maximum Ambient Temperature
= Thermal Resistance of the Package
JMAX
5V
AMAX
Θ
JA
FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
P
= Maximum Power Dissipation in the Package.
DMAX
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
Short Circuit Current Limit
The EL5210 and EL5410 will limit the short circuit current to
±120mA if the output is directly shorted to the positive or the
negative supply. If an output is shorted indefinitely, the
power dissipation could easily increase such that the device
may be damaged. Maximum reliability is maintained if the
P
= Σi[V × I
+ (V + – V
i) × I
i]
LOAD
DMAX
S
SMAX
S
OUT
FN7185.2
May 6, 2005
11
EL5210, EL5410
when sourcing, and
Packages Mounted on a JEDEC JESD51-3 Low Effective
Thermal Conductivity Test Board
P
= Σi[V × I
+ (V
i – V -) × I
i]
LOAD
1200
DMAX
S
SMAX
OUT
S
MAX T =125°C
J
1000
800
600
400
200
0
when sinking.
Where:
SO14
=120°C/W
θ
JA
833mW
606mW
i = 1 to 2 for Dual and 1 to 4 for Quad
V = Total Supply Voltage
TSSOP14
=165°C/W
625mW
θ
JA
485mW
S
SO8
θ
=160°C/W
JA
I
= Maximum Supply Current Per Amplifier
SMAX
MSOP8
θ
=206°C/W
JA
V
i = Maximum Output Voltage of the Application
OUT
I
i = Load current
0
25
50
75 85
100
125
150
LOAD
Ambient Temperature (°C)
If we set the two P
can solve for R
LOAD
equations equal to each other, we
i to avoid device overheat. Figure 3 and
DMAX
FIGURE 4. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
Figure 4 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
Unus ed Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
simple matter to see if P
exceeds the device's power
DMAX
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figure 3 and Figure 4.
Driving Capacitive Loads
The EL5210 and EL5410 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the -3dB bandwidth of the device will decrease and the
peaking increase. The amplifiers drive 10pF loads in parallel
with 1kΩ with just 1.2dB of peaking, and 100pF with 6.5dB of
peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5Ω and 50Ω) can be
placed in series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing peaking
is to add a "snubber" circuit at the output. A snubber is a
shunt load consisting of a resistor in series with a capacitor.
Values of 150Ω and 10nF are typical. The advantage of a
snubber is that it does not draw any DC load current or
reduce the gain.
Packages Mounted on a JEDEC JESD51-7 High Effective
Thermal Conductivity Test Board
1200
1.136W
MAX T =125°C
J
1.0W
909mW
1000
800
600
400
200
0
833mW
SO14
=88°C/W
θ
SO8
JA
θ
=110°C/W
JA
TSSOP14
MSOP8
θ
=100°C/W
JA
θ
=115°C/W
JA
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Power Supply Bypas s ing and Printed Circuit
Board Layout
FIGURE 3. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
The EL5210 and EL5410 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V - pin is
S
connected to ground, a 0.1µF ceramic capacitor should be
placed from V + to pin to V - pin. A 4.7µF tantalum
S
S
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used.
FN7185.2
12
May 6, 2005
EL5210, EL5410
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7185.2
13
May 6, 2005
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